lib/main/STM32F1/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_dma.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f1xx_ll_dma.c
   4   * @author  MCD Application Team
   5   * @version V1.1.1
   6   * @date    12-May-2017
   7   * @brief   DMA LL module driver.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37 #if defined(USE_FULL_LL_DRIVER)
  38
  39 /* Includes ------------------------------------------------------------------*/
  40 #include "stm32f1xx_ll_dma.h"
  41 #include "stm32f1xx_ll_bus.h"
  42 #ifdef  USE_FULL_ASSERT
  43 #include "stm32_assert.h"
  44 #else
  45 #define assert_param(expr) ((void)0U)
  46 #endif
  47
  48 /** @addtogroup STM32F1xx_LL_Driver
  49   * @{
  50   */
  51
  52 #if defined (DMA1) || defined (DMA2)
  53
  54 /** @defgroup DMA_LL DMA
  55   * @{
  56   */
  57
  58 /* Private types -------------------------------------------------------------*/
  59 /* Private variables ---------------------------------------------------------*/
  60 /* Private constants ---------------------------------------------------------*/
  61 /* Private macros ------------------------------------------------------------*/
  62 /** @addtogroup DMA_LL_Private_Macros
  63   * @{
  64   */
  65 #define IS_LL_DMA_DIRECTION(__VALUE__)          (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
  66                                                  ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
  67                                                  ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
  68
  69 #define IS_LL_DMA_MODE(__VALUE__)               (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
  70                                                  ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
  71
  72 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
  73                                                  ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
  74
  75 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
  76                                                  ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
  77
  78 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \
  79                                                  ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \
  80                                                  ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
  81
  82 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \
  83                                                  ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
  84                                                  ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
  85
  86 #define IS_LL_DMA_NBDATA(__VALUE__)             ((__VALUE__)  <= 0x0000FFFFU)
  87
  88 #define IS_LL_DMA_PRIORITY(__VALUE__)           (((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
  89                                                  ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
  90                                                  ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \
  91                                                  ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
  92
  93 #if defined (DMA2)
  94 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
  95                                                             (((CHANNEL) == LL_DMA_CHANNEL_1) || \
  96                                                              ((CHANNEL) == LL_DMA_CHANNEL_2) || \
  97                                                              ((CHANNEL) == LL_DMA_CHANNEL_3) || \
  98                                                              ((CHANNEL) == LL_DMA_CHANNEL_4) || \
  99                                                              ((CHANNEL) == LL_DMA_CHANNEL_5) || \
 100                                                              ((CHANNEL) == LL_DMA_CHANNEL_6) || \
 101                                                              ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
 102                                                             (((INSTANCE) == DMA2) && \
 103                                                             (((CHANNEL) == LL_DMA_CHANNEL_1) || \
 104                                                              ((CHANNEL) == LL_DMA_CHANNEL_2) || \
 105                                                              ((CHANNEL) == LL_DMA_CHANNEL_3) || \
 106                                                              ((CHANNEL) == LL_DMA_CHANNEL_4) || \
 107                                                              ((CHANNEL) == LL_DMA_CHANNEL_5))))
 108 #else
 109 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
 110                                                             (((CHANNEL) == LL_DMA_CHANNEL_1) || \
 111                                                              ((CHANNEL) == LL_DMA_CHANNEL_2) || \
 112                                                              ((CHANNEL) == LL_DMA_CHANNEL_3) || \
 113                                                              ((CHANNEL) == LL_DMA_CHANNEL_4) || \
 114                                                              ((CHANNEL) == LL_DMA_CHANNEL_5) || \
 115                                                              ((CHANNEL) == LL_DMA_CHANNEL_6) || \
 116                                                              ((CHANNEL) == LL_DMA_CHANNEL_7))))
 117 #endif
 118 /**
 119   * @}
 120   */
 121
 122 /* Private function prototypes -----------------------------------------------*/
 123 /* Exported functions --------------------------------------------------------*/
 124 /** @addtogroup DMA_LL_Exported_Functions
 125   * @{
 126   */
 127
 128 /** @addtogroup DMA_LL_EF_Init
 129   * @{
 130   */
 131
 132 /**
 133   * @brief  De-initialize the DMA registers to their default reset values.
 134   * @param  DMAx DMAx Instance
 135   * @param  Channel This parameter can be one of the following values:
 136   *         @arg @ref LL_DMA_CHANNEL_1
 137   *         @arg @ref LL_DMA_CHANNEL_2
 138   *         @arg @ref LL_DMA_CHANNEL_3
 139   *         @arg @ref LL_DMA_CHANNEL_4
 140   *         @arg @ref LL_DMA_CHANNEL_5
 141   *         @arg @ref LL_DMA_CHANNEL_6
 142   *         @arg @ref LL_DMA_CHANNEL_7
 143   * @retval An ErrorStatus enumeration value:
 144   *          - SUCCESS: DMA registers are de-initialized
 145   *          - ERROR: DMA registers are not de-initialized
 146   */
 147 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
 148 {
 149   DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1;
 150   ErrorStatus status = SUCCESS;
 151
 152   /* Check the DMA Instance DMAx and Channel parameters*/
 153   assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
 154
 155   tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
 156
 157   /* Disable the selected DMAx_Channely */
 158   CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
 159
 160   /* Reset DMAx_Channely control register */
 161   LL_DMA_WriteReg(tmp, CCR, 0U);
 162
 163   /* Reset DMAx_Channely remaining bytes register */
 164   LL_DMA_WriteReg(tmp, CNDTR, 0U);
 165
 166   /* Reset DMAx_Channely peripheral address register */
 167   LL_DMA_WriteReg(tmp, CPAR, 0U);
 168
 169   /* Reset DMAx_Channely memory address register */
 170   LL_DMA_WriteReg(tmp, CMAR, 0U);
 171
 172   if (Channel == LL_DMA_CHANNEL_1)
 173   {
 174     /* Reset interrupt pending bits for DMAx Channel1 */
 175     LL_DMA_ClearFlag_GI1(DMAx);
 176   }
 177   else if (Channel == LL_DMA_CHANNEL_2)
 178   {
 179     /* Reset interrupt pending bits for DMAx Channel2 */
 180     LL_DMA_ClearFlag_GI2(DMAx);
 181   }
 182   else if (Channel == LL_DMA_CHANNEL_3)
 183   {
 184     /* Reset interrupt pending bits for DMAx Channel3 */
 185     LL_DMA_ClearFlag_GI3(DMAx);
 186   }
 187   else if (Channel == LL_DMA_CHANNEL_4)
 188   {
 189     /* Reset interrupt pending bits for DMAx Channel4 */
 190     LL_DMA_ClearFlag_GI4(DMAx);
 191   }
 192   else if (Channel == LL_DMA_CHANNEL_5)
 193   {
 194     /* Reset interrupt pending bits for DMAx Channel5 */
 195     LL_DMA_ClearFlag_GI5(DMAx);
 196   }
 197
 198   else if (Channel == LL_DMA_CHANNEL_6)
 199   {
 200     /* Reset interrupt pending bits for DMAx Channel6 */
 201     LL_DMA_ClearFlag_GI6(DMAx);
 202   }
 203   else if (Channel == LL_DMA_CHANNEL_7)
 204   {
 205     /* Reset interrupt pending bits for DMAx Channel7 */
 206     LL_DMA_ClearFlag_GI7(DMAx);
 207   }
 208   else
 209   {
 210     status = ERROR;
 211   }
 212
 213   return status;
 214 }
 215
 216 /**
 217   * @brief  Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
 218   * @note   To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
 219   *         @arg @ref __LL_DMA_GET_INSTANCE
 220   *         @arg @ref __LL_DMA_GET_CHANNEL
 221   * @param  DMAx DMAx Instance
 222   * @param  Channel This parameter can be one of the following values:
 223   *         @arg @ref LL_DMA_CHANNEL_1
 224   *         @arg @ref LL_DMA_CHANNEL_2
 225   *         @arg @ref LL_DMA_CHANNEL_3
 226   *         @arg @ref LL_DMA_CHANNEL_4
 227   *         @arg @ref LL_DMA_CHANNEL_5
 228   *         @arg @ref LL_DMA_CHANNEL_6
 229   *         @arg @ref LL_DMA_CHANNEL_7
 230   * @param  DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
 231   * @retval An ErrorStatus enumeration value:
 232   *          - SUCCESS: DMA registers are initialized
 233   *          - ERROR: Not applicable
 234   */
 235 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
 236 {
 237   /* Check the DMA Instance DMAx and Channel parameters*/
 238   assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
 239
 240   /* Check the DMA parameters from DMA_InitStruct */
 241   assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
 242   assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
 243   assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
 244   assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
 245   assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
 246   assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
 247   assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
 248   assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
 249
 250   /*---------------------------- DMAx CCR Configuration ------------------------
 251    * Configure DMAx_Channely: data transfer direction, data transfer mode,
 252    *                          peripheral and memory increment mode,
 253    *                          data size alignment and  priority level with parameters :
 254    * - Direction:      DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
 255    * - Mode:           DMA_CCR_CIRC bit
 256    * - PeriphOrM2MSrcIncMode:  DMA_CCR_PINC bit
 257    * - MemoryOrM2MDstIncMode:  DMA_CCR_MINC bit
 258    * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
 259    * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
 260    * - Priority:               DMA_CCR_PL[1:0] bits
 261    */
 262   LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \
 263                         DMA_InitStruct->Mode                   | \
 264                         DMA_InitStruct->PeriphOrM2MSrcIncMode  | \
 265                         DMA_InitStruct->MemoryOrM2MDstIncMode  | \
 266                         DMA_InitStruct->PeriphOrM2MSrcDataSize | \
 267                         DMA_InitStruct->MemoryOrM2MDstDataSize | \
 268                         DMA_InitStruct->Priority);
 269
 270   /*-------------------------- DMAx CMAR Configuration -------------------------
 271    * Configure the memory or destination base address with parameter :
 272    * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
 273    */
 274   LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
 275
 276   /*-------------------------- DMAx CPAR Configuration -------------------------
 277    * Configure the peripheral or source base address with parameter :
 278    * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
 279    */
 280   LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
 281
 282   /*--------------------------- DMAx CNDTR Configuration -----------------------
 283    * Configure the peripheral base address with parameter :
 284    * - NbData: DMA_CNDTR_NDT[15:0] bits
 285    */
 286   LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
 287
 288   return SUCCESS;
 289 }
 290
 291 /**
 292   * @brief  Set each @ref LL_DMA_InitTypeDef field to default value.
 293   * @param  DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
 294   * @retval None
 295   */
 296 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
 297 {
 298   /* Set DMA_InitStruct fields to default values */
 299   DMA_InitStruct->PeriphOrM2MSrcAddress  = 0x00000000U;
 300   DMA_InitStruct->MemoryOrM2MDstAddress  = 0x00000000U;
 301   DMA_InitStruct->Direction              = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
 302   DMA_InitStruct->Mode                   = LL_DMA_MODE_NORMAL;
 303   DMA_InitStruct->PeriphOrM2MSrcIncMode  = LL_DMA_PERIPH_NOINCREMENT;
 304   DMA_InitStruct->MemoryOrM2MDstIncMode  = LL_DMA_MEMORY_NOINCREMENT;
 305   DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
 306   DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
 307   DMA_InitStruct->NbData                 = 0x00000000U;
 308   DMA_InitStruct->Priority               = LL_DMA_PRIORITY_LOW;
 309 }
 310
 311 /**
 312   * @}
 313   */
 314
 315 /**
 316   * @}
 317   */
 318
 319 /**
 320   * @}
 321   */
 322
 323 #endif /* DMA1 || DMA2 */
 324
 325 /**
 326   * @}
 327   */
 328
 329 #endif /* USE_FULL_LL_DRIVER */
 330
 331 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/