lib/main/STM32F1/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f1xx_ll_fsmc.c
   4   * @author  MCD Application Team
   5   * @version V1.1.1
   6   * @date    12-May-2017
   7   * @brief   FSMC Low Layer HAL module driver.
   8   *
   9   *          This file provides firmware functions to manage the following
  10   *          functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories:
  11   *           + Initialization/de-initialization functions
  12   *           + Peripheral Control functions
  13   *           + Peripheral State functions
  14   *
  15   @verbatim
  16   =============================================================================
  17                         ##### FSMC peripheral features #####
  18   =============================================================================
  19     [..] The Flexible static memory controller (FSMC) includes following memory controllers:
  20          (+) The NOR/PSRAM memory controller
  21          (+) The PC Card memory controller
  22          (+) The NAND memory controller
  23              (PC Card and NAND controllers available only on STM32F101xE, STM32F103xE, STM32F101xG and STM32F103xG)
  24
  25     [..] The FSMC functional block makes the interface with synchronous and asynchronous static
  26          memories and 16-bit PC memory cards. Its main purposes are:
  27          (+) to translate AHB transactions into the appropriate external device protocol.
  28          (+) to meet the access time requirements of the external memory devices.
  29
  30     [..] All external memories share the addresses, data and control signals with the controller.
  31          Each external device is accessed by means of a unique Chip Select. The FSMC performs
  32          only one access at a time to an external device.
  33          The main features of the FSMC controller are the following:
  34           (+) Interface with static-memory mapped devices including:
  35              (++) Static random access memory (SRAM).
  36              (++) NOR Flash memory.
  37              (++) PSRAM (4 memory banks).
  38              (++) 16-bit PC Card compatible devices.
  39              (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
  40                   data.
  41           (+) Independent Chip Select control for each memory bank.
  42           (+) Independent configuration for each memory bank.
  43
  44   @endverbatim
  45   ******************************************************************************
  46   * @attention
  47   *
  48   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  49   *
  50   * Redistribution and use in source and binary forms, with or without modification,
  51   * are permitted provided that the following conditions are met:
  52   *   1. Redistributions of source code must retain the above copyright notice,
  53   *      this list of conditions and the following disclaimer.
  54   *   2. Redistributions in binary form must reproduce the above copyright notice,
  55   *      this list of conditions and the following disclaimer in the documentation
  56   *      and/or other materials provided with the distribution.
  57   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  58   *      may be used to endorse or promote products derived from this software
  59   *      without specific prior written permission.
  60   *
  61   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  62   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  63   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  64   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  65   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  66   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  67   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  68   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  69   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  70   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  71   *
  72   ******************************************************************************
  73   */
  74
  75 /* Includes ------------------------------------------------------------------*/
  76 #include "stm32f1xx_hal.h"
  77
  78 /** @addtogroup STM32F1xx_HAL_Driver
  79   * @{
  80   */
  81
  82 #if defined(FSMC_BANK1)
  83
  84 #if defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED)
  85
  86 /** @defgroup FSMC_LL FSMC Low Layer
  87   * @brief FSMC driver modules
  88   * @{
  89   */
  90
  91 /* Private typedef -----------------------------------------------------------*/
  92 /* Private define ------------------------------------------------------------*/
  93 /* Private macro -------------------------------------------------------------*/
  94 /* Private variables ---------------------------------------------------------*/
  95 /* Private function prototypes -----------------------------------------------*/
  96 /* Exported functions --------------------------------------------------------*/
  97
  98 /** @defgroup FSMC_LL_Exported_Functions FSMC Low Layer Exported Functions
  99   * @{
 100   */
 101
 102 /** @defgroup FSMC_NORSRAM FSMC NORSRAM Controller functions
 103   * @brief    NORSRAM Controller functions
 104   *
 105   @verbatim
 106   ==============================================================================
 107                    ##### How to use NORSRAM device driver #####
 108   ==============================================================================
 109
 110   [..]
 111     This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
 112     to run the NORSRAM external devices.
 113
 114     (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
 115     (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
 116     (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
 117     (+) FSMC NORSRAM bank extended timing configuration using the function
 118         FSMC_NORSRAM_Extended_Timing_Init()
 119     (+) FSMC NORSRAM bank enable/disable write operation using the functions
 120         FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
 121
 122 @endverbatim
 123   * @{
 124   */
 125
 126 /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group1
 127   * @brief    Initialization and Configuration functions
 128   *
 129   @verbatim
 130   ==============================================================================
 131               ##### Initialization and de_initialization functions #####
 132   ==============================================================================
 133   [..]
 134     This section provides functions allowing to:
 135     (+) Initialize and configure the FSMC NORSRAM interface
 136     (+) De-initialize the FSMC NORSRAM interface
 137     (+) Configure the FSMC clock and associated GPIOs
 138
 139 @endverbatim
 140   * @{
 141   */
 142
 143 /**
 144   * @brief  Initialize the FSMC_NORSRAM device according to the specified
 145   *         control parameters in the FSMC_NORSRAM_InitTypeDef
 146   * @param  Device: Pointer to NORSRAM device instance
 147   * @param  Init: Pointer to NORSRAM Initialization structure
 148   * @retval HAL status
 149   */
 150 HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init)
 151 {
 152   /* Check the parameters */
 153   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
 154   assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
 155   assert_param(IS_FSMC_MUX(Init->DataAddressMux));
 156   assert_param(IS_FSMC_MEMORY(Init->MemoryType));
 157   assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
 158   assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
 159   assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
 160   assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
 161   assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
 162   assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
 163   assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
 164   assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
 165   assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
 166   assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
 167
 168   /* Disable NORSRAM Device */
 169   __FSMC_NORSRAM_DISABLE(Device, Init->NSBank);
 170
 171   /* Set NORSRAM device control parameters */
 172   if (Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
 173   {
 174     MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FSMC_NORSRAM_FLASH_ACCESS_ENABLE
 175                | Init->DataAddressMux
 176                | Init->MemoryType
 177                | Init->MemoryDataWidth
 178                | Init->BurstAccessMode
 179                | Init->WaitSignalPolarity
 180                | Init->WrapMode
 181                | Init->WaitSignalActive
 182                | Init->WriteOperation
 183                | Init->WaitSignal
 184                | Init->ExtendedMode
 185                | Init->AsynchronousWait
 186                | Init->WriteBurst
 187                                                                      )
 188               );
 189   }
 190   else
 191   {
 192     MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FSMC_NORSRAM_FLASH_ACCESS_DISABLE
 193                | Init->DataAddressMux
 194                | Init->MemoryType
 195                | Init->MemoryDataWidth
 196                | Init->BurstAccessMode
 197                | Init->WaitSignalPolarity
 198                | Init->WrapMode
 199                | Init->WaitSignalActive
 200                | Init->WriteOperation
 201                | Init->WaitSignal
 202                | Init->ExtendedMode
 203                | Init->AsynchronousWait
 204                | Init->WriteBurst
 205                                                                      )
 206               );
 207   }
 208
 209   return HAL_OK;
 210 }
 211
 212 /**
 213   * @brief  DeInitialize the FSMC_NORSRAM peripheral
 214   * @param  Device: Pointer to NORSRAM device instance
 215   * @param  ExDevice: Pointer to NORSRAM extended mode device instance
 216   * @param  Bank: NORSRAM bank number
 217   * @retval HAL status
 218   */
 219 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
 220 {
 221   /* Check the parameters */
 222   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
 223   assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
 224   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
 225
 226   /* Disable the FSMC_NORSRAM device */
 227   __FSMC_NORSRAM_DISABLE(Device, Bank);
 228
 229   /* De-initialize the FSMC_NORSRAM device */
 230   /* FSMC_NORSRAM_BANK1 */
 231   if(Bank == FSMC_NORSRAM_BANK1)
 232   {
 233     Device->BTCR[Bank] = 0x000030DBU;
 234   }
 235   /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
 236   else
 237   {
 238     Device->BTCR[Bank] = 0x000030D2U;
 239   }
 240
 241   Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
 242   ExDevice->BWTR[Bank]    = 0x0FFFFFFFU;
 243
 244   return HAL_OK;
 245 }
 246
 247
 248 /**
 249   * @brief  Initialize the FSMC_NORSRAM Timing according to the specified
 250   *         parameters in the FSMC_NORSRAM_TimingTypeDef
 251   * @param  Device: Pointer to NORSRAM device instance
 252   * @param  Timing: Pointer to NORSRAM Timing structure
 253   * @param  Bank: NORSRAM bank number
 254   * @retval HAL status
 255   */
 256 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
 257 {
 258   /* Check the parameters */
 259   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
 260   assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
 261   assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
 262   assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
 263   assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
 264   assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
 265   assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
 266   assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
 267   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
 268
 269   /* Set FSMC_NORSRAM device timing parameters */
 270   MODIFY_REG(Device->BTCR[Bank + 1U],                                                        \
 271              BTR_CLEAR_MASK,                                                                \
 272              (uint32_t)(Timing->AddressSetupTime                                          | \
 273                         ((Timing->AddressHoldTime)        << FSMC_BTRx_ADDHLD_Pos)        | \
 274                         ((Timing->DataSetupTime)          << FSMC_BTRx_DATAST_Pos)        | \
 275                         ((Timing->BusTurnAroundDuration)  << FSMC_BTRx_BUSTURN_Pos)       | \
 276                         (((Timing->CLKDivision) - 1U)     << FSMC_BTRx_CLKDIV_Pos)        | \
 277                         (((Timing->DataLatency) - 2U)     << FSMC_BTRx_DATLAT_Pos)        | \
 278                         (Timing->AccessMode)));
 279
 280   return HAL_OK;
 281 }
 282
 283 /**
 284   * @brief  Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
 285   *         parameters in the FSMC_NORSRAM_TimingTypeDef
 286   * @param  Device: Pointer to NORSRAM device instance
 287   * @param  Timing: Pointer to NORSRAM Timing structure
 288   * @param  Bank: NORSRAM bank number
 289   * @param  ExtendedMode FSMC Extended Mode
 290   *          This parameter can be one of the following values:
 291   *            @arg FSMC_EXTENDED_MODE_DISABLE
 292   *            @arg FSMC_EXTENDED_MODE_ENABLE
 293   * @retval HAL status
 294   */
 295 HAL_StatusTypeDef  FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
 296 {
 297   /* Check the parameters */
 298   assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
 299
 300   /* Set NORSRAM device timing register for write configuration, if extended mode is used */
 301   if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
 302   {
 303     /* Check the parameters */
 304     assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));
 305     assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
 306     assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
 307     assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
 308 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
 309     assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
 310 #else
 311     assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
 312     assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
 313 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
 314     assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
 315     assert_param(IS_FSMC_NORSRAM_BANK(Bank));
 316
 317     /* Set NORSRAM device timing register for write configuration, if extended mode is used */
 318 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
 319     MODIFY_REG(Device->BWTR[Bank],                                                      \
 320                BWTR_CLEAR_MASK,                                                         \
 321                (uint32_t)(Timing->AddressSetupTime                                    | \
 322                           ((Timing->AddressHoldTime)        << FSMC_BWTRx_ADDHLD_Pos) | \
 323                           ((Timing->DataSetupTime)          << FSMC_BWTRx_DATAST_Pos) | \
 324                           Timing->AccessMode                                          | \
 325                           ((Timing->BusTurnAroundDuration)  << FSMC_BWTRx_BUSTURN_Pos)));
 326 #else
 327     MODIFY_REG(Device->BWTR[Bank],                                                      \
 328                BWTR_CLEAR_MASK,                                                         \
 329                (uint32_t)(Timing->AddressSetupTime                                    | \
 330                           ((Timing->AddressHoldTime)  << FSMC_BWTRx_ADDHLD_Pos)       | \
 331                           ((Timing->DataSetupTime)    << FSMC_BWTRx_DATAST_Pos)       | \
 332                           Timing->AccessMode                                          | \
 333                           (((Timing->CLKDivision) - 1U)  << FSMC_BTRx_CLKDIV_Pos)     | \
 334                           (((Timing->DataLatency) - 2U)  << FSMC_BWTRx_DATLAT_Pos)));
 335 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
 336   }
 337   else
 338   {
 339     Device->BWTR[Bank] = 0x0FFFFFFFU;
 340   }
 341
 342   return HAL_OK;
 343 }
 344 /**
 345   * @}
 346   */
 347
 348 /** @defgroup FSMC_NORSRAM_Group2 Control functions
 349   *  @brief   management functions
 350   *
 351 @verbatim
 352   ==============================================================================
 353                       ##### FSMC_NORSRAM Control functions #####
 354   ==============================================================================
 355   [..]
 356     This subsection provides a set of functions allowing to control dynamically
 357     the FSMC NORSRAM interface.
 358
 359 @endverbatim
 360   * @{
 361   */
 362
 363 /**
 364   * @brief  Enables dynamically FSMC_NORSRAM write operation.
 365   * @param  Device: Pointer to NORSRAM device instance
 366   * @param  Bank: NORSRAM bank number
 367   * @retval HAL status
 368   */
 369 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
 370 {
 371   /* Check the parameters */
 372   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
 373   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
 374
 375   /* Enable write operation */
 376   SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
 377
 378   return HAL_OK;
 379 }
 380
 381 /**
 382   * @brief  Disables dynamically FSMC_NORSRAM write operation.
 383   * @param  Device: Pointer to NORSRAM device instance
 384   * @param  Bank: NORSRAM bank number
 385   * @retval HAL status
 386   */
 387 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
 388 {
 389   /* Check the parameters */
 390   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
 391   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
 392
 393   /* Disable write operation */
 394   CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
 395
 396   return HAL_OK;
 397 }
 398 /**
 399   * @}
 400   */
 401
 402 /**
 403   * @}
 404   */
 405
 406 #if (defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
 407 /** @defgroup FSMC_NAND FSMC NAND Controller functions
 408   * @brief    NAND Controller functions
 409   *
 410   @verbatim
 411   ==============================================================================
 412                     ##### How to use NAND device driver #####
 413   ==============================================================================
 414   [..]
 415     This driver contains a set of APIs to interface with the FSMC NAND banks in order
 416     to run the NAND external devices.
 417
 418     (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit()
 419     (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init()
 420     (+) FSMC NAND bank common space timing configuration using the function
 421         FSMC_NAND_CommonSpace_Timing_Init()
 422     (+) FSMC NAND bank attribute space timing configuration using the function
 423         FSMC_NAND_AttributeSpace_Timing_Init()
 424     (+) FSMC NAND bank enable/disable ECC correction feature using the functions
 425         FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable()
 426     (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()
 427
 428 @endverbatim
 429   * @{
 430   */
 431
 432 /** @defgroup FSMC_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
 433   *  @brief    Initialization and Configuration functions
 434   *
 435 @verbatim
 436   ==============================================================================
 437               ##### Initialization and de_initialization functions #####
 438   ==============================================================================
 439   [..]
 440     This section provides functions allowing to:
 441     (+) Initialize and configure the FSMC NAND interface
 442     (+) De-initialize the FSMC NAND interface
 443     (+) Configure the FSMC clock and associated GPIOs
 444
 445 @endverbatim
 446   * @{
 447   */
 448
 449 /**
 450   * @brief  Initializes the FSMC_NAND device according to the specified
 451   *         control parameters in the FSMC_NAND_HandleTypeDef
 452   * @param  Device: Pointer to NAND device instance
 453   * @param  Init: Pointer to NAND Initialization structure
 454   * @retval HAL status
 455   */
 456 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
 457 {
 458   /* Check the parameters */
 459   assert_param(IS_FSMC_NAND_DEVICE(Device));
 460   assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
 461   assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
 462   assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
 463   assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
 464   assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
 465   assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
 466   assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
 467
 468   /* Set NAND device control parameters */
 469   if (Init->NandBank == FSMC_NAND_BANK2)
 470   {
 471     /* NAND bank 2 registers configuration */
 472     MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature                             |
 473                                               FSMC_PCR_MEMORY_TYPE_NAND                     |
 474                                               Init->MemoryDataWidth                         |
 475                                               Init->EccComputation                          |
 476                                               Init->ECCPageSize                             |
 477                                               ((Init->TCLRSetupTime) << FSMC_PCRx_TCLR_Pos) |
 478                                               ((Init->TARSetupTime)  << FSMC_PCRx_TAR_Pos)));
 479   }
 480   else
 481   {
 482     /* NAND bank 3 registers configuration */
 483     MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature                             |
 484                                               FSMC_PCR_MEMORY_TYPE_NAND                     |
 485                                               Init->MemoryDataWidth                         |
 486                                               Init->EccComputation                          |
 487                                               Init->ECCPageSize                             |
 488                                               ((Init->TCLRSetupTime) << FSMC_PCRx_TCLR_Pos) |
 489                                               ((Init->TARSetupTime)  << FSMC_PCRx_TAR_Pos)));
 490   }
 491
 492   return HAL_OK;
 493 }
 494
 495 /**
 496   * @brief  Initializes the FSMC_NAND Common space Timing according to the specified
 497   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
 498   * @param  Device: Pointer to NAND device instance
 499   * @param  Timing: Pointer to NAND timing structure
 500   * @param  Bank: NAND bank number
 501   * @retval HAL status
 502   */
 503 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
 504 {
 505   /* Check the parameters */
 506   assert_param(IS_FSMC_NAND_DEVICE(Device));
 507   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
 508   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
 509   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
 510   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
 511   assert_param(IS_FSMC_NAND_BANK(Bank));
 512
 513   /* Set FMC_NAND device timing parameters */
 514   if(Bank == FSMC_NAND_BANK2)
 515   {
 516     /* NAND bank 2 registers configuration */
 517     MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime                                         | \
 518                                                 ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos)      | \
 519                                                 ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos)      | \
 520                                                 ((Timing->HiZSetupTime)  << FSMC_PMEMx_MEMHIZx_Pos)));
 521   }
 522   else
 523   {
 524     /* NAND bank 3 registers configuration */
 525     MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime                                         | \
 526                                                 ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos)      | \
 527                                                 ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos)      | \
 528                                                 ((Timing->HiZSetupTime)  << FSMC_PMEMx_MEMHIZx_Pos)));
 529   }
 530
 531   return HAL_OK;
 532 }
 533
 534 /**
 535   * @brief  Initializes the FSMC_NAND Attribute space Timing according to the specified
 536   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
 537   * @param  Device: Pointer to NAND device instance
 538   * @param  Timing: Pointer to NAND timing structure
 539   * @param  Bank: NAND bank number
 540   * @retval HAL status
 541   */
 542 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
 543 {
 544   /* Check the parameters */
 545   assert_param(IS_FSMC_NAND_DEVICE(Device));
 546   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
 547   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
 548   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
 549   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
 550   assert_param(IS_FSMC_NAND_BANK(Bank));
 551
 552   /* Set FMC_NAND device timing parameters */
 553   if(Bank == FSMC_NAND_BANK2)
 554   {
 555     /* NAND bank 2 registers configuration */
 556     MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime                                         | \
 557                                                 ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos)      | \
 558                                                 ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos)      | \
 559                                                 ((Timing->HiZSetupTime)  << FSMC_PATTx_ATTHIZx_Pos)));
 560   }
 561   else
 562   {
 563     /* NAND bank 3 registers configuration */
 564     MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime                                         | \
 565                                                 ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos)      | \
 566                                                 ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos)      | \
 567                                                 ((Timing->HiZSetupTime)  << FSMC_PATTx_ATTHIZx_Pos)));
 568   }
 569
 570   return HAL_OK;
 571 }
 572
 573
 574 /**
 575   * @brief  DeInitializes the FSMC_NAND device
 576   * @param  Device: Pointer to NAND device instance
 577   * @param  Bank: NAND bank number
 578   * @retval HAL status
 579   */
 580 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
 581 {
 582   /* Check the parameters */
 583   assert_param(IS_FSMC_NAND_DEVICE(Device));
 584   assert_param(IS_FSMC_NAND_BANK(Bank));
 585
 586   /* Disable the NAND Bank */
 587   __FSMC_NAND_DISABLE(Device, Bank);
 588
 589   /* De-initialize the NAND Bank */
 590   if(Bank == FSMC_NAND_BANK2)
 591   {
 592     /* Set the FSMC_NAND_BANK2 registers to their reset values */
 593     WRITE_REG(Device->PCR2,  0x00000018U);
 594     WRITE_REG(Device->SR2,   0x00000040U);
 595     WRITE_REG(Device->PMEM2, 0xFCFCFCFCU);
 596     WRITE_REG(Device->PATT2, 0xFCFCFCFCU);
 597   }
 598   /* FSMC_Bank3_NAND */
 599   else
 600   {
 601     /* Set the FSMC_NAND_BANK3 registers to their reset values */
 602     WRITE_REG(Device->PCR3,  0x00000018U);
 603     WRITE_REG(Device->SR3,   0x00000040U);
 604     WRITE_REG(Device->PMEM3, 0xFCFCFCFCU);
 605     WRITE_REG(Device->PATT3, 0xFCFCFCFCU);
 606   }
 607
 608   return HAL_OK;
 609 }
 610
 611 /**
 612   * @}
 613   */
 614
 615
 616 /** @defgroup FSMC_NAND_Exported_Functions_Group2 Peripheral Control functions
 617   *  @brief   management functions
 618   *
 619 @verbatim
 620   ==============================================================================
 621                        ##### FSMC_NAND Control functions #####
 622   ==============================================================================
 623   [..]
 624     This subsection provides a set of functions allowing to control dynamically
 625     the FSMC NAND interface.
 626
 627 @endverbatim
 628   * @{
 629   */
 630
 631 /**
 632   * @brief  Enables dynamically FSMC_NAND ECC feature.
 633   * @param  Device: Pointer to NAND device instance
 634   * @param  Bank: NAND bank number
 635   * @retval HAL status
 636   */
 637 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
 638 {
 639   /* Check the parameters */
 640   assert_param(IS_FSMC_NAND_DEVICE(Device));
 641   assert_param(IS_FSMC_NAND_BANK(Bank));
 642
 643   /* Enable ECC feature */
 644   if(Bank == FSMC_NAND_BANK2)
 645   {
 646     SET_BIT(Device->PCR2, FSMC_PCRx_ECCEN);
 647   }
 648   else
 649   {
 650     SET_BIT(Device->PCR3, FSMC_PCRx_ECCEN);
 651   }
 652
 653   return HAL_OK;
 654 }
 655
 656 /**
 657   * @brief  Disables dynamically FSMC_NAND ECC feature.
 658   * @param  Device: Pointer to NAND device instance
 659   * @param  Bank: NAND bank number
 660   * @retval HAL status
 661   */
 662 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
 663 {
 664   /* Check the parameters */
 665   assert_param(IS_FSMC_NAND_DEVICE(Device));
 666   assert_param(IS_FSMC_NAND_BANK(Bank));
 667
 668   /* Disable ECC feature */
 669   if(Bank == FSMC_NAND_BANK2)
 670   {
 671     CLEAR_BIT(Device->PCR2, FSMC_PCRx_ECCEN);
 672   }
 673   else
 674   {
 675     CLEAR_BIT(Device->PCR3, FSMC_PCRx_ECCEN);
 676   }
 677
 678   return HAL_OK;
 679 }
 680
 681 /**
 682   * @brief  Disables dynamically FSMC_NAND ECC feature.
 683   * @param  Device: Pointer to NAND device instance
 684   * @param  ECCval: Pointer to ECC value
 685   * @param  Bank: NAND bank number
 686   * @param  Timeout: Timeout wait value
 687   * @retval HAL status
 688   */
 689 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
 690 {
 691   uint32_t tickstart = 0U;
 692
 693   /* Check the parameters */
 694   assert_param(IS_FSMC_NAND_DEVICE(Device));
 695   assert_param(IS_FSMC_NAND_BANK(Bank));
 696
 697   /* Get tick */
 698   tickstart = HAL_GetTick();
 699
 700   /* Wait until FIFO is empty */
 701   while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
 702   {
 703     /* Check for the Timeout */
 704     if(Timeout != HAL_MAX_DELAY)
 705     {
 706       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
 707       {
 708         return HAL_TIMEOUT;
 709       }
 710     }
 711   }
 712
 713   if(Bank == FSMC_NAND_BANK2)
 714   {
 715     /* Get the ECCR2 register value */
 716     *ECCval = (uint32_t)Device->ECCR2;
 717   }
 718   else
 719   {
 720     /* Get the ECCR3 register value */
 721     *ECCval = (uint32_t)Device->ECCR3;
 722   }
 723
 724   return HAL_OK;
 725 }
 726
 727 /**
 728   * @}
 729   */
 730
 731 /**
 732   * @}
 733   */
 734
 735 /** @defgroup FSMC_PCCARD FSMC PCCARD Controller functions
 736   * @brief    PCCARD Controller functions
 737   *
 738   @verbatim
 739   ==============================================================================
 740                     ##### How to use PCCARD device driver #####
 741   ==============================================================================
 742   [..]
 743     This driver contains a set of APIs to interface with the FSMC PCCARD bank in order
 744     to run the PCCARD/compact flash external devices.
 745
 746     (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit()
 747     (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init()
 748     (+) FSMC PCCARD bank common space timing configuration using the function
 749         FSMC_PCCARD_CommonSpace_Timing_Init()
 750     (+) FSMC PCCARD bank attribute space timing configuration using the function
 751         FSMC_PCCARD_AttributeSpace_Timing_Init()
 752     (+) FSMC PCCARD bank IO space timing configuration using the function
 753         FSMC_PCCARD_IOSpace_Timing_Init()
 754
 755 @endverbatim
 756   * @{
 757   */
 758
 759 /** @defgroup FSMC_PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
 760   *  @brief    Initialization and Configuration functions
 761   *
 762 @verbatim
 763   ==============================================================================
 764               ##### Initialization and de_initialization functions #####
 765   ==============================================================================
 766   [..]
 767     This section provides functions allowing to:
 768     (+) Initialize and configure the FSMC PCCARD interface
 769     (+) De-initialize the FSMC PCCARD interface
 770     (+) Configure the FSMC clock and associated GPIOs
 771
 772 @endverbatim
 773   * @{
 774   */
 775
 776 /**
 777   * @brief  Initializes the FSMC_PCCARD device according to the specified
 778   *         control parameters in the FSMC_PCCARD_HandleTypeDef
 779   * @param  Device: Pointer to PCCARD device instance
 780   * @param  Init: Pointer to PCCARD Initialization structure
 781   * @retval HAL status
 782   */
 783 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
 784 {
 785   /* Check the parameters */
 786   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
 787   assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
 788   assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
 789   assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
 790
 791   /* Set FSMC_PCCARD device control parameters */
 792   MODIFY_REG(Device->PCR4,
 793              (FSMC_PCRx_PTYP | FSMC_PCRx_PWAITEN |  FSMC_PCRx_PWID  |
 794               FSMC_PCRx_TCLR | FSMC_PCRx_TAR),
 795              (FSMC_PCR_MEMORY_TYPE_PCCARD                           |
 796               Init->Waitfeature                                     |
 797               FSMC_NAND_PCC_MEM_BUS_WIDTH_16                        |
 798               (Init->TCLRSetupTime << FSMC_PCRx_TCLR_Pos)           |
 799               (Init->TARSetupTime << FSMC_PCRx_TAR_Pos)));
 800
 801   return HAL_OK;
 802
 803 }
 804
 805 /**
 806   * @brief  Initializes the FSMC_PCCARD Common space Timing according to the specified
 807   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
 808   * @param  Device: Pointer to PCCARD device instance
 809   * @param  Timing: Pointer to PCCARD timing structure
 810   * @retval HAL status
 811   */
 812 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
 813 {
 814   /* Check the parameters */
 815   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
 816   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
 817   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
 818   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
 819   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
 820
 821   /* Set PCCARD timing parameters */
 822   MODIFY_REG(Device->PMEM4, PMEM_CLEAR_MASK,
 823              (Timing->SetupTime                                     |
 824               ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos)  |
 825               ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos)  |
 826               ((Timing->HiZSetupTime) << FSMC_PMEMx_MEMHIZx_Pos)));
 827
 828   return HAL_OK;
 829 }
 830
 831 /**
 832   * @brief  Initializes the FSMC_PCCARD Attribute space Timing according to the specified
 833   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
 834   * @param  Device: Pointer to PCCARD device instance
 835   * @param  Timing: Pointer to PCCARD timing structure
 836   * @retval HAL status
 837   */
 838 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
 839 {
 840   /* Check the parameters */
 841   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
 842   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
 843   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
 844   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
 845   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
 846
 847   /* Set PCCARD timing parameters */
 848   MODIFY_REG(Device->PATT4, PATT_CLEAR_MASK,                          \
 849              (Timing->SetupTime                                     | \
 850               ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos)  | \
 851               ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos)  | \
 852               ((Timing->HiZSetupTime)  << FSMC_PATTx_ATTHIZx_Pos)));
 853
 854   return HAL_OK;
 855 }
 856
 857 /**
 858   * @brief  Initializes the FSMC_PCCARD IO space Timing according to the specified
 859   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
 860   * @param  Device: Pointer to PCCARD device instance
 861   * @param  Timing: Pointer to PCCARD timing structure
 862   * @retval HAL status
 863   */
 864 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
 865 {
 866   /* Check the parameters */
 867   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
 868   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
 869   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
 870   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
 871   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
 872
 873   /* Set FSMC_PCCARD device timing parameters */
 874   MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK,                        \
 875              (Timing->SetupTime                                  | \
 876               (Timing->WaitSetupTime   << FSMC_PIO4_IOWAIT4_Pos) | \
 877               (Timing->HoldSetupTime   << FSMC_PIO4_IOHOLD4_Pos) | \
 878               (Timing->HiZSetupTime    << FSMC_PIO4_IOHIZ4_Pos)));
 879
 880   return HAL_OK;
 881 }
 882
 883 /**
 884   * @brief  DeInitializes the FSMC_PCCARD device
 885   * @param  Device: Pointer to PCCARD device instance
 886   * @retval HAL status
 887   */
 888 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
 889 {
 890   /* Check the parameters */
 891   assert_param(IS_FSMC_PCCARD_DEVICE(Device));
 892
 893   /* Disable the FSMC_PCCARD device */
 894   __FSMC_PCCARD_DISABLE(Device);
 895
 896   /* De-initialize the FSMC_PCCARD device */
 897   WRITE_REG(Device->PCR4,  0x00000018U);
 898   WRITE_REG(Device->SR4,   0x00000040U);
 899   WRITE_REG(Device->PMEM4, 0xFCFCFCFCU);
 900   WRITE_REG(Device->PATT4, 0xFCFCFCFCU);
 901   WRITE_REG(Device->PIO4,  0xFCFCFCFCU);
 902
 903   return HAL_OK;
 904 }
 905
 906 /**
 907   * @}
 908   */
 909
 910 /**
 911   * @}
 912   */
 913 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
 914
 915 /**
 916   * @}
 917   */
 918
 919 /**
 920   * @}
 921   */
 922
 923 #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED */
 924
 925 #endif /* FSMC_BANK1 */
 926
 927 /**
 928   * @}
 929   */
 930
 931 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/