lib/main/STM32F1/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_tim.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f1xx_ll_tim.c
   4   * @author  MCD Application Team
   5   * @version V1.1.1
   6   * @date    12-May-2017
   7   * @brief   TIM LL module driver.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37 #if defined(USE_FULL_LL_DRIVER)
  38
  39 /* Includes ------------------------------------------------------------------*/
  40 #include "stm32f1xx_ll_tim.h"
  41 #include "stm32f1xx_ll_bus.h"
  42
  43 #ifdef  USE_FULL_ASSERT
  44 #include "stm32_assert.h"
  45 #else
  46 #define assert_param(expr) ((void)0U)
  47 #endif
  48
  49 /** @addtogroup STM32F1xx_LL_Driver
  50   * @{
  51   */
  52
  53 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17)
  54
  55 /** @addtogroup TIM_LL
  56   * @{
  57   */
  58
  59 /* Private types -------------------------------------------------------------*/
  60 /* Private variables ---------------------------------------------------------*/
  61 /* Private constants ---------------------------------------------------------*/
  62 /* Private macros ------------------------------------------------------------*/
  63 /** @addtogroup TIM_LL_Private_Macros
  64   * @{
  65   */
  66 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
  67                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
  68                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
  69                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
  70                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
  71
  72 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
  73                                          || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
  74                                          || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
  75
  76 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
  77                                   || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
  78                                   || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
  79                                   || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
  80                                   || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
  81                                   || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
  82                                   || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
  83                                   || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
  84
  85 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
  86                                    || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
  87
  88 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
  89                                       || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
  90
  91 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
  92                                        || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
  93
  94 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
  95                                        || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
  96                                        || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
  97
  98 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
  99                                  || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
 100                                  || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
 101                                  || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
 102
 103 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
 104                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
 105                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
 106                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
 107                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
 108                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
 109                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
 110                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
 111                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
 112                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
 113                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
 114                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
 115                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
 116                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
 117                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
 118                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
 119
 120 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
 121                                        || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
 122
 123 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
 124                                        || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
 125                                        || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
 126
 127 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
 128                                                || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
 129
 130 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
 131                                      || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
 132
 133 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
 134                                       || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
 135
 136 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
 137                                       || ((__VALUE__) == LL_TIM_LOCKLEVEL_1)   \
 138                                       || ((__VALUE__) == LL_TIM_LOCKLEVEL_2)   \
 139                                       || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
 140
 141 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
 142                                        || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
 143
 144 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
 145                                           || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
 146
 147 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
 148                                                   || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
 149 /**
 150   * @}
 151   */
 152
 153
 154 /* Private function prototypes -----------------------------------------------*/
 155 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
 156   * @{
 157   */
 158 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 159 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 160 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 161 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 162 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
 163 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
 164 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
 165 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
 166 /**
 167   * @}
 168   */
 169
 170 /* Exported functions --------------------------------------------------------*/
 171 /** @addtogroup TIM_LL_Exported_Functions
 172   * @{
 173   */
 174
 175 /** @addtogroup TIM_LL_EF_Init
 176   * @{
 177   */
 178
 179 /**
 180   * @brief  Set TIMx registers to their reset values.
 181   * @param  TIMx Timer instance
 182   * @retval An ErrorStatus enumeration value:
 183   *          - SUCCESS: TIMx registers are de-initialized
 184   *          - ERROR: invalid TIMx instance
 185   */
 186 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
 187 {
 188   ErrorStatus result = SUCCESS;
 189
 190   /* Check the parameters */
 191   assert_param(IS_TIM_INSTANCE(TIMx));
 192
 193   if (TIMx == TIM2)
 194   {
 195     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
 196     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
 197   }
 198 #if defined(TIM1)
 199   else if (TIMx == TIM1)
 200   {
 201     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
 202     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
 203   }
 204 #endif
 205 #if defined(TIM3)
 206   else if (TIMx == TIM3)
 207   {
 208     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
 209     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
 210   }
 211 #endif
 212 #if defined(TIM4)
 213   else if (TIMx == TIM4)
 214   {
 215     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
 216     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
 217   }
 218 #endif
 219 #if defined(TIM5)
 220   else if (TIMx == TIM5)
 221   {
 222     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
 223     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
 224   }
 225 #endif
 226 #if defined(TIM6)
 227   else if (TIMx == TIM6)
 228   {
 229     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
 230     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
 231   }
 232 #endif
 233 #if defined (TIM7)
 234   else if (TIMx == TIM7)
 235   {
 236     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
 237     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
 238   }
 239 #endif
 240 #if defined(TIM8)
 241   else if (TIMx == TIM8)
 242   {
 243     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
 244     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
 245   }
 246 #endif
 247 #if defined(TIM9)
 248   else if (TIMx == TIM9)
 249   {
 250     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
 251     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
 252   }
 253 #endif
 254 #if defined(TIM10)
 255   else if (TIMx == TIM10)
 256   {
 257     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10);
 258     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
 259   }
 260 #endif
 261 #if defined(TIM11)
 262   else if (TIMx == TIM11)
 263   {
 264     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11);
 265     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
 266   }
 267 #endif
 268 #if defined(TIM12)
 269   else if (TIMx == TIM12)
 270   {
 271     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
 272     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
 273   }
 274 #endif
 275 #if defined(TIM13)
 276   else if (TIMx == TIM13)
 277   {
 278     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
 279     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
 280   }
 281 #endif
 282 #if defined(TIM14)
 283   else if (TIMx == TIM14)
 284   {
 285     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
 286     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
 287   }
 288 #endif
 289 #if defined(TIM15)
 290   else if (TIMx == TIM15)
 291   {
 292     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
 293     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
 294   }
 295 #endif
 296 #if defined(TIM16)
 297   else if (TIMx == TIM16)
 298   {
 299     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
 300     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
 301   }
 302 #endif
 303 #if defined(TIM17)
 304   else if (TIMx == TIM17)
 305   {
 306     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
 307     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
 308   }
 309 #endif
 310   else
 311   {
 312     result = ERROR;
 313   }
 314
 315   return result;
 316 }
 317
 318 /**
 319   * @brief  Set the fields of the time base unit configuration data structure
 320   *         to their default values.
 321   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
 322   * @retval None
 323   */
 324 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
 325 {
 326   /* Set the default configuration */
 327   TIM_InitStruct->Prescaler         = (uint16_t)0x0000;
 328   TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
 329   TIM_InitStruct->Autoreload        = 0xFFFFFFFFU;
 330   TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
 331   TIM_InitStruct->RepetitionCounter = (uint8_t)0x00;
 332 }
 333
 334 /**
 335   * @brief  Configure the TIMx time base unit.
 336   * @param  TIMx Timer Instance
 337   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
 338   * @retval An ErrorStatus enumeration value:
 339   *          - SUCCESS: TIMx registers are de-initialized
 340   *          - ERROR: not applicable
 341   */
 342 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
 343 {
 344   uint32_t tmpcr1 = 0U;
 345
 346   /* Check the parameters */
 347   assert_param(IS_TIM_INSTANCE(TIMx));
 348   assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
 349   assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
 350
 351   tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
 352
 353   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
 354   {
 355     /* Select the Counter Mode */
 356     MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
 357   }
 358
 359   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
 360   {
 361     /* Set the clock division */
 362     MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
 363   }
 364
 365   /* Write to TIMx CR1 */
 366   LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
 367
 368   /* Set the Autoreload value */
 369   LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
 370
 371   /* Set the Prescaler value */
 372   LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
 373
 374   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
 375   {
 376     /* Set the Repetition Counter value */
 377     LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
 378   }
 379
 380   /* Generate an update event to reload the Prescaler
 381      and the repetition counter value (if applicable) immediately */
 382   LL_TIM_GenerateEvent_UPDATE(TIMx);
 383
 384   return SUCCESS;
 385 }
 386
 387 /**
 388   * @brief  Set the fields of the TIMx output channel configuration data
 389   *         structure to their default values.
 390   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
 391   * @retval None
 392   */
 393 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
 394 {
 395   /* Set the default configuration */
 396   TIM_OC_InitStruct->OCMode       = LL_TIM_OCMODE_FROZEN;
 397   TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
 398   TIM_OC_InitStruct->OCNState     = LL_TIM_OCSTATE_DISABLE;
 399   TIM_OC_InitStruct->CompareValue = 0x00000000U;
 400   TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
 401   TIM_OC_InitStruct->OCNPolarity  = LL_TIM_OCPOLARITY_HIGH;
 402   TIM_OC_InitStruct->OCIdleState  = LL_TIM_OCIDLESTATE_LOW;
 403   TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
 404 }
 405
 406 /**
 407   * @brief  Configure the TIMx output channel.
 408   * @param  TIMx Timer Instance
 409   * @param  Channel This parameter can be one of the following values:
 410   *         @arg @ref LL_TIM_CHANNEL_CH1
 411   *         @arg @ref LL_TIM_CHANNEL_CH2
 412   *         @arg @ref LL_TIM_CHANNEL_CH3
 413   *         @arg @ref LL_TIM_CHANNEL_CH4
 414   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
 415   * @retval An ErrorStatus enumeration value:
 416   *          - SUCCESS: TIMx output channel is initialized
 417   *          - ERROR: TIMx output channel is not initialized
 418   */
 419 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
 420 {
 421   ErrorStatus result = ERROR;
 422
 423   switch (Channel)
 424   {
 425     case LL_TIM_CHANNEL_CH1:
 426       result = OC1Config(TIMx, TIM_OC_InitStruct);
 427       break;
 428     case LL_TIM_CHANNEL_CH2:
 429       result = OC2Config(TIMx, TIM_OC_InitStruct);
 430       break;
 431     case LL_TIM_CHANNEL_CH3:
 432       result = OC3Config(TIMx, TIM_OC_InitStruct);
 433       break;
 434     case LL_TIM_CHANNEL_CH4:
 435       result = OC4Config(TIMx, TIM_OC_InitStruct);
 436       break;
 437     default:
 438       break;
 439   }
 440
 441   return result;
 442 }
 443
 444 /**
 445   * @brief  Set the fields of the TIMx input channel configuration data
 446   *         structure to their default values.
 447   * @param  TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
 448   * @retval None
 449   */
 450 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
 451 {
 452   /* Set the default configuration */
 453   TIM_ICInitStruct->ICPolarity    = LL_TIM_IC_POLARITY_RISING;
 454   TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
 455   TIM_ICInitStruct->ICPrescaler   = LL_TIM_ICPSC_DIV1;
 456   TIM_ICInitStruct->ICFilter      = LL_TIM_IC_FILTER_FDIV1;
 457 }
 458
 459 /**
 460   * @brief  Configure the TIMx input channel.
 461   * @param  TIMx Timer Instance
 462   * @param  Channel This parameter can be one of the following values:
 463   *         @arg @ref LL_TIM_CHANNEL_CH1
 464   *         @arg @ref LL_TIM_CHANNEL_CH2
 465   *         @arg @ref LL_TIM_CHANNEL_CH3
 466   *         @arg @ref LL_TIM_CHANNEL_CH4
 467   * @param  TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
 468   * @retval An ErrorStatus enumeration value:
 469   *          - SUCCESS: TIMx output channel is initialized
 470   *          - ERROR: TIMx output channel is not initialized
 471   */
 472 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
 473 {
 474   ErrorStatus result = ERROR;
 475
 476   switch (Channel)
 477   {
 478     case LL_TIM_CHANNEL_CH1:
 479       result = IC1Config(TIMx, TIM_IC_InitStruct);
 480       break;
 481     case LL_TIM_CHANNEL_CH2:
 482       result = IC2Config(TIMx, TIM_IC_InitStruct);
 483       break;
 484     case LL_TIM_CHANNEL_CH3:
 485       result = IC3Config(TIMx, TIM_IC_InitStruct);
 486       break;
 487     case LL_TIM_CHANNEL_CH4:
 488       result = IC4Config(TIMx, TIM_IC_InitStruct);
 489       break;
 490     default:
 491       break;
 492   }
 493
 494   return result;
 495 }
 496
 497 /**
 498   * @brief  Fills each TIM_EncoderInitStruct field with its default value
 499   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
 500   * @retval None
 501   */
 502 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
 503 {
 504   /* Set the default configuration */
 505   TIM_EncoderInitStruct->EncoderMode    = LL_TIM_ENCODERMODE_X2_TI1;
 506   TIM_EncoderInitStruct->IC1Polarity    = LL_TIM_IC_POLARITY_RISING;
 507   TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
 508   TIM_EncoderInitStruct->IC1Prescaler   = LL_TIM_ICPSC_DIV1;
 509   TIM_EncoderInitStruct->IC1Filter      = LL_TIM_IC_FILTER_FDIV1;
 510   TIM_EncoderInitStruct->IC2Polarity    = LL_TIM_IC_POLARITY_RISING;
 511   TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
 512   TIM_EncoderInitStruct->IC2Prescaler   = LL_TIM_ICPSC_DIV1;
 513   TIM_EncoderInitStruct->IC2Filter      = LL_TIM_IC_FILTER_FDIV1;
 514 }
 515
 516 /**
 517   * @brief  Configure the encoder interface of the timer instance.
 518   * @param  TIMx Timer Instance
 519   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
 520   * @retval An ErrorStatus enumeration value:
 521   *          - SUCCESS: TIMx registers are de-initialized
 522   *          - ERROR: not applicable
 523   */
 524 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
 525 {
 526   uint32_t tmpccmr1 = 0U;
 527   uint32_t tmpccer = 0U;
 528
 529   /* Check the parameters */
 530   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
 531   assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
 532   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
 533   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
 534   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
 535   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
 536   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
 537   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
 538   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
 539   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
 540
 541   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
 542   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
 543
 544   /* Get the TIMx CCMR1 register value */
 545   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
 546
 547   /* Get the TIMx CCER register value */
 548   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
 549
 550   /* Configure TI1 */
 551   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
 552   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
 553   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
 554   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
 555
 556   /* Configure TI2 */
 557   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F  | TIM_CCMR1_IC2PSC);
 558   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
 559   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
 560   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
 561
 562   /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
 563   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
 564   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
 565   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
 566   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
 567
 568   /* Set encoder mode */
 569   LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
 570
 571   /* Write to TIMx CCMR1 */
 572   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
 573
 574   /* Write to TIMx CCER */
 575   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
 576
 577   return SUCCESS;
 578 }
 579
 580 /**
 581   * @brief  Set the fields of the TIMx Hall sensor interface configuration data
 582   *         structure to their default values.
 583   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
 584   * @retval None
 585   */
 586 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
 587 {
 588   /* Set the default configuration */
 589   TIM_HallSensorInitStruct->IC1Polarity       = LL_TIM_IC_POLARITY_RISING;
 590   TIM_HallSensorInitStruct->IC1Prescaler      = LL_TIM_ICPSC_DIV1;
 591   TIM_HallSensorInitStruct->IC1Filter         = LL_TIM_IC_FILTER_FDIV1;
 592   TIM_HallSensorInitStruct->CommutationDelay  = 0U;
 593 }
 594
 595 /**
 596   * @brief  Configure the Hall sensor interface of the timer instance.
 597   * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
 598   *       to the TI1 input channel
 599   * @note TIMx slave mode controller is configured in reset mode.
 600           Selected internal trigger is TI1F_ED.
 601   * @note Channel 1 is configured as input, IC1 is mapped on TRC.
 602   * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
 603   *       between 2 changes on the inputs. It gives information about motor speed.
 604   * @note Channel 2 is configured in output PWM 2 mode.
 605   * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
 606   * @note OC2REF is selected as trigger output on TRGO.
 607   * @param  TIMx Timer Instance
 608   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
 609   * @retval An ErrorStatus enumeration value:
 610   *          - SUCCESS: TIMx registers are de-initialized
 611   *          - ERROR: not applicable
 612   */
 613 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
 614 {
 615   uint32_t tmpcr2 = 0U;
 616   uint32_t tmpccmr1 = 0U;
 617   uint32_t tmpccer = 0U;
 618   uint32_t tmpsmcr = 0U;
 619
 620   /* Check the parameters */
 621   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
 622   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
 623   assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
 624   assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
 625
 626   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
 627   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
 628
 629   /* Get the TIMx CR2 register value */
 630   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
 631
 632   /* Get the TIMx CCMR1 register value */
 633   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
 634
 635   /* Get the TIMx CCER register value */
 636   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
 637
 638   /* Get the TIMx SMCR register value */
 639   tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
 640
 641   /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
 642   tmpcr2 |= TIM_CR2_TI1S;
 643
 644   /* OC2REF signal is used as trigger output (TRGO) */
 645   tmpcr2 |= LL_TIM_TRGO_OC2REF;
 646
 647   /* Configure the slave mode controller */
 648   tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
 649   tmpsmcr |= LL_TIM_TS_TI1F_ED;
 650   tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
 651
 652   /* Configure input channel 1 */
 653   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
 654   tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
 655   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
 656   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
 657
 658   /* Configure input channel 2 */
 659   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE  | TIM_CCMR1_OC2PE  | TIM_CCMR1_OC2CE);
 660   tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
 661
 662   /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
 663   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
 664   tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
 665   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
 666
 667   /* Write to TIMx CR2 */
 668   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
 669
 670   /* Write to TIMx SMCR */
 671   LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
 672
 673   /* Write to TIMx CCMR1 */
 674   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
 675
 676   /* Write to TIMx CCER */
 677   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
 678
 679   /* Write to TIMx CCR2 */
 680   LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
 681
 682   return SUCCESS;
 683 }
 684
 685 /**
 686   * @brief  Set the fields of the Break and Dead Time configuration data structure
 687   *         to their default values.
 688   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
 689   * @retval None
 690   */
 691 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
 692 {
 693   /* Set the default configuration */
 694   TIM_BDTRInitStruct->OSSRState       = LL_TIM_OSSR_DISABLE;
 695   TIM_BDTRInitStruct->OSSIState       = LL_TIM_OSSI_DISABLE;
 696   TIM_BDTRInitStruct->LockLevel       = LL_TIM_LOCKLEVEL_OFF;
 697   TIM_BDTRInitStruct->DeadTime        = (uint8_t)0x00;
 698   TIM_BDTRInitStruct->BreakState      = LL_TIM_BREAK_DISABLE;
 699   TIM_BDTRInitStruct->BreakPolarity   = LL_TIM_BREAK_POLARITY_LOW;
 700   TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
 701 }
 702
 703 /**
 704   * @brief  Configure the Break and Dead Time feature of the timer instance.
 705   * @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked
 706   *  depending on the LOCK configuration, it can be necessary to configure all of
 707   *  them during the first write access to the TIMx_BDTR register.
 708   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
 709   *       a timer instance provides a break input.
 710   * @param  TIMx Timer Instance
 711   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure)
 712   * @retval An ErrorStatus enumeration value:
 713   *          - SUCCESS: Break and Dead Time is initialized
 714   *          - ERROR: not applicable
 715   */
 716 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
 717 {
 718   uint32_t tmpbdtr = 0;
 719
 720   /* Check the parameters */
 721   assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
 722   assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
 723   assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
 724   assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
 725   assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
 726   assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
 727   assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
 728
 729   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
 730   the OSSI State, the dead time value and the Automatic Output Enable Bit */
 731
 732   /* Set the BDTR bits */
 733   MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
 734   MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
 735   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
 736   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
 737   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
 738   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
 739   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
 740   MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
 741
 742   /* Set TIMx_BDTR */
 743   LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
 744
 745   return SUCCESS;
 746 }
 747 /**
 748   * @}
 749   */
 750
 751 /**
 752   * @}
 753   */
 754
 755 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
 756  *  @brief   Private functions
 757   * @{
 758   */
 759 /**
 760   * @brief  Configure the TIMx output channel 1.
 761   * @param  TIMx Timer Instance
 762   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
 763   * @retval An ErrorStatus enumeration value:
 764   *          - SUCCESS: TIMx registers are de-initialized
 765   *          - ERROR: not applicable
 766   */
 767 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
 768 {
 769   uint32_t tmpccmr1 = 0U;
 770   uint32_t tmpccer = 0U;
 771   uint32_t tmpcr2 = 0U;
 772
 773   /* Check the parameters */
 774   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
 775   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
 776   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
 777   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
 778   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
 779   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
 780
 781   /* Disable the Channel 1: Reset the CC1E Bit */
 782   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
 783
 784   /* Get the TIMx CCER register value */
 785   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
 786
 787   /* Get the TIMx CR2 register value */
 788   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
 789
 790   /* Get the TIMx CCMR1 register value */
 791   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
 792
 793   /* Reset Capture/Compare selection Bits */
 794   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
 795
 796   /* Set the Output Compare Mode */
 797   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
 798
 799   /* Set the Output Compare Polarity */
 800   MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
 801
 802   /* Set the Output State */
 803   MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
 804
 805   if (IS_TIM_BREAK_INSTANCE(TIMx))
 806   {
 807     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
 808     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
 809
 810     /* Set the complementary output Polarity */
 811     MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
 812
 813     /* Set the complementary output State */
 814     MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
 815
 816     /* Set the Output Idle state */
 817     MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
 818
 819     /* Set the complementary output Idle state */
 820     MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
 821   }
 822
 823   /* Write to TIMx CR2 */
 824   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
 825
 826   /* Write to TIMx CCMR1 */
 827   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
 828
 829   /* Set the Capture Compare Register value */
 830   LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
 831
 832   /* Write to TIMx CCER */
 833   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
 834
 835   return SUCCESS;
 836 }
 837
 838 /**
 839   * @brief  Configure the TIMx output channel 2.
 840   * @param  TIMx Timer Instance
 841   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
 842   * @retval An ErrorStatus enumeration value:
 843   *          - SUCCESS: TIMx registers are de-initialized
 844   *          - ERROR: not applicable
 845   */
 846 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
 847 {
 848   uint32_t tmpccmr1 = 0U;
 849   uint32_t tmpccer = 0U;
 850   uint32_t tmpcr2 = 0U;
 851
 852   /* Check the parameters */
 853   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
 854   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
 855   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
 856   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
 857   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
 858   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
 859
 860   /* Disable the Channel 2: Reset the CC2E Bit */
 861   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
 862
 863   /* Get the TIMx CCER register value */
 864   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
 865
 866   /* Get the TIMx CR2 register value */
 867   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
 868
 869   /* Get the TIMx CCMR1 register value */
 870   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
 871
 872   /* Reset Capture/Compare selection Bits */
 873   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
 874
 875   /* Select the Output Compare Mode */
 876   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
 877
 878   /* Set the Output Compare Polarity */
 879   MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
 880
 881   /* Set the Output State */
 882   MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
 883
 884   if (IS_TIM_BREAK_INSTANCE(TIMx))
 885   {
 886     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
 887     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
 888
 889     /* Set the complementary output Polarity */
 890     MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
 891
 892     /* Set the complementary output State */
 893     MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
 894
 895     /* Set the Output Idle state */
 896     MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
 897
 898     /* Set the complementary output Idle state */
 899     MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
 900   }
 901
 902   /* Write to TIMx CR2 */
 903   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
 904
 905   /* Write to TIMx CCMR1 */
 906   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
 907
 908   /* Set the Capture Compare Register value */
 909   LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
 910
 911   /* Write to TIMx CCER */
 912   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
 913
 914   return SUCCESS;
 915 }
 916
 917 /**
 918   * @brief  Configure the TIMx output channel 3.
 919   * @param  TIMx Timer Instance
 920   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
 921   * @retval An ErrorStatus enumeration value:
 922   *          - SUCCESS: TIMx registers are de-initialized
 923   *          - ERROR: not applicable
 924   */
 925 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
 926 {
 927   uint32_t tmpccmr2 = 0U;
 928   uint32_t tmpccer = 0U;
 929   uint32_t tmpcr2 = 0U;
 930
 931   /* Check the parameters */
 932   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
 933   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
 934   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
 935   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
 936   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
 937   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
 938
 939   /* Disable the Channel 3: Reset the CC3E Bit */
 940   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
 941
 942   /* Get the TIMx CCER register value */
 943   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
 944
 945   /* Get the TIMx CR2 register value */
 946   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
 947
 948   /* Get the TIMx CCMR2 register value */
 949   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
 950
 951   /* Reset Capture/Compare selection Bits */
 952   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
 953
 954   /* Select the Output Compare Mode */
 955   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
 956
 957   /* Set the Output Compare Polarity */
 958   MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
 959
 960   /* Set the Output State */
 961   MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
 962
 963   if (IS_TIM_BREAK_INSTANCE(TIMx))
 964   {
 965     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
 966     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
 967
 968     /* Set the complementary output Polarity */
 969     MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
 970
 971     /* Set the complementary output State */
 972     MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
 973
 974     /* Set the Output Idle state */
 975     MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
 976
 977     /* Set the complementary output Idle state */
 978     MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
 979   }
 980
 981   /* Write to TIMx CR2 */
 982   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
 983
 984   /* Write to TIMx CCMR2 */
 985   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
 986
 987   /* Set the Capture Compare Register value */
 988   LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
 989
 990   /* Write to TIMx CCER */
 991   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
 992
 993   return SUCCESS;
 994 }
 995
 996 /**
 997   * @brief  Configure the TIMx output channel 4.
 998   * @param  TIMx Timer Instance
 999   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
1000   * @retval An ErrorStatus enumeration value:
1001   *          - SUCCESS: TIMx registers are de-initialized
1002   *          - ERROR: not applicable
1003   */
1004 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1005 {
1006   uint32_t tmpccmr2 = 0U;
1007   uint32_t tmpccer = 0U;
1008   uint32_t tmpcr2 = 0U;
1009
1010   /* Check the parameters */
1011   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1012   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1013   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1014   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1015   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1016   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1017
1018   /* Disable the Channel 4: Reset the CC4E Bit */
1019   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1020
1021   /* Get the TIMx CCER register value */
1022   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1023
1024   /* Get the TIMx CR2 register value */
1025   tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);
1026
1027   /* Get the TIMx CCMR2 register value */
1028   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1029
1030   /* Reset Capture/Compare selection Bits */
1031   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1032
1033   /* Select the Output Compare Mode */
1034   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1035
1036   /* Set the Output Compare Polarity */
1037   MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1038
1039   /* Set the Output State */
1040   MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1041
1042   if (IS_TIM_BREAK_INSTANCE(TIMx))
1043   {
1044     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1045     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1046
1047     /* Set the Output Idle state */
1048     MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1049   }
1050
1051   /* Write to TIMx CR2 */
1052   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1053
1054   /* Write to TIMx CCMR2 */
1055   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1056
1057   /* Set the Capture Compare Register value */
1058   LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1059
1060   /* Write to TIMx CCER */
1061   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1062
1063   return SUCCESS;
1064 }
1065
1066
1067 /**
1068   * @brief  Configure the TIMx input channel 1.
1069   * @param  TIMx Timer Instance
1070   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1071   * @retval An ErrorStatus enumeration value:
1072   *          - SUCCESS: TIMx registers are de-initialized
1073   *          - ERROR: not applicable
1074   */
1075 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1076 {
1077   /* Check the parameters */
1078   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1079   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1080   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1081   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1082   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1083
1084   /* Disable the Channel 1: Reset the CC1E Bit */
1085   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1086
1087   /* Select the Input and set the filter and the prescaler value */
1088   MODIFY_REG(TIMx->CCMR1,
1089              (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1090              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1091
1092   /* Select the Polarity and set the CC1E Bit */
1093   MODIFY_REG(TIMx->CCER,
1094              (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1095              (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1096
1097   return SUCCESS;
1098 }
1099
1100 /**
1101   * @brief  Configure the TIMx input channel 2.
1102   * @param  TIMx Timer Instance
1103   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1104   * @retval An ErrorStatus enumeration value:
1105   *          - SUCCESS: TIMx registers are de-initialized
1106   *          - ERROR: not applicable
1107   */
1108 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1109 {
1110   /* Check the parameters */
1111   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1112   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1113   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1114   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1115   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1116
1117   /* Disable the Channel 2: Reset the CC2E Bit */
1118   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1119
1120   /* Select the Input and set the filter and the prescaler value */
1121   MODIFY_REG(TIMx->CCMR1,
1122              (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1123              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1124
1125   /* Select the Polarity and set the CC2E Bit */
1126   MODIFY_REG(TIMx->CCER,
1127              (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1128              ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1129
1130   return SUCCESS;
1131 }
1132
1133 /**
1134   * @brief  Configure the TIMx input channel 3.
1135   * @param  TIMx Timer Instance
1136   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1137   * @retval An ErrorStatus enumeration value:
1138   *          - SUCCESS: TIMx registers are de-initialized
1139   *          - ERROR: not applicable
1140   */
1141 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1142 {
1143   /* Check the parameters */
1144   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1145   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1146   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1147   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1148   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1149
1150   /* Disable the Channel 3: Reset the CC3E Bit */
1151   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1152
1153   /* Select the Input and set the filter and the prescaler value */
1154   MODIFY_REG(TIMx->CCMR2,
1155              (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1156              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1157
1158   /* Select the Polarity and set the CC3E Bit */
1159   MODIFY_REG(TIMx->CCER,
1160              (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1161              ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1162
1163   return SUCCESS;
1164 }
1165
1166 /**
1167   * @brief  Configure the TIMx input channel 4.
1168   * @param  TIMx Timer Instance
1169   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1170   * @retval An ErrorStatus enumeration value:
1171   *          - SUCCESS: TIMx registers are de-initialized
1172   *          - ERROR: not applicable
1173   */
1174 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1175 {
1176   /* Check the parameters */
1177   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1178   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1179   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1180   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1181   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1182
1183   /* Disable the Channel 4: Reset the CC4E Bit */
1184   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1185
1186   /* Select the Input and set the filter and the prescaler value */
1187   MODIFY_REG(TIMx->CCMR2,
1188              (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1189              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1190
1191   /* Select the Polarity and set the CC4E Bit */
1192   MODIFY_REG(TIMx->CCER,
1193              TIM_CCER_CC4P,
1194              ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1195
1196   return SUCCESS;
1197 }
1198
1199
1200 /**
1201   * @}
1202   */
1203
1204 /**
1205   * @}
1206   */
1207
1208 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14  || TIM15 || TIM16 || TIM17 */
1209
1210 /**
1211   * @}
1212   */
1213
1214 #endif /* USE_FULL_LL_DRIVER */
1215
1216 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/