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Merge pull request #11270 from haslinghuis/rename_attr
[betaflight.git] / lib / main / CMSIS / Core / Include / core_cm33.h
blobb1efbcae7c733a636cfb4e043b6c4858e84ac6b6
1 /**************************************************************************//**
2 * @file core_cm33.h
3 * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
4 * @version V5.0.5
5 * @date 08. January 2018
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29 #endif
30
31 #ifndef __CORE_CM33_H_GENERIC
32 #define __CORE_CM33_H_GENERIC
33
34 #include <stdint.h>
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55 /*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58 /**
59 \ingroup Cortex_M33
60 @{
61 */
62
63 #include "cmsis_version.h"
64
65 /* CMSIS CM33 definitions */
66 #define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
67 #define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
68 #define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
69 __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
70
71 #define __CORTEX_M (33U) /*!< Cortex-M Core */
72
73 /** __FPU_USED indicates whether an FPU is used or not.
74 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
75 */
76 #if defined ( __CC_ARM )
77 #if defined (__TARGET_FPU_VFP)
78 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
79 #define __FPU_USED 1U
80 #else
81 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
82 #define __FPU_USED 0U
83 #endif
84 #else
85 #define __FPU_USED 0U
86 #endif
87
88 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
89 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
90 #define __DSP_USED 1U
91 #else
92 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
93 #define __DSP_USED 0U
94 #endif
95 #else
96 #define __DSP_USED 0U
97 #endif
98
99 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
100 #if defined (__ARM_PCS_VFP)
101 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
102 #define __FPU_USED 1U
103 #else
104 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
105 #define __FPU_USED 0U
106 #endif
107 #else
108 #define __FPU_USED 0U
109 #endif
110
111 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
112 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
113 #define __DSP_USED 1U
114 #else
115 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
116 #define __DSP_USED 0U
117 #endif
118 #else
119 #define __DSP_USED 0U
120 #endif
121
122 #elif defined ( __GNUC__ )
123 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
124 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
125 #define __FPU_USED 1U
126 #else
127 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
128 #define __FPU_USED 0U
129 #endif
130 #else
131 #define __FPU_USED 0U
132 #endif
133
134 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
135 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
136 #define __DSP_USED 1U
137 #else
138 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
139 #define __DSP_USED 0U
140 #endif
141 #else
142 #define __DSP_USED 0U
143 #endif
144
145 #elif defined ( __ICCARM__ )
146 #if defined (__ARMVFP__)
147 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
148 #define __FPU_USED 1U
149 #else
150 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
151 #define __FPU_USED 0U
152 #endif
153 #else
154 #define __FPU_USED 0U
155 #endif
156
157 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
158 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
159 #define __DSP_USED 1U
160 #else
161 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
162 #define __DSP_USED 0U
163 #endif
164 #else
165 #define __DSP_USED 0U
166 #endif
167
168 #elif defined ( __TI_ARM__ )
169 #if defined (__TI_VFP_SUPPORT__)
170 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
171 #define __FPU_USED 1U
172 #else
173 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
174 #define __FPU_USED 0U
175 #endif
176 #else
177 #define __FPU_USED 0U
178 #endif
179
180 #elif defined ( __TASKING__ )
181 #if defined (__FPU_VFP__)
182 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
183 #define __FPU_USED 1U
184 #else
185 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
186 #define __FPU_USED 0U
187 #endif
188 #else
189 #define __FPU_USED 0U
190 #endif
191
192 #elif defined ( __CSMC__ )
193 #if ( __CSMC__ & 0x400U)
194 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
195 #define __FPU_USED 1U
196 #else
197 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
198 #define __FPU_USED 0U
199 #endif
200 #else
201 #define __FPU_USED 0U
202 #endif
203
204 #endif
205
206 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
207
208
209 #ifdef __cplusplus
210 }
211 #endif
212
213 #endif /* __CORE_CM33_H_GENERIC */
214
215 #ifndef __CMSIS_GENERIC
216
217 #ifndef __CORE_CM33_H_DEPENDANT
218 #define __CORE_CM33_H_DEPENDANT
219
220 #ifdef __cplusplus
221 extern "C" {
222 #endif
223
224 /* check device defines and use defaults */
225 #if defined __CHECK_DEVICE_DEFINES
226 #ifndef __CM33_REV
227 #define __CM33_REV 0x0000U
228 #warning "__CM33_REV not defined in device header file; using default!"
229 #endif
230
231 #ifndef __FPU_PRESENT
232 #define __FPU_PRESENT 0U
233 #warning "__FPU_PRESENT not defined in device header file; using default!"
234 #endif
235
236 #ifndef __MPU_PRESENT
237 #define __MPU_PRESENT 0U
238 #warning "__MPU_PRESENT not defined in device header file; using default!"
239 #endif
240
241 #ifndef __SAUREGION_PRESENT
242 #define __SAUREGION_PRESENT 0U
243 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
244 #endif
245
246 #ifndef __DSP_PRESENT
247 #define __DSP_PRESENT 0U
248 #warning "__DSP_PRESENT not defined in device header file; using default!"
249 #endif
250
251 #ifndef __NVIC_PRIO_BITS
252 #define __NVIC_PRIO_BITS 3U
253 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
254 #endif
255
256 #ifndef __Vendor_SysTickConfig
257 #define __Vendor_SysTickConfig 0U
258 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
259 #endif
260 #endif
261
262 /* IO definitions (access restrictions to peripheral registers) */
263 /**
264 \defgroup CMSIS_glob_defs CMSIS Global Defines
265
266 <strong>IO Type Qualifiers</strong> are used
267 \li to specify the access to peripheral variables.
268 \li for automatic generation of peripheral register debug information.
269 */
270 #ifdef __cplusplus
271 #define __I volatile /*!< Defines 'read only' permissions */
272 #else
273 #define __I volatile const /*!< Defines 'read only' permissions */
274 #endif
275 #define __O volatile /*!< Defines 'write only' permissions */
276 #define __IO volatile /*!< Defines 'read / write' permissions */
277
278 /* following defines should be used for structure members */
279 #define __IM volatile const /*! Defines 'read only' structure member permissions */
280 #define __OM volatile /*! Defines 'write only' structure member permissions */
281 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
282
283 /*@} end of group Cortex_M33 */
284
285
286
287 /*******************************************************************************
288 * Register Abstraction
289 Core Register contain:
290 - Core Register
291 - Core NVIC Register
292 - Core SCB Register
293 - Core SysTick Register
294 - Core Debug Register
295 - Core MPU Register
296 - Core SAU Register
297 - Core FPU Register
298 ******************************************************************************/
299 /**
300 \defgroup CMSIS_core_register Defines and Type Definitions
301 \brief Type definitions and defines for Cortex-M processor based devices.
302 */
303
304 /**
305 \ingroup CMSIS_core_register
306 \defgroup CMSIS_CORE Status and Control Registers
307 \brief Core Register type definitions.
308 @{
309 */
310
311 /**
312 \brief Union type to access the Application Program Status Register (APSR).
313 */
314 typedef union
315 {
316 struct
317 {
318 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
319 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
320 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
321 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
322 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
323 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
324 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
325 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
326 } b; /*!< Structure used for bit access */
327 uint32_t w; /*!< Type used for word access */
328 } APSR_Type;
329
330 /* APSR Register Definitions */
331 #define APSR_N_Pos 31U /*!< APSR: N Position */
332 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
333
334 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
335 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
336
337 #define APSR_C_Pos 29U /*!< APSR: C Position */
338 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
339
340 #define APSR_V_Pos 28U /*!< APSR: V Position */
341 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
342
343 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
344 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
345
346 #define APSR_GE_Pos 16U /*!< APSR: GE Position */
347 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
348
349
350 /**
351 \brief Union type to access the Interrupt Program Status Register (IPSR).
352 */
353 typedef union
354 {
355 struct
356 {
357 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
358 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
359 } b; /*!< Structure used for bit access */
360 uint32_t w; /*!< Type used for word access */
361 } IPSR_Type;
362
363 /* IPSR Register Definitions */
364 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
365 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
366
367
368 /**
369 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
370 */
371 typedef union
372 {
373 struct
374 {
375 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
376 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
377 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
378 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
379 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
380 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
381 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
382 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
383 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
384 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
385 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
386 } b; /*!< Structure used for bit access */
387 uint32_t w; /*!< Type used for word access */
388 } xPSR_Type;
389
390 /* xPSR Register Definitions */
391 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
392 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
393
394 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
395 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
396
397 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
398 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
399
400 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
401 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
402
403 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
404 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
405
406 #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
407 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
408
409 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
410 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
411
412 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
413 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
414
415 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
416 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
417
418
419 /**
420 \brief Union type to access the Control Registers (CONTROL).
421 */
422 typedef union
423 {
424 struct
425 {
426 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
427 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
428 uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
429 uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
430 uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
431 } b; /*!< Structure used for bit access */
432 uint32_t w; /*!< Type used for word access */
433 } CONTROL_Type;
434
435 /* CONTROL Register Definitions */
436 #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
437 #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
438
439 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
440 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
441
442 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
443 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
444
445 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
446 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
447
448 /*@} end of group CMSIS_CORE */
449
450
451 /**
452 \ingroup CMSIS_core_register
453 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
454 \brief Type definitions for the NVIC Registers
455 @{
456 */
457
458 /**
459 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
460 */
461 typedef struct
462 {
463 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
464 uint32_t RESERVED0[16U];
465 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
466 uint32_t RSERVED1[16U];
467 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
468 uint32_t RESERVED2[16U];
469 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
470 uint32_t RESERVED3[16U];
471 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
472 uint32_t RESERVED4[16U];
473 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
474 uint32_t RESERVED5[16U];
475 __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
476 uint32_t RESERVED6[580U];
477 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
478 } NVIC_Type;
479
480 /* Software Triggered Interrupt Register Definitions */
481 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
482 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
483
484 /*@} end of group CMSIS_NVIC */
485
486
487 /**
488 \ingroup CMSIS_core_register
489 \defgroup CMSIS_SCB System Control Block (SCB)
490 \brief Type definitions for the System Control Block Registers
491 @{
492 */
493
494 /**
495 \brief Structure type to access the System Control Block (SCB).
496 */
497 typedef struct
498 {
499 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
500 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
501 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
502 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
503 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
504 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
505 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
506 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
507 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
508 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
509 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
510 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
511 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
512 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
513 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
514 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
515 __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
516 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
517 __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
518 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
519 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
520 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
521 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
522 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
523 __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
524 uint32_t RESERVED3[92U];
525 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
526 uint32_t RESERVED4[15U];
527 __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
528 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
529 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
530 uint32_t RESERVED5[1U];
531 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
532 uint32_t RESERVED6[1U];
533 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
534 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
535 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
536 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
537 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
538 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
539 __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
540 __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
541 uint32_t RESERVED7[6U];
542 __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
543 __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
544 __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
545 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
546 __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
547 uint32_t RESERVED8[1U];
548 __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
549 } SCB_Type;
550
551 /* SCB CPUID Register Definitions */
552 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
553 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
554
555 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
556 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
557
558 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
559 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
560
561 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
562 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
563
564 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
565 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
566
567 /* SCB Interrupt Control State Register Definitions */
568 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
569 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
570
571 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
572 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
573
574 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
575 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
576
577 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
578 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
579
580 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
581 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
582
583 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
584 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
585
586 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
587 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
588
589 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
590 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
591
592 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
593 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
594
595 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
596 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
597
598 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
599 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
600
601 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
602 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
603
604 /* SCB Vector Table Offset Register Definitions */
605 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
606 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
607
608 /* SCB Application Interrupt and Reset Control Register Definitions */
609 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
610 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
611
612 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
613 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
614
615 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
616 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
617
618 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
619 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
620
621 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
622 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
623
624 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
625 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
626
627 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
628 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
629
630 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
631 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
632
633 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
634 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
635
636 /* SCB System Control Register Definitions */
637 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
638 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
639
640 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
641 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
642
643 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
644 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
645
646 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
647 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
648
649 /* SCB Configuration Control Register Definitions */
650 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
651 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
652
653 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
654 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
655
656 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
657 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
658
659 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
660 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
661
662 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
663 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
664
665 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
666 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
667
668 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
669 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
670
671 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
672 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
673
674 /* SCB System Handler Control and State Register Definitions */
675 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
676 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
677
678 #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
679 #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
680
681 #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
682 #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
683
684 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
685 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
686
687 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
688 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
689
690 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
691 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
692
693 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
694 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
695
696 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
697 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
698
699 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
700 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
701
702 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
703 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
704
705 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
706 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
707
708 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
709 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
710
711 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
712 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
713
714 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
715 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
716
717 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
718 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
719
720 #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
721 #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
722
723 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
724 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
725
726 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
727 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
728
729 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
730 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
731
732 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
733 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
734
735 /* SCB Configurable Fault Status Register Definitions */
736 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
737 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
738
739 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
740 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
741
742 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
743 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
744
745 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
746 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
747 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
748
749 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
750 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
751
752 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
753 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
754
755 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
756 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
757
758 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
759 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
760
761 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
762 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
763
764 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
765 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
766 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
767
768 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
769 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
770
771 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
772 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
773
774 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
775 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
776
777 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
778 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
779
780 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
781 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
782
783 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
784 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
785
786 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
787 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
788 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
789
790 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
791 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
792
793 #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
794 #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
795
796 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
797 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
798
799 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
800 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
801
802 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
803 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
804
805 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
806 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
807
808 /* SCB Hard Fault Status Register Definitions */
809 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
810 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
811
812 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
813 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
814
815 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
816 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
817
818 /* SCB Debug Fault Status Register Definitions */
819 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
820 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
821
822 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
823 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
824
825 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
826 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
827
828 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
829 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
830
831 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
832 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
833
834 /* SCB Non-Secure Access Control Register Definitions */
835 #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
836 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
837
838 #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
839 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
840
841 #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
842 #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
843
844 /* SCB Cache Level ID Register Definitions */
845 #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
846 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
847
848 #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
849 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
850
851 /* SCB Cache Type Register Definitions */
852 #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
853 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
854
855 #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
856 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
857
858 #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
859 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
860
861 #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
862 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
863
864 #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
865 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
866
867 /* SCB Cache Size ID Register Definitions */
868 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
869 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
870
871 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
872 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
873
874 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
875 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
876
877 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
878 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
879
880 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
881 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
882
883 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
884 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
885
886 #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
887 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
888
889 /* SCB Cache Size Selection Register Definitions */
890 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
891 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
892
893 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
894 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
895
896 /* SCB Software Triggered Interrupt Register Definitions */
897 #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
898 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
899
900 /* SCB D-Cache Invalidate by Set-way Register Definitions */
901 #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
902 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
903
904 #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
905 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
906
907 /* SCB D-Cache Clean by Set-way Register Definitions */
908 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
909 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
910
911 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
912 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
913
914 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
915 #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
916 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
917
918 #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
919 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
920
921 /* Instruction Tightly-Coupled Memory Control Register Definitions */
922 #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
923 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
924
925 #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
926 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
927
928 #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
929 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
930
931 #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
932 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
933
934 /* Data Tightly-Coupled Memory Control Register Definitions */
935 #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
936 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
937
938 #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
939 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
940
941 #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
942 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
943
944 #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
945 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
946
947 /* AHBP Control Register Definitions */
948 #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
949 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
950
951 #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
952 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
953
954 /* L1 Cache Control Register Definitions */
955 #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
956 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
957
958 #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
959 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
960
961 #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
962 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
963
964 /* AHBS Control Register Definitions */
965 #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
966 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
967
968 #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
969 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
970
971 #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
972 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
973
974 /* Auxiliary Bus Fault Status Register Definitions */
975 #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
976 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
977
978 #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
979 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
980
981 #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
982 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
983
984 #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
985 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
986
987 #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
988 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
989
990 #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
991 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
992
993 /*@} end of group CMSIS_SCB */
994
995
996 /**
997 \ingroup CMSIS_core_register
998 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
999 \brief Type definitions for the System Control and ID Register not in the SCB
1000 @{
1001 */
1002
1003 /**
1004 \brief Structure type to access the System Control and ID Register not in the SCB.
1005 */
1006 typedef struct
1007 {
1008 uint32_t RESERVED0[1U];
1009 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
1010 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
1011 __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
1012 } SCnSCB_Type;
1013
1014 /* Interrupt Controller Type Register Definitions */
1015 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
1016 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
1017
1018 /*@} end of group CMSIS_SCnotSCB */
1019
1020
1021 /**
1022 \ingroup CMSIS_core_register
1023 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
1024 \brief Type definitions for the System Timer Registers.
1025 @{
1026 */
1027
1028 /**
1029 \brief Structure type to access the System Timer (SysTick).
1030 */
1031 typedef struct
1032 {
1033 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
1034 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
1035 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
1036 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
1037 } SysTick_Type;
1038
1039 /* SysTick Control / Status Register Definitions */
1040 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
1041 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
1042
1043 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
1044 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
1045
1046 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
1047 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
1048
1049 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
1050 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
1051
1052 /* SysTick Reload Register Definitions */
1053 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
1054 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
1055
1056 /* SysTick Current Register Definitions */
1057 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
1058 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
1059
1060 /* SysTick Calibration Register Definitions */
1061 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
1062 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
1063
1064 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
1065 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
1066
1067 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
1068 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
1069
1070 /*@} end of group CMSIS_SysTick */
1071
1072
1073 /**
1074 \ingroup CMSIS_core_register
1075 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
1076 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
1077 @{
1078 */
1079
1080 /**
1081 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
1082 */
1083 typedef struct
1084 {
1085 __OM union
1086 {
1087 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
1088 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
1089 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
1090 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
1091 uint32_t RESERVED0[864U];
1092 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
1093 uint32_t RESERVED1[15U];
1094 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
1095 uint32_t RESERVED2[15U];
1096 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
1097 uint32_t RESERVED3[29U];
1098 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
1099 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
1100 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
1101 uint32_t RESERVED4[43U];
1102 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
1103 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
1104 uint32_t RESERVED5[1U];
1105 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
1106 uint32_t RESERVED6[4U];
1107 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
1108 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
1109 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
1110 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
1111 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
1112 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
1113 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
1114 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
1115 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
1116 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
1117 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
1118 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
1119 } ITM_Type;
1120
1121 /* ITM Stimulus Port Register Definitions */
1122 #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
1123 #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
1124
1125 #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
1126 #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
1127
1128 /* ITM Trace Privilege Register Definitions */
1129 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
1130 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
1131
1132 /* ITM Trace Control Register Definitions */
1133 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
1134 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
1135
1136 #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
1137 #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
1138
1139 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
1140 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
1141
1142 #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
1143 #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
1144
1145 #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
1146 #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
1147
1148 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
1149 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
1150
1151 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
1152 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
1153
1154 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
1155 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
1156
1157 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
1158 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
1159
1160 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
1161 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
1162
1163 /* ITM Integration Write Register Definitions */
1164 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
1165 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
1166
1167 /* ITM Integration Read Register Definitions */
1168 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
1169 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
1170
1171 /* ITM Integration Mode Control Register Definitions */
1172 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
1173 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
1174
1175 /* ITM Lock Status Register Definitions */
1176 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
1177 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
1178
1179 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
1180 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
1181
1182 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
1183 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
1184
1185 /*@}*/ /* end of group CMSIS_ITM */
1186
1187
1188 /**
1189 \ingroup CMSIS_core_register
1190 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
1191 \brief Type definitions for the Data Watchpoint and Trace (DWT)
1192 @{
1193 */
1194
1195 /**
1196 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
1197 */
1198 typedef struct
1199 {
1200 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
1201 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
1202 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
1203 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
1204 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
1205 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
1206 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
1207 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
1208 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
1209 uint32_t RESERVED1[1U];
1210 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
1211 uint32_t RESERVED2[1U];
1212 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
1213 uint32_t RESERVED3[1U];
1214 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
1215 uint32_t RESERVED4[1U];
1216 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
1217 uint32_t RESERVED5[1U];
1218 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
1219 uint32_t RESERVED6[1U];
1220 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
1221 uint32_t RESERVED7[1U];
1222 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
1223 uint32_t RESERVED8[1U];
1224 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
1225 uint32_t RESERVED9[1U];
1226 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
1227 uint32_t RESERVED10[1U];
1228 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
1229 uint32_t RESERVED11[1U];
1230 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
1231 uint32_t RESERVED12[1U];
1232 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
1233 uint32_t RESERVED13[1U];
1234 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
1235 uint32_t RESERVED14[1U];
1236 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
1237 uint32_t RESERVED15[1U];
1238 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
1239 uint32_t RESERVED16[1U];
1240 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
1241 uint32_t RESERVED17[1U];
1242 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
1243 uint32_t RESERVED18[1U];
1244 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
1245 uint32_t RESERVED19[1U];
1246 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
1247 uint32_t RESERVED20[1U];
1248 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
1249 uint32_t RESERVED21[1U];
1250 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
1251 uint32_t RESERVED22[1U];
1252 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
1253 uint32_t RESERVED23[1U];
1254 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
1255 uint32_t RESERVED24[1U];
1256 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
1257 uint32_t RESERVED25[1U];
1258 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
1259 uint32_t RESERVED26[1U];
1260 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
1261 uint32_t RESERVED27[1U];
1262 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
1263 uint32_t RESERVED28[1U];
1264 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
1265 uint32_t RESERVED29[1U];
1266 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
1267 uint32_t RESERVED30[1U];
1268 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
1269 uint32_t RESERVED31[1U];
1270 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
1271 uint32_t RESERVED32[934U];
1272 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
1273 uint32_t RESERVED33[1U];
1274 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
1275 } DWT_Type;
1276
1277 /* DWT Control Register Definitions */
1278 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
1279 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
1280
1281 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
1282 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
1283
1284 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
1285 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
1286
1287 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
1288 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
1289
1290 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
1291 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
1292
1293 #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
1294 #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
1295
1296 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
1297 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
1298
1299 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
1300 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
1301
1302 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
1303 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
1304
1305 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
1306 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
1307
1308 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
1309 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
1310
1311 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
1312 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
1313
1314 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
1315 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
1316
1317 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
1318 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
1319
1320 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
1321 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
1322
1323 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
1324 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
1325
1326 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
1327 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
1328
1329 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
1330 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
1331
1332 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
1333 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
1334
1335 /* DWT CPI Count Register Definitions */
1336 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
1337 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
1338
1339 /* DWT Exception Overhead Count Register Definitions */
1340 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
1341 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
1342
1343 /* DWT Sleep Count Register Definitions */
1344 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
1345 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
1346
1347 /* DWT LSU Count Register Definitions */
1348 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
1349 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
1350
1351 /* DWT Folded-instruction Count Register Definitions */
1352 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
1353 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
1354
1355 /* DWT Comparator Function Register Definitions */
1356 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
1357 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
1358
1359 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
1360 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
1361
1362 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
1363 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
1364
1365 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
1366 #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
1367
1368 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
1369 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
1370
1371 /*@}*/ /* end of group CMSIS_DWT */
1372
1373
1374 /**
1375 \ingroup CMSIS_core_register
1376 \defgroup CMSIS_TPI Trace Port Interface (TPI)
1377 \brief Type definitions for the Trace Port Interface (TPI)
1378 @{
1379 */
1380
1381 /**
1382 \brief Structure type to access the Trace Port Interface Register (TPI).
1383 */
1384 typedef struct
1385 {
1386 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
1387 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
1388 uint32_t RESERVED0[2U];
1389 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
1390 uint32_t RESERVED1[55U];
1391 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
1392 uint32_t RESERVED2[131U];
1393 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
1394 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
1395 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
1396 uint32_t RESERVED3[759U];
1397 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
1398 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1399 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1400 uint32_t RESERVED4[1U];
1401 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1402 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1403 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
1404 uint32_t RESERVED5[39U];
1405 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
1406 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
1407 uint32_t RESERVED7[8U];
1408 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1409 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
1410 } TPI_Type;
1411
1412 /* TPI Asynchronous Clock Prescaler Register Definitions */
1413 #define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */
1414 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */
1415
1416 #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
1417 #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
1418
1419 /* TPI Selected Pin Protocol Register Definitions */
1420 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
1421 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
1422
1423 /* TPI Formatter and Flush Status Register Definitions */
1424 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
1425 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
1426
1427 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
1428 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
1429
1430 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
1431 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
1432
1433 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
1434 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
1435
1436 /* TPI Formatter and Flush Control Register Definitions */
1437 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
1438 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
1439
1440 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
1441 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
1442
1443 /* TPI TRIGGER Register Definitions */
1444 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
1445 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
1446
1447 /* TPI Integration ETM Data Register Definitions (FIFO0) */
1448 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
1449 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
1450
1451 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
1452 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
1453
1454 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
1455 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
1456
1457 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
1458 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
1459
1460 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
1461 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
1462
1463 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
1464 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
1465
1466 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
1467 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
1468
1469 /* TPI ITATBCTR2 Register Definitions */
1470 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
1471 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
1472
1473 /* TPI Integration ITM Data Register Definitions (FIFO1) */
1474 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
1475 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
1476
1477 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
1478 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
1479
1480 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
1481 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
1482
1483 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
1484 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
1485
1486 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
1487 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
1488
1489 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
1490 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
1491
1492 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
1493 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
1494
1495 /* TPI ITATBCTR0 Register Definitions */
1496 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
1497 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
1498
1499 /* TPI Integration Mode Control Register Definitions */
1500 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
1501 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
1502
1503 /* TPI DEVID Register Definitions */
1504 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
1505 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
1506
1507 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
1508 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
1509
1510 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
1511 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
1512
1513 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
1514 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
1515
1516 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
1517 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
1518
1519 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
1520 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
1521
1522 /* TPI DEVTYPE Register Definitions */
1523 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
1524 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
1525
1526 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
1527 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
1528
1529 /*@}*/ /* end of group CMSIS_TPI */
1530
1531
1532 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1533 /**
1534 \ingroup CMSIS_core_register
1535 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1536 \brief Type definitions for the Memory Protection Unit (MPU)
1537 @{
1538 */
1539
1540 /**
1541 \brief Structure type to access the Memory Protection Unit (MPU).
1542 */
1543 typedef struct
1544 {
1545 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1546 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1547 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
1548 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1549 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
1550 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
1551 __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
1552 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
1553 __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
1554 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
1555 __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
1556 uint32_t RESERVED0[1];
1557 union {
1558 __IOM uint32_t MAIR[2];
1559 struct {
1560 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
1561 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
1562 };
1563 };
1564 } MPU_Type;
1565
1566 #define MPU_TYPE_RALIASES 4U
1567
1568 /* MPU Type Register Definitions */
1569 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
1570 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1571
1572 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
1573 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1574
1575 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
1576 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
1577
1578 /* MPU Control Register Definitions */
1579 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
1580 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1581
1582 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
1583 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1584
1585 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
1586 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
1587
1588 /* MPU Region Number Register Definitions */
1589 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1590 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1591
1592 /* MPU Region Base Address Register Definitions */
1593 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: ADDR Position */
1594 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: ADDR Mask */
1595
1596 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
1597 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
1598
1599 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
1600 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
1601
1602 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
1603 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
1604
1605 /* MPU Region Limit Address Register Definitions */
1606 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
1607 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
1608
1609 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
1610 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
1611
1612 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
1613 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
1614
1615 /* MPU Memory Attribute Indirection Register 0 Definitions */
1616 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
1617 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
1618
1619 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
1620 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
1621
1622 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
1623 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
1624
1625 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
1626 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
1627
1628 /* MPU Memory Attribute Indirection Register 1 Definitions */
1629 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
1630 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
1631
1632 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
1633 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
1634
1635 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
1636 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
1637
1638 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
1639 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
1640
1641 /*@} end of group CMSIS_MPU */
1642 #endif
1643
1644
1645 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1646 /**
1647 \ingroup CMSIS_core_register
1648 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
1649 \brief Type definitions for the Security Attribution Unit (SAU)
1650 @{
1651 */
1652
1653 /**
1654 \brief Structure type to access the Security Attribution Unit (SAU).
1655 */
1656 typedef struct
1657 {
1658 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
1659 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
1660 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1661 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
1662 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
1663 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
1664 #else
1665 uint32_t RESERVED0[3];
1666 #endif
1667 __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
1668 __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
1669 } SAU_Type;
1670
1671 /* SAU Control Register Definitions */
1672 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
1673 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
1674
1675 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
1676 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
1677
1678 /* SAU Type Register Definitions */
1679 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
1680 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
1681
1682 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1683 /* SAU Region Number Register Definitions */
1684 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
1685 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
1686
1687 /* SAU Region Base Address Register Definitions */
1688 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
1689 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
1690
1691 /* SAU Region Limit Address Register Definitions */
1692 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
1693 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
1694
1695 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
1696 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
1697
1698 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
1699 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
1700
1701 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
1702
1703 /* Secure Fault Status Register Definitions */
1704 #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
1705 #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
1706
1707 #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
1708 #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
1709
1710 #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
1711 #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
1712
1713 #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
1714 #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
1715
1716 #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
1717 #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
1718
1719 #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
1720 #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
1721
1722 #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
1723 #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
1724
1725 #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
1726 #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
1727
1728 /*@} end of group CMSIS_SAU */
1729 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1730
1731
1732 /**
1733 \ingroup CMSIS_core_register
1734 \defgroup CMSIS_FPU Floating Point Unit (FPU)
1735 \brief Type definitions for the Floating Point Unit (FPU)
1736 @{
1737 */
1738
1739 /**
1740 \brief Structure type to access the Floating Point Unit (FPU).
1741 */
1742 typedef struct
1743 {
1744 uint32_t RESERVED0[1U];
1745 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
1746 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
1747 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
1748 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
1749 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
1750 } FPU_Type;
1751
1752 /* Floating-Point Context Control Register Definitions */
1753 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
1754 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
1755
1756 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
1757 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
1758
1759 #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
1760 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
1761
1762 #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
1763 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
1764
1765 #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
1766 #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
1767
1768 #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
1769 #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
1770
1771 #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
1772 #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
1773
1774 #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
1775 #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
1776
1777 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
1778 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
1779
1780 #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
1781 #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
1782
1783 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
1784 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
1785
1786 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
1787 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
1788
1789 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
1790 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
1791
1792 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
1793 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
1794
1795 #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
1796 #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
1797
1798 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
1799 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
1800
1801 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
1802 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
1803
1804 /* Floating-Point Context Address Register Definitions */
1805 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
1806 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
1807
1808 /* Floating-Point Default Status Control Register Definitions */
1809 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
1810 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
1811
1812 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
1813 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
1814
1815 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
1816 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
1817
1818 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
1819 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
1820
1821 /* Media and FP Feature Register 0 Definitions */
1822 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
1823 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
1824
1825 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
1826 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
1827
1828 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
1829 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
1830
1831 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
1832 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
1833
1834 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
1835 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
1836
1837 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
1838 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
1839
1840 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
1841 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
1842
1843 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
1844 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
1845
1846 /* Media and FP Feature Register 1 Definitions */
1847 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
1848 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
1849
1850 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
1851 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
1852
1853 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
1854 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
1855
1856 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
1857 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
1858
1859 /*@} end of group CMSIS_FPU */
1860
1861
1862 /**
1863 \ingroup CMSIS_core_register
1864 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1865 \brief Type definitions for the Core Debug Registers
1866 @{
1867 */
1868
1869 /**
1870 \brief Structure type to access the Core Debug Register (CoreDebug).
1871 */
1872 typedef struct
1873 {
1874 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1875 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1876 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1877 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1878 uint32_t RESERVED4[1U];
1879 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
1880 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
1881 } CoreDebug_Type;
1882
1883 /* Debug Halting Control and Status Register Definitions */
1884 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
1885 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1886
1887 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
1888 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
1889
1890 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
1891 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1892
1893 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1894 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1895
1896 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
1897 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1898
1899 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
1900 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1901
1902 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
1903 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1904
1905 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
1906 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1907
1908 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1909 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1910
1911 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
1912 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1913
1914 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
1915 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1916
1917 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
1918 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1919
1920 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1921 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1922
1923 /* Debug Core Register Selector Register Definitions */
1924 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
1925 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1926
1927 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
1928 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
1929
1930 /* Debug Exception and Monitor Control Register Definitions */
1931 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
1932 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1933
1934 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
1935 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1936
1937 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
1938 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1939
1940 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
1941 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1942
1943 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
1944 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1945
1946 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
1947 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1948
1949 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
1950 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1951
1952 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
1953 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1954
1955 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
1956 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1957
1958 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
1959 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1960
1961 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1962 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1963
1964 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
1965 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1966
1967 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
1968 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1969
1970 /* Debug Authentication Control Register Definitions */
1971 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
1972 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
1973
1974 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
1975 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
1976
1977 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
1978 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
1979
1980 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
1981 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
1982
1983 /* Debug Security Control and Status Register Definitions */
1984 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
1985 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
1986
1987 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
1988 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
1989
1990 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
1991 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
1992
1993 /*@} end of group CMSIS_CoreDebug */
1994
1995
1996 /**
1997 \ingroup CMSIS_core_register
1998 \defgroup CMSIS_core_bitfield Core register bit field macros
1999 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
2000 @{
2001 */
2002
2003 /**
2004 \brief Mask and shift a bit field value for use in a register bit range.
2005 \param[in] field Name of the register bit field.
2006 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
2007 \return Masked and shifted value.
2008 */
2009 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
2010
2011 /**
2012 \brief Mask and shift a register value to extract a bit filed value.
2013 \param[in] field Name of the register bit field.
2014 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
2015 \return Masked and shifted bit field value.
2016 */
2017 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
2018
2019 /*@} end of group CMSIS_core_bitfield */
2020
2021
2022 /**
2023 \ingroup CMSIS_core_register
2024 \defgroup CMSIS_core_base Core Definitions
2025 \brief Definitions for base addresses, unions, and structures.
2026 @{
2027 */
2028
2029 /* Memory mapping of Core Hardware */
2030 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
2031 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
2032 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
2033 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
2034 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
2035 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
2036 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
2037 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
2038
2039 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
2040 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
2041 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
2042 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
2043 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
2044 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
2045 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
2046 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
2047
2048 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2049 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
2050 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
2051 #endif
2052
2053 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2054 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
2055 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
2056 #endif
2057
2058 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
2059 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
2060
2061 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2062 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
2063 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
2064 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
2065 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
2066 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
2067
2068 #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
2069 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
2070 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
2071 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
2072 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
2073
2074 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2075 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
2076 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
2077 #endif
2078
2079 #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
2080 #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
2081
2082 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2083 /*@} */
2084
2085
2086
2087 /*******************************************************************************
2088 * Hardware Abstraction Layer
2089 Core Function Interface contains:
2090 - Core NVIC Functions
2091 - Core SysTick Functions
2092 - Core Debug Functions
2093 - Core Register Access Functions
2094 ******************************************************************************/
2095 /**
2096 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
2097 */
2098
2099
2100
2101 /* ########################## NVIC functions #################################### */
2102 /**
2103 \ingroup CMSIS_Core_FunctionInterface
2104 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
2105 \brief Functions that manage interrupts and exceptions via the NVIC.
2106 @{
2107 */
2108
2109 #ifdef CMSIS_NVIC_VIRTUAL
2110 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
2111 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
2112 #endif
2113 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
2114 #else
2115 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
2116 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
2117 #define NVIC_EnableIRQ __NVIC_EnableIRQ
2118 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
2119 #define NVIC_DisableIRQ __NVIC_DisableIRQ
2120 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
2121 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
2122 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
2123 #define NVIC_GetActive __NVIC_GetActive
2124 #define NVIC_SetPriority __NVIC_SetPriority
2125 #define NVIC_GetPriority __NVIC_GetPriority
2126 #define NVIC_SystemReset __NVIC_SystemReset
2127 #endif /* CMSIS_NVIC_VIRTUAL */
2128
2129 #ifdef CMSIS_VECTAB_VIRTUAL
2130 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2131 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
2132 #endif
2133 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2134 #else
2135 #define NVIC_SetVector __NVIC_SetVector
2136 #define NVIC_GetVector __NVIC_GetVector
2137 #endif /* (CMSIS_VECTAB_VIRTUAL) */
2138
2139 #define NVIC_USER_IRQ_OFFSET 16
2140
2141
2142
2143 /**
2144 \brief Set Priority Grouping
2145 \details Sets the priority grouping field using the required unlock sequence.
2146 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
2147 Only values from 0..7 are used.
2148 In case of a conflict between priority grouping and available
2149 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2150 \param [in] PriorityGroup Priority grouping field.
2151 */
2152 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
2153 {
2154 uint32_t reg_value;
2155 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2156
2157 reg_value = SCB->AIRCR; /* read old register configuration */
2158 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2159 reg_value = (reg_value |
2160 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2161 (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */
2162 SCB->AIRCR = reg_value;
2163 }
2164
2165
2166 /**
2167 \brief Get Priority Grouping
2168 \details Reads the priority grouping field from the NVIC Interrupt Controller.
2169 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
2170 */
2171 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
2172 {
2173 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2174 }
2175
2176
2177 /**
2178 \brief Enable Interrupt
2179 \details Enables a device specific interrupt in the NVIC interrupt controller.
2180 \param [in] IRQn Device specific interrupt number.
2181 \note IRQn must not be negative.
2182 */
2183 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
2184 {
2185 if ((int32_t)(IRQn) >= 0)
2186 {
2187 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2188 }
2189 }
2190
2191
2192 /**
2193 \brief Get Interrupt Enable status
2194 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
2195 \param [in] IRQn Device specific interrupt number.
2196 \return 0 Interrupt is not enabled.
2197 \return 1 Interrupt is enabled.
2198 \note IRQn must not be negative.
2199 */
2200 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
2201 {
2202 if ((int32_t)(IRQn) >= 0)
2203 {
2204 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2205 }
2206 else
2207 {
2208 return(0U);
2209 }
2210 }
2211
2212
2213 /**
2214 \brief Disable Interrupt
2215 \details Disables a device specific interrupt in the NVIC interrupt controller.
2216 \param [in] IRQn Device specific interrupt number.
2217 \note IRQn must not be negative.
2218 */
2219 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
2220 {
2221 if ((int32_t)(IRQn) >= 0)
2222 {
2223 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2224 __DSB();
2225 __ISB();
2226 }
2227 }
2228
2229
2230 /**
2231 \brief Get Pending Interrupt
2232 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
2233 \param [in] IRQn Device specific interrupt number.
2234 \return 0 Interrupt status is not pending.
2235 \return 1 Interrupt status is pending.
2236 \note IRQn must not be negative.
2237 */
2238 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
2239 {
2240 if ((int32_t)(IRQn) >= 0)
2241 {
2242 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2243 }
2244 else
2245 {
2246 return(0U);
2247 }
2248 }
2249
2250
2251 /**
2252 \brief Set Pending Interrupt
2253 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
2254 \param [in] IRQn Device specific interrupt number.
2255 \note IRQn must not be negative.
2256 */
2257 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
2258 {
2259 if ((int32_t)(IRQn) >= 0)
2260 {
2261 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2262 }
2263 }
2264
2265
2266 /**
2267 \brief Clear Pending Interrupt
2268 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
2269 \param [in] IRQn Device specific interrupt number.
2270 \note IRQn must not be negative.
2271 */
2272 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
2273 {
2274 if ((int32_t)(IRQn) >= 0)
2275 {
2276 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2277 }
2278 }
2279
2280
2281 /**
2282 \brief Get Active Interrupt
2283 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
2284 \param [in] IRQn Device specific interrupt number.
2285 \return 0 Interrupt status is not active.
2286 \return 1 Interrupt status is active.
2287 \note IRQn must not be negative.
2288 */
2289 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
2290 {
2291 if ((int32_t)(IRQn) >= 0)
2292 {
2293 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2294 }
2295 else
2296 {
2297 return(0U);
2298 }
2299 }
2300
2301
2302 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2303 /**
2304 \brief Get Interrupt Target State
2305 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2306 \param [in] IRQn Device specific interrupt number.
2307 \return 0 if interrupt is assigned to Secure
2308 \return 1 if interrupt is assigned to Non Secure
2309 \note IRQn must not be negative.
2310 */
2311 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
2312 {
2313 if ((int32_t)(IRQn) >= 0)
2314 {
2315 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2316 }
2317 else
2318 {
2319 return(0U);
2320 }
2321 }
2322
2323
2324 /**
2325 \brief Set Interrupt Target State
2326 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2327 \param [in] IRQn Device specific interrupt number.
2328 \return 0 if interrupt is assigned to Secure
2329 1 if interrupt is assigned to Non Secure
2330 \note IRQn must not be negative.
2331 */
2332 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
2333 {
2334 if ((int32_t)(IRQn) >= 0)
2335 {
2336 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2337 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2338 }
2339 else
2340 {
2341 return(0U);
2342 }
2343 }
2344
2345
2346 /**
2347 \brief Clear Interrupt Target State
2348 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2349 \param [in] IRQn Device specific interrupt number.
2350 \return 0 if interrupt is assigned to Secure
2351 1 if interrupt is assigned to Non Secure
2352 \note IRQn must not be negative.
2353 */
2354 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
2355 {
2356 if ((int32_t)(IRQn) >= 0)
2357 {
2358 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2359 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2360 }
2361 else
2362 {
2363 return(0U);
2364 }
2365 }
2366 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2367
2368
2369 /**
2370 \brief Set Interrupt Priority
2371 \details Sets the priority of a device specific interrupt or a processor exception.
2372 The interrupt number can be positive to specify a device specific interrupt,
2373 or negative to specify a processor exception.
2374 \param [in] IRQn Interrupt number.
2375 \param [in] priority Priority to set.
2376 \note The priority cannot be set for every processor exception.
2377 */
2378 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
2379 {
2380 if ((int32_t)(IRQn) >= 0)
2381 {
2382 NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2383 }
2384 else
2385 {
2386 SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2387 }
2388 }
2389
2390
2391 /**
2392 \brief Get Interrupt Priority
2393 \details Reads the priority of a device specific interrupt or a processor exception.
2394 The interrupt number can be positive to specify a device specific interrupt,
2395 or negative to specify a processor exception.
2396 \param [in] IRQn Interrupt number.
2397 \return Interrupt Priority.
2398 Value is aligned automatically to the implemented priority bits of the microcontroller.
2399 */
2400 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
2401 {
2402
2403 if ((int32_t)(IRQn) >= 0)
2404 {
2405 return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2406 }
2407 else
2408 {
2409 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2410 }
2411 }
2412
2413
2414 /**
2415 \brief Encode Priority
2416 \details Encodes the priority for an interrupt with the given priority group,
2417 preemptive priority value, and subpriority value.
2418 In case of a conflict between priority grouping and available
2419 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2420 \param [in] PriorityGroup Used priority group.
2421 \param [in] PreemptPriority Preemptive priority value (starting from 0).
2422 \param [in] SubPriority Subpriority value (starting from 0).
2423 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
2424 */
2425 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
2426 {
2427 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2428 uint32_t PreemptPriorityBits;
2429 uint32_t SubPriorityBits;
2430
2431 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2432 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2433
2434 return (
2435 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
2436 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
2437 );
2438 }
2439
2440
2441 /**
2442 \brief Decode Priority
2443 \details Decodes an interrupt priority value with a given priority group to
2444 preemptive priority value and subpriority value.
2445 In case of a conflict between priority grouping and available
2446 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
2447 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
2448 \param [in] PriorityGroup Used priority group.
2449 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
2450 \param [out] pSubPriority Subpriority value (starting from 0).
2451 */
2452 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
2453 {
2454 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2455 uint32_t PreemptPriorityBits;
2456 uint32_t SubPriorityBits;
2457
2458 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2459 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2460
2461 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
2462 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
2463 }
2464
2465
2466 /**
2467 \brief Set Interrupt Vector
2468 \details Sets an interrupt vector in SRAM based interrupt vector table.
2469 The interrupt number can be positive to specify a device specific interrupt,
2470 or negative to specify a processor exception.
2471 VTOR must been relocated to SRAM before.
2472 \param [in] IRQn Interrupt number
2473 \param [in] vector Address of interrupt handler function
2474 */
2475 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
2476 {
2477 uint32_t *vectors = (uint32_t *)SCB->VTOR;
2478 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
2479 }
2480
2481
2482 /**
2483 \brief Get Interrupt Vector
2484 \details Reads an interrupt vector from interrupt vector table.
2485 The interrupt number can be positive to specify a device specific interrupt,
2486 or negative to specify a processor exception.
2487 \param [in] IRQn Interrupt number.
2488 \return Address of interrupt handler function
2489 */
2490 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
2491 {
2492 uint32_t *vectors = (uint32_t *)SCB->VTOR;
2493 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
2494 }
2495
2496
2497 /**
2498 \brief System Reset
2499 \details Initiates a system reset request to reset the MCU.
2500 */
2501 __STATIC_INLINE void __NVIC_SystemReset(void)
2502 {
2503 __DSB(); /* Ensure all outstanding memory accesses included
2504 buffered write are completed before reset */
2505 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2506 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
2507 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
2508 __DSB(); /* Ensure completion of memory access */
2509
2510 for(;;) /* wait until reset */
2511 {
2512 __NOP();
2513 }
2514 }
2515
2516 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2517 /**
2518 \brief Set Priority Grouping (non-secure)
2519 \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
2520 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
2521 Only values from 0..7 are used.
2522 In case of a conflict between priority grouping and available
2523 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2524 \param [in] PriorityGroup Priority grouping field.
2525 */
2526 __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
2527 {
2528 uint32_t reg_value;
2529 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2530
2531 reg_value = SCB_NS->AIRCR; /* read old register configuration */
2532 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2533 reg_value = (reg_value |
2534 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2535 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
2536 SCB_NS->AIRCR = reg_value;
2537 }
2538
2539
2540 /**
2541 \brief Get Priority Grouping (non-secure)
2542 \details Reads the priority grouping field from the non-secure NVIC when in secure state.
2543 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
2544 */
2545 __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
2546 {
2547 return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2548 }
2549
2550
2551 /**
2552 \brief Enable Interrupt (non-secure)
2553 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
2554 \param [in] IRQn Device specific interrupt number.
2555 \note IRQn must not be negative.
2556 */
2557 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
2558 {
2559 if ((int32_t)(IRQn) >= 0)
2560 {
2561 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2562 }
2563 }
2564
2565
2566 /**
2567 \brief Get Interrupt Enable status (non-secure)
2568 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
2569 \param [in] IRQn Device specific interrupt number.
2570 \return 0 Interrupt is not enabled.
2571 \return 1 Interrupt is enabled.
2572 \note IRQn must not be negative.
2573 */
2574 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
2575 {
2576 if ((int32_t)(IRQn) >= 0)
2577 {
2578 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2579 }
2580 else
2581 {
2582 return(0U);
2583 }
2584 }
2585
2586
2587 /**
2588 \brief Disable Interrupt (non-secure)
2589 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
2590 \param [in] IRQn Device specific interrupt number.
2591 \note IRQn must not be negative.
2592 */
2593 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
2594 {
2595 if ((int32_t)(IRQn) >= 0)
2596 {
2597 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2598 }
2599 }
2600
2601
2602 /**
2603 \brief Get Pending Interrupt (non-secure)
2604 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
2605 \param [in] IRQn Device specific interrupt number.
2606 \return 0 Interrupt status is not pending.
2607 \return 1 Interrupt status is pending.
2608 \note IRQn must not be negative.
2609 */
2610 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
2611 {
2612 if ((int32_t)(IRQn) >= 0)
2613 {
2614 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2615 }
2616 else
2617 {
2618 return(0U);
2619 }
2620 }
2621
2622
2623 /**
2624 \brief Set Pending Interrupt (non-secure)
2625 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
2626 \param [in] IRQn Device specific interrupt number.
2627 \note IRQn must not be negative.
2628 */
2629 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
2630 {
2631 if ((int32_t)(IRQn) >= 0)
2632 {
2633 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2634 }
2635 }
2636
2637
2638 /**
2639 \brief Clear Pending Interrupt (non-secure)
2640 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
2641 \param [in] IRQn Device specific interrupt number.
2642 \note IRQn must not be negative.
2643 */
2644 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
2645 {
2646 if ((int32_t)(IRQn) >= 0)
2647 {
2648 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2649 }
2650 }
2651
2652
2653 /**
2654 \brief Get Active Interrupt (non-secure)
2655 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
2656 \param [in] IRQn Device specific interrupt number.
2657 \return 0 Interrupt status is not active.
2658 \return 1 Interrupt status is active.
2659 \note IRQn must not be negative.
2660 */
2661 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
2662 {
2663 if ((int32_t)(IRQn) >= 0)
2664 {
2665 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2666 }
2667 else
2668 {
2669 return(0U);
2670 }
2671 }
2672
2673
2674 /**
2675 \brief Set Interrupt Priority (non-secure)
2676 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
2677 The interrupt number can be positive to specify a device specific interrupt,
2678 or negative to specify a processor exception.
2679 \param [in] IRQn Interrupt number.
2680 \param [in] priority Priority to set.
2681 \note The priority cannot be set for every non-secure processor exception.
2682 */
2683 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
2684 {
2685 if ((int32_t)(IRQn) >= 0)
2686 {
2687 NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2688 }
2689 else
2690 {
2691 SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2692 }
2693 }
2694
2695
2696 /**
2697 \brief Get Interrupt Priority (non-secure)
2698 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
2699 The interrupt number can be positive to specify a device specific interrupt,
2700 or negative to specify a processor exception.
2701 \param [in] IRQn Interrupt number.
2702 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
2703 */
2704 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
2705 {
2706
2707 if ((int32_t)(IRQn) >= 0)
2708 {
2709 return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2710 }
2711 else
2712 {
2713 return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2714 }
2715 }
2716 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
2717
2718 /*@} end of CMSIS_Core_NVICFunctions */
2719
2720 /* ########################## MPU functions #################################### */
2721
2722 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2723
2724 #include "mpu_armv8.h"
2725
2726 #endif
2727
2728 /* ########################## FPU functions #################################### */
2729 /**
2730 \ingroup CMSIS_Core_FunctionInterface
2731 \defgroup CMSIS_Core_FpuFunctions FPU Functions
2732 \brief Function that provides FPU type.
2733 @{
2734 */
2735
2736 /**
2737 \brief get FPU type
2738 \details returns the FPU type
2739 \returns
2740 - \b 0: No FPU
2741 - \b 1: Single precision FPU
2742 - \b 2: Double + Single precision FPU
2743 */
2744 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
2745 {
2746 uint32_t mvfr0;
2747
2748 mvfr0 = FPU->MVFR0;
2749 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
2750 {
2751 return 2U; /* Double + Single precision FPU */
2752 }
2753 else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
2754 {
2755 return 1U; /* Single precision FPU */
2756 }
2757 else
2758 {
2759 return 0U; /* No FPU */
2760 }
2761 }
2762
2763
2764 /*@} end of CMSIS_Core_FpuFunctions */
2765
2766
2767
2768 /* ########################## SAU functions #################################### */
2769 /**
2770 \ingroup CMSIS_Core_FunctionInterface
2771 \defgroup CMSIS_Core_SAUFunctions SAU Functions
2772 \brief Functions that configure the SAU.
2773 @{
2774 */
2775
2776 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2777
2778 /**
2779 \brief Enable SAU
2780 \details Enables the Security Attribution Unit (SAU).
2781 */
2782 __STATIC_INLINE void TZ_SAU_Enable(void)
2783 {
2784 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
2785 }
2786
2787
2788
2789 /**
2790 \brief Disable SAU
2791 \details Disables the Security Attribution Unit (SAU).
2792 */
2793 __STATIC_INLINE void TZ_SAU_Disable(void)
2794 {
2795 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
2796 }
2797
2798 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2799
2800 /*@} end of CMSIS_Core_SAUFunctions */
2801
2802
2803
2804
2805 /* ################################## SysTick function ############################################ */
2806 /**
2807 \ingroup CMSIS_Core_FunctionInterface
2808 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
2809 \brief Functions that configure the System.
2810 @{
2811 */
2812
2813 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2814
2815 /**
2816 \brief System Tick Configuration
2817 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
2818 Counter is in free running mode to generate periodic interrupts.
2819 \param [in] ticks Number of ticks between two interrupts.
2820 \return 0 Function succeeded.
2821 \return 1 Function failed.
2822 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2823 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
2824 must contain a vendor-specific implementation of this function.
2825 */
2826 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2827 {
2828 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2829 {
2830 return (1UL); /* Reload value impossible */
2831 }
2832
2833 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2834 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2835 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2836 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2837 SysTick_CTRL_TICKINT_Msk |
2838 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2839 return (0UL); /* Function successful */
2840 }
2841
2842 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2843 /**
2844 \brief System Tick Configuration (non-secure)
2845 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
2846 Counter is in free running mode to generate periodic interrupts.
2847 \param [in] ticks Number of ticks between two interrupts.
2848 \return 0 Function succeeded.
2849 \return 1 Function failed.
2850 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2851 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
2852 must contain a vendor-specific implementation of this function.
2853
2854 */
2855 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
2856 {
2857 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2858 {
2859 return (1UL); /* Reload value impossible */
2860 }
2861
2862 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2863 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2864 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
2865 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2866 SysTick_CTRL_TICKINT_Msk |
2867 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2868 return (0UL); /* Function successful */
2869 }
2870 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2871
2872 #endif
2873
2874 /*@} end of CMSIS_Core_SysTickFunctions */
2875
2876
2877
2878 /* ##################################### Debug In/Output function ########################################### */
2879 /**
2880 \ingroup CMSIS_Core_FunctionInterface
2881 \defgroup CMSIS_core_DebugFunctions ITM Functions
2882 \brief Functions that access the ITM debug interface.
2883 @{
2884 */
2885
2886 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
2887 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
2888
2889
2890 /**
2891 \brief ITM Send Character
2892 \details Transmits a character via the ITM channel 0, and
2893 \li Just returns when no debugger is connected that has booked the output.
2894 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
2895 \param [in] ch Character to transmit.
2896 \returns Character to transmit.
2897 */
2898 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
2899 {
2900 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
2901 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
2902 {
2903 while (ITM->PORT[0U].u32 == 0UL)
2904 {
2905 __NOP();
2906 }
2907 ITM->PORT[0U].u8 = (uint8_t)ch;
2908 }
2909 return (ch);
2910 }
2911
2912
2913 /**
2914 \brief ITM Receive Character
2915 \details Inputs a character via the external variable \ref ITM_RxBuffer.
2916 \return Received character.
2917 \return -1 No character pending.
2918 */
2919 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
2920 {
2921 int32_t ch = -1; /* no character available */
2922
2923 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
2924 {
2925 ch = ITM_RxBuffer;
2926 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
2927 }
2928
2929 return (ch);
2930 }
2931
2932
2933 /**
2934 \brief ITM Check Character
2935 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
2936 \return 0 No character available.
2937 \return 1 Character available.
2938 */
2939 __STATIC_INLINE int32_t ITM_CheckChar (void)
2940 {
2941
2942 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
2943 {
2944 return (0); /* no character available */
2945 }
2946 else
2947 {
2948 return (1); /* character available */
2949 }
2950 }
2951
2952 /*@} end of CMSIS_core_DebugFunctions */
2953
2954
2955
2956
2957 #ifdef __cplusplus
2958 }
2959 #endif
2960
2961 #endif /* __CORE_CM33_H_DEPENDANT */
2962
2963 #endif /* __CMSIS_GENERIC */