1 /* ----------------------------------------------------------------------
2 * Project: CMSIS DSP Library
3 * Title: arm_power_q31.c
4 * Description: Sum of the squares of the elements of a Q31 vector
6 * $Date: 27. January 2017
9 * Target Processor: Cortex-M cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
16 * Licensed under the Apache License, Version 2.0 (the License); you may
17 * not use this file except in compliance with the License.
18 * You may obtain a copy of the License at
20 * www.apache.org/licenses/LICENSE-2.0
22 * Unless required by applicable law or agreed to in writing, software
23 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25 * See the License for the specific language governing permissions and
26 * limitations under the License.
41 * @brief Sum of the squares of the elements of a Q31 vector.
42 * @param[in] *pSrc points to the input vector
43 * @param[in] blockSize length of the input vector
44 * @param[out] *pResult sum of the squares value returned here
48 * <b>Scaling and Overflow Behavior:</b>
51 * The function is implemented using a 64-bit internal accumulator.
52 * The input is represented in 1.31 format.
53 * Intermediate multiplication yields a 2.62 format, and this
54 * result is truncated to 2.48 format by discarding the lower 14 bits.
55 * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format.
56 * With 15 guard bits in the accumulator, there is no risk of overflow, and the
57 * full precision of the intermediate multiplication is preserved.
58 * Finally, the return result is in 16.48 format.
67 q63_t sum
= 0; /* Temporary result storage */
69 uint32_t blkCnt
; /* loop counter */
72 #if defined (ARM_MATH_DSP)
73 /* Run the below code for Cortex-M4 and Cortex-M3 */
76 blkCnt
= blockSize
>> 2U;
78 /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
79 ** a second loop below computes the remaining 1 to 3 samples. */
82 /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
83 /* Compute Power then shift intermediate results by 14 bits to maintain 16.48 format and then store the result in a temporary variable sum, providing 15 guard bits. */
85 sum
+= ((q63_t
) in
* in
) >> 14U;
88 sum
+= ((q63_t
) in
* in
) >> 14U;
91 sum
+= ((q63_t
) in
* in
) >> 14U;
94 sum
+= ((q63_t
) in
* in
) >> 14U;
96 /* Decrement the loop counter */
100 /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
101 ** No loop unrolling is used. */
102 blkCnt
= blockSize
% 0x4U
;
105 /* Run the below code for Cortex-M0 */
107 /* Loop over blockSize number of values */
110 #endif /* #if defined (ARM_MATH_DSP) */
114 /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
115 /* Compute Power and then store the result in a temporary variable, sum. */
117 sum
+= ((q63_t
) in
* in
) >> 14U;
119 /* Decrement the loop counter */
123 /* Store the results in 16.48 format */
128 * @} end of power group