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Merge pull request #11270 from haslinghuis/rename_attr
[betaflight.git] / lib / main / STM32F1 / Drivers / STM32F1xx_HAL_Driver / Inc / stm32f1xx_hal_can.h
blob1e2e755b2e1170e58a6b157dc9b950a773570cb8
1 /**
2 ******************************************************************************
3 * @file stm32f1xx_hal_can.h
4 * @author MCD Application Team
5 * @version V1.1.1
6 * @date 12-May-2017
7 * @brief Header file of CAN HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F1xx_HAL_CAN_H
40 #define __STM32F1xx_HAL_CAN_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
47 defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
48
49 /* Includes ------------------------------------------------------------------*/
50 #include "stm32f1xx_hal_def.h"
51
52 /** @addtogroup STM32F1xx_HAL_Driver
53 * @{
54 */
55
56 /** @addtogroup CAN
57 * @{
58 */
59
60 /* Exported types ------------------------------------------------------------*/
61 /** @defgroup CAN_Exported_Types CAN Exported Types
62 * @{
63 */
64
65 /**
66 * @brief HAL State structures definition
67 */
68 typedef enum
69 {
70 HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
71 HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
72 HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */
73 HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */
74 HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */
75 HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */
76 HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */
77 HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */
78 HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */
79 HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */
80 HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */
81 HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */
82
83 }HAL_CAN_StateTypeDef;
84
85 /**
86 * @brief CAN init structure definition
87 */
88 typedef struct
89 {
90 uint32_t Prescaler; /*!< Specifies the length of a time quantum.
91 This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
92
93 uint32_t Mode; /*!< Specifies the CAN operating mode.
94 This parameter can be a value of @ref CAN_operating_mode */
95
96 uint32_t SJW; /*!< Specifies the maximum number of time quanta
97 the CAN hardware is allowed to lengthen or
98 shorten a bit to perform resynchronization.
99 This parameter can be a value of @ref CAN_synchronisation_jump_width */
100
101 uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
102 This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
103
104 uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
105 This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
106
107 uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
108 This parameter can be set to ENABLE or DISABLE. */
109
110 uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
111 This parameter can be set to ENABLE or DISABLE */
112
113 uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
114 This parameter can be set to ENABLE or DISABLE */
115
116 uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
117 This parameter can be set to ENABLE or DISABLE */
118
119 uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode.
120 This parameter can be set to ENABLE or DISABLE */
121
122 uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
123 This parameter can be set to ENABLE or DISABLE */
124 }CAN_InitTypeDef;
125
126 /**
127 * @brief CAN Tx message structure definition
128 */
129 typedef struct
130 {
131 uint32_t StdId; /*!< Specifies the standard identifier.
132 This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
133
134 uint32_t ExtId; /*!< Specifies the extended identifier.
135 This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
136
137 uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
138 This parameter can be a value of @ref CAN_Identifier_Type */
139
140 uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
141 This parameter can be a value of @ref CAN_remote_transmission_request */
142
143 uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
144 This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
145
146 uint8_t Data[8]; /*!< Contains the data to be transmitted.
147 This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
148
149 }CanTxMsgTypeDef;
150
151 /**
152 * @brief CAN Rx message structure definition
153 */
154 typedef struct
155 {
156 uint32_t StdId; /*!< Specifies the standard identifier.
157 This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
158
159 uint32_t ExtId; /*!< Specifies the extended identifier.
160 This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
161
162 uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
163 This parameter can be a value of @ref CAN_Identifier_Type */
164
165 uint32_t RTR; /*!< Specifies the type of frame for the received message.
166 This parameter can be a value of @ref CAN_remote_transmission_request */
167
168 uint32_t DLC; /*!< Specifies the length of the frame that will be received.
169 This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
170
171 uint8_t Data[8]; /*!< Contains the data to be received.
172 This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
173
174 uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
175 This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
176
177 uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
178 This parameter can be CAN_FIFO0 or CAN_FIFO1 */
179
180 }CanRxMsgTypeDef;
181
182 /**
183 * @brief CAN handle Structure definition
184 */
185 typedef struct
186 {
187 CAN_TypeDef *Instance; /*!< Register base address */
188
189 CAN_InitTypeDef Init; /*!< CAN required parameters */
190
191 CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
192
193 CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */
194
195 CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */
196
197 __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
198
199 HAL_LockTypeDef Lock; /*!< CAN locking object */
200
201 __IO uint32_t ErrorCode; /*!< CAN Error code */
202
203 }CAN_HandleTypeDef;
204
205 /**
206 * @}
207 */
208
209 /* Exported constants --------------------------------------------------------*/
210 /** @defgroup CAN_Exported_Constants CAN Exported Constants
211 * @{
212 */
213
214 /** @defgroup CAN_Error_Code CAN Error Code
215 * @{
216 */
217 #define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */
218 #define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */
219 #define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */
220 #define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */
221 #define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */
222 #define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */
223 #define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */
224 #define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */
225 #define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */
226 #define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */
227 #define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */
228 #define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */
229 #define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */
230 /**
231 * @}
232 */
233
234 /** @defgroup CAN_InitStatus CAN initialization Status
235 * @{
236 */
237 #define CAN_INITSTATUS_FAILED 0x00000000U /*!< CAN initialization failed */
238 #define CAN_INITSTATUS_SUCCESS 0x00000001U /*!< CAN initialization OK */
239 /**
240 * @}
241 */
242
243 /** @defgroup CAN_operating_mode CAN Operating Mode
244 * @{
245 */
246 #define CAN_MODE_NORMAL 0x00000000U /*!< Normal mode */
247 #define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
248 #define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
249 #define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
250 /**
251 * @}
252 */
253
254 /** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
255 * @{
256 */
257 #define CAN_SJW_1TQ 0x00000000U /*!< 1 time quantum */
258 #define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
259 #define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
260 #define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
261 /**
262 * @}
263 */
264
265 /** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
266 * @{
267 */
268 #define CAN_BS1_1TQ 0x00000000U /*!< 1 time quantum */
269 #define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
270 #define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
271 #define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
272 #define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
273 #define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
274 #define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
275 #define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
276 #define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
277 #define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
278 #define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
279 #define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
280 #define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
281 #define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
282 #define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
283 #define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
284 /**
285 * @}
286 */
287
288 /** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2
289 * @{
290 */
291 #define CAN_BS2_1TQ 0x00000000U /*!< 1 time quantum */
292 #define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
293 #define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
294 #define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
295 #define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
296 #define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
297 #define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
298 #define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
299 /**
300 * @}
301 */
302
303 /** @defgroup CAN_filter_mode CAN Filter Mode
304 * @{
305 */
306 #define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
307 #define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
308 /**
309 * @}
310 */
311
312 /** @defgroup CAN_filter_scale CAN Filter Scale
313 * @{
314 */
315 #define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
316 #define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
317 /**
318 * @}
319 */
320
321 /** @defgroup CAN_filter_FIFO CAN Filter FIFO
322 * @{
323 */
324 #define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
325 #define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
326 /**
327 * @}
328 */
329
330 /** @defgroup CAN_Identifier_Type CAN Identifier Type
331 * @{
332 */
333 #define CAN_ID_STD 0x00000000U /*!< Standard Id */
334 #define CAN_ID_EXT 0x00000004U /*!< Extended Id */
335 /**
336 * @}
337 */
338
339 /** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
340 * @{
341 */
342 #define CAN_RTR_DATA 0x00000000U /*!< Data frame */
343 #define CAN_RTR_REMOTE 0x00000002U /*!< Remote frame */
344 /**
345 * @}
346 */
347
348 /** @defgroup CAN_transmit_constants CAN Transmit Constants
349 * @{
350 */
351 #define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
352 /**
353 * @}
354 */
355
356 /** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number
357 * @{
358 */
359 #define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
360 #define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
361 /**
362 * @}
363 */
364
365 /** @defgroup CAN_flags CAN Flags
366 * @{
367 */
368 /* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
369 and CAN_ClearFlag() functions. */
370 /* If the flag is 0x1XXXXXXX, it means that it can only be used with
371 CAN_GetFlagStatus() function. */
372
373 /* Transmit Flags */
374 #define CAN_FLAG_RQCP0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP0_BIT_POSITION)) /*!< Request MailBox0 flag */
375 #define CAN_FLAG_RQCP1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP1_BIT_POSITION)) /*!< Request MailBox1 flag */
376 #define CAN_FLAG_RQCP2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP2_BIT_POSITION)) /*!< Request MailBox2 flag */
377 #define CAN_FLAG_TXOK0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK0_BIT_POSITION)) /*!< Transmission OK MailBox0 flag */
378 #define CAN_FLAG_TXOK1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK1_BIT_POSITION)) /*!< Transmission OK MailBox1 flag */
379 #define CAN_FLAG_TXOK2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP0_BIT_POSITION)) /*!< Transmission OK MailBox2 flag */
380 #define CAN_FLAG_TME0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME0_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */
381 #define CAN_FLAG_TME1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME1_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */
382 #define CAN_FLAG_TME2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME2_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */
383
384 /* Receive Flags */
385 #define CAN_FLAG_FF0 ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FF0_BIT_POSITION)) /*!< FIFO 0 Full flag */
386 #define CAN_FLAG_FOV0 ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FOV0_BIT_POSITION)) /*!< FIFO 0 Overrun flag */
387
388 #define CAN_FLAG_FF1 ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FF1_BIT_POSITION)) /*!< FIFO 1 Full flag */
389 #define CAN_FLAG_FOV1 ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FOV1_BIT_POSITION)) /*!< FIFO 1 Overrun flag */
390
391 /* Operating Mode Flags */
392 #define CAN_FLAG_WKU ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_WKU_BIT_POSITION)) /*!< Wake up flag */
393 #define CAN_FLAG_SLAK ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAK_BIT_POSITION)) /*!< Sleep acknowledge flag */
394 #define CAN_FLAG_SLAKI ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAKI_BIT_POSITION)) /*!< Sleep acknowledge flag */
395
396 /* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
397 In this case the SLAK bit can be polled.*/
398
399 /* Error Flags */
400 #define CAN_FLAG_EWG ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EWG_BIT_POSITION)) /*!< Error warning flag */
401 #define CAN_FLAG_EPV ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EPV_BIT_POSITION)) /*!< Error passive flag */
402 #define CAN_FLAG_BOF ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_BOF_BIT_POSITION)) /*!< Bus-Off flag */
403
404 /**
405 * @}
406 */
407
408 /** @defgroup CAN_Interrupts CAN Interrupts
409 * @{
410 */
411 #define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
412
413 /* Receive Interrupts */
414 #define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
415 #define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
416 #define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
417 #define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
418 #define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
419 #define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
420
421 /* Operating Mode Interrupts */
422 #define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
423 #define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
424
425 /* Error Interrupts */
426 #define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
427 #define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
428 #define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
429 #define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
430 #define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
431 /**
432 * @}
433 */
434
435 /**
436 * @}
437 */
438
439 /** @defgroup CAN_Private_Constants CAN Private Constants
440 * @{
441 */
442
443 /* CAN intermediate shift values used for CAN flags */
444 #define TSR_REGISTER_INDEX 0x5U
445 #define RF0R_REGISTER_INDEX 0x2U
446 #define RF1R_REGISTER_INDEX 0x4U
447 #define MSR_REGISTER_INDEX 0x1U
448 #define ESR_REGISTER_INDEX 0x3U
449
450 /* CAN flags bits position into their respective register (TSR, RF0R, RF1R or MSR regsiters) */
451 /* Transmit Flags */
452 #define CAN_TSR_RQCP0_BIT_POSITION 0x00000000U
453 #define CAN_TSR_RQCP1_BIT_POSITION 0x00000008U
454 #define CAN_TSR_RQCP2_BIT_POSITION 0x00000010U
455 #define CAN_TSR_TXOK0_BIT_POSITION 0x00000001U
456 #define CAN_TSR_TXOK1_BIT_POSITION 0x00000009U
457 #define CAN_TSR_TXOK2_BIT_POSITION 0x00000011U
458 #define CAN_TSR_TME0_BIT_POSITION 0x0000001AU
459 #define CAN_TSR_TME1_BIT_POSITION 0x0000001BU
460 #define CAN_TSR_TME2_BIT_POSITION 0x0000001CU
461
462 /* Receive Flags */
463 #define CAN_RF0R_FF0_BIT_POSITION 0x00000003U
464 #define CAN_RF0R_FOV0_BIT_POSITION 0x00000004U
465
466 #define CAN_RF1R_FF1_BIT_POSITION 0x00000003U
467 #define CAN_RF1R_FOV1_BIT_POSITION 0x00000004U
468
469 /* Operating Mode Flags */
470 #define CAN_MSR_WKU_BIT_POSITION 0x00000003U
471 #define CAN_MSR_SLAK_BIT_POSITION 0x00000001U
472 #define CAN_MSR_SLAKI_BIT_POSITION 0x00000004U
473
474 /* Error Flags */
475 #define CAN_ESR_EWG_BIT_POSITION 0x00000000U
476 #define CAN_ESR_EPV_BIT_POSITION 0x00000001U
477 #define CAN_ESR_BOF_BIT_POSITION 0x00000002U
478
479 /* Mask used by macro to get/clear CAN flags*/
480 #define CAN_FLAG_MASK 0x000000FFU
481
482 /* Mailboxes definition */
483 #define CAN_TXMAILBOX_0 ((uint8_t)0x00)
484 #define CAN_TXMAILBOX_1 ((uint8_t)0x01)
485 #define CAN_TXMAILBOX_2 ((uint8_t)0x02)
486 /**
487 * @}
488 */
489
490 /* Exported macros -----------------------------------------------------------*/
491 /** @defgroup CAN_Exported_Macros CAN Exported Macros
492 * @{
493 */
494
495 /** @brief Reset CAN handle state
496 * @param __HANDLE__: CAN handle.
497 * @retval None
498 */
499 #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
500
501 /**
502 * @brief Enable the specified CAN interrupts
503 * @param __HANDLE__: CAN handle.
504 * @param __INTERRUPT__: CAN Interrupt.
505 * This parameter can be one of the following values:
506 * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
507 * @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
508 * @arg CAN_IT_FF0 : FIFO 0 full interrupt
509 * @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
510 * @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
511 * @arg CAN_IT_FF1 : FIFO 1 full interrupt
512 * @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
513 * @arg CAN_IT_WKU : Wake-up interrupt
514 * @arg CAN_IT_SLK : Sleep acknowledge interrupt
515 * @arg CAN_IT_EWG : Error warning interrupt
516 * @arg CAN_IT_EPV : Error passive interrupt
517 * @arg CAN_IT_BOF : Bus-off interrupt
518 * @arg CAN_IT_LEC : Last error code interrupt
519 * @arg CAN_IT_ERR : Error Interrupt
520 * @retval None.
521 */
522 #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
523
524 /**
525 * @brief Disable the specified CAN interrupts
526 * @param __HANDLE__: CAN handle.
527 * @param __INTERRUPT__: CAN Interrupt.
528 * This parameter can be one of the following values:
529 * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
530 * @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
531 * @arg CAN_IT_FF0 : FIFO 0 full interrupt
532 * @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
533 * @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
534 * @arg CAN_IT_FF1 : FIFO 1 full interrupt
535 * @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
536 * @arg CAN_IT_WKU : Wake-up interrupt
537 * @arg CAN_IT_SLK : Sleep acknowledge interrupt
538 * @arg CAN_IT_EWG : Error warning interrupt
539 * @arg CAN_IT_EPV : Error passive interrupt
540 * @arg CAN_IT_BOF : Bus-off interrupt
541 * @arg CAN_IT_LEC : Last error code interrupt
542 * @arg CAN_IT_ERR : Error Interrupt
543 * @retval None.
544 */
545 #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
546
547 /**
548 * @brief Return the number of pending received messages.
549 * @param __HANDLE__: CAN handle.
550 * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
551 * @retval The number of pending message.
552 */
553 #define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
554 ((uint8_t)((__HANDLE__)->Instance->RF0R & 0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & 0x03U)))
555
556 /** @brief Check whether the specified CAN flag is set or not.
557 * @param __HANDLE__: specifies the CAN Handle.
558 * @param __FLAG__: specifies the flag to check.
559 * This parameter can be one of the following values:
560 * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
561 * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
562 * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
563 * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
564 * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
565 * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
566 * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
567 * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
568 * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
569 * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
570 * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
571 * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
572 * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
573 * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
574 * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
575 * @arg CAN_FLAG_WKU: Wake up Flag
576 * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
577 * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
578 * @arg CAN_FLAG_EWG: Error Warning Flag
579 * @arg CAN_FLAG_EPV: Error Passive Flag
580 * @arg CAN_FLAG_BOF: Bus-Off Flag
581 * @retval The new state of __FLAG__ (TRUE or FALSE).
582 */
583 #define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
584 ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
585 (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
586 (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
587 (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
588 ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
589
590 /** @brief Clear the specified CAN pending flag.
591 * @param __HANDLE__: specifies the CAN Handle.
592 * @param __FLAG__: specifies the flag to check.
593 * This parameter can be one of the following values:
594 * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
595 * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
596 * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
597 * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
598 * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
599 * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
600 * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
601 * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
602 * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
603 * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
604 * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
605 * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
606 * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
607 * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
608 * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
609 * @arg CAN_FLAG_WKU: Wake up Flag
610 * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
611 * @retval The new state of __FLAG__ (TRUE or FALSE).
612 */
613 #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
614 ((((__FLAG__) >> 8U) == TSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
615 (((__FLAG__) >> 8U) == RF0R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
616 (((__FLAG__) >> 8U) == RF1R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
617 (((__FLAG__) >> 8U) == MSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
618
619 /** @brief Check if the specified CAN interrupt source is enabled or disabled.
620 * @param __HANDLE__: specifies the CAN Handle.
621 * @param __INTERRUPT__: specifies the CAN interrupt source to check.
622 * This parameter can be one of the following values:
623 * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
624 * @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
625 * @arg CAN_IT_FF0 : FIFO 0 full interrupt
626 * @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
627 * @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
628 * @arg CAN_IT_FF1 : FIFO 1 full interrupt
629 * @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
630 * @arg CAN_IT_WKU : Wake-up interrupt
631 * @arg CAN_IT_SLK : Sleep acknowledge interrupt
632 * @arg CAN_IT_EWG : Error warning interrupt
633 * @arg CAN_IT_EPV : Error passive interrupt
634 * @arg CAN_IT_BOF : Bus-off interrupt
635 * @arg CAN_IT_LEC : Last error code interrupt
636 * @arg CAN_IT_ERR : Error Interrupt
637 * @retval The new state of __IT__ (TRUE or FALSE).
638 */
639 #define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
640
641 /**
642 * @brief Check the transmission status of a CAN Frame.
643 * @param __HANDLE__: specifies the CAN Handle.
644 * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
645 * @retval The new status of transmission (TRUE or FALSE).
646 */
647 #define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
648 (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TME0)) :\
649 ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TME1)) :\
650 ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TME2)))
651
652 /**
653 * @brief Release the specified receive FIFO.
654 * @param __HANDLE__: CAN handle.
655 * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
656 * @retval None.
657 */
658 #define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
659 ((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1))
660
661 /**
662 * @brief Cancel a transmit request.
663 * @param __HANDLE__: specifies the CAN Handle.
664 * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
665 * @retval None.
666 */
667 #define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
668 (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\
669 ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\
670 ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2))
671
672 /**
673 * @brief Enable or disables the DBG Freeze for CAN.
674 * @param __HANDLE__: specifies the CAN Handle.
675 * @param __NEWSTATE__: new state of the CAN peripheral.
676 * This parameter can be: ENABLE (CAN reception/transmission is frozen
677 * during debug. Reception FIFOs can still be accessed/controlled normally)
678 * or DISABLE (CAN is working during debug).
679 * @retval None
680 */
681 #define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
682 ((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
683
684 /**
685 * @}
686 */
687
688 /* Include CAN HAL Extension module */
689 #include "stm32f1xx_hal_can_ex.h"
690
691 /* Exported functions --------------------------------------------------------*/
692 /** @addtogroup CAN_Exported_Functions
693 * @{
694 */
695
696 /** @addtogroup CAN_Exported_Functions_Group1
697 * @brief Initialization and Configuration functions
698 * @{
699 */
700 /* Initialization and de-initialization functions *****************************/
701 HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
702 HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
703 HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
704 void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
705 void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
706 /**
707 * @}
708 */
709
710 /** @addtogroup CAN_Exported_Functions_Group2
711 * @brief I/O operation functions
712 * @{
713 */
714 /* I/O operation functions *****************************************************/
715 HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
716 HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
717 HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
718 HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
719 HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
720 HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
721 void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
722 void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
723 void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
724 void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
725 /**
726 * @}
727 */
728
729 /** @addtogroup CAN_Exported_Functions_Group3
730 * @brief CAN Peripheral State functions
731 * @{
732 */
733 /* Peripheral State and Error functions ***************************************/
734 uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
735 HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
736 /**
737 * @}
738 */
739
740 /**
741 * @}
742 */
743
744 /* Private macros --------------------------------------------------------*/
745 /** @defgroup CAN_Private_Macros CAN Private Macros
746 * @{
747 */
748
749 #define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
750 ((MODE) == CAN_MODE_LOOPBACK)|| \
751 ((MODE) == CAN_MODE_SILENT) || \
752 ((MODE) == CAN_MODE_SILENT_LOOPBACK))
753 #define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
754 ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
755 #define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
756 #define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
757 #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
758
759 #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
760 ((MODE) == CAN_FILTERMODE_IDLIST))
761 #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
762 ((SCALE) == CAN_FILTERSCALE_32BIT))
763 #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
764 ((FIFO) == CAN_FILTER_FIFO1))
765 #define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
766
767 #define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
768 #define IS_CAN_STDID(STDID) ((STDID) <= 0x00007FFU)
769 #define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
770 #define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
771
772 #define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
773 ((IDTYPE) == CAN_ID_EXT))
774 #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
775 #define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
776
777 /**
778 * @}
779 */
780
781 /**
782 * @}
783 */
784
785 /**
786 * @}
787 */
788
789 #endif /* STM32F103x6) || STM32F103xB || STM32F103xE || STM32F103xG) || STM32F105xC || STM32F107xC */
790
791 #ifdef __cplusplus
792 }
793 #endif
794
795 #endif /* __STM32F1xx_HAL_CAN_H */
796
797
798 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/