?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge pull request #11270 from haslinghuis/rename_attr
[betaflight.git] / lib / main / STM32F1 / Drivers / STM32F1xx_HAL_Driver / Inc / stm32f1xx_hal_eth.h
blobe747a8366ddf4dc4395481ec2a8254b6d1b8ed52
1 /**
2 ******************************************************************************
3 * @file stm32f1xx_hal_eth.h
4 * @author MCD Application Team
5 * @version V1.1.1
6 * @date 12-May-2017
7 * @brief Header file of ETH HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F1xx_HAL_ETH_H
40 #define __STM32F1xx_HAL_ETH_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f1xx_hal_def.h"
48
49 /** @addtogroup STM32F1xx_HAL_Driver
50 * @{
51 */
52 #if defined (STM32F107xC)
53
54 /** @addtogroup ETH
55 * @{
56 */
57
58 /** @addtogroup ETH_Private_Macros
59 * @{
60 */
61 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U)
62 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
63 ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
64 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
65 ((SPEED) == ETH_SPEED_100M))
66 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
67 ((MODE) == ETH_MODE_HALFDUPLEX))
68 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
69 ((MODE) == ETH_RXINTERRUPT_MODE))
70 #define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
71 ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
72 #define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
73 ((MODE) == ETH_MEDIA_INTERFACE_RMII))
74 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
75 ((CMD) == ETH_WATCHDOG_DISABLE))
76 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
77 ((CMD) == ETH_JABBER_DISABLE))
78 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
79 ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
80 ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
81 ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
82 ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
83 ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
84 ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
85 ((GAP) == ETH_INTERFRAMEGAP_40BIT))
86 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
87 ((CMD) == ETH_CARRIERSENCE_DISABLE))
88 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
89 ((CMD) == ETH_RECEIVEOWN_DISABLE))
90 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
91 ((CMD) == ETH_LOOPBACKMODE_DISABLE))
92 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
93 ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
94 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
95 ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
96 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
97 ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
98 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
99 ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
100 ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
101 ((LIMIT) == ETH_BACKOFFLIMIT_1))
102 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
103 ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
104 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
105 ((CMD) == ETH_RECEIVEAll_DISABLE))
106 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
107 ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
108 ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
109 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
110 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
111 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
112 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
113 ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
114 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
115 ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
116 #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
117 ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
118 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
119 ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
120 ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
121 ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
122 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
123 ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
124 ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
125 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU)
126 #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
127 ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
128 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
129 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
130 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
131 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
132 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
133 ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
134 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
135 ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
136 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
137 ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
138 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
139 ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
140 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU)
141 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
142 ((ADDRESS) == ETH_MAC_ADDRESS1) || \
143 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
144 ((ADDRESS) == ETH_MAC_ADDRESS3))
145 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
146 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
147 ((ADDRESS) == ETH_MAC_ADDRESS3))
148 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
149 ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
150 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
151 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
152 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
153 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
154 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
155 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
156 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
157 ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
158 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
159 ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
160 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
161 ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
162 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
163 ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
164 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
165 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
166 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
167 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
168 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
169 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
170 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
171 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
172 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
173 ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
174 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
175 ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
176 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
177 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
178 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
179 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
180 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
181 ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
182 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
183 ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
184 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
185 ((CMD) == ETH_FIXEDBURST_DISABLE))
186 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
187 ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
188 ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
189 ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
190 ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
191 ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
192 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
193 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
194 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
195 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
196 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
197 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
198 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
199 ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
200 ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
201 ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
202 ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
203 ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
204 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
205 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
206 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
207 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
208 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
209 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
210 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU)
211 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
212 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
213 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
214 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
215 ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
216 #define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
217 ((FLAG) == ETH_DMATXDESC_IC) || \
218 ((FLAG) == ETH_DMATXDESC_LS) || \
219 ((FLAG) == ETH_DMATXDESC_FS) || \
220 ((FLAG) == ETH_DMATXDESC_DC) || \
221 ((FLAG) == ETH_DMATXDESC_DP) || \
222 ((FLAG) == ETH_DMATXDESC_TTSE) || \
223 ((FLAG) == ETH_DMATXDESC_TER) || \
224 ((FLAG) == ETH_DMATXDESC_TCH) || \
225 ((FLAG) == ETH_DMATXDESC_TTSS) || \
226 ((FLAG) == ETH_DMATXDESC_IHE) || \
227 ((FLAG) == ETH_DMATXDESC_ES) || \
228 ((FLAG) == ETH_DMATXDESC_JT) || \
229 ((FLAG) == ETH_DMATXDESC_FF) || \
230 ((FLAG) == ETH_DMATXDESC_PCE) || \
231 ((FLAG) == ETH_DMATXDESC_LCA) || \
232 ((FLAG) == ETH_DMATXDESC_NC) || \
233 ((FLAG) == ETH_DMATXDESC_LCO) || \
234 ((FLAG) == ETH_DMATXDESC_EC) || \
235 ((FLAG) == ETH_DMATXDESC_VF) || \
236 ((FLAG) == ETH_DMATXDESC_CC) || \
237 ((FLAG) == ETH_DMATXDESC_ED) || \
238 ((FLAG) == ETH_DMATXDESC_UF) || \
239 ((FLAG) == ETH_DMATXDESC_DB))
240 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
241 ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
242 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
243 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
244 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
245 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
246 #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU)
247 #define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
248 ((FLAG) == ETH_DMARXDESC_AFM) || \
249 ((FLAG) == ETH_DMARXDESC_ES) || \
250 ((FLAG) == ETH_DMARXDESC_DE) || \
251 ((FLAG) == ETH_DMARXDESC_SAF) || \
252 ((FLAG) == ETH_DMARXDESC_LE) || \
253 ((FLAG) == ETH_DMARXDESC_OE) || \
254 ((FLAG) == ETH_DMARXDESC_VLAN) || \
255 ((FLAG) == ETH_DMARXDESC_FS) || \
256 ((FLAG) == ETH_DMARXDESC_LS) || \
257 ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
258 ((FLAG) == ETH_DMARXDESC_LC) || \
259 ((FLAG) == ETH_DMARXDESC_FT) || \
260 ((FLAG) == ETH_DMARXDESC_RWT) || \
261 ((FLAG) == ETH_DMARXDESC_RE) || \
262 ((FLAG) == ETH_DMARXDESC_DBE) || \
263 ((FLAG) == ETH_DMARXDESC_CE) || \
264 ((FLAG) == ETH_DMARXDESC_MAMPCE))
265 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
266 ((BUFFER) == ETH_DMARXDESC_BUFFER2))
267 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
268 ((FLAG) == ETH_PMT_FLAG_MPR))
269 #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U))
270 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
271 ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
272 ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
273 ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
274 ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
275 ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
276 ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
277 ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
278 ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
279 ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
280 ((FLAG) == ETH_DMA_FLAG_T))
281 #define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U))
282 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
283 ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
284 ((IT) == ETH_MAC_IT_PMT))
285 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
286 ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
287 ((FLAG) == ETH_MAC_FLAG_PMT))
288 #define IS_ETH_DMA_IT(IT) ((((IT) & 0xC7FE1800U) == 0x00U) && ((IT) != 0x00U))
289 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
290 ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
291 ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
292 ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
293 ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
294 ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
295 ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
296 ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
297 ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
298 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
299 ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
300 #define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFFU) == 0x00U) || (((IT) & 0xEFFDFF9FU) == 0x00U)) && \
301 ((IT) != 0x00U))
302 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
303 ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
304 ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
305 #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
306 ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
307
308 /**
309 * @}
310 */
311
312 /** @addtogroup ETH_Private_Defines
313 * @{
314 */
315 /* Delay to wait when writing to some Ethernet registers */
316 #define ETH_REG_WRITE_DELAY 0x00000001U
317
318 /* ETHERNET Errors */
319 #define ETH_SUCCESS 0U
320 #define ETH_ERROR 1U
321
322 /* ETHERNET DMA Tx descriptors Collision Count Shift */
323 #define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U
324
325 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
326 #define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U
327
328 /* ETHERNET DMA Rx descriptors Frame Length Shift */
329 #define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U
330
331 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
332 #define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U
333
334 /* ETHERNET DMA Rx descriptors Frame length Shift */
335 #define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U
336
337 /* ETHERNET MAC address offsets */
338 #define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */
339 #define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */
340
341 /* ETHERNET MACMIIAR register Mask */
342 #define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U
343
344 /* ETHERNET MACCR register Mask */
345 #define ETH_MACCR_CLEAR_MASK 0xFF20810FU
346
347 /* ETHERNET MACFCR register Mask */
348 #define ETH_MACFCR_CLEAR_MASK 0x0000FF41U
349
350 /* ETHERNET DMAOMR register Mask */
351 #define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U
352
353 /* ETHERNET Remote Wake-up frame register length */
354 #define ETH_WAKEUP_REGISTER_LENGTH 8U
355
356 /* ETHERNET Missed frames counter Shift */
357 #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U
358 /**
359 * @}
360 */
361
362 /* Exported types ------------------------------------------------------------*/
363 /** @defgroup ETH_Exported_Types ETH Exported Types
364 * @{
365 */
366
367 /**
368 * @brief HAL State structures definition
369 */
370 typedef enum
371 {
372 HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */
373 HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
374 HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
375 HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
376 HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
377 HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */
378 HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */
379 HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */
380 HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
381 HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
382 }HAL_ETH_StateTypeDef;
383
384 /**
385 * @brief ETH Init Structure definition
386 */
387
388 typedef struct
389 {
390 uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
391 The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
392 and the mode (half/full-duplex).
393 This parameter can be a value of @ref ETH_AutoNegotiation */
394
395 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
396 This parameter can be a value of @ref ETH_Speed */
397
398 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
399 This parameter can be a value of @ref ETH_Duplex_Mode */
400
401 uint16_t PhyAddress; /*!< Ethernet PHY address.
402 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
403
404 uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
405
406 uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
407 This parameter can be a value of @ref ETH_Rx_Mode */
408
409 uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
410 This parameter can be a value of @ref ETH_Checksum_Mode */
411
412 uint32_t MediaInterface; /*!< Selects the media-independent interface or the reduced media-independent interface.
413 This parameter can be a value of @ref ETH_Media_Interface */
414
415 } ETH_InitTypeDef;
416
417
418 /**
419 * @brief ETH MAC Configuration Structure definition
420 */
421
422 typedef struct
423 {
424 uint32_t Watchdog; /*!< Selects or not the Watchdog timer
425 When enabled, the MAC allows no more then 2048 bytes to be received.
426 When disabled, the MAC can receive up to 16384 bytes.
427 This parameter can be a value of @ref ETH_Watchdog */
428
429 uint32_t Jabber; /*!< Selects or not Jabber timer
430 When enabled, the MAC allows no more then 2048 bytes to be sent.
431 When disabled, the MAC can send up to 16384 bytes.
432 This parameter can be a value of @ref ETH_Jabber */
433
434 uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
435 This parameter can be a value of @ref ETH_Inter_Frame_Gap */
436
437 uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
438 This parameter can be a value of @ref ETH_Carrier_Sense */
439
440 uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
441 ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
442 in Half-Duplex mode.
443 This parameter can be a value of @ref ETH_Receive_Own */
444
445 uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
446 This parameter can be a value of @ref ETH_Loop_Back_Mode */
447
448 uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
449 This parameter can be a value of @ref ETH_Checksum_Offload */
450
451 uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
452 when a collision occurs (Half-Duplex mode).
453 This parameter can be a value of @ref ETH_Retry_Transmission */
454
455 uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
456 This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
457
458 uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
459 This parameter can be a value of @ref ETH_Back_Off_Limit */
460
461 uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
462 This parameter can be a value of @ref ETH_Deferral_Check */
463
464 uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
465 This parameter can be a value of @ref ETH_Receive_All */
466
467 uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
468 This parameter can be a value of @ref ETH_Source_Addr_Filter */
469
470 uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
471 This parameter can be a value of @ref ETH_Pass_Control_Frames */
472
473 uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
474 This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
475
476 uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
477 This parameter can be a value of @ref ETH_Destination_Addr_Filter */
478
479 uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
480 This parameter can be a value of @ref ETH_Promiscuous_Mode */
481
482 uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
483 This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
484
485 uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
486 This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
487
488 uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
489 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
490
491 uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
492 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
493
494 uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
495 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFU */
496
497 uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
498 This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
499
500 uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
501 automatic retransmission of PAUSE Frame.
502 This parameter can be a value of @ref ETH_Pause_Low_Threshold */
503
504 uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
505 unicast address and unique multicast address).
506 This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
507
508 uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
509 disable its transmitter for a specified time (Pause Time)
510 This parameter can be a value of @ref ETH_Receive_Flow_Control */
511
512 uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
513 or the MAC back-pressure operation (Half-Duplex mode)
514 This parameter can be a value of @ref ETH_Transmit_Flow_Control */
515
516 uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
517 comparison and filtering.
518 This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
519
520 uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
521
522 } ETH_MACInitTypeDef;
523
524 /**
525 * @brief ETH DMA Configuration Structure definition
526 */
527
528 typedef struct
529 {
530 uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
531 This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
532
533 uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
534 This parameter can be a value of @ref ETH_Receive_Store_Forward */
535
536 uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
537 This parameter can be a value of @ref ETH_Flush_Received_Frame */
538
539 uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
540 This parameter can be a value of @ref ETH_Transmit_Store_Forward */
541
542 uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
543 This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
544
545 uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
546 This parameter can be a value of @ref ETH_Forward_Error_Frames */
547
548 uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
549 and length less than 64 bytes) including pad-bytes and CRC)
550 This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
551
552 uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
553 This parameter can be a value of @ref ETH_Receive_Threshold_Control */
554
555 uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
556 frame of Transmit data even before obtaining the status for the first frame.
557 This parameter can be a value of @ref ETH_Second_Frame_Operate */
558
559 uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
560 This parameter can be a value of @ref ETH_Address_Aligned_Beats */
561
562 uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
563 This parameter can be a value of @ref ETH_Fixed_Burst */
564
565 uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
566 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
567
568 uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
569 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
570
571 uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
572 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
573
574 uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
575 This parameter can be a value of @ref ETH_DMA_Arbitration */
576 } ETH_DMAInitTypeDef;
577
578
579 /**
580 * @brief ETH DMA Descriptors data structure definition
581 */
582
583 typedef struct
584 {
585 __IO uint32_t Status; /*!< Status */
586
587 uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
588
589 uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
590
591 uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
592
593 } ETH_DMADescTypeDef;
594
595 /**
596 * @brief Received Frame Informations structure definition
597 */
598 typedef struct
599 {
600 ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */
601
602 ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */
603
604 uint32_t SegCount; /*!< Segment count */
605
606 uint32_t length; /*!< Frame length */
607
608 uint32_t buffer; /*!< Frame buffer */
609
610 } ETH_DMARxFrameInfos;
611
612 /**
613 * @brief ETH Handle Structure definition
614 */
615
616 typedef struct
617 {
618 ETH_TypeDef *Instance; /*!< Register base address */
619
620 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
621
622 uint32_t LinkStatus; /*!< Ethernet link status */
623
624 ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */
625
626 ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */
627
628 ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */
629
630 __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */
631
632 HAL_LockTypeDef Lock; /*!< ETH Lock */
633
634 } ETH_HandleTypeDef;
635
636 /**
637 * @}
638 */
639
640 /* Exported constants --------------------------------------------------------*/
641 /** @defgroup ETH_Exported_Constants ETH Exported Constants
642 * @{
643 */
644
645 /** @defgroup ETH_Buffers_setting ETH Buffers setting
646 * @{
647 */
648 #define ETH_MAX_PACKET_SIZE 1524U /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
649 #define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
650 #define ETH_CRC 4U /*!< Ethernet CRC */
651 #define ETH_EXTRA 2U /*!< Extra bytes in some cases */
652 #define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */
653 #define ETH_MIN_ETH_PAYLOAD 46U /*!< Minimum Ethernet payload size */
654 #define ETH_MAX_ETH_PAYLOAD 1500U /*!< Maximum Ethernet payload size */
655 #define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */
656
657 /* Ethernet driver receive buffers are organized in a chained linked-list, when
658 an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
659 to the driver receive buffers memory.
660
661 Depending on the size of the received ethernet packet and the size of
662 each ethernet driver receive buffer, the received packet can take one or more
663 ethernet driver receive buffer.
664
665 In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
666 and the total count of the driver receive buffers ETH_RXBUFNB.
667
668 The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
669 example, they can be reconfigured in the application layer to fit the application
670 needs */
671
672 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
673 packet */
674 #ifndef ETH_RX_BUF_SIZE
675 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
676 #endif
677
678 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
679 #ifndef ETH_RXBUFNB
680 #define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
681 #endif
682
683
684 /* Ethernet driver transmit buffers are organized in a chained linked-list, when
685 an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
686 driver transmit buffers memory to the TxFIFO.
687
688 Depending on the size of the Ethernet packet to be transmitted and the size of
689 each ethernet driver transmit buffer, the packet to be transmitted can take
690 one or more ethernet driver transmit buffer.
691
692 In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
693 and the total count of the driver transmit buffers ETH_TXBUFNB.
694
695 The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
696 example, they can be reconfigured in the application layer to fit the application
697 needs */
698
699 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
700 packet */
701 #ifndef ETH_TX_BUF_SIZE
702 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
703 #endif
704
705 /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
706 #ifndef ETH_TXBUFNB
707 #define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
708 #endif
709
710 /**
711 * @}
712 */
713
714 /** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
715 * @{
716 */
717
718 /*
719 DMA Tx Descriptor
720 -----------------------------------------------------------------------------------------------
721 TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
722 -----------------------------------------------------------------------------------------------
723 TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
724 -----------------------------------------------------------------------------------------------
725 TDES2 | Buffer1 Address [31:0] |
726 -----------------------------------------------------------------------------------------------
727 TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
728 -----------------------------------------------------------------------------------------------
729 */
730
731 /**
732 * @brief Bit definition of TDES0 register: DMA Tx descriptor status register
733 */
734 #define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
735 #define ETH_DMATXDESC_IC 0x40000000U /*!< Interrupt on Completion */
736 #define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */
737 #define ETH_DMATXDESC_FS 0x10000000U /*!< First Segment */
738 #define ETH_DMATXDESC_DC 0x08000000U /*!< Disable CRC */
739 #define ETH_DMATXDESC_DP 0x04000000U /*!< Disable Padding */
740 #define ETH_DMATXDESC_TTSE 0x02000000U /*!< Transmit Time Stamp Enable */
741 #define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */
742 #define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */
743 #define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */
744 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
745 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
746 #define ETH_DMATXDESC_TER 0x00200000U /*!< Transmit End of Ring */
747 #define ETH_DMATXDESC_TCH 0x00100000U /*!< Second Address Chained */
748 #define ETH_DMATXDESC_TTSS 0x00020000U /*!< Tx Time Stamp Status */
749 #define ETH_DMATXDESC_IHE 0x00010000U /*!< IP Header Error */
750 #define ETH_DMATXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
751 #define ETH_DMATXDESC_JT 0x00004000U /*!< Jabber Timeout */
752 #define ETH_DMATXDESC_FF 0x00002000U /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
753 #define ETH_DMATXDESC_PCE 0x00001000U /*!< Payload Checksum Error */
754 #define ETH_DMATXDESC_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */
755 #define ETH_DMATXDESC_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */
756 #define ETH_DMATXDESC_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */
757 #define ETH_DMATXDESC_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */
758 #define ETH_DMATXDESC_VF 0x00000080U /*!< VLAN Frame */
759 #define ETH_DMATXDESC_CC 0x00000078U /*!< Collision Count */
760 #define ETH_DMATXDESC_ED 0x00000004U /*!< Excessive Deferral */
761 #define ETH_DMATXDESC_UF 0x00000002U /*!< Underflow Error: late data arrival from the memory */
762 #define ETH_DMATXDESC_DB 0x00000001U /*!< Deferred Bit */
763
764 /**
765 * @brief Bit definition of TDES1 register
766 */
767 #define ETH_DMATXDESC_TBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */
768 #define ETH_DMATXDESC_TBS1 0x00001FFFU /*!< Transmit Buffer1 Size */
769
770 /**
771 * @brief Bit definition of TDES2 register
772 */
773 #define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */
774
775 /**
776 * @brief Bit definition of TDES3 register
777 */
778 #define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */
779
780 /**
781 * @}
782 */
783 /** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
784 * @{
785 */
786
787 /*
788 DMA Rx Descriptor
789 --------------------------------------------------------------------------------------------------------------------
790 RDES0 | OWN(31) | Status [30:0] |
791 ---------------------------------------------------------------------------------------------------------------------
792 RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
793 ---------------------------------------------------------------------------------------------------------------------
794 RDES2 | Buffer1 Address [31:0] |
795 ---------------------------------------------------------------------------------------------------------------------
796 RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
797 ---------------------------------------------------------------------------------------------------------------------
798 */
799
800 /**
801 * @brief Bit definition of RDES0 register: DMA Rx descriptor status register
802 */
803 #define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
804 #define ETH_DMARXDESC_AFM 0x40000000U /*!< DA Filter Fail for the rx frame */
805 #define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */
806 #define ETH_DMARXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
807 #define ETH_DMARXDESC_DE 0x00004000U /*!< Descriptor error: no more descriptors for receive frame */
808 #define ETH_DMARXDESC_SAF 0x00002000U /*!< SA Filter Fail for the received frame */
809 #define ETH_DMARXDESC_LE 0x00001000U /*!< Frame size not matching with length field */
810 #define ETH_DMARXDESC_OE 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */
811 #define ETH_DMARXDESC_VLAN 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */
812 #define ETH_DMARXDESC_FS 0x00000200U /*!< First descriptor of the frame */
813 #define ETH_DMARXDESC_LS 0x00000100U /*!< Last descriptor of the frame */
814 #define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
815 #define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */
816 #define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */
817 #define ETH_DMARXDESC_RWT 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
818 #define ETH_DMARXDESC_RE 0x00000008U /*!< Receive error: error reported by MII interface */
819 #define ETH_DMARXDESC_DBE 0x00000004U /*!< Dribble bit error: frame contains non int multiple of 8 bits */
820 #define ETH_DMARXDESC_CE 0x00000002U /*!< CRC error */
821 #define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
822
823 /**
824 * @brief Bit definition of RDES1 register
825 */
826 #define ETH_DMARXDESC_DIC 0x80000000U /*!< Disable Interrupt on Completion */
827 #define ETH_DMARXDESC_RBS2 0x1FFF0000U /*!< Receive Buffer2 Size */
828 #define ETH_DMARXDESC_RER 0x00008000U /*!< Receive End of Ring */
829 #define ETH_DMARXDESC_RCH 0x00004000U /*!< Second Address Chained */
830 #define ETH_DMARXDESC_RBS1 0x00001FFFU /*!< Receive Buffer1 Size */
831
832 /**
833 * @brief Bit definition of RDES2 register
834 */
835 #define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */
836
837 /**
838 * @brief Bit definition of RDES3 register
839 */
840 #define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */
841
842 /**
843 * @}
844 */
845 /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
846 * @{
847 */
848 #define ETH_AUTONEGOTIATION_ENABLE 0x00000001U
849 #define ETH_AUTONEGOTIATION_DISABLE 0x00000000U
850
851 /**
852 * @}
853 */
854 /** @defgroup ETH_Speed ETH Speed
855 * @{
856 */
857 #define ETH_SPEED_10M 0x00000000U
858 #define ETH_SPEED_100M 0x00004000U
859
860 /**
861 * @}
862 */
863 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode
864 * @{
865 */
866 #define ETH_MODE_FULLDUPLEX 0x00000800U
867 #define ETH_MODE_HALFDUPLEX 0x00000000U
868 /**
869 * @}
870 */
871 /** @defgroup ETH_Rx_Mode ETH Rx Mode
872 * @{
873 */
874 #define ETH_RXPOLLING_MODE 0x00000000U
875 #define ETH_RXINTERRUPT_MODE 0x00000001U
876 /**
877 * @}
878 */
879
880 /** @defgroup ETH_Checksum_Mode ETH Checksum Mode
881 * @{
882 */
883 #define ETH_CHECKSUM_BY_HARDWARE 0x00000000U
884 #define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U
885 /**
886 * @}
887 */
888
889 /** @defgroup ETH_Media_Interface ETH Media Interface
890 * @{
891 */
892 #define ETH_MEDIA_INTERFACE_MII 0x00000000U
893 #define ETH_MEDIA_INTERFACE_RMII ((uint32_t)AFIO_MAPR_MII_RMII_SEL)
894
895 /**
896 * @}
897 */
898
899 /** @defgroup ETH_Watchdog ETH Watchdog
900 * @{
901 */
902 #define ETH_WATCHDOG_ENABLE 0x00000000U
903 #define ETH_WATCHDOG_DISABLE 0x00800000U
904 /**
905 * @}
906 */
907
908 /** @defgroup ETH_Jabber ETH Jabber
909 * @{
910 */
911 #define ETH_JABBER_ENABLE 0x00000000U
912 #define ETH_JABBER_DISABLE 0x00400000U
913 /**
914 * @}
915 */
916
917 /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
918 * @{
919 */
920 #define ETH_INTERFRAMEGAP_96BIT 0x00000000U /*!< minimum IFG between frames during transmission is 96Bit */
921 #define ETH_INTERFRAMEGAP_88BIT 0x00020000U /*!< minimum IFG between frames during transmission is 88Bit */
922 #define ETH_INTERFRAMEGAP_80BIT 0x00040000U /*!< minimum IFG between frames during transmission is 80Bit */
923 #define ETH_INTERFRAMEGAP_72BIT 0x00060000U /*!< minimum IFG between frames during transmission is 72Bit */
924 #define ETH_INTERFRAMEGAP_64BIT 0x00080000U /*!< minimum IFG between frames during transmission is 64Bit */
925 #define ETH_INTERFRAMEGAP_56BIT 0x000A0000U /*!< minimum IFG between frames during transmission is 56Bit */
926 #define ETH_INTERFRAMEGAP_48BIT 0x000C0000U /*!< minimum IFG between frames during transmission is 48Bit */
927 #define ETH_INTERFRAMEGAP_40BIT 0x000E0000U /*!< minimum IFG between frames during transmission is 40Bit */
928 /**
929 * @}
930 */
931
932 /** @defgroup ETH_Carrier_Sense ETH Carrier Sense
933 * @{
934 */
935 #define ETH_CARRIERSENCE_ENABLE 0x00000000U
936 #define ETH_CARRIERSENCE_DISABLE 0x00010000U
937 /**
938 * @}
939 */
940
941 /** @defgroup ETH_Receive_Own ETH Receive Own
942 * @{
943 */
944 #define ETH_RECEIVEOWN_ENABLE 0x00000000U
945 #define ETH_RECEIVEOWN_DISABLE 0x00002000U
946 /**
947 * @}
948 */
949
950 /** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
951 * @{
952 */
953 #define ETH_LOOPBACKMODE_ENABLE 0x00001000U
954 #define ETH_LOOPBACKMODE_DISABLE 0x00000000U
955 /**
956 * @}
957 */
958
959 /** @defgroup ETH_Checksum_Offload ETH Checksum Offload
960 * @{
961 */
962 #define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U
963 #define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U
964 /**
965 * @}
966 */
967
968 /** @defgroup ETH_Retry_Transmission ETH Retry Transmission
969 * @{
970 */
971 #define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U
972 #define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U
973 /**
974 * @}
975 */
976
977 /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
978 * @{
979 */
980 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U
981 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U
982 /**
983 * @}
984 */
985
986 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
987 * @{
988 */
989 #define ETH_BACKOFFLIMIT_10 0x00000000U
990 #define ETH_BACKOFFLIMIT_8 0x00000020U
991 #define ETH_BACKOFFLIMIT_4 0x00000040U
992 #define ETH_BACKOFFLIMIT_1 0x00000060U
993 /**
994 * @}
995 */
996
997 /** @defgroup ETH_Deferral_Check ETH Deferral Check
998 * @{
999 */
1000 #define ETH_DEFFERRALCHECK_ENABLE 0x00000010U
1001 #define ETH_DEFFERRALCHECK_DISABLE 0x00000000U
1002 /**
1003 * @}
1004 */
1005
1006 /** @defgroup ETH_Receive_All ETH Receive All
1007 * @{
1008 */
1009 #define ETH_RECEIVEALL_ENABLE 0x80000000U
1010 #define ETH_RECEIVEAll_DISABLE 0x00000000U
1011 /**
1012 * @}
1013 */
1014
1015 /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
1016 * @{
1017 */
1018 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U
1019 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U
1020 #define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U
1021 /**
1022 * @}
1023 */
1024
1025 /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
1026 * @{
1027 */
1028 #define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /*!< MAC filters all control frames from reaching the application */
1029 #define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /*!< MAC forwards all control frames to application even if they fail the Address Filter */
1030 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /*!< MAC forwards control frames that pass the Address Filter. */
1031 /**
1032 * @}
1033 */
1034
1035 /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
1036 * @{
1037 */
1038 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U
1039 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U
1040 /**
1041 * @}
1042 */
1043
1044 /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
1045 * @{
1046 */
1047 #define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U
1048 #define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U
1049 /**
1050 * @}
1051 */
1052
1053 /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
1054 * @{
1055 */
1056 #define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U
1057 #define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U
1058 /**
1059 * @}
1060 */
1061
1062 /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
1063 * @{
1064 */
1065 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U
1066 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U
1067 #define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U
1068 #define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U
1069 /**
1070 * @}
1071 */
1072
1073 /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
1074 * @{
1075 */
1076 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U
1077 #define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U
1078 #define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U
1079 /**
1080 * @}
1081 */
1082
1083 /** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
1084 * @{
1085 */
1086 #define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U
1087 #define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U
1088 /**
1089 * @}
1090 */
1091
1092 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
1093 * @{
1094 */
1095 #define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /*!< Pause time minus 4 slot times */
1096 #define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /*!< Pause time minus 28 slot times */
1097 #define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /*!< Pause time minus 144 slot times */
1098 #define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U /*!< Pause time minus 256 slot times */
1099 /**
1100 * @}
1101 */
1102
1103 /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
1104 * @{
1105 */
1106 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U
1107 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U
1108 /**
1109 * @}
1110 */
1111
1112 /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
1113 * @{
1114 */
1115 #define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U
1116 #define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U
1117 /**
1118 * @}
1119 */
1120
1121 /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
1122 * @{
1123 */
1124 #define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U
1125 #define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U
1126 /**
1127 * @}
1128 */
1129
1130 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
1131 * @{
1132 */
1133 #define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U
1134 #define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U
1135 /**
1136 * @}
1137 */
1138
1139 /** @defgroup ETH_MAC_addresses ETH MAC addresses
1140 * @{
1141 */
1142 #define ETH_MAC_ADDRESS0 0x00000000U
1143 #define ETH_MAC_ADDRESS1 0x00000008U
1144 #define ETH_MAC_ADDRESS2 0x00000010U
1145 #define ETH_MAC_ADDRESS3 0x00000018U
1146 /**
1147 * @}
1148 */
1149
1150 /** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
1151 * @{
1152 */
1153 #define ETH_MAC_ADDRESSFILTER_SA 0x00000000U
1154 #define ETH_MAC_ADDRESSFILTER_DA 0x00000008U
1155 /**
1156 * @}
1157 */
1158
1159 /** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
1160 * @{
1161 */
1162 #define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /*!< Mask MAC Address high reg bits [15:8] */
1163 #define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /*!< Mask MAC Address high reg bits [7:0] */
1164 #define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /*!< Mask MAC Address low reg bits [31:24] */
1165 #define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U /*!< Mask MAC Address low reg bits [23:16] */
1166 #define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U /*!< Mask MAC Address low reg bits [15:8] */
1167 #define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U /*!< Mask MAC Address low reg bits [70] */
1168 /**
1169 * @}
1170 */
1171
1172 /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
1173 * @{
1174 */
1175 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U
1176 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U
1177 /**
1178 * @}
1179 */
1180
1181 /** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
1182 * @{
1183 */
1184 #define ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U
1185 #define ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U
1186 /**
1187 * @}
1188 */
1189
1190 /** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
1191 * @{
1192 */
1193 #define ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U
1194 #define ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U
1195 /**
1196 * @}
1197 */
1198
1199 /** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
1200 * @{
1201 */
1202 #define ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U
1203 #define ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U
1204 /**
1205 * @}
1206 */
1207
1208 /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
1209 * @{
1210 */
1211 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
1212 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
1213 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
1214 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
1215 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
1216 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
1217 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
1218 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
1219 /**
1220 * @}
1221 */
1222
1223 /** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
1224 * @{
1225 */
1226 #define ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U
1227 #define ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U
1228 /**
1229 * @}
1230 */
1231
1232 /** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
1233 * @{
1234 */
1235 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U
1236 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U
1237 /**
1238 * @}
1239 */
1240
1241 /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
1242 * @{
1243 */
1244 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
1245 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
1246 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
1247 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
1248 /**
1249 * @}
1250 */
1251
1252 /** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
1253 * @{
1254 */
1255 #define ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U
1256 #define ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U
1257 /**
1258 * @}
1259 */
1260
1261 /** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
1262 * @{
1263 */
1264 #define ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U
1265 #define ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U
1266 /**
1267 * @}
1268 */
1269
1270 /** @defgroup ETH_Fixed_Burst ETH Fixed Burst
1271 * @{
1272 */
1273 #define ETH_FIXEDBURST_ENABLE 0x00010000U
1274 #define ETH_FIXEDBURST_DISABLE 0x00000000U
1275 /**
1276 * @}
1277 */
1278
1279 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
1280 * @{
1281 */
1282 #define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
1283 #define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
1284 #define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
1285 #define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
1286 #define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
1287 #define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
1288 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
1289 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
1290 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
1291 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
1292 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
1293 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
1294 /**
1295 * @}
1296 */
1297
1298 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
1299 * @{
1300 */
1301 #define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
1302 #define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
1303 #define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
1304 #define ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
1305 #define ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
1306 #define ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
1307 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
1308 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
1309 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
1310 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
1311 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
1312 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
1313
1314 /**
1315 * @}
1316 */
1317
1318 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
1319 * @{
1320 */
1321 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U
1322 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U
1323 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U
1324 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U
1325 #define ETH_DMAARBITRATION_RXPRIORTX 0x00000002U
1326 /**
1327 * @}
1328 */
1329
1330 /** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
1331 * @{
1332 */
1333 #define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U /*!< Last Segment */
1334 #define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U /*!< First Segment */
1335 /**
1336 * @}
1337 */
1338
1339 /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
1340 * @{
1341 */
1342 #define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U /*!< Checksum engine bypass */
1343 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U /*!< IPv4 header checksum insertion */
1344 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
1345 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
1346 /**
1347 * @}
1348 */
1349
1350 /** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
1351 * @{
1352 */
1353 #define ETH_DMARXDESC_BUFFER1 0x00000000U /*!< DMA Rx Desc Buffer1 */
1354 #define ETH_DMARXDESC_BUFFER2 0x00000001U /*!< DMA Rx Desc Buffer2 */
1355 /**
1356 * @}
1357 */
1358
1359 /** @defgroup ETH_PMT_Flags ETH PMT Flags
1360 * @{
1361 */
1362 #define ETH_PMT_FLAG_WUFFRPR 0x80000000U /*!< Wake-Up Frame Filter Register Pointer Reset */
1363 #define ETH_PMT_FLAG_WUFR 0x00000040U /*!< Wake-Up Frame Received */
1364 #define ETH_PMT_FLAG_MPR 0x00000020U /*!< Magic Packet Received */
1365 /**
1366 * @}
1367 */
1368
1369 /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
1370 * @{
1371 */
1372 #define ETH_MMC_IT_TGF 0x00200000U /*!< When Tx good frame counter reaches half the maximum value */
1373 #define ETH_MMC_IT_TGFMSC 0x00008000U /*!< When Tx good multi col counter reaches half the maximum value */
1374 #define ETH_MMC_IT_TGFSC 0x00004000U /*!< When Tx good single col counter reaches half the maximum value */
1375 /**
1376 * @}
1377 */
1378
1379 /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
1380 * @{
1381 */
1382 #define ETH_MMC_IT_RGUF 0x10020000U /*!< When Rx good unicast frames counter reaches half the maximum value */
1383 #define ETH_MMC_IT_RFAE 0x10000040U /*!< When Rx alignment error counter reaches half the maximum value */
1384 #define ETH_MMC_IT_RFCE 0x10000020U /*!< When Rx crc error counter reaches half the maximum value */
1385 /**
1386 * @}
1387 */
1388
1389 /** @defgroup ETH_MAC_Flags ETH MAC Flags
1390 * @{
1391 */
1392 #define ETH_MAC_FLAG_TST 0x00000200U /*!< Time stamp trigger flag (on MAC) */
1393 #define ETH_MAC_FLAG_MMCT 0x00000040U /*!< MMC transmit flag */
1394 #define ETH_MAC_FLAG_MMCR 0x00000020U /*!< MMC receive flag */
1395 #define ETH_MAC_FLAG_MMC 0x00000010U /*!< MMC flag (on MAC) */
1396 #define ETH_MAC_FLAG_PMT 0x00000008U /*!< PMT flag (on MAC) */
1397 /**
1398 * @}
1399 */
1400
1401 /** @defgroup ETH_DMA_Flags ETH DMA Flags
1402 * @{
1403 */
1404 #define ETH_DMA_FLAG_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */
1405 #define ETH_DMA_FLAG_PMT 0x10000000U /*!< PMT interrupt (on DMA) */
1406 #define ETH_DMA_FLAG_MMC 0x08000000U /*!< MMC interrupt (on DMA) */
1407 #define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U /*!< Error bits 0-Rx DMA, 1-Tx DMA */
1408 #define ETH_DMA_FLAG_READWRITEERROR 0x01000000U /*!< Error bits 0-write transfer, 1-read transfer */
1409 #define ETH_DMA_FLAG_ACCESSERROR 0x02000000U /*!< Error bits 0-data buffer, 1-desc. access */
1410 #define ETH_DMA_FLAG_NIS 0x00010000U /*!< Normal interrupt summary flag */
1411 #define ETH_DMA_FLAG_AIS 0x00008000U /*!< Abnormal interrupt summary flag */
1412 #define ETH_DMA_FLAG_ER 0x00004000U /*!< Early receive flag */
1413 #define ETH_DMA_FLAG_FBE 0x00002000U /*!< Fatal bus error flag */
1414 #define ETH_DMA_FLAG_ET 0x00000400U /*!< Early transmit flag */
1415 #define ETH_DMA_FLAG_RWT 0x00000200U /*!< Receive watchdog timeout flag */
1416 #define ETH_DMA_FLAG_RPS 0x00000100U /*!< Receive process stopped flag */
1417 #define ETH_DMA_FLAG_RBU 0x00000080U /*!< Receive buffer unavailable flag */
1418 #define ETH_DMA_FLAG_R 0x00000040U /*!< Receive flag */
1419 #define ETH_DMA_FLAG_TU 0x00000020U /*!< Underflow flag */
1420 #define ETH_DMA_FLAG_RO 0x00000010U /*!< Overflow flag */
1421 #define ETH_DMA_FLAG_TJT 0x00000008U /*!< Transmit jabber timeout flag */
1422 #define ETH_DMA_FLAG_TBU 0x00000004U /*!< Transmit buffer unavailable flag */
1423 #define ETH_DMA_FLAG_TPS 0x00000002U /*!< Transmit process stopped flag */
1424 #define ETH_DMA_FLAG_T 0x00000001U /*!< Transmit flag */
1425 /**
1426 * @}
1427 */
1428
1429 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
1430 * @{
1431 */
1432 #define ETH_MAC_IT_TST 0x00000200U /*!< Time stamp trigger interrupt (on MAC) */
1433 #define ETH_MAC_IT_MMCT 0x00000040U /*!< MMC transmit interrupt */
1434 #define ETH_MAC_IT_MMCR 0x00000020U /*!< MMC receive interrupt */
1435 #define ETH_MAC_IT_MMC 0x00000010U /*!< MMC interrupt (on MAC) */
1436 #define ETH_MAC_IT_PMT 0x00000008U /*!< PMT interrupt (on MAC) */
1437 /**
1438 * @}
1439 */
1440
1441 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
1442 * @{
1443 */
1444 #define ETH_DMA_IT_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */
1445 #define ETH_DMA_IT_PMT 0x10000000U /*!< PMT interrupt (on DMA) */
1446 #define ETH_DMA_IT_MMC 0x08000000U /*!< MMC interrupt (on DMA) */
1447 #define ETH_DMA_IT_NIS 0x00010000U /*!< Normal interrupt summary */
1448 #define ETH_DMA_IT_AIS 0x00008000U /*!< Abnormal interrupt summary */
1449 #define ETH_DMA_IT_ER 0x00004000U /*!< Early receive interrupt */
1450 #define ETH_DMA_IT_FBE 0x00002000U /*!< Fatal bus error interrupt */
1451 #define ETH_DMA_IT_ET 0x00000400U /*!< Early transmit interrupt */
1452 #define ETH_DMA_IT_RWT 0x00000200U /*!< Receive watchdog timeout interrupt */
1453 #define ETH_DMA_IT_RPS 0x00000100U /*!< Receive process stopped interrupt */
1454 #define ETH_DMA_IT_RBU 0x00000080U /*!< Receive buffer unavailable interrupt */
1455 #define ETH_DMA_IT_R 0x00000040U /*!< Receive interrupt */
1456 #define ETH_DMA_IT_TU 0x00000020U /*!< Underflow interrupt */
1457 #define ETH_DMA_IT_RO 0x00000010U /*!< Overflow interrupt */
1458 #define ETH_DMA_IT_TJT 0x00000008U /*!< Transmit jabber timeout interrupt */
1459 #define ETH_DMA_IT_TBU 0x00000004U /*!< Transmit buffer unavailable interrupt */
1460 #define ETH_DMA_IT_TPS 0x00000002U /*!< Transmit process stopped interrupt */
1461 #define ETH_DMA_IT_T 0x00000001U /*!< Transmit interrupt */
1462 /**
1463 * @}
1464 */
1465
1466 /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
1467 * @{
1468 */
1469 #define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Tx Command issued */
1470 #define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U /*!< Running - fetching the Tx descriptor */
1471 #define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U /*!< Running - waiting for status */
1472 #define ETH_DMA_TRANSMITPROCESS_READING 0x00300000U /*!< Running - reading the data from host memory */
1473 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U /*!< Suspended - Tx Descriptor unavailable */
1474 #define ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U /*!< Running - closing Rx descriptor */
1475
1476 /**
1477 * @}
1478 */
1479
1480
1481 /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
1482 * @{
1483 */
1484 #define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Rx Command issued */
1485 #define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U /*!< Running - fetching the Rx descriptor */
1486 #define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U /*!< Running - waiting for packet */
1487 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U /*!< Suspended - Rx Descriptor unavailable */
1488 #define ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U /*!< Running - closing descriptor */
1489 #define ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U /*!< Running - queuing the receive frame into host memory */
1490
1491 /**
1492 * @}
1493 */
1494
1495 /** @defgroup ETH_DMA_overflow ETH DMA overflow
1496 * @{
1497 */
1498 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U /*!< Overflow bit for FIFO overflow counter */
1499 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U /*!< Overflow bit for missed frame counter */
1500 /**
1501 * @}
1502 */
1503
1504 /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
1505 * @{
1506 */
1507 #define ETH_EXTI_LINE_WAKEUP 0x00080000U /*!< External interrupt line 19 Connected to the ETH EXTI Line */
1508
1509 /**
1510 * @}
1511 */
1512
1513 /**
1514 * @}
1515 */
1516
1517 /* Exported macro ------------------------------------------------------------*/
1518 /** @defgroup ETH_Exported_Macros ETH Exported Macros
1519 * @brief macros to handle interrupts and specific clock configurations
1520 * @{
1521 */
1522
1523 /** @brief Reset ETH handle state
1524 * @param __HANDLE__: specifies the ETH handle.
1525 * @retval None
1526 */
1527 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
1528
1529 /**
1530 * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
1531 * @param __HANDLE__: ETH Handle
1532 * @param __FLAG__: specifies the flag of TDES0 to check.
1533 * @retval the ETH_DMATxDescFlag (SET or RESET).
1534 */
1535 #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
1536
1537 /**
1538 * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
1539 * @param __HANDLE__: ETH Handle
1540 * @param __FLAG__: specifies the flag of RDES0 to check.
1541 * @retval the ETH_DMATxDescFlag (SET or RESET).
1542 */
1543 #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
1544
1545 /**
1546 * @brief Enables the specified DMA Rx Desc receive interrupt.
1547 * @param __HANDLE__: ETH Handle
1548 * @retval None
1549 */
1550 #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
1551
1552 /**
1553 * @brief Disables the specified DMA Rx Desc receive interrupt.
1554 * @param __HANDLE__: ETH Handle
1555 * @retval None
1556 */
1557 #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
1558
1559 /**
1560 * @brief Set the specified DMA Rx Desc Own bit.
1561 * @param __HANDLE__: ETH Handle
1562 * @retval None
1563 */
1564 #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
1565
1566 /**
1567 * @brief Returns the specified ETHERNET DMA Tx Desc collision count.
1568 * @param __HANDLE__: ETH Handle
1569 * @retval The Transmit descriptor collision counter value.
1570 */
1571 #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
1572
1573 /**
1574 * @brief Set the specified DMA Tx Desc Own bit.
1575 * @param __HANDLE__: ETH Handle
1576 * @retval None
1577 */
1578 #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
1579
1580 /**
1581 * @brief Enables the specified DMA Tx Desc Transmit interrupt.
1582 * @param __HANDLE__: ETH Handle
1583 * @retval None
1584 */
1585 #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
1586
1587 /**
1588 * @brief Disables the specified DMA Tx Desc Transmit interrupt.
1589 * @param __HANDLE__: ETH Handle
1590 * @retval None
1591 */
1592 #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
1593
1594 /**
1595 * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
1596 * @param __HANDLE__: ETH Handle
1597 * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
1598 * This parameter can be one of the following values:
1599 * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
1600 * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
1601 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
1602 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
1603 * @retval None
1604 */
1605 #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
1606
1607 /**
1608 * @brief Enables the DMA Tx Desc CRC.
1609 * @param __HANDLE__: ETH Handle
1610 * @retval None
1611 */
1612 #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
1613
1614 /**
1615 * @brief Disables the DMA Tx Desc CRC.
1616 * @param __HANDLE__: ETH Handle
1617 * @retval None
1618 */
1619 #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
1620
1621 /**
1622 * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
1623 * @param __HANDLE__: ETH Handle
1624 * @retval None
1625 */
1626 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
1627
1628 /**
1629 * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
1630 * @param __HANDLE__: ETH Handle
1631 * @retval None
1632 */
1633 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
1634
1635 /**
1636 * @brief Enables the specified ETHERNET MAC interrupts.
1637 * @param __HANDLE__ : ETH Handle
1638 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
1639 * enabled or disabled.
1640 * This parameter can be any combination of the following values:
1641 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
1642 * @arg ETH_MAC_IT_PMT : PMT interrupt
1643 * @retval None
1644 */
1645 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
1646
1647 /**
1648 * @brief Disables the specified ETHERNET MAC interrupts.
1649 * @param __HANDLE__ : ETH Handle
1650 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
1651 * enabled or disabled.
1652 * This parameter can be any combination of the following values:
1653 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
1654 * @arg ETH_MAC_IT_PMT : PMT interrupt
1655 * @retval None
1656 */
1657 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
1658
1659 /**
1660 * @brief Initiate a Pause Control Frame (Full-duplex only).
1661 * @param __HANDLE__: ETH Handle
1662 * @retval None
1663 */
1664 #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
1665
1666 /**
1667 * @brief Checks whether the ETHERNET flow control busy bit is set or not.
1668 * @param __HANDLE__: ETH Handle
1669 * @retval The new state of flow control busy status bit (SET or RESET).
1670 */
1671 #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
1672
1673 /**
1674 * @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
1675 * @param __HANDLE__: ETH Handle
1676 * @retval None
1677 */
1678 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
1679
1680 /**
1681 * @brief Disables the MAC BackPressure operation activation (Half-duplex only).
1682 * @param __HANDLE__: ETH Handle
1683 * @retval None
1684 */
1685 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
1686
1687 /**
1688 * @brief Checks whether the specified ETHERNET MAC flag is set or not.
1689 * @param __HANDLE__: ETH Handle
1690 * @param __FLAG__: specifies the flag to check.
1691 * This parameter can be one of the following values:
1692 * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
1693 * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
1694 * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
1695 * @arg ETH_MAC_FLAG_MMC : MMC flag
1696 * @arg ETH_MAC_FLAG_PMT : PMT flag
1697 * @retval The state of ETHERNET MAC flag.
1698 */
1699 #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
1700
1701 /**
1702 * @brief Enables the specified ETHERNET DMA interrupts.
1703 * @param __HANDLE__ : ETH Handle
1704 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
1705 * enabled @ref ETH_DMA_Interrupts
1706 * @retval None
1707 */
1708 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
1709
1710 /**
1711 * @brief Disables the specified ETHERNET DMA interrupts.
1712 * @param __HANDLE__ : ETH Handle
1713 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
1714 * disabled. @ref ETH_DMA_Interrupts
1715 * @retval None
1716 */
1717 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
1718
1719 /**
1720 * @brief Clears the ETHERNET DMA IT pending bit.
1721 * @param __HANDLE__ : ETH Handle
1722 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
1723 * @retval None
1724 */
1725 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
1726
1727 /**
1728 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
1729 * @param __HANDLE__: ETH Handle
1730 * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
1731 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
1732 */
1733 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
1734
1735 /**
1736 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
1737 * @param __HANDLE__: ETH Handle
1738 * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
1739 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
1740 */
1741 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
1742
1743 /**
1744 * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
1745 * @param __HANDLE__: ETH Handle
1746 * @param __OVERFLOW__: specifies the DMA overflow flag to check.
1747 * This parameter can be one of the following values:
1748 * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
1749 * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
1750 * @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
1751 */
1752 #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
1753
1754 /**
1755 * @brief Set the DMA Receive status watchdog timer register value
1756 * @param __HANDLE__: ETH Handle
1757 * @param __VALUE__: DMA Receive status watchdog timer register value
1758 * @retval None
1759 */
1760 #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
1761
1762 /**
1763 * @brief Enables any unicast packet filtered by the MAC address
1764 * recognition to be a wake-up frame.
1765 * @param __HANDLE__: ETH Handle.
1766 * @retval None
1767 */
1768 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
1769
1770 /**
1771 * @brief Disables any unicast packet filtered by the MAC address
1772 * recognition to be a wake-up frame.
1773 * @param __HANDLE__: ETH Handle.
1774 * @retval None
1775 */
1776 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
1777
1778 /**
1779 * @brief Enables the MAC Wake-Up Frame Detection.
1780 * @param __HANDLE__: ETH Handle.
1781 * @retval None
1782 */
1783 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
1784
1785 /**
1786 * @brief Disables the MAC Wake-Up Frame Detection.
1787 * @param __HANDLE__: ETH Handle.
1788 * @retval None
1789 */
1790 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
1791
1792 /**
1793 * @brief Enables the MAC Magic Packet Detection.
1794 * @param __HANDLE__: ETH Handle.
1795 * @retval None
1796 */
1797 #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
1798
1799 /**
1800 * @brief Disables the MAC Magic Packet Detection.
1801 * @param __HANDLE__: ETH Handle.
1802 * @retval None
1803 */
1804 #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
1805
1806 /**
1807 * @brief Enables the MAC Power Down.
1808 * @param __HANDLE__: ETH Handle
1809 * @retval None
1810 */
1811 #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
1812
1813 /**
1814 * @brief Disables the MAC Power Down.
1815 * @param __HANDLE__: ETH Handle
1816 * @retval None
1817 */
1818 #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
1819
1820 /**
1821 * @brief Checks whether the specified ETHERNET PMT flag is set or not.
1822 * @param __HANDLE__: ETH Handle.
1823 * @param __FLAG__: specifies the flag to check.
1824 * This parameter can be one of the following values:
1825 * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
1826 * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
1827 * @arg ETH_PMT_FLAG_MPR : Magic Packet Received
1828 * @retval The new state of ETHERNET PMT Flag (SET or RESET).
1829 */
1830 #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
1831
1832 /**
1833 * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
1834 * @param __HANDLE__: ETH Handle.
1835 * @retval None
1836 */
1837 #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
1838
1839 /**
1840 * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
1841 * @param __HANDLE__: ETH Handle.
1842 * @retval None
1843 */
1844 #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
1845 (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while(0U)
1846
1847 /**
1848 * @brief Enables the MMC Counter Freeze.
1849 * @param __HANDLE__: ETH Handle.
1850 * @retval None
1851 */
1852 #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
1853
1854 /**
1855 * @brief Disables the MMC Counter Freeze.
1856 * @param __HANDLE__: ETH Handle.
1857 * @retval None
1858 */
1859 #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
1860
1861 /**
1862 * @brief Enables the MMC Reset On Read.
1863 * @param __HANDLE__: ETH Handle.
1864 * @retval None
1865 */
1866 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
1867
1868 /**
1869 * @brief Disables the MMC Reset On Read.
1870 * @param __HANDLE__: ETH Handle.
1871 * @retval None
1872 */
1873 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
1874
1875 /**
1876 * @brief Enables the MMC Counter Stop Rollover.
1877 * @param __HANDLE__: ETH Handle.
1878 * @retval None
1879 */
1880 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
1881
1882 /**
1883 * @brief Disables the MMC Counter Stop Rollover.
1884 * @param __HANDLE__: ETH Handle.
1885 * @retval None
1886 */
1887 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
1888
1889 /**
1890 * @brief Resets the MMC Counters.
1891 * @param __HANDLE__: ETH Handle.
1892 * @retval None
1893 */
1894 #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
1895
1896 /**
1897 * @brief Enables the specified ETHERNET MMC Rx interrupts.
1898 * @param __HANDLE__: ETH Handle.
1899 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
1900 * This parameter can be one of the following values:
1901 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
1902 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
1903 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
1904 * @retval None
1905 */
1906 #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU)
1907 /**
1908 * @brief Disables the specified ETHERNET MMC Rx interrupts.
1909 * @param __HANDLE__: ETH Handle.
1910 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
1911 * This parameter can be one of the following values:
1912 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
1913 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
1914 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
1915 * @retval None
1916 */
1917 #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU)
1918 /**
1919 * @brief Enables the specified ETHERNET MMC Tx interrupts.
1920 * @param __HANDLE__: ETH Handle.
1921 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
1922 * This parameter can be one of the following values:
1923 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
1924 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
1925 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
1926 * @retval None
1927 */
1928 #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
1929
1930 /**
1931 * @brief Disables the specified ETHERNET MMC Tx interrupts.
1932 * @param __HANDLE__: ETH Handle.
1933 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
1934 * This parameter can be one of the following values:
1935 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
1936 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
1937 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
1938 * @retval None
1939 */
1940 #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
1941
1942 /**
1943 * @brief Enables the ETH External interrupt line.
1944 * @retval None
1945 */
1946 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
1947
1948 /**
1949 * @brief Disables the ETH External interrupt line.
1950 * @retval None
1951 */
1952 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
1953
1954 /**
1955 * @brief Enable event on ETH External event line.
1956 * @retval None.
1957 */
1958 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
1959
1960 /**
1961 * @brief Disable event on ETH External event line
1962 * @retval None.
1963 */
1964 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
1965
1966 /**
1967 * @brief Get flag of the ETH External interrupt line.
1968 * @retval None
1969 */
1970 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
1971
1972 /**
1973 * @brief Clear flag of the ETH External interrupt line.
1974 * @retval None
1975 */
1976 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
1977
1978 /**
1979 * @brief Enables rising edge trigger to the ETH External interrupt line.
1980 * @retval None
1981 */
1982 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
1983
1984 /**
1985 * @brief Disables the rising edge trigger to the ETH External interrupt line.
1986 * @retval None
1987 */
1988 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
1989
1990 /**
1991 * @brief Enables falling edge trigger to the ETH External interrupt line.
1992 * @retval None
1993 */
1994 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
1995
1996 /**
1997 * @brief Disables falling edge trigger to the ETH External interrupt line.
1998 * @retval None
1999 */
2000 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
2001
2002 /**
2003 * @brief Enables rising/falling edge trigger to the ETH External interrupt line.
2004 * @retval None
2005 */
2006 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
2007 EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\
2008 }while(0U)
2009
2010 /**
2011 * @brief Disables rising/falling edge trigger to the ETH External interrupt line.
2012 * @retval None
2013 */
2014 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
2015 EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
2016 }while(0U)
2017
2018 /**
2019 * @brief Generate a Software interrupt on selected EXTI line.
2020 * @retval None.
2021 */
2022 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
2023
2024 /**
2025 * @}
2026 */
2027 /* Exported functions --------------------------------------------------------*/
2028
2029 /** @addtogroup ETH_Exported_Functions
2030 * @{
2031 */
2032
2033 /* Initialization and de-initialization functions ****************************/
2034
2035 /** @addtogroup ETH_Exported_Functions_Group1
2036 * @{
2037 */
2038 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
2039 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
2040 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
2041 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
2042 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
2043 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
2044
2045 /**
2046 * @}
2047 */
2048 /* IO operation functions ****************************************************/
2049
2050 /** @addtogroup ETH_Exported_Functions_Group2
2051 * @{
2052 */
2053 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
2054 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
2055 /* Communication with PHY functions*/
2056 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
2057 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
2058 /* Non-Blocking mode: Interrupt */
2059 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
2060 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
2061 /* Callback in non blocking modes (Interrupt) */
2062 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
2063 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
2064 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
2065 /**
2066 * @}
2067 */
2068
2069 /* Peripheral Control functions **********************************************/
2070
2071 /** @addtogroup ETH_Exported_Functions_Group3
2072 * @{
2073 */
2074
2075 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
2076 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
2077 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
2078 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
2079 /**
2080 * @}
2081 */
2082
2083 /* Peripheral State functions ************************************************/
2084
2085 /** @addtogroup ETH_Exported_Functions_Group4
2086 * @{
2087 */
2088 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
2089 /**
2090 * @}
2091 */
2092
2093 /**
2094 * @}
2095 */
2096
2097 /**
2098 * @}
2099 */
2100
2101 #endif /* STM32F107xC */
2102 /**
2103 * @}
2104 */
2105
2106 #ifdef __cplusplus
2107 }
2108 #endif
2109
2110 #endif /* __STM32F1xx_HAL_ETH_H */
2111
2112
2113 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/