Merge pull request #11270 from haslinghuis/rename_attr
[betaflight.git] / lib / main / STM32F1 / Drivers / STM32F1xx_HAL_Driver / Inc / stm32f1xx_hal_sram.h
blob552d65af518e0f06cc63d754a02b03e882ba121b
1 /**
2 ******************************************************************************
3 * @file stm32f1xx_hal_sram.h
4 * @author MCD Application Team
5 * @version V1.1.1
6 * @date 12-May-2017
7 * @brief Header file of SRAM HAL module.
8 ******************************************************************************
9 * @attention
11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 ******************************************************************************
36 */
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F1xx_HAL_SRAM_H
40 #define __STM32F1xx_HAL_SRAM_H
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f1xx_ll_fsmc.h"
49 /** @addtogroup STM32F1xx_HAL_Driver
50 * @{
53 #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
55 /** @addtogroup SRAM
56 * @{
57 */
59 /* Exported typedef ----------------------------------------------------------*/
61 /** @defgroup SRAM_Exported_Types SRAM Exported Types
62 * @{
63 */
64 /**
65 * @brief HAL SRAM State structures definition
66 */
67 typedef enum
69 HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */
70 HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */
71 HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */
72 HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */
73 HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */
75 }HAL_SRAM_StateTypeDef;
77 /**
78 * @brief SRAM handle Structure definition
79 */
80 typedef struct
82 FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
84 FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
86 FSMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
88 HAL_LockTypeDef Lock; /*!< SRAM locking object */
90 __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
92 DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
94 }SRAM_HandleTypeDef;
96 /**
97 * @}
98 */
100 /* Exported constants --------------------------------------------------------*/
101 /* Exported macro ------------------------------------------------------------*/
103 /** @defgroup SRAM_Exported_Macros SRAM Exported Macros
104 * @{
107 /** @brief Reset SRAM handle state
108 * @param __HANDLE__: SRAM handle
109 * @retval None
111 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
114 * @}
117 /* Exported functions --------------------------------------------------------*/
119 /** @addtogroup SRAM_Exported_Functions
120 * @{
123 /** @addtogroup SRAM_Exported_Functions_Group1
124 * @{
127 /* Initialization/de-initialization functions **********************************/
128 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming);
129 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
130 void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
131 void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
133 void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
134 void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
137 * @}
140 /** @addtogroup SRAM_Exported_Functions_Group2
141 * @{
144 /* I/O operation functions *****************************************************/
145 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
146 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
147 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
148 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
149 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
150 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
151 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
152 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
155 * @}
158 /** @addtogroup SRAM_Exported_Functions_Group3
159 * @{
162 /* SRAM Control functions ******************************************************/
163 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
164 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
167 * @}
170 /** @addtogroup SRAM_Exported_Functions_Group4
171 * @{
174 /* SRAM State functions *********************************************************/
175 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
178 * @}
182 * @}
186 * @}
189 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
192 * @}
195 #ifdef __cplusplus
197 #endif
199 #endif /* __STM32F1xx_HAL_SRAM_H */
201 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/