lib/main/STM32F1/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f1xx_ll_fsmc.h
   4   * @author  MCD Application Team
   5   * @version V1.1.1
   6   * @date    12-May-2017
   7   * @brief   Header file of FSMC HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F1xx_LL_FSMC_H
  40 #define __STM32F1xx_LL_FSMC_H
  41
  42 #ifdef __cplusplus
  43 extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32f1xx_hal_def.h"
  48
  49 /** @addtogroup STM32F1xx_HAL_Driver
  50   * @{
  51   */
  52
  53 #if defined(FSMC_BANK1)
  54
  55 /** @addtogroup FSMC_LL
  56   * @{
  57   */
  58
  59
  60 /* Exported typedef ----------------------------------------------------------*/
  61
  62 /** @defgroup FSMC_NORSRAM_Exported_typedef FSMC Low Layer Exported Types
  63   * @{
  64   */
  65
  66 /**
  67   * @brief FSMC NORSRAM Configuration Structure definition
  68   */
  69 typedef struct
  70 {
  71   uint32_t NSBank;                       /*!< Specifies the NORSRAM memory device that will be used.
  72                                               This parameter can be a value of @ref FSMC_NORSRAM_Bank                     */
  73
  74   uint32_t DataAddressMux;               /*!< Specifies whether the address and data values are
  75                                               multiplexed on the data bus or not.
  76                                               This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing    */
  77
  78   uint32_t MemoryType;                   /*!< Specifies the type of external memory attached to
  79                                               the corresponding memory device.
  80                                               This parameter can be a value of @ref FSMC_Memory_Type                      */
  81
  82   uint32_t MemoryDataWidth;              /*!< Specifies the external memory device width.
  83                                               This parameter can be a value of @ref FSMC_NORSRAM_Data_Width               */
  84
  85   uint32_t BurstAccessMode;              /*!< Enables or disables the burst access mode for Flash memory,
  86                                               valid only with synchronous burst Flash memories.
  87                                               This parameter can be a value of @ref FSMC_Burst_Access_Mode                */
  88
  89   uint32_t WaitSignalPolarity;           /*!< Specifies the wait signal polarity, valid only when accessing
  90                                               the Flash memory in burst mode.
  91                                               This parameter can be a value of @ref FSMC_Wait_Signal_Polarity             */
  92
  93   uint32_t WrapMode;                     /*!< Enables or disables the Wrapped burst access mode for Flash
  94                                               memory, valid only when accessing Flash memories in burst mode.
  95                                               This parameter can be a value of @ref FSMC_Wrap_Mode                        */
  96
  97   uint32_t WaitSignalActive;             /*!< Specifies if the wait signal is asserted by the memory one
  98                                               clock cycle before the wait state or during the wait state,
  99                                               valid only when accessing memories in burst mode.
 100                                               This parameter can be a value of @ref FSMC_Wait_Timing                      */
 101
 102   uint32_t WriteOperation;               /*!< Enables or disables the write operation in the selected device by the FSMC.
 103                                               This parameter can be a value of @ref FSMC_Write_Operation                  */
 104
 105   uint32_t WaitSignal;                   /*!< Enables or disables the wait state insertion via wait
 106                                               signal, valid for Flash memory access in burst mode.
 107                                               This parameter can be a value of @ref FSMC_Wait_Signal                      */
 108
 109   uint32_t ExtendedMode;                 /*!< Enables or disables the extended mode.
 110                                               This parameter can be a value of @ref FSMC_Extended_Mode                    */
 111
 112   uint32_t AsynchronousWait;             /*!< Enables or disables wait signal during asynchronous transfers,
 113                                               valid only with asynchronous Flash memories.
 114                                               This parameter can be a value of @ref FSMC_AsynchronousWait                 */
 115
 116   uint32_t WriteBurst;                   /*!< Enables or disables the write burst operation.
 117                                               This parameter can be a value of @ref FSMC_Write_Burst                      */
 118
 119 }FSMC_NORSRAM_InitTypeDef;
 120
 121 /**
 122   * @brief FSMC NORSRAM Timing parameters structure definition
 123   */
 124 typedef struct
 125 {
 126   uint32_t AddressSetupTime;             /*!< Defines the number of HCLK cycles to configure
 127                                               the duration of the address setup time.
 128                                               This parameter can be a value between Min_Data = 0 and Max_Data = 15.
 129                                               @note This parameter is not used with synchronous NOR Flash memories.      */
 130
 131   uint32_t AddressHoldTime;              /*!< Defines the number of HCLK cycles to configure
 132                                               the duration of the address hold time.
 133                                               This parameter can be a value between Min_Data = 1 and Max_Data = 15.
 134                                               @note This parameter is not used with synchronous NOR Flash memories.      */
 135
 136   uint32_t DataSetupTime;                /*!< Defines the number of HCLK cycles to configure
 137                                               the duration of the data setup time.
 138                                               This parameter can be a value between Min_Data = 1 and Max_Data = 255.
 139                                               @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
 140                                               NOR Flash memories.                                                        */
 141
 142   uint32_t BusTurnAroundDuration;        /*!< Defines the number of HCLK cycles to configure
 143                                               the duration of the bus turnaround.
 144                                               This parameter can be a value between Min_Data = 0 and Max_Data = 15.
 145                                               @note This parameter is only used for multiplexed NOR Flash memories.      */
 146
 147   uint32_t CLKDivision;                  /*!< Defines the period of CLK clock output signal, expressed in number of
 148                                               HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
 149                                               @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
 150                                               accesses.                                                                  */
 151
 152   uint32_t DataLatency;                  /*!< Defines the number of memory clock cycles to issue
 153                                               to the memory before getting the first data.
 154                                               The parameter value depends on the memory type as shown below:
 155                                               - It must be set to 0 in case of a CRAM
 156                                               - It is don't care in asynchronous NOR, SRAM or ROM accesses
 157                                               - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
 158                                                 with synchronous burst mode enable                                       */
 159
 160   uint32_t AccessMode;                   /*!< Specifies the asynchronous access mode.
 161                                               This parameter can be a value of @ref FSMC_Access_Mode                     */
 162
 163 }FSMC_NORSRAM_TimingTypeDef;
 164
 165 #if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
 166 /**
 167   * @brief FSMC NAND Configuration Structure definition
 168   */
 169 typedef struct
 170 {
 171   uint32_t NandBank;               /*!< Specifies the NAND memory device that will be used.
 172                                         This parameter can be a value of @ref FSMC_NAND_Bank                   */
 173
 174   uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the NAND Memory device.
 175                                         This parameter can be any value of @ref FSMC_Wait_feature              */
 176
 177   uint32_t MemoryDataWidth;        /*!< Specifies the external memory device width.
 178                                         This parameter can be any value of @ref FSMC_NAND_Data_Width           */
 179
 180   uint32_t EccComputation;         /*!< Enables or disables the ECC computation.
 181                                         This parameter can be any value of @ref FSMC_ECC                       */
 182
 183   uint32_t ECCPageSize;            /*!< Defines the page size for the extended ECC.
 184                                         This parameter can be any value of @ref FSMC_ECC_Page_Size             */
 185
 186   uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the
 187                                         delay between CLE low and RE low.
 188                                         This parameter can be a value between Min_Data = 0 and Max_Data = 255  */
 189
 190   uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the
 191                                         delay between ALE low and RE low.
 192                                         This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
 193
 194 }FSMC_NAND_InitTypeDef;
 195
 196 /**
 197   * @brief FSMC NAND/PCCARD Timing parameters structure definition
 198   */
 199 typedef struct
 200 {
 201   uint32_t SetupTime;            /*!< Defines the number of HCLK cycles to setup address before
 202                                       the command assertion for NAND-Flash read or write access
 203                                       to common/Attribute or I/O memory space (depending on
 204                                       the memory space timing to be configured).
 205                                       This parameter can be a value between Min_Data = 0 and Max_Data = 255    */
 206
 207   uint32_t WaitSetupTime;        /*!< Defines the minimum number of HCLK cycles to assert the
 208                                       command for NAND-Flash read or write access to
 209                                       common/Attribute or I/O memory space (depending on the
 210                                       memory space timing to be configured).
 211                                       This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
 212
 213   uint32_t HoldSetupTime;        /*!< Defines the number of HCLK clock cycles to hold address
 214                                       (and data for write access) after the command de-assertion
 215                                       for NAND-Flash read or write access to common/Attribute
 216                                       or I/O memory space (depending on the memory space timing
 217                                       to be configured).
 218                                       This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
 219
 220   uint32_t HiZSetupTime;         /*!< Defines the number of HCLK clock cycles during which the
 221                                       data bus is kept in HiZ after the start of a NAND-Flash
 222                                       write access to common/Attribute or I/O memory space (depending
 223                                       on the memory space timing to be configured).
 224                                       This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
 225
 226 }FSMC_NAND_PCC_TimingTypeDef;
 227
 228 /**
 229   * @brief  FSMC NAND Configuration Structure definition
 230   */
 231 typedef struct
 232 {
 233   uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the PCCARD Memory device.
 234                                         This parameter can be any value of @ref FSMC_Wait_feature              */
 235
 236   uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the
 237                                         delay between CLE low and RE low.
 238                                         This parameter can be a value between Min_Data = 0 and Max_Data = 255  */
 239
 240   uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the
 241                                         delay between ALE low and RE low.
 242                                         This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
 243
 244 }FSMC_PCCARD_InitTypeDef;
 245 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
 246 /**
 247   * @}
 248   */
 249
 250 /* Exported constants --------------------------------------------------------*/
 251
 252 /** @defgroup FSMC_Exported_Constants FSMC Low Layer Exported Constants
 253   * @{
 254   */
 255
 256 /** @defgroup FSMC_NORSRAM_Exported_constants FSMC NOR/SRAM Exported constants
 257   * @{
 258   */
 259 /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
 260   * @{
 261   */
 262 #define FSMC_NORSRAM_BANK1                       0x00000000U
 263 #define FSMC_NORSRAM_BANK2                       0x00000002U
 264 #define FSMC_NORSRAM_BANK3                       0x00000004U
 265 #define FSMC_NORSRAM_BANK4                       0x00000006U
 266 /**
 267   * @}
 268   */
 269
 270 /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
 271   * @{
 272   */
 273 #define FSMC_DATA_ADDRESS_MUX_DISABLE            0x00000000U
 274 #define FSMC_DATA_ADDRESS_MUX_ENABLE             ((uint32_t)FSMC_BCRx_MUXEN)
 275 /**
 276   * @}
 277   */
 278
 279 /** @defgroup FSMC_Memory_Type FSMC Memory Type
 280   * @{
 281   */
 282 #define FSMC_MEMORY_TYPE_SRAM                    0x00000000U
 283 #define FSMC_MEMORY_TYPE_PSRAM                   ((uint32_t)FSMC_BCRx_MTYP_0)
 284 #define FSMC_MEMORY_TYPE_NOR                     ((uint32_t)FSMC_BCRx_MTYP_1)
 285 /**
 286   * @}
 287   */
 288
 289 /** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
 290   * @{
 291   */
 292 #define FSMC_NORSRAM_MEM_BUS_WIDTH_8             0x00000000U
 293 #define FSMC_NORSRAM_MEM_BUS_WIDTH_16            ((uint32_t)FSMC_BCRx_MWID_0)
 294 #define FSMC_NORSRAM_MEM_BUS_WIDTH_32            ((uint32_t)FSMC_BCRx_MWID_1)
 295 /**
 296   * @}
 297   */
 298
 299 /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
 300   * @{
 301   */
 302 #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE         ((uint32_t)FSMC_BCRx_FACCEN)
 303 #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE        0x00000000U
 304 /**
 305   * @}
 306   */
 307
 308 /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
 309   * @{
 310   */
 311 #define FSMC_BURST_ACCESS_MODE_DISABLE           0x00000000U
 312 #define FSMC_BURST_ACCESS_MODE_ENABLE            ((uint32_t)FSMC_BCRx_BURSTEN)
 313 /**
 314   * @}
 315   */
 316
 317 /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
 318   * @{
 319   */
 320 #define FSMC_WAIT_SIGNAL_POLARITY_LOW            0x00000000U
 321 #define FSMC_WAIT_SIGNAL_POLARITY_HIGH           ((uint32_t)FSMC_BCRx_WAITPOL)
 322 /**
 323   * @}
 324   */
 325
 326 /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
 327   * @{
 328   */
 329 #define FSMC_WRAP_MODE_DISABLE                   0x00000000U
 330 #define FSMC_WRAP_MODE_ENABLE                    ((uint32_t)FSMC_BCRx_WRAPMOD)
 331 /**
 332   * @}
 333   */
 334
 335 /** @defgroup FSMC_Wait_Timing FSMC Wait Timing
 336   * @{
 337   */
 338 #define FSMC_WAIT_TIMING_BEFORE_WS               0x00000000U
 339 #define FSMC_WAIT_TIMING_DURING_WS               ((uint32_t)FSMC_BCRx_WAITCFG)
 340 /**
 341   * @}
 342   */
 343
 344 /** @defgroup FSMC_Write_Operation FSMC Write Operation
 345   * @{
 346   */
 347 #define FSMC_WRITE_OPERATION_DISABLE             0x00000000U
 348 #define FSMC_WRITE_OPERATION_ENABLE              ((uint32_t)FSMC_BCRx_WREN)
 349 /**
 350   * @}
 351   */
 352
 353 /** @defgroup FSMC_Wait_Signal FSMC Wait Signal
 354   * @{
 355   */
 356 #define FSMC_WAIT_SIGNAL_DISABLE                 0x00000000U
 357 #define FSMC_WAIT_SIGNAL_ENABLE                  ((uint32_t)FSMC_BCRx_WAITEN)
 358 /**
 359   * @}
 360   */
 361
 362 /** @defgroup FSMC_Extended_Mode FSMC Extended Mode
 363   * @{
 364   */
 365 #define FSMC_EXTENDED_MODE_DISABLE               0x00000000U
 366 #define FSMC_EXTENDED_MODE_ENABLE                ((uint32_t)FSMC_BCRx_EXTMOD)
 367 /**
 368   * @}
 369   */
 370
 371 /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
 372   * @{
 373   */
 374 #define FSMC_ASYNCHRONOUS_WAIT_DISABLE           0x00000000U
 375 #define FSMC_ASYNCHRONOUS_WAIT_ENABLE            ((uint32_t)FSMC_BCRx_ASYNCWAIT)
 376 /**
 377   * @}
 378   */
 379
 380 /** @defgroup FSMC_Write_Burst FSMC Write Burst
 381   * @{
 382   */
 383 #define FSMC_WRITE_BURST_DISABLE                 0x00000000U
 384 #define FSMC_WRITE_BURST_ENABLE                  ((uint32_t)FSMC_BCRx_CBURSTRW)
 385 /**
 386   * @}
 387   */
 388
 389 /** @defgroup FSMC_Access_Mode FSMC Access Mode
 390   * @{
 391   */
 392 #define FSMC_ACCESS_MODE_A                        0x00000000U
 393 #define FSMC_ACCESS_MODE_B                        ((uint32_t)FSMC_BTRx_ACCMOD_0)
 394 #define FSMC_ACCESS_MODE_C                        ((uint32_t)FSMC_BTRx_ACCMOD_1)
 395 #define FSMC_ACCESS_MODE_D                        ((uint32_t)(FSMC_BTRx_ACCMOD_0 | FSMC_BTRx_ACCMOD_1))
 396 /**
 397   * @}
 398   */
 399
 400 /**
 401   * @}
 402   */
 403
 404 #if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
 405 /** @defgroup FSMC_NAND_Controller FSMC NAND and PCCARD Controller
 406   * @{
 407   */
 408 /** @defgroup FSMC_NAND_Bank FSMC NAND Bank
 409   * @{
 410   */
 411 #define FSMC_NAND_BANK2                          0x00000010U
 412 #define FSMC_NAND_BANK3                          0x00000100U
 413 /**
 414   * @}
 415   */
 416
 417 /** @defgroup FSMC_Wait_feature FSMC Wait feature
 418   * @{
 419   */
 420 #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE           0x00000000U
 421 #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE            ((uint32_t)FSMC_PCRx_PWAITEN)
 422 /**
 423   * @}
 424   */
 425
 426 /** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
 427   * @{
 428   */
 429 #define FSMC_PCR_MEMORY_TYPE_PCCARD        0x00000000U
 430 #define FSMC_PCR_MEMORY_TYPE_NAND          ((uint32_t)FSMC_PCRx_PTYP)
 431 /**
 432   * @}
 433   */
 434
 435 /** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
 436   * @{
 437   */
 438 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8                0x00000000U
 439 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16               ((uint32_t)FSMC_PCRx_PWID_0)
 440 /**
 441   * @}
 442   */
 443
 444 /** @defgroup FSMC_ECC FSMC NAND ECC
 445   * @{
 446   */
 447 #define FSMC_NAND_ECC_DISABLE                    0x00000000U
 448 #define FSMC_NAND_ECC_ENABLE                     ((uint32_t)FSMC_PCRx_ECCEN)
 449 /**
 450   * @}
 451   */
 452
 453 /** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
 454   * @{
 455   */
 456 #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE          0x00000000U
 457 #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE          ((uint32_t)FSMC_PCRx_ECCPS_0)
 458 #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE         ((uint32_t)FSMC_PCRx_ECCPS_1)
 459 #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE         ((uint32_t)FSMC_PCRx_ECCPS_0|FSMC_PCRx_ECCPS_1)
 460 #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE         ((uint32_t)FSMC_PCRx_ECCPS_2)
 461 #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE         ((uint32_t)FSMC_PCRx_ECCPS_0|FSMC_PCRx_ECCPS_2)
 462 /**
 463   * @}
 464   */
 465
 466 /**
 467   * @}
 468   */
 469 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
 470
 471 /** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition
 472   * @brief FSMC Interrupt definition
 473   * @{
 474   */
 475 #define FSMC_IT_RISING_EDGE                ((uint32_t)FSMC_SRx_IREN)
 476 #define FSMC_IT_LEVEL                      ((uint32_t)FSMC_SRx_ILEN)
 477 #define FSMC_IT_FALLING_EDGE               ((uint32_t)FSMC_SRx_IFEN)
 478 /**
 479   * @}
 480   */
 481
 482 /** @defgroup FSMC_LL_Flag_definition FSMC Flag definition
 483   * @brief FSMC Flag definition
 484   * @{
 485   */
 486 #define FSMC_FLAG_RISING_EDGE                    ((uint32_t)FSMC_SRx_IRS)
 487 #define FSMC_FLAG_LEVEL                          ((uint32_t)FSMC_SRx_ILS)
 488 #define FSMC_FLAG_FALLING_EDGE                   ((uint32_t)FSMC_SRx_IFS)
 489 #define FSMC_FLAG_FEMPT                          ((uint32_t)FSMC_SRx_FEMPT)
 490 /**
 491   * @}
 492   */
 493
 494 /** @defgroup FSMC_LL_Alias_definition  FSMC Alias definition
 495   * @{
 496   */
 497 #define FSMC_NORSRAM_TypeDef            FSMC_Bank1_TypeDef
 498 #define FSMC_NORSRAM_EXTENDED_TypeDef   FSMC_Bank1E_TypeDef
 499 #define FSMC_NAND_TypeDef               FSMC_Bank2_3_TypeDef
 500 #define FSMC_PCCARD_TypeDef             FSMC_Bank4_TypeDef
 501
 502 #define FSMC_NORSRAM_DEVICE             FSMC_Bank1
 503 #define FSMC_NORSRAM_EXTENDED_DEVICE    FSMC_Bank1E
 504 #define FSMC_NAND_DEVICE                FSMC_Bank2_3
 505 #define FSMC_PCCARD_DEVICE              FSMC_Bank4
 506 /**
 507   * @}
 508   */
 509
 510 /**
 511   * @}
 512   */
 513
 514 /* Exported macro ------------------------------------------------------------*/
 515 /** @defgroup FSMC_Exported_Macros FSMC Low Layer Exported Macros
 516   * @{
 517   */
 518
 519 /** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros
 520   *  @brief macros to handle NOR device enable/disable and read/write operations
 521   *  @{
 522   */
 523
 524 /**
 525   * @brief  Enable the NORSRAM device access.
 526   * @param  __INSTANCE__: FSMC_NORSRAM Instance
 527   * @param  __BANK__: FSMC_NORSRAM Bank
 528   * @retval none
 529   */
 530 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__)  SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN)
 531
 532 /**
 533   * @brief  Disable the NORSRAM device access.
 534   * @param  __INSTANCE__: FSMC_NORSRAM Instance
 535   * @param  __BANK__: FSMC_NORSRAM Bank
 536   * @retval none
 537   */
 538 #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN)
 539
 540 /**
 541   * @}
 542   */
 543
 544 #if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
 545 /** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
 546   *  @brief macros to handle NAND device enable/disable
 547   *  @{
 548   */
 549
 550 /**
 551   * @brief  Enable the NAND device access.
 552   * @param  __INSTANCE__: FSMC_NAND Instance
 553   * @param  __BANK__: FSMC_NAND Bank
 554   * @retval None
 555   */
 556 #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__)  (((__BANK__) == FSMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \
 557                                                                                       SET_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))
 558
 559 /**
 560   * @brief  Disable the NAND device access.
 561   * @param  __INSTANCE__: FSMC_NAND Instance
 562   * @param  __BANK__: FSMC_NAND Bank
 563   * @retval None
 564   */
 565 #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \
 566                                                                                       CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))
 567 /**
 568   * @}
 569   */
 570
 571 /** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros
 572   *  @brief macros to handle PCCARD read/write operations
 573   *  @{
 574   */
 575 /**
 576   * @brief  Enable the PCCARD device access.
 577   * @param  __INSTANCE__: FSMC_PCCARD Instance
 578   * @retval None
 579   */
 580 #define __FSMC_PCCARD_ENABLE(__INSTANCE__)  SET_BIT((__INSTANCE__)->PCR4, FSMC_PCRx_PBKEN)
 581
 582 /**
 583   * @brief  Disable the PCCARD device access.
 584   * @param  __INSTANCE__: FSMC_PCCARD Instance
 585   * @retval None
 586   */
 587 #define __FSMC_PCCARD_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->PCR4, FSMC_PCRx_PBKEN)
 588 /**
 589   * @}
 590   */
 591
 592 /** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros
 593   *  @brief macros to handle FSMC flags and interrupts
 594   * @{
 595   */
 596
 597 /**
 598   * @brief  Enable the NAND device interrupt.
 599   * @param  __INSTANCE__: FSMC_NAND Instance
 600   * @param  __BANK__: FSMC_NAND Bank
 601   * @param  __INTERRUPT__: FSMC_NAND interrupt
 602   *         This parameter can be any combination of the following values:
 603   *            @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
 604   *            @arg FSMC_IT_LEVEL: Interrupt level.
 605   *            @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
 606   * @retval None
 607   */
 608 #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__)  (((__BANK__) == FSMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
 609                                                                                                         SET_BIT((__INSTANCE__)->SR3, (__INTERRUPT__)))
 610
 611 /**
 612   * @brief  Disable the NAND device interrupt.
 613   * @param  __INSTANCE__: FSMC_NAND Instance
 614   * @param  __BANK__: FSMC_NAND Bank
 615   * @param  __INTERRUPT__: FSMC_NAND interrupt
 616   *         This parameter can be any combination of the following values:
 617   *            @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
 618   *            @arg FSMC_IT_LEVEL: Interrupt level.
 619   *            @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
 620   * @retval None
 621   */
 622 #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__)  (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
 623                                                                                                          CLEAR_BIT((__INSTANCE__)->SR3, (__INTERRUPT__)))
 624
 625 /**
 626   * @brief  Get flag status of the NAND device.
 627   * @param  __INSTANCE__: FSMC_NAND Instance
 628   * @param  __BANK__    : FSMC_NAND Bank
 629   * @param  __FLAG__    : FSMC_NAND flag
 630   *         This parameter can be any combination of the following values:
 631   *            @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
 632   *            @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
 633   *            @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
 634   *            @arg FSMC_FLAG_FEMPT: FIFO empty flag.
 635   * @retval The state of FLAG (SET or RESET).
 636   */
 637 #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
 638                                                                                                    (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
 639 /**
 640   * @brief  Clear flag status of the NAND device.
 641   * @param  __INSTANCE__: FSMC_NAND Instance
 642   * @param  __BANK__: FSMC_NAND Bank
 643   * @param  __FLAG__: FSMC_NAND flag
 644   *         This parameter can be any combination of the following values:
 645   *            @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
 646   *            @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
 647   *            @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
 648   *            @arg FSMC_FLAG_FEMPT: FIFO empty flag.
 649   * @retval None
 650   */
 651 #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__FLAG__)): \
 652                                                                                                     CLEAR_BIT((__INSTANCE__)->SR3, (__FLAG__)))
 653
 654 /**
 655   * @brief  Enable the PCCARD device interrupt.
 656   * @param  __INSTANCE__: FSMC_PCCARD Instance
 657   * @param  __INTERRUPT__: FSMC_PCCARD interrupt
 658   *         This parameter can be any combination of the following values:
 659   *            @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
 660   *            @arg FSMC_IT_LEVEL: Interrupt level.
 661   *            @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
 662   * @retval None
 663   */
 664 #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  SET_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
 665
 666 /**
 667   * @brief  Disable the PCCARD device interrupt.
 668   * @param  __INSTANCE__: FSMC_PCCARD Instance
 669   * @param  __INTERRUPT__: FSMC_PCCARD interrupt
 670   *         This parameter can be any combination of the following values:
 671   *            @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
 672   *            @arg FSMC_IT_LEVEL: Interrupt level.
 673   *            @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
 674   * @retval None
 675   */
 676 #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  CLEAR_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
 677
 678 /**
 679   * @brief  Get flag status of the PCCARD device.
 680   * @param  __INSTANCE__: FSMC_PCCARD Instance
 681   * @param  __FLAG__: FSMC_PCCARD flag
 682   *         This parameter can be any combination of the following values:
 683   *            @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
 684   *            @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
 685   *            @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
 686   *            @arg FSMC_FLAG_FEMPT: FIFO empty flag.
 687   * @retval The state of FLAG (SET or RESET).
 688   */
 689 #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
 690
 691 /**
 692   * @brief  Clear flag status of the PCCARD device.
 693   * @param  __INSTANCE__: FSMC_PCCARD Instance
 694   * @param  __FLAG__: FSMC_PCCARD flag
 695   *         This parameter can be any combination of the following values:
 696   *            @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
 697   *            @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
 698   *            @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
 699   *            @arg FSMC_FLAG_FEMPT: FIFO empty flag.
 700   * @retval None
 701   */
 702 #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__)  CLEAR_BIT((__INSTANCE__)->SR4, (__FLAG__))
 703
 704 /**
 705   * @}
 706   */
 707 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
 708
 709 /**
 710   * @}
 711   */
 712
 713 /** @defgroup FSMC_LL_Private_Macros FSMC Low Layer Private Macros
 714   * @{
 715   */
 716 #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
 717                                         ((__BANK__) == FSMC_NORSRAM_BANK2) || \
 718                                         ((__BANK__) == FSMC_NORSRAM_BANK3) || \
 719                                         ((__BANK__) == FSMC_NORSRAM_BANK4))
 720
 721 #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
 722                               ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
 723
 724 #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
 725                                     ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
 726                                     ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
 727
 728 #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8)  || \
 729                                                  ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
 730                                                  ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
 731
 732 #define IS_FSMC_WRITE_BURST(__BURST__)          (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
 733                                                  ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
 734
 735 #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
 736                                        ((__MODE__) == FSMC_ACCESS_MODE_B) || \
 737                                        ((__MODE__) == FSMC_ACCESS_MODE_C) || \
 738                                        ((__MODE__) == FSMC_ACCESS_MODE_D))
 739
 740 #define IS_FSMC_NAND_BANK(__BANK__) (((__BANK__) == FSMC_NAND_BANK2) || \
 741                                      ((__BANK__) == FSMC_NAND_BANK3))
 742
 743 #define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
 744                                            ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
 745
 746 #define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
 747                                               ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
 748
 749 #define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \
 750                                       ((__STATE__) == FSMC_NAND_ECC_ENABLE))
 751
 752 #define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE)  || \
 753                                         ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE)  || \
 754                                         ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
 755                                         ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
 756                                         ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
 757                                         ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
 758
 759 /** @defgroup FSMC_TCLR_Setup_Time FSMC_TCLR_Setup_Time
 760   * @{
 761   */
 762 #define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
 763 /**
 764   * @}
 765   */
 766
 767 /** @defgroup FSMC_TAR_Setup_Time FSMC_TAR_Setup_Time
 768   * @{
 769   */
 770 #define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
 771 /**
 772   * @}
 773   */
 774
 775 /** @defgroup FSMC_Setup_Time FSMC_Setup_Time
 776   * @{
 777   */
 778 #define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 255U)
 779 /**
 780   * @}
 781   */
 782
 783 /** @defgroup FSMC_Wait_Setup_Time FSMC_Wait_Setup_Time
 784   * @{
 785   */
 786 #define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 255U)
 787 /**
 788   * @}
 789   */
 790
 791 /** @defgroup FSMC_Hold_Setup_Time FSMC_Hold_Setup_Time
 792   * @{
 793   */
 794 #define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 255U)
 795 /**
 796   * @}
 797   */
 798
 799 /** @defgroup FSMC_HiZ_Setup_Time FSMC_HiZ_Setup_Time
 800   * @{
 801   */
 802 #define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 255U)
 803 /**
 804   * @}
 805   */
 806
 807 /** @defgroup FSMC_NORSRAM_Device_Instance FSMC NOR/SRAM Device Instance
 808   * @{
 809   */
 810 #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
 811 /**
 812   * @}
 813   */
 814
 815 /** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance FSMC NOR/SRAM EXTENDED Device Instance
 816   * @{
 817   */
 818 #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
 819 /**
 820   * @}
 821   */
 822
 823 /** @defgroup FSMC_NAND_Device_Instance FSMC NAND Device Instance
 824   * @{
 825   */
 826 #define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE)
 827 /**
 828   * @}
 829   */
 830
 831 /** @defgroup FSMC_PCCARD_Device_Instance FSMC PCCARD Device Instance
 832   * @{
 833   */
 834 #define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE)
 835
 836 /**
 837   * @}
 838   */
 839 #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
 840                                       ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
 841
 842 #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
 843                                              ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
 844
 845 #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
 846                                      ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
 847
 848 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
 849                                                 ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
 850
 851 #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
 852                                                 ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
 853
 854 #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
 855                                           ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
 856
 857 #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
 858                                          ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
 859
 860 #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
 861                                      ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
 862
 863 #define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
 864
 865 /** @defgroup FSMC_Data_Latency FSMC Data Latency
 866   * @{
 867   */
 868 #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
 869 /**
 870   * @}
 871   */
 872
 873 /** @defgroup FSMC_Address_Setup_Time FSMC Address Setup Time
 874   * @{
 875   */
 876 #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
 877 /**
 878   * @}
 879   */
 880
 881 /** @defgroup FSMC_Address_Hold_Time FSMC Address Hold Time
 882   * @{
 883   */
 884 #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
 885 /**
 886   * @}
 887   */
 888
 889 /** @defgroup FSMC_Data_Setup_Time FSMC Data Setup Time
 890   * @{
 891   */
 892 #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
 893 /**
 894   * @}
 895   */
 896
 897 /** @defgroup FSMC_Bus_Turn_around_Duration FSMC Bus Turn around Duration
 898   * @{
 899   */
 900 #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
 901 /**
 902   * @}
 903   */
 904
 905 /**
 906   * @}
 907   */
 908
 909 /** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants
 910   * @{
 911   */
 912
 913 /* ----------------------- FSMC registers bit mask --------------------------- */
 914 #if (defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
 915 /* --- PCR Register ---*/
 916 /* PCR register clear mask */
 917 #define PCR_CLEAR_MASK    ((uint32_t)(FSMC_PCRx_PWAITEN | FSMC_PCRx_PBKEN  | \
 918                                       FSMC_PCRx_PTYP    | FSMC_PCRx_PWID   | \
 919                                       FSMC_PCRx_ECCEN   | FSMC_PCRx_TCLR   | \
 920                                       FSMC_PCRx_TAR     | FSMC_PCRx_ECCPS))
 921
 922 /* --- PMEM Register ---*/
 923 /* PMEM register clear mask */
 924 #define PMEM_CLEAR_MASK   ((uint32_t)(FSMC_PMEMx_MEMSETx  | FSMC_PMEMx_MEMWAITx |\
 925                                       FSMC_PMEMx_MEMHOLDx | FSMC_PMEMx_MEMHIZx))
 926
 927 /* --- PATT Register ---*/
 928 /* PATT register clear mask */
 929 #define PATT_CLEAR_MASK   ((uint32_t)(FSMC_PATTx_ATTSETx  | FSMC_PATTx_ATTWAITx |\
 930                                       FSMC_PATTx_ATTHOLDx | FSMC_PATTx_ATTHIZx))
 931
 932 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
 933 /* --- BCR Register ---*/
 934 /* BCR register clear mask */
 935 #define BCR_CLEAR_MASK                 ((uint32_t)(FSMC_BCRx_FACCEN  | FSMC_BCRx_MUXEN     | \
 936                                                    FSMC_BCRx_MTYP    | FSMC_BCRx_MWID      | \
 937                                                    FSMC_BCRx_BURSTEN | FSMC_BCRx_WAITPOL   | \
 938                                                    FSMC_BCRx_WRAPMOD | FSMC_BCRx_WAITCFG   | \
 939                                                    FSMC_BCRx_WREN    | FSMC_BCRx_WAITEN    | \
 940                                                    FSMC_BCRx_EXTMOD  | FSMC_BCRx_ASYNCWAIT | \
 941                                                    FSMC_BCRx_CBURSTRW))
 942 /* --- BTR Register ---*/
 943 /* BTR register clear mask */
 944 #define BTR_CLEAR_MASK                 ((uint32_t)(FSMC_BTRx_ADDSET | FSMC_BTRx_ADDHLD  |\
 945                                                    FSMC_BTRx_DATAST | FSMC_BTRx_BUSTURN |\
 946                                                    FSMC_BTRx_CLKDIV | FSMC_BTRx_DATLAT  |\
 947                                                    FSMC_BTRx_ACCMOD))
 948
 949 /* --- BWTR Register ---*/
 950 /* BWTR register clear mask */
 951 #if   (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
 952 #define BWTR_CLEAR_MASK                ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD | \
 953                                                    FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD | \
 954                                                    FSMC_BWTRx_BUSTURN))
 955 #else
 956 #define BWTR_CLEAR_MASK                ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD | \
 957                                                    FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD | \
 958                                                    FSMC_BWTRx_CLKDIV  | FSMC_BWTRx_DATLAT))
 959 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
 960
 961 /* --- PIO4 Register ---*/
 962 /* PIO4 register clear mask */
 963 #define PIO4_CLEAR_MASK   ((uint32_t)(FSMC_PIO4_IOSET4    | FSMC_PIO4_IOWAIT4   | \
 964                                       FSMC_PIO4_IOHOLD4   | FSMC_PIO4_IOHIZ4))
 965 /**
 966   * @}
 967   */
 968 /* Exported functions --------------------------------------------------------*/
 969
 970 /** @addtogroup FSMC_LL_Exported_Functions
 971   * @{
 972   */
 973
 974 /** @addtogroup FSMC_NORSRAM
 975   * @{
 976   */
 977
 978 /** @addtogroup FSMC_NORSRAM_Group1
 979   * @{
 980   */
 981 /* FSMC_NORSRAM Controller functions ******************************************/
 982 /* Initialization/de-initialization functions */
 983 HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
 984 HAL_StatusTypeDef  FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
 985 HAL_StatusTypeDef  FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
 986 HAL_StatusTypeDef  FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
 987 /**
 988   * @}
 989   */
 990
 991 /** @addtogroup FSMC_NORSRAM_Group2
 992   * @{
 993   */
 994 /* FSMC_NORSRAM Control functions */
 995 HAL_StatusTypeDef  FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
 996 HAL_StatusTypeDef  FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
 997 /**
 998   * @}
 999   */
1000
1001 /**
1002   * @}
1003   */
1004
1005 #if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
1006 /** @addtogroup FSMC_NAND
1007   * @{
1008   */
1009
1010 /* FSMC_NAND Controller functions **********************************************/
1011 /* Initialization/de-initialization functions */
1012 /** @addtogroup FSMC_NAND_Exported_Functions_Group1
1013   * @{
1014   */
1015 HAL_StatusTypeDef  FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
1016 HAL_StatusTypeDef  FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1017 HAL_StatusTypeDef  FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1018 HAL_StatusTypeDef  FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
1019 /**
1020   * @}
1021   */
1022
1023 /* FSMC_NAND Control functions */
1024 /** @addtogroup FSMC_NAND_Exported_Functions_Group2
1025   * @{
1026   */
1027 HAL_StatusTypeDef  FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
1028 HAL_StatusTypeDef  FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
1029 HAL_StatusTypeDef  FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
1030 /**
1031   * @}
1032   */
1033
1034 /**
1035   * @}
1036   */
1037
1038 /** @addtogroup FSMC_PCCARD
1039   * @{
1040   */
1041
1042 /* FSMC_PCCARD Controller functions ********************************************/
1043 /* Initialization/de-initialization functions */
1044 /** @addtogroup FSMC_PCCARD_Exported_Functions_Group1
1045   * @{
1046   */
1047 HAL_StatusTypeDef  FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
1048 HAL_StatusTypeDef  FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
1049 HAL_StatusTypeDef  FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
1050 HAL_StatusTypeDef  FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
1051 HAL_StatusTypeDef  FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
1052 /**
1053   * @}
1054   */
1055
1056 /**
1057   * @}
1058   */
1059 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
1060
1061 /**
1062   * @}
1063   */
1064
1065 /**
1066   * @}
1067   */
1068 #endif /* FSMC_BANK1 */
1069
1070 /**
1071   * @}
1072   */
1073
1074 #ifdef __cplusplus
1075 }
1076 #endif
1077
1078 #endif /* __STM32F1xx_LL_FSMC_H */
1079
1080 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1081