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Merge pull request #11270 from haslinghuis/rename_attr
[betaflight.git] / lib / main / STM32F4 / Drivers / STM32F4xx_HAL_Driver / Src / stm32f4xx_ll_adc.c
blob8fe08583767365b1cd85ba0690c1903295b5d4af
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_adc.c
4 * @author MCD Application Team
5 * @version V1.7.1
6 * @date 14-April-2017
7 * @brief ADC LL module driver
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37 #if defined(USE_FULL_LL_DRIVER)
38
39 /* Includes ------------------------------------------------------------------*/
40 #include "stm32f4xx_ll_adc.h"
41 #include "stm32f4xx_ll_bus.h"
42
43 #ifdef USE_FULL_ASSERT
44 #include "stm32_assert.h"
45 #else
46 #define assert_param(expr) ((void)0U)
47 #endif
48
49 /** @addtogroup STM32F4xx_LL_Driver
50 * @{
51 */
52
53 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
54
55 /** @addtogroup ADC_LL ADC
56 * @{
57 */
58
59 /* Private types -------------------------------------------------------------*/
60 /* Private variables ---------------------------------------------------------*/
61 /* Private constants ---------------------------------------------------------*/
62 /* Private macros ------------------------------------------------------------*/
63
64 /** @addtogroup ADC_LL_Private_Macros
65 * @{
66 */
67
68 /* Check of parameters for configuration of ADC hierarchical scope: */
69 /* common to several ADC instances. */
70 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
71 ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
72 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
73 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV6) \
74 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV8) \
75 )
76
77 /* Check of parameters for configuration of ADC hierarchical scope: */
78 /* ADC instance. */
79 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
80 ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
81 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
82 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
83 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
84 )
85
86 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
87 ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
88 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
89 )
90
91 #define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \
92 ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \
93 || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \
94 )
95
96 #define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \
97 ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \
98 || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \
99 )
100
101 /* Check of parameters for configuration of ADC hierarchical scope: */
102 /* ADC group regular */
103 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
104 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
105 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
106 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
107 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
108 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
109 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \
110 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH4) \
111 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
112 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \
113 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
114 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
115 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH1) \
116 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH2) \
117 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH3) \
118 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \
119 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
120 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
121 )
122 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
123 ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
124 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
125 )
126
127 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
128 ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
129 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
130 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
131 )
132
133 #define IS_LL_ADC_REG_FLAG_EOC_SELECTION(__REG_FLAG_EOC_SELECTION__) \
134 ( ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV) \
135 || ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_UNITARY_CONV) \
136 )
137
138 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
139 ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
140 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
141 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
142 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
143 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
144 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
145 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
146 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
147 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
148 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
149 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
150 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
151 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
152 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
153 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
154 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
155 )
156
157 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
158 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
159 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
160 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
161 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
162 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
163 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
164 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
165 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
166 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
167 )
168
169 /* Check of parameters for configuration of ADC hierarchical scope: */
170 /* ADC group injected */
171 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
172 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
173 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
174 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
175 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
176 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
177 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH2) \
178 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
179 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH1) \
180 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH2) \
181 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \
182 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
183 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_CH4) \
184 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \
185 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \
186 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH3) \
187 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
188 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
189 )
190
191 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
192 ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
193 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
194 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
195 )
196
197 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
198 ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
199 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
200 )
201
202 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
203 ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
204 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
205 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
206 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
207 )
208
209 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
210 ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
211 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
212 )
213
214 #if defined(ADC_MULTIMODE_SUPPORT)
215 /* Check of parameters for configuration of ADC hierarchical scope: */
216 /* multimode. */
217 #if defined(ADC3)
218 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
219 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
220 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
221 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
222 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
223 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
224 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
225 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
226 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
227 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM) \
228 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT) \
229 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_SIMULT) \
230 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIMULT) \
231 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_INTERL) \
232 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_ALTERN) \
233 )
234 #else
235 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
236 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
237 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
238 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
239 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
240 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
241 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
242 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
243 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
244 )
245 #endif
246
247 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
248 ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
249 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_1) \
250 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_2) \
251 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_3) \
252 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_1) \
253 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_2) \
254 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_3) \
255 )
256
257 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
258 ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \
259 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
260 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \
261 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
262 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
263 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \
264 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \
265 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \
266 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES) \
267 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES) \
268 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES) \
269 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES) \
270 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES) \
271 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES) \
272 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES) \
273 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES) \
274 )
275
276 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
277 ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
278 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
279 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
280 )
281
282 #endif /* ADC_MULTIMODE_SUPPORT */
283 /**
284 * @}
285 */
286
287
288 /* Private function prototypes -----------------------------------------------*/
289
290 /* Exported functions --------------------------------------------------------*/
291 /** @addtogroup ADC_LL_Exported_Functions
292 * @{
293 */
294
295 /** @addtogroup ADC_LL_EF_Init
296 * @{
297 */
298
299 /**
300 * @brief De-initialize registers of all ADC instances belonging to
301 * the same ADC common instance to their default reset values.
302 * @param ADCxy_COMMON ADC common instance
303 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
304 * @retval An ErrorStatus enumeration value:
305 * - SUCCESS: ADC common registers are de-initialized
306 * - ERROR: not applicable
307 */
308 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
309 {
310 /* Check the parameters */
311 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
312
313
314 /* Force reset of ADC clock (core clock) */
315 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC);
316
317 /* Release reset of ADC clock (core clock) */
318 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC);
319
320 return SUCCESS;
321 }
322
323 /**
324 * @brief Initialize some features of ADC common parameters
325 * (all ADC instances belonging to the same ADC common instance)
326 * and multimode (for devices with several ADC instances available).
327 * @note The setting of ADC common parameters is conditioned to
328 * ADC instances state:
329 * All ADC instances belonging to the same ADC common instance
330 * must be disabled.
331 * @param ADCxy_COMMON ADC common instance
332 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
333 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
334 * @retval An ErrorStatus enumeration value:
335 * - SUCCESS: ADC common registers are initialized
336 * - ERROR: ADC common registers are not initialized
337 */
338 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
339 {
340 ErrorStatus status = SUCCESS;
341
342 /* Check the parameters */
343 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
344 assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
345
346 #if defined(ADC_MULTIMODE_SUPPORT)
347 assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
348 if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
349 {
350 assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
351 assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
352 }
353 #endif /* ADC_MULTIMODE_SUPPORT */
354
355 /* Note: Hardware constraint (refer to description of functions */
356 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
357 /* On this STM32 serie, setting of these features is conditioned to */
358 /* ADC state: */
359 /* All ADC instances of the ADC common group must be disabled. */
360 if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
361 {
362 /* Configuration of ADC hierarchical scope: */
363 /* - common to several ADC */
364 /* (all ADC instances belonging to the same ADC common instance) */
365 /* - Set ADC clock (conversion clock) */
366 /* - multimode (if several ADC instances available on the */
367 /* selected device) */
368 /* - Set ADC multimode configuration */
369 /* - Set ADC multimode DMA transfer */
370 /* - Set ADC multimode: delay between 2 sampling phases */
371 #if defined(ADC_MULTIMODE_SUPPORT)
372 if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
373 {
374 MODIFY_REG(ADCxy_COMMON->CCR,
375 ADC_CCR_ADCPRE
376 | ADC_CCR_MULTI
377 | ADC_CCR_DMA
378 | ADC_CCR_DDS
379 | ADC_CCR_DELAY
380 ,
381 ADC_CommonInitStruct->CommonClock
382 | ADC_CommonInitStruct->Multimode
383 | ADC_CommonInitStruct->MultiDMATransfer
384 | ADC_CommonInitStruct->MultiTwoSamplingDelay
385 );
386 }
387 else
388 {
389 MODIFY_REG(ADCxy_COMMON->CCR,
390 ADC_CCR_ADCPRE
391 | ADC_CCR_MULTI
392 | ADC_CCR_DMA
393 | ADC_CCR_DDS
394 | ADC_CCR_DELAY
395 ,
396 ADC_CommonInitStruct->CommonClock
397 | LL_ADC_MULTI_INDEPENDENT
398 );
399 }
400 #else
401 LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
402 #endif
403 }
404 else
405 {
406 /* Initialization error: One or several ADC instances belonging to */
407 /* the same ADC common instance are not disabled. */
408 status = ERROR;
409 }
410
411 return status;
412 }
413
414 /**
415 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
416 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
417 * whose fields will be set to default values.
418 * @retval None
419 */
420 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
421 {
422 /* Set ADC_CommonInitStruct fields to default values */
423 /* Set fields of ADC common */
424 /* (all ADC instances belonging to the same ADC common instance) */
425 ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
426
427 #if defined(ADC_MULTIMODE_SUPPORT)
428 /* Set fields of ADC multimode */
429 ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
430 ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
431 ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES;
432 #endif /* ADC_MULTIMODE_SUPPORT */
433 }
434
435 /**
436 * @brief De-initialize registers of the selected ADC instance
437 * to their default reset values.
438 * @note To reset all ADC instances quickly (perform a hard reset),
439 * use function @ref LL_ADC_CommonDeInit().
440 * @param ADCx ADC instance
441 * @retval An ErrorStatus enumeration value:
442 * - SUCCESS: ADC registers are de-initialized
443 * - ERROR: ADC registers are not de-initialized
444 */
445 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
446 {
447 ErrorStatus status = SUCCESS;
448
449 /* Check the parameters */
450 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
451
452 /* Disable ADC instance if not already disabled. */
453 if(LL_ADC_IsEnabled(ADCx) == 1U)
454 {
455 /* Set ADC group regular trigger source to SW start to ensure to not */
456 /* have an external trigger event occurring during the conversion stop */
457 /* ADC disable process. */
458 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
459
460 /* Set ADC group injected trigger source to SW start to ensure to not */
461 /* have an external trigger event occurring during the conversion stop */
462 /* ADC disable process. */
463 LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
464
465 /* Disable the ADC instance */
466 LL_ADC_Disable(ADCx);
467 }
468
469 /* Check whether ADC state is compliant with expected state */
470 /* (hardware requirements of bits state to reset registers below) */
471 if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U)
472 {
473 /* ========== Reset ADC registers ========== */
474 /* Reset register SR */
475 CLEAR_BIT(ADCx->SR,
476 ( LL_ADC_FLAG_STRT
477 | LL_ADC_FLAG_JSTRT
478 | LL_ADC_FLAG_EOCS
479 | LL_ADC_FLAG_OVR
480 | LL_ADC_FLAG_JEOS
481 | LL_ADC_FLAG_AWD1 )
482 );
483
484 /* Reset register CR1 */
485 CLEAR_BIT(ADCx->CR1,
486 ( ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN
487 | ADC_CR1_JAWDEN
488 | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN
489 | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN
490 | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE
491 | ADC_CR1_AWDCH )
492 );
493
494 /* Reset register CR2 */
495 CLEAR_BIT(ADCx->CR2,
496 ( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL
497 | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL
498 | ADC_CR2_ALIGN | ADC_CR2_EOCS
499 | ADC_CR2_DDS | ADC_CR2_DMA
500 | ADC_CR2_CONT | ADC_CR2_ADON )
501 );
502
503 /* Reset register SMPR1 */
504 CLEAR_BIT(ADCx->SMPR1,
505 ( ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16
506 | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13
507 | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10)
508 );
509
510 /* Reset register SMPR2 */
511 CLEAR_BIT(ADCx->SMPR2,
512 ( ADC_SMPR2_SMP9
513 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6
514 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3
515 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0)
516 );
517
518 /* Reset register JOFR1 */
519 CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1);
520 /* Reset register JOFR2 */
521 CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2);
522 /* Reset register JOFR3 */
523 CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3);
524 /* Reset register JOFR4 */
525 CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4);
526
527 /* Reset register HTR */
528 SET_BIT(ADCx->HTR, ADC_HTR_HT);
529 /* Reset register LTR */
530 CLEAR_BIT(ADCx->LTR, ADC_LTR_LT);
531
532 /* Reset register SQR1 */
533 CLEAR_BIT(ADCx->SQR1,
534 ( ADC_SQR1_L
535 | ADC_SQR1_SQ16
536 | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13)
537 );
538
539 /* Reset register SQR2 */
540 CLEAR_BIT(ADCx->SQR2,
541 ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10
542 | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7)
543 );
544
545
546 /* Reset register JSQR */
547 CLEAR_BIT(ADCx->JSQR,
548 ( ADC_JSQR_JL
549 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
550 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )
551 );
552
553 /* Reset register DR */
554 /* bits in access mode read only, no direct reset applicable */
555
556 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
557 /* bits in access mode read only, no direct reset applicable */
558
559 /* Reset register CCR */
560 CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE | ADC_CCR_ADCPRE);
561 }
562
563 return status;
564 }
565
566 /**
567 * @brief Initialize some features of ADC instance.
568 * @note These parameters have an impact on ADC scope: ADC instance.
569 * Affects both group regular and group injected (availability
570 * of ADC group injected depends on STM32 families).
571 * Refer to corresponding unitary functions into
572 * @ref ADC_LL_EF_Configuration_ADC_Instance .
573 * @note The setting of these parameters by function @ref LL_ADC_Init()
574 * is conditioned to ADC state:
575 * ADC instance must be disabled.
576 * This condition is applied to all ADC features, for efficiency
577 * and compatibility over all STM32 families. However, the different
578 * features can be set under different ADC state conditions
579 * (setting possible with ADC enabled without conversion on going,
580 * ADC enabled with conversion on going, ...)
581 * Each feature can be updated afterwards with a unitary function
582 * and potentially with ADC in a different state than disabled,
583 * refer to description of each function for setting
584 * conditioned to ADC state.
585 * @note After using this function, some other features must be configured
586 * using LL unitary functions.
587 * The minimum configuration remaining to be done is:
588 * - Set ADC group regular or group injected sequencer:
589 * map channel on the selected sequencer rank.
590 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
591 * - Set ADC channel sampling time
592 * Refer to function LL_ADC_SetChannelSamplingTime();
593 * @param ADCx ADC instance
594 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
595 * @retval An ErrorStatus enumeration value:
596 * - SUCCESS: ADC registers are initialized
597 * - ERROR: ADC registers are not initialized
598 */
599 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
600 {
601 ErrorStatus status = SUCCESS;
602
603 /* Check the parameters */
604 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
605
606 assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
607 assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
608 assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode));
609
610 /* Note: Hardware constraint (refer to description of this function): */
611 /* ADC instance must be disabled. */
612 if(LL_ADC_IsEnabled(ADCx) == 0U)
613 {
614 /* Configuration of ADC hierarchical scope: */
615 /* - ADC instance */
616 /* - Set ADC data resolution */
617 /* - Set ADC conversion data alignment */
618 MODIFY_REG(ADCx->CR1,
619 ADC_CR1_RES
620 | ADC_CR1_SCAN
621 ,
622 ADC_InitStruct->Resolution
623 | ADC_InitStruct->SequencersScanMode
624 );
625
626 MODIFY_REG(ADCx->CR2,
627 ADC_CR2_ALIGN
628 ,
629 ADC_InitStruct->DataAlignment
630 );
631
632 }
633 else
634 {
635 /* Initialization error: ADC instance is not disabled. */
636 status = ERROR;
637 }
638 return status;
639 }
640
641 /**
642 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
643 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
644 * whose fields will be set to default values.
645 * @retval None
646 */
647 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
648 {
649 /* Set ADC_InitStruct fields to default values */
650 /* Set fields of ADC instance */
651 ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
652 ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
653
654 /* Enable scan mode to have a generic behavior with ADC of other */
655 /* STM32 families, without this setting available: */
656 /* ADC group regular sequencer and ADC group injected sequencer depend */
657 /* only of their own configuration. */
658 ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE;
659
660 }
661
662 /**
663 * @brief Initialize some features of ADC group regular.
664 * @note These parameters have an impact on ADC scope: ADC group regular.
665 * Refer to corresponding unitary functions into
666 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
667 * (functions with prefix "REG").
668 * @note The setting of these parameters by function @ref LL_ADC_Init()
669 * is conditioned to ADC state:
670 * ADC instance must be disabled.
671 * This condition is applied to all ADC features, for efficiency
672 * and compatibility over all STM32 families. However, the different
673 * features can be set under different ADC state conditions
674 * (setting possible with ADC enabled without conversion on going,
675 * ADC enabled with conversion on going, ...)
676 * Each feature can be updated afterwards with a unitary function
677 * and potentially with ADC in a different state than disabled,
678 * refer to description of each function for setting
679 * conditioned to ADC state.
680 * @note After using this function, other features must be configured
681 * using LL unitary functions.
682 * The minimum configuration remaining to be done is:
683 * - Set ADC group regular or group injected sequencer:
684 * map channel on the selected sequencer rank.
685 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
686 * - Set ADC channel sampling time
687 * Refer to function LL_ADC_SetChannelSamplingTime();
688 * @param ADCx ADC instance
689 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
690 * @retval An ErrorStatus enumeration value:
691 * - SUCCESS: ADC registers are initialized
692 * - ERROR: ADC registers are not initialized
693 */
694 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
695 {
696 ErrorStatus status = SUCCESS;
697
698 /* Check the parameters */
699 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
700 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
701 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
702 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
703 {
704 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
705 }
706 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
707 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
708
709 /* Note: Hardware constraint (refer to description of this function): */
710 /* ADC instance must be disabled. */
711 if(LL_ADC_IsEnabled(ADCx) == 0U)
712 {
713 /* Configuration of ADC hierarchical scope: */
714 /* - ADC group regular */
715 /* - Set ADC group regular trigger source */
716 /* - Set ADC group regular sequencer length */
717 /* - Set ADC group regular sequencer discontinuous mode */
718 /* - Set ADC group regular continuous mode */
719 /* - Set ADC group regular conversion data transfer: no transfer or */
720 /* transfer by DMA, and DMA requests mode */
721 /* Note: On this STM32 serie, ADC trigger edge is set when starting */
722 /* ADC conversion. */
723 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
724 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
725 {
726 MODIFY_REG(ADCx->CR1,
727 ADC_CR1_DISCEN
728 | ADC_CR1_DISCNUM
729 ,
730 ADC_REG_InitStruct->SequencerLength
731 | ADC_REG_InitStruct->SequencerDiscont
732 );
733 }
734 else
735 {
736 MODIFY_REG(ADCx->CR1,
737 ADC_CR1_DISCEN
738 | ADC_CR1_DISCNUM
739 ,
740 ADC_REG_InitStruct->SequencerLength
741 | LL_ADC_REG_SEQ_DISCONT_DISABLE
742 );
743 }
744
745 MODIFY_REG(ADCx->CR2,
746 ADC_CR2_EXTSEL
747 | ADC_CR2_EXTEN
748 | ADC_CR2_CONT
749 | ADC_CR2_DMA
750 | ADC_CR2_DDS
751 ,
752 (ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL)
753 | ADC_REG_InitStruct->ContinuousMode
754 | ADC_REG_InitStruct->DMATransfer
755 );
756
757 /* Set ADC group regular sequencer length and scan direction */
758 /* Note: Hardware constraint (refer to description of this function): */
759 /* Note: If ADC instance feature scan mode is disabled */
760 /* (refer to ADC instance initialization structure */
761 /* parameter @ref SequencersScanMode */
762 /* or function @ref LL_ADC_SetSequencersScanMode() ), */
763 /* this parameter is discarded. */
764 LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
765 }
766 else
767 {
768 /* Initialization error: ADC instance is not disabled. */
769 status = ERROR;
770 }
771 return status;
772 }
773
774 /**
775 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
776 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
777 * whose fields will be set to default values.
778 * @retval None
779 */
780 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
781 {
782 /* Set ADC_REG_InitStruct fields to default values */
783 /* Set fields of ADC group regular */
784 /* Note: On this STM32 serie, ADC trigger edge is set when starting */
785 /* ADC conversion. */
786 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
787 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
788 ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
789 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
790 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
791 ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
792 }
793
794 /**
795 * @brief Initialize some features of ADC group injected.
796 * @note These parameters have an impact on ADC scope: ADC group injected.
797 * Refer to corresponding unitary functions into
798 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
799 * (functions with prefix "INJ").
800 * @note The setting of these parameters by function @ref LL_ADC_Init()
801 * is conditioned to ADC state:
802 * ADC instance must be disabled.
803 * This condition is applied to all ADC features, for efficiency
804 * and compatibility over all STM32 families. However, the different
805 * features can be set under different ADC state conditions
806 * (setting possible with ADC enabled without conversion on going,
807 * ADC enabled with conversion on going, ...)
808 * Each feature can be updated afterwards with a unitary function
809 * and potentially with ADC in a different state than disabled,
810 * refer to description of each function for setting
811 * conditioned to ADC state.
812 * @note After using this function, other features must be configured
813 * using LL unitary functions.
814 * The minimum configuration remaining to be done is:
815 * - Set ADC group injected sequencer:
816 * map channel on the selected sequencer rank.
817 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
818 * - Set ADC channel sampling time
819 * Refer to function LL_ADC_SetChannelSamplingTime();
820 * @param ADCx ADC instance
821 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
822 * @retval An ErrorStatus enumeration value:
823 * - SUCCESS: ADC registers are initialized
824 * - ERROR: ADC registers are not initialized
825 */
826 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
827 {
828 ErrorStatus status = SUCCESS;
829
830 /* Check the parameters */
831 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
832 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
833 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
834 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
835 {
836 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
837 }
838 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
839
840 /* Note: Hardware constraint (refer to description of this function): */
841 /* ADC instance must be disabled. */
842 if(LL_ADC_IsEnabled(ADCx) == 0U)
843 {
844 /* Configuration of ADC hierarchical scope: */
845 /* - ADC group injected */
846 /* - Set ADC group injected trigger source */
847 /* - Set ADC group injected sequencer length */
848 /* - Set ADC group injected sequencer discontinuous mode */
849 /* - Set ADC group injected conversion trigger: independent or */
850 /* from ADC group regular */
851 /* Note: On this STM32 serie, ADC trigger edge is set when starting */
852 /* ADC conversion. */
853 /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */
854 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
855 {
856 MODIFY_REG(ADCx->CR1,
857 ADC_CR1_JDISCEN
858 | ADC_CR1_JAUTO
859 ,
860 ADC_INJ_InitStruct->SequencerDiscont
861 | ADC_INJ_InitStruct->TrigAuto
862 );
863 }
864 else
865 {
866 MODIFY_REG(ADCx->CR1,
867 ADC_CR1_JDISCEN
868 | ADC_CR1_JAUTO
869 ,
870 LL_ADC_REG_SEQ_DISCONT_DISABLE
871 | ADC_INJ_InitStruct->TrigAuto
872 );
873 }
874
875 MODIFY_REG(ADCx->CR2,
876 ADC_CR2_JEXTSEL
877 | ADC_CR2_JEXTEN
878 ,
879 (ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL)
880 );
881
882 /* Note: Hardware constraint (refer to description of this function): */
883 /* Note: If ADC instance feature scan mode is disabled */
884 /* (refer to ADC instance initialization structure */
885 /* parameter @ref SequencersScanMode */
886 /* or function @ref LL_ADC_SetSequencersScanMode() ), */
887 /* this parameter is discarded. */
888 LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength);
889 }
890 else
891 {
892 /* Initialization error: ADC instance is not disabled. */
893 status = ERROR;
894 }
895 return status;
896 }
897
898 /**
899 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
900 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
901 * whose fields will be set to default values.
902 * @retval None
903 */
904 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
905 {
906 /* Set ADC_INJ_InitStruct fields to default values */
907 /* Set fields of ADC group injected */
908 ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
909 ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
910 ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
911 ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
912 }
913
914 /**
915 * @}
916 */
917
918 /**
919 * @}
920 */
921
922 /**
923 * @}
924 */
925
926 #endif /* ADC1 || ADC2 || ADC3 */
927
928 /**
929 * @}
930 */
931
932 #endif /* USE_FULL_LL_DRIVER */
933
934 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/