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Merge pull request #11270 from haslinghuis/rename_attr
[betaflight.git] / lib / main / STM32F4 / Drivers / STM32F4xx_StdPeriph_Driver / inc / stm32f4xx_tim.h
blobeb5032f0476d4e1588628dc72db6660fc90f260f
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_tim.h
4 * @author MCD Application Team
5 * @version V1.7.1
6 * @date 20-May-2016
7 * @brief This file contains all the functions prototypes for the TIM firmware
8 * library.
9 ******************************************************************************
10 * @attention
11 *
12 * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
13 *
14 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15 * You may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at:
17 *
18 * http://www.st.com/software_license_agreement_liberty_v2
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *
26 ******************************************************************************
27 */
28
29 /* Define to prevent recursive inclusion -------------------------------------*/
30 #ifndef __STM32F4xx_TIM_H
31 #define __STM32F4xx_TIM_H
32
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36
37 /* Includes ------------------------------------------------------------------*/
38 #include "stm32f4xx.h"
39
40 /** @addtogroup STM32F4xx_StdPeriph_Driver
41 * @{
42 */
43
44 /** @addtogroup TIM
45 * @{
46 */
47
48 /* Exported types ------------------------------------------------------------*/
49
50 /**
51 * @brief TIM Time Base Init structure definition
52 * @note This structure is used with all TIMx except for TIM6 and TIM7.
53 */
54
55 typedef struct
56 {
57 uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
58 This parameter can be a number between 0x0000 and 0xFFFF */
59
60 uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
61 This parameter can be a value of @ref TIM_Counter_Mode */
62
63 uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active
64 Auto-Reload Register at the next update event.
65 This parameter must be a number between 0x0000 and 0xFFFF. */
66
67 uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
68 This parameter can be a value of @ref TIM_Clock_Division_CKD */
69
70 uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
71 reaches zero, an update event is generated and counting restarts
72 from the RCR value (N).
73 This means in PWM mode that (N+1) corresponds to:
74 - the number of PWM periods in edge-aligned mode
75 - the number of half PWM period in center-aligned mode
76 This parameter must be a number between 0x00 and 0xFF.
77 @note This parameter is valid only for TIM1 and TIM8. */
78 } TIM_TimeBaseInitTypeDef;
79
80 /**
81 * @brief TIM Output Compare Init structure definition
82 */
83
84 typedef struct
85 {
86 uint16_t TIM_OCMode; /*!< Specifies the TIM mode.
87 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
88
89 uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
90 This parameter can be a value of @ref TIM_Output_Compare_State */
91
92 uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.
93 This parameter can be a value of @ref TIM_Output_Compare_N_State
94 @note This parameter is valid only for TIM1 and TIM8. */
95
96 uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
97 This parameter can be a number between 0x0000 and 0xFFFF */
98
99 uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
100 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
101
102 uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.
103 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
104 @note This parameter is valid only for TIM1 and TIM8. */
105
106 uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
107 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
108 @note This parameter is valid only for TIM1 and TIM8. */
109
110 uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
111 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
112 @note This parameter is valid only for TIM1 and TIM8. */
113 } TIM_OCInitTypeDef;
114
115 /**
116 * @brief TIM Input Capture Init structure definition
117 */
118
119 typedef struct
120 {
121
122 uint16_t TIM_Channel; /*!< Specifies the TIM channel.
123 This parameter can be a value of @ref TIM_Channel */
124
125 uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
126 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
127
128 uint16_t TIM_ICSelection; /*!< Specifies the input.
129 This parameter can be a value of @ref TIM_Input_Capture_Selection */
130
131 uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
132 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
133
134 uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
135 This parameter can be a number between 0x0 and 0xF */
136 } TIM_ICInitTypeDef;
137
138 /**
139 * @brief BDTR structure definition
140 * @note This structure is used only with TIM1 and TIM8.
141 */
142
143 typedef struct
144 {
145
146 uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.
147 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
148
149 uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.
150 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
151
152 uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.
153 This parameter can be a value of @ref TIM_Lock_level */
154
155 uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the
156 switching-on of the outputs.
157 This parameter can be a number between 0x00 and 0xFF */
158
159 uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not.
160 This parameter can be a value of @ref TIM_Break_Input_enable_disable */
161
162 uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
163 This parameter can be a value of @ref TIM_Break_Polarity */
164
165 uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
166 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
167 } TIM_BDTRInitTypeDef;
168
169 /* Exported constants --------------------------------------------------------*/
170
171 /** @defgroup TIM_Exported_constants
172 * @{
173 */
174
175 #define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
176 ((PERIPH) == TIM2) || \
177 ((PERIPH) == TIM3) || \
178 ((PERIPH) == TIM4) || \
179 ((PERIPH) == TIM5) || \
180 ((PERIPH) == TIM6) || \
181 ((PERIPH) == TIM7) || \
182 ((PERIPH) == TIM8) || \
183 ((PERIPH) == TIM9) || \
184 ((PERIPH) == TIM10) || \
185 ((PERIPH) == TIM11) || \
186 ((PERIPH) == TIM12) || \
187 (((PERIPH) == TIM13) || \
188 ((PERIPH) == TIM14)))
189 /* LIST1: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14 */
190 #define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
191 ((PERIPH) == TIM2) || \
192 ((PERIPH) == TIM3) || \
193 ((PERIPH) == TIM4) || \
194 ((PERIPH) == TIM5) || \
195 ((PERIPH) == TIM8) || \
196 ((PERIPH) == TIM9) || \
197 ((PERIPH) == TIM10) || \
198 ((PERIPH) == TIM11) || \
199 ((PERIPH) == TIM12) || \
200 ((PERIPH) == TIM13) || \
201 ((PERIPH) == TIM14))
202
203 /* LIST2: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9 and TIM12 */
204 #define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
205 ((PERIPH) == TIM2) || \
206 ((PERIPH) == TIM3) || \
207 ((PERIPH) == TIM4) || \
208 ((PERIPH) == TIM5) || \
209 ((PERIPH) == TIM8) || \
210 ((PERIPH) == TIM9) || \
211 ((PERIPH) == TIM12))
212 /* LIST3: TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 */
213 #define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
214 ((PERIPH) == TIM2) || \
215 ((PERIPH) == TIM3) || \
216 ((PERIPH) == TIM4) || \
217 ((PERIPH) == TIM5) || \
218 ((PERIPH) == TIM8))
219 /* LIST4: TIM1 and TIM8 */
220 #define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
221 ((PERIPH) == TIM8))
222 /* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */
223 #define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
224 ((PERIPH) == TIM2) || \
225 ((PERIPH) == TIM3) || \
226 ((PERIPH) == TIM4) || \
227 ((PERIPH) == TIM5) || \
228 ((PERIPH) == TIM6) || \
229 ((PERIPH) == TIM7) || \
230 ((PERIPH) == TIM8))
231 /* LIST6: TIM2, TIM5 and TIM11 */
232 #define IS_TIM_LIST6_PERIPH(TIMx)(((TIMx) == TIM2) || \
233 ((TIMx) == TIM5) || \
234 ((TIMx) == TIM11))
235
236 /** @defgroup TIM_Output_Compare_and_PWM_modes
237 * @{
238 */
239
240 #define TIM_OCMode_Timing ((uint16_t)0x0000)
241 #define TIM_OCMode_Active ((uint16_t)0x0010)
242 #define TIM_OCMode_Inactive ((uint16_t)0x0020)
243 #define TIM_OCMode_Toggle ((uint16_t)0x0030)
244 #define TIM_OCMode_PWM1 ((uint16_t)0x0060)
245 #define TIM_OCMode_PWM2 ((uint16_t)0x0070)
246 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
247 ((MODE) == TIM_OCMode_Active) || \
248 ((MODE) == TIM_OCMode_Inactive) || \
249 ((MODE) == TIM_OCMode_Toggle)|| \
250 ((MODE) == TIM_OCMode_PWM1) || \
251 ((MODE) == TIM_OCMode_PWM2))
252 #define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
253 ((MODE) == TIM_OCMode_Active) || \
254 ((MODE) == TIM_OCMode_Inactive) || \
255 ((MODE) == TIM_OCMode_Toggle)|| \
256 ((MODE) == TIM_OCMode_PWM1) || \
257 ((MODE) == TIM_OCMode_PWM2) || \
258 ((MODE) == TIM_ForcedAction_Active) || \
259 ((MODE) == TIM_ForcedAction_InActive))
260 /**
261 * @}
262 */
263
264 /** @defgroup TIM_One_Pulse_Mode
265 * @{
266 */
267
268 #define TIM_OPMode_Single ((uint16_t)0x0008)
269 #define TIM_OPMode_Repetitive ((uint16_t)0x0000)
270 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
271 ((MODE) == TIM_OPMode_Repetitive))
272 /**
273 * @}
274 */
275
276 /** @defgroup TIM_Channel
277 * @{
278 */
279
280 #define TIM_Channel_1 ((uint16_t)0x0000)
281 #define TIM_Channel_2 ((uint16_t)0x0004)
282 #define TIM_Channel_3 ((uint16_t)0x0008)
283 #define TIM_Channel_4 ((uint16_t)0x000C)
284
285 #define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
286 ((CHANNEL) == TIM_Channel_2) || \
287 ((CHANNEL) == TIM_Channel_3) || \
288 ((CHANNEL) == TIM_Channel_4))
289
290 #define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
291 ((CHANNEL) == TIM_Channel_2))
292 #define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
293 ((CHANNEL) == TIM_Channel_2) || \
294 ((CHANNEL) == TIM_Channel_3))
295 /**
296 * @}
297 */
298
299 /** @defgroup TIM_Clock_Division_CKD
300 * @{
301 */
302
303 #define TIM_CKD_DIV1 ((uint16_t)0x0000)
304 #define TIM_CKD_DIV2 ((uint16_t)0x0100)
305 #define TIM_CKD_DIV4 ((uint16_t)0x0200)
306 #define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
307 ((DIV) == TIM_CKD_DIV2) || \
308 ((DIV) == TIM_CKD_DIV4))
309 /**
310 * @}
311 */
312
313 /** @defgroup TIM_Counter_Mode
314 * @{
315 */
316
317 #define TIM_CounterMode_Up ((uint16_t)0x0000)
318 #define TIM_CounterMode_Down ((uint16_t)0x0010)
319 #define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
320 #define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
321 #define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
322 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
323 ((MODE) == TIM_CounterMode_Down) || \
324 ((MODE) == TIM_CounterMode_CenterAligned1) || \
325 ((MODE) == TIM_CounterMode_CenterAligned2) || \
326 ((MODE) == TIM_CounterMode_CenterAligned3))
327 /**
328 * @}
329 */
330
331 /** @defgroup TIM_Output_Compare_Polarity
332 * @{
333 */
334
335 #define TIM_OCPolarity_High ((uint16_t)0x0000)
336 #define TIM_OCPolarity_Low ((uint16_t)0x0002)
337 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
338 ((POLARITY) == TIM_OCPolarity_Low))
339 /**
340 * @}
341 */
342
343 /** @defgroup TIM_Output_Compare_N_Polarity
344 * @{
345 */
346
347 #define TIM_OCNPolarity_High ((uint16_t)0x0000)
348 #define TIM_OCNPolarity_Low ((uint16_t)0x0008)
349 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
350 ((POLARITY) == TIM_OCNPolarity_Low))
351 /**
352 * @}
353 */
354
355 /** @defgroup TIM_Output_Compare_State
356 * @{
357 */
358
359 #define TIM_OutputState_Disable ((uint16_t)0x0000)
360 #define TIM_OutputState_Enable ((uint16_t)0x0001)
361 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
362 ((STATE) == TIM_OutputState_Enable))
363 /**
364 * @}
365 */
366
367 /** @defgroup TIM_Output_Compare_N_State
368 * @{
369 */
370
371 #define TIM_OutputNState_Disable ((uint16_t)0x0000)
372 #define TIM_OutputNState_Enable ((uint16_t)0x0004)
373 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
374 ((STATE) == TIM_OutputNState_Enable))
375 /**
376 * @}
377 */
378
379 /** @defgroup TIM_Capture_Compare_State
380 * @{
381 */
382
383 #define TIM_CCx_Enable ((uint16_t)0x0001)
384 #define TIM_CCx_Disable ((uint16_t)0x0000)
385 #define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
386 ((CCX) == TIM_CCx_Disable))
387 /**
388 * @}
389 */
390
391 /** @defgroup TIM_Capture_Compare_N_State
392 * @{
393 */
394
395 #define TIM_CCxN_Enable ((uint16_t)0x0004)
396 #define TIM_CCxN_Disable ((uint16_t)0x0000)
397 #define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
398 ((CCXN) == TIM_CCxN_Disable))
399 /**
400 * @}
401 */
402
403 /** @defgroup TIM_Break_Input_enable_disable
404 * @{
405 */
406
407 #define TIM_Break_Enable ((uint16_t)0x1000)
408 #define TIM_Break_Disable ((uint16_t)0x0000)
409 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
410 ((STATE) == TIM_Break_Disable))
411 /**
412 * @}
413 */
414
415 /** @defgroup TIM_Break_Polarity
416 * @{
417 */
418
419 #define TIM_BreakPolarity_Low ((uint16_t)0x0000)
420 #define TIM_BreakPolarity_High ((uint16_t)0x2000)
421 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
422 ((POLARITY) == TIM_BreakPolarity_High))
423 /**
424 * @}
425 */
426
427 /** @defgroup TIM_AOE_Bit_Set_Reset
428 * @{
429 */
430
431 #define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
432 #define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
433 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
434 ((STATE) == TIM_AutomaticOutput_Disable))
435 /**
436 * @}
437 */
438
439 /** @defgroup TIM_Lock_level
440 * @{
441 */
442
443 #define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
444 #define TIM_LOCKLevel_1 ((uint16_t)0x0100)
445 #define TIM_LOCKLevel_2 ((uint16_t)0x0200)
446 #define TIM_LOCKLevel_3 ((uint16_t)0x0300)
447 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
448 ((LEVEL) == TIM_LOCKLevel_1) || \
449 ((LEVEL) == TIM_LOCKLevel_2) || \
450 ((LEVEL) == TIM_LOCKLevel_3))
451 /**
452 * @}
453 */
454
455 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
456 * @{
457 */
458
459 #define TIM_OSSIState_Enable ((uint16_t)0x0400)
460 #define TIM_OSSIState_Disable ((uint16_t)0x0000)
461 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
462 ((STATE) == TIM_OSSIState_Disable))
463 /**
464 * @}
465 */
466
467 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
468 * @{
469 */
470
471 #define TIM_OSSRState_Enable ((uint16_t)0x0800)
472 #define TIM_OSSRState_Disable ((uint16_t)0x0000)
473 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
474 ((STATE) == TIM_OSSRState_Disable))
475 /**
476 * @}
477 */
478
479 /** @defgroup TIM_Output_Compare_Idle_State
480 * @{
481 */
482
483 #define TIM_OCIdleState_Set ((uint16_t)0x0100)
484 #define TIM_OCIdleState_Reset ((uint16_t)0x0000)
485 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
486 ((STATE) == TIM_OCIdleState_Reset))
487 /**
488 * @}
489 */
490
491 /** @defgroup TIM_Output_Compare_N_Idle_State
492 * @{
493 */
494
495 #define TIM_OCNIdleState_Set ((uint16_t)0x0200)
496 #define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
497 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
498 ((STATE) == TIM_OCNIdleState_Reset))
499 /**
500 * @}
501 */
502
503 /** @defgroup TIM_Input_Capture_Polarity
504 * @{
505 */
506
507 #define TIM_ICPolarity_Rising ((uint16_t)0x0000)
508 #define TIM_ICPolarity_Falling ((uint16_t)0x0002)
509 #define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
510 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
511 ((POLARITY) == TIM_ICPolarity_Falling)|| \
512 ((POLARITY) == TIM_ICPolarity_BothEdge))
513 /**
514 * @}
515 */
516
517 /** @defgroup TIM_Input_Capture_Selection
518 * @{
519 */
520
521 #define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
522 connected to IC1, IC2, IC3 or IC4, respectively */
523 #define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
524 connected to IC2, IC1, IC4 or IC3, respectively. */
525 #define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
526 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
527 ((SELECTION) == TIM_ICSelection_IndirectTI) || \
528 ((SELECTION) == TIM_ICSelection_TRC))
529 /**
530 * @}
531 */
532
533 /** @defgroup TIM_Input_Capture_Prescaler
534 * @{
535 */
536
537 #define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
538 #define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
539 #define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
540 #define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
541 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
542 ((PRESCALER) == TIM_ICPSC_DIV2) || \
543 ((PRESCALER) == TIM_ICPSC_DIV4) || \
544 ((PRESCALER) == TIM_ICPSC_DIV8))
545 /**
546 * @}
547 */
548
549 /** @defgroup TIM_interrupt_sources
550 * @{
551 */
552
553 #define TIM_IT_Update ((uint16_t)0x0001)
554 #define TIM_IT_CC1 ((uint16_t)0x0002)
555 #define TIM_IT_CC2 ((uint16_t)0x0004)
556 #define TIM_IT_CC3 ((uint16_t)0x0008)
557 #define TIM_IT_CC4 ((uint16_t)0x0010)
558 #define TIM_IT_COM ((uint16_t)0x0020)
559 #define TIM_IT_Trigger ((uint16_t)0x0040)
560 #define TIM_IT_Break ((uint16_t)0x0080)
561 #define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
562
563 #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
564 ((IT) == TIM_IT_CC1) || \
565 ((IT) == TIM_IT_CC2) || \
566 ((IT) == TIM_IT_CC3) || \
567 ((IT) == TIM_IT_CC4) || \
568 ((IT) == TIM_IT_COM) || \
569 ((IT) == TIM_IT_Trigger) || \
570 ((IT) == TIM_IT_Break))
571 /**
572 * @}
573 */
574
575 /** @defgroup TIM_DMA_Base_address
576 * @{
577 */
578
579 #define TIM_DMABase_CR1 ((uint16_t)0x0000)
580 #define TIM_DMABase_CR2 ((uint16_t)0x0001)
581 #define TIM_DMABase_SMCR ((uint16_t)0x0002)
582 #define TIM_DMABase_DIER ((uint16_t)0x0003)
583 #define TIM_DMABase_SR ((uint16_t)0x0004)
584 #define TIM_DMABase_EGR ((uint16_t)0x0005)
585 #define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
586 #define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
587 #define TIM_DMABase_CCER ((uint16_t)0x0008)
588 #define TIM_DMABase_CNT ((uint16_t)0x0009)
589 #define TIM_DMABase_PSC ((uint16_t)0x000A)
590 #define TIM_DMABase_ARR ((uint16_t)0x000B)
591 #define TIM_DMABase_RCR ((uint16_t)0x000C)
592 #define TIM_DMABase_CCR1 ((uint16_t)0x000D)
593 #define TIM_DMABase_CCR2 ((uint16_t)0x000E)
594 #define TIM_DMABase_CCR3 ((uint16_t)0x000F)
595 #define TIM_DMABase_CCR4 ((uint16_t)0x0010)
596 #define TIM_DMABase_BDTR ((uint16_t)0x0011)
597 #define TIM_DMABase_DCR ((uint16_t)0x0012)
598 #define TIM_DMABase_OR ((uint16_t)0x0013)
599 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
600 ((BASE) == TIM_DMABase_CR2) || \
601 ((BASE) == TIM_DMABase_SMCR) || \
602 ((BASE) == TIM_DMABase_DIER) || \
603 ((BASE) == TIM_DMABase_SR) || \
604 ((BASE) == TIM_DMABase_EGR) || \
605 ((BASE) == TIM_DMABase_CCMR1) || \
606 ((BASE) == TIM_DMABase_CCMR2) || \
607 ((BASE) == TIM_DMABase_CCER) || \
608 ((BASE) == TIM_DMABase_CNT) || \
609 ((BASE) == TIM_DMABase_PSC) || \
610 ((BASE) == TIM_DMABase_ARR) || \
611 ((BASE) == TIM_DMABase_RCR) || \
612 ((BASE) == TIM_DMABase_CCR1) || \
613 ((BASE) == TIM_DMABase_CCR2) || \
614 ((BASE) == TIM_DMABase_CCR3) || \
615 ((BASE) == TIM_DMABase_CCR4) || \
616 ((BASE) == TIM_DMABase_BDTR) || \
617 ((BASE) == TIM_DMABase_DCR) || \
618 ((BASE) == TIM_DMABase_OR))
619 /**
620 * @}
621 */
622
623 /** @defgroup TIM_DMA_Burst_Length
624 * @{
625 */
626
627 #define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
628 #define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
629 #define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
630 #define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
631 #define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
632 #define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
633 #define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
634 #define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
635 #define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
636 #define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
637 #define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
638 #define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
639 #define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
640 #define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
641 #define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
642 #define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
643 #define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
644 #define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
645 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
646 ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
647 ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
648 ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
649 ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
650 ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
651 ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
652 ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
653 ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
654 ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
655 ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
656 ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
657 ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
658 ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
659 ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
660 ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
661 ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
662 ((LENGTH) == TIM_DMABurstLength_18Transfers))
663 /**
664 * @}
665 */
666
667 /** @defgroup TIM_DMA_sources
668 * @{
669 */
670
671 #define TIM_DMA_Update ((uint16_t)0x0100)
672 #define TIM_DMA_CC1 ((uint16_t)0x0200)
673 #define TIM_DMA_CC2 ((uint16_t)0x0400)
674 #define TIM_DMA_CC3 ((uint16_t)0x0800)
675 #define TIM_DMA_CC4 ((uint16_t)0x1000)
676 #define TIM_DMA_COM ((uint16_t)0x2000)
677 #define TIM_DMA_Trigger ((uint16_t)0x4000)
678 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
679
680 /**
681 * @}
682 */
683
684 /** @defgroup TIM_External_Trigger_Prescaler
685 * @{
686 */
687
688 #define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
689 #define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
690 #define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
691 #define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
692 #define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
693 ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
694 ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
695 ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
696 /**
697 * @}
698 */
699
700 /** @defgroup TIM_Internal_Trigger_Selection
701 * @{
702 */
703
704 #define TIM_TS_ITR0 ((uint16_t)0x0000)
705 #define TIM_TS_ITR1 ((uint16_t)0x0010)
706 #define TIM_TS_ITR2 ((uint16_t)0x0020)
707 #define TIM_TS_ITR3 ((uint16_t)0x0030)
708 #define TIM_TS_TI1F_ED ((uint16_t)0x0040)
709 #define TIM_TS_TI1FP1 ((uint16_t)0x0050)
710 #define TIM_TS_TI2FP2 ((uint16_t)0x0060)
711 #define TIM_TS_ETRF ((uint16_t)0x0070)
712 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
713 ((SELECTION) == TIM_TS_ITR1) || \
714 ((SELECTION) == TIM_TS_ITR2) || \
715 ((SELECTION) == TIM_TS_ITR3) || \
716 ((SELECTION) == TIM_TS_TI1F_ED) || \
717 ((SELECTION) == TIM_TS_TI1FP1) || \
718 ((SELECTION) == TIM_TS_TI2FP2) || \
719 ((SELECTION) == TIM_TS_ETRF))
720 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
721 ((SELECTION) == TIM_TS_ITR1) || \
722 ((SELECTION) == TIM_TS_ITR2) || \
723 ((SELECTION) == TIM_TS_ITR3))
724 /**
725 * @}
726 */
727
728 /** @defgroup TIM_TIx_External_Clock_Source
729 * @{
730 */
731
732 #define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
733 #define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
734 #define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
735
736 /**
737 * @}
738 */
739
740 /** @defgroup TIM_External_Trigger_Polarity
741 * @{
742 */
743 #define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
744 #define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
745 #define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
746 ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
747 /**
748 * @}
749 */
750
751 /** @defgroup TIM_Prescaler_Reload_Mode
752 * @{
753 */
754
755 #define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
756 #define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
757 #define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
758 ((RELOAD) == TIM_PSCReloadMode_Immediate))
759 /**
760 * @}
761 */
762
763 /** @defgroup TIM_Forced_Action
764 * @{
765 */
766
767 #define TIM_ForcedAction_Active ((uint16_t)0x0050)
768 #define TIM_ForcedAction_InActive ((uint16_t)0x0040)
769 #define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
770 ((ACTION) == TIM_ForcedAction_InActive))
771 /**
772 * @}
773 */
774
775 /** @defgroup TIM_Encoder_Mode
776 * @{
777 */
778
779 #define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
780 #define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
781 #define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
782 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
783 ((MODE) == TIM_EncoderMode_TI2) || \
784 ((MODE) == TIM_EncoderMode_TI12))
785 /**
786 * @}
787 */
788
789
790 /** @defgroup TIM_Event_Source
791 * @{
792 */
793
794 #define TIM_EventSource_Update ((uint16_t)0x0001)
795 #define TIM_EventSource_CC1 ((uint16_t)0x0002)
796 #define TIM_EventSource_CC2 ((uint16_t)0x0004)
797 #define TIM_EventSource_CC3 ((uint16_t)0x0008)
798 #define TIM_EventSource_CC4 ((uint16_t)0x0010)
799 #define TIM_EventSource_COM ((uint16_t)0x0020)
800 #define TIM_EventSource_Trigger ((uint16_t)0x0040)
801 #define TIM_EventSource_Break ((uint16_t)0x0080)
802 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
803
804 /**
805 * @}
806 */
807
808 /** @defgroup TIM_Update_Source
809 * @{
810 */
811
812 #define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
813 or the setting of UG bit, or an update generation
814 through the slave mode controller. */
815 #define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
816 #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
817 ((SOURCE) == TIM_UpdateSource_Regular))
818 /**
819 * @}
820 */
821
822 /** @defgroup TIM_Output_Compare_Preload_State
823 * @{
824 */
825
826 #define TIM_OCPreload_Enable ((uint16_t)0x0008)
827 #define TIM_OCPreload_Disable ((uint16_t)0x0000)
828 #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
829 ((STATE) == TIM_OCPreload_Disable))
830 /**
831 * @}
832 */
833
834 /** @defgroup TIM_Output_Compare_Fast_State
835 * @{
836 */
837
838 #define TIM_OCFast_Enable ((uint16_t)0x0004)
839 #define TIM_OCFast_Disable ((uint16_t)0x0000)
840 #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
841 ((STATE) == TIM_OCFast_Disable))
842
843 /**
844 * @}
845 */
846
847 /** @defgroup TIM_Output_Compare_Clear_State
848 * @{
849 */
850
851 #define TIM_OCClear_Enable ((uint16_t)0x0080)
852 #define TIM_OCClear_Disable ((uint16_t)0x0000)
853 #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
854 ((STATE) == TIM_OCClear_Disable))
855 /**
856 * @}
857 */
858
859 /** @defgroup TIM_Trigger_Output_Source
860 * @{
861 */
862
863 #define TIM_TRGOSource_Reset ((uint16_t)0x0000)
864 #define TIM_TRGOSource_Enable ((uint16_t)0x0010)
865 #define TIM_TRGOSource_Update ((uint16_t)0x0020)
866 #define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
867 #define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
868 #define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
869 #define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
870 #define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
871 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
872 ((SOURCE) == TIM_TRGOSource_Enable) || \
873 ((SOURCE) == TIM_TRGOSource_Update) || \
874 ((SOURCE) == TIM_TRGOSource_OC1) || \
875 ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
876 ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
877 ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
878 ((SOURCE) == TIM_TRGOSource_OC4Ref))
879 /**
880 * @}
881 */
882
883 /** @defgroup TIM_Slave_Mode
884 * @{
885 */
886
887 #define TIM_SlaveMode_Reset ((uint16_t)0x0004)
888 #define TIM_SlaveMode_Gated ((uint16_t)0x0005)
889 #define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
890 #define TIM_SlaveMode_External1 ((uint16_t)0x0007)
891 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
892 ((MODE) == TIM_SlaveMode_Gated) || \
893 ((MODE) == TIM_SlaveMode_Trigger) || \
894 ((MODE) == TIM_SlaveMode_External1))
895 /**
896 * @}
897 */
898
899 /** @defgroup TIM_Master_Slave_Mode
900 * @{
901 */
902
903 #define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
904 #define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
905 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
906 ((STATE) == TIM_MasterSlaveMode_Disable))
907 /**
908 * @}
909 */
910 /** @defgroup TIM_Remap
911 * @{
912 */
913
914 #define TIM2_TIM8_TRGO ((uint16_t)0x0000)
915 #define TIM2_ETH_PTP ((uint16_t)0x0400)
916 #define TIM2_USBFS_SOF ((uint16_t)0x0800)
917 #define TIM2_USBHS_SOF ((uint16_t)0x0C00)
918
919 #define TIM5_GPIO ((uint16_t)0x0000)
920 #define TIM5_LSI ((uint16_t)0x0040)
921 #define TIM5_LSE ((uint16_t)0x0080)
922 #define TIM5_RTC ((uint16_t)0x00C0)
923
924 #define TIM11_GPIO ((uint16_t)0x0000)
925 #define TIM11_HSE ((uint16_t)0x0002)
926
927 #define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM2_TIM8_TRGO)||\
928 ((TIM_REMAP) == TIM2_ETH_PTP)||\
929 ((TIM_REMAP) == TIM2_USBFS_SOF)||\
930 ((TIM_REMAP) == TIM2_USBHS_SOF)||\
931 ((TIM_REMAP) == TIM5_GPIO)||\
932 ((TIM_REMAP) == TIM5_LSI)||\
933 ((TIM_REMAP) == TIM5_LSE)||\
934 ((TIM_REMAP) == TIM5_RTC)||\
935 ((TIM_REMAP) == TIM11_GPIO)||\
936 ((TIM_REMAP) == TIM11_HSE))
937
938 /**
939 * @}
940 */
941 /** @defgroup TIM_Flags
942 * @{
943 */
944
945 #define TIM_FLAG_Update ((uint16_t)0x0001)
946 #define TIM_FLAG_CC1 ((uint16_t)0x0002)
947 #define TIM_FLAG_CC2 ((uint16_t)0x0004)
948 #define TIM_FLAG_CC3 ((uint16_t)0x0008)
949 #define TIM_FLAG_CC4 ((uint16_t)0x0010)
950 #define TIM_FLAG_COM ((uint16_t)0x0020)
951 #define TIM_FLAG_Trigger ((uint16_t)0x0040)
952 #define TIM_FLAG_Break ((uint16_t)0x0080)
953 #define TIM_FLAG_CC1OF ((uint16_t)0x0200)
954 #define TIM_FLAG_CC2OF ((uint16_t)0x0400)
955 #define TIM_FLAG_CC3OF ((uint16_t)0x0800)
956 #define TIM_FLAG_CC4OF ((uint16_t)0x1000)
957 #define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
958 ((FLAG) == TIM_FLAG_CC1) || \
959 ((FLAG) == TIM_FLAG_CC2) || \
960 ((FLAG) == TIM_FLAG_CC3) || \
961 ((FLAG) == TIM_FLAG_CC4) || \
962 ((FLAG) == TIM_FLAG_COM) || \
963 ((FLAG) == TIM_FLAG_Trigger) || \
964 ((FLAG) == TIM_FLAG_Break) || \
965 ((FLAG) == TIM_FLAG_CC1OF) || \
966 ((FLAG) == TIM_FLAG_CC2OF) || \
967 ((FLAG) == TIM_FLAG_CC3OF) || \
968 ((FLAG) == TIM_FLAG_CC4OF))
969
970 /**
971 * @}
972 */
973
974 /** @defgroup TIM_Input_Capture_Filer_Value
975 * @{
976 */
977
978 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
979 /**
980 * @}
981 */
982
983 /** @defgroup TIM_External_Trigger_Filter
984 * @{
985 */
986
987 #define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
988 /**
989 * @}
990 */
991
992 /** @defgroup TIM_Legacy
993 * @{
994 */
995
996 #define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
997 #define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
998 #define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
999 #define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
1000 #define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
1001 #define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
1002 #define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
1003 #define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
1004 #define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
1005 #define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
1006 #define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
1007 #define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
1008 #define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
1009 #define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
1010 #define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
1011 #define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
1012 #define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
1013 #define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
1014 /**
1015 * @}
1016 */
1017
1018 /**
1019 * @}
1020 */
1021
1022 /* Exported macro ------------------------------------------------------------*/
1023 /* Exported functions --------------------------------------------------------*/
1024
1025 /* TimeBase management ********************************************************/
1026 void TIM_DeInit(TIM_TypeDef* TIMx);
1027 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
1028 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
1029 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
1030 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
1031 void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
1032 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
1033 uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
1034 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
1035 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
1036 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
1037 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
1038 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
1039 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
1040 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
1041
1042 /* Output Compare management **************************************************/
1043 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
1044 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
1045 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
1046 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
1047 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
1048 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
1049 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
1050 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
1051 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
1052 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
1053 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
1054 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
1055 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
1056 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
1057 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
1058 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
1059 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
1060 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
1061 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
1062 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
1063 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
1064 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
1065 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
1066 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
1067 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
1068 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
1069 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
1070 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
1071 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
1072 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
1073 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
1074 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
1075 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
1076 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
1077 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
1078
1079 /* Input Capture management ***************************************************/
1080 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
1081 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
1082 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
1083 uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
1084 uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
1085 uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
1086 uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
1087 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
1088 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
1089 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
1090 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
1091
1092 /* Advanced-control timers (TIM1 and TIM8) specific features ******************/
1093 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
1094 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
1095 void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
1096 void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
1097 void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
1098
1099 /* Interrupts, DMA and flags management ***************************************/
1100 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
1101 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
1102 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
1103 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
1104 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
1105 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
1106 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
1107 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
1108 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
1109
1110 /* Clocks management **********************************************************/
1111 void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
1112 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
1113 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
1114 uint16_t TIM_ICPolarity, uint16_t ICFilter);
1115 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
1116 uint16_t ExtTRGFilter);
1117 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
1118 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
1119
1120 /* Synchronization management *************************************************/
1121 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
1122 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
1123 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
1124 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
1125 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
1126 uint16_t ExtTRGFilter);
1127
1128 /* Specific interface management **********************************************/
1129 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
1130 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
1131 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
1132
1133 /* Specific remapping management **********************************************/
1134 void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
1135
1136 #ifdef __cplusplus
1137 }
1138 #endif
1139
1140 #endif /*__STM32F4xx_TIM_H */
1141
1142 /**
1143 * @}
1144 */
1145
1146 /**
1147 * @}
1148 */
1149
1150 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/