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Merge pull request #11270 from haslinghuis/rename_attr
[betaflight.git] / lib / main / STM32G4 / Drivers / CMSIS / Device / ST / STM32G4xx / Include / stm32g474xx.h
blob4a4d0198dc5a66c55ca2f76f84e155b0ccdbef53
1 /**
2 ******************************************************************************
3 * @file stm32g474xx.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32G474xx Device Peripheral Access Layer Header File.
6 *
7 * This file contains:
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral’s registers hardware
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
16 * All rights reserved.</center></h2>
17 *
18 * This software component is licensed by ST under BSD 3-Clause license,
19 * the "License"; You may not use this file except in compliance with the
20 * License. You may obtain a copy of the License at:
21 * opensource.org/licenses/BSD-3-Clause
22 *
23 ******************************************************************************
24 */
25
26 /** @addtogroup CMSIS_Device
27 * @{
28 */
29
30 /** @addtogroup stm32g474xx
31 * @{
32 */
33
34 #ifndef __STM32G474xx_H
35 #define __STM32G474xx_H
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif /* __cplusplus */
40
41 /** @addtogroup Configuration_section_for_CMSIS
42 * @{
43 */
44
45 /**
46 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
47 */
48 #define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
49 #define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */
50 #define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */
51 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
52 #define __FPU_PRESENT 1 /*!< FPU present */
53
54 /**
55 * @}
56 */
57
58 /** @addtogroup Peripheral_interrupt_number_definition
59 * @{
60 */
61
62 /**
63 * @brief STM32G4XX Interrupt Number Definition, according to the selected device
64 * in @ref Library_configuration_section
65 */
66 typedef enum
67 {
68 /****** Cortex-M4 Processor Exceptions Numbers *********************************************************************************/
69 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
70 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
71 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
72 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
73 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
74 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
75 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
76 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
77 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
78 /****** STM32 specific Interrupt Numbers ***************************************************************************************/
79 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
80 PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
81 RTC_TAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI */
82 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
83 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
84 RCC_IRQn = 5, /*!< RCC global Interrupt */
85 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
86 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
87 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
88 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
89 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
90 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
91 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
92 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
93 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
94 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
95 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
96 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
97 ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
98 USB_HP_IRQn = 19, /*!< USB HP Interrupt */
99 USB_LP_IRQn = 20, /*!< USB LP Interrupt */
100 FDCAN1_IT0_IRQn = 21, /*!< FDCAN1 IT0 Interrupt */
101 FDCAN1_IT1_IRQn = 22, /*!< FDCAN1 IT1 Interrupt */
102 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
103 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt */
104 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */
105 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */
106 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
107 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
108 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
109 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
110 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
111 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
112 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
113 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
114 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
115 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
116 USART1_IRQn = 37, /*!< USART1 global Interrupt */
117 USART2_IRQn = 38, /*!< USART2 global Interrupt */
118 USART3_IRQn = 39, /*!< USART3 global Interrupt */
119 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
120 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
121 USBWakeUp_IRQn = 42, /*!< USB Wakeup through EXTI line Interrupt */
122 TIM8_BRK_IRQn = 43, /*!< TIM8 Break, Transition error and Index error Interrupt */
123 TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
124 TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt */
125 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
126 ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
127 FMC_IRQn = 48, /*!< FMC global Interrupt */
128 LPTIM1_IRQn = 49, /*!< LP TIM1 Interrupt */
129 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
130 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
131 UART4_IRQn = 52, /*!< UART4 global Interrupt */
132 UART5_IRQn = 53, /*!< UART5 global Interrupt */
133 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&3 underrun error interrupts */
134 TIM7_DAC_IRQn = 55, /*!< TIM7 global and DAC2&4 underrun error interrupts */
135 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
136 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
137 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
138 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
139 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
140 ADC4_IRQn = 61, /*!< ADC4 global Interrupt */
141 ADC5_IRQn = 62, /*!< ADC5 global Interrupt */
142 UCPD1_IRQn = 63, /*!< UCPD global Interrupt */
143 COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 Interrupts */
144 COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 */
145 COMP7_IRQn = 66, /*!< COMP7 Interrupt */
146 HRTIM1_Master_IRQn = 67, /*!< HRTIM Master Timer global Interrupt */
147 HRTIM1_TIMA_IRQn = 68, /*!< HRTIM Timer A global Interrupt */
148 HRTIM1_TIMB_IRQn = 69, /*!< HRTIM Timer B global Interrupt */
149 HRTIM1_TIMC_IRQn = 70, /*!< HRTIM Timer C global Interrupt */
150 HRTIM1_TIMD_IRQn = 71, /*!< HRTIM Timer D global Interrupt */
151 HRTIM1_TIME_IRQn = 72, /*!< HRTIM Timer E global Interrupt */
152 HRTIM1_FLT_IRQn = 73, /*!< HRTIM Fault global Interrupt */
153 HRTIM1_TIMF_IRQn = 74, /*!< HRTIM Timer F global Interrupt */
154 CRS_IRQn = 75, /*!< CRS global interrupt */
155 SAI1_IRQn = 76, /*!< Serial Audio Interface global interrupt */
156 TIM20_BRK_IRQn = 77, /*!< TIM20 Break, Transition error and Index error Interrupt */
157 TIM20_UP_IRQn = 78, /*!< TIM20 Update interrupt */
158 TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger, Commutation, Direction change and Index Interrupt */
159 TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare interrupt */
160 FPU_IRQn = 81, /*!< FPU global interrupt */
161 I2C4_EV_IRQn = 82, /*!< I2C4 Event interrupt */
162 I2C4_ER_IRQn = 83, /*!< I2C4 Error interrupt */
163 SPI4_IRQn = 84, /*!< SPI4 Event interrupt */
164 FDCAN2_IT0_IRQn = 86, /*!< FDCAN2 interrupt line 0 interrupt */
165 FDCAN2_IT1_IRQn = 87, /*!< FDCAN2 interrupt line 1 interrupt */
166 FDCAN3_IT0_IRQn = 88, /*!< FDCAN3 interrupt line 0 interrupt */
167 FDCAN3_IT1_IRQn = 89, /*!< FDCAN3 interrupt line 1 interrupt */
168 RNG_IRQn = 90, /*!< RNG global interrupt */
169 LPUART1_IRQn = 91, /*!< LP UART 1 Interrupt */
170 I2C3_EV_IRQn = 92, /*!< I2C3 Event Interrupt */
171 I2C3_ER_IRQn = 93, /*!< I2C3 Error interrupt */
172 DMAMUX_OVR_IRQn = 94, /*!< DMAMUX overrun global interrupt */
173 QUADSPI_IRQn = 95, /*!< QUADSPI interrupt */
174 DMA1_Channel8_IRQn = 96, /*!< DMA1 Channel 8 interrupt */
175 DMA2_Channel6_IRQn = 97, /*!< DMA2 Channel 6 interrupt */
176 DMA2_Channel7_IRQn = 98, /*!< DMA2 Channel 7 interrupt */
177 DMA2_Channel8_IRQn = 99, /*!< DMA2 Channel 8 interrupt */
178 CORDIC_IRQn = 100, /*!< CORDIC global Interrupt */
179 FMAC_IRQn = 101 /*!< FMAC global Interrupt */
180 } IRQn_Type;
181
182 /**
183 * @}
184 */
185
186 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
187 #include "system_stm32g4xx.h"
188 #include <stdint.h>
189
190 /** @addtogroup Peripheral_registers_structures
191 * @{
192 */
193
194 /**
195 * @brief Analog to Digital Converter
196 */
197
198 typedef struct
199 {
200 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
201 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
202 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
203 __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
204 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
205 __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
206 __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
207 uint32_t RESERVED1; /*!< Reserved, 0x1C */
208 __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
209 __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
210 __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
211 uint32_t RESERVED2; /*!< Reserved, 0x2C */
212 __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
213 __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
214 __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
215 __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
216 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
217 uint32_t RESERVED3; /*!< Reserved, 0x44 */
218 uint32_t RESERVED4; /*!< Reserved, 0x48 */
219 __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
220 uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
221 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
222 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
223 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
224 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
225 uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
226 __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
227 __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
228 __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
229 __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
230 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
231 __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */
232 __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
233 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
234 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
235 __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
236 __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
237 uint32_t RESERVED10[2];/*!< Reserved, 0x0B8 - 0x0BC */
238 __IO uint32_t GCOMP; /*!< ADC calibration factors, Address offset: 0xC0 */
239 } ADC_TypeDef;
240
241 typedef struct
242 {
243 __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */
244 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */
245 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */
246 __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */
247 } ADC_Common_TypeDef;
248
249 /**
250 * @brief FD Controller Area Network
251 */
252
253 typedef struct
254 {
255 __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
256 __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
257 uint32_t RESERVED1; /*!< Reserved, 0x008 */
258 __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
259 __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
260 __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
261 __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
262 __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
263 __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
264 __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
265 __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
266 __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
267 uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
268 __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
269 __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
270 __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
271 uint32_t RESERVED3; /*!< Reserved, 0x04C */
272 __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
273 __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
274 __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
275 __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
276 uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
277 __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
278 __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */
279 __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */
280 uint32_t RESERVED5; /*!< Reserved, 0x08C */
281 __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */
282 __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */
283 __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */
284 __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */
285 uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */
286 __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
287 __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
288 __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */
289 __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */
290 __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */
291 __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */
292 __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */
293 __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */
294 __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */
295 __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */
296 __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */
297 } FDCAN_GlobalTypeDef;
298
299 /**
300 * @brief FD Controller Area Network Configuration
301 */
302
303 typedef struct
304 {
305 __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */
306 } FDCAN_Config_TypeDef;
307
308 /**
309 * @brief Comparator
310 */
311
312 typedef struct
313 {
314 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
315 } COMP_TypeDef;
316
317 /**
318 * @brief CRC calculation unit
319 */
320
321 typedef struct
322 {
323 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
324 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
325 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
326 uint32_t RESERVED0; /*!< Reserved, 0x0C */
327 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
328 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
329 } CRC_TypeDef;
330
331 /**
332 * @brief Clock Recovery System
333 */
334 typedef struct
335 {
336 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
337 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
338 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
339 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
340 } CRS_TypeDef;
341
342 /**
343 * @brief Digital to Analog Converter
344 */
345
346 typedef struct
347 {
348 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
349 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
350 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
351 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
352 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
353 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
354 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
355 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
356 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
357 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
358 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
359 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
360 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
361 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
362 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
363 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
364 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
365 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
366 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
367 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
368 __IO uint32_t RESERVED[2];
369 __IO uint32_t STR1; /*!< DAC Sawtooth register, Address offset: 0x58 */
370 __IO uint32_t STR2; /*!< DAC Sawtooth register, Address offset: 0x5C */
371 __IO uint32_t STMODR; /*!< DAC Sawtooth Mode register, Address offset: 0x60 */
372 } DAC_TypeDef;
373
374 /**
375 * @brief Debug MCU
376 */
377
378 typedef struct
379 {
380 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
381 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
382 __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
383 __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
384 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
385 } DBGMCU_TypeDef;
386
387 /**
388 * @brief DMA Controller
389 */
390
391 typedef struct
392 {
393 __IO uint32_t CCR; /*!< DMA channel x configuration register */
394 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
395 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
396 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
397 } DMA_Channel_TypeDef;
398
399 typedef struct
400 {
401 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
402 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
403 } DMA_TypeDef;
404
405 /**
406 * @brief DMA Multiplexer
407 */
408
409 typedef struct
410 {
411 __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */
412 }DMAMUX_Channel_TypeDef;
413
414 typedef struct
415 {
416 __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */
417 __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */
418 }DMAMUX_ChannelStatus_TypeDef;
419
420 typedef struct
421 {
422 __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */
423 }DMAMUX_RequestGen_TypeDef;
424
425 typedef struct
426 {
427 __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */
428 __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */
429 }DMAMUX_RequestGenStatus_TypeDef;
430
431 /**
432 * @brief External Interrupt/Event Controller
433 */
434
435 typedef struct
436 {
437 __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */
438 __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */
439 __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */
440 __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */
441 __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */
442 __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */
443 uint32_t RESERVED1; /*!< Reserved, 0x18 */
444 uint32_t RESERVED2; /*!< Reserved, 0x1C */
445 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */
446 __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */
447 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */
448 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */
449 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */
450 __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */
451 } EXTI_TypeDef;
452
453 /**
454 * @brief FLASH Registers
455 */
456
457 typedef struct
458 {
459 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
460 __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */
461 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */
462 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */
463 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */
464 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */
465 __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
466 uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */
467 __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */
468 __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
469 __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
470 __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
471 __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
472 uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34 */
473 __IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
474 __IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */
475 __IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */
476 __IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address offset: 0x50 */
477 uint32_t RESERVED3[7]; /*!< Reserved3, Address offset: 0x54 */
478 __IO uint32_t SEC1R; /*!< FLASH Securable memory register bank1, Address offset: 0x70 */
479 __IO uint32_t SEC2R; /*!< FLASH Securable memory register bank2, Address offset: 0x74 */
480 } FLASH_TypeDef;
481
482 /**
483 * @brief FMAC
484 */
485 typedef struct
486 {
487 __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */
488 __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */
489 __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */
490 __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */
491 __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */
492 __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */
493 __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */
494 __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */
495 } FMAC_TypeDef;
496
497 /**
498 * @brief Flexible Memory Controller
499 */
500
501 typedef struct
502 {
503 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
504 __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, Address offset: 0x20 */
505 } FMC_Bank1_TypeDef;
506
507 /**
508 * @brief Flexible Memory Controller Bank1E
509 */
510
511 typedef struct
512 {
513 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
514 } FMC_Bank1E_TypeDef;
515
516 /**
517 * @brief Flexible Memory Controller Bank3
518 */
519
520 typedef struct
521 {
522 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
523 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
524 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
525 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
526 uint32_t RESERVED0; /*!< Reserved, 0x90 */
527 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
528 } FMC_Bank3_TypeDef;
529
530 /**
531 * @brief General Purpose I/O
532 */
533
534 typedef struct
535 {
536 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
537 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
538 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
539 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
540 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
541 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
542 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
543 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
544 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
545 __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
546 } GPIO_TypeDef;
547
548 /**
549 * @brief Inter-integrated Circuit Interface
550 */
551
552 typedef struct
553 {
554 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
555 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
556 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
557 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
558 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
559 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
560 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
561 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
562 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
563 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
564 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
565 } I2C_TypeDef;
566
567 /**
568 * @brief Independent WATCHDOG
569 */
570
571 typedef struct
572 {
573 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
574 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
575 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
576 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
577 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
578 } IWDG_TypeDef;
579
580 /**
581 * @brief LPTIMER
582 */
583
584 typedef struct
585 {
586 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
587 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
588 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
589 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
590 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
591 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
592 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
593 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
594 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
595 } LPTIM_TypeDef;
596
597 /**
598 * @brief Operational Amplifier (OPAMP)
599 */
600
601 typedef struct
602 {
603 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
604 __IO uint32_t RESERVED[5]; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
605 __IO uint32_t TCMR; /*!< OPAMP timer controlled mux mode register, Address offset: 0x18 */
606 } OPAMP_TypeDef;
607
608 /**
609 * @brief Power Control
610 */
611
612 typedef struct
613 {
614 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
615 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
616 __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
617 __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */
618 __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */
619 __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */
620 __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */
621 uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */
622 __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */
623 __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
624 __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */
625 __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
626 __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */
627 __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
628 __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */
629 __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
630 __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */
631 __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
632 __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */
633 __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */
634 __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */
635 __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */
636 uint32_t RESERVED1[10]; /*!< Reserved Address offset: 0x58 - 0x7C */
637 __IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */
638 } PWR_TypeDef;
639
640 /**
641 * @brief QUAD Serial Peripheral Interface
642 */
643
644 typedef struct
645 {
646 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
647 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
648 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
649 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
650 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
651 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
652 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
653 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
654 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
655 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
656 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
657 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
658 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
659 } QUADSPI_TypeDef;
660
661 /**
662 * @brief Reset and Clock Control
663 */
664
665 typedef struct
666 {
667 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
668 __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */
669 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
670 __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */
671 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */
672 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
673 __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */
674 __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */
675 __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */
676 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */
677 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
678 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
679 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */
680 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */
681 __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
682 __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
683 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
684 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x44 */
685 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
686 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
687 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */
688 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x54 */
689 __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
690 __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
691 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
692 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x64 */
693 __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
694 __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
695 __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
696 uint32_t RESERVED7; /*!< Reserved, Address offset: 0x74 */
697 __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
698 __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
699 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
700 uint32_t RESERVED8; /*!< Reserved, Address offset: 0x84 */
701 __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */
702 uint32_t RESERVED9; /*!< Reserved, Address offset: 0x8C */
703 __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */
704 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */
705 __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */
706 __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */
707 } RCC_TypeDef;
708
709 /**
710 * @brief Real-Time Clock
711 */
712 /*
713 * @brief Specific device feature definitions
714 */
715 #define RTC_TAMP_INT_6_SUPPORT
716 #define RTC_TAMP_INT_NB 4u
717
718 #define RTC_TAMP_NB 3u
719 #define RTC_BACKUP_NB 32u
720
721
722 typedef struct
723 {
724 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
725 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
726 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */
727 __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
728 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
729 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
730 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
731 uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */
732 uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */
733 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
734 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
735 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
736 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
737 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
738 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
739 uint32_t RESERVED2; /*!< Reserved Address offset: 0x3C */
740 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
741 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
742 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */
743 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */
744 __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */
745 __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */
746 uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */
747 __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */
748 } RTC_TypeDef;
749
750 /**
751 * @brief Tamper and backup registers
752 */
753
754 typedef struct
755 {
756 __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */
757 __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */
758 uint32_t RESERVED0; /*!< no configuration register 3, Address offset: 0x08 */
759 __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */
760 uint32_t RESERVED1[6]; /*!< Reserved Address offset: 0x10 - 0x24 */
761 uint32_t RESERVED2; /*!< Reserved Address offset: 0x28 */
762 __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */
763 __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */
764 __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register Address offset: 0x34 */
765 uint32_t RESERVED3; /*!< Reserved Address offset: 0x38 */
766 __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */
767 uint32_t RESERVED4[48]; /*!< Reserved Address offset: 0x040 - 0xFC */
768 __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
769 __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
770 __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
771 __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */
772 __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */
773 __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */
774 __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */
775 __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */
776 __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */
777 __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */
778 __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */
779 __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */
780 __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */
781 __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */
782 __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */
783 __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */
784 __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */
785 __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */
786 __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */
787 __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */
788 __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */
789 __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */
790 __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */
791 __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */
792 __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */
793 __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */
794 __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */
795 __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */
796 __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */
797 __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */
798 __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */
799 __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */
800 } TAMP_TypeDef;
801
802 /**
803 * @brief Serial Audio Interface
804 */
805
806 typedef struct
807 {
808 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
809 uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */
810 __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
811 __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
812 } SAI_TypeDef;
813
814 typedef struct
815 {
816 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
817 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
818 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
819 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
820 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
821 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
822 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
823 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
824 } SAI_Block_TypeDef;
825
826 /**
827 * @brief Serial Peripheral Interface
828 */
829
830 typedef struct
831 {
832 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
833 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
834 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
835 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
836 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
837 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
838 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
839 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
840 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
841 } SPI_TypeDef;
842
843 /**
844 * @brief System configuration controller
845 */
846
847 typedef struct
848 {
849 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
850 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
851 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
852 __IO uint32_t SCSR; /*!< SYSCFG CCMSRAM control and status register, Address offset: 0x18 */
853 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */
854 __IO uint32_t SWPR; /*!< SYSCFG CCMSRAM write protection register, Address offset: 0x20 */
855 __IO uint32_t SKR; /*!< SYSCFG CCMSRAM Key Register, Address offset: 0x24 */
856 } SYSCFG_TypeDef;
857
858 /**
859 * @brief TIM
860 */
861
862 typedef struct
863 {
864 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
865 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
866 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
867 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
868 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
869 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
870 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
871 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
872 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
873 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
874 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
875 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
876 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
877 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
878 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
879 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
880 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
881 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
882 __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */
883 __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */
884 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */
885 __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */
886 __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */
887 __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */
888 __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
889 __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
890 __IO uint32_t OR ; /*!< TIM option register, Address offset: 0x68 */
891 uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */
892 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */
893 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */
894 } TIM_TypeDef;
895
896 /**
897 * @brief Universal Synchronous Asynchronous Receiver Transmitter
898 */
899 typedef struct
900 {
901 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
902 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
903 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
904 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
905 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
906 __IO uint32_t RTOR; /*!< USART Receiver Timeout register, Address offset: 0x14 */
907 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
908 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
909 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
910 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
911 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
912 __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
913 } USART_TypeDef;
914
915 /**
916 * @brief Universal Serial Bus Full Speed Device
917 */
918
919 typedef struct
920 {
921 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
922 __IO uint16_t RESERVED0; /*!< Reserved */
923 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
924 __IO uint16_t RESERVED1; /*!< Reserved */
925 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
926 __IO uint16_t RESERVED2; /*!< Reserved */
927 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
928 __IO uint16_t RESERVED3; /*!< Reserved */
929 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
930 __IO uint16_t RESERVED4; /*!< Reserved */
931 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
932 __IO uint16_t RESERVED5; /*!< Reserved */
933 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
934 __IO uint16_t RESERVED6; /*!< Reserved */
935 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
936 __IO uint16_t RESERVED7[17]; /*!< Reserved */
937 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
938 __IO uint16_t RESERVED8; /*!< Reserved */
939 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
940 __IO uint16_t RESERVED9; /*!< Reserved */
941 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
942 __IO uint16_t RESERVEDA; /*!< Reserved */
943 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
944 __IO uint16_t RESERVEDB; /*!< Reserved */
945 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
946 __IO uint16_t RESERVEDC; /*!< Reserved */
947 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
948 __IO uint16_t RESERVEDD; /*!< Reserved */
949 __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
950 __IO uint16_t RESERVEDE; /*!< Reserved */
951 } USB_TypeDef;
952
953 /**
954 * @brief VREFBUF
955 */
956
957 typedef struct
958 {
959 __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
960 __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
961 } VREFBUF_TypeDef;
962
963 /**
964 * @brief Window WATCHDOG
965 */
966
967 typedef struct
968 {
969 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
970 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
971 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
972 } WWDG_TypeDef;
973
974
975 /**
976 * @brief RNG
977 */
978 typedef struct
979 {
980 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
981 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
982 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
983 } RNG_TypeDef;
984
985 /**
986 * @brief CORDIC
987 */
988
989 typedef struct
990 {
991 __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */
992 __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */
993 __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */
994 } CORDIC_TypeDef;
995
996 /**
997 * @brief UCPD
998 */
999
1000 typedef struct
1001 {
1002 __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */
1003 __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */
1004 __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */
1005 __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */
1006 __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */
1007 __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */
1008 __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */
1009 __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */
1010 __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */
1011 __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */
1012 __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */
1013 __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */
1014 __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */
1015 __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */
1016 __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */
1017 } UCPD_TypeDef;
1018
1019 /**
1020 * @brief High resolution Timer (HRTIM)
1021 */
1022
1023 #define c7amba_hrtim1_v2_0
1024
1025 /* HRTIM master registers definition */
1026 typedef struct
1027 {
1028 __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */
1029 __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */
1030 __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */
1031 __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */
1032 __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */
1033 __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */
1034 __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */
1035 __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */
1036 uint32_t RESERVED0; /*!< Reserved, 0x20 */
1037 __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */
1038 __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */
1039 __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */
1040 uint32_t RESERVED1[20]; /*!< Reserved, 0x30..0x7C */
1041 }HRTIM_Master_TypeDef;
1042
1043 /* HRTIM Timer A to F registers definition */
1044 typedef struct
1045 {
1046 __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */
1047 __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */
1048 __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */
1049 __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */
1050 __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */
1051 __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */
1052 __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */
1053 __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */
1054 __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */
1055 __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */
1056 __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */
1057 __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */
1058 __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */
1059 __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */
1060 __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */
1061 __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */
1062 __IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */
1063 __IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */
1064 __IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */
1065 __IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */
1066 __IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */
1067 __IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */
1068 __IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */
1069 __IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */
1070 __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */
1071 __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */
1072 __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */
1073 __IO uint32_t TIMxCR2; /*!< HRTIM Timerx Control register 2, Address offset: 0x6C */
1074 __IO uint32_t EEFxR3; /*!< HRTIM Timerx external event filtering 3 register, Address offset: 0x70 */
1075 uint32_t RESERVED0[3]; /*!< Reserved, 0x74..0x7C */
1076 }HRTIM_Timerx_TypeDef;
1077
1078 /* HRTIM common register definition */
1079 typedef struct
1080 {
1081 __IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */
1082 __IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */
1083 __IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */
1084 __IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */
1085 __IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */
1086 __IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */
1087 __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */
1088 __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */
1089 __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */
1090 __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */
1091 __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */
1092 __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */
1093 __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */
1094 __IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */
1095 __IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */
1096 __IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */
1097 __IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */
1098 __IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */
1099 __IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */
1100 __IO uint32_t DLLCR; /*!< HRTIM DLL control register, Address offset: 0x4C */
1101 __IO uint32_t FLTINR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */
1102 __IO uint32_t FLTINR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */
1103 __IO uint32_t BDMUPR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */
1104 __IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */
1105 __IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */
1106 __IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */
1107 __IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */
1108 __IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */
1109 __IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */
1110 __IO uint32_t BDTFUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x74 */
1111 __IO uint32_t ADCER; /*!< HRTIM ADC Extended Trigger register, Address offset: 0x78 */
1112 __IO uint32_t ADCUR; /*!< HRTIM ADC Trigger Update register, Address offset: 0x7C */
1113 __IO uint32_t ADCPS1; /*!< HRTIM ADC Post Scaler Register 1, Address offset: 0x80 */
1114 __IO uint32_t ADCPS2; /*!< HRTIM ADC Post Scaler Register 2, Address offset: 0x84 */
1115 __IO uint32_t FLTINR3; /*!< HRTIM Fault input register3, Address offset: 0x88 */
1116 __IO uint32_t FLTINR4; /*!< HRTIM Fault input register4, Address offset: 0x8C */
1117 }HRTIM_Common_TypeDef;
1118
1119 /* HRTIM register definition */
1120 typedef struct {
1121 HRTIM_Master_TypeDef sMasterRegs;
1122 HRTIM_Timerx_TypeDef sTimerxRegs[6];
1123 // uint32_t RESERVED0[32];
1124 HRTIM_Common_TypeDef sCommonRegs;
1125 }HRTIM_TypeDef;
1126
1127 /**
1128 * @}
1129 */
1130
1131 /** @addtogroup Peripheral_memory_map
1132 * @{
1133 */
1134
1135 #define FLASH_BASE (0x08000000UL) /*!< FLASH (up to 512 kB) base address */
1136 #define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 80 KB) base address */
1137 #define SRAM2_BASE (0x20014000UL) /*!< SRAM2(16 KB) base address */
1138 #define CCMSRAM_BASE (0x10000000UL) /*!< CCMSRAM(32 KB) base address */
1139 #define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
1140 #define FMC_BASE (0x60000000UL) /*!< FMC base address */
1141 #define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */
1142
1143 #define FMC_R_BASE (0xA0000000UL) /*!< FMC control registers base address */
1144 #define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */
1145 #define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(80 KB) base address in the bit-band region */
1146 #define SRAM2_BB_BASE (0x22280000UL) /*!< SRAM2(16 KB) base address in the bit-band region */
1147 #define CCMSRAM_BB_BASE (0x22300000UL) /*!< CCMSRAM(32 KB) base address in the bit-band region */
1148 #define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */
1149 /* Legacy defines */
1150 #define SRAM_BASE SRAM1_BASE
1151 #define SRAM_BB_BASE SRAM1_BB_BASE
1152
1153 #define SRAM1_SIZE_MAX (0x00014000UL) /*!< maximum SRAM1 size (up to 80 KBytes) */
1154 #define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */
1155 #define CCMSRAM_SIZE (0x00008000UL) /*!< CCMSRAM size (32 KBytes) */
1156
1157 /*!< Peripheral memory map */
1158 #define APB1PERIPH_BASE PERIPH_BASE
1159 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
1160 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
1161 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
1162
1163 #define FMC_BANK1 FMC_BASE
1164 #define FMC_BANK1_1 FMC_BANK1
1165 #define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL)
1166 #define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL)
1167 #define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL)
1168 #define FMC_BANK3 (FMC_BASE + 0x20000000UL)
1169
1170 /*!< APB1 peripherals */
1171 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
1172 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
1173 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
1174 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
1175 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
1176 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
1177 #define CRS_BASE (APB1PERIPH_BASE + 0x2000UL)
1178 #define TAMP_BASE (APB1PERIPH_BASE + 0x2400UL)
1179 #define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
1180 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
1181 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
1182 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
1183 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
1184 #define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
1185 #define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
1186 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
1187 #define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
1188 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
1189 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
1190 #define USB_BASE (APB1PERIPH_BASE + 0x5C00UL) /*!< USB_IP Peripheral Registers base address */
1191 #define USB_PMAADDR (APB1PERIPH_BASE + 0x6000UL) /*!< USB_IP Packet Memory Area base address */
1192 #define FDCAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
1193 #define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0x6500UL) /*!< FDCAN configuration registers base address */
1194 #define FDCAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
1195 #define FDCAN3_BASE (APB1PERIPH_BASE + 0x6C00UL)
1196 #define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
1197 #define I2C3_BASE (APB1PERIPH_BASE + 0x7800UL)
1198 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL)
1199 #define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL)
1200 #define I2C4_BASE (APB1PERIPH_BASE + 0x8400UL)
1201 #define UCPD1_BASE (APB1PERIPH_BASE + 0xA000UL)
1202 #define SRAMCAN_BASE (APB1PERIPH_BASE + 0xA400UL)
1203
1204 /*!< APB2 peripherals */
1205 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL)
1206 #define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL)
1207 #define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL)
1208 #define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL)
1209 #define COMP3_BASE (APB2PERIPH_BASE + 0x0208UL)
1210 #define COMP4_BASE (APB2PERIPH_BASE + 0x020CUL)
1211 #define COMP5_BASE (APB2PERIPH_BASE + 0x0210UL)
1212 #define COMP6_BASE (APB2PERIPH_BASE + 0x0214UL)
1213 #define COMP7_BASE (APB2PERIPH_BASE + 0x0218UL)
1214 #define OPAMP_BASE (APB2PERIPH_BASE + 0x0300UL)
1215 #define OPAMP1_BASE (APB2PERIPH_BASE + 0x0300UL)
1216 #define OPAMP2_BASE (APB2PERIPH_BASE + 0x0304UL)
1217 #define OPAMP3_BASE (APB2PERIPH_BASE + 0x0308UL)
1218 #define OPAMP4_BASE (APB2PERIPH_BASE + 0x030CUL)
1219 #define OPAMP5_BASE (APB2PERIPH_BASE + 0x0310UL)
1220 #define OPAMP6_BASE (APB2PERIPH_BASE + 0x0314UL)
1221
1222 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL)
1223 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL)
1224 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
1225 #define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL)
1226 #define USART1_BASE (APB2PERIPH_BASE + 0x3800UL)
1227 #define SPI4_BASE (APB2PERIPH_BASE + 0x3C00UL)
1228 #define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL)
1229 #define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL)
1230 #define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL)
1231 #define TIM20_BASE (APB2PERIPH_BASE + 0x5000UL)
1232 #define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL)
1233 #define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL)
1234 #define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL)
1235 #define HRTIM1_BASE (APB2PERIPH_BASE + 0x6800UL)
1236 #define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x0080UL)
1237 #define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x0100UL)
1238 #define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x0180UL)
1239 #define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x0200UL)
1240 #define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x0280UL)
1241 #define HRTIM1_TIMF_BASE (HRTIM1_BASE + 0x0300UL)
1242 #define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x0380UL)
1243
1244 /*!< AHB1 peripherals */
1245 #define DMA1_BASE (AHB1PERIPH_BASE)
1246 #define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL)
1247 #define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL)
1248 #define CORDIC_BASE (AHB1PERIPH_BASE + 0x0C00UL)
1249 #define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL)
1250 #define FMAC_BASE (AHB1PERIPH_BASE + 0x1400UL)
1251 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL)
1252 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
1253
1254 #define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL)
1255 #define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL)
1256 #define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL)
1257 #define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL)
1258 #define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL)
1259 #define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL)
1260 #define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL)
1261 #define DMA1_Channel8_BASE (DMA1_BASE + 0x0094UL)
1262
1263 #define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL)
1264 #define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL)
1265 #define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL)
1266 #define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL)
1267 #define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL)
1268 #define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL)
1269 #define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL)
1270 #define DMA2_Channel8_BASE (DMA2_BASE + 0x0094UL)
1271
1272 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
1273 #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)
1274 #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)
1275 #define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)
1276 #define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)
1277 #define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)
1278 #define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL)
1279 #define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL)
1280 #define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL)
1281 #define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL)
1282 #define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL)
1283 #define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL)
1284 #define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL)
1285 #define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL)
1286 #define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL)
1287 #define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL)
1288 #define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)
1289 #define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)
1290 #define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)
1291 #define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)
1292
1293 #define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)
1294 #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)
1295
1296 /*!< AHB2 peripherals */
1297 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL)
1298 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL)
1299 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL)
1300 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL)
1301 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL)
1302 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL)
1303 #define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL)
1304
1305 #define ADC1_BASE (AHB2PERIPH_BASE + 0x08000000UL)
1306 #define ADC2_BASE (AHB2PERIPH_BASE + 0x08000100UL)
1307 #define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08000300UL)
1308 #define ADC3_BASE (AHB2PERIPH_BASE + 0x08000400UL)
1309 #define ADC4_BASE (AHB2PERIPH_BASE + 0x08000500UL)
1310 #define ADC5_BASE (AHB2PERIPH_BASE + 0x08000600UL)
1311 #define ADC345_COMMON_BASE (AHB2PERIPH_BASE + 0x08000700UL)
1312
1313 #define DAC_BASE (AHB2PERIPH_BASE + 0x08000800UL)
1314 #define DAC1_BASE (AHB2PERIPH_BASE + 0x08000800UL)
1315 #define DAC2_BASE (AHB2PERIPH_BASE + 0x08000C00UL)
1316 #define DAC3_BASE (AHB2PERIPH_BASE + 0x08001000UL)
1317 #define DAC4_BASE (AHB2PERIPH_BASE + 0x08001400UL)
1318
1319 /*!< FMC Banks registers base address */
1320 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
1321 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
1322 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
1323 #define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL)
1324 /* Debug MCU registers base address */
1325 #define DBGMCU_BASE (0xE0042000UL)
1326
1327 #define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */
1328 #define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */
1329 #define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */
1330 /**
1331 * @}
1332 */
1333
1334 /** @addtogroup Peripheral_declaration
1335 * @{
1336 */
1337 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1338 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1339 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1340 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1341 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1342 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1343 #define CRS ((CRS_TypeDef *) CRS_BASE)
1344 #define TAMP ((TAMP_TypeDef *) TAMP_BASE)
1345 #define RTC ((RTC_TypeDef *) RTC_BASE)
1346 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1347 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1348 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1349 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1350 #define USART2 ((USART_TypeDef *) USART2_BASE)
1351 #define USART3 ((USART_TypeDef *) USART3_BASE)
1352 #define UART4 ((USART_TypeDef *) UART4_BASE)
1353 #define UART5 ((USART_TypeDef *) UART5_BASE)
1354 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1355 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1356 #define USB ((USB_TypeDef *) USB_BASE)
1357 #define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
1358 #define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE)
1359 #define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
1360 #define FDCAN3 ((FDCAN_GlobalTypeDef *) FDCAN3_BASE)
1361 #define PWR ((PWR_TypeDef *) PWR_BASE)
1362 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1363 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1364 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
1365 #define I2C4 ((I2C_TypeDef *) I2C4_BASE)
1366 #define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE)
1367
1368 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1369 #define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
1370 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
1371 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
1372 #define COMP3 ((COMP_TypeDef *) COMP3_BASE)
1373 #define COMP4 ((COMP_TypeDef *) COMP4_BASE)
1374 #define COMP5 ((COMP_TypeDef *) COMP5_BASE)
1375 #define COMP6 ((COMP_TypeDef *) COMP6_BASE)
1376 #define COMP7 ((COMP_TypeDef *) COMP7_BASE)
1377
1378 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
1379 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
1380 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
1381 #define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)
1382 #define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE)
1383 #define OPAMP5 ((OPAMP_TypeDef *) OPAMP5_BASE)
1384 #define OPAMP6 ((OPAMP_TypeDef *) OPAMP6_BASE)
1385
1386 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1387 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1388 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1389 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1390 #define USART1 ((USART_TypeDef *) USART1_BASE)
1391 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1392 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
1393 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
1394 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
1395 #define TIM20 ((TIM_TypeDef *) TIM20_BASE)
1396 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1397 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1398 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1399 #define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)
1400 #define HRTIM1_TIMA ((HRTIM_TIM_TypeDef *) HRTIM1_TIMA_BASE)
1401 #define HRTIM1_TIMB ((HRTIM_TIM_TypeDef *) HRTIM1_TIMB_BASE)
1402 #define HRTIM1_TIMC ((HRTIM_TIM_TypeDef *) HRTIM1_TIMC_BASE)
1403 #define HRTIM1_TIMD ((HRTIM_TIM_TypeDef *) HRTIM1_TIMD_BASE)
1404 #define HRTIM1_TIME ((HRTIM_TIM_TypeDef *) HRTIM1_TIME_BASE)
1405 #define HRTIM1_TIMF ((HRTIM_TIM_TypeDef *) HRTIM1_TIMF_BASE)
1406 #define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
1407 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1408 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1409 #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
1410 #define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE)
1411 #define RCC ((RCC_TypeDef *) RCC_BASE)
1412 #define FMAC ((FMAC_TypeDef *) FMAC_BASE)
1413 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1414 #define CRC ((CRC_TypeDef *) CRC_BASE)
1415
1416 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1417 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1418 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1419 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1420 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1421 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1422 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1423 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1424 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1425 #define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
1426 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1427 #define ADC4 ((ADC_TypeDef *) ADC4_BASE)
1428 #define ADC5 ((ADC_TypeDef *) ADC5_BASE)
1429 #define ADC345_COMMON ((ADC_Common_TypeDef *) ADC345_COMMON_BASE)
1430 #define DAC ((DAC_TypeDef *) DAC_BASE)
1431 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
1432 #define DAC2 ((DAC_TypeDef *) DAC2_BASE)
1433 #define DAC3 ((DAC_TypeDef *) DAC3_BASE)
1434 #define DAC4 ((DAC_TypeDef *) DAC4_BASE)
1435 #define RNG ((RNG_TypeDef *) RNG_BASE)
1436
1437 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
1438 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
1439 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
1440 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
1441 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
1442 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
1443 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
1444 #define DMA1_Channel8 ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE)
1445
1446 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
1447 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
1448 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
1449 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
1450 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
1451 #define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
1452 #define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
1453 #define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE)
1454
1455 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
1456 #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
1457 #define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
1458 #define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
1459 #define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
1460 #define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
1461 #define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
1462 #define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
1463 #define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
1464 #define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
1465 #define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
1466 #define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
1467 #define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
1468 #define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
1469 #define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
1470 #define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
1471
1472 #define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
1473 #define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
1474 #define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
1475 #define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
1476
1477 #define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
1478 #define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
1479
1480 #define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1481 #define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1482 #define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1483
1484 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1485
1486 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1487
1488 /**
1489 * @}
1490 */
1491
1492 /** @addtogroup Exported_constants
1493 * @{
1494 */
1495
1496 /** @addtogroup Peripheral_Registers_Bits_Definition
1497 * @{
1498 */
1499
1500 /******************************************************************************/
1501 /* Peripheral Registers_Bits_Definition */
1502 /******************************************************************************/
1503
1504 /******************************************************************************/
1505 /* */
1506 /* Analog to Digital Converter */
1507 /* */
1508 /******************************************************************************/
1509
1510 /*
1511 * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
1512 */
1513 #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
1514
1515 /******************** Bit definition for ADC_ISR register *******************/
1516 #define ADC_ISR_ADRDY_Pos (0U)
1517 #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
1518 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
1519 #define ADC_ISR_EOSMP_Pos (1U)
1520 #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
1521 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
1522 #define ADC_ISR_EOC_Pos (2U)
1523 #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
1524 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
1525 #define ADC_ISR_EOS_Pos (3U)
1526 #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
1527 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
1528 #define ADC_ISR_OVR_Pos (4U)
1529 #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
1530 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
1531 #define ADC_ISR_JEOC_Pos (5U)
1532 #define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
1533 #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
1534 #define ADC_ISR_JEOS_Pos (6U)
1535 #define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
1536 #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
1537 #define ADC_ISR_AWD1_Pos (7U)
1538 #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
1539 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
1540 #define ADC_ISR_AWD2_Pos (8U)
1541 #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
1542 #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
1543 #define ADC_ISR_AWD3_Pos (9U)
1544 #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
1545 #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
1546 #define ADC_ISR_JQOVF_Pos (10U)
1547 #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
1548 #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
1549
1550 /******************** Bit definition for ADC_IER register *******************/
1551 #define ADC_IER_ADRDYIE_Pos (0U)
1552 #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
1553 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
1554 #define ADC_IER_EOSMPIE_Pos (1U)
1555 #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
1556 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
1557 #define ADC_IER_EOCIE_Pos (2U)
1558 #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
1559 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
1560 #define ADC_IER_EOSIE_Pos (3U)
1561 #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
1562 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
1563 #define ADC_IER_OVRIE_Pos (4U)
1564 #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
1565 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
1566 #define ADC_IER_JEOCIE_Pos (5U)
1567 #define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
1568 #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
1569 #define ADC_IER_JEOSIE_Pos (6U)
1570 #define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
1571 #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
1572 #define ADC_IER_AWD1IE_Pos (7U)
1573 #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
1574 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
1575 #define ADC_IER_AWD2IE_Pos (8U)
1576 #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
1577 #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
1578 #define ADC_IER_AWD3IE_Pos (9U)
1579 #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
1580 #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
1581 #define ADC_IER_JQOVFIE_Pos (10U)
1582 #define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
1583 #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
1584
1585 /******************** Bit definition for ADC_CR register ********************/
1586 #define ADC_CR_ADEN_Pos (0U)
1587 #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
1588 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
1589 #define ADC_CR_ADDIS_Pos (1U)
1590 #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
1591 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
1592 #define ADC_CR_ADSTART_Pos (2U)
1593 #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
1594 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
1595 #define ADC_CR_JADSTART_Pos (3U)
1596 #define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
1597 #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
1598 #define ADC_CR_ADSTP_Pos (4U)
1599 #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
1600 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
1601 #define ADC_CR_JADSTP_Pos (5U)
1602 #define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
1603 #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
1604 #define ADC_CR_ADVREGEN_Pos (28U)
1605 #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
1606 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
1607 #define ADC_CR_DEEPPWD_Pos (29U)
1608 #define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
1609 #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */
1610 #define ADC_CR_ADCALDIF_Pos (30U)
1611 #define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
1612 #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
1613 #define ADC_CR_ADCAL_Pos (31U)
1614 #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
1615 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
1616
1617 /******************** Bit definition for ADC_CFGR register ******************/
1618 #define ADC_CFGR_DMAEN_Pos (0U)
1619 #define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
1620 #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */
1621 #define ADC_CFGR_DMACFG_Pos (1U)
1622 #define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
1623 #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */
1624
1625 #define ADC_CFGR_RES_Pos (3U)
1626 #define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
1627 #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
1628 #define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
1629 #define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
1630
1631 #define ADC_CFGR_EXTSEL_Pos (5U)
1632 #define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */
1633 #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
1634 #define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */
1635 #define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
1636 #define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
1637 #define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
1638 #define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
1639
1640 #define ADC_CFGR_EXTEN_Pos (10U)
1641 #define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
1642 #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
1643 #define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
1644 #define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
1645
1646 #define ADC_CFGR_OVRMOD_Pos (12U)
1647 #define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
1648 #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
1649 #define ADC_CFGR_CONT_Pos (13U)
1650 #define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
1651 #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
1652 #define ADC_CFGR_AUTDLY_Pos (14U)
1653 #define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
1654 #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
1655 #define ADC_CFGR_ALIGN_Pos (15U)
1656 #define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */
1657 #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
1658 #define ADC_CFGR_DISCEN_Pos (16U)
1659 #define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
1660 #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
1661
1662 #define ADC_CFGR_DISCNUM_Pos (17U)
1663 #define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
1664 #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
1665 #define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
1666 #define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
1667 #define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
1668
1669 #define ADC_CFGR_JDISCEN_Pos (20U)
1670 #define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
1671 #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
1672 #define ADC_CFGR_JQM_Pos (21U)
1673 #define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
1674 #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
1675 #define ADC_CFGR_AWD1SGL_Pos (22U)
1676 #define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
1677 #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
1678 #define ADC_CFGR_AWD1EN_Pos (23U)
1679 #define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
1680 #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
1681 #define ADC_CFGR_JAWD1EN_Pos (24U)
1682 #define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
1683 #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
1684 #define ADC_CFGR_JAUTO_Pos (25U)
1685 #define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
1686 #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
1687
1688 #define ADC_CFGR_AWD1CH_Pos (26U)
1689 #define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
1690 #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
1691 #define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
1692 #define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
1693 #define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
1694 #define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
1695 #define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
1696
1697 #define ADC_CFGR_JQDIS_Pos (31U)
1698 #define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
1699 #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */
1700
1701 /******************** Bit definition for ADC_CFGR2 register *****************/
1702 #define ADC_CFGR2_ROVSE_Pos (0U)
1703 #define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
1704 #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
1705 #define ADC_CFGR2_JOVSE_Pos (1U)
1706 #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
1707 #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */
1708
1709 #define ADC_CFGR2_OVSR_Pos (2U)
1710 #define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
1711 #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
1712 #define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
1713 #define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
1714 #define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
1715
1716 #define ADC_CFGR2_OVSS_Pos (5U)
1717 #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
1718 #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
1719 #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
1720 #define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
1721 #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
1722 #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
1723
1724 #define ADC_CFGR2_TROVS_Pos (9U)
1725 #define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
1726 #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
1727 #define ADC_CFGR2_ROVSM_Pos (10U)
1728 #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
1729 #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
1730
1731 #define ADC_CFGR2_GCOMP_Pos (16U)
1732 #define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */
1733 #define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */
1734
1735 #define ADC_CFGR2_SWTRIG_Pos (25U)
1736 #define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */
1737 #define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */
1738 #define ADC_CFGR2_BULB_Pos (26U)
1739 #define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */
1740 #define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */
1741 #define ADC_CFGR2_SMPTRIG_Pos (27U)
1742 #define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */
1743 #define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */
1744
1745 #define ADC_CFGR2_LFTRIG_Pos (29U)
1746 #define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */
1747 #define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low Frequency Trigger */
1748
1749 /******************** Bit definition for ADC_SMPR1 register *****************/
1750 #define ADC_SMPR1_SMP0_Pos (0U)
1751 #define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
1752 #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
1753 #define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
1754 #define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
1755 #define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
1756
1757 #define ADC_SMPR1_SMP1_Pos (3U)
1758 #define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
1759 #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
1760 #define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
1761 #define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
1762 #define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
1763
1764 #define ADC_SMPR1_SMP2_Pos (6U)
1765 #define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
1766 #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
1767 #define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
1768 #define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
1769 #define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
1770
1771 #define ADC_SMPR1_SMP3_Pos (9U)
1772 #define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
1773 #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
1774 #define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
1775 #define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
1776 #define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
1777
1778 #define ADC_SMPR1_SMP4_Pos (12U)
1779 #define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
1780 #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
1781 #define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
1782 #define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
1783 #define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
1784
1785 #define ADC_SMPR1_SMP5_Pos (15U)
1786 #define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
1787 #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
1788 #define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
1789 #define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
1790 #define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
1791
1792 #define ADC_SMPR1_SMP6_Pos (18U)
1793 #define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
1794 #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
1795 #define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
1796 #define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
1797 #define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
1798
1799 #define ADC_SMPR1_SMP7_Pos (21U)
1800 #define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
1801 #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
1802 #define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
1803 #define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
1804 #define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
1805
1806 #define ADC_SMPR1_SMP8_Pos (24U)
1807 #define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
1808 #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
1809 #define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
1810 #define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
1811 #define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
1812
1813 #define ADC_SMPR1_SMP9_Pos (27U)
1814 #define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
1815 #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
1816 #define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
1817 #define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
1818 #define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
1819
1820 #define ADC_SMPR1_SMPPLUS_Pos (31U)
1821 #define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */
1822 #define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */
1823
1824 /******************** Bit definition for ADC_SMPR2 register *****************/
1825 #define ADC_SMPR2_SMP10_Pos (0U)
1826 #define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
1827 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
1828 #define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
1829 #define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
1830 #define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
1831
1832 #define ADC_SMPR2_SMP11_Pos (3U)
1833 #define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
1834 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
1835 #define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
1836 #define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
1837 #define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
1838
1839 #define ADC_SMPR2_SMP12_Pos (6U)
1840 #define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
1841 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
1842 #define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
1843 #define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
1844 #define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
1845
1846 #define ADC_SMPR2_SMP13_Pos (9U)
1847 #define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
1848 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
1849 #define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
1850 #define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
1851 #define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
1852
1853 #define ADC_SMPR2_SMP14_Pos (12U)
1854 #define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
1855 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
1856 #define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
1857 #define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
1858 #define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
1859
1860 #define ADC_SMPR2_SMP15_Pos (15U)
1861 #define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
1862 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
1863 #define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
1864 #define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
1865 #define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
1866
1867 #define ADC_SMPR2_SMP16_Pos (18U)
1868 #define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
1869 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
1870 #define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
1871 #define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
1872 #define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
1873
1874 #define ADC_SMPR2_SMP17_Pos (21U)
1875 #define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
1876 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
1877 #define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
1878 #define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
1879 #define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
1880
1881 #define ADC_SMPR2_SMP18_Pos (24U)
1882 #define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
1883 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
1884 #define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
1885 #define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
1886 #define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
1887
1888 /******************** Bit definition for ADC_TR1 register *******************/
1889 #define ADC_TR1_LT1_Pos (0U)
1890 #define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
1891 #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
1892
1893 #define ADC_TR1_AWDFILT_Pos (12U)
1894 #define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */
1895 #define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */
1896 #define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */
1897 #define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */
1898 #define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */
1899
1900 #define ADC_TR1_HT1_Pos (16U)
1901 #define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
1902 #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */
1903
1904 /******************** Bit definition for ADC_TR2 register *******************/
1905 #define ADC_TR2_LT2_Pos (0U)
1906 #define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
1907 #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
1908
1909 #define ADC_TR2_HT2_Pos (16U)
1910 #define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
1911 #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
1912
1913 /******************** Bit definition for ADC_TR3 register *******************/
1914 #define ADC_TR3_LT3_Pos (0U)
1915 #define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
1916 #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
1917
1918 #define ADC_TR3_HT3_Pos (16U)
1919 #define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
1920 #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
1921
1922 /******************** Bit definition for ADC_SQR1 register ******************/
1923 #define ADC_SQR1_L_Pos (0U)
1924 #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
1925 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
1926 #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
1927 #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
1928 #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
1929 #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */
1930
1931 #define ADC_SQR1_SQ1_Pos (6U)
1932 #define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
1933 #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
1934 #define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
1935 #define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
1936 #define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
1937 #define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
1938 #define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
1939
1940 #define ADC_SQR1_SQ2_Pos (12U)
1941 #define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
1942 #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
1943 #define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
1944 #define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
1945 #define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
1946 #define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
1947 #define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
1948
1949 #define ADC_SQR1_SQ3_Pos (18U)
1950 #define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
1951 #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
1952 #define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
1953 #define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
1954 #define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
1955 #define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
1956 #define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
1957
1958 #define ADC_SQR1_SQ4_Pos (24U)
1959 #define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
1960 #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
1961 #define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
1962 #define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
1963 #define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
1964 #define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
1965 #define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
1966
1967 /******************** Bit definition for ADC_SQR2 register ******************/
1968 #define ADC_SQR2_SQ5_Pos (0U)
1969 #define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
1970 #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
1971 #define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
1972 #define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
1973 #define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
1974 #define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
1975 #define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
1976
1977 #define ADC_SQR2_SQ6_Pos (6U)
1978 #define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
1979 #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
1980 #define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
1981 #define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
1982 #define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
1983 #define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
1984 #define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
1985
1986 #define ADC_SQR2_SQ7_Pos (12U)
1987 #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
1988 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
1989 #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
1990 #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
1991 #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
1992 #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
1993 #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
1994
1995 #define ADC_SQR2_SQ8_Pos (18U)
1996 #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
1997 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
1998 #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
1999 #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
2000 #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
2001 #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
2002 #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
2003
2004 #define ADC_SQR2_SQ9_Pos (24U)
2005 #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
2006 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
2007 #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
2008 #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
2009 #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
2010 #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
2011 #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
2012
2013 /******************** Bit definition for ADC_SQR3 register ******************/
2014 #define ADC_SQR3_SQ10_Pos (0U)
2015 #define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
2016 #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
2017 #define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
2018 #define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
2019 #define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
2020 #define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
2021 #define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
2022
2023 #define ADC_SQR3_SQ11_Pos (6U)
2024 #define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
2025 #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
2026 #define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
2027 #define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
2028 #define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
2029 #define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
2030 #define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
2031
2032 #define ADC_SQR3_SQ12_Pos (12U)
2033 #define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
2034 #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
2035 #define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
2036 #define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
2037 #define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
2038 #define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
2039 #define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
2040
2041 #define ADC_SQR3_SQ13_Pos (18U)
2042 #define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
2043 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
2044 #define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
2045 #define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
2046 #define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
2047 #define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
2048 #define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
2049
2050 #define ADC_SQR3_SQ14_Pos (24U)
2051 #define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
2052 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
2053 #define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
2054 #define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
2055 #define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
2056 #define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
2057 #define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
2058
2059 /******************** Bit definition for ADC_SQR4 register ******************/
2060 #define ADC_SQR4_SQ15_Pos (0U)
2061 #define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
2062 #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
2063 #define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
2064 #define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
2065 #define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
2066 #define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
2067 #define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
2068
2069 #define ADC_SQR4_SQ16_Pos (6U)
2070 #define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
2071 #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
2072 #define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
2073 #define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
2074 #define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
2075 #define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
2076 #define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
2077
2078 /******************** Bit definition for ADC_DR register ********************/
2079 #define ADC_DR_RDATA_Pos (0U)
2080 #define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
2081 #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
2082
2083 /******************** Bit definition for ADC_JSQR register ******************/
2084 #define ADC_JSQR_JL_Pos (0U)
2085 #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
2086 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
2087 #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
2088 #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
2089
2090 #define ADC_JSQR_JEXTSEL_Pos (2U)
2091 #define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
2092 #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
2093 #define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
2094 #define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
2095 #define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
2096 #define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
2097 #define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
2098
2099 #define ADC_JSQR_JEXTEN_Pos (7U)
2100 #define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
2101 #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
2102 #define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
2103 #define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
2104
2105 #define ADC_JSQR_JSQ1_Pos (9U)
2106 #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
2107 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
2108 #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
2109 #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
2110 #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
2111 #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
2112 #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
2113
2114 #define ADC_JSQR_JSQ2_Pos (15U)
2115 #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
2116 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
2117 #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
2118 #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
2119 #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
2120 #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
2121 #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
2122
2123 #define ADC_JSQR_JSQ3_Pos (21U)
2124 #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
2125 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
2126 #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
2127 #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
2128 #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
2129 #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
2130 #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
2131
2132 #define ADC_JSQR_JSQ4_Pos (27U)
2133 #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
2134 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
2135 #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
2136 #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
2137 #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
2138 #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
2139 #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
2140
2141 /******************** Bit definition for ADC_OFR1 register ******************/
2142 #define ADC_OFR1_OFFSET1_Pos (0U)
2143 #define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
2144 #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
2145
2146 #define ADC_OFR1_OFFSETPOS_Pos (24U)
2147 #define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */
2148 #define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */
2149 #define ADC_OFR1_SATEN_Pos (25U)
2150 #define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */
2151 #define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */
2152
2153 #define ADC_OFR1_OFFSET1_CH_Pos (26U)
2154 #define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
2155 #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
2156 #define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
2157 #define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
2158 #define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
2159 #define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
2160 #define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
2161
2162 #define ADC_OFR1_OFFSET1_EN_Pos (31U)
2163 #define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
2164 #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
2165
2166 /******************** Bit definition for ADC_OFR2 register ******************/
2167 #define ADC_OFR2_OFFSET2_Pos (0U)
2168 #define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
2169 #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
2170
2171 #define ADC_OFR2_OFFSETPOS_Pos (24U)
2172 #define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */
2173 #define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */
2174 #define ADC_OFR2_SATEN_Pos (25U)
2175 #define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */
2176 #define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */
2177
2178 #define ADC_OFR2_OFFSET2_CH_Pos (26U)
2179 #define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
2180 #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
2181 #define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
2182 #define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
2183 #define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
2184 #define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
2185 #define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
2186
2187 #define ADC_OFR2_OFFSET2_EN_Pos (31U)
2188 #define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
2189 #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
2190
2191 /******************** Bit definition for ADC_OFR3 register ******************/
2192 #define ADC_OFR3_OFFSET3_Pos (0U)
2193 #define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
2194 #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
2195
2196 #define ADC_OFR3_OFFSETPOS_Pos (24U)
2197 #define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */
2198 #define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */
2199 #define ADC_OFR3_SATEN_Pos (25U)
2200 #define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */
2201 #define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */
2202
2203 #define ADC_OFR3_OFFSET3_CH_Pos (26U)
2204 #define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
2205 #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
2206 #define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
2207 #define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
2208 #define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
2209 #define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
2210 #define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
2211
2212 #define ADC_OFR3_OFFSET3_EN_Pos (31U)
2213 #define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
2214 #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
2215
2216 /******************** Bit definition for ADC_OFR4 register ******************/
2217 #define ADC_OFR4_OFFSET4_Pos (0U)
2218 #define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
2219 #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
2220
2221 #define ADC_OFR4_OFFSETPOS_Pos (24U)
2222 #define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */
2223 #define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */
2224 #define ADC_OFR4_SATEN_Pos (25U)
2225 #define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */
2226 #define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */
2227
2228 #define ADC_OFR4_OFFSET4_CH_Pos (26U)
2229 #define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
2230 #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
2231 #define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
2232 #define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
2233 #define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
2234 #define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
2235 #define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
2236
2237 #define ADC_OFR4_OFFSET4_EN_Pos (31U)
2238 #define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
2239 #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
2240
2241 /******************** Bit definition for ADC_JDR1 register ******************/
2242 #define ADC_JDR1_JDATA_Pos (0U)
2243 #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
2244 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
2245
2246 /******************** Bit definition for ADC_JDR2 register ******************/
2247 #define ADC_JDR2_JDATA_Pos (0U)
2248 #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
2249 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
2250
2251 /******************** Bit definition for ADC_JDR3 register ******************/
2252 #define ADC_JDR3_JDATA_Pos (0U)
2253 #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
2254 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
2255
2256 /******************** Bit definition for ADC_JDR4 register ******************/
2257 #define ADC_JDR4_JDATA_Pos (0U)
2258 #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
2259 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
2260
2261 /******************** Bit definition for ADC_AWD2CR register ****************/
2262 #define ADC_AWD2CR_AWD2CH_Pos (0U)
2263 #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
2264 #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
2265 #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
2266 #define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
2267 #define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
2268 #define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
2269 #define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
2270 #define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
2271 #define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
2272 #define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
2273 #define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
2274 #define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
2275 #define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
2276 #define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
2277 #define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
2278 #define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
2279 #define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
2280 #define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
2281 #define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
2282 #define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
2283 #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
2284
2285 /******************** Bit definition for ADC_AWD3CR register ****************/
2286 #define ADC_AWD3CR_AWD3CH_Pos (0U)
2287 #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
2288 #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
2289 #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
2290 #define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
2291 #define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
2292 #define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
2293 #define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
2294 #define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
2295 #define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
2296 #define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
2297 #define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
2298 #define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
2299 #define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
2300 #define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
2301 #define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
2302 #define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
2303 #define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
2304 #define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
2305 #define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
2306 #define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
2307 #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
2308
2309 /******************** Bit definition for ADC_DIFSEL register ****************/
2310 #define ADC_DIFSEL_DIFSEL_Pos (0U)
2311 #define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
2312 #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
2313 #define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
2314 #define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
2315 #define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
2316 #define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
2317 #define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
2318 #define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
2319 #define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
2320 #define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
2321 #define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
2322 #define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
2323 #define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
2324 #define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
2325 #define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
2326 #define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
2327 #define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
2328 #define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
2329 #define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
2330 #define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
2331 #define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
2332
2333 /******************** Bit definition for ADC_CALFACT register ***************/
2334 #define ADC_CALFACT_CALFACT_S_Pos (0U)
2335 #define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
2336 #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
2337 #define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
2338 #define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
2339 #define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
2340 #define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
2341 #define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
2342 #define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
2343 #define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */
2344
2345 #define ADC_CALFACT_CALFACT_D_Pos (16U)
2346 #define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
2347 #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
2348 #define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
2349 #define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
2350 #define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
2351 #define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
2352 #define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
2353 #define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
2354 #define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */
2355
2356 /******************** Bit definition for ADC_GCOMP register *****************/
2357 #define ADC_GCOMP_GCOMPCOEFF_Pos (0U)
2358 #define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */
2359 #define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Gain Compensation Coefficient */
2360
2361 /************************* ADC Common registers *****************************/
2362 /******************** Bit definition for ADC_CSR register *******************/
2363 #define ADC_CSR_ADRDY_MST_Pos (0U)
2364 #define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
2365 #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */
2366 #define ADC_CSR_EOSMP_MST_Pos (1U)
2367 #define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
2368 #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */
2369 #define ADC_CSR_EOC_MST_Pos (2U)
2370 #define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
2371 #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */
2372 #define ADC_CSR_EOS_MST_Pos (3U)
2373 #define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
2374 #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */
2375 #define ADC_CSR_OVR_MST_Pos (4U)
2376 #define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
2377 #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */
2378 #define ADC_CSR_JEOC_MST_Pos (5U)
2379 #define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
2380 #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */
2381 #define ADC_CSR_JEOS_MST_Pos (6U)
2382 #define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
2383 #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */
2384 #define ADC_CSR_AWD1_MST_Pos (7U)
2385 #define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
2386 #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */
2387 #define ADC_CSR_AWD2_MST_Pos (8U)
2388 #define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
2389 #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */
2390 #define ADC_CSR_AWD3_MST_Pos (9U)
2391 #define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
2392 #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */
2393 #define ADC_CSR_JQOVF_MST_Pos (10U)
2394 #define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
2395 #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */
2396
2397 #define ADC_CSR_ADRDY_SLV_Pos (16U)
2398 #define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
2399 #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */
2400 #define ADC_CSR_EOSMP_SLV_Pos (17U)
2401 #define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
2402 #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */
2403 #define ADC_CSR_EOC_SLV_Pos (18U)
2404 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
2405 #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */
2406 #define ADC_CSR_EOS_SLV_Pos (19U)
2407 #define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
2408 #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */
2409 #define ADC_CSR_OVR_SLV_Pos (20U)
2410 #define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
2411 #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */
2412 #define ADC_CSR_JEOC_SLV_Pos (21U)
2413 #define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
2414 #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */
2415 #define ADC_CSR_JEOS_SLV_Pos (22U)
2416 #define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
2417 #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */
2418 #define ADC_CSR_AWD1_SLV_Pos (23U)
2419 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
2420 #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */
2421 #define ADC_CSR_AWD2_SLV_Pos (24U)
2422 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
2423 #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */
2424 #define ADC_CSR_AWD3_SLV_Pos (25U)
2425 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
2426 #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */
2427 #define ADC_CSR_JQOVF_SLV_Pos (26U)
2428 #define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
2429 #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */
2430
2431 /******************** Bit definition for ADC_CCR register *******************/
2432 #define ADC_CCR_DUAL_Pos (0U)
2433 #define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
2434 #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */
2435 #define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
2436 #define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
2437 #define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
2438 #define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
2439 #define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
2440
2441 #define ADC_CCR_DELAY_Pos (8U)
2442 #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
2443 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */
2444 #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
2445 #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
2446 #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
2447 #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
2448
2449 #define ADC_CCR_DMACFG_Pos (13U)
2450 #define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */
2451 #define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */
2452
2453 #define ADC_CCR_MDMA_Pos (14U)
2454 #define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */
2455 #define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */
2456 #define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */
2457 #define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */
2458
2459 #define ADC_CCR_CKMODE_Pos (16U)
2460 #define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
2461 #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
2462 #define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
2463 #define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
2464
2465 #define ADC_CCR_PRESC_Pos (18U)
2466 #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
2467 #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
2468 #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
2469 #define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
2470 #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
2471 #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
2472
2473 #define ADC_CCR_VREFEN_Pos (22U)
2474 #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
2475 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
2476 #define ADC_CCR_VSENSESEL_Pos (23U)
2477 #define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos) /*!< 0x00800000 */
2478 #define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk /*!< ADC internal path to temperature sensor enable */
2479 #define ADC_CCR_VBATSEL_Pos (24U)
2480 #define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos) /*!< 0x01000000 */
2481 #define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk /*!< ADC internal path to battery voltage enable */
2482
2483 /******************** Bit definition for ADC_CDR register *******************/
2484 #define ADC_CDR_RDATA_MST_Pos (0U)
2485 #define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
2486 #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
2487
2488 #define ADC_CDR_RDATA_SLV_Pos (16U)
2489 #define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
2490 #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
2491
2492
2493 /******************************************************************************/
2494 /* */
2495 /* Analog Comparators (COMP) */
2496 /* */
2497 /******************************************************************************/
2498 /********************** Bit definition for COMP_CSR register ****************/
2499 #define COMP_CSR_EN_Pos (0U)
2500 #define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */
2501 #define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */
2502
2503 #define COMP_CSR_DEGLITCHEN_Pos (1U)
2504 #define COMP_CSR_DEGLITCHEN_Msk (0x1UL << COMP_CSR_DEGLITCHEN_Pos) /*!< 0x00000002 */
2505 #define COMP_CSR_DEGLITCHEN COMP_CSR_DEGLITCHEN_Msk /*!< Comparator deglitcher enable */
2506
2507 #define COMP_CSR_INMSEL_Pos (4U)
2508 #define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */
2509 #define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */
2510 #define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */
2511 #define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */
2512 #define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */
2513 #define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */
2514
2515 #define COMP_CSR_INPSEL_Pos (8U)
2516 #define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */
2517 #define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */
2518
2519 #define COMP_CSR_POLARITY_Pos (15U)
2520 #define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */
2521 #define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */
2522
2523 #define COMP_CSR_HYST_Pos (16U)
2524 #define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos) /*!< 0x00070000 */
2525 #define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */
2526 #define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */
2527 #define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */
2528 #define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos) /*!< 0x00040000 */
2529
2530 #define COMP_CSR_BLANKING_Pos (19U)
2531 #define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */
2532 #define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */
2533 #define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
2534 #define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
2535 #define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */
2536
2537 #define COMP_CSR_BRGEN_Pos (22U)
2538 #define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */
2539 #define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */
2540
2541 #define COMP_CSR_SCALEN_Pos (23U)
2542 #define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */
2543 #define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */
2544
2545 #define COMP_CSR_VALUE_Pos (30U)
2546 #define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
2547 #define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */
2548
2549 #define COMP_CSR_LOCK_Pos (31U)
2550 #define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */
2551 #define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */
2552
2553 /******************************************************************************/
2554 /* */
2555 /* CORDIC calculation unit */
2556 /* */
2557 /******************************************************************************/
2558 /******************* Bit definition for CORDIC_CSR register *****************/
2559 #define CORDIC_CSR_FUNC_Pos (0U)
2560 #define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */
2561 #define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */
2562 #define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */
2563 #define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */
2564 #define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */
2565 #define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */
2566 #define CORDIC_CSR_PRECISION_Pos (4U)
2567 #define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */
2568 #define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */
2569 #define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */
2570 #define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */
2571 #define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */
2572 #define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */
2573 #define CORDIC_CSR_SCALE_Pos (8U)
2574 #define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */
2575 #define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */
2576 #define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */
2577 #define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */
2578 #define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */
2579 #define CORDIC_CSR_IEN_Pos (16U)
2580 #define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */
2581 #define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */
2582 #define CORDIC_CSR_DMAREN_Pos (17U)
2583 #define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */
2584 #define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */
2585 #define CORDIC_CSR_DMAWEN_Pos (18U)
2586 #define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */
2587 #define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */
2588 #define CORDIC_CSR_NRES_Pos (19U)
2589 #define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */
2590 #define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */
2591 #define CORDIC_CSR_NARGS_Pos (20U)
2592 #define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */
2593 #define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */
2594 #define CORDIC_CSR_RESSIZE_Pos (21U)
2595 #define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */
2596 #define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */
2597 #define CORDIC_CSR_ARGSIZE_Pos (22U)
2598 #define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */
2599 #define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */
2600 #define CORDIC_CSR_RRDY_Pos (31U)
2601 #define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */
2602 #define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */
2603
2604 /******************* Bit definition for CORDIC_WDATA register ***************/
2605 #define CORDIC_WDATA_ARG_Pos (0U)
2606 #define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */
2607 #define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */
2608
2609 /******************* Bit definition for CORDIC_RDATA register ***************/
2610 #define CORDIC_RDATA_RES_Pos (0U)
2611 #define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */
2612 #define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */
2613
2614
2615 /******************************************************************************/
2616 /* */
2617 /* CRC calculation unit */
2618 /* */
2619 /******************************************************************************/
2620 /******************* Bit definition for CRC_DR register *********************/
2621 #define CRC_DR_DR_Pos (0U)
2622 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
2623 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
2624
2625 /******************* Bit definition for CRC_IDR register ********************/
2626 #define CRC_IDR_IDR_Pos (0U)
2627 #define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
2628 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */
2629
2630 /******************** Bit definition for CRC_CR register ********************/
2631 #define CRC_CR_RESET_Pos (0U)
2632 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
2633 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
2634 #define CRC_CR_POLYSIZE_Pos (3U)
2635 #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
2636 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
2637 #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
2638 #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
2639 #define CRC_CR_REV_IN_Pos (5U)
2640 #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
2641 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
2642 #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
2643 #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
2644 #define CRC_CR_REV_OUT_Pos (7U)
2645 #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
2646 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
2647
2648 /******************* Bit definition for CRC_INIT register *******************/
2649 #define CRC_INIT_INIT_Pos (0U)
2650 #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
2651 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
2652
2653 /******************* Bit definition for CRC_POL register ********************/
2654 #define CRC_POL_POL_Pos (0U)
2655 #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
2656 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
2657
2658 /******************************************************************************/
2659 /* */
2660 /* CRS Clock Recovery System */
2661 /******************************************************************************/
2662
2663 /******************* Bit definition for CRS_CR register *********************/
2664 #define CRS_CR_SYNCOKIE_Pos (0U)
2665 #define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
2666 #define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
2667 #define CRS_CR_SYNCWARNIE_Pos (1U)
2668 #define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
2669 #define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
2670 #define CRS_CR_ERRIE_Pos (2U)
2671 #define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
2672 #define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
2673 #define CRS_CR_ESYNCIE_Pos (3U)
2674 #define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
2675 #define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
2676 #define CRS_CR_CEN_Pos (5U)
2677 #define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */
2678 #define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
2679 #define CRS_CR_AUTOTRIMEN_Pos (6U)
2680 #define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
2681 #define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
2682 #define CRS_CR_SWSYNC_Pos (7U)
2683 #define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
2684 #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
2685 #define CRS_CR_TRIM_Pos (8U)
2686 #define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */
2687 #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
2688
2689 /******************* Bit definition for CRS_CFGR register *********************/
2690 #define CRS_CFGR_RELOAD_Pos (0U)
2691 #define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
2692 #define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
2693 #define CRS_CFGR_FELIM_Pos (16U)
2694 #define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
2695 #define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
2696
2697 #define CRS_CFGR_SYNCDIV_Pos (24U)
2698 #define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
2699 #define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
2700 #define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
2701 #define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
2702 #define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
2703
2704 #define CRS_CFGR_SYNCSRC_Pos (28U)
2705 #define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
2706 #define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
2707 #define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
2708 #define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
2709
2710 #define CRS_CFGR_SYNCPOL_Pos (31U)
2711 #define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
2712 #define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
2713
2714 /******************* Bit definition for CRS_ISR register *********************/
2715 #define CRS_ISR_SYNCOKF_Pos (0U)
2716 #define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
2717 #define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
2718 #define CRS_ISR_SYNCWARNF_Pos (1U)
2719 #define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
2720 #define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
2721 #define CRS_ISR_ERRF_Pos (2U)
2722 #define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
2723 #define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
2724 #define CRS_ISR_ESYNCF_Pos (3U)
2725 #define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
2726 #define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
2727 #define CRS_ISR_SYNCERR_Pos (8U)
2728 #define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
2729 #define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
2730 #define CRS_ISR_SYNCMISS_Pos (9U)
2731 #define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
2732 #define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
2733 #define CRS_ISR_TRIMOVF_Pos (10U)
2734 #define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
2735 #define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
2736 #define CRS_ISR_FEDIR_Pos (15U)
2737 #define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
2738 #define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
2739 #define CRS_ISR_FECAP_Pos (16U)
2740 #define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
2741 #define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
2742
2743 /******************* Bit definition for CRS_ICR register *********************/
2744 #define CRS_ICR_SYNCOKC_Pos (0U)
2745 #define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
2746 #define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
2747 #define CRS_ICR_SYNCWARNC_Pos (1U)
2748 #define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
2749 #define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
2750 #define CRS_ICR_ERRC_Pos (2U)
2751 #define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
2752 #define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
2753 #define CRS_ICR_ESYNCC_Pos (3U)
2754 #define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
2755 #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
2756
2757 /******************************************************************************/
2758 /* */
2759 /* Digital to Analog Converter */
2760 /* */
2761 /******************************************************************************/
2762 /*
2763 * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
2764 */
2765 #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
2766
2767 /******************** Bit definition for DAC_CR register ********************/
2768 #define DAC_CR_EN1_Pos (0U)
2769 #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
2770 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
2771 #define DAC_CR_TEN1_Pos (1U)
2772 #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */
2773 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
2774
2775 #define DAC_CR_TSEL1_Pos (2U)
2776 #define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */
2777 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
2778 #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */
2779 #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
2780 #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
2781 #define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
2782
2783 #define DAC_CR_WAVE1_Pos (6U)
2784 #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
2785 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
2786 #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
2787 #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
2788
2789 #define DAC_CR_MAMP1_Pos (8U)
2790 #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
2791 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
2792 #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
2793 #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
2794 #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
2795 #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
2796
2797 #define DAC_CR_DMAEN1_Pos (12U)
2798 #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
2799 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
2800 #define DAC_CR_DMAUDRIE1_Pos (13U)
2801 #define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
2802 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
2803 #define DAC_CR_CEN1_Pos (14U)
2804 #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
2805 #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
2806
2807 #define DAC_CR_HFSEL_Pos (15U)
2808 #define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */
2809 #define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!<DAC channel 1 and 2 high frequency mode enable >*/
2810
2811 #define DAC_CR_EN2_Pos (16U)
2812 #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
2813 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
2814 #define DAC_CR_TEN2_Pos (17U)
2815 #define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00020000 */
2816 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
2817
2818 #define DAC_CR_TSEL2_Pos (18U)
2819 #define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */
2820 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[3:0] (DAC channel2 Trigger selection) */
2821 #define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */
2822 #define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
2823 #define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
2824 #define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
2825
2826 #define DAC_CR_WAVE2_Pos (22U)
2827 #define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
2828 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
2829 #define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
2830 #define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
2831
2832 #define DAC_CR_MAMP2_Pos (24U)
2833 #define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
2834 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
2835 #define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
2836 #define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
2837 #define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
2838 #define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
2839
2840 #define DAC_CR_DMAEN2_Pos (28U)
2841 #define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
2842 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
2843 #define DAC_CR_DMAUDRIE2_Pos (29U)
2844 #define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
2845 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
2846 #define DAC_CR_CEN2_Pos (30U)
2847 #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
2848 #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
2849
2850 /***************** Bit definition for DAC_SWTRIGR register ******************/
2851 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
2852 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
2853 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
2854 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
2855 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
2856 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
2857 #define DAC_SWTRIGR_SWTRIGB1_Pos (16U)
2858 #define DAC_SWTRIGR_SWTRIGB1_Msk (0x1UL << DAC_SWTRIGR_SWTRIGB1_Pos) /*!< 0x00010000 */
2859 #define DAC_SWTRIGR_SWTRIGB1 DAC_SWTRIGR_SWTRIGB1_Msk /*!<DAC channel1 software trigger B */
2860 #define DAC_SWTRIGR_SWTRIGB2_Pos (17U)
2861 #define DAC_SWTRIGR_SWTRIGB2_Msk (0x1UL << DAC_SWTRIGR_SWTRIGB2_Pos) /*!< 0x00020000 */
2862 #define DAC_SWTRIGR_SWTRIGB2 DAC_SWTRIGR_SWTRIGB2_Msk /*!<DAC channel2 software trigger B */
2863
2864 /***************** Bit definition for DAC_DHR12R1 register ******************/
2865 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
2866 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
2867 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
2868 #define DAC_DHR12R1_DACC1DHRB_Pos (16U)
2869 #define DAC_DHR12R1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x0FFF0000 */
2870 #define DAC_DHR12R1_DACC1DHRB DAC_DHR12R1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Right-aligned data B */
2871
2872 /***************** Bit definition for DAC_DHR12L1 register ******************/
2873 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
2874 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
2875 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
2876 #define DAC_DHR12L1_DACC1DHRB_Pos (20U)
2877 #define DAC_DHR12L1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0xFFF00000 */
2878 #define DAC_DHR12L1_DACC1DHRB DAC_DHR12L1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Left aligned data B */
2879
2880 /****************** Bit definition for DAC_DHR8R1 register ******************/
2881 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
2882 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
2883 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
2884 #define DAC_DHR8R1_DACC1DHRB_Pos (8U)
2885 #define DAC_DHR8R1_DACC1DHRB_Msk (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x0000FF00 */
2886 #define DAC_DHR8R1_DACC1DHRB DAC_DHR8R1_DACC1DHRB_Msk /*!<DAC channel1 8-bit Right aligned data B */
2887
2888 /***************** Bit definition for DAC_DHR12R2 register ******************/
2889 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
2890 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
2891 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
2892 #define DAC_DHR12R2_DACC2DHRB_Pos (16U)
2893 #define DAC_DHR12R2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHRB_Pos) /*!< 0x0FFF0000 */
2894 #define DAC_DHR12R2_DACC2DHRB DAC_DHR12R2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Right-aligned data B */
2895
2896 /***************** Bit definition for DAC_DHR12L2 register ******************/
2897 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
2898 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
2899 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
2900 #define DAC_DHR12L2_DACC2DHRB_Pos (20U)
2901 #define DAC_DHR12L2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHRB_Pos) /*!< 0xFFF00000 */
2902 #define DAC_DHR12L2_DACC2DHRB DAC_DHR12L2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Left aligned data B */
2903
2904 /****************** Bit definition for DAC_DHR8R2 register ******************/
2905 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
2906 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
2907 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
2908 #define DAC_DHR8R2_DACC2DHRB_Pos (8U)
2909 #define DAC_DHR8R2_DACC2DHRB_Msk (0xFFUL << DAC_DHR8R2_DACC2DHRB_Pos) /*!< 0x0000FF00 */
2910 #define DAC_DHR8R2_DACC2DHRB DAC_DHR8R2_DACC2DHRB_Msk /*!<DAC channel2 8-bit Right aligned data B */
2911
2912 /***************** Bit definition for DAC_DHR12RD register ******************/
2913 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
2914 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
2915 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
2916 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
2917 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
2918 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
2919
2920 /***************** Bit definition for DAC_DHR12LD register ******************/
2921 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
2922 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
2923 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
2924 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
2925 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
2926 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
2927
2928 /****************** Bit definition for DAC_DHR8RD register ******************/
2929 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
2930 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
2931 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
2932 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
2933 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
2934 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
2935
2936 /******************* Bit definition for DAC_DOR1 register *******************/
2937 #define DAC_DOR1_DACC1DOR_Pos (0U)
2938 #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
2939 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
2940 #define DAC_DOR1_DACC1DORB_Pos (16U)
2941 #define DAC_DOR1_DACC1DORB_Msk (0xFFFUL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x0FFF0000 */
2942 #define DAC_DOR1_DACC1DORB DAC_DOR1_DACC1DORB_Msk /*!<DAC channel1 data output B */
2943
2944 /******************* Bit definition for DAC_DOR2 register *******************/
2945 #define DAC_DOR2_DACC2DOR_Pos (0U)
2946 #define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
2947 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
2948 #define DAC_DOR2_DACC2DORB_Pos (16U)
2949 #define DAC_DOR2_DACC2DORB_Msk (0xFFFUL << DAC_DOR2_DACC2DORB_Pos) /*!< 0x0FFF0000 */
2950 #define DAC_DOR2_DACC2DORB DAC_DOR2_DACC2DORB_Msk /*!<DAC channel2 data output B */
2951
2952 /******************** Bit definition for DAC_SR register ********************/
2953 #define DAC_SR_DAC1RDY_Pos (11U)
2954 #define DAC_SR_DAC1RDY_Msk (0x1UL << DAC_SR_DAC1RDY_Pos) /*!< 0x00000800 */
2955 #define DAC_SR_DAC1RDY DAC_SR_DAC1RDY_Msk /*!<DAC channel 1 ready status bit */
2956 #define DAC_SR_DORSTAT1_Pos (12U)
2957 #define DAC_SR_DORSTAT1_Msk (0x1UL << DAC_SR_DORSTAT1_Pos) /*!< 0x00001000 */
2958 #define DAC_SR_DORSTAT1 DAC_SR_DORSTAT1_Msk /*!<DAC channel 1 output register status bit */
2959 #define DAC_SR_DMAUDR1_Pos (13U)
2960 #define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
2961 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
2962 #define DAC_SR_CAL_FLAG1_Pos (14U)
2963 #define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
2964 #define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
2965 #define DAC_SR_BWST1_Pos (15U)
2966 #define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */
2967 #define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
2968
2969
2970 #define DAC_SR_DAC2RDY_Pos (27U)
2971 #define DAC_SR_DAC2RDY_Msk (0x1UL << DAC_SR_DAC2RDY_Pos) /*!< 0x08000000 */
2972 #define DAC_SR_DAC2RDY DAC_SR_DAC2RDY_Msk /*!<DAC channel 2 ready status bit */
2973 #define DAC_SR_DORSTAT2_Pos (28U)
2974 #define DAC_SR_DORSTAT2_Msk (0x1UL << DAC_SR_DORSTAT2_Pos) /*!< 0x10000000 */
2975 #define DAC_SR_DORSTAT2 DAC_SR_DORSTAT2_Msk /*!<DAC channel 2 output register status bit */
2976 #define DAC_SR_DMAUDR2_Pos (29U)
2977 #define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
2978 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
2979 #define DAC_SR_CAL_FLAG2_Pos (30U)
2980 #define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
2981 #define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
2982 #define DAC_SR_BWST2_Pos (31U)
2983 #define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
2984 #define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
2985
2986 /******************* Bit definition for DAC_CCR register ********************/
2987 #define DAC_CCR_OTRIM1_Pos (0U)
2988 #define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
2989 #define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
2990 #define DAC_CCR_OTRIM2_Pos (16U)
2991 #define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
2992 #define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
2993
2994 /******************* Bit definition for DAC_MCR register *******************/
2995 #define DAC_MCR_MODE1_Pos (0U)
2996 #define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
2997 #define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
2998 #define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
2999 #define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
3000 #define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
3001
3002 #define DAC_MCR_DMADOUBLE1_Pos (8U)
3003 #define DAC_MCR_DMADOUBLE1_Msk (0x1UL << DAC_MCR_DMADOUBLE1_Pos) /*!< 0x00000100 */
3004 #define DAC_MCR_DMADOUBLE1 DAC_MCR_DMADOUBLE1_Msk /*!<DAC Channel 1 DMA double data mode */
3005
3006 #define DAC_MCR_SINFORMAT1_Pos (9U)
3007 #define DAC_MCR_SINFORMAT1_Msk (0x1UL << DAC_MCR_SINFORMAT1_Pos) /*!< 0x00000200 */
3008 #define DAC_MCR_SINFORMAT1 DAC_MCR_SINFORMAT1_Msk /*!<DAC Channel 1 enable signed format */
3009
3010 #define DAC_MCR_HFSEL_Pos (14U)
3011 #define DAC_MCR_HFSEL_Msk (0x3UL << DAC_MCR_HFSEL_Pos) /*!< 0x0000C000 */
3012 #define DAC_MCR_HFSEL DAC_MCR_HFSEL_Msk /*!<HFSEL[1:0] (High Frequency interface mode selection) */
3013 #define DAC_MCR_HFSEL_0 (0x1UL << DAC_MCR_HFSEL_Pos) /*!< 0x00004000 */
3014 #define DAC_MCR_HFSEL_1 (0x2UL << DAC_MCR_HFSEL_Pos) /*!< 0x00008000 */
3015
3016 #define DAC_MCR_MODE2_Pos (16U)
3017 #define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
3018 #define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
3019 #define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
3020 #define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
3021 #define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
3022
3023 #define DAC_MCR_DMADOUBLE2_Pos (24U)
3024 #define DAC_MCR_DMADOUBLE2_Msk (0x1UL << DAC_MCR_DMADOUBLE2_Pos) /*!< 0x01000000 */
3025 #define DAC_MCR_DMADOUBLE2 DAC_MCR_DMADOUBLE2_Msk /*!<DAC Channel 2 DMA double data mode */
3026
3027 #define DAC_MCR_SINFORMAT2_Pos (25U)
3028 #define DAC_MCR_SINFORMAT2_Msk (0x1UL << DAC_MCR_SINFORMAT2_Pos) /*!< 0x02000000 */
3029 #define DAC_MCR_SINFORMAT2 DAC_MCR_SINFORMAT2_Msk /*!<DAC Channel 2 enable signed format */
3030
3031 /****************** Bit definition for DAC_SHSR1 register ******************/
3032 #define DAC_SHSR1_TSAMPLE1_Pos (0U)
3033 #define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
3034 #define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
3035
3036 /****************** Bit definition for DAC_SHSR2 register ******************/
3037 #define DAC_SHSR2_TSAMPLE2_Pos (0U)
3038 #define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
3039 #define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
3040
3041 /****************** Bit definition for DAC_SHHR register ******************/
3042 #define DAC_SHHR_THOLD1_Pos (0U)
3043 #define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
3044 #define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
3045 #define DAC_SHHR_THOLD2_Pos (16U)
3046 #define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
3047 #define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
3048
3049 /****************** Bit definition for DAC_SHRR register ******************/
3050 #define DAC_SHRR_TREFRESH1_Pos (0U)
3051 #define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
3052 #define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
3053 #define DAC_SHRR_TREFRESH2_Pos (16U)
3054 #define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
3055 #define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
3056
3057 /****************** Bit definition for DAC_STR1 register ******************/
3058 #define DAC_STR1_STRSTDATA1_Pos (0U)
3059 #define DAC_STR1_STRSTDATA1_Msk (0xFFFUL << DAC_STR1_STRSTDATA1_Pos) /*!< 0x00000FFF */
3060 #define DAC_STR1_STRSTDATA1 DAC_STR1_STRSTDATA1_Msk /*!<DAC Channel 1 Sawtooth starting value */
3061 #define DAC_STR1_STDIR1_Pos (12U)
3062 #define DAC_STR1_STDIR1_Msk (0x1UL << DAC_STR1_STDIR1_Pos) /*!< 0x00001000 */
3063 #define DAC_STR1_STDIR1 DAC_STR1_STDIR1_Msk /*!<DAC Channel 1 Sawtooth direction setting */
3064
3065 #define DAC_STR1_STINCDATA1_Pos (16U)
3066 #define DAC_STR1_STINCDATA1_Msk (0xFFFFUL << DAC_STR1_STINCDATA1_Pos) /*!< 0xFFFF0000 */
3067 #define DAC_STR1_STINCDATA1 DAC_STR1_STINCDATA1_Msk /*!<DAC Channel 1 Sawtooth increment value (12.4 bit format) */
3068
3069 /****************** Bit definition for DAC_STR2 register ******************/
3070 #define DAC_STR2_STRSTDATA2_Pos (0U)
3071 #define DAC_STR2_STRSTDATA2_Msk (0xFFFUL << DAC_STR2_STRSTDATA2_Pos) /*!< 0x00000FFF */
3072 #define DAC_STR2_STRSTDATA2 DAC_STR2_STRSTDATA2_Msk /*!<DAC Channel 2 Sawtooth starting value */
3073 #define DAC_STR2_STDIR2_Pos (12U)
3074 #define DAC_STR2_STDIR2_Msk (0x1UL << DAC_STR2_STDIR2_Pos) /*!< 0x00001000 */
3075 #define DAC_STR2_STDIR2 DAC_STR2_STDIR2_Msk /*!<DAC Channel 2 Sawtooth direction setting */
3076
3077 #define DAC_STR2_STINCDATA2_Pos (16U)
3078 #define DAC_STR2_STINCDATA2_Msk (0xFFFFUL << DAC_STR2_STINCDATA2_Pos) /*!< 0xFFFF0000 */
3079 #define DAC_STR2_STINCDATA2 DAC_STR2_STINCDATA2_Msk /*!<DAC Channel 2 Sawtooth increment value (12.4 bit format) */
3080
3081 /****************** Bit definition for DAC_STMODR register ****************/
3082 #define DAC_STMODR_STRSTTRIGSEL1_Pos (0U)
3083 #define DAC_STMODR_STRSTTRIGSEL1_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x0000000F */
3084 #define DAC_STMODR_STRSTTRIGSEL1 DAC_STMODR_STRSTTRIGSEL1_Msk /*!<STRSTTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
3085 #define DAC_STMODR_STRSTTRIGSEL1_0 (0x1UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000001 */
3086 #define DAC_STMODR_STRSTTRIGSEL1_1 (0x2UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000002 */
3087 #define DAC_STMODR_STRSTTRIGSEL1_2 (0x4UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000004 */
3088 #define DAC_STMODR_STRSTTRIGSEL1_3 (0x8UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000008 */
3089
3090 #define DAC_STMODR_STINCTRIGSEL1_Pos (8U)
3091 #define DAC_STMODR_STINCTRIGSEL1_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x0000000F */
3092 #define DAC_STMODR_STINCTRIGSEL1 DAC_STMODR_STINCTRIGSEL1_Msk /*!<STINCTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
3093 #define DAC_STMODR_STINCTRIGSEL1_0 (0x1UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000001 */
3094 #define DAC_STMODR_STINCTRIGSEL1_1 (0x2UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000002 */
3095 #define DAC_STMODR_STINCTRIGSEL1_2 (0x4UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000004 */
3096 #define DAC_STMODR_STINCTRIGSEL1_3 (0x8UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000008 */
3097
3098 #define DAC_STMODR_STRSTTRIGSEL2_Pos (16U)
3099 #define DAC_STMODR_STRSTTRIGSEL2_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x0000000F */
3100 #define DAC_STMODR_STRSTTRIGSEL2 DAC_STMODR_STRSTTRIGSEL2_Msk /*!<STRSTTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
3101 #define DAC_STMODR_STRSTTRIGSEL2_0 (0x1UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000001 */
3102 #define DAC_STMODR_STRSTTRIGSEL2_1 (0x2UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000002 */
3103 #define DAC_STMODR_STRSTTRIGSEL2_2 (0x4UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000004 */
3104 #define DAC_STMODR_STRSTTRIGSEL2_3 (0x8UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000008 */
3105
3106 #define DAC_STMODR_STINCTRIGSEL2_Pos (24U)
3107 #define DAC_STMODR_STINCTRIGSEL2_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x0000000F */
3108 #define DAC_STMODR_STINCTRIGSEL2 DAC_STMODR_STINCTRIGSEL2_Msk /*!<STINCTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
3109 #define DAC_STMODR_STINCTRIGSEL2_0 (0x1UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000001 */
3110 #define DAC_STMODR_STINCTRIGSEL2_1 (0x2UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000002 */
3111 #define DAC_STMODR_STINCTRIGSEL2_2 (0x4UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000004 */
3112 #define DAC_STMODR_STINCTRIGSEL2_3 (0x8UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000008 */
3113
3114 /******************************************************************************/
3115 /* */
3116 /* Debug MCU */
3117 /* */
3118 /******************************************************************************/
3119 /******************** Bit definition for DBGMCU_IDCODE register *************/
3120 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
3121 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)/*!< 0x00000FFF */
3122 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
3123 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
3124 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)/*!< 0xFFFF0000 */
3125 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
3126
3127 /******************** Bit definition for DBGMCU_CR register *****************/
3128 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
3129 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)/*!< 0x00000001 */
3130 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
3131 #define DBGMCU_CR_DBG_STOP_Pos (1U)
3132 #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)/*!< 0x00000002 */
3133 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
3134 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
3135 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)/*!< 0x00000004 */
3136 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
3137 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
3138 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)/*!< 0x00000020 */
3139 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
3140
3141 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
3142 #define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x000000C0 */
3143 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
3144 #define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000040 */
3145 #define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000080 */
3146
3147 /******************** Bit definition for DBGMCU_APB1FZR1 register ***********/
3148 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U)
3149 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)/*!< 0x00000001 */
3150 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
3151 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos (1U)
3152 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos)/*!< 0x00000002 */
3153 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
3154 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U)
3155 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)/*!< 0x00000004 */
3156 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
3157 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U)
3158 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos)/*!< 0x00000008 */
3159 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk
3160 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U)
3161 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)/*!< 0x00000010 */
3162 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
3163 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U)
3164 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos)/*!< 0x00000020 */
3165 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
3166 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U)
3167 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)/*!< 0x00000400 */
3168 #define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
3169 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U)
3170 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)/*!< 0x00000800 */
3171 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
3172 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U)
3173 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)/*!< 0x00001000 */
3174 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
3175 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U)
3176 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)/*!< 0x00200000 */
3177 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
3178 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos (22U)
3179 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)/*!< 0x00400000 */
3180 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
3181 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (30U)
3182 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos)/*!< 0x40000000 */
3183 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
3184 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)
3185 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)/*!< 0x80000000 */
3186 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
3187
3188 /******************** Bit definition for DBGMCU_APB1FZR2 register **********/
3189 #define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos (1U)
3190 #define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos)/*!< 0x00000002 */
3191 #define DBGMCU_APB1FZR2_DBG_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk
3192
3193 /******************** Bit definition for DBGMCU_APB2FZ register ************/
3194 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
3195 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos)/*!< 0x00000800 */
3196 #define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
3197 #define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U)
3198 #define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos)/*!< 0x00002000 */
3199 #define DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk
3200 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U)
3201 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos)/*!< 0x00010000 */
3202 #define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
3203 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U)
3204 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */
3205 #define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
3206 #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U)
3207 #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */
3208 #define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
3209 #define DBGMCU_APB2FZ_DBG_TIM20_STOP_Pos (20U)
3210 #define DBGMCU_APB2FZ_DBG_TIM20_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM20_STOP_Pos)/*!< 0x00100000 */
3211 #define DBGMCU_APB2FZ_DBG_TIM20_STOP DBGMCU_APB2FZ_DBG_TIM20_STOP_Msk
3212 #define DBGMCU_APB2FZ_DBG_HRTIM1_STOP_Pos (26U)
3213 #define DBGMCU_APB2FZ_DBG_HRTIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_HRTIM1_STOP_Pos)/*!< 0x04000000 */
3214 #define DBGMCU_APB2FZ_DBG_HRTIM1_STOP DBGMCU_APB2FZ_DBG_HRTIM1_STOP_Msk
3215
3216 /******************************************************************************/
3217 /* */
3218 /* DMA Controller (DMA) */
3219 /* */
3220 /******************************************************************************/
3221
3222 /******************* Bit definition for DMA_ISR register ********************/
3223 #define DMA_ISR_GIF1_Pos (0U)
3224 #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
3225 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
3226 #define DMA_ISR_TCIF1_Pos (1U)
3227 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
3228 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
3229 #define DMA_ISR_HTIF1_Pos (2U)
3230 #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
3231 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
3232 #define DMA_ISR_TEIF1_Pos (3U)
3233 #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
3234 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
3235 #define DMA_ISR_GIF2_Pos (4U)
3236 #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
3237 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
3238 #define DMA_ISR_TCIF2_Pos (5U)
3239 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
3240 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
3241 #define DMA_ISR_HTIF2_Pos (6U)
3242 #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
3243 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
3244 #define DMA_ISR_TEIF2_Pos (7U)
3245 #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
3246 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
3247 #define DMA_ISR_GIF3_Pos (8U)
3248 #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
3249 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
3250 #define DMA_ISR_TCIF3_Pos (9U)
3251 #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
3252 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
3253 #define DMA_ISR_HTIF3_Pos (10U)
3254 #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
3255 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
3256 #define DMA_ISR_TEIF3_Pos (11U)
3257 #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
3258 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
3259 #define DMA_ISR_GIF4_Pos (12U)
3260 #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
3261 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
3262 #define DMA_ISR_TCIF4_Pos (13U)
3263 #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
3264 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
3265 #define DMA_ISR_HTIF4_Pos (14U)
3266 #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
3267 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
3268 #define DMA_ISR_TEIF4_Pos (15U)
3269 #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
3270 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
3271 #define DMA_ISR_GIF5_Pos (16U)
3272 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
3273 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
3274 #define DMA_ISR_TCIF5_Pos (17U)
3275 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
3276 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
3277 #define DMA_ISR_HTIF5_Pos (18U)
3278 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
3279 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
3280 #define DMA_ISR_TEIF5_Pos (19U)
3281 #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
3282 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
3283 #define DMA_ISR_GIF6_Pos (20U)
3284 #define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
3285 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
3286 #define DMA_ISR_TCIF6_Pos (21U)
3287 #define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
3288 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
3289 #define DMA_ISR_HTIF6_Pos (22U)
3290 #define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
3291 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
3292 #define DMA_ISR_TEIF6_Pos (23U)
3293 #define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
3294 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
3295 #define DMA_ISR_GIF7_Pos (24U)
3296 #define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
3297 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
3298 #define DMA_ISR_TCIF7_Pos (25U)
3299 #define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
3300 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
3301 #define DMA_ISR_HTIF7_Pos (26U)
3302 #define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
3303 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
3304 #define DMA_ISR_TEIF7_Pos (27U)
3305 #define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
3306 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
3307 #define DMA_ISR_GIF8_Pos (28U)
3308 #define DMA_ISR_GIF8_Msk (0x1UL << DMA_ISR_GIF8_Pos) /*!< 0x10000000 */
3309 #define DMA_ISR_GIF8 DMA_ISR_GIF8_Msk /*!< Channel 8 Global interrupt flag */
3310 #define DMA_ISR_TCIF8_Pos (29U)
3311 #define DMA_ISR_TCIF8_Msk (0x1UL << DMA_ISR_TCIF8_Pos) /*!< 0x20000000 */
3312 #define DMA_ISR_TCIF8 DMA_ISR_TCIF8_Msk /*!< Channel 8 Transfer Complete flag */
3313 #define DMA_ISR_HTIF8_Pos (30U)
3314 #define DMA_ISR_HTIF8_Msk (0x1UL << DMA_ISR_HTIF8_Pos) /*!< 0x40000000 */
3315 #define DMA_ISR_HTIF8 DMA_ISR_HTIF8_Msk /*!< Channel 8 Half Transfer flag */
3316 #define DMA_ISR_TEIF8_Pos (31U)
3317 #define DMA_ISR_TEIF8_Msk (0x1UL << DMA_ISR_TEIF8_Pos) /*!< 0x80000000 */
3318 #define DMA_ISR_TEIF8 DMA_ISR_TEIF8_Msk /*!< Channel 8 Transfer Error flag */
3319
3320 /******************* Bit definition for DMA_IFCR register *******************/
3321 #define DMA_IFCR_CGIF1_Pos (0U)
3322 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
3323 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */
3324 #define DMA_IFCR_CTCIF1_Pos (1U)
3325 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
3326 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
3327 #define DMA_IFCR_CHTIF1_Pos (2U)
3328 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
3329 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
3330 #define DMA_IFCR_CTEIF1_Pos (3U)
3331 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
3332 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
3333 #define DMA_IFCR_CGIF2_Pos (4U)
3334 #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
3335 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
3336 #define DMA_IFCR_CTCIF2_Pos (5U)
3337 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
3338 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
3339 #define DMA_IFCR_CHTIF2_Pos (6U)
3340 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
3341 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
3342 #define DMA_IFCR_CTEIF2_Pos (7U)
3343 #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
3344 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
3345 #define DMA_IFCR_CGIF3_Pos (8U)
3346 #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
3347 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
3348 #define DMA_IFCR_CTCIF3_Pos (9U)
3349 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
3350 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
3351 #define DMA_IFCR_CHTIF3_Pos (10U)
3352 #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
3353 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
3354 #define DMA_IFCR_CTEIF3_Pos (11U)
3355 #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
3356 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
3357 #define DMA_IFCR_CGIF4_Pos (12U)
3358 #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
3359 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
3360 #define DMA_IFCR_CTCIF4_Pos (13U)
3361 #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
3362 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
3363 #define DMA_IFCR_CHTIF4_Pos (14U)
3364 #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
3365 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
3366 #define DMA_IFCR_CTEIF4_Pos (15U)
3367 #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
3368 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
3369 #define DMA_IFCR_CGIF5_Pos (16U)
3370 #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
3371 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
3372 #define DMA_IFCR_CTCIF5_Pos (17U)
3373 #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
3374 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
3375 #define DMA_IFCR_CHTIF5_Pos (18U)
3376 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
3377 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
3378 #define DMA_IFCR_CTEIF5_Pos (19U)
3379 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
3380 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
3381 #define DMA_IFCR_CGIF6_Pos (20U)
3382 #define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
3383 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
3384 #define DMA_IFCR_CTCIF6_Pos (21U)
3385 #define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
3386 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
3387 #define DMA_IFCR_CHTIF6_Pos (22U)
3388 #define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
3389 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
3390 #define DMA_IFCR_CTEIF6_Pos (23U)
3391 #define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
3392 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
3393 #define DMA_IFCR_CGIF7_Pos (24U)
3394 #define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
3395 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
3396 #define DMA_IFCR_CTCIF7_Pos (25U)
3397 #define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
3398 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
3399 #define DMA_IFCR_CHTIF7_Pos (26U)
3400 #define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
3401 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
3402 #define DMA_IFCR_CTEIF7_Pos (27U)
3403 #define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
3404 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
3405 #define DMA_IFCR_CGIF8_Pos (28U)
3406 #define DMA_IFCR_CGIF8_Msk (0x1UL << DMA_IFCR_CGIF8_Pos) /*!< 0x10000000 */
3407 #define DMA_IFCR_CGIF8 DMA_IFCR_CGIF8_Msk /*!< Channel 8 Global interrupt clear */
3408 #define DMA_IFCR_CTCIF8_Pos (29U)
3409 #define DMA_IFCR_CTCIF8_Msk (0x1UL << DMA_IFCR_CTCIF8_Pos) /*!< 0x20000000 */
3410 #define DMA_IFCR_CTCIF8 DMA_IFCR_CTCIF8_Msk /*!< Channel 8 Transfer Complete clear */
3411 #define DMA_IFCR_CHTIF8_Pos (30U)
3412 #define DMA_IFCR_CHTIF8_Msk (0x1UL << DMA_IFCR_CHTIF8_Pos) /*!< 0x40000000 */
3413 #define DMA_IFCR_CHTIF8 DMA_IFCR_CHTIF8_Msk /*!< Channel 8 Half Transfer clear */
3414 #define DMA_IFCR_CTEIF8_Pos (31U)
3415 #define DMA_IFCR_CTEIF8_Msk (0x1UL << DMA_IFCR_CTEIF8_Pos) /*!< 0x80000000 */
3416 #define DMA_IFCR_CTEIF8 DMA_IFCR_CTEIF8_Msk /*!< Channel 8 Transfer Error clear */
3417
3418 /******************* Bit definition for DMA_CCR register ********************/
3419 #define DMA_CCR_EN_Pos (0U)
3420 #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
3421 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
3422 #define DMA_CCR_TCIE_Pos (1U)
3423 #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
3424 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
3425 #define DMA_CCR_HTIE_Pos (2U)
3426 #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
3427 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
3428 #define DMA_CCR_TEIE_Pos (3U)
3429 #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
3430 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
3431 #define DMA_CCR_DIR_Pos (4U)
3432 #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
3433 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
3434 #define DMA_CCR_CIRC_Pos (5U)
3435 #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
3436 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
3437 #define DMA_CCR_PINC_Pos (6U)
3438 #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
3439 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
3440 #define DMA_CCR_MINC_Pos (7U)
3441 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
3442 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
3443
3444 #define DMA_CCR_PSIZE_Pos (8U)
3445 #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
3446 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
3447 #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
3448 #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
3449
3450 #define DMA_CCR_MSIZE_Pos (10U)
3451 #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
3452 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
3453 #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
3454 #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
3455
3456 #define DMA_CCR_PL_Pos (12U)
3457 #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
3458 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
3459 #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
3460 #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
3461
3462 #define DMA_CCR_MEM2MEM_Pos (14U)
3463 #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
3464 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
3465
3466 /****************** Bit definition for DMA_CNDTR register *******************/
3467 #define DMA_CNDTR_NDT_Pos (0U)
3468 #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
3469 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
3470
3471 /****************** Bit definition for DMA_CPAR register ********************/
3472 #define DMA_CPAR_PA_Pos (0U)
3473 #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
3474 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
3475
3476 /****************** Bit definition for DMA_CMAR register ********************/
3477 #define DMA_CMAR_MA_Pos (0U)
3478 #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
3479 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
3480
3481 /******************************************************************************/
3482 /* */
3483 /* DMAMUX Controller */
3484 /* */
3485 /******************************************************************************/
3486
3487 /******************** Bits definition for DMAMUX_CxCR register **************/
3488 #define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
3489 #define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x000000FF */
3490 #define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk
3491 #define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */
3492 #define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000002 */
3493 #define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000004 */
3494 #define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000008 */
3495 #define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000010 */
3496 #define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */
3497 #define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */
3498 #define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000080 */
3499
3500 #define DMAMUX_CxCR_SOIE_Pos (8U)
3501 #define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos)/*!< 0x00000100 */
3502 #define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk
3503
3504 #define DMAMUX_CxCR_EGE_Pos (9U)
3505 #define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos)/*!< 0x00000200 */
3506 #define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk
3507
3508 #define DMAMUX_CxCR_SE_Pos (16U)
3509 #define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos)/*!< 0x00010000 */
3510 #define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk
3511
3512 #define DMAMUX_CxCR_SPOL_Pos (17U)
3513 #define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00060000 */
3514 #define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk
3515 #define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00020000 */
3516 #define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00040000 */
3517
3518 #define DMAMUX_CxCR_NBREQ_Pos (19U)
3519 #define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00F80000 */
3520 #define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk
3521 #define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00080000 */
3522 #define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00100000 */
3523 #define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00200000 */
3524 #define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00400000 */
3525 #define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00800000 */
3526
3527 #define DMAMUX_CxCR_SYNC_ID_Pos (24U)
3528 #define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x1F000000 */
3529 #define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk
3530 #define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x01000000 */
3531 #define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x02000000 */
3532 #define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x04000000 */
3533 #define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x08000000 */
3534 #define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x10000000 */
3535
3536 /******************** Bits definition for DMAMUX_CSR register ****************/
3537 #define DMAMUX_CSR_SOF0_Pos (0U)
3538 #define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos)/*!< 0x00000001 */
3539 #define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk
3540 #define DMAMUX_CSR_SOF1_Pos (1U)
3541 #define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos)/*!< 0x00000002 */
3542 #define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk
3543 #define DMAMUX_CSR_SOF2_Pos (2U)
3544 #define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos)/*!< 0x00000004 */
3545 #define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk
3546 #define DMAMUX_CSR_SOF3_Pos (3U)
3547 #define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos)/*!< 0x00000008 */
3548 #define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk
3549 #define DMAMUX_CSR_SOF4_Pos (4U)
3550 #define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos)/*!< 0x00000010 */
3551 #define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk
3552 #define DMAMUX_CSR_SOF5_Pos (5U)
3553 #define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos)/*!< 0x00000020 */
3554 #define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk
3555 #define DMAMUX_CSR_SOF6_Pos (6U)
3556 #define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos)/*!< 0x00000040 */
3557 #define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk
3558 #define DMAMUX_CSR_SOF7_Pos (7U)
3559 #define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos)/*!< 0x00000080 */
3560 #define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk
3561 #define DMAMUX_CSR_SOF8_Pos (8U)
3562 #define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos)/*!< 0x00000100 */
3563 #define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk
3564 #define DMAMUX_CSR_SOF9_Pos (9U)
3565 #define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos)/*!< 0x00000200 */
3566 #define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk
3567 #define DMAMUX_CSR_SOF10_Pos (10U)
3568 #define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos)/*!< 0x00000400 */
3569 #define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk
3570 #define DMAMUX_CSR_SOF11_Pos (11U)
3571 #define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos)/*!< 0x00000800 */
3572 #define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk
3573 #define DMAMUX_CSR_SOF12_Pos (12U)
3574 #define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos)/*!< 0x00001000 */
3575 #define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk
3576 #define DMAMUX_CSR_SOF13_Pos (13U)
3577 #define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos)/*!< 0x00002000 */
3578 #define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk
3579 #define DMAMUX_CSR_SOF14_Pos (14U)
3580 #define DMAMUX_CSR_SOF14_Msk (0x1UL << DMAMUX_CSR_SOF14_Pos)/*!< 0x00004000 */
3581 #define DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14_Msk
3582 #define DMAMUX_CSR_SOF15_Pos (15U)
3583 #define DMAMUX_CSR_SOF15_Msk (0x1UL << DMAMUX_CSR_SOF15_Pos)/*!< 0x00008000 */
3584 #define DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15_Msk
3585
3586 /******************** Bits definition for DMAMUX_CFR register ****************/
3587 #define DMAMUX_CFR_CSOF0_Pos (0U)
3588 #define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos)/*!< 0x00000001 */
3589 #define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk
3590 #define DMAMUX_CFR_CSOF1_Pos (1U)
3591 #define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos)/*!< 0x00000002 */
3592 #define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk
3593 #define DMAMUX_CFR_CSOF2_Pos (2U)
3594 #define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos)/*!< 0x00000004 */
3595 #define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk
3596 #define DMAMUX_CFR_CSOF3_Pos (3U)
3597 #define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos)/*!< 0x00000008 */
3598 #define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk
3599 #define DMAMUX_CFR_CSOF4_Pos (4U)
3600 #define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos)/*!< 0x00000010 */
3601 #define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk
3602 #define DMAMUX_CFR_CSOF5_Pos (5U)
3603 #define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos)/*!< 0x00000020 */
3604 #define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk
3605 #define DMAMUX_CFR_CSOF6_Pos (6U)
3606 #define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos)/*!< 0x00000040 */
3607 #define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk
3608 #define DMAMUX_CFR_CSOF7_Pos (7U)
3609 #define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos)/*!< 0x00000080 */
3610 #define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk
3611 #define DMAMUX_CFR_CSOF8_Pos (8U)
3612 #define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos)/*!< 0x00000100 */
3613 #define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk
3614 #define DMAMUX_CFR_CSOF9_Pos (9U)
3615 #define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos)/*!< 0x00000200 */
3616 #define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk
3617 #define DMAMUX_CFR_CSOF10_Pos (10U)
3618 #define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos)/*!< 0x00000400 */
3619 #define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk
3620 #define DMAMUX_CFR_CSOF11_Pos (11U)
3621 #define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos)/*!< 0x00000800 */
3622 #define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk
3623 #define DMAMUX_CFR_CSOF12_Pos (12U)
3624 #define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos)/*!< 0x00001000 */
3625 #define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk
3626 #define DMAMUX_CFR_CSOF13_Pos (13U)
3627 #define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos)/*!< 0x00002000 */
3628 #define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk
3629 #define DMAMUX_CFR_CSOF14_Pos (14U)
3630 #define DMAMUX_CFR_CSOF14_Msk (0x1UL << DMAMUX_CFR_CSOF14_Pos)/*!< 0x00004000 */
3631 #define DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14_Msk
3632 #define DMAMUX_CFR_CSOF15_Pos (15U)
3633 #define DMAMUX_CFR_CSOF15_Msk (0x1UL << DMAMUX_CFR_CSOF15_Pos)/*!< 0x00008000 */
3634 #define DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15_Msk
3635
3636 /******************** Bits definition for DMAMUX_RGxCR register ************/
3637 #define DMAMUX_RGxCR_SIG_ID_Pos (0U)
3638 #define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x0000001F */
3639 #define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk
3640 #define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000001 */
3641 #define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000002 */
3642 #define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000004 */
3643 #define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000008 */
3644 #define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000010 */
3645
3646 #define DMAMUX_RGxCR_OIE_Pos (8U)
3647 #define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos)/*!< 0x00000100 */
3648 #define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk
3649
3650 #define DMAMUX_RGxCR_GE_Pos (16U)
3651 #define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos)/*!< 0x00010000 */
3652 #define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk
3653
3654 #define DMAMUX_RGxCR_GPOL_Pos (17U)
3655 #define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00060000 */
3656 #define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk
3657 #define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00020000 */
3658 #define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00040000 */
3659
3660 #define DMAMUX_RGxCR_GNBREQ_Pos (19U)
3661 #define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00F80000 */
3662 #define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk
3663 #define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00080000 */
3664 #define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00100000 */
3665 #define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00200000 */
3666 #define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00400000 */
3667 #define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00800000 */
3668
3669 /******************** Bits definition for DMAMUX_RGSR register **************/
3670 #define DMAMUX_RGSR_OF0_Pos (0U)
3671 #define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos)/*!< 0x00000001 */
3672 #define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk
3673 #define DMAMUX_RGSR_OF1_Pos (1U)
3674 #define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos)/*!< 0x00000002 */
3675 #define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk
3676 #define DMAMUX_RGSR_OF2_Pos (2U)
3677 #define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos)/*!< 0x00000004 */
3678 #define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk
3679 #define DMAMUX_RGSR_OF3_Pos (3U)
3680 #define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos)/*!< 0x00000008 */
3681 #define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk
3682
3683 /******************** Bits definition for DMAMUX_RGCFR register ************/
3684 #define DMAMUX_RGCFR_COF0_Pos (0U)
3685 #define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos)/*!< 0x00000001 */
3686 #define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk
3687 #define DMAMUX_RGCFR_COF1_Pos (1U)
3688 #define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos)/*!< 0x00000002 */
3689 #define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk
3690 #define DMAMUX_RGCFR_COF2_Pos (2U)
3691 #define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos)/*!< 0x00000004 */
3692 #define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk
3693 #define DMAMUX_RGCFR_COF3_Pos (3U)
3694 #define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos)/*!< 0x00000008 */
3695 #define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk
3696
3697 /******************** Bits definition for DMAMUX_IPHW_CFGR2 ******************/
3698 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos (0U)
3699 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos)/*!< 0x00000001 */
3700 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk
3701 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos (1U)
3702 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos)/*!< 0x00000002 */
3703 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk
3704 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos (2U)
3705 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos)/*!< 0x00000004 */
3706 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk
3707 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos (3U)
3708 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos)/*!< 0x00000008 */
3709 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk
3710 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos (4U)
3711 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos)/*!< 0x00000010 */
3712 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk
3713 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos (5U)
3714 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos)/*!< 0x00000020 */
3715 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk
3716 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos (6U)
3717 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos)/*!< 0x00000040 */
3718 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk
3719 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos (7U)
3720 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos)/*!< 0x00000080 */
3721 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk
3722
3723 /******************** Bits definition for DMAMUX_IPHW_CFGR1 ******************/
3724 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos (0U)
3725 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos)/*!< 0x00000001 */
3726 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk
3727 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos (1U)
3728 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos)/*!< 0x00000002 */
3729 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk
3730 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos (2U)
3731 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos)/*!< 0x00000004 */
3732 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk
3733 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos (3U)
3734 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos)/*!< 0x00000008 */
3735 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk
3736 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos (4U)
3737 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos)/*!< 0x00000010 */
3738 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk
3739 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos (5U)
3740 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos)/*!< 0x00000020 */
3741 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk
3742 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos (6U)
3743 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos)/*!< 0x00000040 */
3744 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk
3745 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos (7U)
3746 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos)/*!< 0x00000080 */
3747 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk
3748 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos (8U)
3749 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos)/*!< 0x00000100 */
3750 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk
3751 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos (9U)
3752 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos)/*!< 0x00000200 */
3753 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk
3754 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos (10U)
3755 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos)/*!< 0x00000400 */
3756 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk
3757 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos (11U)
3758 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos)/*!< 0x00000800 */
3759 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk
3760 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos (12U)
3761 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos)/*!< 0x00001000 */
3762 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk
3763 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos (13U)
3764 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos)/*!< 0x00002000 */
3765 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk
3766 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos (14U)
3767 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos)/*!< 0x00004000 */
3768 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk
3769 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos (15U)
3770 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos)/*!< 0x00008000 */
3771 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk
3772 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos (16U)
3773 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos)/*!< 0x00010000 */
3774 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk
3775 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos (17U)
3776 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos)/*!< 0x00020000 */
3777 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk
3778 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos (18U)
3779 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos)/*!< 0x00040000 */
3780 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk
3781 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos (19U)
3782 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos)/*!< 0x00080000 */
3783 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk
3784 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos (20U)
3785 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos)/*!< 0x00100000 */
3786 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk
3787 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos (21U)
3788 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos)/*!< 0x00200000 */
3789 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk
3790 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos (22U)
3791 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos)/*!< 0x00400000 */
3792 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk
3793 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos (23U)
3794 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos)/*!< 0x00800000 */
3795 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk
3796 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos (24U)
3797 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos)/*!< 0x01000000 */
3798 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk
3799 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos (25U)
3800 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos)/*!< 0x02000000 */
3801 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk
3802 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos (26U)
3803 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos)/*!< 0x04000000 */
3804 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk
3805 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos (27U)
3806 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos)/*!< 0x08000000 */
3807 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk
3808 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos (28U)
3809 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos)/*!< 0x10000000 */
3810 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk
3811 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos (29U)
3812 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos)/*!< 0x20000000 */
3813 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk
3814 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos (30U)
3815 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos)/*!< 0x40000000 */
3816 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk
3817 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos (31U)
3818 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos)/*!< 0x80000000 */
3819 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk
3820
3821
3822 /******************************************************************************/
3823 /* */
3824 /* External Interrupt/Event Controller */
3825 /* */
3826 /******************************************************************************/
3827 /******************* Bit definition for EXTI_IMR1 register ******************/
3828 #define EXTI_IMR1_IM0_Pos (0U)
3829 #define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
3830 #define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
3831 #define EXTI_IMR1_IM1_Pos (1U)
3832 #define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
3833 #define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
3834 #define EXTI_IMR1_IM2_Pos (2U)
3835 #define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
3836 #define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
3837 #define EXTI_IMR1_IM3_Pos (3U)
3838 #define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
3839 #define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
3840 #define EXTI_IMR1_IM4_Pos (4U)
3841 #define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
3842 #define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
3843 #define EXTI_IMR1_IM5_Pos (5U)
3844 #define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
3845 #define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
3846 #define EXTI_IMR1_IM6_Pos (6U)
3847 #define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
3848 #define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
3849 #define EXTI_IMR1_IM7_Pos (7U)
3850 #define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
3851 #define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
3852 #define EXTI_IMR1_IM8_Pos (8U)
3853 #define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
3854 #define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
3855 #define EXTI_IMR1_IM9_Pos (9U)
3856 #define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
3857 #define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
3858 #define EXTI_IMR1_IM10_Pos (10U)
3859 #define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
3860 #define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
3861 #define EXTI_IMR1_IM11_Pos (11U)
3862 #define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
3863 #define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
3864 #define EXTI_IMR1_IM12_Pos (12U)
3865 #define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
3866 #define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
3867 #define EXTI_IMR1_IM13_Pos (13U)
3868 #define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
3869 #define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
3870 #define EXTI_IMR1_IM14_Pos (14U)
3871 #define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
3872 #define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
3873 #define EXTI_IMR1_IM15_Pos (15U)
3874 #define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
3875 #define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
3876 #define EXTI_IMR1_IM16_Pos (16U)
3877 #define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
3878 #define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
3879 #define EXTI_IMR1_IM17_Pos (17U)
3880 #define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
3881 #define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
3882 #define EXTI_IMR1_IM18_Pos (18U)
3883 #define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
3884 #define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
3885 #define EXTI_IMR1_IM19_Pos (19U)
3886 #define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
3887 #define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
3888 #define EXTI_IMR1_IM20_Pos (20U)
3889 #define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
3890 #define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
3891 #define EXTI_IMR1_IM21_Pos (21U)
3892 #define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
3893 #define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
3894 #define EXTI_IMR1_IM22_Pos (22U)
3895 #define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
3896 #define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
3897 #define EXTI_IMR1_IM23_Pos (23U)
3898 #define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
3899 #define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
3900 #define EXTI_IMR1_IM24_Pos (24U)
3901 #define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
3902 #define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
3903 #define EXTI_IMR1_IM25_Pos (25U)
3904 #define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
3905 #define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
3906 #define EXTI_IMR1_IM26_Pos (26U)
3907 #define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
3908 #define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
3909 #define EXTI_IMR1_IM27_Pos (27U)
3910 #define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
3911 #define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
3912 #define EXTI_IMR1_IM28_Pos (28U)
3913 #define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
3914 #define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
3915 #define EXTI_IMR1_IM29_Pos (29U)
3916 #define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
3917 #define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
3918 #define EXTI_IMR1_IM30_Pos (30U)
3919 #define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
3920 #define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
3921 #define EXTI_IMR1_IM31_Pos (31U)
3922 #define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
3923 #define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
3924 #define EXTI_IMR1_IM_Pos (0U)
3925 #define EXTI_IMR1_IM_Msk (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0xFFFFFFFF */
3926 #define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
3927
3928 /******************* Bit definition for EXTI_EMR1 register ******************/
3929 #define EXTI_EMR1_EM0_Pos (0U)
3930 #define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
3931 #define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
3932 #define EXTI_EMR1_EM1_Pos (1U)
3933 #define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
3934 #define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
3935 #define EXTI_EMR1_EM2_Pos (2U)
3936 #define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
3937 #define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
3938 #define EXTI_EMR1_EM3_Pos (3U)
3939 #define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
3940 #define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
3941 #define EXTI_EMR1_EM4_Pos (4U)
3942 #define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
3943 #define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
3944 #define EXTI_EMR1_EM5_Pos (5U)
3945 #define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
3946 #define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
3947 #define EXTI_EMR1_EM6_Pos (6U)
3948 #define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
3949 #define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
3950 #define EXTI_EMR1_EM7_Pos (7U)
3951 #define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
3952 #define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
3953 #define EXTI_EMR1_EM8_Pos (8U)
3954 #define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
3955 #define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
3956 #define EXTI_EMR1_EM9_Pos (9U)
3957 #define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
3958 #define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
3959 #define EXTI_EMR1_EM10_Pos (10U)
3960 #define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
3961 #define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
3962 #define EXTI_EMR1_EM11_Pos (11U)
3963 #define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
3964 #define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
3965 #define EXTI_EMR1_EM12_Pos (12U)
3966 #define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
3967 #define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
3968 #define EXTI_EMR1_EM13_Pos (13U)
3969 #define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
3970 #define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
3971 #define EXTI_EMR1_EM14_Pos (14U)
3972 #define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
3973 #define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
3974 #define EXTI_EMR1_EM15_Pos (15U)
3975 #define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
3976 #define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
3977 #define EXTI_EMR1_EM16_Pos (16U)
3978 #define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
3979 #define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
3980 #define EXTI_EMR1_EM17_Pos (17U)
3981 #define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
3982 #define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
3983 #define EXTI_EMR1_EM18_Pos (18U)
3984 #define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
3985 #define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
3986 #define EXTI_EMR1_EM19_Pos (19U)
3987 #define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
3988 #define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
3989 #define EXTI_EMR1_EM20_Pos (20U)
3990 #define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
3991 #define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
3992 #define EXTI_EMR1_EM21_Pos (21U)
3993 #define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
3994 #define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
3995 #define EXTI_EMR1_EM22_Pos (22U)
3996 #define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
3997 #define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
3998 #define EXTI_EMR1_EM23_Pos (23U)
3999 #define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
4000 #define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
4001 #define EXTI_EMR1_EM24_Pos (24U)
4002 #define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
4003 #define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
4004 #define EXTI_EMR1_EM25_Pos (25U)
4005 #define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
4006 #define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
4007 #define EXTI_EMR1_EM26_Pos (26U)
4008 #define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
4009 #define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
4010 #define EXTI_EMR1_EM27_Pos (27U)
4011 #define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
4012 #define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
4013 #define EXTI_EMR1_EM28_Pos (28U)
4014 #define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
4015 #define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
4016 #define EXTI_EMR1_EM29_Pos (29U)
4017 #define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
4018 #define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
4019 #define EXTI_EMR1_EM30_Pos (30U)
4020 #define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
4021 #define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
4022 #define EXTI_EMR1_EM31_Pos (31U)
4023 #define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
4024 #define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
4025
4026 /****************** Bit definition for EXTI_RTSR1 register ******************/
4027 #define EXTI_RTSR1_RT0_Pos (0U)
4028 #define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
4029 #define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
4030 #define EXTI_RTSR1_RT1_Pos (1U)
4031 #define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
4032 #define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
4033 #define EXTI_RTSR1_RT2_Pos (2U)
4034 #define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
4035 #define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
4036 #define EXTI_RTSR1_RT3_Pos (3U)
4037 #define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
4038 #define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
4039 #define EXTI_RTSR1_RT4_Pos (4U)
4040 #define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
4041 #define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
4042 #define EXTI_RTSR1_RT5_Pos (5U)
4043 #define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
4044 #define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
4045 #define EXTI_RTSR1_RT6_Pos (6U)
4046 #define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
4047 #define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
4048 #define EXTI_RTSR1_RT7_Pos (7U)
4049 #define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
4050 #define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
4051 #define EXTI_RTSR1_RT8_Pos (8U)
4052 #define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
4053 #define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
4054 #define EXTI_RTSR1_RT9_Pos (9U)
4055 #define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
4056 #define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
4057 #define EXTI_RTSR1_RT10_Pos (10U)
4058 #define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
4059 #define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
4060 #define EXTI_RTSR1_RT11_Pos (11U)
4061 #define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
4062 #define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
4063 #define EXTI_RTSR1_RT12_Pos (12U)
4064 #define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
4065 #define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
4066 #define EXTI_RTSR1_RT13_Pos (13U)
4067 #define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
4068 #define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
4069 #define EXTI_RTSR1_RT14_Pos (14U)
4070 #define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
4071 #define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
4072 #define EXTI_RTSR1_RT15_Pos (15U)
4073 #define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
4074 #define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
4075 #define EXTI_RTSR1_RT16_Pos (16U)
4076 #define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */
4077 #define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
4078 #define EXTI_RTSR1_RT17_Pos (17U)
4079 #define EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos) /*!< 0x00020000 */
4080 #define EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
4081 #define EXTI_RTSR1_RT19_Pos (19U)
4082 #define EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */
4083 #define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
4084 #define EXTI_RTSR1_RT20_Pos (20U)
4085 #define EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */
4086 #define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
4087 #define EXTI_RTSR1_RT21_Pos (21U)
4088 #define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */
4089 #define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
4090 #define EXTI_RTSR1_RT22_Pos (22U)
4091 #define EXTI_RTSR1_RT22_Msk (0x1UL << EXTI_RTSR1_RT22_Pos) /*!< 0x00400000 */
4092 #define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
4093 #define EXTI_RTSR1_RT29_Pos (29U)
4094 #define EXTI_RTSR1_RT29_Msk (0x1UL << EXTI_RTSR1_RT29_Pos) /*!< 0x20000000 */
4095 #define EXTI_RTSR1_RT29 EXTI_RTSR1_RT29_Msk /*!< Rising trigger event configuration bit of line 29 */
4096 #define EXTI_RTSR1_RT30_Pos (30U)
4097 #define EXTI_RTSR1_RT30_Msk (0x1UL << EXTI_RTSR1_RT30_Pos) /*!< 0x40000000 */
4098 #define EXTI_RTSR1_RT30 EXTI_RTSR1_RT30_Msk /*!< Rising trigger event configuration bit of line 30 */
4099 #define EXTI_RTSR1_RT31_Pos (31U)
4100 #define EXTI_RTSR1_RT31_Msk (0x1UL << EXTI_RTSR1_RT31_Pos) /*!< 0x80000000 */
4101 #define EXTI_RTSR1_RT31 EXTI_RTSR1_RT31_Msk /*!< Rising trigger event configuration bit of line 31 */
4102
4103 /****************** Bit definition for EXTI_FTSR1 register ******************/
4104 #define EXTI_FTSR1_FT0_Pos (0U)
4105 #define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
4106 #define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
4107 #define EXTI_FTSR1_FT1_Pos (1U)
4108 #define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
4109 #define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
4110 #define EXTI_FTSR1_FT2_Pos (2U)
4111 #define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
4112 #define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
4113 #define EXTI_FTSR1_FT3_Pos (3U)
4114 #define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
4115 #define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
4116 #define EXTI_FTSR1_FT4_Pos (4U)
4117 #define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
4118 #define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
4119 #define EXTI_FTSR1_FT5_Pos (5U)
4120 #define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
4121 #define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
4122 #define EXTI_FTSR1_FT6_Pos (6U)
4123 #define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
4124 #define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
4125 #define EXTI_FTSR1_FT7_Pos (7U)
4126 #define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
4127 #define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
4128 #define EXTI_FTSR1_FT8_Pos (8U)
4129 #define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
4130 #define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
4131 #define EXTI_FTSR1_FT9_Pos (9U)
4132 #define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
4133 #define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
4134 #define EXTI_FTSR1_FT10_Pos (10U)
4135 #define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
4136 #define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
4137 #define EXTI_FTSR1_FT11_Pos (11U)
4138 #define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
4139 #define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
4140 #define EXTI_FTSR1_FT12_Pos (12U)
4141 #define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
4142 #define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
4143 #define EXTI_FTSR1_FT13_Pos (13U)
4144 #define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
4145 #define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
4146 #define EXTI_FTSR1_FT14_Pos (14U)
4147 #define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
4148 #define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
4149 #define EXTI_FTSR1_FT15_Pos (15U)
4150 #define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
4151 #define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
4152 #define EXTI_FTSR1_FT16_Pos (16U)
4153 #define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */
4154 #define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
4155 #define EXTI_FTSR1_FT17_Pos (17U)
4156 #define EXTI_FTSR1_FT17_Msk (0x1UL << EXTI_FTSR1_FT17_Pos) /*!< 0x00020000 */
4157 #define EXTI_FTSR1_FT17 EXTI_FTSR1_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
4158 #define EXTI_FTSR1_FT19_Pos (19U)
4159 #define EXTI_FTSR1_FT19_Msk (0x1UL << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */
4160 #define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
4161 #define EXTI_FTSR1_FT20_Pos (20U)
4162 #define EXTI_FTSR1_FT20_Msk (0x1UL << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */
4163 #define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
4164 #define EXTI_FTSR1_FT21_Pos (21U)
4165 #define EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */
4166 #define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
4167 #define EXTI_FTSR1_FT22_Pos (22U)
4168 #define EXTI_FTSR1_FT22_Msk (0x1UL << EXTI_FTSR1_FT22_Pos) /*!< 0x00400000 */
4169 #define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
4170 #define EXTI_FTSR1_FT29_Pos (29U)
4171 #define EXTI_FTSR1_FT29_Msk (0x1UL << EXTI_FTSR1_FT29_Pos) /*!< 0x20000000 */
4172 #define EXTI_FTSR1_FT29 EXTI_FTSR1_FT29_Msk /*!< Falling trigger event configuration bit of line 29 */
4173 #define EXTI_FTSR1_FT30_Pos (30U)
4174 #define EXTI_FTSR1_FT30_Msk (0x1UL << EXTI_FTSR1_FT30_Pos) /*!< 0x40000000 */
4175 #define EXTI_FTSR1_FT30 EXTI_FTSR1_FT30_Msk /*!< Falling trigger event configuration bit of line 30 */
4176 #define EXTI_FTSR1_FT31_Pos (31U)
4177 #define EXTI_FTSR1_FT31_Msk (0x1UL << EXTI_FTSR1_FT31_Pos) /*!< 0x80000000 */
4178 #define EXTI_FTSR1_FT31 EXTI_FTSR1_FT31_Msk /*!< Falling trigger event configuration bit of line 31 */
4179
4180 /****************** Bit definition for EXTI_SWIER1 register *****************/
4181 #define EXTI_SWIER1_SWI0_Pos (0U)
4182 #define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
4183 #define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
4184 #define EXTI_SWIER1_SWI1_Pos (1U)
4185 #define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
4186 #define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
4187 #define EXTI_SWIER1_SWI2_Pos (2U)
4188 #define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
4189 #define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
4190 #define EXTI_SWIER1_SWI3_Pos (3U)
4191 #define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
4192 #define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
4193 #define EXTI_SWIER1_SWI4_Pos (4U)
4194 #define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
4195 #define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
4196 #define EXTI_SWIER1_SWI5_Pos (5U)
4197 #define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
4198 #define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
4199 #define EXTI_SWIER1_SWI6_Pos (6U)
4200 #define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
4201 #define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
4202 #define EXTI_SWIER1_SWI7_Pos (7U)
4203 #define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
4204 #define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
4205 #define EXTI_SWIER1_SWI8_Pos (8U)
4206 #define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
4207 #define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
4208 #define EXTI_SWIER1_SWI9_Pos (9U)
4209 #define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
4210 #define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
4211 #define EXTI_SWIER1_SWI10_Pos (10U)
4212 #define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
4213 #define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
4214 #define EXTI_SWIER1_SWI11_Pos (11U)
4215 #define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
4216 #define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
4217 #define EXTI_SWIER1_SWI12_Pos (12U)
4218 #define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
4219 #define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
4220 #define EXTI_SWIER1_SWI13_Pos (13U)
4221 #define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
4222 #define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
4223 #define EXTI_SWIER1_SWI14_Pos (14U)
4224 #define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
4225 #define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
4226 #define EXTI_SWIER1_SWI15_Pos (15U)
4227 #define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
4228 #define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
4229 #define EXTI_SWIER1_SWI16_Pos (16U)
4230 #define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */
4231 #define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */
4232 #define EXTI_SWIER1_SWI17_Pos (17U)
4233 #define EXTI_SWIER1_SWI17_Msk (0x1UL << EXTI_SWIER1_SWI17_Pos) /*!< 0x00020000 */
4234 #define EXTI_SWIER1_SWI17 EXTI_SWIER1_SWI17_Msk /*!< Software Interrupt on line 17 */
4235 #define EXTI_SWIER1_SWI19_Pos (19U)
4236 #define EXTI_SWIER1_SWI19_Msk (0x1UL << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */
4237 #define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */
4238 #define EXTI_SWIER1_SWI20_Pos (20U)
4239 #define EXTI_SWIER1_SWI20_Msk (0x1UL << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */
4240 #define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */
4241 #define EXTI_SWIER1_SWI21_Pos (21U)
4242 #define EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */
4243 #define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */
4244 #define EXTI_SWIER1_SWI22_Pos (22U)
4245 #define EXTI_SWIER1_SWI22_Msk (0x1UL << EXTI_SWIER1_SWI22_Pos) /*!< 0x00400000 */
4246 #define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk /*!< Software Interrupt on line 22 */
4247 #define EXTI_SWIER1_SWI29_Pos (29U)
4248 #define EXTI_SWIER1_SWI29_Msk (0x1UL << EXTI_SWIER1_SWI29_Pos) /*!< 0x20000000 */
4249 #define EXTI_SWIER1_SWI29 EXTI_SWIER1_SWI29_Msk /*!< Software Interrupt on line 29 */
4250 #define EXTI_SWIER1_SWI30_Pos (30U)
4251 #define EXTI_SWIER1_SWI30_Msk (0x1UL << EXTI_SWIER1_SWI30_Pos) /*!< 0x40000000 */
4252 #define EXTI_SWIER1_SWI30 EXTI_SWIER1_SWI30_Msk /*!< Software Interrupt on line 30 */
4253 #define EXTI_SWIER1_SWI31_Pos (31U)
4254 #define EXTI_SWIER1_SWI31_Msk (0x1UL << EXTI_SWIER1_SWI31_Pos) /*!< 0x80000000 */
4255 #define EXTI_SWIER1_SWI31 EXTI_SWIER1_SWI31_Msk /*!< Software Interrupt on line 31 */
4256
4257 /******************* Bit definition for EXTI_PR1 register *******************/
4258 #define EXTI_PR1_PIF0_Pos (0U)
4259 #define EXTI_PR1_PIF0_Msk (0x1UL << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */
4260 #define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */
4261 #define EXTI_PR1_PIF1_Pos (1U)
4262 #define EXTI_PR1_PIF1_Msk (0x1UL << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */
4263 #define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */
4264 #define EXTI_PR1_PIF2_Pos (2U)
4265 #define EXTI_PR1_PIF2_Msk (0x1UL << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */
4266 #define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */
4267 #define EXTI_PR1_PIF3_Pos (3U)
4268 #define EXTI_PR1_PIF3_Msk (0x1UL << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */
4269 #define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */
4270 #define EXTI_PR1_PIF4_Pos (4U)
4271 #define EXTI_PR1_PIF4_Msk (0x1UL << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */
4272 #define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */
4273 #define EXTI_PR1_PIF5_Pos (5U)
4274 #define EXTI_PR1_PIF5_Msk (0x1UL << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */
4275 #define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */
4276 #define EXTI_PR1_PIF6_Pos (6U)
4277 #define EXTI_PR1_PIF6_Msk (0x1UL << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */
4278 #define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */
4279 #define EXTI_PR1_PIF7_Pos (7U)
4280 #define EXTI_PR1_PIF7_Msk (0x1UL << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */
4281 #define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */
4282 #define EXTI_PR1_PIF8_Pos (8U)
4283 #define EXTI_PR1_PIF8_Msk (0x1UL << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */
4284 #define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */
4285 #define EXTI_PR1_PIF9_Pos (9U)
4286 #define EXTI_PR1_PIF9_Msk (0x1UL << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */
4287 #define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */
4288 #define EXTI_PR1_PIF10_Pos (10U)
4289 #define EXTI_PR1_PIF10_Msk (0x1UL << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */
4290 #define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */
4291 #define EXTI_PR1_PIF11_Pos (11U)
4292 #define EXTI_PR1_PIF11_Msk (0x1UL << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */
4293 #define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */
4294 #define EXTI_PR1_PIF12_Pos (12U)
4295 #define EXTI_PR1_PIF12_Msk (0x1UL << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */
4296 #define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */
4297 #define EXTI_PR1_PIF13_Pos (13U)
4298 #define EXTI_PR1_PIF13_Msk (0x1UL << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */
4299 #define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */
4300 #define EXTI_PR1_PIF14_Pos (14U)
4301 #define EXTI_PR1_PIF14_Msk (0x1UL << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */
4302 #define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */
4303 #define EXTI_PR1_PIF15_Pos (15U)
4304 #define EXTI_PR1_PIF15_Msk (0x1UL << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */
4305 #define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */
4306 #define EXTI_PR1_PIF16_Pos (16U)
4307 #define EXTI_PR1_PIF16_Msk (0x1UL << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */
4308 #define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */
4309 #define EXTI_PR1_PIF17_Pos (17U)
4310 #define EXTI_PR1_PIF17_Msk (0x1UL << EXTI_PR1_PIF17_Pos) /*!< 0x00020000 */
4311 #define EXTI_PR1_PIF17 EXTI_PR1_PIF17_Msk /*!< Pending bit for line 17 */
4312 #define EXTI_PR1_PIF19_Pos (19U)
4313 #define EXTI_PR1_PIF19_Msk (0x1UL << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */
4314 #define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */
4315 #define EXTI_PR1_PIF20_Pos (20U)
4316 #define EXTI_PR1_PIF20_Msk (0x1UL << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */
4317 #define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */
4318 #define EXTI_PR1_PIF21_Pos (21U)
4319 #define EXTI_PR1_PIF21_Msk (0x1UL << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */
4320 #define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */
4321 #define EXTI_PR1_PIF22_Pos (22U)
4322 #define EXTI_PR1_PIF22_Msk (0x1UL << EXTI_PR1_PIF22_Pos) /*!< 0x00400000 */
4323 #define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk /*!< Pending bit for line 22 */
4324 #define EXTI_PR1_PIF29_Pos (29U)
4325 #define EXTI_PR1_PIF29_Msk (0x1UL << EXTI_PR1_PIF29_Pos) /*!< 0x20000000 */
4326 #define EXTI_PR1_PIF29 EXTI_PR1_PIF29_Msk /*!< Pending bit for line 29 */
4327 #define EXTI_PR1_PIF30_Pos (30U)
4328 #define EXTI_PR1_PIF30_Msk (0x1UL << EXTI_PR1_PIF30_Pos) /*!< 0x40000000 */
4329 #define EXTI_PR1_PIF30 EXTI_PR1_PIF30_Msk /*!< Pending bit for line 30 */
4330 #define EXTI_PR1_PIF31_Pos (31U)
4331 #define EXTI_PR1_PIF31_Msk (0x1UL << EXTI_PR1_PIF31_Pos) /*!< 0x80000000 */
4332 #define EXTI_PR1_PIF31 EXTI_PR1_PIF31_Msk /*!< Pending bit for line 31 */
4333
4334 /******************* Bit definition for EXTI_IMR2 register ******************/
4335 #define EXTI_IMR2_IM32_Pos (0U)
4336 #define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
4337 #define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */
4338 #define EXTI_IMR2_IM33_Pos (1U)
4339 #define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
4340 #define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
4341 #define EXTI_IMR2_IM34_Pos (2U)
4342 #define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
4343 #define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
4344 #define EXTI_IMR2_IM35_Pos (3U)
4345 #define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
4346 #define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
4347 #define EXTI_IMR2_IM36_Pos (4U)
4348 #define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
4349 #define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
4350 #define EXTI_IMR2_IM37_Pos (5U)
4351 #define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
4352 #define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
4353 #define EXTI_IMR2_IM38_Pos (6U)
4354 #define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
4355 #define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
4356 #define EXTI_IMR2_IM39_Pos (7U)
4357 #define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
4358 #define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
4359 #define EXTI_IMR2_IM40_Pos (8U)
4360 #define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
4361 #define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
4362 #define EXTI_IMR2_IM41_Pos (9U)
4363 #define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos) /*!< 0x00000200 */
4364 #define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk /*!< Interrupt Mask on line 41 */
4365 #define EXTI_IMR2_IM42_Pos (10U)
4366 #define EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos) /*!< 0x00000400 */
4367 #define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk /*!< Interrupt Mask on line 42 */
4368 #define EXTI_IMR2_IM_Pos (0U)
4369 #define EXTI_IMR2_IM_Msk (0x7FFUL << EXTI_IMR2_IM_Pos) /*!< 0x000007FF */
4370 #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
4371
4372 /******************* Bit definition for EXTI_EMR2 register ******************/
4373 #define EXTI_EMR2_EM32_Pos (0U)
4374 #define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */
4375 #define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32 */
4376 #define EXTI_EMR2_EM33_Pos (1U)
4377 #define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
4378 #define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
4379 #define EXTI_EMR2_EM34_Pos (2U)
4380 #define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
4381 #define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */
4382 #define EXTI_EMR2_EM35_Pos (3U)
4383 #define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
4384 #define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
4385 #define EXTI_EMR2_EM36_Pos (4U)
4386 #define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
4387 #define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
4388 #define EXTI_EMR2_EM37_Pos (5U)
4389 #define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
4390 #define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
4391 #define EXTI_EMR2_EM38_Pos (6U)
4392 #define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
4393 #define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
4394 #define EXTI_EMR2_EM39_Pos (7U)
4395 #define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
4396 #define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
4397 #define EXTI_EMR2_EM40_Pos (8U)
4398 #define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
4399 #define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40 */
4400 #define EXTI_EMR2_EM41_Pos (9U)
4401 #define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos) /*!< 0x00000200 */
4402 #define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk /*!< Event Mask on line 41 */
4403 #define EXTI_EMR2_EM42_Pos (10U)
4404 #define EXTI_EMR2_EM42_Msk (0x1UL << EXTI_EMR2_EM42_Pos) /*!< 0x00000400 */
4405 #define EXTI_EMR2_EM42 EXTI_EMR2_EM42_Msk /*!< Event Mask on line 42 */
4406 #define EXTI_EMR2_EM_Pos (0U)
4407 #define EXTI_EMR2_EM_Msk (0x7FFUL << EXTI_EMR2_EM_Pos) /*!< 0x000007FF */
4408 #define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
4409
4410 /****************** Bit definition for EXTI_RTSR2 register ******************/
4411 #define EXTI_RTSR2_RT32_Pos (0U)
4412 #define EXTI_RTSR2_RT32_Msk (0x1UL << EXTI_RTSR2_RT32_Pos) /*!< 0x00000001 */
4413 #define EXTI_RTSR2_RT32 EXTI_RTSR2_RT32_Msk /*!< Rising trigger event configuration bit of line 32 */
4414 #define EXTI_RTSR2_RT33_Pos (1U)
4415 #define EXTI_RTSR2_RT33_Msk (0x1UL << EXTI_RTSR2_RT33_Pos) /*!< 0x00000002 */
4416 #define EXTI_RTSR2_RT33 EXTI_RTSR2_RT33_Msk /*!< Rising trigger event configuration bit of line 33 */
4417 #define EXTI_RTSR2_RT38_Pos (6U)
4418 #define EXTI_RTSR2_RT38_Msk (0x1UL << EXTI_RTSR2_RT38_Pos) /*!< 0x00000040 */
4419 #define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger event configuration bit of line 38 */
4420 #define EXTI_RTSR2_RT39_Pos (7U)
4421 #define EXTI_RTSR2_RT39_Msk (0x1UL << EXTI_RTSR2_RT39_Pos) /*!< 0x00000080 */
4422 #define EXTI_RTSR2_RT39 EXTI_RTSR2_RT39_Msk /*!< Rising trigger event configuration bit of line 39 */
4423 #define EXTI_RTSR2_RT40_Pos (8U)
4424 #define EXTI_RTSR2_RT40_Msk (0x1UL << EXTI_RTSR2_RT40_Pos) /*!< 0x00000100 */
4425 #define EXTI_RTSR2_RT40 EXTI_RTSR2_RT40_Msk /*!< Rising trigger event configuration bit of line 40 */
4426 #define EXTI_RTSR2_RT41_Pos (9U)
4427 #define EXTI_RTSR2_RT41_Msk (0x1UL << EXTI_RTSR2_RT41_Pos) /*!< 0x00000200 */
4428 #define EXTI_RTSR2_RT41 EXTI_RTSR2_RT41_Msk /*!< Rising trigger event configuration bit of line 41 */
4429
4430 /****************** Bit definition for EXTI_FTSR2 register ******************/
4431 #define EXTI_FTSR2_FT32_Pos (0U)
4432 #define EXTI_FTSR2_FT32_Msk (0x1UL << EXTI_FTSR2_FT32_Pos) /*!< 0x00000001 */
4433 #define EXTI_FTSR2_FT32 EXTI_FTSR2_FT32_Msk /*!< Falling trigger event configuration bit of line 32 */
4434 #define EXTI_FTSR2_FT33_Pos (1U)
4435 #define EXTI_FTSR2_FT33_Msk (0x1UL << EXTI_FTSR2_FT33_Pos) /*!< 0x00000002 */
4436 #define EXTI_FTSR2_FT33 EXTI_FTSR2_FT33_Msk /*!< Falling trigger event configuration bit of line 33 */
4437 #define EXTI_FTSR2_FT38_Pos (6U)
4438 #define EXTI_FTSR2_FT38_Msk (0x1UL << EXTI_FTSR2_FT38_Pos) /*!< 0x00000040 */
4439 #define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger event configuration bit of line 37 */
4440 #define EXTI_FTSR2_FT39_Pos (7U)
4441 #define EXTI_FTSR2_FT39_Msk (0x1UL << EXTI_FTSR2_FT39_Pos) /*!< 0x00000080 */
4442 #define EXTI_FTSR2_FT39 EXTI_FTSR2_FT39_Msk /*!< Falling trigger event configuration bit of line 39 */
4443 #define EXTI_FTSR2_FT40_Pos (8U)
4444 #define EXTI_FTSR2_FT40_Msk (0x1UL << EXTI_FTSR2_FT40_Pos) /*!< 0x00000100 */
4445 #define EXTI_FTSR2_FT40 EXTI_FTSR2_FT40_Msk /*!< Falling trigger event configuration bit of line 40 */
4446 #define EXTI_FTSR2_FT41_Pos (9U)
4447 #define EXTI_FTSR2_FT41_Msk (0x1UL << EXTI_FTSR2_FT41_Pos) /*!< 0x00000200 */
4448 #define EXTI_FTSR2_FT41 EXTI_FTSR2_FT41_Msk /*!< Falling trigger event configuration bit of line 41 */
4449
4450 /****************** Bit definition for EXTI_SWIER2 register *****************/
4451 #define EXTI_SWIER2_SWI32_Pos (0U)
4452 #define EXTI_SWIER2_SWI32_Msk (0x1UL << EXTI_SWIER2_SWI32_Pos) /*!< 0x00000001 */
4453 #define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWI32_Msk /*!< Software Interrupt on line 32 */
4454 #define EXTI_SWIER2_SWI33_Pos (1U)
4455 #define EXTI_SWIER2_SWI33_Msk (0x1UL << EXTI_SWIER2_SWI33_Pos) /*!< 0x00000002 */
4456 #define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWI33_Msk /*!< Software Interrupt on line 33 */
4457 #define EXTI_SWIER2_SWI38_Pos (6U)
4458 #define EXTI_SWIER2_SWI38_Msk (0x1UL << EXTI_SWIER2_SWI38_Pos) /*!< 0x00000040 */
4459 #define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */
4460 #define EXTI_SWIER2_SWI39_Pos (7U)
4461 #define EXTI_SWIER2_SWI39_Msk (0x1UL << EXTI_SWIER2_SWI39_Pos) /*!< 0x00000080 */
4462 #define EXTI_SWIER2_SWI39 EXTI_SWIER2_SWI39_Msk /*!< Software Interrupt on line 39 */
4463 #define EXTI_SWIER2_SWI40_Pos (8U)
4464 #define EXTI_SWIER2_SWI40_Msk (0x1UL << EXTI_SWIER2_SWI40_Pos) /*!< 0x00000100 */
4465 #define EXTI_SWIER2_SWI40 EXTI_SWIER2_SWI40_Msk /*!< Software Interrupt on line 40 */
4466 #define EXTI_SWIER2_SWI41_Pos (9U)
4467 #define EXTI_SWIER2_SWI41_Msk (0x1UL << EXTI_SWIER2_SWI41_Pos) /*!< 0x00000200 */
4468 #define EXTI_SWIER2_SWI41 EXTI_SWIER2_SWI41_Msk /*!< Software Interrupt on line 41 */
4469
4470 /******************* Bit definition for EXTI_PR2 register *******************/
4471 #define EXTI_PR2_PIF32_Pos (0U)
4472 #define EXTI_PR2_PIF32_Msk (0x1UL << EXTI_PR2_PIF32_Pos) /*!< 0x00000001 */
4473 #define EXTI_PR2_PIF32 EXTI_PR2_PIF32_Msk /*!< Pending bit for line 32 */
4474 #define EXTI_PR2_PIF33_Pos (1U)
4475 #define EXTI_PR2_PIF33_Msk (0x1UL << EXTI_PR2_PIF33_Pos) /*!< 0x00000002 */
4476 #define EXTI_PR2_PIF33 EXTI_PR2_PIF33_Msk /*!< Pending bit for line 33 */
4477 #define EXTI_PR2_PIF38_Pos (6U)
4478 #define EXTI_PR2_PIF38_Msk (0x1UL << EXTI_PR2_PIF38_Pos) /*!< 0x00000040 */
4479 #define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk /*!< Pending bit for line 38 */
4480 #define EXTI_PR2_PIF39_Pos (7U)
4481 #define EXTI_PR2_PIF39_Msk (0x1UL << EXTI_PR2_PIF39_Pos) /*!< 0x00000080 */
4482 #define EXTI_PR2_PIF39 EXTI_PR2_PIF39_Msk /*!< Pending bit for line 39 */
4483 #define EXTI_PR2_PIF40_Pos (8U)
4484 #define EXTI_PR2_PIF40_Msk (0x1UL << EXTI_PR2_PIF40_Pos) /*!< 0x00000100 */
4485 #define EXTI_PR2_PIF40 EXTI_PR2_PIF40_Msk /*!< Pending bit for line 40 */
4486 #define EXTI_PR2_PIF41_Pos (9U)
4487 #define EXTI_PR2_PIF41_Msk (0x1UL << EXTI_PR2_PIF41_Pos) /*!< 0x00000200 */
4488 #define EXTI_PR2_PIF41 EXTI_PR2_PIF41_Msk /*!< Pending bit for line 41 */
4489
4490 /******************************************************************************/
4491 /* */
4492 /* Flexible Datarate Controller Area Network */
4493 /* */
4494 /******************************************************************************/
4495 /*!<FDCAN control and status registers */
4496 /***************** Bit definition for FDCAN_CREL register *******************/
4497 #define FDCAN_CREL_DAY_Pos (0U)
4498 #define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos) /*!< 0x000000FF */
4499 #define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk /*!<Timestamp Day */
4500 #define FDCAN_CREL_MON_Pos (8U)
4501 #define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos) /*!< 0x0000FF00 */
4502 #define FDCAN_CREL_MON FDCAN_CREL_MON_Msk /*!<Timestamp Month */
4503 #define FDCAN_CREL_YEAR_Pos (16U)
4504 #define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos) /*!< 0x000F0000 */
4505 #define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk /*!<Timestamp Year */
4506 #define FDCAN_CREL_SUBSTEP_Pos (20U)
4507 #define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
4508 #define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
4509 #define FDCAN_CREL_STEP_Pos (24U)
4510 #define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos) /*!< 0x0F000000 */
4511 #define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk /*!<Step of Core release */
4512 #define FDCAN_CREL_REL_Pos (28U)
4513 #define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos) /*!< 0xF0000000 */
4514 #define FDCAN_CREL_REL FDCAN_CREL_REL_Msk /*!<Core release */
4515
4516 /***************** Bit definition for FDCAN_ENDN register *******************/
4517 #define FDCAN_ENDN_ETV_Pos (0U)
4518 #define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
4519 #define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
4520
4521 /***************** Bit definition for FDCAN_DBTP register *******************/
4522 #define FDCAN_DBTP_DSJW_Pos (0U)
4523 #define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos) /*!< 0x0000000F */
4524 #define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk /*!<Synchronization Jump Width */
4525 #define FDCAN_DBTP_DTSEG2_Pos (4U)
4526 #define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos) /*!< 0x000000F0 */
4527 #define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk /*!<Data time segment after sample point */
4528 #define FDCAN_DBTP_DTSEG1_Pos (8U)
4529 #define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos) /*!< 0x00001F00 */
4530 #define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk /*!<Data time segment before sample point */
4531 #define FDCAN_DBTP_DBRP_Pos (16U)
4532 #define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos) /*!< 0x001F0000 */
4533 #define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk /*!<Data BIt Rate Prescaler */
4534 #define FDCAN_DBTP_TDC_Pos (23U)
4535 #define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos) /*!< 0x00800000 */
4536 #define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk /*!<Transceiver Delay Compensation */
4537
4538 /***************** Bit definition for FDCAN_TEST register *******************/
4539 #define FDCAN_TEST_LBCK_Pos (4U)
4540 #define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos) /*!< 0x00000010 */
4541 #define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk /*!<Loop Back mode */
4542 #define FDCAN_TEST_TX_Pos (5U)
4543 #define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos) /*!< 0x00000060 */
4544 #define FDCAN_TEST_TX FDCAN_TEST_TX_Msk /*!<Control of Transmit Pin */
4545 #define FDCAN_TEST_RX_Pos (7U)
4546 #define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos) /*!< 0x00000080 */
4547 #define FDCAN_TEST_RX FDCAN_TEST_RX_Msk /*!<Receive Pin */
4548
4549 /***************** Bit definition for FDCAN_RWD register ********************/
4550 #define FDCAN_RWD_WDC_Pos (0U)
4551 #define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos) /*!< 0x000000FF */
4552 #define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk /*!<Watchdog configuration */
4553 #define FDCAN_RWD_WDV_Pos (8U)
4554 #define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos) /*!< 0x0000FF00 */
4555 #define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk /*!<Watchdog value */
4556
4557 /***************** Bit definition for FDCAN_CCCR register ********************/
4558 #define FDCAN_CCCR_INIT_Pos (0U)
4559 #define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos) /*!< 0x00000001 */
4560 #define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk /*!<Initialization */
4561 #define FDCAN_CCCR_CCE_Pos (1U)
4562 #define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos) /*!< 0x00000002 */
4563 #define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk /*!<Configuration Change Enable */
4564 #define FDCAN_CCCR_ASM_Pos (2U)
4565 #define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos) /*!< 0x00000004 */
4566 #define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk /*!<ASM Restricted Operation Mode */
4567 #define FDCAN_CCCR_CSA_Pos (3U)
4568 #define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos) /*!< 0x00000008 */
4569 #define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk /*!<Clock Stop Acknowledge */
4570 #define FDCAN_CCCR_CSR_Pos (4U)
4571 #define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos) /*!< 0x00000010 */
4572 #define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk /*!<Clock Stop Request */
4573 #define FDCAN_CCCR_MON_Pos (5U)
4574 #define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos) /*!< 0x00000020 */
4575 #define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk /*!<Bus Monitoring Mode */
4576 #define FDCAN_CCCR_DAR_Pos (6U)
4577 #define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos) /*!< 0x00000040 */
4578 #define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk /*!<Disable Automatic Retransmission */
4579 #define FDCAN_CCCR_TEST_Pos (7U)
4580 #define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos) /*!< 0x00000080 */
4581 #define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk /*!<Test Mode Enable */
4582 #define FDCAN_CCCR_FDOE_Pos (8U)
4583 #define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos) /*!< 0x00000100 */
4584 #define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk /*!<FD Operation Enable */
4585 #define FDCAN_CCCR_BRSE_Pos (9U)
4586 #define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos) /*!< 0x00000200 */
4587 #define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk /*!<FDCAN Bit Rate Switching */
4588 #define FDCAN_CCCR_PXHD_Pos (12U)
4589 #define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos) /*!< 0x00001000 */
4590 #define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk /*!<Protocol Exception Handling Disable */
4591 #define FDCAN_CCCR_EFBI_Pos (13U)
4592 #define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos) /*!< 0x00002000 */
4593 #define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk /*!<Edge Filtering during Bus Integration */
4594 #define FDCAN_CCCR_TXP_Pos (14U)
4595 #define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos) /*!< 0x00004000 */
4596 #define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk /*!<Two CAN bit times Pause */
4597 #define FDCAN_CCCR_NISO_Pos (15U)
4598 #define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos) /*!< 0x00008000 */
4599 #define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk /*!<Non ISO Operation */
4600
4601 /***************** Bit definition for FDCAN_NBTP register ********************/
4602 #define FDCAN_NBTP_NTSEG2_Pos (0U)
4603 #define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos) /*!< 0x0000007F */
4604 #define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk /*!<Nominal Time segment after sample point */
4605 #define FDCAN_NBTP_NTSEG1_Pos (8U)
4606 #define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos) /*!< 0x0000FF00 */
4607 #define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk /*!<Nominal Time segment before sample point */
4608 #define FDCAN_NBTP_NBRP_Pos (16U)
4609 #define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos) /*!< 0x01FF0000 */
4610 #define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk /*!<Bit Rate Prescaler */
4611 #define FDCAN_NBTP_NSJW_Pos (25U)
4612 #define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos) /*!< 0xFE000000 */
4613 #define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk /*!<Nominal (Re)Synchronization Jump Width */
4614
4615 /***************** Bit definition for FDCAN_TSCC register ********************/
4616 #define FDCAN_TSCC_TSS_Pos (0U)
4617 #define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos) /*!< 0x00000003 */
4618 #define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk /*!<Timestamp Select */
4619 #define FDCAN_TSCC_TCP_Pos (16U)
4620 #define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos) /*!< 0x000F0000 */
4621 #define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk /*!<Timestamp Counter Prescaler */
4622
4623 /***************** Bit definition for FDCAN_TSCV register ********************/
4624 #define FDCAN_TSCV_TSC_Pos (0U)
4625 #define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos) /*!< 0x0000FFFF */
4626 #define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk /*!<Timestamp Counter */
4627
4628 /***************** Bit definition for FDCAN_TOCC register ********************/
4629 #define FDCAN_TOCC_ETOC_Pos (0U)
4630 #define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos) /*!< 0x00000001 */
4631 #define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk /*!<Enable Timeout Counter */
4632 #define FDCAN_TOCC_TOS_Pos (1U)
4633 #define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos) /*!< 0x00000006 */
4634 #define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk /*!<Timeout Select */
4635 #define FDCAN_TOCC_TOP_Pos (16U)
4636 #define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos) /*!< 0xFFFF0000 */
4637 #define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk /*!<Timeout Period */
4638
4639 /***************** Bit definition for FDCAN_TOCV register ********************/
4640 #define FDCAN_TOCV_TOC_Pos (0U)
4641 #define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos) /*!< 0x0000FFFF */
4642 #define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk /*!<Timeout Counter */
4643
4644 /***************** Bit definition for FDCAN_ECR register *********************/
4645 #define FDCAN_ECR_TEC_Pos (0U)
4646 #define FDCAN_ECR_TEC_Msk (0xFFUL << FDCAN_ECR_TEC_Pos) /*!< 0x000000FF */
4647 #define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk /*!<Transmit Error Counter */
4648 #define FDCAN_ECR_REC_Pos (8U)
4649 #define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos) /*!< 0x00007F00 */
4650 #define FDCAN_ECR_REC FDCAN_ECR_REC_Msk /*!<Receive Error Counter */
4651 #define FDCAN_ECR_RP_Pos (15U)
4652 #define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos) /*!< 0x00008000 */
4653 #define FDCAN_ECR_RP FDCAN_ECR_RP_Msk /*!<Receive Error Passive */
4654 #define FDCAN_ECR_CEL_Pos (16U)
4655 #define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos) /*!< 0x00FF0000 */
4656 #define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk /*!<CAN Error Logging */
4657
4658 /***************** Bit definition for FDCAN_PSR register *********************/
4659 #define FDCAN_PSR_LEC_Pos (0U)
4660 #define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos) /*!< 0x00000007 */
4661 #define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk /*!<Last Error Code */
4662 #define FDCAN_PSR_ACT_Pos (3U)
4663 #define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos) /*!< 0x00000018 */
4664 #define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk /*!<Activity */
4665 #define FDCAN_PSR_EP_Pos (5U)
4666 #define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos) /*!< 0x00000020 */
4667 #define FDCAN_PSR_EP FDCAN_PSR_EP_Msk /*!<Error Passive */
4668 #define FDCAN_PSR_EW_Pos (6U)
4669 #define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos) /*!< 0x00000040 */
4670 #define FDCAN_PSR_EW FDCAN_PSR_EW_Msk /*!<Warning Status */
4671 #define FDCAN_PSR_BO_Pos (7U)
4672 #define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos) /*!< 0x00000080 */
4673 #define FDCAN_PSR_BO FDCAN_PSR_BO_Msk /*!<Bus_Off Status */
4674 #define FDCAN_PSR_DLEC_Pos (8U)
4675 #define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos) /*!< 0x00000700 */
4676 #define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk /*!<Data Last Error Code */
4677 #define FDCAN_PSR_RESI_Pos (11U)
4678 #define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos) /*!< 0x00000800 */
4679 #define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk /*!<ESI flag of last received FDCAN Message */
4680 #define FDCAN_PSR_RBRS_Pos (12U)
4681 #define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos) /*!< 0x00001000 */
4682 #define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk /*!<BRS flag of last received FDCAN Message */
4683 #define FDCAN_PSR_REDL_Pos (13U)
4684 #define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos) /*!< 0x00002000 */
4685 #define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk /*!<Received FDCAN Message */
4686 #define FDCAN_PSR_PXE_Pos (14U)
4687 #define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos) /*!< 0x00004000 */
4688 #define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk /*!<Protocol Exception Event */
4689 #define FDCAN_PSR_TDCV_Pos (16U)
4690 #define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos) /*!< 0x007F0000 */
4691 #define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk /*!<Transmitter Delay Compensation Value */
4692
4693 /***************** Bit definition for FDCAN_TDCR register ********************/
4694 #define FDCAN_TDCR_TDCF_Pos (0U)
4695 #define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos) /*!< 0x0000007F */
4696 #define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk /*!<Transmitter Delay Compensation Filter */
4697 #define FDCAN_TDCR_TDCO_Pos (8U)
4698 #define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos) /*!< 0x00007F00 */
4699 #define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk /*!<Transmitter Delay Compensation Offset */
4700
4701 /***************** Bit definition for FDCAN_IR register **********************/
4702 #define FDCAN_IR_RF0N_Pos (0U)
4703 #define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos) /*!< 0x00000001 */
4704 #define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk /*!<Rx FIFO 0 New Message */
4705 #define FDCAN_IR_RF0F_Pos (1U)
4706 #define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos) /*!< 0x00000002 */
4707 #define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk /*!<Rx FIFO 0 Full */
4708 #define FDCAN_IR_RF0L_Pos (2U)
4709 #define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos) /*!< 0x00000004 */
4710 #define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
4711 #define FDCAN_IR_RF1N_Pos (3U)
4712 #define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos) /*!< 0x00000008 */
4713 #define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk /*!<Rx FIFO 1 New Message */
4714 #define FDCAN_IR_RF1F_Pos (4U)
4715 #define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos) /*!< 0x00000010 */
4716 #define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk /*!<Rx FIFO 1 Full */
4717 #define FDCAN_IR_RF1L_Pos (5U)
4718 #define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos) /*!< 0x00000020 */
4719 #define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
4720 #define FDCAN_IR_HPM_Pos (6U)
4721 #define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos) /*!< 0x00000040 */
4722 #define FDCAN_IR_HPM FDCAN_IR_HPM_Msk /*!<High Priority Message */
4723 #define FDCAN_IR_TC_Pos (7U)
4724 #define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos) /*!< 0x00000080 */
4725 #define FDCAN_IR_TC FDCAN_IR_TC_Msk /*!<Transmission Completed */
4726 #define FDCAN_IR_TCF_Pos (8U)
4727 #define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos) /*!< 0x00000100 */
4728 #define FDCAN_IR_TCF FDCAN_IR_TCF_Msk /*!<Transmission Cancellation Finished */
4729 #define FDCAN_IR_TFE_Pos (9U)
4730 #define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos) /*!< 0x00000200 */
4731 #define FDCAN_IR_TFE FDCAN_IR_TFE_Msk /*!<Tx FIFO Empty */
4732 #define FDCAN_IR_TEFN_Pos (10U)
4733 #define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos) /*!< 0x00000400 */
4734 #define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk /*!<Tx Event FIFO New Entry */
4735 #define FDCAN_IR_TEFF_Pos (11U)
4736 #define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos) /*!< 0x00000800 */
4737 #define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk /*!<Tx Event FIFO Full */
4738 #define FDCAN_IR_TEFL_Pos (12U)
4739 #define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos) /*!< 0x00001000 */
4740 #define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk /*!<Tx Event FIFO Element Lost */
4741 #define FDCAN_IR_TSW_Pos (13U)
4742 #define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos) /*!< 0x00002000 */
4743 #define FDCAN_IR_TSW FDCAN_IR_TSW_Msk /*!<Timestamp Wraparound */
4744 #define FDCAN_IR_MRAF_Pos (14U)
4745 #define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos) /*!< 0x00004000 */
4746 #define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk /*!<Message RAM Access Failure */
4747 #define FDCAN_IR_TOO_Pos (15U)
4748 #define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos) /*!< 0x00008000 */
4749 #define FDCAN_IR_TOO FDCAN_IR_TOO_Msk /*!<Timeout Occurred */
4750 #define FDCAN_IR_ELO_Pos (16U)
4751 #define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos) /*!< 0x00010000 */
4752 #define FDCAN_IR_ELO FDCAN_IR_ELO_Msk /*!<Error Logging Overflow */
4753 #define FDCAN_IR_EP_Pos (17U)
4754 #define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos) /*!< 0x00020000 */
4755 #define FDCAN_IR_EP FDCAN_IR_EP_Msk /*!<Error Passive */
4756 #define FDCAN_IR_EW_Pos (18U)
4757 #define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos) /*!< 0x00040000 */
4758 #define FDCAN_IR_EW FDCAN_IR_EW_Msk /*!<Warning Status */
4759 #define FDCAN_IR_BO_Pos (19U)
4760 #define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos) /*!< 0x00080000 */
4761 #define FDCAN_IR_BO FDCAN_IR_BO_Msk /*!<Bus_Off Status */
4762 #define FDCAN_IR_WDI_Pos (20U)
4763 #define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos) /*!< 0x00100000 */
4764 #define FDCAN_IR_WDI FDCAN_IR_WDI_Msk /*!<Watchdog Interrupt */
4765 #define FDCAN_IR_PEA_Pos (21U)
4766 #define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos) /*!< 0x00200000 */
4767 #define FDCAN_IR_PEA FDCAN_IR_PEA_Msk /*!<Protocol Error in Arbitration Phase */
4768 #define FDCAN_IR_PED_Pos (22U)
4769 #define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos) /*!< 0x00400000 */
4770 #define FDCAN_IR_PED FDCAN_IR_PED_Msk /*!<Protocol Error in Data Phase */
4771 #define FDCAN_IR_ARA_Pos (23U)
4772 #define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos) /*!< 0x00800000 */
4773 #define FDCAN_IR_ARA FDCAN_IR_ARA_Msk /*!<Access to Reserved Address */
4774
4775 /***************** Bit definition for FDCAN_IE register **********************/
4776 #define FDCAN_IE_RF0NE_Pos (0U)
4777 #define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos) /*!< 0x00000001 */
4778 #define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk /*!<Rx FIFO 0 New Message Enable */
4779 #define FDCAN_IE_RF0FE_Pos (1U)
4780 #define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos) /*!< 0x00000002 */
4781 #define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk /*!<Rx FIFO 0 Full Enable */
4782 #define FDCAN_IE_RF0LE_Pos (2U)
4783 #define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos) /*!< 0x00000004 */
4784 #define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk /*!<Rx FIFO 0 Message Lost Enable */
4785 #define FDCAN_IE_RF1NE_Pos (3U)
4786 #define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos) /*!< 0x00000008 */
4787 #define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk /*!<Rx FIFO 1 New Message Enable */
4788 #define FDCAN_IE_RF1FE_Pos (4U)
4789 #define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos) /*!< 0x00000010 */
4790 #define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk /*!<Rx FIFO 1 Full Enable */
4791 #define FDCAN_IE_RF1LE_Pos (5U)
4792 #define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos) /*!< 0x00000020 */
4793 #define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk /*!<Rx FIFO 1 Message Lost Enable */
4794 #define FDCAN_IE_HPME_Pos (6U)
4795 #define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos) /*!< 0x00000040 */
4796 #define FDCAN_IE_HPME FDCAN_IE_HPME_Msk /*!<High Priority Message Enable */
4797 #define FDCAN_IE_TCE_Pos (7U)
4798 #define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos) /*!< 0x00000080 */
4799 #define FDCAN_IE_TCE FDCAN_IE_TCE_Msk /*!<Transmission Completed Enable */
4800 #define FDCAN_IE_TCFE_Pos (8U)
4801 #define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos) /*!< 0x00000100 */
4802 #define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk /*!<Transmission Cancellation Finished Enable*/
4803 #define FDCAN_IE_TFEE_Pos (9U)
4804 #define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos) /*!< 0x00000200 */
4805 #define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk /*!<Tx FIFO Empty Enable */
4806 #define FDCAN_IE_TEFNE_Pos (10U)
4807 #define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos) /*!< 0x00000400 */
4808 #define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk /*!<Tx Event FIFO New Entry Enable */
4809 #define FDCAN_IE_TEFFE_Pos (11U)
4810 #define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos) /*!< 0x00000800 */
4811 #define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk /*!<Tx Event FIFO Full Enable */
4812 #define FDCAN_IE_TEFLE_Pos (12U)
4813 #define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos) /*!< 0x00001000 */
4814 #define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk /*!<Tx Event FIFO Element Lost Enable */
4815 #define FDCAN_IE_TSWE_Pos (13U)
4816 #define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos) /*!< 0x00002000 */
4817 #define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk /*!<Timestamp Wraparound Enable */
4818 #define FDCAN_IE_MRAFE_Pos (14U)
4819 #define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos) /*!< 0x00004000 */
4820 #define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk /*!<Message RAM Access Failure Enable */
4821 #define FDCAN_IE_TOOE_Pos (15U)
4822 #define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos) /*!< 0x00008000 */
4823 #define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk /*!<Timeout Occurred Enable */
4824 #define FDCAN_IE_ELOE_Pos (16U)
4825 #define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos) /*!< 0x00010000 */
4826 #define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk /*!<Error Logging Overflow Enable */
4827 #define FDCAN_IE_EPE_Pos (17U)
4828 #define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos) /*!< 0x00020000 */
4829 #define FDCAN_IE_EPE FDCAN_IE_EPE_Msk /*!<Error Passive Enable */
4830 #define FDCAN_IE_EWE_Pos (18U)
4831 #define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos) /*!< 0x00040000 */
4832 #define FDCAN_IE_EWE FDCAN_IE_EWE_Msk /*!<Warning Status Enable */
4833 #define FDCAN_IE_BOE_Pos (19U)
4834 #define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos) /*!< 0x00080000 */
4835 #define FDCAN_IE_BOE FDCAN_IE_BOE_Msk /*!<Bus_Off Status Enable */
4836 #define FDCAN_IE_WDIE_Pos (20U)
4837 #define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos) /*!< 0x00100000 */
4838 #define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk /*!<Watchdog Interrupt Enable */
4839 #define FDCAN_IE_PEAE_Pos (21U)
4840 #define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos) /*!< 0x00200000 */
4841 #define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk /*!<Protocol Error in Arbitration Phase Enable*/
4842 #define FDCAN_IE_PEDE_Pos (22U)
4843 #define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos) /*!< 0x00400000 */
4844 #define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk /*!<Protocol Error in Data Phase Enable */
4845 #define FDCAN_IE_ARAE_Pos (23U)
4846 #define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos) /*!< 0x00800000 */
4847 #define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk /*!<Access to Reserved Address Enable */
4848
4849 /***************** Bit definition for FDCAN_ILS register **********************/
4850 #define FDCAN_ILS_RXFIFO0_Pos (0U)
4851 #define FDCAN_ILS_RXFIFO0_Msk (0x1UL << FDCAN_ILS_RXFIFO0_Pos) /*!< 0x00000001 */
4852 #define FDCAN_ILS_RXFIFO0 FDCAN_ILS_RXFIFO0_Msk /*!<Rx FIFO 0 Message Lost
4853 Rx FIFO 0 is Full
4854 Rx FIFO 0 Has New Message */
4855 #define FDCAN_ILS_RXFIFO1_Pos (1U)
4856 #define FDCAN_ILS_RXFIFO1_Msk (0x1UL << FDCAN_ILS_RXFIFO1_Pos) /*!< 0x00000002 */
4857 #define FDCAN_ILS_RXFIFO1 FDCAN_ILS_RXFIFO1_Msk /*!<Rx FIFO 1 Message Lost
4858 Rx FIFO 1 is Full
4859 Rx FIFO 1 Has New Message */
4860 #define FDCAN_ILS_SMSG_Pos (2U)
4861 #define FDCAN_ILS_SMSG_Msk (0x1UL << FDCAN_ILS_SMSG_Pos) /*!< 0x00000004 */
4862 #define FDCAN_ILS_SMSG FDCAN_ILS_SMSG_Msk /*!<Transmission Cancellation Finished
4863 Transmission Completed
4864 High Priority Message */
4865 #define FDCAN_ILS_TFERR_Pos (3U)
4866 #define FDCAN_ILS_TFERR_Msk (0x1UL << FDCAN_ILS_TFERR_Pos) /*!< 0x00000008 */
4867 #define FDCAN_ILS_TFERR FDCAN_ILS_TFERR_Msk /*!<Tx Event FIFO Element Lost
4868 Tx Event FIFO Full
4869 Tx Event FIFO New Entry
4870 Tx FIFO Empty Interrupt Line */
4871 #define FDCAN_ILS_MISC_Pos (4U)
4872 #define FDCAN_ILS_MISC_Msk (0x1UL << FDCAN_ILS_MISC_Pos) /*!< 0x00000010 */
4873 #define FDCAN_ILS_MISC FDCAN_ILS_MISC_Msk /*!<Timeout Occurred
4874 Message RAM Access Failure
4875 Timestamp Wraparound */
4876 #define FDCAN_ILS_BERR_Pos (5U)
4877 #define FDCAN_ILS_BERR_Msk (0x1UL << FDCAN_ILS_BERR_Pos) /*!< 0x00000020 */
4878 #define FDCAN_ILS_BERR FDCAN_ILS_BERR_Msk /*!<Error Passive
4879 Error Logging Overflow */
4880 #define FDCAN_ILS_PERR_Pos (6U)
4881 #define FDCAN_ILS_PERR_Msk (0x1UL << FDCAN_ILS_PERR_Pos) /*!< 0x00000040 */
4882 #define FDCAN_ILS_PERR FDCAN_ILS_PERR_Msk /*!<Access to Reserved Address Line
4883 Protocol Error in Data Phase Line
4884 Protocol Error in Arbitration Phase Line
4885 Watchdog Interrupt Line
4886 Bus_Off Status
4887 Warning Status */
4888
4889 /***************** Bit definition for FDCAN_ILE register **********************/
4890 #define FDCAN_ILE_EINT0_Pos (0U)
4891 #define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos) /*!< 0x00000001 */
4892 #define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk /*!<Enable Interrupt Line 0 */
4893 #define FDCAN_ILE_EINT1_Pos (1U)
4894 #define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos) /*!< 0x00000002 */
4895 #define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk /*!<Enable Interrupt Line 1 */
4896
4897 /***************** Bit definition for FDCAN_RXGFC register ********************/
4898 #define FDCAN_RXGFC_RRFE_Pos (0U)
4899 #define FDCAN_RXGFC_RRFE_Msk (0x1UL << FDCAN_RXGFC_RRFE_Pos) /*!< 0x00000001 */
4900 #define FDCAN_RXGFC_RRFE FDCAN_RXGFC_RRFE_Msk /*!<Reject Remote Frames Extended */
4901 #define FDCAN_RXGFC_RRFS_Pos (1U)
4902 #define FDCAN_RXGFC_RRFS_Msk (0x1UL << FDCAN_RXGFC_RRFS_Pos) /*!< 0x00000002 */
4903 #define FDCAN_RXGFC_RRFS FDCAN_RXGFC_RRFS_Msk /*!<Reject Remote Frames Standard */
4904 #define FDCAN_RXGFC_ANFE_Pos (2U)
4905 #define FDCAN_RXGFC_ANFE_Msk (0x3UL << FDCAN_RXGFC_ANFE_Pos) /*!< 0x0000000C */
4906 #define FDCAN_RXGFC_ANFE FDCAN_RXGFC_ANFE_Msk /*!<Accept Non-matching Frames Extended */
4907 #define FDCAN_RXGFC_ANFS_Pos (4U)
4908 #define FDCAN_RXGFC_ANFS_Msk (0x3UL << FDCAN_RXGFC_ANFS_Pos) /*!< 0x00000030 */
4909 #define FDCAN_RXGFC_ANFS FDCAN_RXGFC_ANFS_Msk /*!<Accept Non-matching Frames Standard */
4910 #define FDCAN_RXGFC_F1OM_Pos (8U)
4911 #define FDCAN_RXGFC_F1OM_Msk (0x1UL << FDCAN_RXGFC_F1OM_Pos) /*!< 0x00000100 */
4912 #define FDCAN_RXGFC_F1OM FDCAN_RXGFC_F1OM_Msk /*!<FIFO 1 operation mode */
4913 #define FDCAN_RXGFC_F0OM_Pos (9U)
4914 #define FDCAN_RXGFC_F0OM_Msk (0x1UL << FDCAN_RXGFC_F0OM_Pos) /*!< 0x00000200 */
4915 #define FDCAN_RXGFC_F0OM FDCAN_RXGFC_F0OM_Msk /*!<FIFO 0 operation mode */
4916 #define FDCAN_RXGFC_LSS_Pos (16U)
4917 #define FDCAN_RXGFC_LSS_Msk (0x1FUL << FDCAN_RXGFC_LSS_Pos) /*!< 0x001F0000 */
4918 #define FDCAN_RXGFC_LSS FDCAN_RXGFC_LSS_Msk /*!<List Size Standard */
4919 #define FDCAN_RXGFC_LSE_Pos (24U)
4920 #define FDCAN_RXGFC_LSE_Msk (0xFUL << FDCAN_RXGFC_LSE_Pos) /*!< 0x0F000000 */
4921 #define FDCAN_RXGFC_LSE FDCAN_RXGFC_LSE_Msk /*!<List Size Extended */
4922
4923 /***************** Bit definition for FDCAN_XIDAM register ********************/
4924 #define FDCAN_XIDAM_EIDM_Pos (0U)
4925 #define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos) /*!< 0x1FFFFFFF */
4926 #define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk /*!<Extended ID Mask */
4927
4928 /***************** Bit definition for FDCAN_HPMS register *********************/
4929 #define FDCAN_HPMS_BIDX_Pos (0U)
4930 #define FDCAN_HPMS_BIDX_Msk (0x7UL << FDCAN_HPMS_BIDX_Pos) /*!< 0x00000007 */
4931 #define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk /*!<Buffer Index */
4932 #define FDCAN_HPMS_MSI_Pos (6U)
4933 #define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos) /*!< 0x000000C0 */
4934 #define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk /*!<Message Storage Indicator */
4935 #define FDCAN_HPMS_FIDX_Pos (8U)
4936 #define FDCAN_HPMS_FIDX_Msk (0x1FUL << FDCAN_HPMS_FIDX_Pos) /*!< 0x00001F00 */
4937 #define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk /*!<Filter Index */
4938 #define FDCAN_HPMS_FLST_Pos (15U)
4939 #define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos) /*!< 0x00008000 */
4940 #define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk /*!<Filter List */
4941
4942 /***************** Bit definition for FDCAN_RXF0S register ********************/
4943 #define FDCAN_RXF0S_F0FL_Pos (0U)
4944 #define FDCAN_RXF0S_F0FL_Msk (0xFUL << FDCAN_RXF0S_F0FL_Pos) /*!< 0x0000000F */
4945 #define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk /*!<Rx FIFO 0 Fill Level */
4946 #define FDCAN_RXF0S_F0GI_Pos (8U)
4947 #define FDCAN_RXF0S_F0GI_Msk (0x3UL << FDCAN_RXF0S_F0GI_Pos) /*!< 0x00000300 */
4948 #define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk /*!<Rx FIFO 0 Get Index */
4949 #define FDCAN_RXF0S_F0PI_Pos (16U)
4950 #define FDCAN_RXF0S_F0PI_Msk (0x3UL << FDCAN_RXF0S_F0PI_Pos) /*!< 0x00030000 */
4951 #define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk /*!<Rx FIFO 0 Put Index */
4952 #define FDCAN_RXF0S_F0F_Pos (24U)
4953 #define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos) /*!< 0x01000000 */
4954 #define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk /*!<Rx FIFO 0 Full */
4955 #define FDCAN_RXF0S_RF0L_Pos (25U)
4956 #define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos) /*!< 0x02000000 */
4957 #define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
4958
4959 /***************** Bit definition for FDCAN_RXF0A register ********************/
4960 #define FDCAN_RXF0A_F0AI_Pos (0U)
4961 #define FDCAN_RXF0A_F0AI_Msk (0x7UL << FDCAN_RXF0A_F0AI_Pos) /*!< 0x00000007 */
4962 #define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk /*!<Rx FIFO 0 Acknowledge Index */
4963
4964 /***************** Bit definition for FDCAN_RXF1S register ********************/
4965 #define FDCAN_RXF1S_F1FL_Pos (0U)
4966 #define FDCAN_RXF1S_F1FL_Msk (0xFUL << FDCAN_RXF1S_F1FL_Pos) /*!< 0x0000000F */
4967 #define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk /*!<Rx FIFO 1 Fill Level */
4968 #define FDCAN_RXF1S_F1GI_Pos (8U)
4969 #define FDCAN_RXF1S_F1GI_Msk (0x3UL << FDCAN_RXF1S_F1GI_Pos) /*!< 0x00000300 */
4970 #define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk /*!<Rx FIFO 1 Get Index */
4971 #define FDCAN_RXF1S_F1PI_Pos (16U)
4972 #define FDCAN_RXF1S_F1PI_Msk (0x3UL << FDCAN_RXF1S_F1PI_Pos) /*!< 0x00030000 */
4973 #define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk /*!<Rx FIFO 1 Put Index */
4974 #define FDCAN_RXF1S_F1F_Pos (24U)
4975 #define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos) /*!< 0x01000000 */
4976 #define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk /*!<Rx FIFO 1 Full */
4977 #define FDCAN_RXF1S_RF1L_Pos (25U)
4978 #define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos) /*!< 0x02000000 */
4979 #define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
4980
4981 /***************** Bit definition for FDCAN_RXF1A register ********************/
4982 #define FDCAN_RXF1A_F1AI_Pos (0U)
4983 #define FDCAN_RXF1A_F1AI_Msk (0x7UL << FDCAN_RXF1A_F1AI_Pos) /*!< 0x00000007 */
4984 #define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk /*!<Rx FIFO 1 Acknowledge Index */
4985
4986 /***************** Bit definition for FDCAN_TXBC register *********************/
4987 #define FDCAN_TXBC_TFQM_Pos (24U)
4988 #define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos) /*!< 0x01000000 */
4989 #define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk /*!<Tx FIFO/Queue Mode */
4990
4991 /***************** Bit definition for FDCAN_TXFQS register *********************/
4992 #define FDCAN_TXFQS_TFFL_Pos (0U)
4993 #define FDCAN_TXFQS_TFFL_Msk (0x7UL << FDCAN_TXFQS_TFFL_Pos) /*!< 0x00000007 */
4994 #define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk /*!<Tx FIFO Free Level */
4995 #define FDCAN_TXFQS_TFGI_Pos (8U)
4996 #define FDCAN_TXFQS_TFGI_Msk (0x3UL << FDCAN_TXFQS_TFGI_Pos) /*!< 0x00000300 */
4997 #define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk /*!<Tx FIFO Get Index */
4998 #define FDCAN_TXFQS_TFQPI_Pos (16U)
4999 #define FDCAN_TXFQS_TFQPI_Msk (0x3UL << FDCAN_TXFQS_TFQPI_Pos) /*!< 0x00030000 */
5000 #define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk /*!<Tx FIFO/Queue Put Index */
5001 #define FDCAN_TXFQS_TFQF_Pos (21U)
5002 #define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos) /*!< 0x00200000 */
5003 #define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk /*!<Tx FIFO/Queue Full */
5004
5005 /***************** Bit definition for FDCAN_TXBRP register *********************/
5006 #define FDCAN_TXBRP_TRP_Pos (0U)
5007 #define FDCAN_TXBRP_TRP_Msk (0x7UL << FDCAN_TXBRP_TRP_Pos) /*!< 0x00000007 */
5008 #define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk /*!<Transmission Request Pending */
5009
5010 /***************** Bit definition for FDCAN_TXBAR register *********************/
5011 #define FDCAN_TXBAR_AR_Pos (0U)
5012 #define FDCAN_TXBAR_AR_Msk (0x7UL << FDCAN_TXBAR_AR_Pos) /*!< 0x00000007 */
5013 #define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk /*!<Add Request */
5014
5015 /***************** Bit definition for FDCAN_TXBCR register *********************/
5016 #define FDCAN_TXBCR_CR_Pos (0U)
5017 #define FDCAN_TXBCR_CR_Msk (0x7UL << FDCAN_TXBCR_CR_Pos) /*!< 0x00000007 */
5018 #define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk /*!<Cancellation Request */
5019
5020 /***************** Bit definition for FDCAN_TXBTO register *********************/
5021 #define FDCAN_TXBTO_TO_Pos (0U)
5022 #define FDCAN_TXBTO_TO_Msk (0x7UL << FDCAN_TXBTO_TO_Pos) /*!< 0x00000007 */
5023 #define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk /*!<Transmission Occurred */
5024
5025 /***************** Bit definition for FDCAN_TXBCF register *********************/
5026 #define FDCAN_TXBCF_CF_Pos (0U)
5027 #define FDCAN_TXBCF_CF_Msk (0x7UL << FDCAN_TXBCF_CF_Pos) /*!< 0x00000007 */
5028 #define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk /*!<Cancellation Finished */
5029
5030 /***************** Bit definition for FDCAN_TXBTIE register ********************/
5031 #define FDCAN_TXBTIE_TIE_Pos (0U)
5032 #define FDCAN_TXBTIE_TIE_Msk (0x7UL << FDCAN_TXBTIE_TIE_Pos) /*!< 0x00000007 */
5033 #define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk /*!<Transmission Interrupt Enable */
5034
5035 /***************** Bit definition for FDCAN_ TXBCIE register *******************/
5036 #define FDCAN_TXBCIE_CFIE_Pos (0U)
5037 #define FDCAN_TXBCIE_CFIE_Msk (0x7UL << FDCAN_TXBCIE_CFIE_Pos) /*!< 0x00000007 */
5038 #define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk /*!<Cancellation Finished Interrupt Enable */
5039
5040 /***************** Bit definition for FDCAN_TXEFS register *********************/
5041 #define FDCAN_TXEFS_EFFL_Pos (0U)
5042 #define FDCAN_TXEFS_EFFL_Msk (0x7UL << FDCAN_TXEFS_EFFL_Pos) /*!< 0x00000007 */
5043 #define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk /*!<Event FIFO Fill Level */
5044 #define FDCAN_TXEFS_EFGI_Pos (8U)
5045 #define FDCAN_TXEFS_EFGI_Msk (0x3UL << FDCAN_TXEFS_EFGI_Pos) /*!< 0x00000300 */
5046 #define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk /*!<Event FIFO Get Index */
5047 #define FDCAN_TXEFS_EFPI_Pos (16U)
5048 #define FDCAN_TXEFS_EFPI_Msk (0x3UL << FDCAN_TXEFS_EFPI_Pos) /*!< 0x00030000 */
5049 #define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk /*!<Event FIFO Put Index */
5050 #define FDCAN_TXEFS_EFF_Pos (24U)
5051 #define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos) /*!< 0x01000000 */
5052 #define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk /*!<Event FIFO Full */
5053 #define FDCAN_TXEFS_TEFL_Pos (25U)
5054 #define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos) /*!< 0x02000000 */
5055 #define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk /*!<Tx Event FIFO Element Lost */
5056
5057 /***************** Bit definition for FDCAN_TXEFA register *********************/
5058 #define FDCAN_TXEFA_EFAI_Pos (0U)
5059 #define FDCAN_TXEFA_EFAI_Msk (0x3UL << FDCAN_TXEFA_EFAI_Pos) /*!< 0x00000003 */
5060 #define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk /*!<Event FIFO Acknowledge Index */
5061
5062
5063 /*!<FDCAN config registers */
5064 /***************** Bit definition for FDCAN_CKDIV register *********************/
5065 #define FDCAN_CKDIV_PDIV_Pos (0U)
5066 #define FDCAN_CKDIV_PDIV_Msk (0xFUL << FDCAN_CKDIV_PDIV_Pos) /*!< 0x0000000F */
5067 #define FDCAN_CKDIV_PDIV FDCAN_CKDIV_PDIV_Msk /*!<Input Clock Divider */
5068
5069 /******************************************************************************/
5070 /* */
5071 /* FLASH */
5072 /* */
5073 /******************************************************************************/
5074 /******************* Bits definition for FLASH_ACR register *****************/
5075 #define FLASH_ACR_LATENCY_Pos (0U)
5076 #define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
5077 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
5078 #define FLASH_ACR_LATENCY_0WS (0x00000000U)
5079 #define FLASH_ACR_LATENCY_1WS (0x00000001U)
5080 #define FLASH_ACR_LATENCY_2WS (0x00000002U)
5081 #define FLASH_ACR_LATENCY_3WS (0x00000003U)
5082 #define FLASH_ACR_LATENCY_4WS (0x00000004U)
5083 #define FLASH_ACR_LATENCY_5WS (0x00000005U)
5084 #define FLASH_ACR_LATENCY_6WS (0x00000006U)
5085 #define FLASH_ACR_LATENCY_7WS (0x00000007U)
5086 #define FLASH_ACR_LATENCY_8WS (0x00000008U)
5087 #define FLASH_ACR_LATENCY_9WS (0x00000009U)
5088 #define FLASH_ACR_LATENCY_10WS (0x0000000AU)
5089 #define FLASH_ACR_LATENCY_11WS (0x0000000BU)
5090 #define FLASH_ACR_LATENCY_12WS (0x0000000CU)
5091 #define FLASH_ACR_LATENCY_13WS (0x0000000DU)
5092 #define FLASH_ACR_LATENCY_14WS (0x0000000EU)
5093 #define FLASH_ACR_LATENCY_15WS (0x0000000FU)
5094 #define FLASH_ACR_PRFTEN_Pos (8U)
5095 #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
5096 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
5097 #define FLASH_ACR_ICEN_Pos (9U)
5098 #define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
5099 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
5100 #define FLASH_ACR_DCEN_Pos (10U)
5101 #define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
5102 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
5103 #define FLASH_ACR_ICRST_Pos (11U)
5104 #define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
5105 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
5106 #define FLASH_ACR_DCRST_Pos (12U)
5107 #define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
5108 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
5109 #define FLASH_ACR_RUN_PD_Pos (13U)
5110 #define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00002000 */
5111 #define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash power down mode during run */
5112 #define FLASH_ACR_SLEEP_PD_Pos (14U)
5113 #define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */
5114 #define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power down mode during sleep */
5115 #define FLASH_ACR_DBG_SWEN_Pos (18U)
5116 #define FLASH_ACR_DBG_SWEN_Msk (0x1UL << FLASH_ACR_DBG_SWEN_Pos) /*!< 0x00040000 */
5117 #define FLASH_ACR_DBG_SWEN FLASH_ACR_DBG_SWEN_Msk /*!< Software disable for debugger */
5118
5119 /******************* Bits definition for FLASH_SR register ******************/
5120 #define FLASH_SR_EOP_Pos (0U)
5121 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
5122 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
5123 #define FLASH_SR_OPERR_Pos (1U)
5124 #define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
5125 #define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
5126 #define FLASH_SR_PROGERR_Pos (3U)
5127 #define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */
5128 #define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
5129 #define FLASH_SR_WRPERR_Pos (4U)
5130 #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
5131 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
5132 #define FLASH_SR_PGAERR_Pos (5U)
5133 #define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
5134 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
5135 #define FLASH_SR_SIZERR_Pos (6U)
5136 #define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */
5137 #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
5138 #define FLASH_SR_PGSERR_Pos (7U)
5139 #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
5140 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
5141 #define FLASH_SR_MISERR_Pos (8U)
5142 #define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */
5143 #define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
5144 #define FLASH_SR_FASTERR_Pos (9U)
5145 #define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */
5146 #define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
5147 #define FLASH_SR_RDERR_Pos (14U)
5148 #define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */
5149 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
5150 #define FLASH_SR_OPTVERR_Pos (15U)
5151 #define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */
5152 #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
5153 #define FLASH_SR_BSY_Pos (16U)
5154 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
5155 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
5156
5157 /******************* Bits definition for FLASH_CR register ******************/
5158 #define FLASH_CR_PG_Pos (0U)
5159 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */
5160 #define FLASH_CR_PG FLASH_CR_PG_Msk
5161 #define FLASH_CR_PER_Pos (1U)
5162 #define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */
5163 #define FLASH_CR_PER FLASH_CR_PER_Msk
5164 #define FLASH_CR_MER1_Pos (2U)
5165 #define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
5166 #define FLASH_CR_MER1 FLASH_CR_MER1_Msk
5167 #define FLASH_CR_PNB_Pos (3U)
5168 #define FLASH_CR_PNB_Msk (0x7FUL << FLASH_CR_PNB_Pos) /*!< 0x000003F8 */
5169 #define FLASH_CR_PNB FLASH_CR_PNB_Msk
5170 #define FLASH_CR_BKER_Pos (11U)
5171 #define FLASH_CR_BKER_Msk (0x1UL << FLASH_CR_BKER_Pos) /*!< 0x00000800 */
5172 #define FLASH_CR_BKER FLASH_CR_BKER_Msk
5173 #define FLASH_CR_MER2_Pos (15U)
5174 #define FLASH_CR_MER2_Msk (0x1UL << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
5175 #define FLASH_CR_MER2 FLASH_CR_MER2_Msk
5176 #define FLASH_CR_STRT_Pos (16U)
5177 #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
5178 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
5179 #define FLASH_CR_OPTSTRT_Pos (17U)
5180 #define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
5181 #define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
5182 #define FLASH_CR_FSTPG_Pos (18U)
5183 #define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
5184 #define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
5185 #define FLASH_CR_EOPIE_Pos (24U)
5186 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
5187 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
5188 #define FLASH_CR_ERRIE_Pos (25U)
5189 #define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
5190 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
5191 #define FLASH_CR_RDERRIE_Pos (26U)
5192 #define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */
5193 #define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
5194 #define FLASH_CR_OBL_LAUNCH_Pos (27U)
5195 #define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
5196 #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
5197 #define FLASH_CR_SEC_PROT1_Pos (28U)
5198 #define FLASH_CR_SEC_PROT1_Msk (0x1UL << FLASH_CR_SEC_PROT1_Pos) /*!< 0x10000000 */
5199 #define FLASH_CR_SEC_PROT1 FLASH_CR_SEC_PROT1_Msk
5200 #define FLASH_CR_SEC_PROT2_Pos (29U)
5201 #define FLASH_CR_SEC_PROT2_Msk (0x1UL << FLASH_CR_SEC_PROT2_Pos) /*!< 0x20000000 */
5202 #define FLASH_CR_SEC_PROT2 FLASH_CR_SEC_PROT2_Msk
5203 #define FLASH_CR_OPTLOCK_Pos (30U)
5204 #define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
5205 #define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
5206 #define FLASH_CR_LOCK_Pos (31U)
5207 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
5208 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
5209
5210 /******************* Bits definition for FLASH_ECCR register ***************/
5211 #define FLASH_ECCR_ADDR_ECC_Pos (0U)
5212 #define FLASH_ECCR_ADDR_ECC_Msk (0x7FFFFUL << FLASH_ECCR_ADDR_ECC_Pos)/*!< 0x0007FFFF */
5213 #define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
5214 #define FLASH_ECCR_BK_ECC_Pos (21U)
5215 #define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */
5216 #define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk
5217 #define FLASH_ECCR_SYSF_ECC_Pos (22U)
5218 #define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */
5219 #define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
5220 #define FLASH_ECCR_ECCIE_Pos (24U)
5221 #define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */
5222 #define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk
5223 #define FLASH_ECCR_ECCC2_Pos (28U)
5224 #define FLASH_ECCR_ECCC2_Msk (0x1UL << FLASH_ECCR_ECCC2_Pos) /*!< 0x10000000 */
5225 #define FLASH_ECCR_ECCC2 FLASH_ECCR_ECCC2_Msk
5226 #define FLASH_ECCR_ECCD2_Pos (29U)
5227 #define FLASH_ECCR_ECCD2_Msk (0x1UL << FLASH_ECCR_ECCD2_Pos) /*!< 0x20000000 */
5228 #define FLASH_ECCR_ECCD2 FLASH_ECCR_ECCD2_Msk
5229 #define FLASH_ECCR_ECCC_Pos (30U)
5230 #define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
5231 #define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
5232 #define FLASH_ECCR_ECCD_Pos (31U)
5233 #define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
5234 #define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
5235
5236 /******************* Bits definition for FLASH_OPTR register ***************/
5237 #define FLASH_OPTR_RDP_Pos (0U)
5238 #define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
5239 #define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
5240 #define FLASH_OPTR_BOR_LEV_Pos (8U)
5241 #define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */
5242 #define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk
5243 #define FLASH_OPTR_BOR_LEV_0 (0x0UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000000 */
5244 #define FLASH_OPTR_BOR_LEV_1 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */
5245 #define FLASH_OPTR_BOR_LEV_2 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */
5246 #define FLASH_OPTR_BOR_LEV_3 (0x3UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000300 */
5247 #define FLASH_OPTR_BOR_LEV_4 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */
5248 #define FLASH_OPTR_nRST_STOP_Pos (12U)
5249 #define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */
5250 #define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
5251 #define FLASH_OPTR_nRST_STDBY_Pos (13U)
5252 #define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
5253 #define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
5254 #define FLASH_OPTR_nRST_SHDW_Pos (14U)
5255 #define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */
5256 #define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
5257 #define FLASH_OPTR_IWDG_SW_Pos (16U)
5258 #define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
5259 #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
5260 #define FLASH_OPTR_IWDG_STOP_Pos (17U)
5261 #define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
5262 #define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
5263 #define FLASH_OPTR_IWDG_STDBY_Pos (18U)
5264 #define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
5265 #define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
5266 #define FLASH_OPTR_WWDG_SW_Pos (19U)
5267 #define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
5268 #define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
5269 #define FLASH_OPTR_BFB2_Pos (20U)
5270 #define FLASH_OPTR_BFB2_Msk (0x1UL << FLASH_OPTR_BFB2_Pos) /*!< 0x00100000 */
5271 #define FLASH_OPTR_BFB2 FLASH_OPTR_BFB2_Msk
5272 #define FLASH_OPTR_DBANK_Pos (22U)
5273 #define FLASH_OPTR_DBANK_Msk (0x1UL << FLASH_OPTR_DBANK_Pos) /*!< 0x00400000 */
5274 #define FLASH_OPTR_DBANK FLASH_OPTR_DBANK_Msk
5275 #define FLASH_OPTR_nBOOT1_Pos (23U)
5276 #define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */
5277 #define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
5278 #define FLASH_OPTR_SRAM_PE_Pos (24U)
5279 #define FLASH_OPTR_SRAM_PE_Msk (0x1UL << FLASH_OPTR_SRAM_PE_Pos) /*!< 0x01000000 */
5280 #define FLASH_OPTR_SRAM_PE FLASH_OPTR_SRAM_PE_Msk
5281 #define FLASH_OPTR_CCMSRAM_RST_Pos (25U)
5282 #define FLASH_OPTR_CCMSRAM_RST_Msk (0x1UL << FLASH_OPTR_CCMSRAM_RST_Pos)/*!< 0x02000000 */
5283 #define FLASH_OPTR_CCMSRAM_RST FLASH_OPTR_CCMSRAM_RST_Msk
5284 #define FLASH_OPTR_nSWBOOT0_Pos (26U)
5285 #define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */
5286 #define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk
5287 #define FLASH_OPTR_nBOOT0_Pos (27U)
5288 #define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */
5289 #define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk
5290 #define FLASH_OPTR_NRST_MODE_Pos (28U)
5291 #define FLASH_OPTR_NRST_MODE_Msk (0x3UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x30000000 */
5292 #define FLASH_OPTR_NRST_MODE FLASH_OPTR_NRST_MODE_Msk
5293 #define FLASH_OPTR_NRST_MODE_0 (0x1UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x10000000 */
5294 #define FLASH_OPTR_NRST_MODE_1 (0x2UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x20000000 */
5295 #define FLASH_OPTR_IRHEN_Pos (30U)
5296 #define FLASH_OPTR_IRHEN_Msk (0x1UL << FLASH_OPTR_IRHEN_Pos) /*!< 0x40000000 */
5297 #define FLASH_OPTR_IRHEN FLASH_OPTR_IRHEN_Msk
5298
5299 /****************** Bits definition for FLASH_PCROP1SR register **********/
5300 #define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U)
5301 #define FLASH_PCROP1SR_PCROP1_STRT_Msk (0x7FFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos)/*!< 0x00007FFF */
5302 #define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk
5303
5304 /****************** Bits definition for FLASH_PCROP1ER register ***********/
5305 #define FLASH_PCROP1ER_PCROP1_END_Pos (0U)
5306 #define FLASH_PCROP1ER_PCROP1_END_Msk (0x7FFFUL << FLASH_PCROP1ER_PCROP1_END_Pos)/*!< 0x00007FFF */
5307 #define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk
5308 #define FLASH_PCROP1ER_PCROP_RDP_Pos (31U)
5309 #define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos)/*!< 0x80000000 */
5310 #define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk
5311
5312 /****************** Bits definition for FLASH_WRP1AR register ***************/
5313 #define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
5314 #define FLASH_WRP1AR_WRP1A_STRT_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_STRT_Pos)/*!< 0x0000007F */
5315 #define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
5316 #define FLASH_WRP1AR_WRP1A_END_Pos (16U)
5317 #define FLASH_WRP1AR_WRP1A_END_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_END_Pos)/*!< 0x007F0000 */
5318 #define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
5319
5320 /****************** Bits definition for FLASH_WRPB1R register ***************/
5321 #define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
5322 #define FLASH_WRP1BR_WRP1B_STRT_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_STRT_Pos)/*!< 0x0000007F */
5323 #define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
5324 #define FLASH_WRP1BR_WRP1B_END_Pos (16U)
5325 #define FLASH_WRP1BR_WRP1B_END_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_END_Pos)/*!< 0x007F0000 */
5326 #define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
5327
5328 /****************** Bits definition for FLASH_PCROP2SR register **********/
5329 #define FLASH_PCROP2SR_PCROP2_STRT_Pos (0U)
5330 #define FLASH_PCROP2SR_PCROP2_STRT_Msk (0x07FFFUL << FLASH_PCROP2SR_PCROP2_STRT_Pos)/*!< 0x00007FFF */
5331 #define FLASH_PCROP2SR_PCROP2_STRT FLASH_PCROP2SR_PCROP2_STRT_Msk
5332
5333 /****************** Bits definition for FLASH_PCROP2ER register ***********/
5334 #define FLASH_PCROP2ER_PCROP2_END_Pos (0U)
5335 #define FLASH_PCROP2ER_PCROP2_END_Msk (0x07FFFUL << FLASH_PCROP2ER_PCROP2_END_Pos)/*!< 0x00007FFF */
5336 #define FLASH_PCROP2ER_PCROP2_END FLASH_PCROP2ER_PCROP2_END_Msk
5337
5338 /****************** Bits definition for FLASH_WRP2AR register ***************/
5339 #define FLASH_WRP2AR_WRP2A_STRT_Pos (0U)
5340 #define FLASH_WRP2AR_WRP2A_STRT_Msk (0x7FUL << FLASH_WRP2AR_WRP2A_STRT_Pos)/*!< 0x000000FF */
5341 #define FLASH_WRP2AR_WRP2A_STRT FLASH_WRP2AR_WRP2A_STRT_Msk
5342 #define FLASH_WRP2AR_WRP2A_END_Pos (16U)
5343 #define FLASH_WRP2AR_WRP2A_END_Msk (0x7FUL << FLASH_WRP2AR_WRP2A_END_Pos)/*!< 0x00FF0000 */
5344 #define FLASH_WRP2AR_WRP2A_END FLASH_WRP2AR_WRP2A_END_Msk
5345
5346 /****************** Bits definition for FLASH_WRP2BR register ***************/
5347 #define FLASH_WRP2BR_WRP2B_STRT_Pos (0U)
5348 #define FLASH_WRP2BR_WRP2B_STRT_Msk (0x7FUL << FLASH_WRP2BR_WRP2B_STRT_Pos)/*!< 0x0000007F */
5349 #define FLASH_WRP2BR_WRP2B_STRT FLASH_WRP2BR_WRP2B_STRT_Msk
5350 #define FLASH_WRP2BR_WRP2B_END_Pos (16U)
5351 #define FLASH_WRP2BR_WRP2B_END_Msk (0x7FUL << FLASH_WRP2BR_WRP2B_END_Pos)/*!< 0x007F0000 */
5352 #define FLASH_WRP2BR_WRP2B_END FLASH_WRP2BR_WRP2B_END_Msk
5353
5354 /****************** Bits definition for FLASH_SEC1R register **************/
5355 #define FLASH_SEC1R_SEC_SIZE1_Pos (0U)
5356 #define FLASH_SEC1R_SEC_SIZE1_Msk (0xFFUL << FLASH_SEC1R_SEC_SIZE1_Pos)/*!< 0x000000FF */
5357 #define FLASH_SEC1R_SEC_SIZE1 FLASH_SEC1R_SEC_SIZE1_Msk
5358 #define FLASH_SEC1R_BOOT_LOCK_Pos (16U)
5359 #define FLASH_SEC1R_BOOT_LOCK_Msk (0x1UL << FLASH_SEC1R_BOOT_LOCK_Pos)/*!< 0x00010000 */
5360 #define FLASH_SEC1R_BOOT_LOCK FLASH_SEC1R_BOOT_LOCK_Msk
5361
5362 /****************** Bits definition for FLASH_SEC2R register **************/
5363 #define FLASH_SEC2R_SEC_SIZE2_Pos (0U)
5364 #define FLASH_SEC2R_SEC_SIZE2_Msk (0xFFUL << FLASH_SEC2R_SEC_SIZE2_Pos)/*!< 0x000000FF */
5365 #define FLASH_SEC2R_SEC_SIZE2 FLASH_SEC2R_SEC_SIZE2_Msk
5366
5367 /******************************************************************************/
5368 /* */
5369 /* Filter Mathematical ACcelerator unit (FMAC) */
5370 /* */
5371 /******************************************************************************/
5372 /***************** Bit definition for FMAC_X1BUFCFG register ****************/
5373 #define FMAC_X1BUFCFG_X1_BASE_Pos (0U)
5374 #define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */
5375 #define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */
5376 #define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U)
5377 #define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos)/*!< 0x0000FF00 */
5378 #define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */
5379 #define FMAC_X1BUFCFG_FULL_WM_Pos (24U)
5380 #define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */
5381 #define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */
5382 /***************** Bit definition for FMAC_X2BUFCFG register ****************/
5383 #define FMAC_X2BUFCFG_X2_BASE_Pos (0U)
5384 #define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */
5385 #define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */
5386 #define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U)
5387 #define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos)/*!< 0x0000FF00 */
5388 #define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */
5389 /***************** Bit definition for FMAC_YBUFCFG register *****************/
5390 #define FMAC_YBUFCFG_Y_BASE_Pos (0U)
5391 #define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */
5392 #define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */
5393 #define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8U)
5394 #define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */
5395 #define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */
5396 #define FMAC_YBUFCFG_EMPTY_WM_Pos (24U)
5397 #define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */
5398 #define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */
5399 /****************** Bit definition for FMAC_PARAM register ******************/
5400 #define FMAC_PARAM_P_Pos (0U)
5401 #define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */
5402 #define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */
5403 #define FMAC_PARAM_Q_Pos (8U)
5404 #define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */
5405 #define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */
5406 #define FMAC_PARAM_R_Pos (16U)
5407 #define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */
5408 #define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */
5409 #define FMAC_PARAM_FUNC_Pos (24U)
5410 #define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */
5411 #define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */
5412 #define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */
5413 #define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */
5414 #define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */
5415 #define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */
5416 #define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */
5417 #define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */
5418 #define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */
5419 #define FMAC_PARAM_START_Pos (31U)
5420 #define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */
5421 #define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */
5422 /******************** Bit definition for FMAC_CR register *******************/
5423 #define FMAC_CR_RIEN_Pos (0U)
5424 #define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */
5425 #define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */
5426 #define FMAC_CR_WIEN_Pos (1U)
5427 #define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */
5428 #define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */
5429 #define FMAC_CR_OVFLIEN_Pos (2U)
5430 #define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */
5431 #define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */
5432 #define FMAC_CR_UNFLIEN_Pos (3U)
5433 #define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */
5434 #define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */
5435 #define FMAC_CR_SATIEN_Pos (4U)
5436 #define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */
5437 #define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */
5438 #define FMAC_CR_DMAREN_Pos (8U)
5439 #define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */
5440 #define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */
5441 #define FMAC_CR_DMAWEN_Pos (9U)
5442 #define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */
5443 #define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */
5444 #define FMAC_CR_CLIPEN_Pos (15U)
5445 #define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */
5446 #define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */
5447 #define FMAC_CR_RESET_Pos (16U)
5448 #define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */
5449 #define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */
5450 /******************* Bit definition for FMAC_SR register ********************/
5451 #define FMAC_SR_YEMPTY_Pos (0U)
5452 #define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */
5453 #define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */
5454 #define FMAC_SR_X1FULL_Pos (1U)
5455 #define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */
5456 #define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */
5457 #define FMAC_SR_OVFL_Pos (8U)
5458 #define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */
5459 #define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */
5460 #define FMAC_SR_UNFL_Pos (9U)
5461 #define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */
5462 #define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */
5463 #define FMAC_SR_SAT_Pos (10U)
5464 #define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */
5465 #define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */
5466 /****************** Bit definition for FMAC_WDATA register ******************/
5467 #define FMAC_WDATA_WDATA_Pos (0U)
5468 #define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */
5469 #define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */
5470 /****************** Bit definition for FMACX_RDATA register *****************/
5471 #define FMAC_RDATA_RDATA_Pos (0U)
5472 #define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */
5473 #define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */
5474
5475 /******************************************************************************/
5476 /* */
5477 /* Flexible Memory Controller */
5478 /* */
5479 /******************************************************************************/
5480 /****************** Bit definition for FMC_BCR1 register *******************/
5481 #define FMC_BCR1_CCLKEN_Pos (20U)
5482 #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
5483 #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
5484 #define FMC_BCR1_WFDIS_Pos (21U)
5485 #define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
5486 #define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
5487
5488 /****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
5489 #define FMC_BCRx_MBKEN_Pos (0U)
5490 #define FMC_BCRx_MBKEN_Msk (0x1UL << FMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */
5491 #define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk /*!<Memory bank enable bit */
5492 #define FMC_BCRx_MUXEN_Pos (1U)
5493 #define FMC_BCRx_MUXEN_Msk (0x1UL << FMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */
5494 #define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk /*!<Address/data multiplexing enable bit */
5495
5496 #define FMC_BCRx_MTYP_Pos (2U)
5497 #define FMC_BCRx_MTYP_Msk (0x3UL << FMC_BCRx_MTYP_Pos) /*!< 0x0000000C */
5498 #define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
5499 #define FMC_BCRx_MTYP_0 (0x1UL << FMC_BCRx_MTYP_Pos) /*!< 0x00000004 */
5500 #define FMC_BCRx_MTYP_1 (0x2UL << FMC_BCRx_MTYP_Pos) /*!< 0x00000008 */
5501
5502 #define FMC_BCRx_MWID_Pos (4U)
5503 #define FMC_BCRx_MWID_Msk (0x3UL << FMC_BCRx_MWID_Pos) /*!< 0x00000030 */
5504 #define FMC_BCRx_MWID FMC_BCRx_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
5505 #define FMC_BCRx_MWID_0 (0x1UL << FMC_BCRx_MWID_Pos) /*!< 0x00000010 */
5506 #define FMC_BCRx_MWID_1 (0x2UL << FMC_BCRx_MWID_Pos) /*!< 0x00000020 */
5507
5508 #define FMC_BCRx_FACCEN_Pos (6U)
5509 #define FMC_BCRx_FACCEN_Msk (0x1UL << FMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */
5510 #define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk /*!<Flash access enable */
5511 #define FMC_BCRx_BURSTEN_Pos (8U)
5512 #define FMC_BCRx_BURSTEN_Msk (0x1UL << FMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */
5513 #define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk /*!<Burst enable bit */
5514 #define FMC_BCRx_WAITPOL_Pos (9U)
5515 #define FMC_BCRx_WAITPOL_Msk (0x1UL << FMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */
5516 #define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk /*!<Wait signal polarity bit */
5517 #define FMC_BCRx_WAITCFG_Pos (11U)
5518 #define FMC_BCRx_WAITCFG_Msk (0x1UL << FMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */
5519 #define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk /*!<Wait timing configuration */
5520 #define FMC_BCRx_WREN_Pos (12U)
5521 #define FMC_BCRx_WREN_Msk (0x1UL << FMC_BCRx_WREN_Pos) /*!< 0x00001000 */
5522 #define FMC_BCRx_WREN FMC_BCRx_WREN_Msk /*!<Write enable bit */
5523 #define FMC_BCRx_WAITEN_Pos (13U)
5524 #define FMC_BCRx_WAITEN_Msk (0x1UL << FMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */
5525 #define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk /*!<Wait enable bit */
5526 #define FMC_BCRx_EXTMOD_Pos (14U)
5527 #define FMC_BCRx_EXTMOD_Msk (0x1UL << FMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */
5528 #define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk /*!<Extended mode enable */
5529 #define FMC_BCRx_ASYNCWAIT_Pos (15U)
5530 #define FMC_BCRx_ASYNCWAIT_Msk (0x1UL << FMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */
5531 #define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk /*!<Asynchronous wait */
5532
5533 #define FMC_BCRx_CPSIZE_Pos (16U)
5534 #define FMC_BCRx_CPSIZE_Msk (0x7UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00070000 */
5535 #define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk /*!<CRAM page size */
5536 #define FMC_BCRx_CPSIZE_0 (0x1UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00010000 */
5537 #define FMC_BCRx_CPSIZE_1 (0x2UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00020000 */
5538 #define FMC_BCRx_CPSIZE_2 (0x4UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00040000 */
5539
5540 #define FMC_BCRx_CBURSTRW_Pos (19U)
5541 #define FMC_BCRx_CBURSTRW_Msk (0x1UL << FMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */
5542 #define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk /*!<Write burst enable */
5543
5544 #define FMC_BCRx_NBLSET_Pos (22U)
5545 #define FMC_BCRx_NBLSET_Msk (0x3UL << FMC_BCRx_NBLSET_Pos) /*!< 0x00C00000 */
5546 #define FMC_BCRx_NBLSET FMC_BCRx_NBLSET_Msk /*!<Byte lane (NBL) setup */
5547 #define FMC_BCRx_NBLSET_0 (0x1UL << FMC_BCRx_NBLSET_Pos) /*!< 0x00500000 */
5548 #define FMC_BCRx_NBLSET_1 (0x2UL << FMC_BCRx_NBLSET_Pos) /*!< 0x00800000 */
5549
5550 /****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
5551 #define FMC_BTRx_ADDSET_Pos (0U)
5552 #define FMC_BTRx_ADDSET_Msk (0xFUL << FMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */
5553 #define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
5554 #define FMC_BTRx_ADDSET_0 (0x1UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */
5555 #define FMC_BTRx_ADDSET_1 (0x2UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */
5556 #define FMC_BTRx_ADDSET_2 (0x4UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */
5557 #define FMC_BTRx_ADDSET_3 (0x8UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
5558
5559 #define FMC_BTRx_ADDHLD_Pos (4U)
5560 #define FMC_BTRx_ADDHLD_Msk (0xFUL << FMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
5561 #define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
5562 #define FMC_BTRx_ADDHLD_0 (0x1UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
5563 #define FMC_BTRx_ADDHLD_1 (0x2UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
5564 #define FMC_BTRx_ADDHLD_2 (0x4UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
5565 #define FMC_BTRx_ADDHLD_3 (0x8UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
5566
5567 #define FMC_BTRx_DATAST_Pos (8U)
5568 #define FMC_BTRx_DATAST_Msk (0xFFUL << FMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */
5569 #define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
5570 #define FMC_BTRx_DATAST_0 (0x01UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000100 */
5571 #define FMC_BTRx_DATAST_1 (0x02UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000200 */
5572 #define FMC_BTRx_DATAST_2 (0x04UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000400 */
5573 #define FMC_BTRx_DATAST_3 (0x08UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000800 */
5574 #define FMC_BTRx_DATAST_4 (0x10UL << FMC_BTRx_DATAST_Pos) /*!< 0x00001000 */
5575 #define FMC_BTRx_DATAST_5 (0x20UL << FMC_BTRx_DATAST_Pos) /*!< 0x00002000 */
5576 #define FMC_BTRx_DATAST_6 (0x40UL << FMC_BTRx_DATAST_Pos) /*!< 0x00004000 */
5577 #define FMC_BTRx_DATAST_7 (0x80UL << FMC_BTRx_DATAST_Pos) /*!< 0x00008000 */
5578
5579 #define FMC_BTRx_BUSTURN_Pos (16U)
5580 #define FMC_BTRx_BUSTURN_Msk (0xFUL << FMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */
5581 #define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
5582 #define FMC_BTRx_BUSTURN_0 (0x1UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */
5583 #define FMC_BTRx_BUSTURN_1 (0x2UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */
5584 #define FMC_BTRx_BUSTURN_2 (0x4UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */
5585 #define FMC_BTRx_BUSTURN_3 (0x8UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */
5586
5587 #define FMC_BTRx_CLKDIV_Pos (20U)
5588 #define FMC_BTRx_CLKDIV_Msk (0xFUL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */
5589 #define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
5590 #define FMC_BTRx_CLKDIV_0 (0x1UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */
5591 #define FMC_BTRx_CLKDIV_1 (0x2UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */
5592 #define FMC_BTRx_CLKDIV_2 (0x4UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */
5593 #define FMC_BTRx_CLKDIV_3 (0x8UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */
5594
5595 #define FMC_BTRx_DATLAT_Pos (24U)
5596 #define FMC_BTRx_DATLAT_Msk (0xFUL << FMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */
5597 #define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk /*!<DATLAT[3:0] bits (Data latency) */
5598 #define FMC_BTRx_DATLAT_0 (0x1UL << FMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */
5599 #define FMC_BTRx_DATLAT_1 (0x2UL << FMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */
5600 #define FMC_BTRx_DATLAT_2 (0x4UL << FMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */
5601 #define FMC_BTRx_DATLAT_3 (0x8UL << FMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */
5602
5603 #define FMC_BTRx_ACCMOD_Pos (28U)
5604 #define FMC_BTRx_ACCMOD_Msk (0x3UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */
5605 #define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
5606 #define FMC_BTRx_ACCMOD_0 (0x1UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */
5607 #define FMC_BTRx_ACCMOD_1 (0x2UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */
5608
5609 #define FMC_BTRx_DATAHLD_Pos (30U)
5610 #define FMC_BTRx_DATAHLD_Msk (0x3UL << FMC_BTRx_DATAHLD_Pos) /*!< 0xC0000000 */
5611 #define FMC_BTRx_DATAHLD FMC_BTRx_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data hold phase duration) */
5612 #define FMC_BTRx_DATAHLD_0 (0x1UL << FMC_BTRx_DATAHLD_Pos) /*!< 0x40000000 */
5613 #define FMC_BTRx_DATAHLD_1 (0x2UL << FMC_BTRx_DATAHLD_Pos) /*!< 0x80000000 */
5614
5615 /****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
5616 #define FMC_BWTRx_ADDSET_Pos (0U)
5617 #define FMC_BWTRx_ADDSET_Msk (0xFUL << FMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */
5618 #define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
5619 #define FMC_BWTRx_ADDSET_0 (0x1UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */
5620 #define FMC_BWTRx_ADDSET_1 (0x2UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */
5621 #define FMC_BWTRx_ADDSET_2 (0x4UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */
5622 #define FMC_BWTRx_ADDSET_3 (0x8UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */
5623
5624 #define FMC_BWTRx_ADDHLD_Pos (4U)
5625 #define FMC_BWTRx_ADDHLD_Msk (0xFUL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */
5626 #define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
5627 #define FMC_BWTRx_ADDHLD_0 (0x1UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */
5628 #define FMC_BWTRx_ADDHLD_1 (0x2UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */
5629 #define FMC_BWTRx_ADDHLD_2 (0x4UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */
5630 #define FMC_BWTRx_ADDHLD_3 (0x8UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */
5631
5632 #define FMC_BWTRx_DATAST_Pos (8U)
5633 #define FMC_BWTRx_DATAST_Msk (0xFFUL << FMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */
5634 #define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
5635 #define FMC_BWTRx_DATAST_0 (0x01UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */
5636 #define FMC_BWTRx_DATAST_1 (0x02UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */
5637 #define FMC_BWTRx_DATAST_2 (0x04UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */
5638 #define FMC_BWTRx_DATAST_3 (0x08UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */
5639 #define FMC_BWTRx_DATAST_4 (0x10UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */
5640 #define FMC_BWTRx_DATAST_5 (0x20UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */
5641 #define FMC_BWTRx_DATAST_6 (0x40UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */
5642 #define FMC_BWTRx_DATAST_7 (0x80UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */
5643
5644 #define FMC_BWTRx_BUSTURN_Pos (16U)
5645 #define FMC_BWTRx_BUSTURN_Msk (0xFUL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x000F0000 */
5646 #define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
5647 #define FMC_BWTRx_BUSTURN_0 (0x1UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00010000 */
5648 #define FMC_BWTRx_BUSTURN_1 (0x2UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00020000 */
5649 #define FMC_BWTRx_BUSTURN_2 (0x4UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00040000 */
5650 #define FMC_BWTRx_BUSTURN_3 (0x8UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00080000 */
5651
5652 #define FMC_BWTRx_ACCMOD_Pos (28U)
5653 #define FMC_BWTRx_ACCMOD_Msk (0x3UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */
5654 #define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
5655 #define FMC_BWTRx_ACCMOD_0 (0x1UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */
5656 #define FMC_BWTRx_ACCMOD_1 (0x2UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */
5657
5658 #define FMC_BWTRx_DATAHLD_Pos (30U)
5659 #define FMC_BWTRx_DATAHLD_Msk (0x3UL << FMC_BWTRx_DATAHLD_Pos) /*!< 0xC0000000 */
5660 #define FMC_BWTRx_DATAHLD FMC_BWTRx_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data hold phase duration) */
5661 #define FMC_BWTRx_DATAHLD_0 (0x1UL << FMC_BWTRx_DATAHLD_Pos) /*!< 0x40000000 */
5662 #define FMC_BWTRx_DATAHLD_1 (0x2UL << FMC_BWTRx_DATAHLD_Pos) /*!< 0x80000000 */
5663
5664 /****************** Bit definition for FMC_PCSCNTR register ******************/
5665 #define FMC_PCSCNTR_CSCOUNT_Pos (0U)
5666 #define FMC_PCSCNTR_CSCOUNT_Msk (0xFFFFUL << FMC_PCSCNTR_CSCOUNT_Pos) /*!< 0x0000FFFF */
5667 #define FMC_PCSCNTR_CSCOUNT FMC_PCSCNTR_CSCOUNT_Msk /*!<CSCOUNT[15:0] bits (Chip select counter) */
5668
5669 #define FMC_PCSCNTR_CNTB1EN_Pos (16U)
5670 #define FMC_PCSCNTR_CNTB1EN_Msk (0x1UL << FMC_PCSCNTR_CNTB1EN_Pos) /*!< 0x00010000 */
5671 #define FMC_PCSCNTR_CNTB1EN FMC_PCSCNTR_CNTB1EN_Msk /*!<Counter PSRAM/NOR Bank1_1 enable */
5672
5673 #define FMC_PCSCNTR_CNTB2EN_Pos (17U)
5674 #define FMC_PCSCNTR_CNTB2EN_Msk (0x1UL << FMC_PCSCNTR_CNTB2EN_Pos) /*!< 0x00020000 */
5675 #define FMC_PCSCNTR_CNTB2EN FMC_PCSCNTR_CNTB2EN_Msk /*!<Counter PSRAM/NOR Bank1_2 enable */
5676
5677 #define FMC_PCSCNTR_CNTB3EN_Pos (18U)
5678 #define FMC_PCSCNTR_CNTB3EN_Msk (0x1UL << FMC_PCSCNTR_CNTB3EN_Pos) /*!< 0x00040000 */
5679 #define FMC_PCSCNTR_CNTB3EN FMC_PCSCNTR_CNTB3EN_Msk /*!<Counter PSRAM/NOR Bank1_3 enable */
5680
5681 #define FMC_PCSCNTR_CNTB4EN_Pos (19U)
5682 #define FMC_PCSCNTR_CNTB4EN_Msk (0x1UL << FMC_PCSCNTR_CNTB4EN_Pos) /*!< 0x00080000 */
5683 #define FMC_PCSCNTR_CNTB4EN FMC_PCSCNTR_CNTB4EN_Msk /*!<Counter PSRAM/NOR Bank1_4 enable */
5684
5685 /****************** Bit definition for FMC_PCR register ********************/
5686 #define FMC_PCR_PWAITEN_Pos (1U)
5687 #define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
5688 #define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
5689 #define FMC_PCR_PBKEN_Pos (2U)
5690 #define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
5691 #define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<NAND Flash memory bank enable bit */
5692 #define FMC_PCR_PTYP_Pos (3U)
5693 #define FMC_PCR_PTYP_Msk (0x1UL << FMC_PCR_PTYP_Pos) /*!< 0x00000008 */
5694 #define FMC_PCR_PTYP FMC_PCR_PTYP_Msk /*!<Memory type */
5695
5696 #define FMC_PCR_PWID_Pos (4U)
5697 #define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
5698 #define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
5699 #define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
5700 #define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
5701
5702 #define FMC_PCR_ECCEN_Pos (6U)
5703 #define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
5704 #define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
5705
5706 #define FMC_PCR_TCLR_Pos (9U)
5707 #define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
5708 #define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
5709 #define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
5710 #define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
5711 #define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
5712 #define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
5713
5714 #define FMC_PCR_TAR_Pos (13U)
5715 #define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
5716 #define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
5717 #define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
5718 #define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
5719 #define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
5720 #define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
5721
5722 #define FMC_PCR_ECCPS_Pos (17U)
5723 #define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
5724 #define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
5725 #define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
5726 #define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
5727 #define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
5728
5729 /******************* Bit definition for FMC_SR register ********************/
5730 #define FMC_SR_IRS_Pos (0U)
5731 #define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos) /*!< 0x00000001 */
5732 #define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
5733 #define FMC_SR_ILS_Pos (1U)
5734 #define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos) /*!< 0x00000002 */
5735 #define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
5736 #define FMC_SR_IFS_Pos (2U)
5737 #define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos) /*!< 0x00000004 */
5738 #define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
5739 #define FMC_SR_IREN_Pos (3U)
5740 #define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos) /*!< 0x00000008 */
5741 #define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
5742 #define FMC_SR_ILEN_Pos (4U)
5743 #define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
5744 #define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
5745 #define FMC_SR_IFEN_Pos (5U)
5746 #define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
5747 #define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
5748 #define FMC_SR_FEMPT_Pos (6U)
5749 #define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
5750 #define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
5751
5752 /****************** Bit definition for FMC_PMEM register ******************/
5753 #define FMC_PMEM_MEMSET_Pos (0U)
5754 #define FMC_PMEM_MEMSET_Msk (0xFFUL << FMC_PMEM_MEMSET_Pos) /*!< 0x000000FF */
5755 #define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk /*!<MEMSET[7:0] bits (Common memory setup time) */
5756 #define FMC_PMEM_MEMSET_0 (0x01UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000001 */
5757 #define FMC_PMEM_MEMSET_1 (0x02UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000002 */
5758 #define FMC_PMEM_MEMSET_2 (0x04UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000004 */
5759 #define FMC_PMEM_MEMSET_3 (0x08UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000008 */
5760 #define FMC_PMEM_MEMSET_4 (0x10UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000010 */
5761 #define FMC_PMEM_MEMSET_5 (0x20UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000020 */
5762 #define FMC_PMEM_MEMSET_6 (0x40UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000040 */
5763 #define FMC_PMEM_MEMSET_7 (0x80UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000080 */
5764
5765 #define FMC_PMEM_MEMWAIT_Pos (8U)
5766 #define FMC_PMEM_MEMWAIT_Msk (0xFFUL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x0000FF00 */
5767 #define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk /*!<MEMWAIT[7:0] bits (Common memory wait time) */
5768 #define FMC_PMEM_MEMWAIT_0 (0x01UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000100 */
5769 #define FMC_PMEM_MEMWAIT_1 (0x02UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000200 */
5770 #define FMC_PMEM_MEMWAIT_2 (0x04UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000400 */
5771 #define FMC_PMEM_MEMWAIT_3 (0x08UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000800 */
5772 #define FMC_PMEM_MEMWAIT_4 (0x10UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00001000 */
5773 #define FMC_PMEM_MEMWAIT_5 (0x20UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00002000 */
5774 #define FMC_PMEM_MEMWAIT_6 (0x40UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00004000 */
5775 #define FMC_PMEM_MEMWAIT_7 (0x80UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00008000 */
5776
5777 #define FMC_PMEM_MEMHOLD_Pos (16U)
5778 #define FMC_PMEM_MEMHOLD_Msk (0xFFUL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00FF0000 */
5779 #define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk /*!<MEMHOLD[7:0] bits (Common memory hold time) */
5780 #define FMC_PMEM_MEMHOLD_0 (0x01UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00010000 */
5781 #define FMC_PMEM_MEMHOLD_1 (0x02UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00020000 */
5782 #define FMC_PMEM_MEMHOLD_2 (0x04UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00040000 */
5783 #define FMC_PMEM_MEMHOLD_3 (0x08UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00080000 */
5784 #define FMC_PMEM_MEMHOLD_4 (0x10UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00100000 */
5785 #define FMC_PMEM_MEMHOLD_5 (0x20UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00200000 */
5786 #define FMC_PMEM_MEMHOLD_6 (0x40UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00400000 */
5787 #define FMC_PMEM_MEMHOLD_7 (0x80UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00800000 */
5788
5789 #define FMC_PMEM_MEMHIZ_Pos (24U)
5790 #define FMC_PMEM_MEMHIZ_Msk (0xFFUL << FMC_PMEM_MEMHIZ_Pos) /*!< 0xFF000000 */
5791 #define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
5792 #define FMC_PMEM_MEMHIZ_0 (0x01UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x01000000 */
5793 #define FMC_PMEM_MEMHIZ_1 (0x02UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x02000000 */
5794 #define FMC_PMEM_MEMHIZ_2 (0x04UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x04000000 */
5795 #define FMC_PMEM_MEMHIZ_3 (0x08UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x08000000 */
5796 #define FMC_PMEM_MEMHIZ_4 (0x10UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x10000000 */
5797 #define FMC_PMEM_MEMHIZ_5 (0x20UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x20000000 */
5798 #define FMC_PMEM_MEMHIZ_6 (0x40UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x40000000 */
5799 #define FMC_PMEM_MEMHIZ_7 (0x80UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x80000000 */
5800
5801 /****************** Bit definition for FMC_PATT register *******************/
5802 #define FMC_PATT_ATTSET_Pos (0U)
5803 #define FMC_PATT_ATTSET_Msk (0xFFUL << FMC_PATT_ATTSET_Pos) /*!< 0x000000FF */
5804 #define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk /*!<ATTSET[7:0] bits (Attribute memory setup time) */
5805 #define FMC_PATT_ATTSET_0 (0x01UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000001 */
5806 #define FMC_PATT_ATTSET_1 (0x02UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000002 */
5807 #define FMC_PATT_ATTSET_2 (0x04UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000004 */
5808 #define FMC_PATT_ATTSET_3 (0x08UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000008 */
5809 #define FMC_PATT_ATTSET_4 (0x10UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000010 */
5810 #define FMC_PATT_ATTSET_5 (0x20UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000020 */
5811 #define FMC_PATT_ATTSET_6 (0x40UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000040 */
5812 #define FMC_PATT_ATTSET_7 (0x80UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000080 */
5813
5814 #define FMC_PATT_ATTWAIT_Pos (8U)
5815 #define FMC_PATT_ATTWAIT_Msk (0xFFUL << FMC_PATT_ATTWAIT_Pos) /*!< 0x0000FF00 */
5816 #define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
5817 #define FMC_PATT_ATTWAIT_0 (0x01UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000100 */
5818 #define FMC_PATT_ATTWAIT_1 (0x02UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000200 */
5819 #define FMC_PATT_ATTWAIT_2 (0x04UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000400 */
5820 #define FMC_PATT_ATTWAIT_3 (0x08UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000800 */
5821 #define FMC_PATT_ATTWAIT_4 (0x10UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00001000 */
5822 #define FMC_PATT_ATTWAIT_5 (0x20UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00002000 */
5823 #define FMC_PATT_ATTWAIT_6 (0x40UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00004000 */
5824 #define FMC_PATT_ATTWAIT_7 (0x80UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00008000 */
5825
5826 #define FMC_PATT_ATTHOLD_Pos (16U)
5827 #define FMC_PATT_ATTHOLD_Msk (0xFFUL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00FF0000 */
5828 #define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
5829 #define FMC_PATT_ATTHOLD_0 (0x01UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00010000 */
5830 #define FMC_PATT_ATTHOLD_1 (0x02UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00020000 */
5831 #define FMC_PATT_ATTHOLD_2 (0x04UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00040000 */
5832 #define FMC_PATT_ATTHOLD_3 (0x08UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00080000 */
5833 #define FMC_PATT_ATTHOLD_4 (0x10UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00100000 */
5834 #define FMC_PATT_ATTHOLD_5 (0x20UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00200000 */
5835 #define FMC_PATT_ATTHOLD_6 (0x40UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00400000 */
5836 #define FMC_PATT_ATTHOLD_7 (0x80UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00800000 */
5837
5838 #define FMC_PATT_ATTHIZ_Pos (24U)
5839 #define FMC_PATT_ATTHIZ_Msk (0xFFUL << FMC_PATT_ATTHIZ_Pos) /*!< 0xFF000000 */
5840 #define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
5841 #define FMC_PATT_ATTHIZ_0 (0x01UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x01000000 */
5842 #define FMC_PATT_ATTHIZ_1 (0x02UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x02000000 */
5843 #define FMC_PATT_ATTHIZ_2 (0x04UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x04000000 */
5844 #define FMC_PATT_ATTHIZ_3 (0x08UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x08000000 */
5845 #define FMC_PATT_ATTHIZ_4 (0x10UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x10000000 */
5846 #define FMC_PATT_ATTHIZ_5 (0x20UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x20000000 */
5847 #define FMC_PATT_ATTHIZ_6 (0x40UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x40000000 */
5848 #define FMC_PATT_ATTHIZ_7 (0x80UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x80000000 */
5849
5850 /****************** Bit definition for FMC_ECCR register *******************/
5851 #define FMC_ECCR_ECC_Pos (0U)
5852 #define FMC_ECCR_ECC_Msk (0xFFFFFFFFUL << FMC_ECCR_ECC_Pos) /*!< 0xFFFFFFFF */
5853 #define FMC_ECCR_ECC FMC_ECCR_ECC_Msk /*!<ECC result */
5854
5855 /******************************************************************************/
5856 /* */
5857 /* General Purpose IOs (GPIO) */
5858 /* */
5859 /******************************************************************************/
5860 /****************** Bits definition for GPIO_MODER register *****************/
5861 #define GPIO_MODER_MODE0_Pos (0U)
5862 #define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
5863 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
5864 #define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
5865 #define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
5866 #define GPIO_MODER_MODE1_Pos (2U)
5867 #define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
5868 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
5869 #define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
5870 #define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
5871 #define GPIO_MODER_MODE2_Pos (4U)
5872 #define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
5873 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
5874 #define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
5875 #define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
5876 #define GPIO_MODER_MODE3_Pos (6U)
5877 #define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
5878 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
5879 #define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
5880 #define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
5881 #define GPIO_MODER_MODE4_Pos (8U)
5882 #define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
5883 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
5884 #define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
5885 #define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
5886 #define GPIO_MODER_MODE5_Pos (10U)
5887 #define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
5888 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
5889 #define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
5890 #define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
5891 #define GPIO_MODER_MODE6_Pos (12U)
5892 #define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
5893 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
5894 #define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
5895 #define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
5896 #define GPIO_MODER_MODE7_Pos (14U)
5897 #define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
5898 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
5899 #define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
5900 #define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
5901 #define GPIO_MODER_MODE8_Pos (16U)
5902 #define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
5903 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
5904 #define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
5905 #define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
5906 #define GPIO_MODER_MODE9_Pos (18U)
5907 #define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
5908 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
5909 #define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
5910 #define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
5911 #define GPIO_MODER_MODE10_Pos (20U)
5912 #define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
5913 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
5914 #define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
5915 #define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
5916 #define GPIO_MODER_MODE11_Pos (22U)
5917 #define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
5918 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
5919 #define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
5920 #define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
5921 #define GPIO_MODER_MODE12_Pos (24U)
5922 #define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
5923 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
5924 #define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
5925 #define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
5926 #define GPIO_MODER_MODE13_Pos (26U)
5927 #define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
5928 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
5929 #define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
5930 #define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
5931 #define GPIO_MODER_MODE14_Pos (28U)
5932 #define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
5933 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
5934 #define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
5935 #define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
5936 #define GPIO_MODER_MODE15_Pos (30U)
5937 #define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
5938 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
5939 #define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
5940 #define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
5941
5942 /* Legacy defines */
5943 #define GPIO_MODER_MODER0 GPIO_MODER_MODE0
5944 #define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
5945 #define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
5946 #define GPIO_MODER_MODER1 GPIO_MODER_MODE1
5947 #define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
5948 #define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
5949 #define GPIO_MODER_MODER2 GPIO_MODER_MODE2
5950 #define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
5951 #define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
5952 #define GPIO_MODER_MODER3 GPIO_MODER_MODE3
5953 #define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
5954 #define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
5955 #define GPIO_MODER_MODER4 GPIO_MODER_MODE4
5956 #define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
5957 #define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
5958 #define GPIO_MODER_MODER5 GPIO_MODER_MODE5
5959 #define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
5960 #define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
5961 #define GPIO_MODER_MODER6 GPIO_MODER_MODE6
5962 #define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
5963 #define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
5964 #define GPIO_MODER_MODER7 GPIO_MODER_MODE7
5965 #define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
5966 #define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
5967 #define GPIO_MODER_MODER8 GPIO_MODER_MODE8
5968 #define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
5969 #define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
5970 #define GPIO_MODER_MODER9 GPIO_MODER_MODE9
5971 #define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
5972 #define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
5973 #define GPIO_MODER_MODER10 GPIO_MODER_MODE10
5974 #define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
5975 #define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
5976 #define GPIO_MODER_MODER11 GPIO_MODER_MODE11
5977 #define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
5978 #define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
5979 #define GPIO_MODER_MODER12 GPIO_MODER_MODE12
5980 #define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
5981 #define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
5982 #define GPIO_MODER_MODER13 GPIO_MODER_MODE13
5983 #define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
5984 #define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
5985 #define GPIO_MODER_MODER14 GPIO_MODER_MODE14
5986 #define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
5987 #define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
5988 #define GPIO_MODER_MODER15 GPIO_MODER_MODE15
5989 #define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
5990 #define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
5991
5992 /****************** Bits definition for GPIO_OTYPER register ****************/
5993 #define GPIO_OTYPER_OT0_Pos (0U)
5994 #define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
5995 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
5996 #define GPIO_OTYPER_OT1_Pos (1U)
5997 #define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
5998 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
5999 #define GPIO_OTYPER_OT2_Pos (2U)
6000 #define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
6001 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
6002 #define GPIO_OTYPER_OT3_Pos (3U)
6003 #define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
6004 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
6005 #define GPIO_OTYPER_OT4_Pos (4U)
6006 #define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
6007 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
6008 #define GPIO_OTYPER_OT5_Pos (5U)
6009 #define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
6010 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
6011 #define GPIO_OTYPER_OT6_Pos (6U)
6012 #define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
6013 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
6014 #define GPIO_OTYPER_OT7_Pos (7U)
6015 #define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
6016 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
6017 #define GPIO_OTYPER_OT8_Pos (8U)
6018 #define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
6019 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
6020 #define GPIO_OTYPER_OT9_Pos (9U)
6021 #define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
6022 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
6023 #define GPIO_OTYPER_OT10_Pos (10U)
6024 #define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
6025 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
6026 #define GPIO_OTYPER_OT11_Pos (11U)
6027 #define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
6028 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
6029 #define GPIO_OTYPER_OT12_Pos (12U)
6030 #define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
6031 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
6032 #define GPIO_OTYPER_OT13_Pos (13U)
6033 #define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
6034 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
6035 #define GPIO_OTYPER_OT14_Pos (14U)
6036 #define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
6037 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
6038 #define GPIO_OTYPER_OT15_Pos (15U)
6039 #define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
6040 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
6041
6042 /* Legacy defines */
6043 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
6044 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
6045 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
6046 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
6047 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
6048 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
6049 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
6050 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
6051 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
6052 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
6053 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
6054 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
6055 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
6056 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
6057 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
6058 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
6059
6060 /****************** Bits definition for GPIO_OSPEEDR register ***************/
6061 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
6062 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
6063 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
6064 #define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
6065 #define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
6066 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
6067 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
6068 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
6069 #define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
6070 #define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
6071 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
6072 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
6073 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
6074 #define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
6075 #define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
6076 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
6077 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
6078 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
6079 #define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
6080 #define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
6081 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
6082 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
6083 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
6084 #define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
6085 #define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
6086 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
6087 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
6088 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
6089 #define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
6090 #define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
6091 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
6092 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
6093 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
6094 #define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
6095 #define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
6096 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
6097 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
6098 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
6099 #define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
6100 #define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
6101 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
6102 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
6103 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
6104 #define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
6105 #define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
6106 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
6107 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
6108 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
6109 #define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
6110 #define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
6111 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
6112 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
6113 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
6114 #define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
6115 #define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
6116 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
6117 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
6118 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
6119 #define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
6120 #define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
6121 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
6122 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
6123 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
6124 #define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
6125 #define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
6126 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
6127 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
6128 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
6129 #define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
6130 #define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
6131 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
6132 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
6133 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
6134 #define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
6135 #define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
6136 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
6137 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
6138 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
6139 #define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
6140 #define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
6141
6142 /* Legacy defines */
6143 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
6144 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
6145 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
6146 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
6147 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
6148 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
6149 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
6150 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
6151 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
6152 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
6153 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
6154 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
6155 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
6156 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
6157 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
6158 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
6159 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
6160 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
6161 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
6162 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
6163 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
6164 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
6165 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
6166 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
6167 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
6168 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
6169 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
6170 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
6171 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
6172 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
6173 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
6174 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
6175 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
6176 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
6177 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
6178 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
6179 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
6180 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
6181 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
6182 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
6183 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
6184 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
6185 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
6186 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
6187 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
6188 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
6189 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
6190 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
6191
6192 /****************** Bits definition for GPIO_PUPDR register *****************/
6193 #define GPIO_PUPDR_PUPD0_Pos (0U)
6194 #define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
6195 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
6196 #define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
6197 #define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
6198 #define GPIO_PUPDR_PUPD1_Pos (2U)
6199 #define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
6200 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
6201 #define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
6202 #define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
6203 #define GPIO_PUPDR_PUPD2_Pos (4U)
6204 #define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
6205 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
6206 #define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
6207 #define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
6208 #define GPIO_PUPDR_PUPD3_Pos (6U)
6209 #define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
6210 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
6211 #define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
6212 #define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
6213 #define GPIO_PUPDR_PUPD4_Pos (8U)
6214 #define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
6215 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
6216 #define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
6217 #define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
6218 #define GPIO_PUPDR_PUPD5_Pos (10U)
6219 #define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
6220 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
6221 #define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
6222 #define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
6223 #define GPIO_PUPDR_PUPD6_Pos (12U)
6224 #define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
6225 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
6226 #define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
6227 #define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
6228 #define GPIO_PUPDR_PUPD7_Pos (14U)
6229 #define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
6230 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
6231 #define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
6232 #define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
6233 #define GPIO_PUPDR_PUPD8_Pos (16U)
6234 #define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
6235 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
6236 #define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
6237 #define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
6238 #define GPIO_PUPDR_PUPD9_Pos (18U)
6239 #define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
6240 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
6241 #define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
6242 #define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
6243 #define GPIO_PUPDR_PUPD10_Pos (20U)
6244 #define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
6245 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
6246 #define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
6247 #define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
6248 #define GPIO_PUPDR_PUPD11_Pos (22U)
6249 #define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
6250 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
6251 #define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
6252 #define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
6253 #define GPIO_PUPDR_PUPD12_Pos (24U)
6254 #define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
6255 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
6256 #define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
6257 #define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
6258 #define GPIO_PUPDR_PUPD13_Pos (26U)
6259 #define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
6260 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
6261 #define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
6262 #define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
6263 #define GPIO_PUPDR_PUPD14_Pos (28U)
6264 #define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
6265 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
6266 #define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
6267 #define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
6268 #define GPIO_PUPDR_PUPD15_Pos (30U)
6269 #define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
6270 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
6271 #define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
6272 #define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
6273
6274 /* Legacy defines */
6275 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
6276 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
6277 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
6278 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
6279 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
6280 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
6281 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
6282 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
6283 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
6284 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
6285 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
6286 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
6287 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
6288 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
6289 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
6290 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
6291 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
6292 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
6293 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
6294 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
6295 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
6296 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
6297 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
6298 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
6299 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
6300 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
6301 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
6302 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
6303 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
6304 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
6305 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
6306 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
6307 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
6308 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
6309 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
6310 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
6311 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
6312 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
6313 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
6314 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
6315 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
6316 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
6317 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
6318 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
6319 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
6320 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
6321 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
6322 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
6323
6324 /****************** Bits definition for GPIO_IDR register *******************/
6325 #define GPIO_IDR_ID0_Pos (0U)
6326 #define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
6327 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
6328 #define GPIO_IDR_ID1_Pos (1U)
6329 #define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
6330 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
6331 #define GPIO_IDR_ID2_Pos (2U)
6332 #define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
6333 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
6334 #define GPIO_IDR_ID3_Pos (3U)
6335 #define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
6336 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
6337 #define GPIO_IDR_ID4_Pos (4U)
6338 #define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
6339 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
6340 #define GPIO_IDR_ID5_Pos (5U)
6341 #define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
6342 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
6343 #define GPIO_IDR_ID6_Pos (6U)
6344 #define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
6345 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
6346 #define GPIO_IDR_ID7_Pos (7U)
6347 #define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
6348 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
6349 #define GPIO_IDR_ID8_Pos (8U)
6350 #define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
6351 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
6352 #define GPIO_IDR_ID9_Pos (9U)
6353 #define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
6354 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
6355 #define GPIO_IDR_ID10_Pos (10U)
6356 #define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
6357 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
6358 #define GPIO_IDR_ID11_Pos (11U)
6359 #define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
6360 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
6361 #define GPIO_IDR_ID12_Pos (12U)
6362 #define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
6363 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
6364 #define GPIO_IDR_ID13_Pos (13U)
6365 #define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
6366 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
6367 #define GPIO_IDR_ID14_Pos (14U)
6368 #define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
6369 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
6370 #define GPIO_IDR_ID15_Pos (15U)
6371 #define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
6372 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
6373
6374 /* Legacy defines */
6375 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
6376 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
6377 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
6378 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
6379 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
6380 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
6381 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
6382 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
6383 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
6384 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
6385 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
6386 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
6387 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
6388 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
6389 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
6390 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
6391
6392 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
6393 #define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0
6394 #define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1
6395 #define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2
6396 #define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3
6397 #define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4
6398 #define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5
6399 #define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6
6400 #define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7
6401 #define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8
6402 #define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9
6403 #define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10
6404 #define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11
6405 #define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12
6406 #define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13
6407 #define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14
6408 #define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15
6409
6410 /****************** Bits definition for GPIO_ODR register *******************/
6411 #define GPIO_ODR_OD0_Pos (0U)
6412 #define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
6413 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
6414 #define GPIO_ODR_OD1_Pos (1U)
6415 #define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
6416 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
6417 #define GPIO_ODR_OD2_Pos (2U)
6418 #define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
6419 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
6420 #define GPIO_ODR_OD3_Pos (3U)
6421 #define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
6422 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
6423 #define GPIO_ODR_OD4_Pos (4U)
6424 #define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
6425 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
6426 #define GPIO_ODR_OD5_Pos (5U)
6427 #define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
6428 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
6429 #define GPIO_ODR_OD6_Pos (6U)
6430 #define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
6431 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
6432 #define GPIO_ODR_OD7_Pos (7U)
6433 #define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
6434 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
6435 #define GPIO_ODR_OD8_Pos (8U)
6436 #define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
6437 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
6438 #define GPIO_ODR_OD9_Pos (9U)
6439 #define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
6440 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
6441 #define GPIO_ODR_OD10_Pos (10U)
6442 #define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
6443 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
6444 #define GPIO_ODR_OD11_Pos (11U)
6445 #define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
6446 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
6447 #define GPIO_ODR_OD12_Pos (12U)
6448 #define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
6449 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
6450 #define GPIO_ODR_OD13_Pos (13U)
6451 #define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
6452 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
6453 #define GPIO_ODR_OD14_Pos (14U)
6454 #define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
6455 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
6456 #define GPIO_ODR_OD15_Pos (15U)
6457 #define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
6458 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
6459
6460 /* Legacy defines */
6461 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
6462 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
6463 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
6464 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
6465 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
6466 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
6467 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
6468 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
6469 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
6470 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
6471 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
6472 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
6473 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
6474 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
6475 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
6476 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
6477
6478 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
6479 #define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0
6480 #define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1
6481 #define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2
6482 #define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3
6483 #define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4
6484 #define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5
6485 #define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6
6486 #define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7
6487 #define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8
6488 #define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9
6489 #define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10
6490 #define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11
6491 #define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12
6492 #define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13
6493 #define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14
6494 #define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15
6495
6496 /****************** Bits definition for GPIO_BSRR register ******************/
6497 #define GPIO_BSRR_BS0_Pos (0U)
6498 #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
6499 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
6500 #define GPIO_BSRR_BS1_Pos (1U)
6501 #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
6502 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
6503 #define GPIO_BSRR_BS2_Pos (2U)
6504 #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
6505 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
6506 #define GPIO_BSRR_BS3_Pos (3U)
6507 #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
6508 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
6509 #define GPIO_BSRR_BS4_Pos (4U)
6510 #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
6511 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
6512 #define GPIO_BSRR_BS5_Pos (5U)
6513 #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
6514 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
6515 #define GPIO_BSRR_BS6_Pos (6U)
6516 #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
6517 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
6518 #define GPIO_BSRR_BS7_Pos (7U)
6519 #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
6520 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
6521 #define GPIO_BSRR_BS8_Pos (8U)
6522 #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
6523 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
6524 #define GPIO_BSRR_BS9_Pos (9U)
6525 #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
6526 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
6527 #define GPIO_BSRR_BS10_Pos (10U)
6528 #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
6529 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
6530 #define GPIO_BSRR_BS11_Pos (11U)
6531 #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
6532 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
6533 #define GPIO_BSRR_BS12_Pos (12U)
6534 #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
6535 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
6536 #define GPIO_BSRR_BS13_Pos (13U)
6537 #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
6538 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
6539 #define GPIO_BSRR_BS14_Pos (14U)
6540 #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
6541 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
6542 #define GPIO_BSRR_BS15_Pos (15U)
6543 #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
6544 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
6545 #define GPIO_BSRR_BR0_Pos (16U)
6546 #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
6547 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
6548 #define GPIO_BSRR_BR1_Pos (17U)
6549 #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
6550 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
6551 #define GPIO_BSRR_BR2_Pos (18U)
6552 #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
6553 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
6554 #define GPIO_BSRR_BR3_Pos (19U)
6555 #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
6556 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
6557 #define GPIO_BSRR_BR4_Pos (20U)
6558 #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
6559 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
6560 #define GPIO_BSRR_BR5_Pos (21U)
6561 #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
6562 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
6563 #define GPIO_BSRR_BR6_Pos (22U)
6564 #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
6565 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
6566 #define GPIO_BSRR_BR7_Pos (23U)
6567 #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
6568 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
6569 #define GPIO_BSRR_BR8_Pos (24U)
6570 #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
6571 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
6572 #define GPIO_BSRR_BR9_Pos (25U)
6573 #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
6574 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
6575 #define GPIO_BSRR_BR10_Pos (26U)
6576 #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
6577 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
6578 #define GPIO_BSRR_BR11_Pos (27U)
6579 #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
6580 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
6581 #define GPIO_BSRR_BR12_Pos (28U)
6582 #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
6583 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
6584 #define GPIO_BSRR_BR13_Pos (29U)
6585 #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
6586 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
6587 #define GPIO_BSRR_BR14_Pos (30U)
6588 #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
6589 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
6590 #define GPIO_BSRR_BR15_Pos (31U)
6591 #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
6592 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
6593
6594 /* Legacy defines */
6595 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
6596 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
6597 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
6598 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
6599 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
6600 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
6601 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
6602 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
6603 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
6604 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
6605 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
6606 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
6607 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
6608 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
6609 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
6610 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
6611 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
6612 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
6613 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
6614 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
6615 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
6616 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
6617 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
6618 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
6619 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
6620 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
6621 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
6622 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
6623 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
6624 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
6625 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
6626 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
6627
6628 /****************** Bit definition for GPIO_LCKR register *********************/
6629 #define GPIO_LCKR_LCK0_Pos (0U)
6630 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
6631 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
6632 #define GPIO_LCKR_LCK1_Pos (1U)
6633 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
6634 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
6635 #define GPIO_LCKR_LCK2_Pos (2U)
6636 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
6637 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
6638 #define GPIO_LCKR_LCK3_Pos (3U)
6639 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
6640 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
6641 #define GPIO_LCKR_LCK4_Pos (4U)
6642 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
6643 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
6644 #define GPIO_LCKR_LCK5_Pos (5U)
6645 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
6646 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
6647 #define GPIO_LCKR_LCK6_Pos (6U)
6648 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
6649 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
6650 #define GPIO_LCKR_LCK7_Pos (7U)
6651 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
6652 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
6653 #define GPIO_LCKR_LCK8_Pos (8U)
6654 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
6655 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
6656 #define GPIO_LCKR_LCK9_Pos (9U)
6657 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
6658 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
6659 #define GPIO_LCKR_LCK10_Pos (10U)
6660 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
6661 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
6662 #define GPIO_LCKR_LCK11_Pos (11U)
6663 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
6664 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
6665 #define GPIO_LCKR_LCK12_Pos (12U)
6666 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
6667 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
6668 #define GPIO_LCKR_LCK13_Pos (13U)
6669 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
6670 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
6671 #define GPIO_LCKR_LCK14_Pos (14U)
6672 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
6673 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
6674 #define GPIO_LCKR_LCK15_Pos (15U)
6675 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
6676 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
6677 #define GPIO_LCKR_LCKK_Pos (16U)
6678 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
6679 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
6680
6681 /****************** Bit definition for GPIO_AFRL register *********************/
6682 #define GPIO_AFRL_AFSEL0_Pos (0U)
6683 #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
6684 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
6685 #define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
6686 #define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
6687 #define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
6688 #define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
6689 #define GPIO_AFRL_AFSEL1_Pos (4U)
6690 #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
6691 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
6692 #define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
6693 #define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
6694 #define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
6695 #define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
6696 #define GPIO_AFRL_AFSEL2_Pos (8U)
6697 #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
6698 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
6699 #define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
6700 #define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
6701 #define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
6702 #define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
6703 #define GPIO_AFRL_AFSEL3_Pos (12U)
6704 #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
6705 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
6706 #define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
6707 #define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
6708 #define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
6709 #define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
6710 #define GPIO_AFRL_AFSEL4_Pos (16U)
6711 #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
6712 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
6713 #define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
6714 #define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
6715 #define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
6716 #define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
6717 #define GPIO_AFRL_AFSEL5_Pos (20U)
6718 #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
6719 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
6720 #define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
6721 #define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
6722 #define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
6723 #define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
6724 #define GPIO_AFRL_AFSEL6_Pos (24U)
6725 #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
6726 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
6727 #define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
6728 #define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
6729 #define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
6730 #define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
6731 #define GPIO_AFRL_AFSEL7_Pos (28U)
6732 #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
6733 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
6734 #define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
6735 #define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
6736 #define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
6737 #define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
6738
6739 /* Legacy defines */
6740 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
6741 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
6742 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
6743 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
6744 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
6745 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
6746 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
6747 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
6748
6749 /****************** Bit definition for GPIO_AFRH register *********************/
6750 #define GPIO_AFRH_AFSEL8_Pos (0U)
6751 #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
6752 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
6753 #define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
6754 #define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
6755 #define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
6756 #define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
6757 #define GPIO_AFRH_AFSEL9_Pos (4U)
6758 #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
6759 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
6760 #define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
6761 #define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
6762 #define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
6763 #define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
6764 #define GPIO_AFRH_AFSEL10_Pos (8U)
6765 #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
6766 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
6767 #define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
6768 #define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
6769 #define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
6770 #define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
6771 #define GPIO_AFRH_AFSEL11_Pos (12U)
6772 #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
6773 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
6774 #define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
6775 #define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
6776 #define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
6777 #define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
6778 #define GPIO_AFRH_AFSEL12_Pos (16U)
6779 #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
6780 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
6781 #define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
6782 #define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
6783 #define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
6784 #define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
6785 #define GPIO_AFRH_AFSEL13_Pos (20U)
6786 #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
6787 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
6788 #define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
6789 #define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
6790 #define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
6791 #define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
6792 #define GPIO_AFRH_AFSEL14_Pos (24U)
6793 #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
6794 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
6795 #define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
6796 #define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
6797 #define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
6798 #define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
6799 #define GPIO_AFRH_AFSEL15_Pos (28U)
6800 #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
6801 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
6802 #define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
6803 #define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
6804 #define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
6805 #define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
6806
6807 /* Legacy defines */
6808 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
6809 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
6810 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
6811 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
6812 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
6813 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
6814 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
6815 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
6816
6817 /****************** Bits definition for GPIO_BRR register ******************/
6818 #define GPIO_BRR_BR0_Pos (0U)
6819 #define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
6820 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
6821 #define GPIO_BRR_BR1_Pos (1U)
6822 #define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
6823 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
6824 #define GPIO_BRR_BR2_Pos (2U)
6825 #define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
6826 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
6827 #define GPIO_BRR_BR3_Pos (3U)
6828 #define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
6829 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
6830 #define GPIO_BRR_BR4_Pos (4U)
6831 #define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
6832 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
6833 #define GPIO_BRR_BR5_Pos (5U)
6834 #define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
6835 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
6836 #define GPIO_BRR_BR6_Pos (6U)
6837 #define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
6838 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
6839 #define GPIO_BRR_BR7_Pos (7U)
6840 #define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
6841 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
6842 #define GPIO_BRR_BR8_Pos (8U)
6843 #define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
6844 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
6845 #define GPIO_BRR_BR9_Pos (9U)
6846 #define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
6847 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
6848 #define GPIO_BRR_BR10_Pos (10U)
6849 #define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
6850 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
6851 #define GPIO_BRR_BR11_Pos (11U)
6852 #define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
6853 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
6854 #define GPIO_BRR_BR12_Pos (12U)
6855 #define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
6856 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
6857 #define GPIO_BRR_BR13_Pos (13U)
6858 #define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
6859 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
6860 #define GPIO_BRR_BR14_Pos (14U)
6861 #define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
6862 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
6863 #define GPIO_BRR_BR15_Pos (15U)
6864 #define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
6865 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
6866
6867 /* Legacy defines */
6868 #define GPIO_BRR_BR_0 GPIO_BRR_BR0
6869 #define GPIO_BRR_BR_1 GPIO_BRR_BR1
6870 #define GPIO_BRR_BR_2 GPIO_BRR_BR2
6871 #define GPIO_BRR_BR_3 GPIO_BRR_BR3
6872 #define GPIO_BRR_BR_4 GPIO_BRR_BR4
6873 #define GPIO_BRR_BR_5 GPIO_BRR_BR5
6874 #define GPIO_BRR_BR_6 GPIO_BRR_BR6
6875 #define GPIO_BRR_BR_7 GPIO_BRR_BR7
6876 #define GPIO_BRR_BR_8 GPIO_BRR_BR8
6877 #define GPIO_BRR_BR_9 GPIO_BRR_BR9
6878 #define GPIO_BRR_BR_10 GPIO_BRR_BR10
6879 #define GPIO_BRR_BR_11 GPIO_BRR_BR11
6880 #define GPIO_BRR_BR_12 GPIO_BRR_BR12
6881 #define GPIO_BRR_BR_13 GPIO_BRR_BR13
6882 #define GPIO_BRR_BR_14 GPIO_BRR_BR14
6883 #define GPIO_BRR_BR_15 GPIO_BRR_BR15
6884
6885 /******************************************************************************/
6886 /* */
6887 /* High Resolution Timer (HRTIM) */
6888 /* */
6889 /******************************************************************************/
6890 /******************** Master Timer control register ***************************/
6891 #define HRTIM_MCR_CK_PSC_Pos (0U)
6892 #define HRTIM_MCR_CK_PSC_Msk (0x7UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000007 */
6893 #define HRTIM_MCR_CK_PSC HRTIM_MCR_CK_PSC_Msk /*!< Prescaler mask */
6894 #define HRTIM_MCR_CK_PSC_0 (0x1UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000001 */
6895 #define HRTIM_MCR_CK_PSC_1 (0x2UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000002 */
6896 #define HRTIM_MCR_CK_PSC_2 (0x4UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000004 */
6897 #define HRTIM_MCR_CONT_Pos (3U)
6898 #define HRTIM_MCR_CONT_Msk (0x1UL << HRTIM_MCR_CONT_Pos) /*!< 0x00000008 */
6899 #define HRTIM_MCR_CONT HRTIM_MCR_CONT_Msk /*!< Continuous mode */
6900 #define HRTIM_MCR_RETRIG_Pos (4U)
6901 #define HRTIM_MCR_RETRIG_Msk (0x1UL << HRTIM_MCR_RETRIG_Pos) /*!< 0x00000010 */
6902 #define HRTIM_MCR_RETRIG HRTIM_MCR_RETRIG_Msk /*!< Rettrigreable mode */
6903 #define HRTIM_MCR_HALF_Pos (5U)
6904 #define HRTIM_MCR_HALF_Msk (0x1UL << HRTIM_MCR_HALF_Pos) /*!< 0x00000020 */
6905 #define HRTIM_MCR_HALF HRTIM_MCR_HALF_Msk /*!< Half mode */
6906 #define HRTIM_MCR_INTLVD_Pos (6U)
6907 #define HRTIM_MCR_INTLVD_Msk (0x3UL << HRTIM_MCR_INTLVD_Pos) /*!< 0x000000C0 */
6908 #define HRTIM_MCR_INTLVD HRTIM_MCR_INTLVD_Msk /*!< Interleaved mode */
6909 #define HRTIM_MCR_INTLVD_0 (0x1UL << HRTIM_MCR_INTLVD_Pos) /*!< 0x00000040 */
6910 #define HRTIM_MCR_INTLVD_1 (0x2UL << HRTIM_MCR_INTLVD_Pos) /*!< 0x00000080 */
6911 #define HRTIM_MCR_SYNC_IN_Pos (8U)
6912 #define HRTIM_MCR_SYNC_IN_Msk (0x3UL << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000300 */
6913 #define HRTIM_MCR_SYNC_IN HRTIM_MCR_SYNC_IN_Msk /*!< Synchronization input master */
6914 #define HRTIM_MCR_SYNC_IN_0 (0x1UL << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000100 */
6915 #define HRTIM_MCR_SYNC_IN_1 (0x2UL << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000200 */
6916 #define HRTIM_MCR_SYNCRSTM_Pos (10U)
6917 #define HRTIM_MCR_SYNCRSTM_Msk (0x1UL << HRTIM_MCR_SYNCRSTM_Pos) /*!< 0x00000400 */
6918 #define HRTIM_MCR_SYNCRSTM HRTIM_MCR_SYNCRSTM_Msk /*!< Synchronization reset master */
6919 #define HRTIM_MCR_SYNCSTRTM_Pos (11U)
6920 #define HRTIM_MCR_SYNCSTRTM_Msk (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos) /*!< 0x00000800 */
6921 #define HRTIM_MCR_SYNCSTRTM HRTIM_MCR_SYNCSTRTM_Msk /*!< Synchronization start master */
6922 #define HRTIM_MCR_SYNC_OUT_Pos (12U)
6923 #define HRTIM_MCR_SYNC_OUT_Msk (0x3UL << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00003000 */
6924 #define HRTIM_MCR_SYNC_OUT HRTIM_MCR_SYNC_OUT_Msk /*!< Synchronization output master */
6925 #define HRTIM_MCR_SYNC_OUT_0 (0x1UL << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00001000 */
6926 #define HRTIM_MCR_SYNC_OUT_1 (0x2UL << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00002000 */
6927 #define HRTIM_MCR_SYNC_SRC_Pos (14U)
6928 #define HRTIM_MCR_SYNC_SRC_Msk (0x3UL << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x0000C000 */
6929 #define HRTIM_MCR_SYNC_SRC HRTIM_MCR_SYNC_SRC_Msk /*!< Synchronization source */
6930 #define HRTIM_MCR_SYNC_SRC_0 (0x1UL << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x00004000 */
6931 #define HRTIM_MCR_SYNC_SRC_1 (0x2UL << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x00008000 */
6932 #define HRTIM_MCR_MCEN_Pos (16U)
6933 #define HRTIM_MCR_MCEN_Msk (0x1UL << HRTIM_MCR_MCEN_Pos) /*!< 0x00010000 */
6934 #define HRTIM_MCR_MCEN HRTIM_MCR_MCEN_Msk /*!< Master counter enable */
6935 #define HRTIM_MCR_TACEN_Pos (17U)
6936 #define HRTIM_MCR_TACEN_Msk (0x1UL << HRTIM_MCR_TACEN_Pos) /*!< 0x00020000 */
6937 #define HRTIM_MCR_TACEN HRTIM_MCR_TACEN_Msk /*!< Timer A counter enable */
6938 #define HRTIM_MCR_TBCEN_Pos (18U)
6939 #define HRTIM_MCR_TBCEN_Msk (0x1UL << HRTIM_MCR_TBCEN_Pos) /*!< 0x00040000 */
6940 #define HRTIM_MCR_TBCEN HRTIM_MCR_TBCEN_Msk /*!< Timer B counter enable */
6941 #define HRTIM_MCR_TCCEN_Pos (19U)
6942 #define HRTIM_MCR_TCCEN_Msk (0x1UL << HRTIM_MCR_TCCEN_Pos) /*!< 0x00080000 */
6943 #define HRTIM_MCR_TCCEN HRTIM_MCR_TCCEN_Msk /*!< Timer C counter enable */
6944 #define HRTIM_MCR_TDCEN_Pos (20U)
6945 #define HRTIM_MCR_TDCEN_Msk (0x1UL << HRTIM_MCR_TDCEN_Pos) /*!< 0x00100000 */
6946 #define HRTIM_MCR_TDCEN HRTIM_MCR_TDCEN_Msk /*!< Timer D counter enable */
6947 #define HRTIM_MCR_TECEN_Pos (21U)
6948 #define HRTIM_MCR_TECEN_Msk (0x1UL << HRTIM_MCR_TECEN_Pos) /*!< 0x00200000 */
6949 #define HRTIM_MCR_TECEN HRTIM_MCR_TECEN_Msk /*!< Timer E counter enable */
6950 #define HRTIM_MCR_TFCEN_Pos (22U)
6951 #define HRTIM_MCR_TFCEN_Msk (0x1UL << HRTIM_MCR_TFCEN_Pos) /*!< 0x00400000 */
6952 #define HRTIM_MCR_TFCEN HRTIM_MCR_TFCEN_Msk /*!< Timer F counter enable */
6953 #define HRTIM_MCR_DACSYNC_Pos (25U)
6954 #define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */
6955 #define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */
6956 #define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */
6957 #define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */
6958 #define HRTIM_MCR_PREEN_Pos (27U)
6959 #define HRTIM_MCR_PREEN_Msk (0x1UL << HRTIM_MCR_PREEN_Pos) /*!< 0x08000000 */
6960 #define HRTIM_MCR_PREEN HRTIM_MCR_PREEN_Msk /*!< Master preload enable */
6961 #define HRTIM_MCR_MREPU_Pos (29U)
6962 #define HRTIM_MCR_MREPU_Msk (0x1UL << HRTIM_MCR_MREPU_Pos) /*!< 0x20000000 */
6963 #define HRTIM_MCR_MREPU HRTIM_MCR_MREPU_Msk /*!< Master repetition update */
6964 #define HRTIM_MCR_BRSTDMA_Pos (30U)
6965 #define HRTIM_MCR_BRSTDMA_Msk (0x3UL << HRTIM_MCR_BRSTDMA_Pos) /*!< 0xC0000000 */
6966 #define HRTIM_MCR_BRSTDMA HRTIM_MCR_BRSTDMA_Msk /*!< Burst DMA update */
6967 #define HRTIM_MCR_BRSTDMA_0 (0x1UL << HRTIM_MCR_BRSTDMA_Pos) /*!< 0x40000000 */
6968 #define HRTIM_MCR_BRSTDMA_1 (0x2UL << HRTIM_MCR_BRSTDMA_Pos) /*!< 0x80000000 */
6969
6970 /******************** Master Timer Interrupt status register ******************/
6971 #define HRTIM_MISR_MCMP1_Pos (0U)
6972 #define HRTIM_MISR_MCMP1_Msk (0x1UL << HRTIM_MISR_MCMP1_Pos) /*!< 0x00000001 */
6973 #define HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1_Msk /*!< Master compare 1 interrupt flag */
6974 #define HRTIM_MISR_MCMP2_Pos (1U)
6975 #define HRTIM_MISR_MCMP2_Msk (0x1UL << HRTIM_MISR_MCMP2_Pos) /*!< 0x00000002 */
6976 #define HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2_Msk /*!< Master compare 2 interrupt flag */
6977 #define HRTIM_MISR_MCMP3_Pos (2U)
6978 #define HRTIM_MISR_MCMP3_Msk (0x1UL << HRTIM_MISR_MCMP3_Pos) /*!< 0x00000004 */
6979 #define HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3_Msk /*!< Master compare 3 interrupt flag */
6980 #define HRTIM_MISR_MCMP4_Pos (3U)
6981 #define HRTIM_MISR_MCMP4_Msk (0x1UL << HRTIM_MISR_MCMP4_Pos) /*!< 0x00000008 */
6982 #define HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4_Msk /*!< Master compare 4 interrupt flag */
6983 #define HRTIM_MISR_MREP_Pos (4U)
6984 #define HRTIM_MISR_MREP_Msk (0x1UL << HRTIM_MISR_MREP_Pos) /*!< 0x00000010 */
6985 #define HRTIM_MISR_MREP HRTIM_MISR_MREP_Msk /*!< Master Repetition interrupt flag */
6986 #define HRTIM_MISR_SYNC_Pos (5U)
6987 #define HRTIM_MISR_SYNC_Msk (0x1UL << HRTIM_MISR_SYNC_Pos) /*!< 0x00000020 */
6988 #define HRTIM_MISR_SYNC HRTIM_MISR_SYNC_Msk /*!< Synchronization input interrupt flag */
6989 #define HRTIM_MISR_MUPD_Pos (6U)
6990 #define HRTIM_MISR_MUPD_Msk (0x1UL << HRTIM_MISR_MUPD_Pos) /*!< 0x00000040 */
6991 #define HRTIM_MISR_MUPD HRTIM_MISR_MUPD_Msk /*!< Master update interrupt flag */
6992
6993 /******************** Master Timer Interrupt clear register *******************/
6994 #define HRTIM_MICR_MCMP1_Pos (0U)
6995 #define HRTIM_MICR_MCMP1_Msk (0x1UL << HRTIM_MICR_MCMP1_Pos) /*!< 0x00000001 */
6996 #define HRTIM_MICR_MCMP1 HRTIM_MICR_MCMP1_Msk /*!< Master compare 1 interrupt flag clear */
6997 #define HRTIM_MICR_MCMP2_Pos (1U)
6998 #define HRTIM_MICR_MCMP2_Msk (0x1UL << HRTIM_MICR_MCMP2_Pos) /*!< 0x00000002 */
6999 #define HRTIM_MICR_MCMP2 HRTIM_MICR_MCMP2_Msk /*!< Master compare 2 interrupt flag clear */
7000 #define HRTIM_MICR_MCMP3_Pos (2U)
7001 #define HRTIM_MICR_MCMP3_Msk (0x1UL << HRTIM_MICR_MCMP3_Pos) /*!< 0x00000004 */
7002 #define HRTIM_MICR_MCMP3 HRTIM_MICR_MCMP3_Msk /*!< Master compare 3 interrupt flag clear */
7003 #define HRTIM_MICR_MCMP4_Pos (3U)
7004 #define HRTIM_MICR_MCMP4_Msk (0x1UL << HRTIM_MICR_MCMP4_Pos) /*!< 0x00000008 */
7005 #define HRTIM_MICR_MCMP4 HRTIM_MICR_MCMP4_Msk /*!< Master compare 4 interrupt flag clear */
7006 #define HRTIM_MICR_MREP_Pos (4U)
7007 #define HRTIM_MICR_MREP_Msk (0x1UL << HRTIM_MICR_MREP_Pos) /*!< 0x00000010 */
7008 #define HRTIM_MICR_MREP HRTIM_MICR_MREP_Msk /*!< Master Repetition interrupt flag clear */
7009 #define HRTIM_MICR_SYNC_Pos (5U)
7010 #define HRTIM_MICR_SYNC_Msk (0x1UL << HRTIM_MICR_SYNC_Pos) /*!< 0x00000020 */
7011 #define HRTIM_MICR_SYNC HRTIM_MICR_SYNC_Msk /*!< Synchronization input interrupt flag clear */
7012 #define HRTIM_MICR_MUPD_Pos (6U)
7013 #define HRTIM_MICR_MUPD_Msk (0x1UL << HRTIM_MICR_MUPD_Pos) /*!< 0x00000040 */
7014 #define HRTIM_MICR_MUPD HRTIM_MICR_MUPD_Msk /*!< Master update interrupt flag clear */
7015
7016 /******************** Master Timer DMA/Interrupt enable register **************/
7017 #define HRTIM_MDIER_MCMP1IE_Pos (0U)
7018 #define HRTIM_MDIER_MCMP1IE_Msk (0x1UL << HRTIM_MDIER_MCMP1IE_Pos) /*!< 0x00000001 */
7019 #define HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE_Msk /*!< Master compare 1 interrupt enable */
7020 #define HRTIM_MDIER_MCMP2IE_Pos (1U)
7021 #define HRTIM_MDIER_MCMP2IE_Msk (0x1UL << HRTIM_MDIER_MCMP2IE_Pos) /*!< 0x00000002 */
7022 #define HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE_Msk /*!< Master compare 2 interrupt enable */
7023 #define HRTIM_MDIER_MCMP3IE_Pos (2U)
7024 #define HRTIM_MDIER_MCMP3IE_Msk (0x1UL << HRTIM_MDIER_MCMP3IE_Pos) /*!< 0x00000004 */
7025 #define HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE_Msk /*!< Master compare 3 interrupt enable */
7026 #define HRTIM_MDIER_MCMP4IE_Pos (3U)
7027 #define HRTIM_MDIER_MCMP4IE_Msk (0x1UL << HRTIM_MDIER_MCMP4IE_Pos) /*!< 0x00000008 */
7028 #define HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE_Msk /*!< Master compare 4 interrupt enable */
7029 #define HRTIM_MDIER_MREPIE_Pos (4U)
7030 #define HRTIM_MDIER_MREPIE_Msk (0x1UL << HRTIM_MDIER_MREPIE_Pos) /*!< 0x00000010 */
7031 #define HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE_Msk /*!< Master Repetition interrupt enable */
7032 #define HRTIM_MDIER_SYNCIE_Pos (5U)
7033 #define HRTIM_MDIER_SYNCIE_Msk (0x1UL << HRTIM_MDIER_SYNCIE_Pos) /*!< 0x00000020 */
7034 #define HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE_Msk /*!< Synchronization input interrupt enable */
7035 #define HRTIM_MDIER_MUPDIE_Pos (6U)
7036 #define HRTIM_MDIER_MUPDIE_Msk (0x1UL << HRTIM_MDIER_MUPDIE_Pos) /*!< 0x00000040 */
7037 #define HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE_Msk /*!< Master update interrupt enable */
7038 #define HRTIM_MDIER_MCMP1DE_Pos (16U)
7039 #define HRTIM_MDIER_MCMP1DE_Msk (0x1UL << HRTIM_MDIER_MCMP1DE_Pos) /*!< 0x00010000 */
7040 #define HRTIM_MDIER_MCMP1DE HRTIM_MDIER_MCMP1DE_Msk /*!< Master compare 1 DMA enable */
7041 #define HRTIM_MDIER_MCMP2DE_Pos (17U)
7042 #define HRTIM_MDIER_MCMP2DE_Msk (0x1UL << HRTIM_MDIER_MCMP2DE_Pos) /*!< 0x00020000 */
7043 #define HRTIM_MDIER_MCMP2DE HRTIM_MDIER_MCMP2DE_Msk /*!< Master compare 2 DMA enable */
7044 #define HRTIM_MDIER_MCMP3DE_Pos (18U)
7045 #define HRTIM_MDIER_MCMP3DE_Msk (0x1UL << HRTIM_MDIER_MCMP3DE_Pos) /*!< 0x00040000 */
7046 #define HRTIM_MDIER_MCMP3DE HRTIM_MDIER_MCMP3DE_Msk /*!< Master compare 3 DMA enable */
7047 #define HRTIM_MDIER_MCMP4DE_Pos (19U)
7048 #define HRTIM_MDIER_MCMP4DE_Msk (0x1UL << HRTIM_MDIER_MCMP4DE_Pos) /*!< 0x00080000 */
7049 #define HRTIM_MDIER_MCMP4DE HRTIM_MDIER_MCMP4DE_Msk /*!< Master compare 4 DMA enable */
7050 #define HRTIM_MDIER_MREPDE_Pos (20U)
7051 #define HRTIM_MDIER_MREPDE_Msk (0x1UL << HRTIM_MDIER_MREPDE_Pos) /*!< 0x00100000 */
7052 #define HRTIM_MDIER_MREPDE HRTIM_MDIER_MREPDE_Msk /*!< Master Repetition DMA enable */
7053 #define HRTIM_MDIER_SYNCDE_Pos (21U)
7054 #define HRTIM_MDIER_SYNCDE_Msk (0x1UL << HRTIM_MDIER_SYNCDE_Pos) /*!< 0x00200000 */
7055 #define HRTIM_MDIER_SYNCDE HRTIM_MDIER_SYNCDE_Msk /*!< Synchronization input DMA enable */
7056 #define HRTIM_MDIER_MUPDDE_Pos (22U)
7057 #define HRTIM_MDIER_MUPDDE_Msk (0x1UL << HRTIM_MDIER_MUPDDE_Pos) /*!< 0x00400000 */
7058 #define HRTIM_MDIER_MUPDDE HRTIM_MDIER_MUPDDE_Msk /*!< Master update DMA enable */
7059
7060 /******************* Bit definition for HRTIM_MCNTR register ****************/
7061 #define HRTIM_MCNTR_MCNTR_Pos (0U)
7062 #define HRTIM_MCNTR_MCNTR_Msk (0x0000FFFFUL << HRTIM_MCNTR_MCNTR_Pos) /*!< 0x0000FFFF */
7063 #define HRTIM_MCNTR_MCNTR HRTIM_MCNTR_MCNTR_Msk /*!<Counter Value */
7064
7065 /******************* Bit definition for HRTIM_MPER register *****************/
7066 #define HRTIM_MPER_MPER_Pos (0U)
7067 #define HRTIM_MPER_MPER_Msk (0x0000FFFFUL << HRTIM_MPER_MPER_Pos) /*!< 0x0000FFFF */
7068 #define HRTIM_MPER_MPER HRTIM_MPER_MPER_Msk /*!< Period Value */
7069
7070 /******************* Bit definition for HRTIM_MREP register *****************/
7071 #define HRTIM_MREP_MREP_Pos (0U)
7072 #define HRTIM_MREP_MREP_Msk (0x000000FFUL << HRTIM_MREP_MREP_Pos) /*!< 0x000000FF */
7073 #define HRTIM_MREP_MREP HRTIM_MREP_MREP_Msk /*!<Repetition Value */
7074
7075 /******************* Bit definition for HRTIM_MCMP1R register *****************/
7076 #define HRTIM_MCMP1R_MCMP1R_Pos (0U)
7077 #define HRTIM_MCMP1R_MCMP1R_Msk (0x0000FFFFUL << HRTIM_MCMP1R_MCMP1R_Pos)/*!< 0x0000FFFF */
7078 #define HRTIM_MCMP1R_MCMP1R HRTIM_MCMP1R_MCMP1R_Msk /*!<Compare Value */
7079
7080 /******************* Bit definition for HRTIM_MCMP2R register *****************/
7081 #define HRTIM_MCMP2R_MCMP2R_Pos (0U)
7082 #define HRTIM_MCMP2R_MCMP2R_Msk (0x0000FFFFUL << HRTIM_MCMP2R_MCMP2R_Pos)/*!< 0x0000FFFF */
7083 #define HRTIM_MCMP2R_MCMP2R HRTIM_MCMP2R_MCMP2R_Msk /*!<Compare Value */
7084
7085 /******************* Bit definition for HRTIM_MCMP3R register *****************/
7086 #define HRTIM_MCMP3R_MCMP3R_Pos (0U)
7087 #define HRTIM_MCMP3R_MCMP3R_Msk (0x0000FFFFUL << HRTIM_MCMP3R_MCMP3R_Pos)/*!< 0x0000FFFF */
7088 #define HRTIM_MCMP3R_MCMP3R HRTIM_MCMP3R_MCMP3R_Msk /*!<Compare Value */
7089
7090 /******************* Bit definition for HRTIM_MCMP4R register *****************/
7091 #define HRTIM_MCMP4R_MCMP4R_Pos (0U)
7092 #define HRTIM_MCMP4R_MCMP4R_Msk (0x0000FFFFUL << HRTIM_MCMP4R_MCMP4R_Pos)/*!< 0x0000FFFF */
7093 #define HRTIM_MCMP4R_MCMP4R HRTIM_MCMP4R_MCMP4R_Msk /*!<Compare Value */
7094
7095 /* Legacy defines */
7096 #define HRTIM_MCMP1R_MCMP2R HRTIM_MCMP2R_MCMP2R
7097 #define HRTIM_MCMP1R_MCMP3R HRTIM_MCMP3R_MCMP3R
7098 #define HRTIM_MCMP1R_MCMP4R HRTIM_MCMP4R_MCMP4R
7099
7100 /******************** Slave control register **********************************/
7101 #define HRTIM_TIMCR_CK_PSC_Pos (0U)
7102 #define HRTIM_TIMCR_CK_PSC_Msk (0x7UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000007 */
7103 #define HRTIM_TIMCR_CK_PSC HRTIM_TIMCR_CK_PSC_Msk /*!< Slave prescaler mask*/
7104 #define HRTIM_TIMCR_CK_PSC_0 (0x1UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000001 */
7105 #define HRTIM_TIMCR_CK_PSC_1 (0x2UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000002 */
7106 #define HRTIM_TIMCR_CK_PSC_2 (0x4UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000004 */
7107 #define HRTIM_TIMCR_CONT_Pos (3U)
7108 #define HRTIM_TIMCR_CONT_Msk (0x1UL << HRTIM_TIMCR_CONT_Pos) /*!< 0x00000008 */
7109 #define HRTIM_TIMCR_CONT HRTIM_TIMCR_CONT_Msk /*!< Slave continuous mode */
7110 #define HRTIM_TIMCR_RETRIG_Pos (4U)
7111 #define HRTIM_TIMCR_RETRIG_Msk (0x1UL << HRTIM_TIMCR_RETRIG_Pos) /*!< 0x00000010 */
7112 #define HRTIM_TIMCR_RETRIG HRTIM_TIMCR_RETRIG_Msk /*!< Slave Retrigreable mode */
7113 #define HRTIM_TIMCR_HALF_Pos (5U)
7114 #define HRTIM_TIMCR_HALF_Msk (0x1UL << HRTIM_TIMCR_HALF_Pos) /*!< 0x00000020 */
7115 #define HRTIM_TIMCR_HALF HRTIM_TIMCR_HALF_Msk /*!< Slave Half mode */
7116 #define HRTIM_TIMCR_PSHPLL_Pos (6U)
7117 #define HRTIM_TIMCR_PSHPLL_Msk (0x1UL << HRTIM_TIMCR_PSHPLL_Pos) /*!< 0x00000040 */
7118 #define HRTIM_TIMCR_PSHPLL HRTIM_TIMCR_PSHPLL_Msk /*!< Slave push-pull mode */
7119 #define HRTIM_TIMCR_INTLVD_Pos (7U)
7120 #define HRTIM_TIMCR_INTLVD_Msk (0x3UL << HRTIM_TIMCR_INTLVD_Pos) /*!< 0x00000180 */
7121 #define HRTIM_TIMCR_INTLVD HRTIM_TIMCR_INTLVD_Msk /*!< Interleaved mode */
7122 #define HRTIM_TIMCR_INTLVD_0 (0x1UL << HRTIM_TIMCR_INTLVD_Pos) /*!< 0x00000080 */
7123 #define HRTIM_TIMCR_INTLVD_1 (0x2UL << HRTIM_TIMCR_INTLVD_Pos) /*!< 0x00000100 */
7124 #define HRTIM_TIMCR_RSYNCU_Pos (9U)
7125 #define HRTIM_TIMCR_RSYNCU_Msk (0x1UL << HRTIM_TIMCR_RSYNCU_Pos) /*!< 0x00000200 */
7126 #define HRTIM_TIMCR_RSYNCU HRTIM_TIMCR_RSYNCU_Msk /*!< Resynchronization update */
7127 #define HRTIM_TIMCR_SYNCRST_Pos (10U)
7128 #define HRTIM_TIMCR_SYNCRST_Msk (0x1UL << HRTIM_TIMCR_SYNCRST_Pos) /*!< 0x00000400 */
7129 #define HRTIM_TIMCR_SYNCRST HRTIM_TIMCR_SYNCRST_Msk /*!< Slave synchronization resets */
7130 #define HRTIM_TIMCR_SYNCSTRT_Pos (11U)
7131 #define HRTIM_TIMCR_SYNCSTRT_Msk (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos) /*!< 0x00000800 */
7132 #define HRTIM_TIMCR_SYNCSTRT HRTIM_TIMCR_SYNCSTRT_Msk /*!< Slave synchronization starts */
7133 #define HRTIM_TIMCR_DELCMP2_Pos (12U)
7134 #define HRTIM_TIMCR_DELCMP2_Msk (0x3UL << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00003000 */
7135 #define HRTIM_TIMCR_DELCMP2 HRTIM_TIMCR_DELCMP2_Msk /*!< Slave delayed compartor 2 mode mask */
7136 #define HRTIM_TIMCR_DELCMP2_0 (0x1UL << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00001000 */
7137 #define HRTIM_TIMCR_DELCMP2_1 (0x2UL << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00002000 */
7138 #define HRTIM_TIMCR_DELCMP4_Pos (14U)
7139 #define HRTIM_TIMCR_DELCMP4_Msk (0x3UL << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x0000C000 */
7140 #define HRTIM_TIMCR_DELCMP4 HRTIM_TIMCR_DELCMP4_Msk /*!< Slave delayed compartor 4 mode mask */
7141 #define HRTIM_TIMCR_DELCMP4_0 (0x1UL << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x00004000 */
7142 #define HRTIM_TIMCR_DELCMP4_1 (0x2UL << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x00008000 */
7143 #define HRTIM_TIMCR_TFU_Pos (16U)
7144 #define HRTIM_TIMCR_TFU_Msk (0x1UL << HRTIM_TIMCR_TFU_Pos) /*!< 0x00010000 */
7145 #define HRTIM_TIMCR_TFU HRTIM_TIMCR_TFU_Msk /*!< Slave Timer F update reserved for TIM F */
7146 #define HRTIM_TIMCR_TREPU_Pos (17U)
7147 #define HRTIM_TIMCR_TREPU_Msk (0x1UL << HRTIM_TIMCR_TREPU_Pos) /*!< 0x00020000 */
7148 #define HRTIM_TIMCR_TREPU HRTIM_TIMCR_TREPU_Msk /*!< Slave repetition update */
7149 #define HRTIM_TIMCR_TRSTU_Pos (18U)
7150 #define HRTIM_TIMCR_TRSTU_Msk (0x1UL << HRTIM_TIMCR_TRSTU_Pos) /*!< 0x00040000 */
7151 #define HRTIM_TIMCR_TRSTU HRTIM_TIMCR_TRSTU_Msk /*!< Slave reset update */
7152 #define HRTIM_TIMCR_TAU_Pos (19U)
7153 #define HRTIM_TIMCR_TAU_Msk (0x1UL << HRTIM_TIMCR_TAU_Pos) /*!< 0x00080000 */
7154 #define HRTIM_TIMCR_TAU HRTIM_TIMCR_TAU_Msk /*!< Slave Timer A update reserved for TIM A */
7155 #define HRTIM_TIMCR_TBU_Pos (20U)
7156 #define HRTIM_TIMCR_TBU_Msk (0x1UL << HRTIM_TIMCR_TBU_Pos) /*!< 0x00100000 */
7157 #define HRTIM_TIMCR_TBU HRTIM_TIMCR_TBU_Msk /*!< Slave Timer B update reserved for TIM B */
7158 #define HRTIM_TIMCR_TCU_Pos (21U)
7159 #define HRTIM_TIMCR_TCU_Msk (0x1UL << HRTIM_TIMCR_TCU_Pos) /*!< 0x00200000 */
7160 #define HRTIM_TIMCR_TCU HRTIM_TIMCR_TCU_Msk /*!< Slave Timer C update reserved for TIM C */
7161 #define HRTIM_TIMCR_TDU_Pos (22U)
7162 #define HRTIM_TIMCR_TDU_Msk (0x1UL << HRTIM_TIMCR_TDU_Pos) /*!< 0x00400000 */
7163 #define HRTIM_TIMCR_TDU HRTIM_TIMCR_TDU_Msk /*!< Slave Timer D update reserved for TIM D */
7164 #define HRTIM_TIMCR_TEU_Pos (23U)
7165 #define HRTIM_TIMCR_TEU_Msk (0x1UL << HRTIM_TIMCR_TEU_Pos) /*!< 0x00800000 */
7166 #define HRTIM_TIMCR_TEU HRTIM_TIMCR_TEU_Msk /*!< Slave Timer E update reserved for TIM E */
7167 #define HRTIM_TIMCR_MSTU_Pos (24U)
7168 #define HRTIM_TIMCR_MSTU_Msk (0x1UL << HRTIM_TIMCR_MSTU_Pos) /*!< 0x02000000 */
7169 #define HRTIM_TIMCR_MSTU HRTIM_TIMCR_MSTU_Msk /*!< Master Update */
7170 #define HRTIM_TIMCR_DACSYNC_Pos (25U)
7171 #define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */
7172 #define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */
7173 #define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */
7174 #define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */
7175 #define HRTIM_TIMCR_PREEN_Pos (27U)
7176 #define HRTIM_TIMCR_PREEN_Msk (0x1UL << HRTIM_TIMCR_PREEN_Pos) /*!< 0x08000000 */
7177 #define HRTIM_TIMCR_PREEN HRTIM_TIMCR_PREEN_Msk /*!< Slave preload enable */
7178 #define HRTIM_TIMCR_UPDGAT_Pos (28U)
7179 #define HRTIM_TIMCR_UPDGAT_Msk (0xFUL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0xF0000000 */
7180 #define HRTIM_TIMCR_UPDGAT HRTIM_TIMCR_UPDGAT_Msk /*!< Slave update gating mask */
7181 #define HRTIM_TIMCR_UPDGAT_0 (0x1UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x10000000 */
7182 #define HRTIM_TIMCR_UPDGAT_1 (0x2UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x20000000 */
7183 #define HRTIM_TIMCR_UPDGAT_2 (0x4UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x40000000 */
7184 #define HRTIM_TIMCR_UPDGAT_3 (0x8UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x80000000 */
7185
7186 /******************** Slave Interrupt status register **************************/
7187 #define HRTIM_TIMISR_CMP1_Pos (0U)
7188 #define HRTIM_TIMISR_CMP1_Msk (0x1UL << HRTIM_TIMISR_CMP1_Pos) /*!< 0x00000001 */
7189 #define HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1_Msk /*!< Slave compare 1 interrupt flag */
7190 #define HRTIM_TIMISR_CMP2_Pos (1U)
7191 #define HRTIM_TIMISR_CMP2_Msk (0x1UL << HRTIM_TIMISR_CMP2_Pos) /*!< 0x00000002 */
7192 #define HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2_Msk /*!< Slave compare 2 interrupt flag */
7193 #define HRTIM_TIMISR_CMP3_Pos (2U)
7194 #define HRTIM_TIMISR_CMP3_Msk (0x1UL << HRTIM_TIMISR_CMP3_Pos) /*!< 0x00000004 */
7195 #define HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3_Msk /*!< Slave compare 3 interrupt flag */
7196 #define HRTIM_TIMISR_CMP4_Pos (3U)
7197 #define HRTIM_TIMISR_CMP4_Msk (0x1UL << HRTIM_TIMISR_CMP4_Pos) /*!< 0x00000008 */
7198 #define HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4_Msk /*!< Slave compare 4 interrupt flag */
7199 #define HRTIM_TIMISR_REP_Pos (4U)
7200 #define HRTIM_TIMISR_REP_Msk (0x1UL << HRTIM_TIMISR_REP_Pos) /*!< 0x00000010 */
7201 #define HRTIM_TIMISR_REP HRTIM_TIMISR_REP_Msk /*!< Slave repetition interrupt flag */
7202 #define HRTIM_TIMISR_UPD_Pos (6U)
7203 #define HRTIM_TIMISR_UPD_Msk (0x1UL << HRTIM_TIMISR_UPD_Pos) /*!< 0x00000040 */
7204 #define HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD_Msk /*!< Slave update interrupt flag */
7205 #define HRTIM_TIMISR_CPT1_Pos (7U)
7206 #define HRTIM_TIMISR_CPT1_Msk (0x1UL << HRTIM_TIMISR_CPT1_Pos) /*!< 0x00000080 */
7207 #define HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1_Msk /*!< Slave capture 1 interrupt flag */
7208 #define HRTIM_TIMISR_CPT2_Pos (8U)
7209 #define HRTIM_TIMISR_CPT2_Msk (0x1UL << HRTIM_TIMISR_CPT2_Pos) /*!< 0x00000100 */
7210 #define HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2_Msk /*!< Slave capture 2 interrupt flag */
7211 #define HRTIM_TIMISR_SET1_Pos (9U)
7212 #define HRTIM_TIMISR_SET1_Msk (0x1UL << HRTIM_TIMISR_SET1_Pos) /*!< 0x00000200 */
7213 #define HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1_Msk /*!< Slave output 1 set interrupt flag */
7214 #define HRTIM_TIMISR_RST1_Pos (10U)
7215 #define HRTIM_TIMISR_RST1_Msk (0x1UL << HRTIM_TIMISR_RST1_Pos) /*!< 0x00000400 */
7216 #define HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1_Msk /*!< Slave output 1 reset interrupt flag */
7217 #define HRTIM_TIMISR_SET2_Pos (11U)
7218 #define HRTIM_TIMISR_SET2_Msk (0x1UL << HRTIM_TIMISR_SET2_Pos) /*!< 0x00000800 */
7219 #define HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2_Msk /*!< Slave output 2 set interrupt flag */
7220 #define HRTIM_TIMISR_RST2_Pos (12U)
7221 #define HRTIM_TIMISR_RST2_Msk (0x1UL << HRTIM_TIMISR_RST2_Pos) /*!< 0x00001000 */
7222 #define HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2_Msk /*!< Slave output 2 reset interrupt flag */
7223 #define HRTIM_TIMISR_RST_Pos (13U)
7224 #define HRTIM_TIMISR_RST_Msk (0x1UL << HRTIM_TIMISR_RST_Pos) /*!< 0x00002000 */
7225 #define HRTIM_TIMISR_RST HRTIM_TIMISR_RST_Msk /*!< Slave reset interrupt flag */
7226 #define HRTIM_TIMISR_DLYPRT_Pos (14U)
7227 #define HRTIM_TIMISR_DLYPRT_Msk (0x1UL << HRTIM_TIMISR_DLYPRT_Pos) /*!< 0x00004000 */
7228 #define HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT_Msk /*!< Slave output 1 delay protection interrupt flag */
7229 #define HRTIM_TIMISR_CPPSTAT_Pos (16U)
7230 #define HRTIM_TIMISR_CPPSTAT_Msk (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos) /*!< 0x00010000 */
7231 #define HRTIM_TIMISR_CPPSTAT HRTIM_TIMISR_CPPSTAT_Msk /*!< Slave current push-pull flag */
7232 #define HRTIM_TIMISR_IPPSTAT_Pos (17U)
7233 #define HRTIM_TIMISR_IPPSTAT_Msk (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos) /*!< 0x00020000 */
7234 #define HRTIM_TIMISR_IPPSTAT HRTIM_TIMISR_IPPSTAT_Msk /*!< Slave idle push-pull flag */
7235 #define HRTIM_TIMISR_O1STAT_Pos (18U)
7236 #define HRTIM_TIMISR_O1STAT_Msk (0x1UL << HRTIM_TIMISR_O1STAT_Pos) /*!< 0x00040000 */
7237 #define HRTIM_TIMISR_O1STAT HRTIM_TIMISR_O1STAT_Msk /*!< Slave output 1 state flag */
7238 #define HRTIM_TIMISR_O2STAT_Pos (19U)
7239 #define HRTIM_TIMISR_O2STAT_Msk (0x1UL << HRTIM_TIMISR_O2STAT_Pos) /*!< 0x00080000 */
7240 #define HRTIM_TIMISR_O2STAT HRTIM_TIMISR_O2STAT_Msk /*!< Slave output 2 state flag */
7241 #define HRTIM_TIMISR_O1CPY_Pos (20U)
7242 #define HRTIM_TIMISR_O1CPY_Msk (0x1UL << HRTIM_TIMISR_O1CPY_Pos) /*!< 0x00100000 */
7243 #define HRTIM_TIMISR_O1CPY HRTIM_TIMISR_O1CPY_Msk /*!< Slave output 1 copy flag */
7244 #define HRTIM_TIMISR_O2CPY_Pos (21U)
7245 #define HRTIM_TIMISR_O2CPY_Msk (0x1UL << HRTIM_TIMISR_O2CPY_Pos) /*!< 0x00200000 */
7246 #define HRTIM_TIMISR_O2CPY HRTIM_TIMISR_O2CPY_Msk /*!< Slave output 2 copy flag */
7247
7248 /******************** Slave Interrupt clear register **************************/
7249 #define HRTIM_TIMICR_CMP1C_Pos (0U)
7250 #define HRTIM_TIMICR_CMP1C_Msk (0x1UL << HRTIM_TIMICR_CMP1C_Pos) /*!< 0x00000001 */
7251 #define HRTIM_TIMICR_CMP1C HRTIM_TIMICR_CMP1C_Msk /*!< Slave compare 1 clear flag */
7252 #define HRTIM_TIMICR_CMP2C_Pos (1U)
7253 #define HRTIM_TIMICR_CMP2C_Msk (0x1UL << HRTIM_TIMICR_CMP2C_Pos) /*!< 0x00000002 */
7254 #define HRTIM_TIMICR_CMP2C HRTIM_TIMICR_CMP2C_Msk /*!< Slave compare 2 clear flag */
7255 #define HRTIM_TIMICR_CMP3C_Pos (2U)
7256 #define HRTIM_TIMICR_CMP3C_Msk (0x1UL << HRTIM_TIMICR_CMP3C_Pos) /*!< 0x00000004 */
7257 #define HRTIM_TIMICR_CMP3C HRTIM_TIMICR_CMP3C_Msk /*!< Slave compare 3 clear flag */
7258 #define HRTIM_TIMICR_CMP4C_Pos (3U)
7259 #define HRTIM_TIMICR_CMP4C_Msk (0x1UL << HRTIM_TIMICR_CMP4C_Pos) /*!< 0x00000008 */
7260 #define HRTIM_TIMICR_CMP4C HRTIM_TIMICR_CMP4C_Msk /*!< Slave compare 4 clear flag */
7261 #define HRTIM_TIMICR_REPC_Pos (4U)
7262 #define HRTIM_TIMICR_REPC_Msk (0x1UL << HRTIM_TIMICR_REPC_Pos) /*!< 0x00000010 */
7263 #define HRTIM_TIMICR_REPC HRTIM_TIMICR_REPC_Msk /*!< Slave repetition clear flag */
7264 #define HRTIM_TIMICR_UPDC_Pos (6U)
7265 #define HRTIM_TIMICR_UPDC_Msk (0x1UL << HRTIM_TIMICR_UPDC_Pos) /*!< 0x00000040 */
7266 #define HRTIM_TIMICR_UPDC HRTIM_TIMICR_UPDC_Msk /*!< Slave update clear flag */
7267 #define HRTIM_TIMICR_CPT1C_Pos (7U)
7268 #define HRTIM_TIMICR_CPT1C_Msk (0x1UL << HRTIM_TIMICR_CPT1C_Pos) /*!< 0x00000080 */
7269 #define HRTIM_TIMICR_CPT1C HRTIM_TIMICR_CPT1C_Msk /*!< Slave capture 1 clear flag */
7270 #define HRTIM_TIMICR_CPT2C_Pos (8U)
7271 #define HRTIM_TIMICR_CPT2C_Msk (0x1UL << HRTIM_TIMICR_CPT2C_Pos) /*!< 0x00000100 */
7272 #define HRTIM_TIMICR_CPT2C HRTIM_TIMICR_CPT2C_Msk /*!< Slave capture 2 clear flag */
7273 #define HRTIM_TIMICR_SET1C_Pos (9U)
7274 #define HRTIM_TIMICR_SET1C_Msk (0x1UL << HRTIM_TIMICR_SET1C_Pos) /*!< 0x00000200 */
7275 #define HRTIM_TIMICR_SET1C HRTIM_TIMICR_SET1C_Msk /*!< Slave output 1 set clear flag */
7276 #define HRTIM_TIMICR_RST1C_Pos (10U)
7277 #define HRTIM_TIMICR_RST1C_Msk (0x1UL << HRTIM_TIMICR_RST1C_Pos) /*!< 0x00000400 */
7278 #define HRTIM_TIMICR_RST1C HRTIM_TIMICR_RST1C_Msk /*!< Slave output 1 reset clear flag */
7279 #define HRTIM_TIMICR_SET2C_Pos (11U)
7280 #define HRTIM_TIMICR_SET2C_Msk (0x1UL << HRTIM_TIMICR_SET2C_Pos) /*!< 0x00000800 */
7281 #define HRTIM_TIMICR_SET2C HRTIM_TIMICR_SET2C_Msk /*!< Slave output 2 set clear flag */
7282 #define HRTIM_TIMICR_RST2C_Pos (12U)
7283 #define HRTIM_TIMICR_RST2C_Msk (0x1UL << HRTIM_TIMICR_RST2C_Pos) /*!< 0x00001000 */
7284 #define HRTIM_TIMICR_RST2C HRTIM_TIMICR_RST2C_Msk /*!< Slave output 2 reset clear flag */
7285 #define HRTIM_TIMICR_RSTC_Pos (13U)
7286 #define HRTIM_TIMICR_RSTC_Msk (0x1UL << HRTIM_TIMICR_RSTC_Pos) /*!< 0x00002000 */
7287 #define HRTIM_TIMICR_RSTC HRTIM_TIMICR_RSTC_Msk /*!< Slave reset clear flag */
7288 #define HRTIM_TIMICR_DLYPRTC_Pos (14U)
7289 #define HRTIM_TIMICR_DLYPRTC_Msk (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos) /*!< 0x00004000 */
7290 #define HRTIM_TIMICR_DLYPRTC HRTIM_TIMICR_DLYPRTC_Msk /*!< Slave output delay protection clear flag */
7291
7292 /******************** Slave DMA/Interrupt enable register *********************/
7293 #define HRTIM_TIMDIER_CMP1IE_Pos (0U)
7294 #define HRTIM_TIMDIER_CMP1IE_Msk (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos) /*!< 0x00000001 */
7295 #define HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE_Msk /*!< Slave compare 1 interrupt enable */
7296 #define HRTIM_TIMDIER_CMP2IE_Pos (1U)
7297 #define HRTIM_TIMDIER_CMP2IE_Msk (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos) /*!< 0x00000002 */
7298 #define HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE_Msk /*!< Slave compare 2 interrupt enable */
7299 #define HRTIM_TIMDIER_CMP3IE_Pos (2U)
7300 #define HRTIM_TIMDIER_CMP3IE_Msk (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos) /*!< 0x00000004 */
7301 #define HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE_Msk /*!< Slave compare 3 interrupt enable */
7302 #define HRTIM_TIMDIER_CMP4IE_Pos (3U)
7303 #define HRTIM_TIMDIER_CMP4IE_Msk (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos) /*!< 0x00000008 */
7304 #define HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE_Msk /*!< Slave compare 4 interrupt enable */
7305 #define HRTIM_TIMDIER_REPIE_Pos (4U)
7306 #define HRTIM_TIMDIER_REPIE_Msk (0x1UL << HRTIM_TIMDIER_REPIE_Pos) /*!< 0x00000010 */
7307 #define HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE_Msk /*!< Slave repetition interrupt enable */
7308 #define HRTIM_TIMDIER_UPDIE_Pos (6U)
7309 #define HRTIM_TIMDIER_UPDIE_Msk (0x1UL << HRTIM_TIMDIER_UPDIE_Pos) /*!< 0x00000040 */
7310 #define HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE_Msk /*!< Slave update interrupt enable */
7311 #define HRTIM_TIMDIER_CPT1IE_Pos (7U)
7312 #define HRTIM_TIMDIER_CPT1IE_Msk (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos) /*!< 0x00000080 */
7313 #define HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE_Msk /*!< Slave capture 1 interrupt enable */
7314 #define HRTIM_TIMDIER_CPT2IE_Pos (8U)
7315 #define HRTIM_TIMDIER_CPT2IE_Msk (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos) /*!< 0x00000100 */
7316 #define HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE_Msk /*!< Slave capture 2 interrupt enable */
7317 #define HRTIM_TIMDIER_SET1IE_Pos (9U)
7318 #define HRTIM_TIMDIER_SET1IE_Msk (0x1UL << HRTIM_TIMDIER_SET1IE_Pos) /*!< 0x00000200 */
7319 #define HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE_Msk /*!< Slave output 1 set interrupt enable */
7320 #define HRTIM_TIMDIER_RST1IE_Pos (10U)
7321 #define HRTIM_TIMDIER_RST1IE_Msk (0x1UL << HRTIM_TIMDIER_RST1IE_Pos) /*!< 0x00000400 */
7322 #define HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE_Msk /*!< Slave output 1 reset interrupt enable */
7323 #define HRTIM_TIMDIER_SET2IE_Pos (11U)
7324 #define HRTIM_TIMDIER_SET2IE_Msk (0x1UL << HRTIM_TIMDIER_SET2IE_Pos) /*!< 0x00000800 */
7325 #define HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE_Msk /*!< Slave output 2 set interrupt enable */
7326 #define HRTIM_TIMDIER_RST2IE_Pos (12U)
7327 #define HRTIM_TIMDIER_RST2IE_Msk (0x1UL << HRTIM_TIMDIER_RST2IE_Pos) /*!< 0x00001000 */
7328 #define HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE_Msk /*!< Slave output 2 reset interrupt enable */
7329 #define HRTIM_TIMDIER_RSTIE_Pos (13U)
7330 #define HRTIM_TIMDIER_RSTIE_Msk (0x1UL << HRTIM_TIMDIER_RSTIE_Pos) /*!< 0x00002000 */
7331 #define HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE_Msk /*!< Slave reset interrupt enable */
7332 #define HRTIM_TIMDIER_DLYPRTIE_Pos (14U)
7333 #define HRTIM_TIMDIER_DLYPRTIE_Msk (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos) /*!< 0x00004000 */
7334 #define HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE_Msk /*!< Slave delay protection interrupt enable */
7335
7336 #define HRTIM_TIMDIER_CMP1DE_Pos (16U)
7337 #define HRTIM_TIMDIER_CMP1DE_Msk (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos) /*!< 0x00010000 */
7338 #define HRTIM_TIMDIER_CMP1DE HRTIM_TIMDIER_CMP1DE_Msk /*!< Slave compare 1 request enable */
7339 #define HRTIM_TIMDIER_CMP2DE_Pos (17U)
7340 #define HRTIM_TIMDIER_CMP2DE_Msk (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos) /*!< 0x00020000 */
7341 #define HRTIM_TIMDIER_CMP2DE HRTIM_TIMDIER_CMP2DE_Msk /*!< Slave compare 2 request enable */
7342 #define HRTIM_TIMDIER_CMP3DE_Pos (18U)
7343 #define HRTIM_TIMDIER_CMP3DE_Msk (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos) /*!< 0x00040000 */
7344 #define HRTIM_TIMDIER_CMP3DE HRTIM_TIMDIER_CMP3DE_Msk /*!< Slave compare 3 request enable */
7345 #define HRTIM_TIMDIER_CMP4DE_Pos (19U)
7346 #define HRTIM_TIMDIER_CMP4DE_Msk (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos) /*!< 0x00080000 */
7347 #define HRTIM_TIMDIER_CMP4DE HRTIM_TIMDIER_CMP4DE_Msk /*!< Slave compare 4 request enable */
7348 #define HRTIM_TIMDIER_REPDE_Pos (20U)
7349 #define HRTIM_TIMDIER_REPDE_Msk (0x1UL << HRTIM_TIMDIER_REPDE_Pos) /*!< 0x00100000 */
7350 #define HRTIM_TIMDIER_REPDE HRTIM_TIMDIER_REPDE_Msk /*!< Slave repetition request enable */
7351 #define HRTIM_TIMDIER_UPDDE_Pos (22U)
7352 #define HRTIM_TIMDIER_UPDDE_Msk (0x1UL << HRTIM_TIMDIER_UPDDE_Pos) /*!< 0x00400000 */
7353 #define HRTIM_TIMDIER_UPDDE HRTIM_TIMDIER_UPDDE_Msk /*!< Slave update request enable */
7354 #define HRTIM_TIMDIER_CPT1DE_Pos (23U)
7355 #define HRTIM_TIMDIER_CPT1DE_Msk (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos) /*!< 0x00800000 */
7356 #define HRTIM_TIMDIER_CPT1DE HRTIM_TIMDIER_CPT1DE_Msk /*!< Slave capture 1 request enable */
7357 #define HRTIM_TIMDIER_CPT2DE_Pos (24U)
7358 #define HRTIM_TIMDIER_CPT2DE_Msk (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos) /*!< 0x01000000 */
7359 #define HRTIM_TIMDIER_CPT2DE HRTIM_TIMDIER_CPT2DE_Msk /*!< Slave capture 2 request enable */
7360 #define HRTIM_TIMDIER_SET1DE_Pos (25U)
7361 #define HRTIM_TIMDIER_SET1DE_Msk (0x1UL << HRTIM_TIMDIER_SET1DE_Pos) /*!< 0x02000000 */
7362 #define HRTIM_TIMDIER_SET1DE HRTIM_TIMDIER_SET1DE_Msk /*!< Slave output 1 set request enable */
7363 #define HRTIM_TIMDIER_RST1DE_Pos (26U)
7364 #define HRTIM_TIMDIER_RST1DE_Msk (0x1UL << HRTIM_TIMDIER_RST1DE_Pos) /*!< 0x04000000 */
7365 #define HRTIM_TIMDIER_RST1DE HRTIM_TIMDIER_RST1DE_Msk /*!< Slave output 1 reset request enable */
7366 #define HRTIM_TIMDIER_SET2DE_Pos (27U)
7367 #define HRTIM_TIMDIER_SET2DE_Msk (0x1UL << HRTIM_TIMDIER_SET2DE_Pos) /*!< 0x08000000 */
7368 #define HRTIM_TIMDIER_SET2DE HRTIM_TIMDIER_SET2DE_Msk /*!< Slave output 2 set request enable */
7369 #define HRTIM_TIMDIER_RST2DE_Pos (28U)
7370 #define HRTIM_TIMDIER_RST2DE_Msk (0x1UL << HRTIM_TIMDIER_RST2DE_Pos) /*!< 0x10000000 */
7371 #define HRTIM_TIMDIER_RST2DE HRTIM_TIMDIER_RST2DE_Msk /*!< Slave output 2 reset request enable */
7372 #define HRTIM_TIMDIER_RSTDE_Pos (29U)
7373 #define HRTIM_TIMDIER_RSTDE_Msk (0x1UL << HRTIM_TIMDIER_RSTDE_Pos) /*!< 0x20000000 */
7374 #define HRTIM_TIMDIER_RSTDE HRTIM_TIMDIER_RSTDE_Msk /*!< Slave reset request enable */
7375 #define HRTIM_TIMDIER_DLYPRTDE_Pos (30U)
7376 #define HRTIM_TIMDIER_DLYPRTDE_Msk (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos) /*!< 0x40000000 */
7377 #define HRTIM_TIMDIER_DLYPRTDE HRTIM_TIMDIER_DLYPRTDE_Msk /*!< Slavedelay protection request enable */
7378
7379 /****************** Bit definition for HRTIM_CNTR register ****************/
7380 #define HRTIM_CNTR_CNTR_Pos (0U)
7381 #define HRTIM_CNTR_CNTR_Msk (0x0000FFFFUL << HRTIM_CNTR_CNTR_Pos) /*!< 0x0000FFFF */
7382 #define HRTIM_CNTR_CNTR HRTIM_CNTR_CNTR_Msk /*!< Counter Value */
7383
7384 /******************* Bit definition for HRTIM_PER register *****************/
7385 #define HRTIM_PER_PER_Pos (0U)
7386 #define HRTIM_PER_PER_Msk (0x0000FFFFUL << HRTIM_PER_PER_Pos) /*!< 0x0000FFFF */
7387 #define HRTIM_PER_PER HRTIM_PER_PER_Msk /*!< Period Value */
7388
7389 /******************* Bit definition for HRTIM_REP register *****************/
7390 #define HRTIM_REP_REP_Pos (0U)
7391 #define HRTIM_REP_REP_Msk (0x000000FFUL << HRTIM_REP_REP_Pos) /*!< 0x000000FF */
7392 #define HRTIM_REP_REP HRTIM_REP_REP_Msk /*!< Repetition Value */
7393
7394 /******************* Bit definition for HRTIM_CMP1R register *****************/
7395 #define HRTIM_CMP1R_CMP1R_Pos (0U)
7396 #define HRTIM_CMP1R_CMP1R_Msk (0x0000FFFFUL << HRTIM_CMP1R_CMP1R_Pos) /*!< 0x0000FFFF */
7397 #define HRTIM_CMP1R_CMP1R HRTIM_CMP1R_CMP1R_Msk /*!< Compare Value */
7398
7399 /******************* Bit definition for HRTIM_CMP1CR register *****************/
7400 #define HRTIM_CMP1CR_CMP1CR_Pos (0U)
7401 #define HRTIM_CMP1CR_CMP1CR_Msk (0x0000FFFFUL << HRTIM_CMP1CR_CMP1CR_Pos)/*!< 0x0000FFFF */
7402 #define HRTIM_CMP1CR_CMP1CR HRTIM_CMP1CR_CMP1CR_Msk /*!< Compare Value */
7403
7404 /******************* Bit definition for HRTIM_CMP2R register *****************/
7405 #define HRTIM_CMP2R_CMP2R_Pos (0U)
7406 #define HRTIM_CMP2R_CMP2R_Msk (0x0000FFFFUL << HRTIM_CMP2R_CMP2R_Pos) /*!< 0x0000FFFF */
7407 #define HRTIM_CMP2R_CMP2R HRTIM_CMP2R_CMP2R_Msk /*!< Compare Value */
7408
7409 /******************* Bit definition for HRTIM_CMP3R register *****************/
7410 #define HRTIM_CMP3R_CMP3R_Pos (0U)
7411 #define HRTIM_CMP3R_CMP3R_Msk (0x0000FFFFUL << HRTIM_CMP3R_CMP3R_Pos) /*!< 0x0000FFFF */
7412 #define HRTIM_CMP3R_CMP3R HRTIM_CMP3R_CMP3R_Msk /*!< Compare Value */
7413
7414 /******************* Bit definition for HRTIM_CMP4R register *****************/
7415 #define HRTIM_CMP4R_CMP4R_Pos (0U)
7416 #define HRTIM_CMP4R_CMP4R_Msk (0x0000FFFFUL << HRTIM_CMP4R_CMP4R_Pos) /*!< 0x0000FFFF */
7417 #define HRTIM_CMP4R_CMP4R HRTIM_CMP4R_CMP4R_Msk /*!< Compare Value */
7418
7419 /******************* Bit definition for HRTIM_CPT1R register ****************/
7420 #define HRTIM_CPT1R_CPT1R_Pos (0U)
7421 #define HRTIM_CPT1R_CPT1R_Msk (0x0000FFFFUL << HRTIM_CPT1R_CPT1R_Pos) /*!< 0x0000FFFF */
7422 #define HRTIM_CPT1R_CPT1R HRTIM_CPT1R_CPT1R_Msk /*!< Capture 1 Value */
7423 #define HRTIM_CPT1R_DIR_Pos (16U)
7424 #define HRTIM_CPT1R_DIR_Msk (0x1UL << HRTIM_CPT1R_DIR_Pos) /*!< 0x00010000 */
7425 #define HRTIM_CPT1R_DIR HRTIM_CPT1R_DIR_Msk /*!< Capture 1 direction> */
7426
7427 /******************* Bit definition for HRTIM_CPT2R register ****************/
7428 #define HRTIM_CPT2R_CPT2R_Pos (0U)
7429 #define HRTIM_CPT2R_CPT2R_Msk (0x0000FFFFUL << HRTIM_CPT2R_CPT2R_Pos) /*!< 0x0000FFFF */
7430 #define HRTIM_CPT2R_CPT2R HRTIM_CPT2R_CPT2R_Msk /*!< Capture 2 Value */
7431 #define HRTIM_CPT2R_DIR_Pos (16U)
7432 #define HRTIM_CPT2R_DIR_Msk (0x1UL << HRTIM_CPT2R_DIR_Pos) /*!< 0x00010000 */
7433 #define HRTIM_CPT2R_DIR HRTIM_CPT2R_DIR_Msk /*!< Capture 2 direction */
7434
7435 /******************** Bit definition for Slave Deadtime register **************/
7436 #define HRTIM_DTR_DTR_Pos (0U)
7437 #define HRTIM_DTR_DTR_Msk (0x1FFUL << HRTIM_DTR_DTR_Pos) /*!< 0x000001FF */
7438 #define HRTIM_DTR_DTR HRTIM_DTR_DTR_Msk /*!< Dead time rising value */
7439 #define HRTIM_DTR_DTR_0 (0x001UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000001 */
7440 #define HRTIM_DTR_DTR_1 (0x002UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000002 */
7441 #define HRTIM_DTR_DTR_2 (0x004UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000004 */
7442 #define HRTIM_DTR_DTR_3 (0x008UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000008 */
7443 #define HRTIM_DTR_DTR_4 (0x010UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000010 */
7444 #define HRTIM_DTR_DTR_5 (0x020UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000020 */
7445 #define HRTIM_DTR_DTR_6 (0x040UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000040 */
7446 #define HRTIM_DTR_DTR_7 (0x080UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000080 */
7447 #define HRTIM_DTR_DTR_8 (0x100UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000100 */
7448 #define HRTIM_DTR_SDTR_Pos (9U)
7449 #define HRTIM_DTR_SDTR_Msk (0x1UL << HRTIM_DTR_SDTR_Pos) /*!< 0x00000200 */
7450 #define HRTIM_DTR_SDTR HRTIM_DTR_SDTR_Msk /*!< Sign dead time rising value */
7451 #define HRTIM_DTR_DTPRSC_Pos (10U)
7452 #define HRTIM_DTR_DTPRSC_Msk (0x7UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00001C00 */
7453 #define HRTIM_DTR_DTPRSC HRTIM_DTR_DTPRSC_Msk /*!< Dead time prescaler */
7454 #define HRTIM_DTR_DTPRSC_0 (0x1UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00000400 */
7455 #define HRTIM_DTR_DTPRSC_1 (0x2UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00000800 */
7456 #define HRTIM_DTR_DTPRSC_2 (0x4UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00001000 */
7457 #define HRTIM_DTR_DTRSLK_Pos (14U)
7458 #define HRTIM_DTR_DTRSLK_Msk (0x1UL << HRTIM_DTR_DTRSLK_Pos) /*!< 0x00004000 */
7459 #define HRTIM_DTR_DTRSLK HRTIM_DTR_DTRSLK_Msk /*!< Dead time rising sign lock */
7460 #define HRTIM_DTR_DTRLK_Pos (15U)
7461 #define HRTIM_DTR_DTRLK_Msk (0x1UL << HRTIM_DTR_DTRLK_Pos) /*!< 0x00008000 */
7462 #define HRTIM_DTR_DTRLK HRTIM_DTR_DTRLK_Msk /*!< Dead time rising lock */
7463 #define HRTIM_DTR_DTF_Pos (16U)
7464 #define HRTIM_DTR_DTF_Msk (0x1FFUL << HRTIM_DTR_DTF_Pos) /*!< 0x01FF0000 */
7465 #define HRTIM_DTR_DTF HRTIM_DTR_DTF_Msk /*!< Dead time falling value */
7466 #define HRTIM_DTR_DTF_0 (0x001UL << HRTIM_DTR_DTF_Pos) /*!< 0x00010000 */
7467 #define HRTIM_DTR_DTF_1 (0x002UL << HRTIM_DTR_DTF_Pos) /*!< 0x00020000 */
7468 #define HRTIM_DTR_DTF_2 (0x004UL << HRTIM_DTR_DTF_Pos) /*!< 0x00040000 */
7469 #define HRTIM_DTR_DTF_3 (0x008UL << HRTIM_DTR_DTF_Pos) /*!< 0x00080000 */
7470 #define HRTIM_DTR_DTF_4 (0x010UL << HRTIM_DTR_DTF_Pos) /*!< 0x00100000 */
7471 #define HRTIM_DTR_DTF_5 (0x020UL << HRTIM_DTR_DTF_Pos) /*!< 0x00200000 */
7472 #define HRTIM_DTR_DTF_6 (0x040UL << HRTIM_DTR_DTF_Pos) /*!< 0x00400000 */
7473 #define HRTIM_DTR_DTF_7 (0x080UL << HRTIM_DTR_DTF_Pos) /*!< 0x00800000 */
7474 #define HRTIM_DTR_DTF_8 (0x100UL << HRTIM_DTR_DTF_Pos) /*!< 0x01000000 */
7475 #define HRTIM_DTR_SDTF_Pos (25U)
7476 #define HRTIM_DTR_SDTF_Msk (0x1UL << HRTIM_DTR_SDTF_Pos) /*!< 0x02000000 */
7477 #define HRTIM_DTR_SDTF HRTIM_DTR_SDTF_Msk /*!< Sign dead time falling value */
7478 #define HRTIM_DTR_DTFSLK_Pos (30U)
7479 #define HRTIM_DTR_DTFSLK_Msk (0x1UL << HRTIM_DTR_DTFSLK_Pos) /*!< 0x40000000 */
7480 #define HRTIM_DTR_DTFSLK HRTIM_DTR_DTFSLK_Msk /*!< Dead time falling sign lock */
7481 #define HRTIM_DTR_DTFLK_Pos (31U)
7482 #define HRTIM_DTR_DTFLK_Msk (0x1UL << HRTIM_DTR_DTFLK_Pos) /*!< 0x80000000 */
7483 #define HRTIM_DTR_DTFLK HRTIM_DTR_DTFLK_Msk /*!< Dead time falling lock */
7484
7485 /**** Bit definition for Slave Output 1 set register **************************/
7486 #define HRTIM_SET1R_SST_Pos (0U)
7487 #define HRTIM_SET1R_SST_Msk (0x1UL << HRTIM_SET1R_SST_Pos) /*!< 0x00000001 */
7488 #define HRTIM_SET1R_SST HRTIM_SET1R_SST_Msk /*!< software set trigger */
7489 #define HRTIM_SET1R_RESYNC_Pos (1U)
7490 #define HRTIM_SET1R_RESYNC_Msk (0x1UL << HRTIM_SET1R_RESYNC_Pos) /*!< 0x00000002 */
7491 #define HRTIM_SET1R_RESYNC HRTIM_SET1R_RESYNC_Msk /*!< Timer A resynchronization */
7492 #define HRTIM_SET1R_PER_Pos (2U)
7493 #define HRTIM_SET1R_PER_Msk (0x1UL << HRTIM_SET1R_PER_Pos) /*!< 0x00000004 */
7494 #define HRTIM_SET1R_PER HRTIM_SET1R_PER_Msk /*!< Timer A period */
7495 #define HRTIM_SET1R_CMP1_Pos (3U)
7496 #define HRTIM_SET1R_CMP1_Msk (0x1UL << HRTIM_SET1R_CMP1_Pos) /*!< 0x00000008 */
7497 #define HRTIM_SET1R_CMP1 HRTIM_SET1R_CMP1_Msk /*!< Timer A compare 1 */
7498 #define HRTIM_SET1R_CMP2_Pos (4U)
7499 #define HRTIM_SET1R_CMP2_Msk (0x1UL << HRTIM_SET1R_CMP2_Pos) /*!< 0x00000010 */
7500 #define HRTIM_SET1R_CMP2 HRTIM_SET1R_CMP2_Msk /*!< Timer A compare 2 */
7501 #define HRTIM_SET1R_CMP3_Pos (5U)
7502 #define HRTIM_SET1R_CMP3_Msk (0x1UL << HRTIM_SET1R_CMP3_Pos) /*!< 0x00000020 */
7503 #define HRTIM_SET1R_CMP3 HRTIM_SET1R_CMP3_Msk /*!< Timer A compare 3 */
7504 #define HRTIM_SET1R_CMP4_Pos (6U)
7505 #define HRTIM_SET1R_CMP4_Msk (0x1UL << HRTIM_SET1R_CMP4_Pos) /*!< 0x00000040 */
7506 #define HRTIM_SET1R_CMP4 HRTIM_SET1R_CMP4_Msk /*!< Timer A compare 4 */
7507
7508 #define HRTIM_SET1R_MSTPER_Pos (7U)
7509 #define HRTIM_SET1R_MSTPER_Msk (0x1UL << HRTIM_SET1R_MSTPER_Pos) /*!< 0x00000080 */
7510 #define HRTIM_SET1R_MSTPER HRTIM_SET1R_MSTPER_Msk /*!< Master period */
7511 #define HRTIM_SET1R_MSTCMP1_Pos (8U)
7512 #define HRTIM_SET1R_MSTCMP1_Msk (0x1UL << HRTIM_SET1R_MSTCMP1_Pos) /*!< 0x00000100 */
7513 #define HRTIM_SET1R_MSTCMP1 HRTIM_SET1R_MSTCMP1_Msk /*!< Master compare 1 */
7514 #define HRTIM_SET1R_MSTCMP2_Pos (9U)
7515 #define HRTIM_SET1R_MSTCMP2_Msk (0x1UL << HRTIM_SET1R_MSTCMP2_Pos) /*!< 0x00000200 */
7516 #define HRTIM_SET1R_MSTCMP2 HRTIM_SET1R_MSTCMP2_Msk /*!< Master compare 2 */
7517 #define HRTIM_SET1R_MSTCMP3_Pos (10U)
7518 #define HRTIM_SET1R_MSTCMP3_Msk (0x1UL << HRTIM_SET1R_MSTCMP3_Pos) /*!< 0x00000400 */
7519 #define HRTIM_SET1R_MSTCMP3 HRTIM_SET1R_MSTCMP3_Msk /*!< Master compare 3 */
7520 #define HRTIM_SET1R_MSTCMP4_Pos (11U)
7521 #define HRTIM_SET1R_MSTCMP4_Msk (0x1UL << HRTIM_SET1R_MSTCMP4_Pos) /*!< 0x00000800 */
7522 #define HRTIM_SET1R_MSTCMP4 HRTIM_SET1R_MSTCMP4_Msk /*!< Master compare 4 */
7523
7524 #define HRTIM_SET1R_TIMEVNT1_Pos (12U)
7525 #define HRTIM_SET1R_TIMEVNT1_Msk (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos) /*!< 0x00001000 */
7526 #define HRTIM_SET1R_TIMEVNT1 HRTIM_SET1R_TIMEVNT1_Msk /*!< Timer event 1 */
7527 #define HRTIM_SET1R_TIMEVNT2_Pos (13U)
7528 #define HRTIM_SET1R_TIMEVNT2_Msk (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos) /*!< 0x00002000 */
7529 #define HRTIM_SET1R_TIMEVNT2 HRTIM_SET1R_TIMEVNT2_Msk /*!< Timer event 2 */
7530 #define HRTIM_SET1R_TIMEVNT3_Pos (14U)
7531 #define HRTIM_SET1R_TIMEVNT3_Msk (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos) /*!< 0x00004000 */
7532 #define HRTIM_SET1R_TIMEVNT3 HRTIM_SET1R_TIMEVNT3_Msk /*!< Timer event 3 */
7533 #define HRTIM_SET1R_TIMEVNT4_Pos (15U)
7534 #define HRTIM_SET1R_TIMEVNT4_Msk (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos) /*!< 0x00008000 */
7535 #define HRTIM_SET1R_TIMEVNT4 HRTIM_SET1R_TIMEVNT4_Msk /*!< Timer event 4 */
7536 #define HRTIM_SET1R_TIMEVNT5_Pos (16U)
7537 #define HRTIM_SET1R_TIMEVNT5_Msk (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos) /*!< 0x00010000 */
7538 #define HRTIM_SET1R_TIMEVNT5 HRTIM_SET1R_TIMEVNT5_Msk /*!< Timer event 5 */
7539 #define HRTIM_SET1R_TIMEVNT6_Pos (17U)
7540 #define HRTIM_SET1R_TIMEVNT6_Msk (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos) /*!< 0x00020000 */
7541 #define HRTIM_SET1R_TIMEVNT6 HRTIM_SET1R_TIMEVNT6_Msk /*!< Timer event 6 */
7542 #define HRTIM_SET1R_TIMEVNT7_Pos (18U)
7543 #define HRTIM_SET1R_TIMEVNT7_Msk (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos) /*!< 0x00040000 */
7544 #define HRTIM_SET1R_TIMEVNT7 HRTIM_SET1R_TIMEVNT7_Msk /*!< Timer event 7 */
7545 #define HRTIM_SET1R_TIMEVNT8_Pos (19U)
7546 #define HRTIM_SET1R_TIMEVNT8_Msk (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos) /*!< 0x00080000 */
7547 #define HRTIM_SET1R_TIMEVNT8 HRTIM_SET1R_TIMEVNT8_Msk /*!< Timer event 8 */
7548 #define HRTIM_SET1R_TIMEVNT9_Pos (20U)
7549 #define HRTIM_SET1R_TIMEVNT9_Msk (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos) /*!< 0x00100000 */
7550 #define HRTIM_SET1R_TIMEVNT9 HRTIM_SET1R_TIMEVNT9_Msk /*!< Timer event 9 */
7551
7552 #define HRTIM_SET1R_EXTVNT1_Pos (21U)
7553 #define HRTIM_SET1R_EXTVNT1_Msk (0x1UL << HRTIM_SET1R_EXTVNT1_Pos) /*!< 0x00200000 */
7554 #define HRTIM_SET1R_EXTVNT1 HRTIM_SET1R_EXTVNT1_Msk /*!< External event 1 */
7555 #define HRTIM_SET1R_EXTVNT2_Pos (22U)
7556 #define HRTIM_SET1R_EXTVNT2_Msk (0x1UL << HRTIM_SET1R_EXTVNT2_Pos) /*!< 0x00400000 */
7557 #define HRTIM_SET1R_EXTVNT2 HRTIM_SET1R_EXTVNT2_Msk /*!< External event 2 */
7558 #define HRTIM_SET1R_EXTVNT3_Pos (23U)
7559 #define HRTIM_SET1R_EXTVNT3_Msk (0x1UL << HRTIM_SET1R_EXTVNT3_Pos) /*!< 0x00800000 */
7560 #define HRTIM_SET1R_EXTVNT3 HRTIM_SET1R_EXTVNT3_Msk /*!< External event 3 */
7561 #define HRTIM_SET1R_EXTVNT4_Pos (24U)
7562 #define HRTIM_SET1R_EXTVNT4_Msk (0x1UL << HRTIM_SET1R_EXTVNT4_Pos) /*!< 0x01000000 */
7563 #define HRTIM_SET1R_EXTVNT4 HRTIM_SET1R_EXTVNT4_Msk /*!< External event 4 */
7564 #define HRTIM_SET1R_EXTVNT5_Pos (25U)
7565 #define HRTIM_SET1R_EXTVNT5_Msk (0x1UL << HRTIM_SET1R_EXTVNT5_Pos) /*!< 0x02000000 */
7566 #define HRTIM_SET1R_EXTVNT5 HRTIM_SET1R_EXTVNT5_Msk /*!< External event 5 */
7567 #define HRTIM_SET1R_EXTVNT6_Pos (26U)
7568 #define HRTIM_SET1R_EXTVNT6_Msk (0x1UL << HRTIM_SET1R_EXTVNT6_Pos) /*!< 0x04000000 */
7569 #define HRTIM_SET1R_EXTVNT6 HRTIM_SET1R_EXTVNT6_Msk /*!< External event 6 */
7570 #define HRTIM_SET1R_EXTVNT7_Pos (27U)
7571 #define HRTIM_SET1R_EXTVNT7_Msk (0x1UL << HRTIM_SET1R_EXTVNT7_Pos) /*!< 0x08000000 */
7572 #define HRTIM_SET1R_EXTVNT7 HRTIM_SET1R_EXTVNT7_Msk /*!< External event 7 */
7573 #define HRTIM_SET1R_EXTVNT8_Pos (28U)
7574 #define HRTIM_SET1R_EXTVNT8_Msk (0x1UL << HRTIM_SET1R_EXTVNT8_Pos) /*!< 0x10000000 */
7575 #define HRTIM_SET1R_EXTVNT8 HRTIM_SET1R_EXTVNT8_Msk /*!< External event 8 */
7576 #define HRTIM_SET1R_EXTVNT9_Pos (29U)
7577 #define HRTIM_SET1R_EXTVNT9_Msk (0x1UL << HRTIM_SET1R_EXTVNT9_Pos) /*!< 0x20000000 */
7578 #define HRTIM_SET1R_EXTVNT9 HRTIM_SET1R_EXTVNT9_Msk /*!< External event 9 */
7579 #define HRTIM_SET1R_EXTVNT10_Pos (30U)
7580 #define HRTIM_SET1R_EXTVNT10_Msk (0x1UL << HRTIM_SET1R_EXTVNT10_Pos) /*!< 0x40000000 */
7581 #define HRTIM_SET1R_EXTVNT10 HRTIM_SET1R_EXTVNT10_Msk /*!< External event 10 */
7582
7583 #define HRTIM_SET1R_UPDATE_Pos (31U)
7584 #define HRTIM_SET1R_UPDATE_Msk (0x1UL << HRTIM_SET1R_UPDATE_Pos) /*!< 0x80000000 */
7585 #define HRTIM_SET1R_UPDATE HRTIM_SET1R_UPDATE_Msk /*!< Register update (transfer preload to active) */
7586
7587 /**** Bit definition for Slave Output 1 reset register ************************/
7588 #define HRTIM_RST1R_SRT_Pos (0U)
7589 #define HRTIM_RST1R_SRT_Msk (0x1UL << HRTIM_RST1R_SRT_Pos) /*!< 0x00000001 */
7590 #define HRTIM_RST1R_SRT HRTIM_RST1R_SRT_Msk /*!< software reset trigger */
7591 #define HRTIM_RST1R_RESYNC_Pos (1U)
7592 #define HRTIM_RST1R_RESYNC_Msk (0x1UL << HRTIM_RST1R_RESYNC_Pos) /*!< 0x00000002 */
7593 #define HRTIM_RST1R_RESYNC HRTIM_RST1R_RESYNC_Msk /*!< Timer A resynchronization */
7594 #define HRTIM_RST1R_PER_Pos (2U)
7595 #define HRTIM_RST1R_PER_Msk (0x1UL << HRTIM_RST1R_PER_Pos) /*!< 0x00000004 */
7596 #define HRTIM_RST1R_PER HRTIM_RST1R_PER_Msk /*!< Timer A period */
7597 #define HRTIM_RST1R_CMP1_Pos (3U)
7598 #define HRTIM_RST1R_CMP1_Msk (0x1UL << HRTIM_RST1R_CMP1_Pos) /*!< 0x00000008 */
7599 #define HRTIM_RST1R_CMP1 HRTIM_RST1R_CMP1_Msk /*!< Timer A compare 1 */
7600 #define HRTIM_RST1R_CMP2_Pos (4U)
7601 #define HRTIM_RST1R_CMP2_Msk (0x1UL << HRTIM_RST1R_CMP2_Pos) /*!< 0x00000010 */
7602 #define HRTIM_RST1R_CMP2 HRTIM_RST1R_CMP2_Msk /*!< Timer A compare 2 */
7603 #define HRTIM_RST1R_CMP3_Pos (5U)
7604 #define HRTIM_RST1R_CMP3_Msk (0x1UL << HRTIM_RST1R_CMP3_Pos) /*!< 0x00000020 */
7605 #define HRTIM_RST1R_CMP3 HRTIM_RST1R_CMP3_Msk /*!< Timer A compare 3 */
7606 #define HRTIM_RST1R_CMP4_Pos (6U)
7607 #define HRTIM_RST1R_CMP4_Msk (0x1UL << HRTIM_RST1R_CMP4_Pos) /*!< 0x00000040 */
7608 #define HRTIM_RST1R_CMP4 HRTIM_RST1R_CMP4_Msk /*!< Timer A compare 4 */
7609
7610 #define HRTIM_RST1R_MSTPER_Pos (7U)
7611 #define HRTIM_RST1R_MSTPER_Msk (0x1UL << HRTIM_RST1R_MSTPER_Pos) /*!< 0x00000080 */
7612 #define HRTIM_RST1R_MSTPER HRTIM_RST1R_MSTPER_Msk /*!< Master period */
7613 #define HRTIM_RST1R_MSTCMP1_Pos (8U)
7614 #define HRTIM_RST1R_MSTCMP1_Msk (0x1UL << HRTIM_RST1R_MSTCMP1_Pos) /*!< 0x00000100 */
7615 #define HRTIM_RST1R_MSTCMP1 HRTIM_RST1R_MSTCMP1_Msk /*!< Master compare 1 */
7616 #define HRTIM_RST1R_MSTCMP2_Pos (9U)
7617 #define HRTIM_RST1R_MSTCMP2_Msk (0x1UL << HRTIM_RST1R_MSTCMP2_Pos) /*!< 0x00000200 */
7618 #define HRTIM_RST1R_MSTCMP2 HRTIM_RST1R_MSTCMP2_Msk /*!< Master compare 2 */
7619 #define HRTIM_RST1R_MSTCMP3_Pos (10U)
7620 #define HRTIM_RST1R_MSTCMP3_Msk (0x1UL << HRTIM_RST1R_MSTCMP3_Pos) /*!< 0x00000400 */
7621 #define HRTIM_RST1R_MSTCMP3 HRTIM_RST1R_MSTCMP3_Msk /*!< Master compare 3 */
7622 #define HRTIM_RST1R_MSTCMP4_Pos (11U)
7623 #define HRTIM_RST1R_MSTCMP4_Msk (0x1UL << HRTIM_RST1R_MSTCMP4_Pos) /*!< 0x00000800 */
7624 #define HRTIM_RST1R_MSTCMP4 HRTIM_RST1R_MSTCMP4_Msk /*!< Master compare 4 */
7625
7626 #define HRTIM_RST1R_TIMEVNT1_Pos (12U)
7627 #define HRTIM_RST1R_TIMEVNT1_Msk (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos) /*!< 0x00001000 */
7628 #define HRTIM_RST1R_TIMEVNT1 HRTIM_RST1R_TIMEVNT1_Msk /*!< Timer event 1 */
7629 #define HRTIM_RST1R_TIMEVNT2_Pos (13U)
7630 #define HRTIM_RST1R_TIMEVNT2_Msk (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos) /*!< 0x00002000 */
7631 #define HRTIM_RST1R_TIMEVNT2 HRTIM_RST1R_TIMEVNT2_Msk /*!< Timer event 2 */
7632 #define HRTIM_RST1R_TIMEVNT3_Pos (14U)
7633 #define HRTIM_RST1R_TIMEVNT3_Msk (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos) /*!< 0x00004000 */
7634 #define HRTIM_RST1R_TIMEVNT3 HRTIM_RST1R_TIMEVNT3_Msk /*!< Timer event 3 */
7635 #define HRTIM_RST1R_TIMEVNT4_Pos (15U)
7636 #define HRTIM_RST1R_TIMEVNT4_Msk (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos) /*!< 0x00008000 */
7637 #define HRTIM_RST1R_TIMEVNT4 HRTIM_RST1R_TIMEVNT4_Msk /*!< Timer event 4 */
7638 #define HRTIM_RST1R_TIMEVNT5_Pos (16U)
7639 #define HRTIM_RST1R_TIMEVNT5_Msk (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos) /*!< 0x00010000 */
7640 #define HRTIM_RST1R_TIMEVNT5 HRTIM_RST1R_TIMEVNT5_Msk /*!< Timer event 5 */
7641 #define HRTIM_RST1R_TIMEVNT6_Pos (17U)
7642 #define HRTIM_RST1R_TIMEVNT6_Msk (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos) /*!< 0x00020000 */
7643 #define HRTIM_RST1R_TIMEVNT6 HRTIM_RST1R_TIMEVNT6_Msk /*!< Timer event 6 */
7644 #define HRTIM_RST1R_TIMEVNT7_Pos (18U)
7645 #define HRTIM_RST1R_TIMEVNT7_Msk (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos) /*!< 0x00040000 */
7646 #define HRTIM_RST1R_TIMEVNT7 HRTIM_RST1R_TIMEVNT7_Msk /*!< Timer event 7 */
7647 #define HRTIM_RST1R_TIMEVNT8_Pos (19U)
7648 #define HRTIM_RST1R_TIMEVNT8_Msk (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos) /*!< 0x00080000 */
7649 #define HRTIM_RST1R_TIMEVNT8 HRTIM_RST1R_TIMEVNT8_Msk /*!< Timer event 8 */
7650 #define HRTIM_RST1R_TIMEVNT9_Pos (20U)
7651 #define HRTIM_RST1R_TIMEVNT9_Msk (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos) /*!< 0x00100000 */
7652 #define HRTIM_RST1R_TIMEVNT9 HRTIM_RST1R_TIMEVNT9_Msk /*!< Timer event 9 */
7653
7654 #define HRTIM_RST1R_EXTVNT1_Pos (21U)
7655 #define HRTIM_RST1R_EXTVNT1_Msk (0x1UL << HRTIM_RST1R_EXTVNT1_Pos) /*!< 0x00200000 */
7656 #define HRTIM_RST1R_EXTVNT1 HRTIM_RST1R_EXTVNT1_Msk /*!< External event 1 */
7657 #define HRTIM_RST1R_EXTVNT2_Pos (22U)
7658 #define HRTIM_RST1R_EXTVNT2_Msk (0x1UL << HRTIM_RST1R_EXTVNT2_Pos) /*!< 0x00400000 */
7659 #define HRTIM_RST1R_EXTVNT2 HRTIM_RST1R_EXTVNT2_Msk /*!< External event 2 */
7660 #define HRTIM_RST1R_EXTVNT3_Pos (23U)
7661 #define HRTIM_RST1R_EXTVNT3_Msk (0x1UL << HRTIM_RST1R_EXTVNT3_Pos) /*!< 0x00800000 */
7662 #define HRTIM_RST1R_EXTVNT3 HRTIM_RST1R_EXTVNT3_Msk /*!< External event 3 */
7663 #define HRTIM_RST1R_EXTVNT4_Pos (24U)
7664 #define HRTIM_RST1R_EXTVNT4_Msk (0x1UL << HRTIM_RST1R_EXTVNT4_Pos) /*!< 0x01000000 */
7665 #define HRTIM_RST1R_EXTVNT4 HRTIM_RST1R_EXTVNT4_Msk /*!< External event 4 */
7666 #define HRTIM_RST1R_EXTVNT5_Pos (25U)
7667 #define HRTIM_RST1R_EXTVNT5_Msk (0x1UL << HRTIM_RST1R_EXTVNT5_Pos) /*!< 0x02000000 */
7668 #define HRTIM_RST1R_EXTVNT5 HRTIM_RST1R_EXTVNT5_Msk /*!< External event 5 */
7669 #define HRTIM_RST1R_EXTVNT6_Pos (26U)
7670 #define HRTIM_RST1R_EXTVNT6_Msk (0x1UL << HRTIM_RST1R_EXTVNT6_Pos) /*!< 0x04000000 */
7671 #define HRTIM_RST1R_EXTVNT6 HRTIM_RST1R_EXTVNT6_Msk /*!< External event 6 */
7672 #define HRTIM_RST1R_EXTVNT7_Pos (27U)
7673 #define HRTIM_RST1R_EXTVNT7_Msk (0x1UL << HRTIM_RST1R_EXTVNT7_Pos) /*!< 0x08000000 */
7674 #define HRTIM_RST1R_EXTVNT7 HRTIM_RST1R_EXTVNT7_Msk /*!< External event 7 */
7675 #define HRTIM_RST1R_EXTVNT8_Pos (28U)
7676 #define HRTIM_RST1R_EXTVNT8_Msk (0x1UL << HRTIM_RST1R_EXTVNT8_Pos) /*!< 0x10000000 */
7677 #define HRTIM_RST1R_EXTVNT8 HRTIM_RST1R_EXTVNT8_Msk /*!< External event 8 */
7678 #define HRTIM_RST1R_EXTVNT9_Pos (29U)
7679 #define HRTIM_RST1R_EXTVNT9_Msk (0x1UL << HRTIM_RST1R_EXTVNT9_Pos) /*!< 0x20000000 */
7680 #define HRTIM_RST1R_EXTVNT9 HRTIM_RST1R_EXTVNT9_Msk /*!< External event 9 */
7681 #define HRTIM_RST1R_EXTVNT10_Pos (30U)
7682 #define HRTIM_RST1R_EXTVNT10_Msk (0x1UL << HRTIM_RST1R_EXTVNT10_Pos) /*!< 0x40000000 */
7683 #define HRTIM_RST1R_EXTVNT10 HRTIM_RST1R_EXTVNT10_Msk /*!< External event 10 */
7684 #define HRTIM_RST1R_UPDATE_Pos (31U)
7685 #define HRTIM_RST1R_UPDATE_Msk (0x1UL << HRTIM_RST1R_UPDATE_Pos) /*!< 0x80000000 */
7686 #define HRTIM_RST1R_UPDATE HRTIM_RST1R_UPDATE_Msk /*!< Register update (transfer preload to active) */
7687
7688 /**** Bit definition for Slave Output 2 set register **************************/
7689 #define HRTIM_SET2R_SST_Pos (0U)
7690 #define HRTIM_SET2R_SST_Msk (0x1UL << HRTIM_SET2R_SST_Pos) /*!< 0x00000001 */
7691 #define HRTIM_SET2R_SST HRTIM_SET2R_SST_Msk /*!< software set trigger */
7692 #define HRTIM_SET2R_RESYNC_Pos (1U)
7693 #define HRTIM_SET2R_RESYNC_Msk (0x1UL << HRTIM_SET2R_RESYNC_Pos) /*!< 0x00000002 */
7694 #define HRTIM_SET2R_RESYNC HRTIM_SET2R_RESYNC_Msk /*!< Timer A resynchronization */
7695 #define HRTIM_SET2R_PER_Pos (2U)
7696 #define HRTIM_SET2R_PER_Msk (0x1UL << HRTIM_SET2R_PER_Pos) /*!< 0x00000004 */
7697 #define HRTIM_SET2R_PER HRTIM_SET2R_PER_Msk /*!< Timer A period */
7698 #define HRTIM_SET2R_CMP1_Pos (3U)
7699 #define HRTIM_SET2R_CMP1_Msk (0x1UL << HRTIM_SET2R_CMP1_Pos) /*!< 0x00000008 */
7700 #define HRTIM_SET2R_CMP1 HRTIM_SET2R_CMP1_Msk /*!< Timer A compare 1 */
7701 #define HRTIM_SET2R_CMP2_Pos (4U)
7702 #define HRTIM_SET2R_CMP2_Msk (0x1UL << HRTIM_SET2R_CMP2_Pos) /*!< 0x00000010 */
7703 #define HRTIM_SET2R_CMP2 HRTIM_SET2R_CMP2_Msk /*!< Timer A compare 2 */
7704 #define HRTIM_SET2R_CMP3_Pos (5U)
7705 #define HRTIM_SET2R_CMP3_Msk (0x1UL << HRTIM_SET2R_CMP3_Pos) /*!< 0x00000020 */
7706 #define HRTIM_SET2R_CMP3 HRTIM_SET2R_CMP3_Msk /*!< Timer A compare 3 */
7707 #define HRTIM_SET2R_CMP4_Pos (6U)
7708 #define HRTIM_SET2R_CMP4_Msk (0x1UL << HRTIM_SET2R_CMP4_Pos) /*!< 0x00000040 */
7709 #define HRTIM_SET2R_CMP4 HRTIM_SET2R_CMP4_Msk /*!< Timer A compare 4 */
7710
7711 #define HRTIM_SET2R_MSTPER_Pos (7U)
7712 #define HRTIM_SET2R_MSTPER_Msk (0x1UL << HRTIM_SET2R_MSTPER_Pos) /*!< 0x00000080 */
7713 #define HRTIM_SET2R_MSTPER HRTIM_SET2R_MSTPER_Msk /*!< Master period */
7714 #define HRTIM_SET2R_MSTCMP1_Pos (8U)
7715 #define HRTIM_SET2R_MSTCMP1_Msk (0x1UL << HRTIM_SET2R_MSTCMP1_Pos) /*!< 0x00000100 */
7716 #define HRTIM_SET2R_MSTCMP1 HRTIM_SET2R_MSTCMP1_Msk /*!< Master compare 1 */
7717 #define HRTIM_SET2R_MSTCMP2_Pos (9U)
7718 #define HRTIM_SET2R_MSTCMP2_Msk (0x1UL << HRTIM_SET2R_MSTCMP2_Pos) /*!< 0x00000200 */
7719 #define HRTIM_SET2R_MSTCMP2 HRTIM_SET2R_MSTCMP2_Msk /*!< Master compare 2 */
7720 #define HRTIM_SET2R_MSTCMP3_Pos (10U)
7721 #define HRTIM_SET2R_MSTCMP3_Msk (0x1UL << HRTIM_SET2R_MSTCMP3_Pos) /*!< 0x00000400 */
7722 #define HRTIM_SET2R_MSTCMP3 HRTIM_SET2R_MSTCMP3_Msk /*!< Master compare 3 */
7723 #define HRTIM_SET2R_MSTCMP4_Pos (11U)
7724 #define HRTIM_SET2R_MSTCMP4_Msk (0x1UL << HRTIM_SET2R_MSTCMP4_Pos) /*!< 0x00000800 */
7725 #define HRTIM_SET2R_MSTCMP4 HRTIM_SET2R_MSTCMP4_Msk /*!< Master compare 4 */
7726
7727 #define HRTIM_SET2R_TIMEVNT1_Pos (12U)
7728 #define HRTIM_SET2R_TIMEVNT1_Msk (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos) /*!< 0x00001000 */
7729 #define HRTIM_SET2R_TIMEVNT1 HRTIM_SET2R_TIMEVNT1_Msk /*!< Timer event 1 */
7730 #define HRTIM_SET2R_TIMEVNT2_Pos (13U)
7731 #define HRTIM_SET2R_TIMEVNT2_Msk (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos) /*!< 0x00002000 */
7732 #define HRTIM_SET2R_TIMEVNT2 HRTIM_SET2R_TIMEVNT2_Msk /*!< Timer event 2 */
7733 #define HRTIM_SET2R_TIMEVNT3_Pos (14U)
7734 #define HRTIM_SET2R_TIMEVNT3_Msk (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos) /*!< 0x00004000 */
7735 #define HRTIM_SET2R_TIMEVNT3 HRTIM_SET2R_TIMEVNT3_Msk /*!< Timer event 3 */
7736 #define HRTIM_SET2R_TIMEVNT4_Pos (15U)
7737 #define HRTIM_SET2R_TIMEVNT4_Msk (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos) /*!< 0x00008000 */
7738 #define HRTIM_SET2R_TIMEVNT4 HRTIM_SET2R_TIMEVNT4_Msk /*!< Timer event 4 */
7739 #define HRTIM_SET2R_TIMEVNT5_Pos (16U)
7740 #define HRTIM_SET2R_TIMEVNT5_Msk (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos) /*!< 0x00010000 */
7741 #define HRTIM_SET2R_TIMEVNT5 HRTIM_SET2R_TIMEVNT5_Msk /*!< Timer event 5 */
7742 #define HRTIM_SET2R_TIMEVNT6_Pos (17U)
7743 #define HRTIM_SET2R_TIMEVNT6_Msk (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos) /*!< 0x00020000 */
7744 #define HRTIM_SET2R_TIMEVNT6 HRTIM_SET2R_TIMEVNT6_Msk /*!< Timer event 6 */
7745 #define HRTIM_SET2R_TIMEVNT7_Pos (18U)
7746 #define HRTIM_SET2R_TIMEVNT7_Msk (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos) /*!< 0x00040000 */
7747 #define HRTIM_SET2R_TIMEVNT7 HRTIM_SET2R_TIMEVNT7_Msk /*!< Timer event 7 */
7748 #define HRTIM_SET2R_TIMEVNT8_Pos (19U)
7749 #define HRTIM_SET2R_TIMEVNT8_Msk (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos) /*!< 0x00080000 */
7750 #define HRTIM_SET2R_TIMEVNT8 HRTIM_SET2R_TIMEVNT8_Msk /*!< Timer event 8 */
7751 #define HRTIM_SET2R_TIMEVNT9_Pos (20U)
7752 #define HRTIM_SET2R_TIMEVNT9_Msk (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos) /*!< 0x00100000 */
7753 #define HRTIM_SET2R_TIMEVNT9 HRTIM_SET2R_TIMEVNT9_Msk /*!< Timer event 9 */
7754
7755 #define HRTIM_SET2R_EXTVNT1_Pos (21U)
7756 #define HRTIM_SET2R_EXTVNT1_Msk (0x1UL << HRTIM_SET2R_EXTVNT1_Pos) /*!< 0x00200000 */
7757 #define HRTIM_SET2R_EXTVNT1 HRTIM_SET2R_EXTVNT1_Msk /*!< External event 1 */
7758 #define HRTIM_SET2R_EXTVNT2_Pos (22U)
7759 #define HRTIM_SET2R_EXTVNT2_Msk (0x1UL << HRTIM_SET2R_EXTVNT2_Pos) /*!< 0x00400000 */
7760 #define HRTIM_SET2R_EXTVNT2 HRTIM_SET2R_EXTVNT2_Msk /*!< External event 2 */
7761 #define HRTIM_SET2R_EXTVNT3_Pos (23U)
7762 #define HRTIM_SET2R_EXTVNT3_Msk (0x1UL << HRTIM_SET2R_EXTVNT3_Pos) /*!< 0x00800000 */
7763 #define HRTIM_SET2R_EXTVNT3 HRTIM_SET2R_EXTVNT3_Msk /*!< External event 3 */
7764 #define HRTIM_SET2R_EXTVNT4_Pos (24U)
7765 #define HRTIM_SET2R_EXTVNT4_Msk (0x1UL << HRTIM_SET2R_EXTVNT4_Pos) /*!< 0x01000000 */
7766 #define HRTIM_SET2R_EXTVNT4 HRTIM_SET2R_EXTVNT4_Msk /*!< External event 4 */
7767 #define HRTIM_SET2R_EXTVNT5_Pos (25U)
7768 #define HRTIM_SET2R_EXTVNT5_Msk (0x1UL << HRTIM_SET2R_EXTVNT5_Pos) /*!< 0x02000000 */
7769 #define HRTIM_SET2R_EXTVNT5 HRTIM_SET2R_EXTVNT5_Msk /*!< External event 5 */
7770 #define HRTIM_SET2R_EXTVNT6_Pos (26U)
7771 #define HRTIM_SET2R_EXTVNT6_Msk (0x1UL << HRTIM_SET2R_EXTVNT6_Pos) /*!< 0x04000000 */
7772 #define HRTIM_SET2R_EXTVNT6 HRTIM_SET2R_EXTVNT6_Msk /*!< External event 6 */
7773 #define HRTIM_SET2R_EXTVNT7_Pos (27U)
7774 #define HRTIM_SET2R_EXTVNT7_Msk (0x1UL << HRTIM_SET2R_EXTVNT7_Pos) /*!< 0x08000000 */
7775 #define HRTIM_SET2R_EXTVNT7 HRTIM_SET2R_EXTVNT7_Msk /*!< External event 7 */
7776 #define HRTIM_SET2R_EXTVNT8_Pos (28U)
7777 #define HRTIM_SET2R_EXTVNT8_Msk (0x1UL << HRTIM_SET2R_EXTVNT8_Pos) /*!< 0x10000000 */
7778 #define HRTIM_SET2R_EXTVNT8 HRTIM_SET2R_EXTVNT8_Msk /*!< External event 8 */
7779 #define HRTIM_SET2R_EXTVNT9_Pos (29U)
7780 #define HRTIM_SET2R_EXTVNT9_Msk (0x1UL << HRTIM_SET2R_EXTVNT9_Pos) /*!< 0x20000000 */
7781 #define HRTIM_SET2R_EXTVNT9 HRTIM_SET2R_EXTVNT9_Msk /*!< External event 9 */
7782 #define HRTIM_SET2R_EXTVNT10_Pos (30U)
7783 #define HRTIM_SET2R_EXTVNT10_Msk (0x1UL << HRTIM_SET2R_EXTVNT10_Pos) /*!< 0x40000000 */
7784 #define HRTIM_SET2R_EXTVNT10 HRTIM_SET2R_EXTVNT10_Msk /*!< External event 10 */
7785
7786 #define HRTIM_SET2R_UPDATE_Pos (31U)
7787 #define HRTIM_SET2R_UPDATE_Msk (0x1UL << HRTIM_SET2R_UPDATE_Pos) /*!< 0x80000000 */
7788 #define HRTIM_SET2R_UPDATE HRTIM_SET2R_UPDATE_Msk /*!< Register update (transfer preload to active) */
7789
7790 /**** Bit definition for Slave Output 2 reset register ************************/
7791 #define HRTIM_RST2R_SRT_Pos (0U)
7792 #define HRTIM_RST2R_SRT_Msk (0x1UL << HRTIM_RST2R_SRT_Pos) /*!< 0x00000001 */
7793 #define HRTIM_RST2R_SRT HRTIM_RST2R_SRT_Msk /*!< software reset trigger */
7794 #define HRTIM_RST2R_RESYNC_Pos (1U)
7795 #define HRTIM_RST2R_RESYNC_Msk (0x1UL << HRTIM_RST2R_RESYNC_Pos) /*!< 0x00000002 */
7796 #define HRTIM_RST2R_RESYNC HRTIM_RST2R_RESYNC_Msk /*!< Timer A resynchronization */
7797 #define HRTIM_RST2R_PER_Pos (2U)
7798 #define HRTIM_RST2R_PER_Msk (0x1UL << HRTIM_RST2R_PER_Pos) /*!< 0x00000004 */
7799 #define HRTIM_RST2R_PER HRTIM_RST2R_PER_Msk /*!< Timer A period */
7800 #define HRTIM_RST2R_CMP1_Pos (3U)
7801 #define HRTIM_RST2R_CMP1_Msk (0x1UL << HRTIM_RST2R_CMP1_Pos) /*!< 0x00000008 */
7802 #define HRTIM_RST2R_CMP1 HRTIM_RST2R_CMP1_Msk /*!< Timer A compare 1 */
7803 #define HRTIM_RST2R_CMP2_Pos (4U)
7804 #define HRTIM_RST2R_CMP2_Msk (0x1UL << HRTIM_RST2R_CMP2_Pos) /*!< 0x00000010 */
7805 #define HRTIM_RST2R_CMP2 HRTIM_RST2R_CMP2_Msk /*!< Timer A compare 2 */
7806 #define HRTIM_RST2R_CMP3_Pos (5U)
7807 #define HRTIM_RST2R_CMP3_Msk (0x1UL << HRTIM_RST2R_CMP3_Pos) /*!< 0x00000020 */
7808 #define HRTIM_RST2R_CMP3 HRTIM_RST2R_CMP3_Msk /*!< Timer A compare 3 */
7809 #define HRTIM_RST2R_CMP4_Pos (6U)
7810 #define HRTIM_RST2R_CMP4_Msk (0x1UL << HRTIM_RST2R_CMP4_Pos) /*!< 0x00000040 */
7811 #define HRTIM_RST2R_CMP4 HRTIM_RST2R_CMP4_Msk /*!< Timer A compare 4 */
7812 #define HRTIM_RST2R_MSTPER_Pos (7U)
7813 #define HRTIM_RST2R_MSTPER_Msk (0x1UL << HRTIM_RST2R_MSTPER_Pos) /*!< 0x00000080 */
7814 #define HRTIM_RST2R_MSTPER HRTIM_RST2R_MSTPER_Msk /*!< Master period */
7815 #define HRTIM_RST2R_MSTCMP1_Pos (8U)
7816 #define HRTIM_RST2R_MSTCMP1_Msk (0x1UL << HRTIM_RST2R_MSTCMP1_Pos) /*!< 0x00000100 */
7817 #define HRTIM_RST2R_MSTCMP1 HRTIM_RST2R_MSTCMP1_Msk /*!< Master compare 1 */
7818 #define HRTIM_RST2R_MSTCMP2_Pos (9U)
7819 #define HRTIM_RST2R_MSTCMP2_Msk (0x1UL << HRTIM_RST2R_MSTCMP2_Pos) /*!< 0x00000200 */
7820 #define HRTIM_RST2R_MSTCMP2 HRTIM_RST2R_MSTCMP2_Msk /*!< Master compare 2 */
7821 #define HRTIM_RST2R_MSTCMP3_Pos (10U)
7822 #define HRTIM_RST2R_MSTCMP3_Msk (0x1UL << HRTIM_RST2R_MSTCMP3_Pos) /*!< 0x00000400 */
7823 #define HRTIM_RST2R_MSTCMP3 HRTIM_RST2R_MSTCMP3_Msk /*!< Master compare 3 */
7824 #define HRTIM_RST2R_MSTCMP4_Pos (11U)
7825 #define HRTIM_RST2R_MSTCMP4_Msk (0x1UL << HRTIM_RST2R_MSTCMP4_Pos) /*!< 0x00000800 */
7826 #define HRTIM_RST2R_MSTCMP4 HRTIM_RST2R_MSTCMP4_Msk /*!< Master compare 4 */
7827
7828 #define HRTIM_RST2R_TIMEVNT1_Pos (12U)
7829 #define HRTIM_RST2R_TIMEVNT1_Msk (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos) /*!< 0x00001000 */
7830 #define HRTIM_RST2R_TIMEVNT1 HRTIM_RST2R_TIMEVNT1_Msk /*!< Timer event 1 */
7831 #define HRTIM_RST2R_TIMEVNT2_Pos (13U)
7832 #define HRTIM_RST2R_TIMEVNT2_Msk (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos) /*!< 0x00002000 */
7833 #define HRTIM_RST2R_TIMEVNT2 HRTIM_RST2R_TIMEVNT2_Msk /*!< Timer event 2 */
7834 #define HRTIM_RST2R_TIMEVNT3_Pos (14U)
7835 #define HRTIM_RST2R_TIMEVNT3_Msk (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos) /*!< 0x00004000 */
7836 #define HRTIM_RST2R_TIMEVNT3 HRTIM_RST2R_TIMEVNT3_Msk /*!< Timer event 3 */
7837 #define HRTIM_RST2R_TIMEVNT4_Pos (15U)
7838 #define HRTIM_RST2R_TIMEVNT4_Msk (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos) /*!< 0x00008000 */
7839 #define HRTIM_RST2R_TIMEVNT4 HRTIM_RST2R_TIMEVNT4_Msk /*!< Timer event 4 */
7840 #define HRTIM_RST2R_TIMEVNT5_Pos (16U)
7841 #define HRTIM_RST2R_TIMEVNT5_Msk (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos) /*!< 0x00010000 */
7842 #define HRTIM_RST2R_TIMEVNT5 HRTIM_RST2R_TIMEVNT5_Msk /*!< Timer event 5 */
7843 #define HRTIM_RST2R_TIMEVNT6_Pos (17U)
7844 #define HRTIM_RST2R_TIMEVNT6_Msk (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos) /*!< 0x00020000 */
7845 #define HRTIM_RST2R_TIMEVNT6 HRTIM_RST2R_TIMEVNT6_Msk /*!< Timer event 6 */
7846 #define HRTIM_RST2R_TIMEVNT7_Pos (18U)
7847 #define HRTIM_RST2R_TIMEVNT7_Msk (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos) /*!< 0x00040000 */
7848 #define HRTIM_RST2R_TIMEVNT7 HRTIM_RST2R_TIMEVNT7_Msk /*!< Timer event 7 */
7849 #define HRTIM_RST2R_TIMEVNT8_Pos (19U)
7850 #define HRTIM_RST2R_TIMEVNT8_Msk (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos) /*!< 0x00080000 */
7851 #define HRTIM_RST2R_TIMEVNT8 HRTIM_RST2R_TIMEVNT8_Msk /*!< Timer event 8 */
7852 #define HRTIM_RST2R_TIMEVNT9_Pos (20U)
7853 #define HRTIM_RST2R_TIMEVNT9_Msk (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos) /*!< 0x00100000 */
7854 #define HRTIM_RST2R_TIMEVNT9 HRTIM_RST2R_TIMEVNT9_Msk /*!< Timer event 9 */
7855
7856 #define HRTIM_RST2R_EXTVNT1_Pos (21U)
7857 #define HRTIM_RST2R_EXTVNT1_Msk (0x1UL << HRTIM_RST2R_EXTVNT1_Pos) /*!< 0x00200000 */
7858 #define HRTIM_RST2R_EXTVNT1 HRTIM_RST2R_EXTVNT1_Msk /*!< External event 1 */
7859 #define HRTIM_RST2R_EXTVNT2_Pos (22U)
7860 #define HRTIM_RST2R_EXTVNT2_Msk (0x1UL << HRTIM_RST2R_EXTVNT2_Pos) /*!< 0x00400000 */
7861 #define HRTIM_RST2R_EXTVNT2 HRTIM_RST2R_EXTVNT2_Msk /*!< External event 2 */
7862 #define HRTIM_RST2R_EXTVNT3_Pos (23U)
7863 #define HRTIM_RST2R_EXTVNT3_Msk (0x1UL << HRTIM_RST2R_EXTVNT3_Pos) /*!< 0x00800000 */
7864 #define HRTIM_RST2R_EXTVNT3 HRTIM_RST2R_EXTVNT3_Msk /*!< External event 3 */
7865 #define HRTIM_RST2R_EXTVNT4_Pos (24U)
7866 #define HRTIM_RST2R_EXTVNT4_Msk (0x1UL << HRTIM_RST2R_EXTVNT4_Pos) /*!< 0x01000000 */
7867 #define HRTIM_RST2R_EXTVNT4 HRTIM_RST2R_EXTVNT4_Msk /*!< External event 4 */
7868 #define HRTIM_RST2R_EXTVNT5_Pos (25U)
7869 #define HRTIM_RST2R_EXTVNT5_Msk (0x1UL << HRTIM_RST2R_EXTVNT5_Pos) /*!< 0x02000000 */
7870 #define HRTIM_RST2R_EXTVNT5 HRTIM_RST2R_EXTVNT5_Msk /*!< External event 5 */
7871 #define HRTIM_RST2R_EXTVNT6_Pos (26U)
7872 #define HRTIM_RST2R_EXTVNT6_Msk (0x1UL << HRTIM_RST2R_EXTVNT6_Pos) /*!< 0x04000000 */
7873 #define HRTIM_RST2R_EXTVNT6 HRTIM_RST2R_EXTVNT6_Msk /*!< External event 6 */
7874 #define HRTIM_RST2R_EXTVNT7_Pos (27U)
7875 #define HRTIM_RST2R_EXTVNT7_Msk (0x1UL << HRTIM_RST2R_EXTVNT7_Pos) /*!< 0x08000000 */
7876 #define HRTIM_RST2R_EXTVNT7 HRTIM_RST2R_EXTVNT7_Msk /*!< External event 7 */
7877 #define HRTIM_RST2R_EXTVNT8_Pos (28U)
7878 #define HRTIM_RST2R_EXTVNT8_Msk (0x1UL << HRTIM_RST2R_EXTVNT8_Pos) /*!< 0x10000000 */
7879 #define HRTIM_RST2R_EXTVNT8 HRTIM_RST2R_EXTVNT8_Msk /*!< External event 8 */
7880 #define HRTIM_RST2R_EXTVNT9_Pos (29U)
7881 #define HRTIM_RST2R_EXTVNT9_Msk (0x1UL << HRTIM_RST2R_EXTVNT9_Pos) /*!< 0x20000000 */
7882 #define HRTIM_RST2R_EXTVNT9 HRTIM_RST2R_EXTVNT9_Msk /*!< External event 9 */
7883 #define HRTIM_RST2R_EXTVNT10_Pos (30U)
7884 #define HRTIM_RST2R_EXTVNT10_Msk (0x1UL << HRTIM_RST2R_EXTVNT10_Pos) /*!< 0x40000000 */
7885 #define HRTIM_RST2R_EXTVNT10 HRTIM_RST2R_EXTVNT10_Msk /*!< External event 10 */
7886 #define HRTIM_RST2R_UPDATE_Pos (31U)
7887 #define HRTIM_RST2R_UPDATE_Msk (0x1UL << HRTIM_RST2R_UPDATE_Pos) /*!< 0x80000000 */
7888 #define HRTIM_RST2R_UPDATE HRTIM_RST2R_UPDATE_Msk /*!< Register update (transfer preload to active) */
7889
7890 /**** Bit definition for Slave external event filtering register 1 ***********/
7891 #define HRTIM_EEFR1_EE1LTCH_Pos (0U)
7892 #define HRTIM_EEFR1_EE1LTCH_Msk (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos) /*!< 0x00000001 */
7893 #define HRTIM_EEFR1_EE1LTCH HRTIM_EEFR1_EE1LTCH_Msk /*!< External Event 1 latch */
7894 #define HRTIM_EEFR1_EE1FLTR_Pos (1U)
7895 #define HRTIM_EEFR1_EE1FLTR_Msk (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x0000001E */
7896 #define HRTIM_EEFR1_EE1FLTR HRTIM_EEFR1_EE1FLTR_Msk /*!< External Event 1 filter mask */
7897 #define HRTIM_EEFR1_EE1FLTR_0 (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000002 */
7898 #define HRTIM_EEFR1_EE1FLTR_1 (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000004 */
7899 #define HRTIM_EEFR1_EE1FLTR_2 (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000008 */
7900 #define HRTIM_EEFR1_EE1FLTR_3 (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000010 */
7901
7902 #define HRTIM_EEFR1_EE2LTCH_Pos (6U)
7903 #define HRTIM_EEFR1_EE2LTCH_Msk (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos) /*!< 0x00000040 */
7904 #define HRTIM_EEFR1_EE2LTCH HRTIM_EEFR1_EE2LTCH_Msk /*!< External Event 2 latch */
7905 #define HRTIM_EEFR1_EE2FLTR_Pos (7U)
7906 #define HRTIM_EEFR1_EE2FLTR_Msk (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000780 */
7907 #define HRTIM_EEFR1_EE2FLTR HRTIM_EEFR1_EE2FLTR_Msk /*!< External Event 2 filter mask */
7908 #define HRTIM_EEFR1_EE2FLTR_0 (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000080 */
7909 #define HRTIM_EEFR1_EE2FLTR_1 (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000100 */
7910 #define HRTIM_EEFR1_EE2FLTR_2 (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000200 */
7911 #define HRTIM_EEFR1_EE2FLTR_3 (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000400 */
7912
7913 #define HRTIM_EEFR1_EE3LTCH_Pos (12U)
7914 #define HRTIM_EEFR1_EE3LTCH_Msk (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos) /*!< 0x00001000 */
7915 #define HRTIM_EEFR1_EE3LTCH HRTIM_EEFR1_EE3LTCH_Msk /*!< External Event 3 latch */
7916 #define HRTIM_EEFR1_EE3FLTR_Pos (13U)
7917 #define HRTIM_EEFR1_EE3FLTR_Msk (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x0001E000 */
7918 #define HRTIM_EEFR1_EE3FLTR HRTIM_EEFR1_EE3FLTR_Msk /*!< External Event 3 filter mask */
7919 #define HRTIM_EEFR1_EE3FLTR_0 (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00002000 */
7920 #define HRTIM_EEFR1_EE3FLTR_1 (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00004000 */
7921 #define HRTIM_EEFR1_EE3FLTR_2 (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00008000 */
7922 #define HRTIM_EEFR1_EE3FLTR_3 (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00010000 */
7923
7924 #define HRTIM_EEFR1_EE4LTCH_Pos (18U)
7925 #define HRTIM_EEFR1_EE4LTCH_Msk (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos) /*!< 0x00040000 */
7926 #define HRTIM_EEFR1_EE4LTCH HRTIM_EEFR1_EE4LTCH_Msk /*!< External Event 4 latch */
7927 #define HRTIM_EEFR1_EE4FLTR_Pos (19U)
7928 #define HRTIM_EEFR1_EE4FLTR_Msk (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00780000 */
7929 #define HRTIM_EEFR1_EE4FLTR HRTIM_EEFR1_EE4FLTR_Msk /*!< External Event 4 filter mask */
7930 #define HRTIM_EEFR1_EE4FLTR_0 (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00080000 */
7931 #define HRTIM_EEFR1_EE4FLTR_1 (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00100000 */
7932 #define HRTIM_EEFR1_EE4FLTR_2 (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00200000 */
7933 #define HRTIM_EEFR1_EE4FLTR_3 (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00400000 */
7934
7935 #define HRTIM_EEFR1_EE5LTCH_Pos (24U)
7936 #define HRTIM_EEFR1_EE5LTCH_Msk (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos) /*!< 0x01000000 */
7937 #define HRTIM_EEFR1_EE5LTCH HRTIM_EEFR1_EE5LTCH_Msk /*!< External Event 5 latch */
7938 #define HRTIM_EEFR1_EE5FLTR_Pos (25U)
7939 #define HRTIM_EEFR1_EE5FLTR_Msk (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x1E000000 */
7940 #define HRTIM_EEFR1_EE5FLTR HRTIM_EEFR1_EE5FLTR_Msk /*!< External Event 5 filter mask */
7941 #define HRTIM_EEFR1_EE5FLTR_0 (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x02000000 */
7942 #define HRTIM_EEFR1_EE5FLTR_1 (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x04000000 */
7943 #define HRTIM_EEFR1_EE5FLTR_2 (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x08000000 */
7944 #define HRTIM_EEFR1_EE5FLTR_3 (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x10000000 */
7945
7946 /**** Bit definition for Slave external event filtering register 2 ***********/
7947 #define HRTIM_EEFR2_EE6LTCH_Pos (0U)
7948 #define HRTIM_EEFR2_EE6LTCH_Msk (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos) /*!< 0x00000001 */
7949 #define HRTIM_EEFR2_EE6LTCH HRTIM_EEFR2_EE6LTCH_Msk /*!< External Event 6 latch */
7950 #define HRTIM_EEFR2_EE6FLTR_Pos (1U)
7951 #define HRTIM_EEFR2_EE6FLTR_Msk (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x0000001E */
7952 #define HRTIM_EEFR2_EE6FLTR HRTIM_EEFR2_EE6FLTR_Msk /*!< External Event 6 filter mask */
7953 #define HRTIM_EEFR2_EE6FLTR_0 (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000002 */
7954 #define HRTIM_EEFR2_EE6FLTR_1 (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000004 */
7955 #define HRTIM_EEFR2_EE6FLTR_2 (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000008 */
7956 #define HRTIM_EEFR2_EE6FLTR_3 (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000010 */
7957
7958 #define HRTIM_EEFR2_EE7LTCH_Pos (6U)
7959 #define HRTIM_EEFR2_EE7LTCH_Msk (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos) /*!< 0x00000040 */
7960 #define HRTIM_EEFR2_EE7LTCH HRTIM_EEFR2_EE7LTCH_Msk /*!< External Event 7 latch */
7961 #define HRTIM_EEFR2_EE7FLTR_Pos (7U)
7962 #define HRTIM_EEFR2_EE7FLTR_Msk (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000780 */
7963 #define HRTIM_EEFR2_EE7FLTR HRTIM_EEFR2_EE7FLTR_Msk /*!< External Event 7 filter mask */
7964 #define HRTIM_EEFR2_EE7FLTR_0 (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000080 */
7965 #define HRTIM_EEFR2_EE7FLTR_1 (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000100 */
7966 #define HRTIM_EEFR2_EE7FLTR_2 (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000200 */
7967 #define HRTIM_EEFR2_EE7FLTR_3 (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000400 */
7968
7969 #define HRTIM_EEFR2_EE8LTCH_Pos (12U)
7970 #define HRTIM_EEFR2_EE8LTCH_Msk (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos) /*!< 0x00001000 */
7971 #define HRTIM_EEFR2_EE8LTCH HRTIM_EEFR2_EE8LTCH_Msk /*!< External Event 8 latch */
7972 #define HRTIM_EEFR2_EE8FLTR_Pos (13U)
7973 #define HRTIM_EEFR2_EE8FLTR_Msk (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x0001E000 */
7974 #define HRTIM_EEFR2_EE8FLTR HRTIM_EEFR2_EE8FLTR_Msk /*!< External Event 8 filter mask */
7975 #define HRTIM_EEFR2_EE8FLTR_0 (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00002000 */
7976 #define HRTIM_EEFR2_EE8FLTR_1 (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00004000 */
7977 #define HRTIM_EEFR2_EE8FLTR_2 (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00008000 */
7978 #define HRTIM_EEFR2_EE8FLTR_3 (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00010000 */
7979
7980 #define HRTIM_EEFR2_EE9LTCH_Pos (18U)
7981 #define HRTIM_EEFR2_EE9LTCH_Msk (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos) /*!< 0x00040000 */
7982 #define HRTIM_EEFR2_EE9LTCH HRTIM_EEFR2_EE9LTCH_Msk /*!< External Event 9 latch */
7983 #define HRTIM_EEFR2_EE9FLTR_Pos (19U)
7984 #define HRTIM_EEFR2_EE9FLTR_Msk (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00780000 */
7985 #define HRTIM_EEFR2_EE9FLTR HRTIM_EEFR2_EE9FLTR_Msk /*!< External Event 9 filter mask */
7986 #define HRTIM_EEFR2_EE9FLTR_0 (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00080000 */
7987 #define HRTIM_EEFR2_EE9FLTR_1 (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00100000 */
7988 #define HRTIM_EEFR2_EE9FLTR_2 (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00200000 */
7989 #define HRTIM_EEFR2_EE9FLTR_3 (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00400000 */
7990
7991 #define HRTIM_EEFR2_EE10LTCH_Pos (24U)
7992 #define HRTIM_EEFR2_EE10LTCH_Msk (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos) /*!< 0x01000000 */
7993 #define HRTIM_EEFR2_EE10LTCH HRTIM_EEFR2_EE10LTCH_Msk /*!< External Event 10 latch */
7994 #define HRTIM_EEFR2_EE10FLTR_Pos (25U)
7995 #define HRTIM_EEFR2_EE10FLTR_Msk (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x1E000000 */
7996 #define HRTIM_EEFR2_EE10FLTR HRTIM_EEFR2_EE10FLTR_Msk /*!< External Event 10 filter mask */
7997 #define HRTIM_EEFR2_EE10FLTR_0 (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x02000000 */
7998 #define HRTIM_EEFR2_EE10FLTR_1 (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x04000000 */
7999 #define HRTIM_EEFR2_EE10FLTR_2 (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x08000000 */
8000 #define HRTIM_EEFR2_EE10FLTR_3 (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x10000000 */
8001
8002 /**** Bit definition for Slave Timer reset register ***************************/
8003
8004 #define HRTIM_RSTR_TIMFCMP1_Pos (0U)
8005 #define HRTIM_RSTR_TIMFCMP1_Msk (0x1UL << HRTIM_RSTR_TIMFCMP1_Pos) /*!< 0x00000001 */
8006 #define HRTIM_RSTR_TIMFCMP1 HRTIM_RSTR_TIMFCMP1_Msk /*!< Timer F compare 1 */
8007 #define HRTIM_RSTR_UPDATE_Pos (1U)
8008 #define HRTIM_RSTR_UPDATE_Msk (0x1UL << HRTIM_RSTR_UPDATE_Pos) /*!< 0x00000002 */
8009 #define HRTIM_RSTR_UPDATE HRTIM_RSTR_UPDATE_Msk /*!< Timer update */
8010 #define HRTIM_RSTR_CMP2_Pos (2U)
8011 #define HRTIM_RSTR_CMP2_Msk (0x1UL << HRTIM_RSTR_CMP2_Pos) /*!< 0x00000004 */
8012 #define HRTIM_RSTR_CMP2 HRTIM_RSTR_CMP2_Msk /*!< Timer compare2 */
8013 #define HRTIM_RSTR_CMP4_Pos (3U)
8014 #define HRTIM_RSTR_CMP4_Msk (0x1UL << HRTIM_RSTR_CMP4_Pos) /*!< 0x00000008 */
8015 #define HRTIM_RSTR_CMP4 HRTIM_RSTR_CMP4_Msk /*!< Timer compare4 */
8016 #define HRTIM_RSTR_MSTPER_Pos (4U)
8017 #define HRTIM_RSTR_MSTPER_Msk (0x1UL << HRTIM_RSTR_MSTPER_Pos) /*!< 0x00000010 */
8018 #define HRTIM_RSTR_MSTPER HRTIM_RSTR_MSTPER_Msk /*!< Master period */
8019 #define HRTIM_RSTR_MSTCMP1_Pos (5U)
8020 #define HRTIM_RSTR_MSTCMP1_Msk (0x1UL << HRTIM_RSTR_MSTCMP1_Pos) /*!< 0x00000020 */
8021 #define HRTIM_RSTR_MSTCMP1 HRTIM_RSTR_MSTCMP1_Msk /*!< Master compare1 */
8022 #define HRTIM_RSTR_MSTCMP2_Pos (6U)
8023 #define HRTIM_RSTR_MSTCMP2_Msk (0x1UL << HRTIM_RSTR_MSTCMP2_Pos) /*!< 0x00000040 */
8024 #define HRTIM_RSTR_MSTCMP2 HRTIM_RSTR_MSTCMP2_Msk /*!< Master compare2 */
8025 #define HRTIM_RSTR_MSTCMP3_Pos (7U)
8026 #define HRTIM_RSTR_MSTCMP3_Msk (0x1UL << HRTIM_RSTR_MSTCMP3_Pos) /*!< 0x00000080 */
8027 #define HRTIM_RSTR_MSTCMP3 HRTIM_RSTR_MSTCMP3_Msk /*!< Master compare3 */
8028 #define HRTIM_RSTR_MSTCMP4_Pos (8U)
8029 #define HRTIM_RSTR_MSTCMP4_Msk (0x1UL << HRTIM_RSTR_MSTCMP4_Pos) /*!< 0x00000100 */
8030 #define HRTIM_RSTR_MSTCMP4 HRTIM_RSTR_MSTCMP4_Msk /*!< Master compare4 */
8031 #define HRTIM_RSTR_EXTEVNT1_Pos (9U)
8032 #define HRTIM_RSTR_EXTEVNT1_Msk (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos) /*!< 0x00000200 */
8033 #define HRTIM_RSTR_EXTEVNT1 HRTIM_RSTR_EXTEVNT1_Msk /*!< External event 1 */
8034 #define HRTIM_RSTR_EXTEVNT2_Pos (10U)
8035 #define HRTIM_RSTR_EXTEVNT2_Msk (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos) /*!< 0x00000400 */
8036 #define HRTIM_RSTR_EXTEVNT2 HRTIM_RSTR_EXTEVNT2_Msk /*!< External event 2 */
8037 #define HRTIM_RSTR_EXTEVNT3_Pos (11U)
8038 #define HRTIM_RSTR_EXTEVNT3_Msk (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos) /*!< 0x00000800 */
8039 #define HRTIM_RSTR_EXTEVNT3 HRTIM_RSTR_EXTEVNT3_Msk /*!< External event 3 */
8040 #define HRTIM_RSTR_EXTEVNT4_Pos (12U)
8041 #define HRTIM_RSTR_EXTEVNT4_Msk (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos) /*!< 0x00001000 */
8042 #define HRTIM_RSTR_EXTEVNT4 HRTIM_RSTR_EXTEVNT4_Msk /*!< External event 4 */
8043 #define HRTIM_RSTR_EXTEVNT5_Pos (13U)
8044 #define HRTIM_RSTR_EXTEVNT5_Msk (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos) /*!< 0x00002000 */
8045 #define HRTIM_RSTR_EXTEVNT5 HRTIM_RSTR_EXTEVNT5_Msk /*!< External event 5 */
8046 #define HRTIM_RSTR_EXTEVNT6_Pos (14U)
8047 #define HRTIM_RSTR_EXTEVNT6_Msk (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos) /*!< 0x00004000 */
8048 #define HRTIM_RSTR_EXTEVNT6 HRTIM_RSTR_EXTEVNT6_Msk /*!< External event 6 */
8049 #define HRTIM_RSTR_EXTEVNT7_Pos (15U)
8050 #define HRTIM_RSTR_EXTEVNT7_Msk (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos) /*!< 0x00008000 */
8051 #define HRTIM_RSTR_EXTEVNT7 HRTIM_RSTR_EXTEVNT7_Msk /*!< External event 7 */
8052 #define HRTIM_RSTR_EXTEVNT8_Pos (16U)
8053 #define HRTIM_RSTR_EXTEVNT8_Msk (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos) /*!< 0x00010000 */
8054 #define HRTIM_RSTR_EXTEVNT8 HRTIM_RSTR_EXTEVNT8_Msk /*!< External event 8 */
8055 #define HRTIM_RSTR_EXTEVNT9_Pos (17U)
8056 #define HRTIM_RSTR_EXTEVNT9_Msk (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos) /*!< 0x00020000 */
8057 #define HRTIM_RSTR_EXTEVNT9 HRTIM_RSTR_EXTEVNT9_Msk /*!< External event 9 */
8058 #define HRTIM_RSTR_EXTEVNT10_Pos (18U)
8059 #define HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos) /*!< 0x00040000 */
8060 #define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk /*!< External event 10 */
8061 #define HRTIM_RSTR_TIMBCMP1_Pos (19U)
8062 #define HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos) /*!< 0x00080000 */
8063 #define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk /*!< Timer B compare 1 */
8064 #define HRTIM_RSTR_TIMBCMP2_Pos (20U)
8065 #define HRTIM_RSTR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos) /*!< 0x00100000 */
8066 #define HRTIM_RSTR_TIMBCMP2 HRTIM_RSTR_TIMBCMP2_Msk /*!< Timer B compare 2 */
8067 #define HRTIM_RSTR_TIMBCMP4_Pos (21U)
8068 #define HRTIM_RSTR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos) /*!< 0x00200000 */
8069 #define HRTIM_RSTR_TIMBCMP4 HRTIM_RSTR_TIMBCMP4_Msk /*!< Timer B compare 4 */
8070 #define HRTIM_RSTR_TIMCCMP1_Pos (22U)
8071 #define HRTIM_RSTR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos) /*!< 0x00400000 */
8072 #define HRTIM_RSTR_TIMCCMP1 HRTIM_RSTR_TIMCCMP1_Msk /*!< Timer C compare 1 */
8073 #define HRTIM_RSTR_TIMCCMP2_Pos (23U)
8074 #define HRTIM_RSTR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos) /*!< 0x00800000 */
8075 #define HRTIM_RSTR_TIMCCMP2 HRTIM_RSTR_TIMCCMP2_Msk /*!< Timer C compare 2 */
8076 #define HRTIM_RSTR_TIMCCMP4_Pos (24U)
8077 #define HRTIM_RSTR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos) /*!< 0x01000000 */
8078 #define HRTIM_RSTR_TIMCCMP4 HRTIM_RSTR_TIMCCMP4_Msk /*!< Timer C compare 4 */
8079 #define HRTIM_RSTR_TIMDCMP1_Pos (25U)
8080 #define HRTIM_RSTR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos) /*!< 0x02000000 */
8081 #define HRTIM_RSTR_TIMDCMP1 HRTIM_RSTR_TIMDCMP1_Msk /*!< Timer D compare 1 */
8082 #define HRTIM_RSTR_TIMDCMP2_Pos (26U)
8083 #define HRTIM_RSTR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos) /*!< 0x04000000 */
8084 #define HRTIM_RSTR_TIMDCMP2 HRTIM_RSTR_TIMDCMP2_Msk /*!< Timer D compare 2 */
8085 #define HRTIM_RSTR_TIMDCMP4_Pos (27U)
8086 #define HRTIM_RSTR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos) /*!< 0x08000000 */
8087 #define HRTIM_RSTR_TIMDCMP4 HRTIM_RSTR_TIMDCMP4_Msk /*!< Timer D compare 4 */
8088 #define HRTIM_RSTR_TIMECMP1_Pos (28U)
8089 #define HRTIM_RSTR_TIMECMP1_Msk (0x1UL << HRTIM_RSTR_TIMECMP1_Pos) /*!< 0x10000000 */
8090 #define HRTIM_RSTR_TIMECMP1 HRTIM_RSTR_TIMECMP1_Msk /*!< Timer E compare 1 */
8091 #define HRTIM_RSTR_TIMECMP2_Pos (29U)
8092 #define HRTIM_RSTR_TIMECMP2_Msk (0x1UL << HRTIM_RSTR_TIMECMP2_Pos) /*!< 0x20000000 */
8093 #define HRTIM_RSTR_TIMECMP2 HRTIM_RSTR_TIMECMP2_Msk /*!< Timer E compare 2 */
8094 #define HRTIM_RSTR_TIMECMP4_Pos (30U)
8095 #define HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos) /*!< 0x40000000 */
8096 #define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk /*!< Timer E compare 4 */
8097 #define HRTIM_RSTR_TIMFCMP2_Pos (31U)
8098 #define HRTIM_RSTR_TIMFCMP2_Msk (0x1UL << HRTIM_RSTR_TIMFCMP2_Pos) /*!< 0x80000000 */
8099 #define HRTIM_RSTR_TIMFCMP2 HRTIM_RSTR_TIMFCMP2_Msk /*!< Timer F compare 2 */
8100
8101 /**** Bit definition for Slave Timer Chopper register *************************/
8102 #define HRTIM_CHPR_CARFRQ_Pos (0U)
8103 #define HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x0000000F */
8104 #define HRTIM_CHPR_CARFRQ HRTIM_CHPR_CARFRQ_Msk /*!< Timer carrier frequency value */
8105 #define HRTIM_CHPR_CARFRQ_0 (0x1UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000001 */
8106 #define HRTIM_CHPR_CARFRQ_1 (0x2UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000002 */
8107 #define HRTIM_CHPR_CARFRQ_2 (0x4UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000004 */
8108 #define HRTIM_CHPR_CARFRQ_3 (0x8UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000008 */
8109
8110 #define HRTIM_CHPR_CARDTY_Pos (4U)
8111 #define HRTIM_CHPR_CARDTY_Msk (0x7UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000070 */
8112 #define HRTIM_CHPR_CARDTY HRTIM_CHPR_CARDTY_Msk /*!< Timer chopper duty cycle value */
8113 #define HRTIM_CHPR_CARDTY_0 (0x1UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000010 */
8114 #define HRTIM_CHPR_CARDTY_1 (0x2UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000020 */
8115 #define HRTIM_CHPR_CARDTY_2 (0x4UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000040 */
8116
8117 #define HRTIM_CHPR_STRPW_Pos (7U)
8118 #define HRTIM_CHPR_STRPW_Msk (0xFUL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000780 */
8119 #define HRTIM_CHPR_STRPW HRTIM_CHPR_STRPW_Msk /*!< Timer start pulse width value */
8120 #define HRTIM_CHPR_STRPW_0 (0x1UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000080 */
8121 #define HRTIM_CHPR_STRPW_1 (0x2UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000100 */
8122 #define HRTIM_CHPR_STRPW_2 (0x4UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000200 */
8123 #define HRTIM_CHPR_STRPW_3 (0x8UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000400 */
8124
8125 /**** Bit definition for Slave Timer Capture 1 control register ***************/
8126 #define HRTIM_CPT1CR_SWCPT_Pos (0U)
8127 #define HRTIM_CPT1CR_SWCPT_Msk (0x1UL << HRTIM_CPT1CR_SWCPT_Pos) /*!< 0x00000001 */
8128 #define HRTIM_CPT1CR_SWCPT HRTIM_CPT1CR_SWCPT_Msk /*!< Software capture */
8129 #define HRTIM_CPT1CR_UPDCPT_Pos (1U)
8130 #define HRTIM_CPT1CR_UPDCPT_Msk (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos) /*!< 0x00000002 */
8131 #define HRTIM_CPT1CR_UPDCPT HRTIM_CPT1CR_UPDCPT_Msk /*!< Update capture */
8132 #define HRTIM_CPT1CR_EXEV1CPT_Pos (2U)
8133 #define HRTIM_CPT1CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos) /*!< 0x00000004 */
8134 #define HRTIM_CPT1CR_EXEV1CPT HRTIM_CPT1CR_EXEV1CPT_Msk /*!< External event 1 capture */
8135 #define HRTIM_CPT1CR_EXEV2CPT_Pos (3U)
8136 #define HRTIM_CPT1CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos) /*!< 0x00000008 */
8137 #define HRTIM_CPT1CR_EXEV2CPT HRTIM_CPT1CR_EXEV2CPT_Msk /*!< External event 2 capture */
8138 #define HRTIM_CPT1CR_EXEV3CPT_Pos (4U)
8139 #define HRTIM_CPT1CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos) /*!< 0x00000010 */
8140 #define HRTIM_CPT1CR_EXEV3CPT HRTIM_CPT1CR_EXEV3CPT_Msk /*!< External event 3 capture */
8141 #define HRTIM_CPT1CR_EXEV4CPT_Pos (5U)
8142 #define HRTIM_CPT1CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos) /*!< 0x00000020 */
8143 #define HRTIM_CPT1CR_EXEV4CPT HRTIM_CPT1CR_EXEV4CPT_Msk /*!< External event 4 capture */
8144 #define HRTIM_CPT1CR_EXEV5CPT_Pos (6U)
8145 #define HRTIM_CPT1CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos) /*!< 0x00000040 */
8146 #define HRTIM_CPT1CR_EXEV5CPT HRTIM_CPT1CR_EXEV5CPT_Msk /*!< External event 5 capture */
8147 #define HRTIM_CPT1CR_EXEV6CPT_Pos (7U)
8148 #define HRTIM_CPT1CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos) /*!< 0x00000080 */
8149 #define HRTIM_CPT1CR_EXEV6CPT HRTIM_CPT1CR_EXEV6CPT_Msk /*!< External event 6 capture */
8150 #define HRTIM_CPT1CR_EXEV7CPT_Pos (8U)
8151 #define HRTIM_CPT1CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos) /*!< 0x00000100 */
8152 #define HRTIM_CPT1CR_EXEV7CPT HRTIM_CPT1CR_EXEV7CPT_Msk /*!< External event 7 capture */
8153 #define HRTIM_CPT1CR_EXEV8CPT_Pos (9U)
8154 #define HRTIM_CPT1CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos) /*!< 0x00000200 */
8155 #define HRTIM_CPT1CR_EXEV8CPT HRTIM_CPT1CR_EXEV8CPT_Msk /*!< External event 8 capture */
8156 #define HRTIM_CPT1CR_EXEV9CPT_Pos (10U)
8157 #define HRTIM_CPT1CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos) /*!< 0x00000400 */
8158 #define HRTIM_CPT1CR_EXEV9CPT HRTIM_CPT1CR_EXEV9CPT_Msk /*!< External event 9 capture */
8159 #define HRTIM_CPT1CR_EXEV10CPT_Pos (11U)
8160 #define HRTIM_CPT1CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos) /*!< 0x00000800 */
8161 #define HRTIM_CPT1CR_EXEV10CPT HRTIM_CPT1CR_EXEV10CPT_Msk /*!< External event 10 capture */
8162
8163 #define HRTIM_CPT1CR_TF1SET_Pos (0U)
8164 #define HRTIM_CPT1CR_TF1SET_Msk (0x1UL << HRTIM_CPT1CR_TF1SET_Pos) /*!< 0x00000001 */
8165 #define HRTIM_CPT1CR_TF1SET HRTIM_CPT1CR_TF1SET_Msk /*!< Timer F output 1 set */
8166 #define HRTIM_CPT1CR_TF1RST_Pos (1U)
8167 #define HRTIM_CPT1CR_TF1RST_Msk (0x1UL << HRTIM_CPT1CR_TF1RST_Pos) /*!< 0x00000002 */
8168 #define HRTIM_CPT1CR_TF1RST HRTIM_CPT1CR_TF1RST_Msk /*!< Timer F output 1 reset */
8169 #define HRTIM_CPT1CR_TIMFCMP1_Pos (2U)
8170 #define HRTIM_CPT1CR_TIMFCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMFCMP1_Pos) /*!< 0x00000004 */
8171 #define HRTIM_CPT1CR_TIMFCMP1 HRTIM_CPT1CR_TIMFCMP1_Msk /*!< Timer F compare 1 */
8172 #define HRTIM_CPT1CR_TIMFCMP2_Pos (3U)
8173 #define HRTIM_CPT1CR_TIMFCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMFCMP2_Pos) /*!< 0x00000008 */
8174 #define HRTIM_CPT1CR_TIMFCMP2 HRTIM_CPT1CR_TIMFCMP2_Msk /*!< Timer F compare 2 */
8175
8176 #define HRTIM_CPT1CR_TA1SET_Pos (12U)
8177 #define HRTIM_CPT1CR_TA1SET_Msk (0x1UL << HRTIM_CPT1CR_TA1SET_Pos) /*!< 0x00001000 */
8178 #define HRTIM_CPT1CR_TA1SET HRTIM_CPT1CR_TA1SET_Msk /*!< Timer A output 1 set */
8179 #define HRTIM_CPT1CR_TA1RST_Pos (13U)
8180 #define HRTIM_CPT1CR_TA1RST_Msk (0x1UL << HRTIM_CPT1CR_TA1RST_Pos) /*!< 0x00002000 */
8181 #define HRTIM_CPT1CR_TA1RST HRTIM_CPT1CR_TA1RST_Msk /*!< Timer A output 1 reset */
8182 #define HRTIM_CPT1CR_TIMACMP1_Pos (14U)
8183 #define HRTIM_CPT1CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos) /*!< 0x00004000 */
8184 #define HRTIM_CPT1CR_TIMACMP1 HRTIM_CPT1CR_TIMACMP1_Msk /*!< Timer A compare 1 */
8185 #define HRTIM_CPT1CR_TIMACMP2_Pos (15U)
8186 #define HRTIM_CPT1CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos) /*!< 0x00008000 */
8187 #define HRTIM_CPT1CR_TIMACMP2 HRTIM_CPT1CR_TIMACMP2_Msk /*!< Timer A compare 2 */
8188
8189 #define HRTIM_CPT1CR_TB1SET_Pos (16U)
8190 #define HRTIM_CPT1CR_TB1SET_Msk (0x1UL << HRTIM_CPT1CR_TB1SET_Pos) /*!< 0x00010000 */
8191 #define HRTIM_CPT1CR_TB1SET HRTIM_CPT1CR_TB1SET_Msk /*!< Timer B output 1 set */
8192 #define HRTIM_CPT1CR_TB1RST_Pos (17U)
8193 #define HRTIM_CPT1CR_TB1RST_Msk (0x1UL << HRTIM_CPT1CR_TB1RST_Pos) /*!< 0x00020000 */
8194 #define HRTIM_CPT1CR_TB1RST HRTIM_CPT1CR_TB1RST_Msk /*!< Timer B output 1 reset */
8195 #define HRTIM_CPT1CR_TIMBCMP1_Pos (18U)
8196 #define HRTIM_CPT1CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos) /*!< 0x00040000 */
8197 #define HRTIM_CPT1CR_TIMBCMP1 HRTIM_CPT1CR_TIMBCMP1_Msk /*!< Timer B compare 1 */
8198 #define HRTIM_CPT1CR_TIMBCMP2_Pos (19U)
8199 #define HRTIM_CPT1CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos) /*!< 0x00080000 */
8200 #define HRTIM_CPT1CR_TIMBCMP2 HRTIM_CPT1CR_TIMBCMP2_Msk /*!< Timer B compare 2 */
8201
8202 #define HRTIM_CPT1CR_TC1SET_Pos (20U)
8203 #define HRTIM_CPT1CR_TC1SET_Msk (0x1UL << HRTIM_CPT1CR_TC1SET_Pos) /*!< 0x00100000 */
8204 #define HRTIM_CPT1CR_TC1SET HRTIM_CPT1CR_TC1SET_Msk /*!< Timer C output 1 set */
8205 #define HRTIM_CPT1CR_TC1RST_Pos (21U)
8206 #define HRTIM_CPT1CR_TC1RST_Msk (0x1UL << HRTIM_CPT1CR_TC1RST_Pos) /*!< 0x00200000 */
8207 #define HRTIM_CPT1CR_TC1RST HRTIM_CPT1CR_TC1RST_Msk /*!< Timer C output 1 reset */
8208 #define HRTIM_CPT1CR_TIMCCMP1_Pos (22U)
8209 #define HRTIM_CPT1CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos) /*!< 0x00400000 */
8210 #define HRTIM_CPT1CR_TIMCCMP1 HRTIM_CPT1CR_TIMCCMP1_Msk /*!< Timer C compare 1 */
8211 #define HRTIM_CPT1CR_TIMCCMP2_Pos (23U)
8212 #define HRTIM_CPT1CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos) /*!< 0x00800000 */
8213 #define HRTIM_CPT1CR_TIMCCMP2 HRTIM_CPT1CR_TIMCCMP2_Msk /*!< Timer C compare 2 */
8214
8215 #define HRTIM_CPT1CR_TD1SET_Pos (24U)
8216 #define HRTIM_CPT1CR_TD1SET_Msk (0x1UL << HRTIM_CPT1CR_TD1SET_Pos) /*!< 0x01000000 */
8217 #define HRTIM_CPT1CR_TD1SET HRTIM_CPT1CR_TD1SET_Msk /*!< Timer D output 1 set */
8218 #define HRTIM_CPT1CR_TD1RST_Pos (25U)
8219 #define HRTIM_CPT1CR_TD1RST_Msk (0x1UL << HRTIM_CPT1CR_TD1RST_Pos) /*!< 0x02000000 */
8220 #define HRTIM_CPT1CR_TD1RST HRTIM_CPT1CR_TD1RST_Msk /*!< Timer D output 1 reset */
8221 #define HRTIM_CPT1CR_TIMDCMP1_Pos (26U)
8222 #define HRTIM_CPT1CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos) /*!< 0x04000000 */
8223 #define HRTIM_CPT1CR_TIMDCMP1 HRTIM_CPT1CR_TIMDCMP1_Msk /*!< Timer D compare 1 */
8224 #define HRTIM_CPT1CR_TIMDCMP2_Pos (27U)
8225 #define HRTIM_CPT1CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos) /*!< 0x08000000 */
8226 #define HRTIM_CPT1CR_TIMDCMP2 HRTIM_CPT1CR_TIMDCMP2_Msk /*!< Timer D compare 2 */
8227
8228 #define HRTIM_CPT1CR_TE1SET_Pos (28U)
8229 #define HRTIM_CPT1CR_TE1SET_Msk (0x1UL << HRTIM_CPT1CR_TE1SET_Pos) /*!< 0x10000000 */
8230 #define HRTIM_CPT1CR_TE1SET HRTIM_CPT1CR_TE1SET_Msk /*!< Timer E output 1 set */
8231 #define HRTIM_CPT1CR_TE1RST_Pos (29U)
8232 #define HRTIM_CPT1CR_TE1RST_Msk (0x1UL << HRTIM_CPT1CR_TE1RST_Pos) /*!< 0x20000000 */
8233 #define HRTIM_CPT1CR_TE1RST HRTIM_CPT1CR_TE1RST_Msk /*!< Timer E output 1 reset */
8234 #define HRTIM_CPT1CR_TIMECMP1_Pos (30U)
8235 #define HRTIM_CPT1CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos) /*!< 0x40000000 */
8236 #define HRTIM_CPT1CR_TIMECMP1 HRTIM_CPT1CR_TIMECMP1_Msk /*!< Timer E compare 1 */
8237 #define HRTIM_CPT1CR_TIMECMP2_Pos (31U)
8238 #define HRTIM_CPT1CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos) /*!< 0x80000000 */
8239 #define HRTIM_CPT1CR_TIMECMP2 HRTIM_CPT1CR_TIMECMP2_Msk /*!< Timer E compare 2 */
8240
8241 /**** Bit definition for Slave Timer Capture 2 control register ***************/
8242 #define HRTIM_CPT2CR_SWCPT_Pos (0U)
8243 #define HRTIM_CPT2CR_SWCPT_Msk (0x1UL << HRTIM_CPT2CR_SWCPT_Pos) /*!< 0x00000001 */
8244 #define HRTIM_CPT2CR_SWCPT HRTIM_CPT2CR_SWCPT_Msk /*!< Software capture */
8245 #define HRTIM_CPT2CR_UPDCPT_Pos (1U)
8246 #define HRTIM_CPT2CR_UPDCPT_Msk (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos) /*!< 0x00000002 */
8247 #define HRTIM_CPT2CR_UPDCPT HRTIM_CPT2CR_UPDCPT_Msk /*!< Update capture */
8248 #define HRTIM_CPT2CR_EXEV1CPT_Pos (2U)
8249 #define HRTIM_CPT2CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos) /*!< 0x00000004 */
8250 #define HRTIM_CPT2CR_EXEV1CPT HRTIM_CPT2CR_EXEV1CPT_Msk /*!< External event 1 capture */
8251 #define HRTIM_CPT2CR_EXEV2CPT_Pos (3U)
8252 #define HRTIM_CPT2CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos) /*!< 0x00000008 */
8253 #define HRTIM_CPT2CR_EXEV2CPT HRTIM_CPT2CR_EXEV2CPT_Msk /*!< External event 2 capture */
8254 #define HRTIM_CPT2CR_EXEV3CPT_Pos (4U)
8255 #define HRTIM_CPT2CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos) /*!< 0x00000010 */
8256 #define HRTIM_CPT2CR_EXEV3CPT HRTIM_CPT2CR_EXEV3CPT_Msk /*!< External event 3 capture */
8257 #define HRTIM_CPT2CR_EXEV4CPT_Pos (5U)
8258 #define HRTIM_CPT2CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos) /*!< 0x00000020 */
8259 #define HRTIM_CPT2CR_EXEV4CPT HRTIM_CPT2CR_EXEV4CPT_Msk /*!< External event 4 capture */
8260 #define HRTIM_CPT2CR_EXEV5CPT_Pos (6U)
8261 #define HRTIM_CPT2CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos) /*!< 0x00000040 */
8262 #define HRTIM_CPT2CR_EXEV5CPT HRTIM_CPT2CR_EXEV5CPT_Msk /*!< External event 5 capture */
8263 #define HRTIM_CPT2CR_EXEV6CPT_Pos (7U)
8264 #define HRTIM_CPT2CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos) /*!< 0x00000080 */
8265 #define HRTIM_CPT2CR_EXEV6CPT HRTIM_CPT2CR_EXEV6CPT_Msk /*!< External event 6 capture */
8266 #define HRTIM_CPT2CR_EXEV7CPT_Pos (8U)
8267 #define HRTIM_CPT2CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos) /*!< 0x00000100 */
8268 #define HRTIM_CPT2CR_EXEV7CPT HRTIM_CPT2CR_EXEV7CPT_Msk /*!< External event 7 capture */
8269 #define HRTIM_CPT2CR_EXEV8CPT_Pos (9U)
8270 #define HRTIM_CPT2CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos) /*!< 0x00000200 */
8271 #define HRTIM_CPT2CR_EXEV8CPT HRTIM_CPT2CR_EXEV8CPT_Msk /*!< External event 8 capture */
8272 #define HRTIM_CPT2CR_EXEV9CPT_Pos (10U)
8273 #define HRTIM_CPT2CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos) /*!< 0x00000400 */
8274 #define HRTIM_CPT2CR_EXEV9CPT HRTIM_CPT2CR_EXEV9CPT_Msk /*!< External event 9 capture */
8275 #define HRTIM_CPT2CR_EXEV10CPT_Pos (11U)
8276 #define HRTIM_CPT2CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos) /*!< 0x00000800 */
8277 #define HRTIM_CPT2CR_EXEV10CPT HRTIM_CPT2CR_EXEV10CPT_Msk /*!< External event 10 capture */
8278
8279 #define HRTIM_CPT2CR_TF1SET_Pos (0U)
8280 #define HRTIM_CPT2CR_TF1SET_Msk (0x1UL << HRTIM_CPT2CR_TF1SET_Pos) /*!< 0x00000001 */
8281 #define HRTIM_CPT2CR_TF1SET HRTIM_CPT2CR_TF1SET_Msk /*!< Timer F output 1 set */
8282 #define HRTIM_CPT2CR_TF1RST_Pos (1U)
8283 #define HRTIM_CPT2CR_TF1RST_Msk (0x1UL << HRTIM_CPT2CR_TF1RST_Pos) /*!< 0x00000002 */
8284 #define HRTIM_CPT2CR_TF1RST HRTIM_CPT2CR_TF1RST_Msk /*!< Timer F output 1 reset */
8285 #define HRTIM_CPT2CR_TIMFCMP1_Pos (2U)
8286 #define HRTIM_CPT2CR_TIMFCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMFCMP1_Pos) /*!< 0x00000004 */
8287 #define HRTIM_CPT2CR_TIMFCMP1 HRTIM_CPT2CR_TIMFCMP1_Msk /*!< Timer F compare 1 */
8288 #define HRTIM_CPT2CR_TIMFCMP2_Pos (3U)
8289 #define HRTIM_CPT2CR_TIMFCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMFCMP2_Pos) /*!< 0x00000008 */
8290 #define HRTIM_CPT2CR_TIMFCMP2 HRTIM_CPT2CR_TIMFCMP2_Msk /*!< Timer F compare 2 */
8291
8292 #define HRTIM_CPT2CR_TA1SET_Pos (12U)
8293 #define HRTIM_CPT2CR_TA1SET_Msk (0x1UL << HRTIM_CPT2CR_TA1SET_Pos) /*!< 0x00001000 */
8294 #define HRTIM_CPT2CR_TA1SET HRTIM_CPT2CR_TA1SET_Msk /*!< Timer A output 1 set */
8295 #define HRTIM_CPT2CR_TA1RST_Pos (13U)
8296 #define HRTIM_CPT2CR_TA1RST_Msk (0x1UL << HRTIM_CPT2CR_TA1RST_Pos) /*!< 0x00002000 */
8297 #define HRTIM_CPT2CR_TA1RST HRTIM_CPT2CR_TA1RST_Msk /*!< Timer A output 1 reset */
8298 #define HRTIM_CPT2CR_TIMACMP1_Pos (14U)
8299 #define HRTIM_CPT2CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos) /*!< 0x00004000 */
8300 #define HRTIM_CPT2CR_TIMACMP1 HRTIM_CPT2CR_TIMACMP1_Msk /*!< Timer A compare 1 */
8301 #define HRTIM_CPT2CR_TIMACMP2_Pos (15U)
8302 #define HRTIM_CPT2CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos) /*!< 0x00008000 */
8303 #define HRTIM_CPT2CR_TIMACMP2 HRTIM_CPT2CR_TIMACMP2_Msk /*!< Timer A compare 2 */
8304
8305 #define HRTIM_CPT2CR_TB1SET_Pos (16U)
8306 #define HRTIM_CPT2CR_TB1SET_Msk (0x1UL << HRTIM_CPT2CR_TB1SET_Pos) /*!< 0x00010000 */
8307 #define HRTIM_CPT2CR_TB1SET HRTIM_CPT2CR_TB1SET_Msk /*!< Timer B output 1 set */
8308 #define HRTIM_CPT2CR_TB1RST_Pos (17U)
8309 #define HRTIM_CPT2CR_TB1RST_Msk (0x1UL << HRTIM_CPT2CR_TB1RST_Pos) /*!< 0x00020000 */
8310 #define HRTIM_CPT2CR_TB1RST HRTIM_CPT2CR_TB1RST_Msk /*!< Timer B output 1 reset */
8311 #define HRTIM_CPT2CR_TIMBCMP1_Pos (18U)
8312 #define HRTIM_CPT2CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos) /*!< 0x00040000 */
8313 #define HRTIM_CPT2CR_TIMBCMP1 HRTIM_CPT2CR_TIMBCMP1_Msk /*!< Timer B compare 1 */
8314 #define HRTIM_CPT2CR_TIMBCMP2_Pos (19U)
8315 #define HRTIM_CPT2CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos) /*!< 0x00080000 */
8316 #define HRTIM_CPT2CR_TIMBCMP2 HRTIM_CPT2CR_TIMBCMP2_Msk /*!< Timer B compare 2 */
8317
8318 #define HRTIM_CPT2CR_TC1SET_Pos (20U)
8319 #define HRTIM_CPT2CR_TC1SET_Msk (0x1UL << HRTIM_CPT2CR_TC1SET_Pos) /*!< 0x00100000 */
8320 #define HRTIM_CPT2CR_TC1SET HRTIM_CPT2CR_TC1SET_Msk /*!< Timer C output 1 set */
8321 #define HRTIM_CPT2CR_TC1RST_Pos (21U)
8322 #define HRTIM_CPT2CR_TC1RST_Msk (0x1UL << HRTIM_CPT2CR_TC1RST_Pos) /*!< 0x00200000 */
8323 #define HRTIM_CPT2CR_TC1RST HRTIM_CPT2CR_TC1RST_Msk /*!< Timer C output 1 reset */
8324 #define HRTIM_CPT2CR_TIMCCMP1_Pos (22U)
8325 #define HRTIM_CPT2CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos) /*!< 0x00400000 */
8326 #define HRTIM_CPT2CR_TIMCCMP1 HRTIM_CPT2CR_TIMCCMP1_Msk /*!< Timer C compare 1 */
8327 #define HRTIM_CPT2CR_TIMCCMP2_Pos (23U)
8328 #define HRTIM_CPT2CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos) /*!< 0x00800000 */
8329 #define HRTIM_CPT2CR_TIMCCMP2 HRTIM_CPT2CR_TIMCCMP2_Msk /*!< Timer C compare 2 */
8330
8331 #define HRTIM_CPT2CR_TD1SET_Pos (24U)
8332 #define HRTIM_CPT2CR_TD1SET_Msk (0x1UL << HRTIM_CPT2CR_TD1SET_Pos) /*!< 0x01000000 */
8333 #define HRTIM_CPT2CR_TD1SET HRTIM_CPT2CR_TD1SET_Msk /*!< Timer D output 1 set */
8334 #define HRTIM_CPT2CR_TD1RST_Pos (25U)
8335 #define HRTIM_CPT2CR_TD1RST_Msk (0x1UL << HRTIM_CPT2CR_TD1RST_Pos) /*!< 0x02000000 */
8336 #define HRTIM_CPT2CR_TD1RST HRTIM_CPT2CR_TD1RST_Msk /*!< Timer D output 1 reset */
8337 #define HRTIM_CPT2CR_TIMDCMP1_Pos (26U)
8338 #define HRTIM_CPT2CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos) /*!< 0x04000000 */
8339 #define HRTIM_CPT2CR_TIMDCMP1 HRTIM_CPT2CR_TIMDCMP1_Msk /*!< Timer D compare 1 */
8340 #define HRTIM_CPT2CR_TIMDCMP2_Pos (27U)
8341 #define HRTIM_CPT2CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos) /*!< 0x08000000 */
8342 #define HRTIM_CPT2CR_TIMDCMP2 HRTIM_CPT2CR_TIMDCMP2_Msk /*!< Timer D compare 2 */
8343
8344 #define HRTIM_CPT2CR_TE1SET_Pos (28U)
8345 #define HRTIM_CPT2CR_TE1SET_Msk (0x1UL << HRTIM_CPT2CR_TE1SET_Pos) /*!< 0x10000000 */
8346 #define HRTIM_CPT2CR_TE1SET HRTIM_CPT2CR_TE1SET_Msk /*!< Timer E output 1 set */
8347 #define HRTIM_CPT2CR_TE1RST_Pos (29U)
8348 #define HRTIM_CPT2CR_TE1RST_Msk (0x1UL << HRTIM_CPT2CR_TE1RST_Pos) /*!< 0x20000000 */
8349 #define HRTIM_CPT2CR_TE1RST HRTIM_CPT2CR_TE1RST_Msk /*!< Timer E output 1 reset */
8350 #define HRTIM_CPT2CR_TIMECMP1_Pos (30U)
8351 #define HRTIM_CPT2CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos) /*!< 0x40000000 */
8352 #define HRTIM_CPT2CR_TIMECMP1 HRTIM_CPT2CR_TIMECMP1_Msk /*!< Timer E compare 1 */
8353 #define HRTIM_CPT2CR_TIMECMP2_Pos (31U)
8354 #define HRTIM_CPT2CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos) /*!< 0x80000000 */
8355 #define HRTIM_CPT2CR_TIMECMP2 HRTIM_CPT2CR_TIMECMP2_Msk /*!< Timer E compare 2 */
8356
8357 /**** Bit definition for Slave Timer Output register **************************/
8358 #define HRTIM_OUTR_POL1_Pos (1U)
8359 #define HRTIM_OUTR_POL1_Msk (0x1UL << HRTIM_OUTR_POL1_Pos) /*!< 0x00000002 */
8360 #define HRTIM_OUTR_POL1 HRTIM_OUTR_POL1_Msk /*!< Slave output 1 polarity */
8361 #define HRTIM_OUTR_IDLM1_Pos (2U)
8362 #define HRTIM_OUTR_IDLM1_Msk (0x1UL << HRTIM_OUTR_IDLM1_Pos) /*!< 0x00000004 */
8363 #define HRTIM_OUTR_IDLM1 HRTIM_OUTR_IDLM1_Msk /*!< Slave output 1 idle mode */
8364 #define HRTIM_OUTR_IDLES1_Pos (3U)
8365 #define HRTIM_OUTR_IDLES1_Msk (0x1UL << HRTIM_OUTR_IDLES1_Pos) /*!< 0x00000008 */
8366 #define HRTIM_OUTR_IDLES1 HRTIM_OUTR_IDLES1_Msk /*!< Slave output 1 idle state */
8367 #define HRTIM_OUTR_FAULT1_Pos (4U)
8368 #define HRTIM_OUTR_FAULT1_Msk (0x3UL << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000030 */
8369 #define HRTIM_OUTR_FAULT1 HRTIM_OUTR_FAULT1_Msk /*!< Slave output 1 fault state */
8370 #define HRTIM_OUTR_FAULT1_0 (0x1UL << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000010 */
8371 #define HRTIM_OUTR_FAULT1_1 (0x2UL << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000020 */
8372 #define HRTIM_OUTR_CHP1_Pos (6U)
8373 #define HRTIM_OUTR_CHP1_Msk (0x1UL << HRTIM_OUTR_CHP1_Pos) /*!< 0x00000040 */
8374 #define HRTIM_OUTR_CHP1 HRTIM_OUTR_CHP1_Msk /*!< Slave output 1 chopper enable */
8375 #define HRTIM_OUTR_DIDL1_Pos (7U)
8376 #define HRTIM_OUTR_DIDL1_Msk (0x1UL << HRTIM_OUTR_DIDL1_Pos) /*!< 0x00000080 */
8377 #define HRTIM_OUTR_DIDL1 HRTIM_OUTR_DIDL1_Msk /*!< Slave output 1 dead time idle */
8378
8379 #define HRTIM_OUTR_DTEN_Pos (8U)
8380 #define HRTIM_OUTR_DTEN_Msk (0x1UL << HRTIM_OUTR_DTEN_Pos) /*!< 0x00000100 */
8381 #define HRTIM_OUTR_DTEN HRTIM_OUTR_DTEN_Msk /*!< Slave output deadtime enable */
8382 #define HRTIM_OUTR_DLYPRTEN_Pos (9U)
8383 #define HRTIM_OUTR_DLYPRTEN_Msk (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos) /*!< 0x00000200 */
8384 #define HRTIM_OUTR_DLYPRTEN HRTIM_OUTR_DLYPRTEN_Msk /*!< Slave output delay protection enable */
8385 #define HRTIM_OUTR_DLYPRT_Pos (10U)
8386 #define HRTIM_OUTR_DLYPRT_Msk (0x7UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00001C00 */
8387 #define HRTIM_OUTR_DLYPRT HRTIM_OUTR_DLYPRT_Msk /*!< Slave output delay protection */
8388 #define HRTIM_OUTR_DLYPRT_0 (0x1UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00000400 */
8389 #define HRTIM_OUTR_DLYPRT_1 (0x2UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00000800 */
8390 #define HRTIM_OUTR_DLYPRT_2 (0x4UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00001000 */
8391 #define HRTIM_OUTR_BIAR_Pos (14U)
8392 #define HRTIM_OUTR_BIAR_Msk (0x1UL << HRTIM_OUTR_BIAR_Pos) /*!< 0x00004000 */
8393 #define HRTIM_OUTR_BIAR HRTIM_OUTR_BIAR_Msk /*!< Slave output Balanced Idle Automatic resume */
8394 #define HRTIM_OUTR_POL2_Pos (17U)
8395 #define HRTIM_OUTR_POL2_Msk (0x1UL << HRTIM_OUTR_POL2_Pos) /*!< 0x00020000 */
8396 #define HRTIM_OUTR_POL2 HRTIM_OUTR_POL2_Msk /*!< Slave output 2 polarity */
8397 #define HRTIM_OUTR_IDLM2_Pos (18U)
8398 #define HRTIM_OUTR_IDLM2_Msk (0x1UL << HRTIM_OUTR_IDLM2_Pos) /*!< 0x00040000 */
8399 #define HRTIM_OUTR_IDLM2 HRTIM_OUTR_IDLM2_Msk /*!< Slave output 2 idle mode */
8400 #define HRTIM_OUTR_IDLES2_Pos (19U)
8401 #define HRTIM_OUTR_IDLES2_Msk (0x1UL << HRTIM_OUTR_IDLES2_Pos) /*!< 0x00080000 */
8402 #define HRTIM_OUTR_IDLES2 HRTIM_OUTR_IDLES2_Msk /*!< Slave output 2 idle state */
8403 #define HRTIM_OUTR_FAULT2_Pos (20U)
8404 #define HRTIM_OUTR_FAULT2_Msk (0x3UL << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00300000 */
8405 #define HRTIM_OUTR_FAULT2 HRTIM_OUTR_FAULT2_Msk /*!< Slave output 2 fault state */
8406 #define HRTIM_OUTR_FAULT2_0 (0x1UL << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00100000 */
8407 #define HRTIM_OUTR_FAULT2_1 (0x2UL << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00200000 */
8408 #define HRTIM_OUTR_CHP2_Pos (22U)
8409 #define HRTIM_OUTR_CHP2_Msk (0x1UL << HRTIM_OUTR_CHP2_Pos) /*!< 0x00400000 */
8410 #define HRTIM_OUTR_CHP2 HRTIM_OUTR_CHP2_Msk /*!< Slave output 2 chopper enable */
8411 #define HRTIM_OUTR_DIDL2_Pos (23U)
8412 #define HRTIM_OUTR_DIDL2_Msk (0x1UL << HRTIM_OUTR_DIDL2_Pos) /*!< 0x00800000 */
8413 #define HRTIM_OUTR_DIDL2 HRTIM_OUTR_DIDL2_Msk /*!< Slave output 2 dead time idle */
8414
8415 /**** Bit definition for Timerx Fault register ***************************/
8416 #define HRTIM_FLTR_FLT1EN_Pos (0U)
8417 #define HRTIM_FLTR_FLT1EN_Msk (0x1UL << HRTIM_FLTR_FLT1EN_Pos) /*!< 0x00000001 */
8418 #define HRTIM_FLTR_FLT1EN HRTIM_FLTR_FLT1EN_Msk /*!< Fault 1 enable */
8419 #define HRTIM_FLTR_FLT2EN_Pos (1U)
8420 #define HRTIM_FLTR_FLT2EN_Msk (0x1UL << HRTIM_FLTR_FLT2EN_Pos) /*!< 0x00000002 */
8421 #define HRTIM_FLTR_FLT2EN HRTIM_FLTR_FLT2EN_Msk /*!< Fault 2 enable */
8422 #define HRTIM_FLTR_FLT3EN_Pos (2U)
8423 #define HRTIM_FLTR_FLT3EN_Msk (0x1UL << HRTIM_FLTR_FLT3EN_Pos) /*!< 0x00000004 */
8424 #define HRTIM_FLTR_FLT3EN HRTIM_FLTR_FLT3EN_Msk /*!< Fault 3 enable */
8425 #define HRTIM_FLTR_FLT4EN_Pos (3U)
8426 #define HRTIM_FLTR_FLT4EN_Msk (0x1UL << HRTIM_FLTR_FLT4EN_Pos) /*!< 0x00000008 */
8427 #define HRTIM_FLTR_FLT4EN HRTIM_FLTR_FLT4EN_Msk /*!< Fault 4 enable */
8428 #define HRTIM_FLTR_FLT5EN_Pos (4U)
8429 #define HRTIM_FLTR_FLT5EN_Msk (0x1UL << HRTIM_FLTR_FLT5EN_Pos) /*!< 0x00000010 */
8430 #define HRTIM_FLTR_FLT5EN HRTIM_FLTR_FLT5EN_Msk /*!< Fault 5 enable */
8431 #define HRTIM_FLTR_FLT6EN_Pos (5U)
8432 #define HRTIM_FLTR_FLT6EN_Msk (0x1UL << HRTIM_FLTR_FLT6EN_Pos) /*!< 0x00000020 */
8433 #define HRTIM_FLTR_FLT6EN HRTIM_FLTR_FLT6EN_Msk /*!< Fault 6 enable */
8434 #define HRTIM_FLTR_FLTLCK_Pos (31U)
8435 #define HRTIM_FLTR_FLTLCK_Msk (0x1UL << HRTIM_FLTR_FLTLCK_Pos) /*!< 0x80000000 */
8436 #define HRTIM_FLTR_FLTLCK HRTIM_FLTR_FLTLCK_Msk /*!< Fault sources lock */
8437
8438 /**** Bit definition for HRTIM Timerx control register 2 ****************/
8439 #define HRTIM_TIMCR2_DCDE_Pos (0U)
8440 #define HRTIM_TIMCR2_DCDE_Msk (0x1UL << HRTIM_TIMCR2_DCDE_Pos) /*!< 0x00000001 */
8441 #define HRTIM_TIMCR2_DCDE HRTIM_TIMCR2_DCDE_Msk /*!< Dual Channel DAC trigger enable */
8442 #define HRTIM_TIMCR2_DCDS_Pos (1U)
8443 #define HRTIM_TIMCR2_DCDS_Msk (0x1UL << HRTIM_TIMCR2_DCDS_Pos) /*!< 0x00000002 */
8444 #define HRTIM_TIMCR2_DCDS HRTIM_TIMCR2_DCDS_Msk /*!< Dual Channel DAC step trigger */
8445 #define HRTIM_TIMCR2_DCDR_Pos (2U)
8446 #define HRTIM_TIMCR2_DCDR_Msk (0x1UL << HRTIM_TIMCR2_DCDR_Pos) /*!< 0x00000004 */
8447 #define HRTIM_TIMCR2_DCDR HRTIM_TIMCR2_DCDR_Msk /*!< Dual Channel DAC reset trigger */
8448 #define HRTIM_TIMCR2_UDM_Pos (4U)
8449 #define HRTIM_TIMCR2_UDM_Msk (0x1UL << HRTIM_TIMCR2_UDM_Pos) /*!< 0x00000010 */
8450 #define HRTIM_TIMCR2_UDM HRTIM_TIMCR2_UDM_Msk /*!< Up-Down Mode*/
8451 #define HRTIM_TIMCR2_ROM_Pos (6U)
8452 #define HRTIM_TIMCR2_ROM_Msk (0x3UL << HRTIM_TIMCR2_ROM_Pos) /*!< 0x000000C0 */
8453 #define HRTIM_TIMCR2_ROM HRTIM_TIMCR2_ROM_Msk /*!< Roll-over Mode */
8454 #define HRTIM_TIMCR2_ROM_0 (0x1UL << HRTIM_TIMCR2_ROM_Pos) /*!< 0x00000040 */
8455 #define HRTIM_TIMCR2_ROM_1 (0x2UL << HRTIM_TIMCR2_ROM_Pos) /*!< 0x00000080 */
8456 #define HRTIM_TIMCR2_OUTROM_Pos (8U)
8457 #define HRTIM_TIMCR2_OUTROM_Msk (0x3UL << HRTIM_TIMCR2_OUTROM_Pos) /*!< 0x00000300 */
8458 #define HRTIM_TIMCR2_OUTROM HRTIM_TIMCR2_OUTROM_Msk /*!< Output Roll-Over Mode */
8459 #define HRTIM_TIMCR2_OUTROM_0 (0x1UL << HRTIM_TIMCR2_OUTROM_Pos) /*!< 0x00000100 */
8460 #define HRTIM_TIMCR2_OUTROM_1 (0x2UL << HRTIM_TIMCR2_OUTROM_Pos) /*!< 0x00000200 */
8461 #define HRTIM_TIMCR2_ADROM_Pos (10U)
8462 #define HRTIM_TIMCR2_ADROM_Msk (0x3UL << HRTIM_TIMCR2_ADROM_Pos) /*!< 0x00000C00 */
8463 #define HRTIM_TIMCR2_ADROM HRTIM_TIMCR2_ADROM_Msk /*!< ADC Roll-Over Mode */
8464 #define HRTIM_TIMCR2_ADROM_0 (0x1UL << HRTIM_TIMCR2_ADROM_Pos) /*!< 0x00000400 */
8465 #define HRTIM_TIMCR2_ADROM_1 (0x2UL << HRTIM_TIMCR2_ADROM_Pos) /*!< 0x00000800 */
8466 #define HRTIM_TIMCR2_BMROM_Pos (12U)
8467 #define HRTIM_TIMCR2_BMROM_Msk (0x3UL << HRTIM_TIMCR2_BMROM_Pos) /*!< 0x00003000 */
8468 #define HRTIM_TIMCR2_BMROM HRTIM_TIMCR2_BMROM_Msk /*!< Burst Mode Rollover Mode */
8469 #define HRTIM_TIMCR2_BMROM_0 (0x1UL << HRTIM_TIMCR2_BMROM_Pos) /*!< 0x00001000 */
8470 #define HRTIM_TIMCR2_BMROM_1 (0x2UL << HRTIM_TIMCR2_BMROM_Pos) /*!< 0x00002000 */
8471 #define HRTIM_TIMCR2_FEROM_Pos (14U)
8472 #define HRTIM_TIMCR2_FEROM_Msk (0x3UL << HRTIM_TIMCR2_FEROM_Pos) /*!< 0x0000C000 */
8473 #define HRTIM_TIMCR2_FEROM HRTIM_TIMCR2_FEROM_Msk /*!< Fault and Event Rollover Mode */
8474 #define HRTIM_TIMCR2_FEROM_0 (0x1UL << HRTIM_TIMCR2_FEROM_Pos) /*!< 0x00004000 */
8475 #define HRTIM_TIMCR2_FEROM_1 (0x2UL << HRTIM_TIMCR2_FEROM_Pos) /*!< 0x00008000 */
8476 #define HRTIM_TIMCR2_GTCMP1_Pos (16U)
8477 #define HRTIM_TIMCR2_GTCMP1_Msk (0x1UL << HRTIM_TIMCR2_GTCMP1_Pos) /*!< 0x00010000 */
8478 #define HRTIM_TIMCR2_GTCMP1 HRTIM_TIMCR2_GTCMP1_Msk /*!< Greater than Compare 1 PWM mode */
8479 #define HRTIM_TIMCR2_GTCMP3_Pos (17U)
8480 #define HRTIM_TIMCR2_GTCMP3_Msk (0x1UL << HRTIM_TIMCR2_GTCMP3_Pos) /*!< 0x00020000 */
8481 #define HRTIM_TIMCR2_GTCMP3 HRTIM_TIMCR2_GTCMP3_Msk /*!< Greater than Compare 3 PWM mode */
8482 #define HRTIM_TIMCR2_TRGHLF_Pos (20U)
8483 #define HRTIM_TIMCR2_TRGHLF_Msk (0x1UL << HRTIM_TIMCR2_TRGHLF_Pos) /*!< 0x00100000 */
8484 #define HRTIM_TIMCR2_TRGHLF HRTIM_TIMCR2_TRGHLF_Msk /*!< Triggered-Half mode */
8485
8486 /**** Bit definition for Slave external event filtering register 3 ***********/
8487 #define HRTIM_EEFR3_EEVACE_Pos (0U)
8488 #define HRTIM_EEFR3_EEVACE_Msk (0x1UL << HRTIM_EEFR3_EEVACE_Pos) /*!< 0x00000001 */
8489 #define HRTIM_EEFR3_EEVACE HRTIM_EEFR3_EEVACE_Msk /*!< External Event A Counter Enable */
8490 #define HRTIM_EEFR3_EEVACRES_Pos (1U)
8491 #define HRTIM_EEFR3_EEVACRES_Msk (0x1UL << HRTIM_EEFR3_EEVACRES_Pos) /*!< 0x00000002 */
8492 #define HRTIM_EEFR3_EEVACRES HRTIM_EEFR3_EEVACRES_Msk /*!< External Event A Counter Reset */
8493 #define HRTIM_EEFR3_EEVARSTM_Pos (2U)
8494 #define HRTIM_EEFR3_EEVARSTM_Msk (0x1UL << HRTIM_EEFR3_EEVARSTM_Pos) /*!< 0x00000004 */
8495 #define HRTIM_EEFR3_EEVARSTM HRTIM_EEFR3_EEVARSTM_Msk /*!< External Event A Counter Reset Mode */
8496 #define HRTIM_EEFR3_EEVASEL_Pos (4U)
8497 #define HRTIM_EEFR3_EEVASEL_Msk (0xFUL << HRTIM_EEFR3_EEVASEL_Pos) /*!< 0x000000F0 */
8498 #define HRTIM_EEFR3_EEVASEL HRTIM_EEFR3_EEVASEL_Msk /*!< External Event A Selection */
8499 #define HRTIM_EEFR3_EEVASEL_0 (0x1UL << HRTIM_EEFR3_EEVASEL_Pos) /*!< 0x00000010 */
8500 #define HRTIM_EEFR3_EEVASEL_1 (0x2UL << HRTIM_EEFR3_EEVASEL_Pos) /*!< 0x00000020 */
8501 #define HRTIM_EEFR3_EEVASEL_2 (0x4UL << HRTIM_EEFR3_EEVASEL_Pos) /*!< 0x00000040 */
8502 #define HRTIM_EEFR3_EEVASEL_3 (0x8UL << HRTIM_EEFR3_EEVASEL_Pos) /*!< 0x00000080 */
8503 #define HRTIM_EEFR3_EEVACNT_Pos (8U)
8504 #define HRTIM_EEFR3_EEVACNT_Msk (0x3FUL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x00003F00 */
8505 #define HRTIM_EEFR3_EEVACNT HRTIM_EEFR3_EEVACNT_Msk /*!< External Event A Selection */
8506 #define HRTIM_EEFR3_EEVACNT_0 (0x1UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x00000100 */
8507 #define HRTIM_EEFR3_EEVACNT_1 (0x2UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x00000200 */
8508 #define HRTIM_EEFR3_EEVACNT_2 (0x4UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x00000400 */
8509 #define HRTIM_EEFR3_EEVACNT_3 (0x8UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x00000800 */
8510 #define HRTIM_EEFR3_EEVACNT_4 (0x10UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x00001000 */
8511 #define HRTIM_EEFR3_EEVACNT_5 (0x20UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x00002000 */
8512 #define HRTIM_EEFR3_EEVBCE_Pos (16U)
8513 #define HRTIM_EEFR3_EEVBCE_Msk (0x1UL << HRTIM_EEFR3_EEVBCE_Pos) /*!< 0x00010000 */
8514 #define HRTIM_EEFR3_EEVBCE HRTIM_EEFR3_EEVBCE_Msk /*!< External Event B Counter Enable */
8515 #define HRTIM_EEFR3_EEVBCRES_Pos (17U)
8516 #define HRTIM_EEFR3_EEVBCRES_Msk (0x1UL << HRTIM_EEFR3_EEVBCRES_Pos) /*!< 0x00020000 */
8517 #define HRTIM_EEFR3_EEVBCRES HRTIM_EEFR3_EEVBCRES_Msk /*!< External Event B Counter Reset */
8518 #define HRTIM_EEFR3_EEVBRSTM_Pos (18U)
8519 #define HRTIM_EEFR3_EEVBRSTM_Msk (0x1UL << HRTIM_EEFR3_EEVBRSTM_Pos) /*!< 0x00040000 */
8520 #define HRTIM_EEFR3_EEVBRSTM HRTIM_EEFR3_EEVBRSTM_Msk /*!< External Event B Counter Reset Mode */
8521 #define HRTIM_EEFR3_EEVBSEL_Pos (20U)
8522 #define HRTIM_EEFR3_EEVBSEL_Msk (0xFUL << HRTIM_EEFR3_EEVBSEL_Pos) /*!< 0x00F00000 */
8523 #define HRTIM_EEFR3_EEVBSEL HRTIM_EEFR3_EEVBSEL_Msk /*!< External Event B Selection */
8524 #define HRTIM_EEFR3_EEVBSEL_0 (0x1UL << HRTIM_EEFR3_EEVBSEL_Pos) /*!< 0x00100000 */
8525 #define HRTIM_EEFR3_EEVBSEL_1 (0x2UL << HRTIM_EEFR3_EEVBSEL_Pos) /*!< 0x00200000 */
8526 #define HRTIM_EEFR3_EEVBSEL_2 (0x4UL << HRTIM_EEFR3_EEVBSEL_Pos) /*!< 0x00400000 */
8527 #define HRTIM_EEFR3_EEVBSEL_3 (0x8UL << HRTIM_EEFR3_EEVBSEL_Pos) /*!< 0x00800000 */
8528 #define HRTIM_EEFR3_EEVBCNT_Pos (24U)
8529 #define HRTIM_EEFR3_EEVBCNT_Msk (0x3FUL << HRTIM_EEFR3_EEVBCNT_Pos) /*!< 0x3F000000 */
8530 #define HRTIM_EEFR3_EEVBCNT HRTIM_EEFR3_EEVBCNT_Msk /*!< External Event B Counter */
8531 #define HRTIM_EEFR3_EEVBCNT_0 (0x1UL << HRTIM_EEFR3_EEVBCNT_Pos) /*!< 0x01000000 */
8532 #define HRTIM_EEFR3_EEVBCNT_1 (0x2UL << HRTIM_EEFR3_EEVBCNT_Pos) /*!< 0x02000000 */
8533 #define HRTIM_EEFR3_EEVBCNT_2 (0x4UL << HRTIM_EEFR3_EEVBCNT_Pos) /*!< 0x04000000 */
8534 #define HRTIM_EEFR3_EEVBCNT_3 (0x8UL << HRTIM_EEFR3_EEVBCNT_Pos) /*!< 0x08000000 */
8535 #define HRTIM_EEFR3_EEVBCNT_4 (0x10UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x10000000 */
8536 #define HRTIM_EEFR3_EEVBCNT_5 (0x20UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x20000000 */
8537
8538 /**** Bit definition for Common HRTIM Timer control register 1 ****************/
8539 #define HRTIM_CR1_MUDIS_Pos (0U)
8540 #define HRTIM_CR1_MUDIS_Msk (0x1UL << HRTIM_CR1_MUDIS_Pos) /*!< 0x00000001 */
8541 #define HRTIM_CR1_MUDIS HRTIM_CR1_MUDIS_Msk /*!< Master update disable*/
8542 #define HRTIM_CR1_TAUDIS_Pos (1U)
8543 #define HRTIM_CR1_TAUDIS_Msk (0x1UL << HRTIM_CR1_TAUDIS_Pos) /*!< 0x00000002 */
8544 #define HRTIM_CR1_TAUDIS HRTIM_CR1_TAUDIS_Msk /*!< Timer A update disable*/
8545 #define HRTIM_CR1_TBUDIS_Pos (2U)
8546 #define HRTIM_CR1_TBUDIS_Msk (0x1UL << HRTIM_CR1_TBUDIS_Pos) /*!< 0x00000004 */
8547 #define HRTIM_CR1_TBUDIS HRTIM_CR1_TBUDIS_Msk /*!< Timer B update disable*/
8548 #define HRTIM_CR1_TCUDIS_Pos (3U)
8549 #define HRTIM_CR1_TCUDIS_Msk (0x1UL << HRTIM_CR1_TCUDIS_Pos) /*!< 0x00000008 */
8550 #define HRTIM_CR1_TCUDIS HRTIM_CR1_TCUDIS_Msk /*!< Timer C update disable*/
8551 #define HRTIM_CR1_TDUDIS_Pos (4U)
8552 #define HRTIM_CR1_TDUDIS_Msk (0x1UL << HRTIM_CR1_TDUDIS_Pos) /*!< 0x00000010 */
8553 #define HRTIM_CR1_TDUDIS HRTIM_CR1_TDUDIS_Msk /*!< Timer D update disable*/
8554 #define HRTIM_CR1_TEUDIS_Pos (5U)
8555 #define HRTIM_CR1_TEUDIS_Msk (0x1UL << HRTIM_CR1_TEUDIS_Pos) /*!< 0x00000020 */
8556 #define HRTIM_CR1_TEUDIS HRTIM_CR1_TEUDIS_Msk /*!< Timer E update disable*/
8557 #define HRTIM_CR1_TFUDIS_Pos (6U)
8558 #define HRTIM_CR1_TFUDIS_Msk (0x1UL << HRTIM_CR1_TFUDIS_Pos) /*!< 0x00000040 */
8559 #define HRTIM_CR1_TFUDIS HRTIM_CR1_TFUDIS_Msk /*!< Timer F update disable*/
8560 #define HRTIM_CR1_ADC1USRC_Pos (16U)
8561 #define HRTIM_CR1_ADC1USRC_Msk (0x7UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00070000 */
8562 #define HRTIM_CR1_ADC1USRC HRTIM_CR1_ADC1USRC_Msk /*!< ADC Trigger 1 update source */
8563 #define HRTIM_CR1_ADC1USRC_0 (0x1UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00010000 */
8564 #define HRTIM_CR1_ADC1USRC_1 (0x2UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00020000 */
8565 #define HRTIM_CR1_ADC1USRC_2 (0x4UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00040000 */
8566 #define HRTIM_CR1_ADC2USRC_Pos (19U)
8567 #define HRTIM_CR1_ADC2USRC_Msk (0x7UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00380000 */
8568 #define HRTIM_CR1_ADC2USRC HRTIM_CR1_ADC2USRC_Msk /*!< ADC Trigger 2 update source */
8569 #define HRTIM_CR1_ADC2USRC_0 (0x1UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00080000 */
8570 #define HRTIM_CR1_ADC2USRC_1 (0x2UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00100000 */
8571 #define HRTIM_CR1_ADC2USRC_2 (0x4UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00200000 */
8572 #define HRTIM_CR1_ADC3USRC_Pos (22U)
8573 #define HRTIM_CR1_ADC3USRC_Msk (0x7UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x01C00000 */
8574 #define HRTIM_CR1_ADC3USRC HRTIM_CR1_ADC3USRC_Msk /*!< ADC Trigger 3 update source */
8575 #define HRTIM_CR1_ADC3USRC_0 (0x1UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x00400000 */
8576 #define HRTIM_CR1_ADC3USRC_1 (0x2UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x00800000 */
8577 #define HRTIM_CR1_ADC3USRC_2 (0x4UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x01000000 */
8578 #define HRTIM_CR1_ADC4USRC_Pos (25U)
8579 #define HRTIM_CR1_ADC4USRC_Msk (0x7UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x0E000000 */
8580 #define HRTIM_CR1_ADC4USRC HRTIM_CR1_ADC4USRC_Msk /*!< ADC Trigger 4 update source */
8581 #define HRTIM_CR1_ADC4USRC_0 (0x1UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x02000000 */
8582 #define HRTIM_CR1_ADC4USRC_1 (0x2UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x04000000 */
8583 #define HRTIM_CR1_ADC4USRC_2 (0x0UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x0800000 */
8584
8585 /**** Bit definition for Common HRTIM Timer control register 2 ****************/
8586 #define HRTIM_CR2_MSWU_Pos (0U)
8587 #define HRTIM_CR2_MSWU_Msk (0x1UL << HRTIM_CR2_MSWU_Pos) /*!< 0x00000001 */
8588 #define HRTIM_CR2_MSWU HRTIM_CR2_MSWU_Msk /*!< Master software update */
8589 #define HRTIM_CR2_TASWU_Pos (1U)
8590 #define HRTIM_CR2_TASWU_Msk (0x1UL << HRTIM_CR2_TASWU_Pos) /*!< 0x00000002 */
8591 #define HRTIM_CR2_TASWU HRTIM_CR2_TASWU_Msk /*!< Timer A software update */
8592 #define HRTIM_CR2_TBSWU_Pos (2U)
8593 #define HRTIM_CR2_TBSWU_Msk (0x1UL << HRTIM_CR2_TBSWU_Pos) /*!< 0x00000004 */
8594 #define HRTIM_CR2_TBSWU HRTIM_CR2_TBSWU_Msk /*!< Timer B software update */
8595 #define HRTIM_CR2_TCSWU_Pos (3U)
8596 #define HRTIM_CR2_TCSWU_Msk (0x1UL << HRTIM_CR2_TCSWU_Pos) /*!< 0x00000008 */
8597 #define HRTIM_CR2_TCSWU HRTIM_CR2_TCSWU_Msk /*!< Timer C software update */
8598 #define HRTIM_CR2_TDSWU_Pos (4U)
8599 #define HRTIM_CR2_TDSWU_Msk (0x1UL << HRTIM_CR2_TDSWU_Pos) /*!< 0x00000010 */
8600 #define HRTIM_CR2_TDSWU HRTIM_CR2_TDSWU_Msk /*!< Timer D software update */
8601 #define HRTIM_CR2_TESWU_Pos (5U)
8602 #define HRTIM_CR2_TESWU_Msk (0x1UL << HRTIM_CR2_TESWU_Pos) /*!< 0x00000020 */
8603 #define HRTIM_CR2_TESWU HRTIM_CR2_TESWU_Msk /*!< Timer E software update */
8604 #define HRTIM_CR2_TFSWU_Pos (6U)
8605 #define HRTIM_CR2_TFSWU_Msk (0x1UL << HRTIM_CR2_TFSWU_Pos) /*!< 0x00000040 */
8606 #define HRTIM_CR2_TFSWU HRTIM_CR2_TFSWU_Msk /*!< Timer F software update */
8607 #define HRTIM_CR2_MRST_Pos (8U)
8608 #define HRTIM_CR2_MRST_Msk (0x1UL << HRTIM_CR2_MRST_Pos) /*!< 0x00000100 */
8609 #define HRTIM_CR2_MRST HRTIM_CR2_MRST_Msk /*!< Master count software reset */
8610 #define HRTIM_CR2_TARST_Pos (9U)
8611 #define HRTIM_CR2_TARST_Msk (0x1UL << HRTIM_CR2_TARST_Pos) /*!< 0x00000200 */
8612 #define HRTIM_CR2_TARST HRTIM_CR2_TARST_Msk /*!< Timer A count software reset */
8613 #define HRTIM_CR2_TBRST_Pos (10U)
8614 #define HRTIM_CR2_TBRST_Msk (0x1UL << HRTIM_CR2_TBRST_Pos) /*!< 0x00000400 */
8615 #define HRTIM_CR2_TBRST HRTIM_CR2_TBRST_Msk /*!< Timer B count software reset */
8616 #define HRTIM_CR2_TCRST_Pos (11U)
8617 #define HRTIM_CR2_TCRST_Msk (0x1UL << HRTIM_CR2_TCRST_Pos) /*!< 0x00000800 */
8618 #define HRTIM_CR2_TCRST HRTIM_CR2_TCRST_Msk /*!< Timer C count software reset */
8619 #define HRTIM_CR2_TDRST_Pos (12U)
8620 #define HRTIM_CR2_TDRST_Msk (0x1UL << HRTIM_CR2_TDRST_Pos) /*!< 0x00001000 */
8621 #define HRTIM_CR2_TDRST HRTIM_CR2_TDRST_Msk /*!< Timer D count software reset */
8622 #define HRTIM_CR2_TERST_Pos (13U)
8623 #define HRTIM_CR2_TERST_Msk (0x1UL << HRTIM_CR2_TERST_Pos) /*!< 0x00002000 */
8624 #define HRTIM_CR2_TERST HRTIM_CR2_TERST_Msk /*!< Timer E count software reset */
8625 #define HRTIM_CR2_TFRST_Pos (14U)
8626 #define HRTIM_CR2_TFRST_Msk (0x1UL << HRTIM_CR2_TFRST_Pos) /*!< 0x00004000 */
8627 #define HRTIM_CR2_TFRST HRTIM_CR2_TFRST_Msk /*!< Timer F count software reset */
8628 #define HRTIM_CR2_SWPA_Pos (16U)
8629 #define HRTIM_CR2_SWPA_Msk (0x1UL << HRTIM_CR2_SWPA_Pos) /*!< 0x00010000 */
8630 #define HRTIM_CR2_SWPA HRTIM_CR2_SWPA_Msk /*!< Timer A swap outputs */
8631 #define HRTIM_CR2_SWPB_Pos (17U)
8632 #define HRTIM_CR2_SWPB_Msk (0x1UL << HRTIM_CR2_SWPB_Pos) /*!< 0x00020000 */
8633 #define HRTIM_CR2_SWPB HRTIM_CR2_SWPB_Msk /*!< Timer B swap outputs */
8634 #define HRTIM_CR2_SWPC_Pos (18U)
8635 #define HRTIM_CR2_SWPC_Msk (0x1UL << HRTIM_CR2_SWPC_Pos) /*!< 0x00040000 */
8636 #define HRTIM_CR2_SWPC HRTIM_CR2_SWPC_Msk /*!< Timer C swap outputs */
8637 #define HRTIM_CR2_SWPD_Pos (19U)
8638 #define HRTIM_CR2_SWPD_Msk (0x1UL << HRTIM_CR2_SWPD_Pos) /*!< 0x00080000 */
8639 #define HRTIM_CR2_SWPD HRTIM_CR2_SWPD_Msk /*!< Timer D swap outputs */
8640 #define HRTIM_CR2_SWPE_Pos (20U)
8641 #define HRTIM_CR2_SWPE_Msk (0x1UL << HRTIM_CR2_SWPE_Pos) /*!< 0x00100000 */
8642 #define HRTIM_CR2_SWPE HRTIM_CR2_SWPE_Msk /*!< Timer E swap outputs */
8643 #define HRTIM_CR2_SWPF_Pos (21U)
8644 #define HRTIM_CR2_SWPF_Msk (0x1UL << HRTIM_CR2_SWPF_Pos) /*!< 0x00200000 */
8645 #define HRTIM_CR2_SWPF HRTIM_CR2_SWPF_Msk /*!< Timer F swap outputs */
8646
8647 /**** Bit definition for Common HRTIM Timer interrupt status register *********/
8648 #define HRTIM_ISR_FLT1_Pos (0U)
8649 #define HRTIM_ISR_FLT1_Msk (0x1UL << HRTIM_ISR_FLT1_Pos) /*!< 0x00000001 */
8650 #define HRTIM_ISR_FLT1 HRTIM_ISR_FLT1_Msk /*!< Fault 1 interrupt flag */
8651 #define HRTIM_ISR_FLT2_Pos (1U)
8652 #define HRTIM_ISR_FLT2_Msk (0x1UL << HRTIM_ISR_FLT2_Pos) /*!< 0x00000002 */
8653 #define HRTIM_ISR_FLT2 HRTIM_ISR_FLT2_Msk /*!< Fault 2 interrupt flag */
8654 #define HRTIM_ISR_FLT3_Pos (2U)
8655 #define HRTIM_ISR_FLT3_Msk (0x1UL << HRTIM_ISR_FLT3_Pos) /*!< 0x00000004 */
8656 #define HRTIM_ISR_FLT3 HRTIM_ISR_FLT3_Msk /*!< Fault 3 interrupt flag */
8657 #define HRTIM_ISR_FLT4_Pos (3U)
8658 #define HRTIM_ISR_FLT4_Msk (0x1UL << HRTIM_ISR_FLT4_Pos) /*!< 0x00000008 */
8659 #define HRTIM_ISR_FLT4 HRTIM_ISR_FLT4_Msk /*!< Fault 4 interrupt flag */
8660 #define HRTIM_ISR_FLT5_Pos (4U)
8661 #define HRTIM_ISR_FLT5_Msk (0x1UL << HRTIM_ISR_FLT5_Pos) /*!< 0x00000010 */
8662 #define HRTIM_ISR_FLT5 HRTIM_ISR_FLT5_Msk /*!< Fault 5 interrupt flag */
8663 #define HRTIM_ISR_SYSFLT_Pos (5U)
8664 #define HRTIM_ISR_SYSFLT_Msk (0x1UL << HRTIM_ISR_SYSFLT_Pos) /*!< 0x00000020 */
8665 #define HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT_Msk /*!< System Fault interrupt flag */
8666 #define HRTIM_ISR_FLT6_Pos (6U)
8667 #define HRTIM_ISR_FLT6_Msk (0x1UL << HRTIM_ISR_FLT6_Pos) /*!< 0x00000040 */
8668 #define HRTIM_ISR_FLT6 HRTIM_ISR_FLT6_Msk /*!< Fault 6 interrupt flag */
8669 #define HRTIM_ISR_DLLRDY_Pos (16U)
8670 #define HRTIM_ISR_DLLRDY_Msk (0x1UL << HRTIM_ISR_DLLRDY_Pos) /*!< 0x00010000 */
8671 #define HRTIM_ISR_DLLRDY HRTIM_ISR_DLLRDY_Msk /*!< DLL ready interrupt flag */
8672 #define HRTIM_ISR_BMPER_Pos (17U)
8673 #define HRTIM_ISR_BMPER_Msk (0x1UL << HRTIM_ISR_BMPER_Pos) /*!< 0x00020000 */
8674 #define HRTIM_ISR_BMPER HRTIM_ISR_BMPER_Msk /*!< Burst mode period interrupt flag */
8675
8676 /**** Bit definition for Common HRTIM Timer interrupt clear register **********/
8677 #define HRTIM_ICR_FLT1C_Pos (0U)
8678 #define HRTIM_ICR_FLT1C_Msk (0x1UL << HRTIM_ICR_FLT1C_Pos) /*!< 0x00000001 */
8679 #define HRTIM_ICR_FLT1C HRTIM_ICR_FLT1C_Msk /*!< Fault 1 interrupt flag clear */
8680 #define HRTIM_ICR_FLT2C_Pos (1U)
8681 #define HRTIM_ICR_FLT2C_Msk (0x1UL << HRTIM_ICR_FLT2C_Pos) /*!< 0x00000002 */
8682 #define HRTIM_ICR_FLT2C HRTIM_ICR_FLT2C_Msk /*!< Fault 2 interrupt flag clear */
8683 #define HRTIM_ICR_FLT3C_Pos (2U)
8684 #define HRTIM_ICR_FLT3C_Msk (0x1UL << HRTIM_ICR_FLT3C_Pos) /*!< 0x00000004 */
8685 #define HRTIM_ICR_FLT3C HRTIM_ICR_FLT3C_Msk /*!< Fault 3 interrupt flag clear */
8686 #define HRTIM_ICR_FLT4C_Pos (3U)
8687 #define HRTIM_ICR_FLT4C_Msk (0x1UL << HRTIM_ICR_FLT4C_Pos) /*!< 0x00000008 */
8688 #define HRTIM_ICR_FLT4C HRTIM_ICR_FLT4C_Msk /*!< Fault 4 interrupt flag clear */
8689 #define HRTIM_ICR_FLT5C_Pos (4U)
8690 #define HRTIM_ICR_FLT5C_Msk (0x1UL << HRTIM_ICR_FLT5C_Pos) /*!< 0x00000010 */
8691 #define HRTIM_ICR_FLT5C HRTIM_ICR_FLT5C_Msk /*!< Fault 5 interrupt flag clear */
8692 #define HRTIM_ICR_SYSFLTC_Pos (5U)
8693 #define HRTIM_ICR_SYSFLTC_Msk (0x1UL << HRTIM_ICR_SYSFLTC_Pos) /*!< 0x00000020 */
8694 #define HRTIM_ICR_SYSFLTC HRTIM_ICR_SYSFLTC_Msk /*!< System Fault interrupt flag clear */
8695
8696 #define HRTIM_ICR_FLT6C_Pos (6U)
8697 #define HRTIM_ICR_FLT6C_Msk (0x1UL << HRTIM_ICR_FLT6C_Pos) /*!< 0x00000040 */
8698 #define HRTIM_ICR_FLT6C HRTIM_ICR_FLT6C_Msk /*!< Fault 6 interrupt flag clear */
8699
8700 #define HRTIM_ICR_DLLRDYC_Pos (16U)
8701 #define HRTIM_ICR_DLLRDYC_Msk (0x1UL << HRTIM_ICR_DLLRDYC_Pos) /*!< 0x00010000 */
8702 #define HRTIM_ICR_DLLRDYC HRTIM_ICR_DLLRDYC_Msk /*!< DLL ready interrupt flag clear */
8703 #define HRTIM_ICR_BMPERC_Pos (17U)
8704 #define HRTIM_ICR_BMPERC_Msk (0x1UL << HRTIM_ICR_BMPERC_Pos) /*!< 0x00020000 */
8705 #define HRTIM_ICR_BMPERC HRTIM_ICR_BMPERC_Msk /*!< Burst mode period interrupt flag clear */
8706
8707 /**** Bit definition for Common HRTIM Timer interrupt enable register *********/
8708 #define HRTIM_IER_FLT1_Pos (0U)
8709 #define HRTIM_IER_FLT1_Msk (0x1UL << HRTIM_IER_FLT1_Pos) /*!< 0x00000001 */
8710 #define HRTIM_IER_FLT1 HRTIM_IER_FLT1_Msk /*!< Fault 1 interrupt enable */
8711 #define HRTIM_IER_FLT2_Pos (1U)
8712 #define HRTIM_IER_FLT2_Msk (0x1UL << HRTIM_IER_FLT2_Pos) /*!< 0x00000002 */
8713 #define HRTIM_IER_FLT2 HRTIM_IER_FLT2_Msk /*!< Fault 2 interrupt enable */
8714 #define HRTIM_IER_FLT3_Pos (2U)
8715 #define HRTIM_IER_FLT3_Msk (0x1UL << HRTIM_IER_FLT3_Pos) /*!< 0x00000004 */
8716 #define HRTIM_IER_FLT3 HRTIM_IER_FLT3_Msk /*!< Fault 3 interrupt enable */
8717 #define HRTIM_IER_FLT4_Pos (3U)
8718 #define HRTIM_IER_FLT4_Msk (0x1UL << HRTIM_IER_FLT4_Pos) /*!< 0x00000008 */
8719 #define HRTIM_IER_FLT4 HRTIM_IER_FLT4_Msk /*!< Fault 4 interrupt enable */
8720 #define HRTIM_IER_FLT5_Pos (4U)
8721 #define HRTIM_IER_FLT5_Msk (0x1UL << HRTIM_IER_FLT5_Pos) /*!< 0x00000010 */
8722 #define HRTIM_IER_FLT5 HRTIM_IER_FLT5_Msk /*!< Fault 5 interrupt enable */
8723 #define HRTIM_IER_SYSFLT_Pos (5U)
8724 #define HRTIM_IER_SYSFLT_Msk (0x1UL << HRTIM_IER_SYSFLT_Pos) /*!< 0x00000020 */
8725 #define HRTIM_IER_SYSFLT HRTIM_IER_SYSFLT_Msk /*!< System Fault interrupt enable */
8726 #define HRTIM_IER_FLT6_Pos (6U)
8727 #define HRTIM_IER_FLT6_Msk (0x1UL << HRTIM_IER_FLT6_Pos) /*!< 0x00000040 */
8728 #define HRTIM_IER_FLT6 HRTIM_IER_FLT6_Msk /*!< Fault 6 interrupt enable */
8729
8730 #define HRTIM_IER_DLLRDY_Pos (16U)
8731 #define HRTIM_IER_DLLRDY_Msk (0x1UL << HRTIM_IER_DLLRDY_Pos) /*!< 0x00010000 */
8732 #define HRTIM_IER_DLLRDY HRTIM_IER_DLLRDY_Msk /*!< DLL ready interrupt enable */
8733 #define HRTIM_IER_BMPER_Pos (17U)
8734 #define HRTIM_IER_BMPER_Msk (0x1UL << HRTIM_IER_BMPER_Pos) /*!< 0x00020000 */
8735 #define HRTIM_IER_BMPER HRTIM_IER_BMPER_Msk /*!< Burst mode period interrupt enable */
8736
8737 /**** Bit definition for Common HRTIM Timer output enable register ************/
8738 #define HRTIM_OENR_TA1OEN_Pos (0U)
8739 #define HRTIM_OENR_TA1OEN_Msk (0x1UL << HRTIM_OENR_TA1OEN_Pos) /*!< 0x00000001 */
8740 #define HRTIM_OENR_TA1OEN HRTIM_OENR_TA1OEN_Msk /*!< Timer A Output 1 enable */
8741 #define HRTIM_OENR_TA2OEN_Pos (1U)
8742 #define HRTIM_OENR_TA2OEN_Msk (0x1UL << HRTIM_OENR_TA2OEN_Pos) /*!< 0x00000002 */
8743 #define HRTIM_OENR_TA2OEN HRTIM_OENR_TA2OEN_Msk /*!< Timer A Output 2 enable */
8744 #define HRTIM_OENR_TB1OEN_Pos (2U)
8745 #define HRTIM_OENR_TB1OEN_Msk (0x1UL << HRTIM_OENR_TB1OEN_Pos) /*!< 0x00000004 */
8746 #define HRTIM_OENR_TB1OEN HRTIM_OENR_TB1OEN_Msk /*!< Timer B Output 1 enable */
8747 #define HRTIM_OENR_TB2OEN_Pos (3U)
8748 #define HRTIM_OENR_TB2OEN_Msk (0x1UL << HRTIM_OENR_TB2OEN_Pos) /*!< 0x00000008 */
8749 #define HRTIM_OENR_TB2OEN HRTIM_OENR_TB2OEN_Msk /*!< Timer B Output 2 enable */
8750 #define HRTIM_OENR_TC1OEN_Pos (4U)
8751 #define HRTIM_OENR_TC1OEN_Msk (0x1UL << HRTIM_OENR_TC1OEN_Pos) /*!< 0x00000010 */
8752 #define HRTIM_OENR_TC1OEN HRTIM_OENR_TC1OEN_Msk /*!< Timer C Output 1 enable */
8753 #define HRTIM_OENR_TC2OEN_Pos (5U)
8754 #define HRTIM_OENR_TC2OEN_Msk (0x1UL << HRTIM_OENR_TC2OEN_Pos) /*!< 0x00000020 */
8755 #define HRTIM_OENR_TC2OEN HRTIM_OENR_TC2OEN_Msk /*!< Timer C Output 2 enable */
8756 #define HRTIM_OENR_TD1OEN_Pos (6U)
8757 #define HRTIM_OENR_TD1OEN_Msk (0x1UL << HRTIM_OENR_TD1OEN_Pos) /*!< 0x00000040 */
8758 #define HRTIM_OENR_TD1OEN HRTIM_OENR_TD1OEN_Msk /*!< Timer D Output 1 enable */
8759 #define HRTIM_OENR_TD2OEN_Pos (7U)
8760 #define HRTIM_OENR_TD2OEN_Msk (0x1UL << HRTIM_OENR_TD2OEN_Pos) /*!< 0x00000080 */
8761 #define HRTIM_OENR_TD2OEN HRTIM_OENR_TD2OEN_Msk /*!< Timer D Output 2 enable */
8762 #define HRTIM_OENR_TE1OEN_Pos (8U)
8763 #define HRTIM_OENR_TE1OEN_Msk (0x1UL << HRTIM_OENR_TE1OEN_Pos) /*!< 0x00000100 */
8764 #define HRTIM_OENR_TE1OEN HRTIM_OENR_TE1OEN_Msk /*!< Timer E Output 1 enable */
8765 #define HRTIM_OENR_TE2OEN_Pos (9U)
8766 #define HRTIM_OENR_TE2OEN_Msk (0x1UL << HRTIM_OENR_TE2OEN_Pos) /*!< 0x00000200 */
8767 #define HRTIM_OENR_TE2OEN HRTIM_OENR_TE2OEN_Msk /*!< Timer E Output 2 enable */
8768 #define HRTIM_OENR_TF1OEN_Pos (10U)
8769 #define HRTIM_OENR_TF1OEN_Msk (0x1UL << HRTIM_OENR_TF1OEN_Pos) /*!< 0x00000400 */
8770 #define HRTIM_OENR_TF1OEN HRTIM_OENR_TF1OEN_Msk /*!< Timer F Output 1 enable */
8771 #define HRTIM_OENR_TF2OEN_Pos (11U)
8772 #define HRTIM_OENR_TF2OEN_Msk (0x1UL << HRTIM_OENR_TF2OEN_Pos) /*!< 0x00000800 */
8773 #define HRTIM_OENR_TF2OEN HRTIM_OENR_TF2OEN_Msk /*!< Timer F Output 2 enable */
8774
8775 /**** Bit definition for Common HRTIM Timer output disable register ***********/
8776 #define HRTIM_ODISR_TA1ODIS_Pos (0U)
8777 #define HRTIM_ODISR_TA1ODIS_Msk (0x1UL << HRTIM_ODISR_TA1ODIS_Pos) /*!< 0x00000001 */
8778 #define HRTIM_ODISR_TA1ODIS HRTIM_ODISR_TA1ODIS_Msk /*!< Timer A Output 1 disable */
8779 #define HRTIM_ODISR_TA2ODIS_Pos (1U)
8780 #define HRTIM_ODISR_TA2ODIS_Msk (0x1UL << HRTIM_ODISR_TA2ODIS_Pos) /*!< 0x00000002 */
8781 #define HRTIM_ODISR_TA2ODIS HRTIM_ODISR_TA2ODIS_Msk /*!< Timer A Output 2 disable */
8782 #define HRTIM_ODISR_TB1ODIS_Pos (2U)
8783 #define HRTIM_ODISR_TB1ODIS_Msk (0x1UL << HRTIM_ODISR_TB1ODIS_Pos) /*!< 0x00000004 */
8784 #define HRTIM_ODISR_TB1ODIS HRTIM_ODISR_TB1ODIS_Msk /*!< Timer B Output 1 disable */
8785 #define HRTIM_ODISR_TB2ODIS_Pos (3U)
8786 #define HRTIM_ODISR_TB2ODIS_Msk (0x1UL << HRTIM_ODISR_TB2ODIS_Pos) /*!< 0x00000008 */
8787 #define HRTIM_ODISR_TB2ODIS HRTIM_ODISR_TB2ODIS_Msk /*!< Timer B Output 2 disable */
8788 #define HRTIM_ODISR_TC1ODIS_Pos (4U)
8789 #define HRTIM_ODISR_TC1ODIS_Msk (0x1UL << HRTIM_ODISR_TC1ODIS_Pos) /*!< 0x00000010 */
8790 #define HRTIM_ODISR_TC1ODIS HRTIM_ODISR_TC1ODIS_Msk /*!< Timer C Output 1 disable */
8791 #define HRTIM_ODISR_TC2ODIS_Pos (5U)
8792 #define HRTIM_ODISR_TC2ODIS_Msk (0x1UL << HRTIM_ODISR_TC2ODIS_Pos) /*!< 0x00000020 */
8793 #define HRTIM_ODISR_TC2ODIS HRTIM_ODISR_TC2ODIS_Msk /*!< Timer C Output 2 disable */
8794 #define HRTIM_ODISR_TD1ODIS_Pos (6U)
8795 #define HRTIM_ODISR_TD1ODIS_Msk (0x1UL << HRTIM_ODISR_TD1ODIS_Pos) /*!< 0x00000040 */
8796 #define HRTIM_ODISR_TD1ODIS HRTIM_ODISR_TD1ODIS_Msk /*!< Timer D Output 1 disable */
8797 #define HRTIM_ODISR_TD2ODIS_Pos (7U)
8798 #define HRTIM_ODISR_TD2ODIS_Msk (0x1UL << HRTIM_ODISR_TD2ODIS_Pos) /*!< 0x00000080 */
8799 #define HRTIM_ODISR_TD2ODIS HRTIM_ODISR_TD2ODIS_Msk /*!< Timer D Output 2 disable */
8800 #define HRTIM_ODISR_TE1ODIS_Pos (8U)
8801 #define HRTIM_ODISR_TE1ODIS_Msk (0x1UL << HRTIM_ODISR_TE1ODIS_Pos) /*!< 0x00000100 */
8802 #define HRTIM_ODISR_TE1ODIS HRTIM_ODISR_TE1ODIS_Msk /*!< Timer E Output 1 disable */
8803 #define HRTIM_ODISR_TE2ODIS_Pos (9U)
8804 #define HRTIM_ODISR_TE2ODIS_Msk (0x1UL << HRTIM_ODISR_TE2ODIS_Pos) /*!< 0x00000200 */
8805 #define HRTIM_ODISR_TE2ODIS HRTIM_ODISR_TE2ODIS_Msk /*!< Timer E Output 2 disable */
8806 #define HRTIM_ODISR_TF1ODIS_Pos (10U)
8807 #define HRTIM_ODISR_TF1ODIS_Msk (0x1UL << HRTIM_ODISR_TF1ODIS_Pos) /*!< 0x00000100 */
8808 #define HRTIM_ODISR_TF1ODIS HRTIM_ODISR_TF1ODIS_Msk /*!< Timer F Output 1 disable */
8809 #define HRTIM_ODISR_TF2ODIS_Pos (11U)
8810 #define HRTIM_ODISR_TF2ODIS_Msk (0x1UL << HRTIM_ODISR_TF2ODIS_Pos) /*!< 0x00000200 */
8811 #define HRTIM_ODISR_TF2ODIS HRTIM_ODISR_TF2ODIS_Msk /*!< Timer F Output 2 disable */
8812
8813 /**** Bit definition for Common HRTIM Timer output disable status register *****/
8814 #define HRTIM_ODSR_TA1ODS_Pos (0U)
8815 #define HRTIM_ODSR_TA1ODS_Msk (0x1UL << HRTIM_ODSR_TA1ODS_Pos) /*!< 0x00000001 */
8816 #define HRTIM_ODSR_TA1ODS HRTIM_ODSR_TA1ODS_Msk /*!< Timer A Output 1 disable status */
8817 #define HRTIM_ODSR_TA2ODS_Pos (1U)
8818 #define HRTIM_ODSR_TA2ODS_Msk (0x1UL << HRTIM_ODSR_TA2ODS_Pos) /*!< 0x00000002 */
8819 #define HRTIM_ODSR_TA2ODS HRTIM_ODSR_TA2ODS_Msk /*!< Timer A Output 2 disable status */
8820 #define HRTIM_ODSR_TB1ODS_Pos (2U)
8821 #define HRTIM_ODSR_TB1ODS_Msk (0x1UL << HRTIM_ODSR_TB1ODS_Pos) /*!< 0x00000004 */
8822 #define HRTIM_ODSR_TB1ODS HRTIM_ODSR_TB1ODS_Msk /*!< Timer B Output 1 disable status */
8823 #define HRTIM_ODSR_TB2ODS_Pos (3U)
8824 #define HRTIM_ODSR_TB2ODS_Msk (0x1UL << HRTIM_ODSR_TB2ODS_Pos) /*!< 0x00000008 */
8825 #define HRTIM_ODSR_TB2ODS HRTIM_ODSR_TB2ODS_Msk /*!< Timer B Output 2 disable status */
8826 #define HRTIM_ODSR_TC1ODS_Pos (4U)
8827 #define HRTIM_ODSR_TC1ODS_Msk (0x1UL << HRTIM_ODSR_TC1ODS_Pos) /*!< 0x00000010 */
8828 #define HRTIM_ODSR_TC1ODS HRTIM_ODSR_TC1ODS_Msk /*!< Timer C Output 1 disable status */
8829 #define HRTIM_ODSR_TC2ODS_Pos (5U)
8830 #define HRTIM_ODSR_TC2ODS_Msk (0x1UL << HRTIM_ODSR_TC2ODS_Pos) /*!< 0x00000020 */
8831 #define HRTIM_ODSR_TC2ODS HRTIM_ODSR_TC2ODS_Msk /*!< Timer C Output 2 disable status */
8832 #define HRTIM_ODSR_TD1ODS_Pos (6U)
8833 #define HRTIM_ODSR_TD1ODS_Msk (0x1UL << HRTIM_ODSR_TD1ODS_Pos) /*!< 0x00000040 */
8834 #define HRTIM_ODSR_TD1ODS HRTIM_ODSR_TD1ODS_Msk /*!< Timer D Output 1 disable status */
8835 #define HRTIM_ODSR_TD2ODS_Pos (7U)
8836 #define HRTIM_ODSR_TD2ODS_Msk (0x1UL << HRTIM_ODSR_TD2ODS_Pos) /*!< 0x00000080 */
8837 #define HRTIM_ODSR_TD2ODS HRTIM_ODSR_TD2ODS_Msk /*!< Timer D Output 2 disable status */
8838 #define HRTIM_ODSR_TE1ODS_Pos (8U)
8839 #define HRTIM_ODSR_TE1ODS_Msk (0x1UL << HRTIM_ODSR_TE1ODS_Pos) /*!< 0x00000100 */
8840 #define HRTIM_ODSR_TE1ODS HRTIM_ODSR_TE1ODS_Msk /*!< Timer E Output 1 disable status */
8841 #define HRTIM_ODSR_TE2ODS_Pos (9U)
8842 #define HRTIM_ODSR_TE2ODS_Msk (0x1UL << HRTIM_ODSR_TE2ODS_Pos) /*!< 0x00000200 */
8843 #define HRTIM_ODSR_TE2ODS HRTIM_ODSR_TE2ODS_Msk /*!< Timer E Output 2 disable status */
8844 #define HRTIM_ODSR_TF1ODS_Pos (10U)
8845 #define HRTIM_ODSR_TF1ODS_Msk (0x1UL << HRTIM_ODSR_TF1ODS_Pos) /*!< 0x00000100 */
8846 #define HRTIM_ODSR_TF1ODS HRTIM_ODSR_TF1ODS_Msk /*!< Timer F Output 1 disable status */
8847 #define HRTIM_ODSR_TF2ODS_Pos (11U)
8848 #define HRTIM_ODSR_TF2ODS_Msk (0x1UL << HRTIM_ODSR_TF2ODS_Pos) /*!< 0x00000200 */
8849 #define HRTIM_ODSR_TF2ODS HRTIM_ODSR_TF2ODS_Msk /*!< Timer F Output 2 disable status */
8850
8851 /**** Bit definition for Common HRTIM Timer Burst mode control register ********/
8852 #define HRTIM_BMCR_BME_Pos (0U)
8853 #define HRTIM_BMCR_BME_Msk (0x1UL << HRTIM_BMCR_BME_Pos) /*!< 0x00000001 */
8854 #define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enbale */
8855 #define HRTIM_BMCR_BMOM_Pos (1U)
8856 #define HRTIM_BMCR_BMOM_Msk (0x1UL << HRTIM_BMCR_BMOM_Pos) /*!< 0x00000002 */
8857 #define HRTIM_BMCR_BMOM HRTIM_BMCR_BMOM_Msk /*!< Burst mode operating mode */
8858 #define HRTIM_BMCR_BMCLK_Pos (2U)
8859 #define HRTIM_BMCR_BMCLK_Msk (0xFUL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x0000003C */
8860 #define HRTIM_BMCR_BMCLK HRTIM_BMCR_BMCLK_Msk /*!< Burst mode clock source */
8861 #define HRTIM_BMCR_BMCLK_0 (0x1UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000004 */
8862 #define HRTIM_BMCR_BMCLK_1 (0x2UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000008 */
8863 #define HRTIM_BMCR_BMCLK_2 (0x4UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000010 */
8864 #define HRTIM_BMCR_BMCLK_3 (0x8UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000020 */
8865 #define HRTIM_BMCR_BMPRSC_Pos (6U)
8866 #define HRTIM_BMCR_BMPRSC_Msk (0xFUL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x000003C0 */
8867 #define HRTIM_BMCR_BMPRSC HRTIM_BMCR_BMPRSC_Msk /*!< Burst mode prescaler */
8868 #define HRTIM_BMCR_BMPRSC_0 (0x1UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000040 */
8869 #define HRTIM_BMCR_BMPRSC_1 (0x2UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000080 */
8870 #define HRTIM_BMCR_BMPRSC_2 (0x4UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000100 */
8871 #define HRTIM_BMCR_BMPRSC_3 (0x8UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000200 */
8872 #define HRTIM_BMCR_BMPREN_Pos (10U)
8873 #define HRTIM_BMCR_BMPREN_Msk (0x1UL << HRTIM_BMCR_BMPREN_Pos) /*!< 0x00000400 */
8874 #define HRTIM_BMCR_BMPREN HRTIM_BMCR_BMPREN_Msk /*!< Burst mode Preload bit */
8875 #define HRTIM_BMCR_MTBM_Pos (16U)
8876 #define HRTIM_BMCR_MTBM_Msk (0x1UL << HRTIM_BMCR_MTBM_Pos) /*!< 0x00010000 */
8877 #define HRTIM_BMCR_MTBM HRTIM_BMCR_MTBM_Msk /*!< Master Timer Burst mode */
8878 #define HRTIM_BMCR_TABM_Pos (17U)
8879 #define HRTIM_BMCR_TABM_Msk (0x1UL << HRTIM_BMCR_TABM_Pos) /*!< 0x00020000 */
8880 #define HRTIM_BMCR_TABM HRTIM_BMCR_TABM_Msk /*!< Timer A Burst mode */
8881 #define HRTIM_BMCR_TBBM_Pos (18U)
8882 #define HRTIM_BMCR_TBBM_Msk (0x1UL << HRTIM_BMCR_TBBM_Pos) /*!< 0x00040000 */
8883 #define HRTIM_BMCR_TBBM HRTIM_BMCR_TBBM_Msk /*!< Timer B Burst mode */
8884 #define HRTIM_BMCR_TCBM_Pos (19U)
8885 #define HRTIM_BMCR_TCBM_Msk (0x1UL << HRTIM_BMCR_TCBM_Pos) /*!< 0x00080000 */
8886 #define HRTIM_BMCR_TCBM HRTIM_BMCR_TCBM_Msk /*!< Timer C Burst mode */
8887 #define HRTIM_BMCR_TDBM_Pos (20U)
8888 #define HRTIM_BMCR_TDBM_Msk (0x1UL << HRTIM_BMCR_TDBM_Pos) /*!< 0x00100000 */
8889 #define HRTIM_BMCR_TDBM HRTIM_BMCR_TDBM_Msk /*!< Timer D Burst mode */
8890 #define HRTIM_BMCR_TEBM_Pos (21U)
8891 #define HRTIM_BMCR_TEBM_Msk (0x1UL << HRTIM_BMCR_TEBM_Pos) /*!< 0x00200000 */
8892 #define HRTIM_BMCR_TEBM HRTIM_BMCR_TEBM_Msk /*!< Timer E Burst mode */
8893
8894 #define HRTIM_BMCR_TFBM_Pos (22U)
8895 #define HRTIM_BMCR_TFBM_Msk (0x1UL << HRTIM_BMCR_TFBM_Pos) /*!< 0x00400000 */
8896 #define HRTIM_BMCR_TFBM HRTIM_BMCR_TFBM_Msk /*!< Timer F Burst mode */
8897
8898 #define HRTIM_BMCR_BMSTAT_Pos (31U)
8899 #define HRTIM_BMCR_BMSTAT_Msk (0x1UL << HRTIM_BMCR_BMSTAT_Pos) /*!< 0x80000000 */
8900 #define HRTIM_BMCR_BMSTAT HRTIM_BMCR_BMSTAT_Msk /*!< Burst mode status */
8901
8902 /**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/
8903 #define HRTIM_BMTRGR_SW_Pos (0U)
8904 #define HRTIM_BMTRGR_SW_Msk (0x1UL << HRTIM_BMTRGR_SW_Pos) /*!< 0x00000001 */
8905 #define HRTIM_BMTRGR_SW HRTIM_BMTRGR_SW_Msk /*!< Software start */
8906 #define HRTIM_BMTRGR_MSTRST_Pos (1U)
8907 #define HRTIM_BMTRGR_MSTRST_Msk (0x1UL << HRTIM_BMTRGR_MSTRST_Pos) /*!< 0x00000002 */
8908 #define HRTIM_BMTRGR_MSTRST HRTIM_BMTRGR_MSTRST_Msk /*!< Master reset */
8909 #define HRTIM_BMTRGR_MSTREP_Pos (2U)
8910 #define HRTIM_BMTRGR_MSTREP_Msk (0x1UL << HRTIM_BMTRGR_MSTREP_Pos) /*!< 0x00000004 */
8911 #define HRTIM_BMTRGR_MSTREP HRTIM_BMTRGR_MSTREP_Msk /*!< Master repetition */
8912 #define HRTIM_BMTRGR_MSTCMP1_Pos (3U)
8913 #define HRTIM_BMTRGR_MSTCMP1_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos) /*!< 0x00000008 */
8914 #define HRTIM_BMTRGR_MSTCMP1 HRTIM_BMTRGR_MSTCMP1_Msk /*!< Master compare 1 */
8915 #define HRTIM_BMTRGR_MSTCMP2_Pos (4U)
8916 #define HRTIM_BMTRGR_MSTCMP2_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos) /*!< 0x00000010 */
8917 #define HRTIM_BMTRGR_MSTCMP2 HRTIM_BMTRGR_MSTCMP2_Msk /*!< Master compare 2 */
8918 #define HRTIM_BMTRGR_MSTCMP3_Pos (5U)
8919 #define HRTIM_BMTRGR_MSTCMP3_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos) /*!< 0x00000020 */
8920 #define HRTIM_BMTRGR_MSTCMP3 HRTIM_BMTRGR_MSTCMP3_Msk /*!< Master compare 3 */
8921 #define HRTIM_BMTRGR_MSTCMP4_Pos (6U)
8922 #define HRTIM_BMTRGR_MSTCMP4_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos) /*!< 0x00000040 */
8923 #define HRTIM_BMTRGR_MSTCMP4 HRTIM_BMTRGR_MSTCMP4_Msk /*!< Master compare 4 */
8924 #define HRTIM_BMTRGR_TARST_Pos (7U)
8925 #define HRTIM_BMTRGR_TARST_Msk (0x1UL << HRTIM_BMTRGR_TARST_Pos) /*!< 0x00000080 */
8926 #define HRTIM_BMTRGR_TARST HRTIM_BMTRGR_TARST_Msk /*!< Timer A reset */
8927 #define HRTIM_BMTRGR_TAREP_Pos (8U)
8928 #define HRTIM_BMTRGR_TAREP_Msk (0x1UL << HRTIM_BMTRGR_TAREP_Pos) /*!< 0x00000100 */
8929 #define HRTIM_BMTRGR_TAREP HRTIM_BMTRGR_TAREP_Msk /*!< Timer A repetition */
8930 #define HRTIM_BMTRGR_TACMP1_Pos (9U)
8931 #define HRTIM_BMTRGR_TACMP1_Msk (0x1UL << HRTIM_BMTRGR_TACMP1_Pos) /*!< 0x00000200 */
8932 #define HRTIM_BMTRGR_TACMP1 HRTIM_BMTRGR_TACMP1_Msk /*!< Timer A compare 1 */
8933 #define HRTIM_BMTRGR_TACMP2_Pos (10U)
8934 #define HRTIM_BMTRGR_TACMP2_Msk (0x1UL << HRTIM_BMTRGR_TACMP2_Pos) /*!< 0x00000400 */
8935 #define HRTIM_BMTRGR_TACMP2 HRTIM_BMTRGR_TACMP2_Msk /*!< Timer A compare 2 */
8936 #define HRTIM_BMTRGR_TBRST_Pos (11U)
8937 #define HRTIM_BMTRGR_TBRST_Msk (0x1UL << HRTIM_BMTRGR_TBRST_Pos) /*!< 0x00000800 */
8938 #define HRTIM_BMTRGR_TBRST HRTIM_BMTRGR_TBRST_Msk /*!< Timer B reset */
8939 #define HRTIM_BMTRGR_TBREP_Pos (12U)
8940 #define HRTIM_BMTRGR_TBREP_Msk (0x1UL << HRTIM_BMTRGR_TBREP_Pos) /*!< 0x00001000 */
8941 #define HRTIM_BMTRGR_TBREP HRTIM_BMTRGR_TBREP_Msk /*!< Timer B repetition */
8942 #define HRTIM_BMTRGR_TBCMP1_Pos (13U)
8943 #define HRTIM_BMTRGR_TBCMP1_Msk (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos) /*!< 0x00002000 */
8944 #define HRTIM_BMTRGR_TBCMP1 HRTIM_BMTRGR_TBCMP1_Msk /*!< Timer B compare 1 */
8945 #define HRTIM_BMTRGR_TBCMP2_Pos (14U)
8946 #define HRTIM_BMTRGR_TBCMP2_Msk (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos) /*!< 0x00004000 */
8947 #define HRTIM_BMTRGR_TBCMP2 HRTIM_BMTRGR_TBCMP2_Msk /*!< Timer B compare 2 */
8948 #define HRTIM_BMTRGR_TCRST_Pos (15U)
8949 #define HRTIM_BMTRGR_TCRST_Msk (0x1UL << HRTIM_BMTRGR_TCRST_Pos) /*!< 0x00008000 */
8950 #define HRTIM_BMTRGR_TCRST HRTIM_BMTRGR_TCRST_Msk /*!< Timer C reset */
8951 #define HRTIM_BMTRGR_TCREP_Pos (16U)
8952 #define HRTIM_BMTRGR_TCREP_Msk (0x1UL << HRTIM_BMTRGR_TCREP_Pos) /*!< 0x00010000 */
8953 #define HRTIM_BMTRGR_TCREP HRTIM_BMTRGR_TCREP_Msk /*!< Timer C repetition */
8954 #define HRTIM_BMTRGR_TCCMP1_Pos (17U)
8955 #define HRTIM_BMTRGR_TCCMP1_Msk (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos) /*!< 0x00020000 */
8956 #define HRTIM_BMTRGR_TCCMP1 HRTIM_BMTRGR_TCCMP1_Msk /*!< Timer C compare 1 */
8957 #define HRTIM_BMTRGR_TFRST_Pos (18U)
8958 #define HRTIM_BMTRGR_TFRST_Msk (0x1UL << HRTIM_BMTRGR_TFRST_Pos) /*!< 0x00040000 */
8959 #define HRTIM_BMTRGR_TFRST HRTIM_BMTRGR_TFRST_Msk /*!< Timer F reset */
8960 #define HRTIM_BMTRGR_TCCMP2_Pos (18U)
8961 #define HRTIM_BMTRGR_TCCMP2_Msk (0x1UL << HRTIM_BMTRGR_TCCMP2_Pos) /*!< 0x00040000 */
8962 #define HRTIM_BMTRGR_TCCMP2 HRTIM_BMTRGR_TCCMP2_Msk /*!< Timer C compare 2 */
8963 #define HRTIM_BMTRGR_TDRST_Pos (19U)
8964 #define HRTIM_BMTRGR_TDRST_Msk (0x1UL << HRTIM_BMTRGR_TDRST_Pos) /*!< 0x00080000 */
8965 #define HRTIM_BMTRGR_TDRST HRTIM_BMTRGR_TDRST_Msk /*!< Timer D reset */
8966 #define HRTIM_BMTRGR_TDREP_Pos (20U)
8967 #define HRTIM_BMTRGR_TDREP_Msk (0x1UL << HRTIM_BMTRGR_TDREP_Pos) /*!< 0x00100000 */
8968 #define HRTIM_BMTRGR_TDREP HRTIM_BMTRGR_TDREP_Msk /*!< Timer D repetition */
8969 #define HRTIM_BMTRGR_TFREP_Pos (21U)
8970 #define HRTIM_BMTRGR_TFREP_Msk (0x1UL << HRTIM_BMTRGR_TFREP_Pos) /*!< 0x00200000 */
8971 #define HRTIM_BMTRGR_TFREP HRTIM_BMTRGR_TFREP_Msk /*!< Timer F repetition*/
8972 #define HRTIM_BMTRGR_TDCMP1_Pos (21U)
8973 #define HRTIM_BMTRGR_TDCMP1_Msk (0x1UL << HRTIM_BMTRGR_TDCMP1_Pos) /*!< 0x00200000 */
8974 #define HRTIM_BMTRGR_TDCMP1 HRTIM_BMTRGR_TDCMP1_Msk /*!< Timer D compare 1 */
8975 #define HRTIM_BMTRGR_TDCMP2_Pos (22U)
8976 #define HRTIM_BMTRGR_TDCMP2_Msk (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos) /*!< 0x00400000 */
8977 #define HRTIM_BMTRGR_TDCMP2 HRTIM_BMTRGR_TDCMP2_Msk /*!< Timer D compare 2 */
8978 #define HRTIM_BMTRGR_TFCMP1_Pos (23U)
8979 #define HRTIM_BMTRGR_TFCMP1_Msk (0x1UL << HRTIM_BMTRGR_TFCMP1_Pos) /*!< 0x00800000 */
8980 #define HRTIM_BMTRGR_TFCMP1 HRTIM_BMTRGR_TFCMP1_Msk /*!< Timer F compare 1 */
8981 #define HRTIM_BMTRGR_TERST_Pos (23U)
8982 #define HRTIM_BMTRGR_TERST_Msk (HRTIM_BMTRGR_TERST_Pos) /*!< 0x00800000 */
8983 #define HRTIM_BMTRGR_TERST HRTIM_BMTRGR_TERST_Msk /*!< Timer E reset */
8984 #define HRTIM_BMTRGR_TEREP_Pos (24U)
8985 #define HRTIM_BMTRGR_TEREP_Msk (0x1UL << HRTIM_BMTRGR_TEREP_Pos) /*!< 0x01000000 */
8986 #define HRTIM_BMTRGR_TEREP HRTIM_BMTRGR_TEREP_Msk /*!< Timer E repetition */
8987 #define HRTIM_BMTRGR_TECMP1_Pos (25U)
8988 #define HRTIM_BMTRGR_TECMP1_Msk (0x1UL << HRTIM_BMTRGR_TECMP1_Pos) /*!< 0x02000000 */
8989 #define HRTIM_BMTRGR_TECMP1 HRTIM_BMTRGR_TECMP1_Msk /*!< Timer E compare 1 */
8990 #define HRTIM_BMTRGR_TECMP2_Pos (26U)
8991 #define HRTIM_BMTRGR_TECMP2_Msk (0x1UL << HRTIM_BMTRGR_TECMP2_Pos) /*!< 0x04000000 */
8992 #define HRTIM_BMTRGR_TECMP2 HRTIM_BMTRGR_TECMP2_Msk /*!< Timer E compare 2 */
8993 #define HRTIM_BMTRGR_TAEEV7_Pos (27U)
8994 #define HRTIM_BMTRGR_TAEEV7_Msk (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos) /*!< 0x08000000 */
8995 #define HRTIM_BMTRGR_TAEEV7 HRTIM_BMTRGR_TAEEV7_Msk /*!< Timer A period following External Event7 */
8996 #define HRTIM_BMTRGR_TDEEV8_Pos (28U)
8997 #define HRTIM_BMTRGR_TDEEV8_Msk (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos) /*!< 0x10000000 */
8998 #define HRTIM_BMTRGR_TDEEV8 HRTIM_BMTRGR_TDEEV8_Msk /*!< Timer D period following External Event8 */
8999 #define HRTIM_BMTRGR_EEV7_Pos (29U)
9000 #define HRTIM_BMTRGR_EEV7_Msk (0x1UL << HRTIM_BMTRGR_EEV7_Pos) /*!< 0x20000000 */
9001 #define HRTIM_BMTRGR_EEV7 HRTIM_BMTRGR_EEV7_Msk /*!< External Event 7 */
9002 #define HRTIM_BMTRGR_EEV8_Pos (30U)
9003 #define HRTIM_BMTRGR_EEV8_Msk (0x1UL << HRTIM_BMTRGR_EEV8_Pos) /*!< 0x40000000 */
9004 #define HRTIM_BMTRGR_EEV8 HRTIM_BMTRGR_EEV8_Msk /*!< External Event 8 */
9005 #define HRTIM_BMTRGR_OCHPEV_Pos (31U)
9006 #define HRTIM_BMTRGR_OCHPEV_Msk (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos) /*!< 0x80000000 */
9007 #define HRTIM_BMTRGR_OCHPEV HRTIM_BMTRGR_OCHPEV_Msk /*!< on-chip Event */
9008
9009 /******************* Bit definition for HRTIM_BMCMPR register ***************/
9010 #define HRTIM_BMCMPR_BMCMPR_Pos (0U)
9011 #define HRTIM_BMCMPR_BMCMPR_Msk (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos) /*!< 0x0000FFFF */
9012 #define HRTIM_BMCMPR_BMCMPR HRTIM_BMCMPR_BMCMPR_Msk /*!<!<Burst Compare Value */
9013
9014 /******************* Bit definition for HRTIM_BMPER register ****************/
9015 #define HRTIM_BMPER_BMPER_Pos (0U)
9016 #define HRTIM_BMPER_BMPER_Msk (0xFFFFUL << HRTIM_BMPER_BMPER_Pos) /*!< 0x0000FFFF */
9017 #define HRTIM_BMPER_BMPER HRTIM_BMPER_BMPER_Msk /*!<!<Burst period Value */
9018
9019 /******************* Bit definition for HRTIM_EECR1 register ****************/
9020 #define HRTIM_EECR1_EE1SRC_Pos (0U)
9021 #define HRTIM_EECR1_EE1SRC_Msk (0x3UL << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000003 */
9022 #define HRTIM_EECR1_EE1SRC HRTIM_EECR1_EE1SRC_Msk /*!< External event 1 source */
9023 #define HRTIM_EECR1_EE1SRC_0 (0x1UL << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000001 */
9024 #define HRTIM_EECR1_EE1SRC_1 (0x2UL << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000002 */
9025 #define HRTIM_EECR1_EE1POL_Pos (2U)
9026 #define HRTIM_EECR1_EE1POL_Msk (0x1UL << HRTIM_EECR1_EE1POL_Pos) /*!< 0x00000004 */
9027 #define HRTIM_EECR1_EE1POL HRTIM_EECR1_EE1POL_Msk /*!< External event 1 Polarity */
9028 #define HRTIM_EECR1_EE1SNS_Pos (3U)
9029 #define HRTIM_EECR1_EE1SNS_Msk (0x3UL << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000018 */
9030 #define HRTIM_EECR1_EE1SNS HRTIM_EECR1_EE1SNS_Msk /*!< External event 1 sensitivity */
9031 #define HRTIM_EECR1_EE1SNS_0 (0x1UL << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000008 */
9032 #define HRTIM_EECR1_EE1SNS_1 (0x2UL << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000010 */
9033 #define HRTIM_EECR1_EE1FAST_Pos (5U)
9034 #define HRTIM_EECR1_EE1FAST_Msk (0x1UL << HRTIM_EECR1_EE1FAST_Pos) /*!< 0x00000020 */
9035 #define HRTIM_EECR1_EE1FAST HRTIM_EECR1_EE1FAST_Msk /*!< External event 1 Fast mode */
9036
9037 #define HRTIM_EECR1_EE2SRC_Pos (6U)
9038 #define HRTIM_EECR1_EE2SRC_Msk (0x3UL << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x000000C0 */
9039 #define HRTIM_EECR1_EE2SRC HRTIM_EECR1_EE2SRC_Msk /*!< External event 2 source */
9040 #define HRTIM_EECR1_EE2SRC_0 (0x1UL << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x00000040 */
9041 #define HRTIM_EECR1_EE2SRC_1 (0x2UL << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x00000080 */
9042 #define HRTIM_EECR1_EE2POL_Pos (8U)
9043 #define HRTIM_EECR1_EE2POL_Msk (0x1UL << HRTIM_EECR1_EE2POL_Pos) /*!< 0x00000100 */
9044 #define HRTIM_EECR1_EE2POL HRTIM_EECR1_EE2POL_Msk /*!< External event 2 Polarity */
9045 #define HRTIM_EECR1_EE2SNS_Pos (9U)
9046 #define HRTIM_EECR1_EE2SNS_Msk (0x3UL << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000600 */
9047 #define HRTIM_EECR1_EE2SNS HRTIM_EECR1_EE2SNS_Msk /*!< External event 2 sensitivity */
9048 #define HRTIM_EECR1_EE2SNS_0 (0x1UL << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000200 */
9049 #define HRTIM_EECR1_EE2SNS_1 (0x2UL << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000400 */
9050 #define HRTIM_EECR1_EE2FAST_Pos (11U)
9051 #define HRTIM_EECR1_EE2FAST_Msk (0x1UL << HRTIM_EECR1_EE2FAST_Pos) /*!< 0x00000800 */
9052 #define HRTIM_EECR1_EE2FAST HRTIM_EECR1_EE2FAST_Msk /*!< External event 2 Fast mode */
9053
9054 #define HRTIM_EECR1_EE3SRC_Pos (12U)
9055 #define HRTIM_EECR1_EE3SRC_Msk (0x3UL << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00003000 */
9056 #define HRTIM_EECR1_EE3SRC HRTIM_EECR1_EE3SRC_Msk /*!< External event 3 source */
9057 #define HRTIM_EECR1_EE3SRC_0 (0x1UL << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00001000 */
9058 #define HRTIM_EECR1_EE3SRC_1 (0x2UL << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00002000 */
9059 #define HRTIM_EECR1_EE3POL_Pos (14U)
9060 #define HRTIM_EECR1_EE3POL_Msk (0x1UL << HRTIM_EECR1_EE3POL_Pos) /*!< 0x00004000 */
9061 #define HRTIM_EECR1_EE3POL HRTIM_EECR1_EE3POL_Msk /*!< External event 3 Polarity */
9062 #define HRTIM_EECR1_EE3SNS_Pos (15U)
9063 #define HRTIM_EECR1_EE3SNS_Msk (0x3UL << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00018000 */
9064 #define HRTIM_EECR1_EE3SNS HRTIM_EECR1_EE3SNS_Msk /*!< External event 3 sensitivity */
9065 #define HRTIM_EECR1_EE3SNS_0 (0x1UL << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00008000 */
9066 #define HRTIM_EECR1_EE3SNS_1 (0x2UL << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00010000 */
9067 #define HRTIM_EECR1_EE3FAST_Pos (17U)
9068 #define HRTIM_EECR1_EE3FAST_Msk (0x1UL << HRTIM_EECR1_EE3FAST_Pos) /*!< 0x00020000 */
9069 #define HRTIM_EECR1_EE3FAST HRTIM_EECR1_EE3FAST_Msk /*!< External event 3 Fast mode */
9070
9071 #define HRTIM_EECR1_EE4SRC_Pos (18U)
9072 #define HRTIM_EECR1_EE4SRC_Msk (0x3UL << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x000C0000 */
9073 #define HRTIM_EECR1_EE4SRC HRTIM_EECR1_EE4SRC_Msk /*!< External event 4 source */
9074 #define HRTIM_EECR1_EE4SRC_0 (0x1UL << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x00040000 */
9075 #define HRTIM_EECR1_EE4SRC_1 (0x2UL << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x00080000 */
9076 #define HRTIM_EECR1_EE4POL_Pos (20U)
9077 #define HRTIM_EECR1_EE4POL_Msk (0x1UL << HRTIM_EECR1_EE4POL_Pos) /*!< 0x00100000 */
9078 #define HRTIM_EECR1_EE4POL HRTIM_EECR1_EE4POL_Msk /*!< External event 4 Polarity */
9079 #define HRTIM_EECR1_EE4SNS_Pos (21U)
9080 #define HRTIM_EECR1_EE4SNS_Msk (0x3UL << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00600000 */
9081 #define HRTIM_EECR1_EE4SNS HRTIM_EECR1_EE4SNS_Msk /*!< External event 4 sensitivity */
9082 #define HRTIM_EECR1_EE4SNS_0 (0x1UL << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00200000 */
9083 #define HRTIM_EECR1_EE4SNS_1 (0x2UL << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00400000 */
9084 #define HRTIM_EECR1_EE4FAST_Pos (23U)
9085 #define HRTIM_EECR1_EE4FAST_Msk (0x1UL << HRTIM_EECR1_EE4FAST_Pos) /*!< 0x00800000 */
9086 #define HRTIM_EECR1_EE4FAST HRTIM_EECR1_EE4FAST_Msk /*!< External event 4 Fast mode */
9087
9088 #define HRTIM_EECR1_EE5SRC_Pos (24U)
9089 #define HRTIM_EECR1_EE5SRC_Msk (0x3UL << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x03000000 */
9090 #define HRTIM_EECR1_EE5SRC HRTIM_EECR1_EE5SRC_Msk /*!< External event 5 source */
9091 #define HRTIM_EECR1_EE5SRC_0 (0x1UL << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x01000000 */
9092 #define HRTIM_EECR1_EE5SRC_1 (0x2UL << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x02000000 */
9093 #define HRTIM_EECR1_EE5POL_Pos (26U)
9094 #define HRTIM_EECR1_EE5POL_Msk (0x1UL << HRTIM_EECR1_EE5POL_Pos) /*!< 0x04000000 */
9095 #define HRTIM_EECR1_EE5POL HRTIM_EECR1_EE5POL_Msk /*!< External event 5 Polarity */
9096 #define HRTIM_EECR1_EE5SNS_Pos (27U)
9097 #define HRTIM_EECR1_EE5SNS_Msk (0x3UL << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x18000000 */
9098 #define HRTIM_EECR1_EE5SNS HRTIM_EECR1_EE5SNS_Msk /*!< External event 5 sensitivity */
9099 #define HRTIM_EECR1_EE5SNS_0 (0x1UL << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x08000000 */
9100 #define HRTIM_EECR1_EE5SNS_1 (0x2UL << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x10000000 */
9101 #define HRTIM_EECR1_EE5FAST_Pos (29U)
9102 #define HRTIM_EECR1_EE5FAST_Msk (0x1UL << HRTIM_EECR1_EE5FAST_Pos) /*!< 0x20000000 */
9103 #define HRTIM_EECR1_EE5FAST HRTIM_EECR1_EE5FAST_Msk /*!< External event 5 Fast mode */
9104
9105 /******************* Bit definition for HRTIM_EECR2 register ****************/
9106 #define HRTIM_EECR2_EE6SRC_Pos (0U)
9107 #define HRTIM_EECR2_EE6SRC_Msk (0x3UL << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000003 */
9108 #define HRTIM_EECR2_EE6SRC HRTIM_EECR2_EE6SRC_Msk /*!< External event 6 source */
9109 #define HRTIM_EECR2_EE6SRC_0 (0x1UL << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000001 */
9110 #define HRTIM_EECR2_EE6SRC_1 (0x2UL << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000002 */
9111 #define HRTIM_EECR2_EE6POL_Pos (2U)
9112 #define HRTIM_EECR2_EE6POL_Msk (0x1UL << HRTIM_EECR2_EE6POL_Pos) /*!< 0x00000004 */
9113 #define HRTIM_EECR2_EE6POL HRTIM_EECR2_EE6POL_Msk /*!< External event 6 Polarity */
9114 #define HRTIM_EECR2_EE6SNS_Pos (3U)
9115 #define HRTIM_EECR2_EE6SNS_Msk (0x3UL << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000018 */
9116 #define HRTIM_EECR2_EE6SNS HRTIM_EECR2_EE6SNS_Msk /*!< External event 6 sensitivity */
9117 #define HRTIM_EECR2_EE6SNS_0 (0x1UL << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000008 */
9118 #define HRTIM_EECR2_EE6SNS_1 (0x2UL << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000010 */
9119
9120 #define HRTIM_EECR2_EE7SRC_Pos (6U)
9121 #define HRTIM_EECR2_EE7SRC_Msk (0x3UL << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x000000C0 */
9122 #define HRTIM_EECR2_EE7SRC HRTIM_EECR2_EE7SRC_Msk /*!< External event 7 source */
9123 #define HRTIM_EECR2_EE7SRC_0 (0x1UL << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x00000040 */
9124 #define HRTIM_EECR2_EE7SRC_1 (0x2UL << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x00000080 */
9125 #define HRTIM_EECR2_EE7POL_Pos (8U)
9126 #define HRTIM_EECR2_EE7POL_Msk (0x1UL << HRTIM_EECR2_EE7POL_Pos) /*!< 0x00000100 */
9127 #define HRTIM_EECR2_EE7POL HRTIM_EECR2_EE7POL_Msk /*!< External event 7 Polarity */
9128 #define HRTIM_EECR2_EE7SNS_Pos (9U)
9129 #define HRTIM_EECR2_EE7SNS_Msk (0x3UL << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000600 */
9130 #define HRTIM_EECR2_EE7SNS HRTIM_EECR2_EE7SNS_Msk /*!< External event 7 sensitivity */
9131 #define HRTIM_EECR2_EE7SNS_0 (0x1UL << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000200 */
9132 #define HRTIM_EECR2_EE7SNS_1 (0x2UL << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000400 */
9133
9134 #define HRTIM_EECR2_EE8SRC_Pos (12U)
9135 #define HRTIM_EECR2_EE8SRC_Msk (0x3UL << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00003000 */
9136 #define HRTIM_EECR2_EE8SRC HRTIM_EECR2_EE8SRC_Msk /*!< External event 8 source */
9137 #define HRTIM_EECR2_EE8SRC_0 (0x1UL << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00001000 */
9138 #define HRTIM_EECR2_EE8SRC_1 (0x2UL << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00002000 */
9139 #define HRTIM_EECR2_EE8POL_Pos (14U)
9140 #define HRTIM_EECR2_EE8POL_Msk (0x1UL << HRTIM_EECR2_EE8POL_Pos) /*!< 0x00004000 */
9141 #define HRTIM_EECR2_EE8POL HRTIM_EECR2_EE8POL_Msk /*!< External event 8 Polarity */
9142 #define HRTIM_EECR2_EE8SNS_Pos (15U)
9143 #define HRTIM_EECR2_EE8SNS_Msk (0x3UL << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00018000 */
9144 #define HRTIM_EECR2_EE8SNS HRTIM_EECR2_EE8SNS_Msk /*!< External event 8 sensitivity */
9145 #define HRTIM_EECR2_EE8SNS_0 (0x1UL << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00008000 */
9146 #define HRTIM_EECR2_EE8SNS_1 (0x2UL << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00010000 */
9147
9148 #define HRTIM_EECR2_EE9SRC_Pos (18U)
9149 #define HRTIM_EECR2_EE9SRC_Msk (0x3UL << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x000C0000 */
9150 #define HRTIM_EECR2_EE9SRC HRTIM_EECR2_EE9SRC_Msk /*!< External event 9 source */
9151 #define HRTIM_EECR2_EE9SRC_0 (0x1UL << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x00040000 */
9152 #define HRTIM_EECR2_EE9SRC_1 (0x2UL << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x00080000 */
9153 #define HRTIM_EECR2_EE9POL_Pos (20U)
9154 #define HRTIM_EECR2_EE9POL_Msk (0x1UL << HRTIM_EECR2_EE9POL_Pos) /*!< 0x00100000 */
9155 #define HRTIM_EECR2_EE9POL HRTIM_EECR2_EE9POL_Msk /*!< External event 9 Polarity */
9156 #define HRTIM_EECR2_EE9SNS_Pos (21U)
9157 #define HRTIM_EECR2_EE9SNS_Msk (0x3UL << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00600000 */
9158 #define HRTIM_EECR2_EE9SNS HRTIM_EECR2_EE9SNS_Msk /*!< External event 9 sensitivity */
9159 #define HRTIM_EECR2_EE9SNS_0 (0x1UL << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00200000 */
9160 #define HRTIM_EECR2_EE9SNS_1 (0x2UL << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00400000 */
9161
9162 #define HRTIM_EECR2_EE10SRC_Pos (24U)
9163 #define HRTIM_EECR2_EE10SRC_Msk (0x3UL << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x03000000 */
9164 #define HRTIM_EECR2_EE10SRC HRTIM_EECR2_EE10SRC_Msk /*!< External event 10 source */
9165 #define HRTIM_EECR2_EE10SRC_0 (0x1UL << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x01000000 */
9166 #define HRTIM_EECR2_EE10SRC_1 (0x2UL << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x02000000 */
9167 #define HRTIM_EECR2_EE10POL_Pos (26U)
9168 #define HRTIM_EECR2_EE10POL_Msk (0x1UL << HRTIM_EECR2_EE10POL_Pos) /*!< 0x04000000 */
9169 #define HRTIM_EECR2_EE10POL HRTIM_EECR2_EE10POL_Msk /*!< External event 10 Polarity */
9170 #define HRTIM_EECR2_EE10SNS_Pos (27U)
9171 #define HRTIM_EECR2_EE10SNS_Msk (0x3UL << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x18000000 */
9172 #define HRTIM_EECR2_EE10SNS HRTIM_EECR2_EE10SNS_Msk /*!< External event 10 sensitivity */
9173 #define HRTIM_EECR2_EE10SNS_0 (0x1UL << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x08000000 */
9174 #define HRTIM_EECR2_EE10SNS_1 (0x2UL << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x10000000 */
9175
9176 /******************* Bit definition for HRTIM_EECR3 register ****************/
9177 #define HRTIM_EECR3_EE6F_Pos (0U)
9178 #define HRTIM_EECR3_EE6F_Msk (0xFUL << HRTIM_EECR3_EE6F_Pos) /*!< 0x0000000F */
9179 #define HRTIM_EECR3_EE6F HRTIM_EECR3_EE6F_Msk /*!< External event 6 filter */
9180 #define HRTIM_EECR3_EE6F_0 (0x1UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000001 */
9181 #define HRTIM_EECR3_EE6F_1 (0x2UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000002 */
9182 #define HRTIM_EECR3_EE6F_2 (0x4UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000004 */
9183 #define HRTIM_EECR3_EE6F_3 (0x8UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000008 */
9184 #define HRTIM_EECR3_EE7F_Pos (6U)
9185 #define HRTIM_EECR3_EE7F_Msk (0xFUL << HRTIM_EECR3_EE7F_Pos) /*!< 0x000003C0 */
9186 #define HRTIM_EECR3_EE7F HRTIM_EECR3_EE7F_Msk /*!< External event 7 filter */
9187 #define HRTIM_EECR3_EE7F_0 (0x1UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000040 */
9188 #define HRTIM_EECR3_EE7F_1 (0x2UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000080 */
9189 #define HRTIM_EECR3_EE7F_2 (0x4UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000100 */
9190 #define HRTIM_EECR3_EE7F_3 (0x8UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000200 */
9191 #define HRTIM_EECR3_EE8F_Pos (12U)
9192 #define HRTIM_EECR3_EE8F_Msk (0xFUL << HRTIM_EECR3_EE8F_Pos) /*!< 0x0000F000 */
9193 #define HRTIM_EECR3_EE8F HRTIM_EECR3_EE8F_Msk /*!< External event 8 filter */
9194 #define HRTIM_EECR3_EE8F_0 (0x1UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00001000 */
9195 #define HRTIM_EECR3_EE8F_1 (0x2UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00002000 */
9196 #define HRTIM_EECR3_EE8F_2 (0x4UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00004000 */
9197 #define HRTIM_EECR3_EE8F_3 (0x8UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00008000 */
9198 #define HRTIM_EECR3_EE9F_Pos (18U)
9199 #define HRTIM_EECR3_EE9F_Msk (0xFUL << HRTIM_EECR3_EE9F_Pos) /*!< 0x003C0000 */
9200 #define HRTIM_EECR3_EE9F HRTIM_EECR3_EE9F_Msk /*!< External event 9 filter */
9201 #define HRTIM_EECR3_EE9F_0 (0x1UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00040000 */
9202 #define HRTIM_EECR3_EE9F_1 (0x2UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00080000 */
9203 #define HRTIM_EECR3_EE9F_2 (0x4UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00100000 */
9204 #define HRTIM_EECR3_EE9F_3 (0x8UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00200000 */
9205 #define HRTIM_EECR3_EE10F_Pos (24U)
9206 #define HRTIM_EECR3_EE10F_Msk (0xFUL << HRTIM_EECR3_EE10F_Pos) /*!< 0x0F000000 */
9207 #define HRTIM_EECR3_EE10F HRTIM_EECR3_EE10F_Msk /*!< External event 10 filter */
9208 #define HRTIM_EECR3_EE10F_0 (0x1UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x01000000 */
9209 #define HRTIM_EECR3_EE10F_1 (0x2UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x02000000 */
9210 #define HRTIM_EECR3_EE10F_2 (0x4UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x04000000 */
9211 #define HRTIM_EECR3_EE10F_3 (0x8UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x08000000 */
9212 #define HRTIM_EECR3_EEVSD_Pos (30U)
9213 #define HRTIM_EECR3_EEVSD_Msk (0x3UL << HRTIM_EECR3_EEVSD_Pos) /*!< 0xC0000000 */
9214 #define HRTIM_EECR3_EEVSD HRTIM_EECR3_EEVSD_Msk /*!< External event sampling clock division */
9215 #define HRTIM_EECR3_EEVSD_0 (0x1UL << HRTIM_EECR3_EEVSD_Pos) /*!< 0x40000000 */
9216 #define HRTIM_EECR3_EEVSD_1 (0x2UL << HRTIM_EECR3_EEVSD_Pos) /*!< 0x80000000 */
9217
9218 /******************* Bit definition for HRTIM_ADC1R register ****************/
9219 #define HRTIM_ADC1R_AD1MC1_Pos (0U)
9220 #define HRTIM_ADC1R_AD1MC1_Msk (0x1UL << HRTIM_ADC1R_AD1MC1_Pos) /*!< 0x00000001 */
9221 #define HRTIM_ADC1R_AD1MC1 HRTIM_ADC1R_AD1MC1_Msk /*!< ADC Trigger 1 on master compare 1 */
9222 #define HRTIM_ADC1R_AD1MC2_Pos (1U)
9223 #define HRTIM_ADC1R_AD1MC2_Msk (0x1UL << HRTIM_ADC1R_AD1MC2_Pos) /*!< 0x00000002 */
9224 #define HRTIM_ADC1R_AD1MC2 HRTIM_ADC1R_AD1MC2_Msk /*!< ADC Trigger 1 on master compare 2 */
9225 #define HRTIM_ADC1R_AD1MC3_Pos (2U)
9226 #define HRTIM_ADC1R_AD1MC3_Msk (0x1UL << HRTIM_ADC1R_AD1MC3_Pos) /*!< 0x00000004 */
9227 #define HRTIM_ADC1R_AD1MC3 HRTIM_ADC1R_AD1MC3_Msk /*!< ADC Trigger 1 on master compare 3 */
9228 #define HRTIM_ADC1R_AD1MC4_Pos (3U)
9229 #define HRTIM_ADC1R_AD1MC4_Msk (0x1UL << HRTIM_ADC1R_AD1MC4_Pos) /*!< 0x00000008 */
9230 #define HRTIM_ADC1R_AD1MC4 HRTIM_ADC1R_AD1MC4_Msk /*!< ADC Trigger 1 on master compare 4 */
9231 #define HRTIM_ADC1R_AD1MPER_Pos (4U)
9232 #define HRTIM_ADC1R_AD1MPER_Msk (0x1UL << HRTIM_ADC1R_AD1MPER_Pos) /*!< 0x00000010 */
9233 #define HRTIM_ADC1R_AD1MPER HRTIM_ADC1R_AD1MPER_Msk /*!< ADC Trigger 1 on master period */
9234 #define HRTIM_ADC1R_AD1EEV1_Pos (5U)
9235 #define HRTIM_ADC1R_AD1EEV1_Msk (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos) /*!< 0x00000020 */
9236 #define HRTIM_ADC1R_AD1EEV1 HRTIM_ADC1R_AD1EEV1_Msk /*!< ADC Trigger 1 on external event 1 */
9237 #define HRTIM_ADC1R_AD1EEV2_Pos (6U)
9238 #define HRTIM_ADC1R_AD1EEV2_Msk (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos) /*!< 0x00000040 */
9239 #define HRTIM_ADC1R_AD1EEV2 HRTIM_ADC1R_AD1EEV2_Msk /*!< ADC Trigger 1 on external event 2 */
9240 #define HRTIM_ADC1R_AD1EEV3_Pos (7U)
9241 #define HRTIM_ADC1R_AD1EEV3_Msk (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos) /*!< 0x00000080 */
9242 #define HRTIM_ADC1R_AD1EEV3 HRTIM_ADC1R_AD1EEV3_Msk /*!< ADC Trigger 1 on external event 3 */
9243 #define HRTIM_ADC1R_AD1EEV4_Pos (8U)
9244 #define HRTIM_ADC1R_AD1EEV4_Msk (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos) /*!< 0x00000100 */
9245 #define HRTIM_ADC1R_AD1EEV4 HRTIM_ADC1R_AD1EEV4_Msk /*!< ADC Trigger 1 on external event 4 */
9246 #define HRTIM_ADC1R_AD1EEV5_Pos (9U)
9247 #define HRTIM_ADC1R_AD1EEV5_Msk (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos) /*!< 0x00000200 */
9248 #define HRTIM_ADC1R_AD1EEV5 HRTIM_ADC1R_AD1EEV5_Msk /*!< ADC Trigger 1 on external event 5 */
9249
9250 #define HRTIM_ADC1R_AD1TFC2_Pos (10U)
9251 #define HRTIM_ADC1R_AD1TFC2_Msk (0x1UL << HRTIM_ADC1R_AD1TFC2_Pos) /*!< 0x00000400 */
9252 #define HRTIM_ADC1R_AD1TFC2 HRTIM_ADC1R_AD1TFC2_Msk /*!< ADC Trigger 1 on Timer F compare 2 */
9253
9254 #define HRTIM_ADC1R_AD1TAC3_Pos (11U)
9255 #define HRTIM_ADC1R_AD1TAC3_Msk (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos) /*!< 0x00000800 */
9256 #define HRTIM_ADC1R_AD1TAC3 HRTIM_ADC1R_AD1TAC3_Msk /*!< ADC Trigger 1 on Timer A compare 3 */
9257 #define HRTIM_ADC1R_AD1TAC4_Pos (12U)
9258 #define HRTIM_ADC1R_AD1TAC4_Msk (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos) /*!< 0x00001000 */
9259 #define HRTIM_ADC1R_AD1TAC4 HRTIM_ADC1R_AD1TAC4_Msk /*!< ADC Trigger 1 on Timer A compare 4 */
9260 #define HRTIM_ADC1R_AD1TAPER_Pos (13U)
9261 #define HRTIM_ADC1R_AD1TAPER_Msk (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos) /*!< 0x00002000 */
9262 #define HRTIM_ADC1R_AD1TAPER HRTIM_ADC1R_AD1TAPER_Msk /*!< ADC Trigger 1 on Timer A period */
9263 #define HRTIM_ADC1R_AD1TARST_Pos (14U)
9264 #define HRTIM_ADC1R_AD1TARST_Msk (0x1UL << HRTIM_ADC1R_AD1TARST_Pos) /*!< 0x00004000 */
9265 #define HRTIM_ADC1R_AD1TARST HRTIM_ADC1R_AD1TARST_Msk /*!< ADC Trigger 1 on Timer A reset */
9266
9267 #define HRTIM_ADC1R_AD1TFC3_Pos (15U)
9268 #define HRTIM_ADC1R_AD1TFC3_Msk (0x1UL << HRTIM_ADC1R_AD1TFC3_Pos) /*!< 0x00008000 */
9269 #define HRTIM_ADC1R_AD1TFC3 HRTIM_ADC1R_AD1TFC3_Msk /*!< ADC Trigger 1 on Timer F compare 3 */
9270
9271 #define HRTIM_ADC1R_AD1TBC3_Pos (16U)
9272 #define HRTIM_ADC1R_AD1TBC3_Msk (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos) /*!< 0x00010000 */
9273 #define HRTIM_ADC1R_AD1TBC3 HRTIM_ADC1R_AD1TBC3_Msk /*!< ADC Trigger 1 on Timer B compare 3 */
9274 #define HRTIM_ADC1R_AD1TBC4_Pos (17U)
9275 #define HRTIM_ADC1R_AD1TBC4_Msk (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos) /*!< 0x00020000 */
9276 #define HRTIM_ADC1R_AD1TBC4 HRTIM_ADC1R_AD1TBC4_Msk /*!< ADC Trigger 1 on Timer B compare 4 */
9277 #define HRTIM_ADC1R_AD1TBPER_Pos (18U)
9278 #define HRTIM_ADC1R_AD1TBPER_Msk (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos) /*!< 0x00040000 */
9279 #define HRTIM_ADC1R_AD1TBPER HRTIM_ADC1R_AD1TBPER_Msk /*!< ADC Trigger 1 on Timer B period */
9280 #define HRTIM_ADC1R_AD1TBRST_Pos (19U)
9281 #define HRTIM_ADC1R_AD1TBRST_Msk (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos) /*!< 0x00080000 */
9282 #define HRTIM_ADC1R_AD1TBRST HRTIM_ADC1R_AD1TBRST_Msk /*!< ADC Trigger 1 on Timer B reset */
9283
9284 #define HRTIM_ADC1R_AD1TFC4_Pos (20U)
9285 #define HRTIM_ADC1R_AD1TFC4_Msk (0x1UL << HRTIM_ADC1R_AD1TFC4_Pos) /*!< 0x00100000 */
9286 #define HRTIM_ADC1R_AD1TFC4 HRTIM_ADC1R_AD1TFC4_Msk /*!< ADC Trigger 1 on Timer F compare 4 */
9287
9288 #define HRTIM_ADC1R_AD1TCC3_Pos (21U)
9289 #define HRTIM_ADC1R_AD1TCC3_Msk (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos) /*!< 0x00200000 */
9290 #define HRTIM_ADC1R_AD1TCC3 HRTIM_ADC1R_AD1TCC3_Msk /*!< ADC Trigger 1 on Timer C compare 3 */
9291 #define HRTIM_ADC1R_AD1TCC4_Pos (22U)
9292 #define HRTIM_ADC1R_AD1TCC4_Msk (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos) /*!< 0x00400000 */
9293 #define HRTIM_ADC1R_AD1TCC4 HRTIM_ADC1R_AD1TCC4_Msk /*!< ADC Trigger 1 on Timer C compare 4 */
9294 #define HRTIM_ADC1R_AD1TCPER_Pos (23U)
9295 #define HRTIM_ADC1R_AD1TCPER_Msk (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos) /*!< 0x00800000 */
9296 #define HRTIM_ADC1R_AD1TCPER HRTIM_ADC1R_AD1TCPER_Msk /*!< ADC Trigger 1 on Timer C period */
9297
9298 #define HRTIM_ADC1R_AD1TFPER_Pos (24U)
9299 #define HRTIM_ADC1R_AD1TFPER_Msk (0x1UL << HRTIM_ADC1R_AD1TFPER_Pos) /*!< 0x01000000 */
9300 #define HRTIM_ADC1R_AD1TFPER HRTIM_ADC1R_AD1TFPER_Msk /*!< ADC Trigger 1 on Timer F period */
9301
9302 #define HRTIM_ADC1R_AD1TDC3_Pos (25U)
9303 #define HRTIM_ADC1R_AD1TDC3_Msk (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos) /*!< 0x02000000 */
9304 #define HRTIM_ADC1R_AD1TDC3 HRTIM_ADC1R_AD1TDC3_Msk /*!< ADC Trigger 1 on Timer D compare 3 */
9305 #define HRTIM_ADC1R_AD1TDC4_Pos (26U)
9306 #define HRTIM_ADC1R_AD1TDC4_Msk (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos) /*!< 0x04000000 */
9307 #define HRTIM_ADC1R_AD1TDC4 HRTIM_ADC1R_AD1TDC4_Msk /*!< ADC Trigger 1 on Timer D compare 4 */
9308 #define HRTIM_ADC1R_AD1TDPER_Pos (27U)
9309 #define HRTIM_ADC1R_AD1TDPER_Msk (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos) /*!< 0x08000000 */
9310 #define HRTIM_ADC1R_AD1TDPER HRTIM_ADC1R_AD1TDPER_Msk /*!< ADC Trigger 1 on Timer D period */
9311
9312 #define HRTIM_ADC1R_AD1TFRST_Pos (28U)
9313 #define HRTIM_ADC1R_AD1TFRST_Msk (0x1UL << HRTIM_ADC1R_AD1TFRST_Pos) /*!< 0x10000000 */
9314 #define HRTIM_ADC1R_AD1TFRST HRTIM_ADC1R_AD1TFRST_Msk /*!< ADC Trigger 1 on Timer F reset */
9315
9316 #define HRTIM_ADC1R_AD1TEC3_Pos (29U)
9317 #define HRTIM_ADC1R_AD1TEC3_Msk (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos) /*!< 0x20000000 */
9318 #define HRTIM_ADC1R_AD1TEC3 HRTIM_ADC1R_AD1TEC3_Msk /*!< ADC Trigger 1 on Timer E compare 3 */
9319 #define HRTIM_ADC1R_AD1TEC4_Pos (30U)
9320 #define HRTIM_ADC1R_AD1TEC4_Msk (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos) /*!< 0x40000000 */
9321 #define HRTIM_ADC1R_AD1TEC4 HRTIM_ADC1R_AD1TEC4_Msk /*!< ADC Trigger 1 on Timer E compare 4 */
9322 #define HRTIM_ADC1R_AD1TEPER_Pos (31U)
9323 #define HRTIM_ADC1R_AD1TEPER_Msk (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos) /*!< 0x80000000 */
9324 #define HRTIM_ADC1R_AD1TEPER HRTIM_ADC1R_AD1TEPER_Msk /*!< ADC Trigger 1 on Timer E compare period */
9325
9326 /******************* Bit definition for HRTIM_ADC2R register ****************/
9327 #define HRTIM_ADC2R_AD2MC1_Pos (0U)
9328 #define HRTIM_ADC2R_AD2MC1_Msk (0x1UL << HRTIM_ADC2R_AD2MC1_Pos) /*!< 0x00000001 */
9329 #define HRTIM_ADC2R_AD2MC1 HRTIM_ADC2R_AD2MC1_Msk /*!< ADC Trigger 2 on master compare 1 */
9330 #define HRTIM_ADC2R_AD2MC2_Pos (1U)
9331 #define HRTIM_ADC2R_AD2MC2_Msk (0x1UL << HRTIM_ADC2R_AD2MC2_Pos) /*!< 0x00000002 */
9332 #define HRTIM_ADC2R_AD2MC2 HRTIM_ADC2R_AD2MC2_Msk /*!< ADC Trigger 2 on master compare 2 */
9333 #define HRTIM_ADC2R_AD2MC3_Pos (2U)
9334 #define HRTIM_ADC2R_AD2MC3_Msk (0x1UL << HRTIM_ADC2R_AD2MC3_Pos) /*!< 0x00000004 */
9335 #define HRTIM_ADC2R_AD2MC3 HRTIM_ADC2R_AD2MC3_Msk /*!< ADC Trigger 2 on master compare 3 */
9336 #define HRTIM_ADC2R_AD2MC4_Pos (3U)
9337 #define HRTIM_ADC2R_AD2MC4_Msk (0x1UL << HRTIM_ADC2R_AD2MC4_Pos) /*!< 0x00000008 */
9338 #define HRTIM_ADC2R_AD2MC4 HRTIM_ADC2R_AD2MC4_Msk /*!< ADC Trigger 2 on master compare 4 */
9339 #define HRTIM_ADC2R_AD2MPER_Pos (4U)
9340 #define HRTIM_ADC2R_AD2MPER_Msk (0x1UL << HRTIM_ADC2R_AD2MPER_Pos) /*!< 0x00000010 */
9341 #define HRTIM_ADC2R_AD2MPER HRTIM_ADC2R_AD2MPER_Msk /*!< ADC Trigger 2 on master period */
9342 #define HRTIM_ADC2R_AD2EEV6_Pos (5U)
9343 #define HRTIM_ADC2R_AD2EEV6_Msk (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos) /*!< 0x00000020 */
9344 #define HRTIM_ADC2R_AD2EEV6 HRTIM_ADC2R_AD2EEV6_Msk /*!< ADC Trigger 2 on external event 6 */
9345 #define HRTIM_ADC2R_AD2EEV7_Pos (6U)
9346 #define HRTIM_ADC2R_AD2EEV7_Msk (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos) /*!< 0x00000040 */
9347 #define HRTIM_ADC2R_AD2EEV7 HRTIM_ADC2R_AD2EEV7_Msk /*!< ADC Trigger 2 on external event 7 */
9348 #define HRTIM_ADC2R_AD2EEV8_Pos (7U)
9349 #define HRTIM_ADC2R_AD2EEV8_Msk (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos) /*!< 0x00000080 */
9350 #define HRTIM_ADC2R_AD2EEV8 HRTIM_ADC2R_AD2EEV8_Msk /*!< ADC Trigger 2 on external event 8 */
9351 #define HRTIM_ADC2R_AD2EEV9_Pos (8U)
9352 #define HRTIM_ADC2R_AD2EEV9_Msk (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos) /*!< 0x00000100 */
9353 #define HRTIM_ADC2R_AD2EEV9 HRTIM_ADC2R_AD2EEV9_Msk /*!< ADC Trigger 2 on external event 9 */
9354 #define HRTIM_ADC2R_AD2EEV10_Pos (9U)
9355 #define HRTIM_ADC2R_AD2EEV10_Msk (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos) /*!< 0x00000200 */
9356 #define HRTIM_ADC2R_AD2EEV10 HRTIM_ADC2R_AD2EEV10_Msk /*!< ADC Trigger 2 on external event 10 */
9357 #define HRTIM_ADC2R_AD2TAC2_Pos (10U)
9358 #define HRTIM_ADC2R_AD2TAC2_Msk (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos) /*!< 0x00000400 */
9359 #define HRTIM_ADC2R_AD2TAC2 HRTIM_ADC2R_AD2TAC2_Msk /*!< ADC Trigger 2 on Timer A compare 2 */
9360
9361 #define HRTIM_ADC2R_AD2TFC2_Pos (11U)
9362 #define HRTIM_ADC2R_AD2TFC2_Msk (0x1UL << HRTIM_ADC2R_AD2TFC2_Pos) /*!< 0x00000800 */
9363 #define HRTIM_ADC2R_AD2TFC2 HRTIM_ADC2R_AD2TFC2_Msk /*!< ADC Trigger 2 on Timer F compare 2 */
9364
9365 #define HRTIM_ADC2R_AD2TAC4_Pos (12U)
9366 #define HRTIM_ADC2R_AD2TAC4_Msk (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos) /*!< 0x00001000 */
9367 #define HRTIM_ADC2R_AD2TAC4 HRTIM_ADC2R_AD2TAC4_Msk /*!< ADC Trigger 2 on Timer A compare 4*/
9368 #define HRTIM_ADC2R_AD2TAPER_Pos (13U)
9369 #define HRTIM_ADC2R_AD2TAPER_Msk (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos) /*!< 0x00002000 */
9370 #define HRTIM_ADC2R_AD2TAPER HRTIM_ADC2R_AD2TAPER_Msk /*!< ADC Trigger 2 on Timer A period */
9371 #define HRTIM_ADC2R_AD2TBC2_Pos (14U)
9372 #define HRTIM_ADC2R_AD2TBC2_Msk (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos) /*!< 0x00004000 */
9373 #define HRTIM_ADC2R_AD2TBC2 HRTIM_ADC2R_AD2TBC2_Msk /*!< ADC Trigger 2 on Timer B compare 2 */
9374
9375 #define HRTIM_ADC2R_AD2TFC3_Pos (15U)
9376 #define HRTIM_ADC2R_AD2TFC3_Msk (0x1UL << HRTIM_ADC2R_AD2TFC3_Pos) /*!< 0x00008000 */
9377 #define HRTIM_ADC2R_AD2TFC3 HRTIM_ADC2R_AD2TFC3_Msk /*!< ADC Trigger 2 on Timer F compare 3 */
9378
9379 #define HRTIM_ADC2R_AD2TBC4_Pos (16U)
9380 #define HRTIM_ADC2R_AD2TBC4_Msk (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos) /*!< 0x00010000 */
9381 #define HRTIM_ADC2R_AD2TBC4 HRTIM_ADC2R_AD2TBC4_Msk /*!< ADC Trigger 2 on Timer B compare 4 */
9382 #define HRTIM_ADC2R_AD2TBPER_Pos (17U)
9383 #define HRTIM_ADC2R_AD2TBPER_Msk (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos) /*!< 0x00020000 */
9384 #define HRTIM_ADC2R_AD2TBPER HRTIM_ADC2R_AD2TBPER_Msk /*!< ADC Trigger 2 on Timer B period */
9385 #define HRTIM_ADC2R_AD2TCC2_Pos (18U)
9386 #define HRTIM_ADC2R_AD2TCC2_Msk (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos) /*!< 0x00040000 */
9387 #define HRTIM_ADC2R_AD2TCC2 HRTIM_ADC2R_AD2TCC2_Msk /*!< ADC Trigger 2 on Timer C compare 2 */
9388
9389 #define HRTIM_ADC2R_AD2TFC4_Pos (19U)
9390 #define HRTIM_ADC2R_AD2TFC4_Msk (0x1UL << HRTIM_ADC2R_AD2TFC4_Pos) /*!< 0x00080000 */
9391 #define HRTIM_ADC2R_AD2TFC4 HRTIM_ADC2R_AD2TFC4_Msk /*!< ADC Trigger 2 on Timer F compare 4 */
9392
9393 #define HRTIM_ADC2R_AD2TCC4_Pos (20U)
9394 #define HRTIM_ADC2R_AD2TCC4_Msk (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos) /*!< 0x00100000 */
9395 #define HRTIM_ADC2R_AD2TCC4 HRTIM_ADC2R_AD2TCC4_Msk /*!< ADC Trigger 2 on Timer C compare 4 */
9396 #define HRTIM_ADC2R_AD2TCPER_Pos (21U)
9397 #define HRTIM_ADC2R_AD2TCPER_Msk (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos) /*!< 0x00200000 */
9398 #define HRTIM_ADC2R_AD2TCPER HRTIM_ADC2R_AD2TCPER_Msk /*!< ADC Trigger 2 on Timer C period */
9399 #define HRTIM_ADC2R_AD2TCRST_Pos (22U)
9400 #define HRTIM_ADC2R_AD2TCRST_Msk (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos) /*!< 0x00400000 */
9401 #define HRTIM_ADC2R_AD2TCRST HRTIM_ADC2R_AD2TCRST_Msk /*!< ADC Trigger 2 on Timer C reset */
9402 #define HRTIM_ADC2R_AD2TDC2_Pos (23U)
9403 #define HRTIM_ADC2R_AD2TDC2_Msk (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos) /*!< 0x00800000 */
9404 #define HRTIM_ADC2R_AD2TDC2 HRTIM_ADC2R_AD2TDC2_Msk /*!< ADC Trigger 2 on Timer D compare 2 */
9405
9406 #define HRTIM_ADC2R_AD2TFPER_Pos (24U)
9407 #define HRTIM_ADC2R_AD2TFPER_Msk (0x1UL << HRTIM_ADC2R_AD2TFPER_Pos) /*!< 0x01000000 */
9408 #define HRTIM_ADC2R_AD2TFPER HRTIM_ADC2R_AD2TFPER_Msk /*!< ADC Trigger 2 on Timer F period */
9409
9410 #define HRTIM_ADC2R_AD2TDC4_Pos (25U)
9411 #define HRTIM_ADC2R_AD2TDC4_Msk (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos) /*!< 0x02000000 */
9412 #define HRTIM_ADC2R_AD2TDC4 HRTIM_ADC2R_AD2TDC4_Msk /*!< ADC Trigger 2 on Timer D compare 4*/
9413 #define HRTIM_ADC2R_AD2TDPER_Pos (26U)
9414 #define HRTIM_ADC2R_AD2TDPER_Msk (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos) /*!< 0x04000000 */
9415 #define HRTIM_ADC2R_AD2TDPER HRTIM_ADC2R_AD2TDPER_Msk /*!< ADC Trigger 2 on Timer D period */
9416 #define HRTIM_ADC2R_AD2TDRST_Pos (27U)
9417 #define HRTIM_ADC2R_AD2TDRST_Msk (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos) /*!< 0x08000000 */
9418 #define HRTIM_ADC2R_AD2TDRST HRTIM_ADC2R_AD2TDRST_Msk /*!< ADC Trigger 2 on Timer D reset */
9419 #define HRTIM_ADC2R_AD2TEC2_Pos (28U)
9420 #define HRTIM_ADC2R_AD2TEC2_Msk (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos) /*!< 0x10000000 */
9421 #define HRTIM_ADC2R_AD2TEC2 HRTIM_ADC2R_AD2TEC2_Msk /*!< ADC Trigger 2 on Timer E compare 2 */
9422 #define HRTIM_ADC2R_AD2TEC3_Pos (29U)
9423 #define HRTIM_ADC2R_AD2TEC3_Msk (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos) /*!< 0x20000000 */
9424 #define HRTIM_ADC2R_AD2TEC3 HRTIM_ADC2R_AD2TEC3_Msk /*!< ADC Trigger 2 on Timer E compare 3 */
9425 #define HRTIM_ADC2R_AD2TEC4_Pos (30U)
9426 #define HRTIM_ADC2R_AD2TEC4_Msk (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos) /*!< 0x40000000 */
9427 #define HRTIM_ADC2R_AD2TEC4 HRTIM_ADC2R_AD2TEC4_Msk /*!< ADC Trigger 2 on Timer E compare 4 */
9428 #define HRTIM_ADC2R_AD2TERST_Pos (31U)
9429 #define HRTIM_ADC2R_AD2TERST_Msk (0x1UL << HRTIM_ADC2R_AD2TERST_Pos) /*!< 0x80000000 */
9430 #define HRTIM_ADC2R_AD2TERST HRTIM_ADC2R_AD2TERST_Msk /*!< ADC Trigger 2 on Timer E reset */
9431
9432 /******************* Bit definition for HRTIM_ADC3R register ****************/
9433 #define HRTIM_ADC3R_AD3MC1_Pos (0U)
9434 #define HRTIM_ADC3R_AD3MC1_Msk (0x1UL << HRTIM_ADC3R_AD3MC1_Pos) /*!< 0x00000001 */
9435 #define HRTIM_ADC3R_AD3MC1 HRTIM_ADC3R_AD3MC1_Msk /*!< ADC Trigger 3 on master compare 1 */
9436 #define HRTIM_ADC3R_AD3MC2_Pos (1U)
9437 #define HRTIM_ADC3R_AD3MC2_Msk (0x1UL << HRTIM_ADC3R_AD3MC2_Pos) /*!< 0x00000002 */
9438 #define HRTIM_ADC3R_AD3MC2 HRTIM_ADC3R_AD3MC2_Msk /*!< ADC Trigger 3 on master compare 2 */
9439 #define HRTIM_ADC3R_AD3MC3_Pos (2U)
9440 #define HRTIM_ADC3R_AD3MC3_Msk (0x1UL << HRTIM_ADC3R_AD3MC3_Pos) /*!< 0x00000004 */
9441 #define HRTIM_ADC3R_AD3MC3 HRTIM_ADC3R_AD3MC3_Msk /*!< ADC Trigger 3 on master compare 3 */
9442 #define HRTIM_ADC3R_AD3MC4_Pos (3U)
9443 #define HRTIM_ADC3R_AD3MC4_Msk (0x1UL << HRTIM_ADC3R_AD3MC4_Pos) /*!< 0x00000008 */
9444 #define HRTIM_ADC3R_AD3MC4 HRTIM_ADC3R_AD3MC4_Msk /*!< ADC Trigger 3 on master compare 4 */
9445 #define HRTIM_ADC3R_AD3MPER_Pos (4U)
9446 #define HRTIM_ADC3R_AD3MPER_Msk (0x1UL << HRTIM_ADC3R_AD3MPER_Pos) /*!< 0x00000010 */
9447 #define HRTIM_ADC3R_AD3MPER HRTIM_ADC3R_AD3MPER_Msk /*!< ADC Trigger 3 on master period */
9448 #define HRTIM_ADC3R_AD3EEV1_Pos (5U)
9449 #define HRTIM_ADC3R_AD3EEV1_Msk (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos) /*!< 0x00000020 */
9450 #define HRTIM_ADC3R_AD3EEV1 HRTIM_ADC3R_AD3EEV1_Msk /*!< ADC Trigger 3 on external event 1 */
9451 #define HRTIM_ADC3R_AD3EEV2_Pos (6U)
9452 #define HRTIM_ADC3R_AD3EEV2_Msk (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos) /*!< 0x00000040 */
9453 #define HRTIM_ADC3R_AD3EEV2 HRTIM_ADC3R_AD3EEV2_Msk /*!< ADC Trigger 3 on external event 2 */
9454 #define HRTIM_ADC3R_AD3EEV3_Pos (7U)
9455 #define HRTIM_ADC3R_AD3EEV3_Msk (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos) /*!< 0x00000080 */
9456 #define HRTIM_ADC3R_AD3EEV3 HRTIM_ADC3R_AD3EEV3_Msk /*!< ADC Trigger 3 on external event 3 */
9457 #define HRTIM_ADC3R_AD3EEV4_Pos (8U)
9458 #define HRTIM_ADC3R_AD3EEV4_Msk (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos) /*!< 0x00000100 */
9459 #define HRTIM_ADC3R_AD3EEV4 HRTIM_ADC3R_AD3EEV4_Msk /*!< ADC Trigger 3 on external event 4 */
9460 #define HRTIM_ADC3R_AD3EEV5_Pos (9U)
9461 #define HRTIM_ADC3R_AD3EEV5_Msk (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos) /*!< 0x00000200 */
9462 #define HRTIM_ADC3R_AD3EEV5 HRTIM_ADC3R_AD3EEV5_Msk /*!< ADC Trigger 3 on external event 5 */
9463
9464 #define HRTIM_ADC3R_AD3TFC2_Pos (10U)
9465 #define HRTIM_ADC3R_AD3TFC2_Msk (0x1UL << HRTIM_ADC3R_AD3TFC2_Pos) /*!< 0x00000400 */
9466 #define HRTIM_ADC3R_AD3TFC2 HRTIM_ADC3R_AD3TFC2_Msk /*!< ADC Trigger 3 on Timer F compare 2 */
9467
9468 #define HRTIM_ADC3R_AD3TAC3_Pos (11U)
9469 #define HRTIM_ADC3R_AD3TAC3_Msk (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos) /*!< 0x00000800 */
9470 #define HRTIM_ADC3R_AD3TAC3 HRTIM_ADC3R_AD3TAC3_Msk /*!< ADC Trigger 3 on Timer A compare 3 */
9471 #define HRTIM_ADC3R_AD3TAC4_Pos (12U)
9472 #define HRTIM_ADC3R_AD3TAC4_Msk (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos) /*!< 0x00001000 */
9473 #define HRTIM_ADC3R_AD3TAC4 HRTIM_ADC3R_AD3TAC4_Msk /*!< ADC Trigger 3 on Timer A compare 4 */
9474 #define HRTIM_ADC3R_AD3TAPER_Pos (13U)
9475 #define HRTIM_ADC3R_AD3TAPER_Msk (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos) /*!< 0x00002000 */
9476 #define HRTIM_ADC3R_AD3TAPER HRTIM_ADC3R_AD3TAPER_Msk /*!< ADC Trigger 3 on Timer A period */
9477 #define HRTIM_ADC3R_AD3TARST_Pos (14U)
9478 #define HRTIM_ADC3R_AD3TARST_Msk (0x1UL << HRTIM_ADC3R_AD3TARST_Pos) /*!< 0x00004000 */
9479 #define HRTIM_ADC3R_AD3TARST HRTIM_ADC3R_AD3TARST_Msk /*!< ADC Trigger 3 on Timer A reset */
9480
9481 #define HRTIM_ADC3R_AD3TFC3_Pos (15U)
9482 #define HRTIM_ADC3R_AD3TFC3_Msk (0x1UL << HRTIM_ADC3R_AD3TFC3_Pos) /*!< 0x00008000 */
9483 #define HRTIM_ADC3R_AD3TFC3 HRTIM_ADC3R_AD3TFC3_Msk /*!< ADC Trigger 3 on Timer F compare 3 */
9484
9485 #define HRTIM_ADC3R_AD3TBC3_Pos (16U)
9486 #define HRTIM_ADC3R_AD3TBC3_Msk (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos) /*!< 0x00010000 */
9487 #define HRTIM_ADC3R_AD3TBC3 HRTIM_ADC3R_AD3TBC3_Msk /*!< ADC Trigger 3 on Timer B compare 3 */
9488 #define HRTIM_ADC3R_AD3TBC4_Pos (17U)
9489 #define HRTIM_ADC3R_AD3TBC4_Msk (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos) /*!< 0x00020000 */
9490 #define HRTIM_ADC3R_AD3TBC4 HRTIM_ADC3R_AD3TBC4_Msk /*!< ADC Trigger 3 on Timer B compare 4 */
9491 #define HRTIM_ADC3R_AD3TBPER_Pos (18U)
9492 #define HRTIM_ADC3R_AD3TBPER_Msk (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos) /*!< 0x00040000 */
9493 #define HRTIM_ADC3R_AD3TBPER HRTIM_ADC3R_AD3TBPER_Msk /*!< ADC Trigger 3 on Timer B period */
9494 #define HRTIM_ADC3R_AD3TBRST_Pos (19U)
9495 #define HRTIM_ADC3R_AD3TBRST_Msk (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos) /*!< 0x00080000 */
9496 #define HRTIM_ADC3R_AD3TBRST HRTIM_ADC3R_AD3TBRST_Msk /*!< ADC Trigger 3 on Timer B reset */
9497
9498 #define HRTIM_ADC3R_AD3TFC4_Pos (20U)
9499 #define HRTIM_ADC3R_AD3TFC4_Msk (0x1UL << HRTIM_ADC3R_AD3TFC4_Pos) /*!< 0x00100000 */
9500 #define HRTIM_ADC3R_AD3TFC4 HRTIM_ADC3R_AD3TFC4_Msk /*!< ADC Trigger 3 on Timer F compare 4 */
9501
9502 #define HRTIM_ADC3R_AD3TCC3_Pos (21U)
9503 #define HRTIM_ADC3R_AD3TCC3_Msk (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos) /*!< 0x00200000 */
9504 #define HRTIM_ADC3R_AD3TCC3 HRTIM_ADC3R_AD3TCC3_Msk /*!< ADC Trigger 3 on Timer C compare 3 */
9505 #define HRTIM_ADC3R_AD3TCC4_Pos (22U)
9506 #define HRTIM_ADC3R_AD3TCC4_Msk (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos) /*!< 0x00400000 */
9507 #define HRTIM_ADC3R_AD3TCC4 HRTIM_ADC3R_AD3TCC4_Msk /*!< ADC Trigger 3 on Timer C compare 4 */
9508 #define HRTIM_ADC3R_AD3TCPER_Pos (23U)
9509 #define HRTIM_ADC3R_AD3TCPER_Msk (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos) /*!< 0x00800000 */
9510 #define HRTIM_ADC3R_AD3TCPER HRTIM_ADC3R_AD3TCPER_Msk /*!< ADC Trigger 3 on Timer C period */
9511
9512 #define HRTIM_ADC3R_AD3TFPER_Pos (24U)
9513 #define HRTIM_ADC3R_AD3TFPER_Msk (0x1UL << HRTIM_ADC3R_AD3TFPER_Pos) /*!< 0x01000000 */
9514 #define HRTIM_ADC3R_AD3TFPER HRTIM_ADC3R_AD3TFPER_Msk /*!< ADC Trigger 3 on Timer F period */
9515
9516 #define HRTIM_ADC3R_AD3TDC3_Pos (25U)
9517 #define HRTIM_ADC3R_AD3TDC3_Msk (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos) /*!< 0x02000000 */
9518 #define HRTIM_ADC3R_AD3TDC3 HRTIM_ADC3R_AD3TDC3_Msk /*!< ADC Trigger 3 on Timer D compare 3 */
9519 #define HRTIM_ADC3R_AD3TDC4_Pos (26U)
9520 #define HRTIM_ADC3R_AD3TDC4_Msk (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos) /*!< 0x04000000 */
9521 #define HRTIM_ADC3R_AD3TDC4 HRTIM_ADC3R_AD3TDC4_Msk /*!< ADC Trigger 3 on Timer D compare 4 */
9522 #define HRTIM_ADC3R_AD3TDPER_Pos (27U)
9523 #define HRTIM_ADC3R_AD3TDPER_Msk (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos) /*!< 0x08000000 */
9524 #define HRTIM_ADC3R_AD3TDPER HRTIM_ADC3R_AD3TDPER_Msk /*!< ADC Trigger 3 on Timer D period */
9525
9526 #define HRTIM_ADC3R_AD3TFRST_Pos (28U)
9527 #define HRTIM_ADC3R_AD3TFRST_Msk (0x1UL << HRTIM_ADC3R_AD3TFRST_Pos) /*!< 0x10000000 */
9528 #define HRTIM_ADC3R_AD3TFRST HRTIM_ADC3R_AD3TFRST_Msk /*!< ADC Trigger 3 on Timer F reset */
9529
9530 #define HRTIM_ADC3R_AD3TEC3_Pos (29U)
9531 #define HRTIM_ADC3R_AD3TEC3_Msk (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos) /*!< 0x20000000 */
9532 #define HRTIM_ADC3R_AD3TEC3 HRTIM_ADC3R_AD3TEC3_Msk /*!< ADC Trigger 3 on Timer E compare 3 */
9533 #define HRTIM_ADC3R_AD3TEC4_Pos (30U)
9534 #define HRTIM_ADC3R_AD3TEC4_Msk (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos) /*!< 0x40000000 */
9535 #define HRTIM_ADC3R_AD3TEC4 HRTIM_ADC3R_AD3TEC4_Msk /*!< ADC Trigger 3 on Timer E compare 4 */
9536 #define HRTIM_ADC3R_AD3TEPER_Pos (31U)
9537 #define HRTIM_ADC3R_AD3TEPER_Msk (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos) /*!< 0x80000000 */
9538 #define HRTIM_ADC3R_AD3TEPER HRTIM_ADC3R_AD3TEPER_Msk /*!< ADC Trigger 3 on Timer E period */
9539
9540 /******************* Bit definition for HRTIM_ADC4R register ****************/
9541 #define HRTIM_ADC4R_AD4MC1_Pos (0U)
9542 #define HRTIM_ADC4R_AD4MC1_Msk (0x1UL << HRTIM_ADC4R_AD4MC1_Pos) /*!< 0x00000001 */
9543 #define HRTIM_ADC4R_AD4MC1 HRTIM_ADC4R_AD4MC1_Msk /*!< ADC Trigger 4 on master compare 1 */
9544 #define HRTIM_ADC4R_AD4MC2_Pos (1U)
9545 #define HRTIM_ADC4R_AD4MC2_Msk (0x1UL << HRTIM_ADC4R_AD4MC2_Pos) /*!< 0x00000002 */
9546 #define HRTIM_ADC4R_AD4MC2 HRTIM_ADC4R_AD4MC2_Msk /*!< ADC Trigger 4 on master compare 2 */
9547 #define HRTIM_ADC4R_AD4MC3_Pos (2U)
9548 #define HRTIM_ADC4R_AD4MC3_Msk (0x1UL << HRTIM_ADC4R_AD4MC3_Pos) /*!< 0x00000004 */
9549 #define HRTIM_ADC4R_AD4MC3 HRTIM_ADC4R_AD4MC3_Msk /*!< ADC Trigger 4 on master compare 3 */
9550 #define HRTIM_ADC4R_AD4MC4_Pos (3U)
9551 #define HRTIM_ADC4R_AD4MC4_Msk (0x1UL << HRTIM_ADC4R_AD4MC4_Pos) /*!< 0x00000008 */
9552 #define HRTIM_ADC4R_AD4MC4 HRTIM_ADC4R_AD4MC4_Msk /*!< ADC Trigger 4 on master compare 4 */
9553 #define HRTIM_ADC4R_AD4MPER_Pos (4U)
9554 #define HRTIM_ADC4R_AD4MPER_Msk (0x1UL << HRTIM_ADC4R_AD4MPER_Pos) /*!< 0x00000010 */
9555 #define HRTIM_ADC4R_AD4MPER HRTIM_ADC4R_AD4MPER_Msk /*!< ADC Trigger 4 on master period */
9556 #define HRTIM_ADC4R_AD4EEV6_Pos (5U)
9557 #define HRTIM_ADC4R_AD4EEV6_Msk (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos) /*!< 0x00000020 */
9558 #define HRTIM_ADC4R_AD4EEV6 HRTIM_ADC4R_AD4EEV6_Msk /*!< ADC Trigger 4 on external event 6 */
9559 #define HRTIM_ADC4R_AD4EEV7_Pos (6U)
9560 #define HRTIM_ADC4R_AD4EEV7_Msk (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos) /*!< 0x00000040 */
9561 #define HRTIM_ADC4R_AD4EEV7 HRTIM_ADC4R_AD4EEV7_Msk /*!< ADC Trigger 4 on external event 7 */
9562 #define HRTIM_ADC4R_AD4EEV8_Pos (7U)
9563 #define HRTIM_ADC4R_AD4EEV8_Msk (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos) /*!< 0x00000080 */
9564 #define HRTIM_ADC4R_AD4EEV8 HRTIM_ADC4R_AD4EEV8_Msk /*!< ADC Trigger 4 on external event 8 */
9565 #define HRTIM_ADC4R_AD4EEV9_Pos (8U)
9566 #define HRTIM_ADC4R_AD4EEV9_Msk (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos) /*!< 0x00000100 */
9567 #define HRTIM_ADC4R_AD4EEV9 HRTIM_ADC4R_AD4EEV9_Msk /*!< ADC Trigger 4 on external event 9 */
9568 #define HRTIM_ADC4R_AD4EEV10_Pos (9U)
9569 #define HRTIM_ADC4R_AD4EEV10_Msk (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos) /*!< 0x00000200 */
9570 #define HRTIM_ADC4R_AD4EEV10 HRTIM_ADC4R_AD4EEV10_Msk /*!< ADC Trigger 4 on external event 10 */
9571 #define HRTIM_ADC4R_AD4TAC2_Pos (10U)
9572 #define HRTIM_ADC4R_AD4TAC2_Msk (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos) /*!< 0x00000400 */
9573 #define HRTIM_ADC4R_AD4TAC2 HRTIM_ADC4R_AD4TAC2_Msk /*!< ADC Trigger 4 on Timer A compare 2 */
9574
9575 #define HRTIM_ADC4R_AD4TFC2_Pos (11U)
9576 #define HRTIM_ADC4R_AD4TFC2_Msk (0x1UL << HRTIM_ADC4R_AD4TFC2_Pos) /*!< 0x00000800 */
9577 #define HRTIM_ADC4R_AD4TFC2 HRTIM_ADC4R_AD4TFC2_Msk /*!< ADC Trigger 4 on Timer F compare 2 */
9578
9579 #define HRTIM_ADC4R_AD4TAC4_Pos (12U)
9580 #define HRTIM_ADC4R_AD4TAC4_Msk (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos) /*!< 0x00001000 */
9581 #define HRTIM_ADC4R_AD4TAC4 HRTIM_ADC4R_AD4TAC4_Msk /*!< ADC Trigger 4 on Timer A compare 4*/
9582 #define HRTIM_ADC4R_AD4TAPER_Pos (13U)
9583 #define HRTIM_ADC4R_AD4TAPER_Msk (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos) /*!< 0x00002000 */
9584 #define HRTIM_ADC4R_AD4TAPER HRTIM_ADC4R_AD4TAPER_Msk /*!< ADC Trigger 4 on Timer A period */
9585 #define HRTIM_ADC4R_AD4TBC2_Pos (14U)
9586 #define HRTIM_ADC4R_AD4TBC2_Msk (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos) /*!< 0x00004000 */
9587 #define HRTIM_ADC4R_AD4TBC2 HRTIM_ADC4R_AD4TBC2_Msk /*!< ADC Trigger 4 on Timer B compare 2 */
9588
9589 #define HRTIM_ADC4R_AD4TFC3_Pos (15U)
9590 #define HRTIM_ADC4R_AD4TFC3_Msk (0x1UL << HRTIM_ADC4R_AD4TFC3_Pos) /*!< 0x00008000 */
9591 #define HRTIM_ADC4R_AD4TFC3 HRTIM_ADC4R_AD4TFC3_Msk /*!< ADC Trigger 4 on Timer F compare 3 */
9592
9593 #define HRTIM_ADC4R_AD4TBC4_Pos (16U)
9594 #define HRTIM_ADC4R_AD4TBC4_Msk (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos) /*!< 0x00010000 */
9595 #define HRTIM_ADC4R_AD4TBC4 HRTIM_ADC4R_AD4TBC4_Msk /*!< ADC Trigger 4 on Timer B compare 4 */
9596 #define HRTIM_ADC4R_AD4TBPER_Pos (17U)
9597 #define HRTIM_ADC4R_AD4TBPER_Msk (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos) /*!< 0x00020000 */
9598 #define HRTIM_ADC4R_AD4TBPER HRTIM_ADC4R_AD4TBPER_Msk /*!< ADC Trigger 4 on Timer B period */
9599 #define HRTIM_ADC4R_AD4TCC2_Pos (18U)
9600 #define HRTIM_ADC4R_AD4TCC2_Msk (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos) /*!< 0x00040000 */
9601 #define HRTIM_ADC4R_AD4TCC2 HRTIM_ADC4R_AD4TCC2_Msk /*!< ADC Trigger 4 on Timer C compare 2 */
9602
9603 #define HRTIM_ADC4R_AD4TFC4_Pos (19U)
9604 #define HRTIM_ADC4R_AD4TFC4_Msk (0x1UL << HRTIM_ADC4R_AD4TFC4_Pos) /*!< 0x00080000 */
9605 #define HRTIM_ADC4R_AD4TFC4 HRTIM_ADC4R_AD4TFC4_Msk /*!< ADC Trigger 4 on Timer F compare 4 */
9606
9607 #define HRTIM_ADC4R_AD4TCC4_Pos (20U)
9608 #define HRTIM_ADC4R_AD4TCC4_Msk (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos) /*!< 0x00100000 */
9609 #define HRTIM_ADC4R_AD4TCC4 HRTIM_ADC4R_AD4TCC4_Msk /*!< ADC Trigger 4 on Timer C compare 4 */
9610 #define HRTIM_ADC4R_AD4TCPER_Pos (21U)
9611 #define HRTIM_ADC4R_AD4TCPER_Msk (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos) /*!< 0x00200000 */
9612 #define HRTIM_ADC4R_AD4TCPER HRTIM_ADC4R_AD4TCPER_Msk /*!< ADC Trigger 4 on Timer C period */
9613 #define HRTIM_ADC4R_AD4TCRST_Pos (22U)
9614 #define HRTIM_ADC4R_AD4TCRST_Msk (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos) /*!< 0x00400000 */
9615 #define HRTIM_ADC4R_AD4TCRST HRTIM_ADC4R_AD4TCRST_Msk /*!< ADC Trigger 4 on Timer C reset */
9616 #define HRTIM_ADC4R_AD4TDC2_Pos (23U)
9617 #define HRTIM_ADC4R_AD4TDC2_Msk (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos) /*!< 0x00800000 */
9618 #define HRTIM_ADC4R_AD4TDC2 HRTIM_ADC4R_AD4TDC2_Msk /*!< ADC Trigger 4 on Timer D compare 2 */
9619
9620 #define HRTIM_ADC4R_AD4TFPER_Pos (24U)
9621 #define HRTIM_ADC4R_AD4TFPER_Msk (0x1UL << HRTIM_ADC4R_AD4TFPER_Pos) /*!< 0x01000000 */
9622 #define HRTIM_ADC4R_AD4TFPER HRTIM_ADC4R_AD4TFPER_Msk /*!< ADC Trigger 4 on Timer F period */
9623
9624 #define HRTIM_ADC4R_AD4TDC4_Pos (25U)
9625 #define HRTIM_ADC4R_AD4TDC4_Msk (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos) /*!< 0x02000000 */
9626 #define HRTIM_ADC4R_AD4TDC4 HRTIM_ADC4R_AD4TDC4_Msk /*!< ADC Trigger 4 on Timer D compare 4*/
9627 #define HRTIM_ADC4R_AD4TDPER_Pos (26U)
9628 #define HRTIM_ADC4R_AD4TDPER_Msk (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos) /*!< 0x04000000 */
9629 #define HRTIM_ADC4R_AD4TDPER HRTIM_ADC4R_AD4TDPER_Msk /*!< ADC Trigger 4 on Timer D period */
9630 #define HRTIM_ADC4R_AD4TDRST_Pos (27U)
9631 #define HRTIM_ADC4R_AD4TDRST_Msk (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos) /*!< 0x08000000 */
9632 #define HRTIM_ADC4R_AD4TDRST HRTIM_ADC4R_AD4TDRST_Msk /*!< ADC Trigger 4 on Timer D reset */
9633 #define HRTIM_ADC4R_AD4TEC2_Pos (28U)
9634 #define HRTIM_ADC4R_AD4TEC2_Msk (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos) /*!< 0x10000000 */
9635 #define HRTIM_ADC4R_AD4TEC2 HRTIM_ADC4R_AD4TEC2_Msk /*!< ADC Trigger 4 on Timer E compare 2 */
9636 #define HRTIM_ADC4R_AD4TEC3_Pos (29U)
9637 #define HRTIM_ADC4R_AD4TEC3_Msk (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos) /*!< 0x20000000 */
9638 #define HRTIM_ADC4R_AD4TEC3 HRTIM_ADC4R_AD4TEC3_Msk /*!< ADC Trigger 4 on Timer E compare 3 */
9639 #define HRTIM_ADC4R_AD4TEC4_Pos (30U)
9640 #define HRTIM_ADC4R_AD4TEC4_Msk (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos) /*!< 0x40000000 */
9641 #define HRTIM_ADC4R_AD4TEC4 HRTIM_ADC4R_AD4TEC4_Msk /*!< ADC Trigger 4 on Timer E compare 4 */
9642 #define HRTIM_ADC4R_AD4TERST_Pos (31U)
9643 #define HRTIM_ADC4R_AD4TERST_Msk (0x1UL << HRTIM_ADC4R_AD4TERST_Pos) /*!< 0x80000000 */
9644 #define HRTIM_ADC4R_AD4TERST HRTIM_ADC4R_AD4TERST_Msk /*!< ADC Trigger 4 on Timer E reset */
9645
9646 /******************* Bit definition for HRTIM_DLLCR register ****************/
9647 #define HRTIM_DLLCR_CAL_Pos (0U)
9648 #define HRTIM_DLLCR_CAL_Msk (0x1UL << HRTIM_DLLCR_CAL_Pos) /*!< 0x00000001 */
9649 #define HRTIM_DLLCR_CAL HRTIM_DLLCR_CAL_Msk /*!< DLL calibration start */
9650 #define HRTIM_DLLCR_CALEN_Pos (1U)
9651 #define HRTIM_DLLCR_CALEN_Msk (0x1UL << HRTIM_DLLCR_CALEN_Pos) /*!< 0x00000002 */
9652 #define HRTIM_DLLCR_CALEN HRTIM_DLLCR_CALEN_Msk /*!< DLL calibration enable */
9653 #define HRTIM_DLLCR_CALRTE_Pos (2U)
9654 #define HRTIM_DLLCR_CALRTE_Msk (0x3UL << HRTIM_DLLCR_CALRTE_Pos) /*!< 0x0000000C */
9655 #define HRTIM_DLLCR_CALRTE HRTIM_DLLCR_CALRTE_Msk /*!< DLL calibration rate */
9656 #define HRTIM_DLLCR_CALRTE_0 (0x1UL << HRTIM_DLLCR_CALRTE_Pos) /*!< 0x00000004 */
9657 #define HRTIM_DLLCR_CALRTE_1 (0x2UL << HRTIM_DLLCR_CALRTE_Pos) /*!< 0x00000008 */
9658
9659 /******************* Bit definition for HRTIM_FLTINR1 register ***************/
9660 #define HRTIM_FLTINR1_FLT1E_Pos (0U)
9661 #define HRTIM_FLTINR1_FLT1E_Msk (0x1UL << HRTIM_FLTINR1_FLT1E_Pos) /*!< 0x00000001 */
9662 #define HRTIM_FLTINR1_FLT1E HRTIM_FLTINR1_FLT1E_Msk /*!< Fault 1 enable */
9663 #define HRTIM_FLTINR1_FLT1P_Pos (1U)
9664 #define HRTIM_FLTINR1_FLT1P_Msk (0x1UL << HRTIM_FLTINR1_FLT1P_Pos) /*!< 0x00000002 */
9665 #define HRTIM_FLTINR1_FLT1P HRTIM_FLTINR1_FLT1P_Msk /*!< Fault 1 polarity */
9666 #define HRTIM_FLTINR1_FLT1SRC_0_Pos (2U)
9667 #define HRTIM_FLTINR1_FLT1SRC_0_Msk (0x1UL << HRTIM_FLTINR1_FLT1SRC_0_Pos) /*!< 0x00000004 */
9668 #define HRTIM_FLTINR1_FLT1SRC_0 HRTIM_FLTINR1_FLT1SRC_0_Msk /*!< Fault 1 source bit 0 */
9669 #define HRTIM_FLTINR1_FLT1F_Pos (3U)
9670 #define HRTIM_FLTINR1_FLT1F_Msk (0xFUL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000078 */
9671 #define HRTIM_FLTINR1_FLT1F HRTIM_FLTINR1_FLT1F_Msk /*!< Fault 1 filter */
9672 #define HRTIM_FLTINR1_FLT1F_0 (0x1UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000008 */
9673 #define HRTIM_FLTINR1_FLT1F_1 (0x2UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000010 */
9674 #define HRTIM_FLTINR1_FLT1F_2 (0x4UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000020 */
9675 #define HRTIM_FLTINR1_FLT1F_3 (0x8UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000040 */
9676 #define HRTIM_FLTINR1_FLT1LCK_Pos (7U)
9677 #define HRTIM_FLTINR1_FLT1LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos) /*!< 0x00000080 */
9678 #define HRTIM_FLTINR1_FLT1LCK HRTIM_FLTINR1_FLT1LCK_Msk /*!< Fault 1 lock */
9679 #define HRTIM_FLTINR1_FLT2E_Pos (8U)
9680 #define HRTIM_FLTINR1_FLT2E_Msk (0x1UL << HRTIM_FLTINR1_FLT2E_Pos) /*!< 0x00000100 */
9681 #define HRTIM_FLTINR1_FLT2E HRTIM_FLTINR1_FLT2E_Msk /*!< Fault 2 enable */
9682 #define HRTIM_FLTINR1_FLT2P_Pos (9U)
9683 #define HRTIM_FLTINR1_FLT2P_Msk (0x1UL << HRTIM_FLTINR1_FLT2P_Pos) /*!< 0x00000200 */
9684 #define HRTIM_FLTINR1_FLT2P HRTIM_FLTINR1_FLT2P_Msk /*!< Fault 2 polarity */
9685 #define HRTIM_FLTINR1_FLT2SRC_0_Pos (10U)
9686 #define HRTIM_FLTINR1_FLT2SRC_0_Msk (0x1UL << HRTIM_FLTINR1_FLT2SRC_0_Pos) /*!< 0x00000400 */
9687 #define HRTIM_FLTINR1_FLT2SRC_0 HRTIM_FLTINR1_FLT2SRC_0_Msk /*!< Fault 2 source bit 0 */
9688 #define HRTIM_FLTINR1_FLT2F_Pos (11U)
9689 #define HRTIM_FLTINR1_FLT2F_Msk (0xFUL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00007800 */
9690 #define HRTIM_FLTINR1_FLT2F HRTIM_FLTINR1_FLT2F_Msk /*!< Fault 2 filter */
9691 #define HRTIM_FLTINR1_FLT2F_0 (0x1UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00000800 */
9692 #define HRTIM_FLTINR1_FLT2F_1 (0x2UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00001000 */
9693 #define HRTIM_FLTINR1_FLT2F_2 (0x4UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00002000 */
9694 #define HRTIM_FLTINR1_FLT2F_3 (0x8UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00004000 */
9695 #define HRTIM_FLTINR1_FLT2LCK_Pos (15U)
9696 #define HRTIM_FLTINR1_FLT2LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos) /*!< 0x00008000 */
9697 #define HRTIM_FLTINR1_FLT2LCK HRTIM_FLTINR1_FLT2LCK_Msk /*!< Fault 2 lock */
9698 #define HRTIM_FLTINR1_FLT3E_Pos (16U)
9699 #define HRTIM_FLTINR1_FLT3E_Msk (0x1UL << HRTIM_FLTINR1_FLT3E_Pos) /*!< 0x00010000 */
9700 #define HRTIM_FLTINR1_FLT3E HRTIM_FLTINR1_FLT3E_Msk /*!< Fault 3 enable */
9701 #define HRTIM_FLTINR1_FLT3P_Pos (17U)
9702 #define HRTIM_FLTINR1_FLT3P_Msk (0x1UL << HRTIM_FLTINR1_FLT3P_Pos) /*!< 0x00020000 */
9703 #define HRTIM_FLTINR1_FLT3P HRTIM_FLTINR1_FLT3P_Msk /*!< Fault 3 polarity */
9704 #define HRTIM_FLTINR1_FLT3SRC_0_Pos (18U)
9705 #define HRTIM_FLTINR1_FLT3SRC_0_Msk (0x1UL << HRTIM_FLTINR1_FLT3SRC_0_Pos) /*!< 0x00040000 */
9706 #define HRTIM_FLTINR1_FLT3SRC_0 HRTIM_FLTINR1_FLT3SRC_0_Msk /*!< Fault 3 source bit 0 */
9707 #define HRTIM_FLTINR1_FLT3F_Pos (19U)
9708 #define HRTIM_FLTINR1_FLT3F_Msk (0xFUL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00780000 */
9709 #define HRTIM_FLTINR1_FLT3F HRTIM_FLTINR1_FLT3F_Msk /*!< Fault 3 filter */
9710 #define HRTIM_FLTINR1_FLT3F_0 (0x1UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00080000 */
9711 #define HRTIM_FLTINR1_FLT3F_1 (0x2UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00100000 */
9712 #define HRTIM_FLTINR1_FLT3F_2 (0x4UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00200000 */
9713 #define HRTIM_FLTINR1_FLT3F_3 (0x8UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00400000 */
9714 #define HRTIM_FLTINR1_FLT3LCK_Pos (23U)
9715 #define HRTIM_FLTINR1_FLT3LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos) /*!< 0x00800000 */
9716 #define HRTIM_FLTINR1_FLT3LCK HRTIM_FLTINR1_FLT3LCK_Msk /*!< Fault 3 lock */
9717 #define HRTIM_FLTINR1_FLT4E_Pos (24U)
9718 #define HRTIM_FLTINR1_FLT4E_Msk (0x1UL << HRTIM_FLTINR1_FLT4E_Pos) /*!< 0x01000000 */
9719 #define HRTIM_FLTINR1_FLT4E HRTIM_FLTINR1_FLT4E_Msk /*!< Fault 4 enable */
9720 #define HRTIM_FLTINR1_FLT4P_Pos (25U)
9721 #define HRTIM_FLTINR1_FLT4P_Msk (0x1UL << HRTIM_FLTINR1_FLT4P_Pos) /*!< 0x02000000 */
9722 #define HRTIM_FLTINR1_FLT4P HRTIM_FLTINR1_FLT4P_Msk /*!< Fault 4 polarity */
9723 #define HRTIM_FLTINR1_FLT4SRC_0_Pos (26U)
9724 #define HRTIM_FLTINR1_FLT4SRC_0_Msk (0x1UL << HRTIM_FLTINR1_FLT4SRC_0_Pos) /*!< 0x04000000 */
9725 #define HRTIM_FLTINR1_FLT4SRC_0 HRTIM_FLTINR1_FLT4SRC_0_Msk /*!< Fault 4 source bit 0 */
9726 #define HRTIM_FLTINR1_FLT4F_Pos (27U)
9727 #define HRTIM_FLTINR1_FLT4F_Msk (0xFUL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x78000000 */
9728 #define HRTIM_FLTINR1_FLT4F HRTIM_FLTINR1_FLT4F_Msk /*!< Fault 4 filter */
9729 #define HRTIM_FLTINR1_FLT4F_0 (0x1UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x08000000 */
9730 #define HRTIM_FLTINR1_FLT4F_1 (0x2UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x10000000 */
9731 #define HRTIM_FLTINR1_FLT4F_2 (0x4UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x20000000 */
9732 #define HRTIM_FLTINR1_FLT4F_3 (0x8UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x40000000 */
9733 #define HRTIM_FLTINR1_FLT4LCK_Pos (31U)
9734 #define HRTIM_FLTINR1_FLT4LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos) /*!< 0x80000000 */
9735 #define HRTIM_FLTINR1_FLT4LCK HRTIM_FLTINR1_FLT4LCK_Msk /*!< Fault 4 lock */
9736
9737 /******************* Bit definition for HRTIM_FLTINR2 register ***************/
9738 #define HRTIM_FLTINR2_FLT5E_Pos (0U)
9739 #define HRTIM_FLTINR2_FLT5E_Msk (0x1UL << HRTIM_FLTINR2_FLT5E_Pos) /*!< 0x00000001 */
9740 #define HRTIM_FLTINR2_FLT5E HRTIM_FLTINR2_FLT5E_Msk /*!< Fault 5 enable */
9741 #define HRTIM_FLTINR2_FLT5P_Pos (1U)
9742 #define HRTIM_FLTINR2_FLT5P_Msk (0x1UL << HRTIM_FLTINR2_FLT5P_Pos) /*!< 0x00000002 */
9743 #define HRTIM_FLTINR2_FLT5P HRTIM_FLTINR2_FLT5P_Msk /*!< Fault 5 polarity */
9744 #define HRTIM_FLTINR2_FLT5SRC_0_Pos (2U)
9745 #define HRTIM_FLTINR2_FLT5SRC_0_Msk (0x1UL << HRTIM_FLTINR2_FLT5SRC_0_Pos) /*!< 0x00000004 */
9746 #define HRTIM_FLTINR2_FLT5SRC_0 HRTIM_FLTINR2_FLT5SRC_0_Msk /*!< Fault 5 source bit 0 */
9747 #define HRTIM_FLTINR2_FLT5F_Pos (3U)
9748 #define HRTIM_FLTINR2_FLT5F_Msk (0xFUL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000078 */
9749 #define HRTIM_FLTINR2_FLT5F HRTIM_FLTINR2_FLT5F_Msk /*!< Fault 5 filter */
9750 #define HRTIM_FLTINR2_FLT5F_0 (0x1UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000008 */
9751 #define HRTIM_FLTINR2_FLT5F_1 (0x2UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000010 */
9752 #define HRTIM_FLTINR2_FLT5F_2 (0x4UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000020 */
9753 #define HRTIM_FLTINR2_FLT5F_3 (0x8UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000040 */
9754 #define HRTIM_FLTINR2_FLT5LCK_Pos (7U)
9755 #define HRTIM_FLTINR2_FLT5LCK_Msk (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos) /*!< 0x00000080 */
9756 #define HRTIM_FLTINR2_FLT5LCK HRTIM_FLTINR2_FLT5LCK_Msk /*!< Fault 5 lock */
9757 #define HRTIM_FLTINR2_FLT6E_Pos (8U)
9758 #define HRTIM_FLTINR2_FLT6E_Msk (0x1UL << HRTIM_FLTINR2_FLT6E_Pos) /*!< 0x00000100 */
9759 #define HRTIM_FLTINR2_FLT6E HRTIM_FLTINR2_FLT6E_Msk /*!< Fault 6 enable */
9760 #define HRTIM_FLTINR2_FLT6P_Pos (9U)
9761 #define HRTIM_FLTINR2_FLT6P_Msk (0x1UL << HRTIM_FLTINR2_FLT6P_Pos) /*!< 0x00000200 */
9762 #define HRTIM_FLTINR2_FLT6P HRTIM_FLTINR2_FLT6P_Msk /*!< Fault 6 polarity */
9763 #define HRTIM_FLTINR2_FLT6SRC_0_Pos (10U)
9764 #define HRTIM_FLTINR2_FLT6SRC_0_Msk (0x1UL << HRTIM_FLTINR2_FLT6SRC_0_Pos) /*!< 0x00000400 */
9765 #define HRTIM_FLTINR2_FLT6SRC_0 HRTIM_FLTINR2_FLT6SRC_0_Msk /*!< Fault 6 source bit 0 */
9766 #define HRTIM_FLTINR2_FLT6F_Pos (11U)
9767 #define HRTIM_FLTINR2_FLT6F_Msk (0xFUL << HRTIM_FLTINR2_FLT6F_Pos) /*!< 0x00007800 */
9768 #define HRTIM_FLTINR2_FLT6F HRTIM_FLTINR2_FLT6F_Msk /*!< Fault 6 filter */
9769 #define HRTIM_FLTINR2_FLT6F_0 (0x1UL << HRTIM_FLTINR2_FLT6F_Pos) /*!< 0x00000008 */
9770 #define HRTIM_FLTINR2_FLT6F_1 (0x2UL << HRTIM_FLTINR2_FLT6F_Pos) /*!< 0x00000010 */
9771 #define HRTIM_FLTINR2_FLT6F_2 (0x4UL << HRTIM_FLTINR2_FLT6F_Pos) /*!< 0x00000020 */
9772 #define HRTIM_FLTINR2_FLT6F_3 (0x8UL << HRTIM_FLTINR2_FLT6F_Pos) /*!< 0x00000040 */
9773 #define HRTIM_FLTINR2_FLT6LCK_Pos (15U)
9774 #define HRTIM_FLTINR2_FLT6LCK_Msk (0x1UL << HRTIM_FLTINR2_FLT6LCK_Pos) /*!< 0x00008000 */
9775 #define HRTIM_FLTINR2_FLT6LCK HRTIM_FLTINR2_FLT6LCK_Msk /*!< Fault 6 lock */
9776 #define HRTIM_FLTINR2_FLT1SRC_1_Pos (16U)
9777 #define HRTIM_FLTINR2_FLT1SRC_1_Msk (0x1UL << HRTIM_FLTINR2_FLT1SRC_1_Pos) /*!< 0x00010000 */
9778 #define HRTIM_FLTINR2_FLT1SRC_1 HRTIM_FLTINR2_FLT1SRC_1_Msk /*!< Fault 1 source bit 1 */
9779 #define HRTIM_FLTINR2_FLT2SRC_1_Pos (17U)
9780 #define HRTIM_FLTINR2_FLT2SRC_1_Msk (0x1UL << HRTIM_FLTINR2_FLT2SRC_1_Pos) /*!< 0x00020000 */
9781 #define HRTIM_FLTINR2_FLT2SRC_1 HRTIM_FLTINR2_FLT2SRC_1_Msk /*!< Fault 2 source bit1 */
9782 #define HRTIM_FLTINR2_FLT3SRC_1_Pos (18U)
9783 #define HRTIM_FLTINR2_FLT3SRC_1_Msk (0x1UL << HRTIM_FLTINR2_FLT3SRC_1_Pos) /*!< 0x00040000 */
9784 #define HRTIM_FLTINR2_FLT3SRC_1 HRTIM_FLTINR2_FLT3SRC_1_Msk /*!< Fault 3 source bit 1 */
9785 #define HRTIM_FLTINR2_FLT4SRC_1_Pos (19U)
9786 #define HRTIM_FLTINR2_FLT4SRC_1_Msk (0x1UL << HRTIM_FLTINR2_FLT4SRC_1_Pos) /*!< 0x00080000 */
9787 #define HRTIM_FLTINR2_FLT4SRC_1 HRTIM_FLTINR2_FLT4SRC_1_Msk /*!< Fault 4 source bit 1 */
9788 #define HRTIM_FLTINR2_FLT5SRC_1_Pos (20U)
9789 #define HRTIM_FLTINR2_FLT5SRC_1_Msk (0x1UL << HRTIM_FLTINR2_FLT5SRC_1_Pos) /*!< 0x00100000 */
9790 #define HRTIM_FLTINR2_FLT5SRC_1 HRTIM_FLTINR2_FLT5SRC_1_Msk /*!< Fault 5 source bit 1 */
9791 #define HRTIM_FLTINR2_FLT6SRC_1_Pos (21U)
9792 #define HRTIM_FLTINR2_FLT6SRC_1_Msk (0x1UL << HRTIM_FLTINR2_FLT6SRC_1_Pos) /*!< 0x00200000 */
9793 #define HRTIM_FLTINR2_FLT6SRC_1 HRTIM_FLTINR2_FLT6SRC_1_Msk /*!< Fault 6 source bit 1 */
9794 #define HRTIM_FLTINR2_FLTSD_Pos (24U)
9795 #define HRTIM_FLTINR2_FLTSD_Msk (0x3UL << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x03000000 */
9796 #define HRTIM_FLTINR2_FLTSD HRTIM_FLTINR2_FLTSD_Msk /*!< Fault sampling clock division */
9797 #define HRTIM_FLTINR2_FLTSD_0 (0x1UL << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x01000000 */
9798 #define HRTIM_FLTINR2_FLTSD_1 (0x2UL << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x02000000 */
9799
9800 /******************* Bit definition for HRTIM_FLTINR3 register ***************/
9801 #define HRTIM_FLTINR3_FLT1BLKE_Pos (0U)
9802 #define HRTIM_FLTINR3_FLT1BLKE_Msk (0x1UL << HRTIM_FLTINR3_FLT1BLKE_Pos) /*!< 0x00000001 */
9803 #define HRTIM_FLTINR3_FLT1BLKE HRTIM_FLTINR3_FLT1BLKE_Msk /*!< Fault 1 Blanking Enable */
9804 #define HRTIM_FLTINR3_FLT1BLKS_Pos (1U)
9805 #define HRTIM_FLTINR3_FLT1BLKS_Msk (0x1UL << HRTIM_FLTINR3_FLT1BLKS_Pos) /*!< 0x00000002 */
9806 #define HRTIM_FLTINR3_FLT1BLKS HRTIM_FLTINR3_FLT1BLKS_Msk /*!< Fault 1 Blanking Source */
9807 #define HRTIM_FLTINR3_FLT1CNT_Pos (2U)
9808 #define HRTIM_FLTINR3_FLT1CNT_Msk (0xFUL << HRTIM_FLTINR3_FLT1CNT_Pos) /*!< 0x0000003C */
9809 #define HRTIM_FLTINR3_FLT1CNT HRTIM_FLTINR3_FLT1CNT_Msk /*!< Fault 1 Counter */
9810 #define HRTIM_FLTINR3_FLT1CNT_0 (0x1UL << HRTIM_FLTINR3_FLT1CNT_Pos) /*!< 0x00000004 */
9811 #define HRTIM_FLTINR3_FLT1CNT_1 (0x2UL << HRTIM_FLTINR3_FLT1CNT_Pos) /*!< 0x00000008 */
9812 #define HRTIM_FLTINR3_FLT1CNT_2 (0x4UL << HRTIM_FLTINR3_FLT1CNT_Pos) /*!< 0x00000010 */
9813 #define HRTIM_FLTINR3_FLT1CNT_3 (0x8UL << HRTIM_FLTINR3_FLT1CNT_Pos) /*!< 0x00000020 */
9814 #define HRTIM_FLTINR3_FLT1CRES_Pos (6U)
9815 #define HRTIM_FLTINR3_FLT1CRES_Msk (0x1UL << HRTIM_FLTINR3_FLT1CRES_Pos) /*!< 0x00000040 */
9816 #define HRTIM_FLTINR3_FLT1CRES HRTIM_FLTINR3_FLT1CRES_Msk /*!< Fault 1 Counter Reset */
9817 #define HRTIM_FLTINR3_FLT1RSTM_Pos (7U)
9818 #define HRTIM_FLTINR3_FLT1RSTM_Msk (0x1UL << HRTIM_FLTINR3_FLT1RSTM_Pos) /*!< 0x00000080 */
9819 #define HRTIM_FLTINR3_FLT1RSTM HRTIM_FLTINR3_FLT1RSTM_Msk /*!< Fault 1 Counter Reset Mode */
9820 #define HRTIM_FLTINR3_FLT2BLKE_Pos (8U)
9821 #define HRTIM_FLTINR3_FLT2BLKE_Msk (0x1UL << HRTIM_FLTINR3_FLT2BLKE_Pos) /*!< 0x00000100 */
9822 #define HRTIM_FLTINR3_FLT2BLKE HRTIM_FLTINR3_FLT2BLKE_Msk /*!< Fault 2 Blanking Enable */
9823 #define HRTIM_FLTINR3_FLT2BLKS_Pos (9U)
9824 #define HRTIM_FLTINR3_FLT2BLKS_Msk (0x1UL << HRTIM_FLTINR3_FLT2BLKS_Pos) /*!< 0x00000200 */
9825 #define HRTIM_FLTINR3_FLT2BLKS HRTIM_FLTINR3_FLT2BLKS_Msk /*!< Fault 2 Blanking Source */
9826 #define HRTIM_FLTINR3_FLT2CNT_Pos (10U)
9827 #define HRTIM_FLTINR3_FLT2CNT_Msk (0xFUL << HRTIM_FLTINR3_FLT2CNT_Pos) /*!< 0x00003C00 */
9828 #define HRTIM_FLTINR3_FLT2CNT HRTIM_FLTINR3_FLT2CNT_Msk /*!< Fault 2 Counter */
9829 #define HRTIM_FLTINR3_FLT2CNT_0 (0x1UL << HRTIM_FLTINR3_FLT2CNT_Pos) /*!< 0x00000400 */
9830 #define HRTIM_FLTINR3_FLT2CNT_1 (0x2UL << HRTIM_FLTINR3_FLT2CNT_Pos) /*!< 0x00000800 */
9831 #define HRTIM_FLTINR3_FLT2CNT_2 (0x4UL << HRTIM_FLTINR3_FLT2CNT_Pos) /*!< 0x00001000 */
9832 #define HRTIM_FLTINR3_FLT2CNT_3 (0x8UL << HRTIM_FLTINR3_FLT2CNT_Pos) /*!< 0x00002000 */
9833 #define HRTIM_FLTINR3_FLT2CRES_Pos (14U)
9834 #define HRTIM_FLTINR3_FLT2CRES_Msk (0x1UL << HRTIM_FLTINR3_FLT2CRES_Pos) /*!< 0x00004000 */
9835 #define HRTIM_FLTINR3_FLT2CRES HRTIM_FLTINR3_FLT2CRES_Msk /*!< Fault 2 Counter Reset */
9836 #define HRTIM_FLTINR3_FLT2RSTM_Pos (15U)
9837 #define HRTIM_FLTINR3_FLT2RSTM_Msk (0x1UL << HRTIM_FLTINR3_FLT2RSTM_Pos) /*!< 0x00008000 */
9838 #define HRTIM_FLTINR3_FLT2RSTM HRTIM_FLTINR3_FLT2RSTM_Msk /*!< Fault 2 Counter Reset Mode */
9839 #define HRTIM_FLTINR3_FLT3BLKE_Pos (16U)
9840 #define HRTIM_FLTINR3_FLT3BLKE_Msk (0x1UL << HRTIM_FLTINR3_FLT3BLKE_Pos) /*!< 0x00010000 */
9841 #define HRTIM_FLTINR3_FLT3BLKE HRTIM_FLTINR3_FLT3BLKE_Msk /*!< Fault 3 Blanking Enable */
9842 #define HRTIM_FLTINR3_FLT3BLKS_Pos (17U)
9843 #define HRTIM_FLTINR3_FLT3BLKS_Msk (0x1UL << HRTIM_FLTINR3_FLT3BLKS_Pos) /*!< 0x00020000 */
9844 #define HRTIM_FLTINR3_FLT3BLKS HRTIM_FLTINR3_FLT3BLKS_Msk /*!< Fault 3 Blanking Source */
9845 #define HRTIM_FLTINR3_FLT3CNT_Pos (18U)
9846 #define HRTIM_FLTINR3_FLT3CNT_Msk (0xFUL << HRTIM_FLTINR3_FLT3CNT_Pos) /*!< 0x003C0000 */
9847 #define HRTIM_FLTINR3_FLT3CNT HRTIM_FLTINR3_FLT3CNT_Msk /*!< Fault 3 Counter */
9848 #define HRTIM_FLTINR3_FLT3CNT_0 (0x1UL << HRTIM_FLTINR3_FLT3CNT_Pos) /*!< 0x00040000 */
9849 #define HRTIM_FLTINR3_FLT3CNT_1 (0x2UL << HRTIM_FLTINR3_FLT3CNT_Pos) /*!< 0x00080000 */
9850 #define HRTIM_FLTINR3_FLT3CNT_2 (0x4UL << HRTIM_FLTINR3_FLT3CNT_Pos) /*!< 0x00100000 */
9851 #define HRTIM_FLTINR3_FLT3CNT_3 (0x8UL << HRTIM_FLTINR3_FLT3CNT_Pos) /*!< 0x00200000 */
9852 #define HRTIM_FLTINR3_FLT3CRES_Pos (22U)
9853 #define HRTIM_FLTINR3_FLT3CRES_Msk (0x1UL << HRTIM_FLTINR3_FLT3CRES_Pos) /*!< 0x00400000 */
9854 #define HRTIM_FLTINR3_FLT3CRES HRTIM_FLTINR3_FLT3CRES_Msk /*!< Fault 3 Counter Reset */
9855 #define HRTIM_FLTINR3_FLT3RSTM_Pos (23U)
9856 #define HRTIM_FLTINR3_FLT3RSTM_Msk (0x1UL << HRTIM_FLTINR3_FLT3RSTM_Pos) /*!< 0x00800000 */
9857 #define HRTIM_FLTINR3_FLT3RSTM HRTIM_FLTINR3_FLT3RSTM_Msk /*!< Fault 3 Counter Reset Mode */
9858 #define HRTIM_FLTINR3_FLT4BLKE_Pos (24U)
9859 #define HRTIM_FLTINR3_FLT4BLKE_Msk (0x1UL << HRTIM_FLTINR3_FLT4BLKE_Pos) /*!< 0x01000000 */
9860 #define HRTIM_FLTINR3_FLT4BLKE HRTIM_FLTINR3_FLT4BLKE_Msk /*!< Fault 4 Blanking Enable */
9861 #define HRTIM_FLTINR3_FLT4BLKS_Pos (25U)
9862 #define HRTIM_FLTINR3_FLT4BLKS_Msk (0x1UL << HRTIM_FLTINR3_FLT4BLKS_Pos) /*!< 0x02000000 */
9863 #define HRTIM_FLTINR3_FLT4BLKS HRTIM_FLTINR3_FLT4BLKS_Msk /*!< Fault 4 Blanking Source */
9864 #define HRTIM_FLTINR3_FLT4CNT_Pos (26U)
9865 #define HRTIM_FLTINR3_FLT4CNT_Msk (0xFUL << HRTIM_FLTINR3_FLT4CNT_Pos) /*!< 0x003C0000 */
9866 #define HRTIM_FLTINR3_FLT4CNT HRTIM_FLTINR3_FLT4CNT_Msk /*!< Fault 4 Counter */
9867 #define HRTIM_FLTINR3_FLT4CNT_0 (0x1UL << HRTIM_FLTINR3_FLT4CNT_Pos) /*!< 0x00040000 */
9868 #define HRTIM_FLTINR3_FLT4CNT_1 (0x2UL << HRTIM_FLTINR3_FLT4CNT_Pos) /*!< 0x00080000 */
9869 #define HRTIM_FLTINR3_FLT4CNT_2 (0x4UL << HRTIM_FLTINR3_FLT4CNT_Pos) /*!< 0x00100000 */
9870 #define HRTIM_FLTINR3_FLT4CNT_3 (0x8UL << HRTIM_FLTINR3_FLT4CNT_Pos) /*!< 0x00200000 */
9871 #define HRTIM_FLTINR3_FLT4CRES_Pos (30U)
9872 #define HRTIM_FLTINR3_FLT4CRES_Msk (0x1UL << HRTIM_FLTINR3_FLT4CRES_Pos) /*!< 0x40000000 */
9873 #define HRTIM_FLTINR3_FLT4CRES HRTIM_FLTINR3_FLT4CRES_Msk /*!< Fault 4 Counter Reset */
9874 #define HRTIM_FLTINR3_FLT4RSTM_Pos (31U)
9875 #define HRTIM_FLTINR3_FLT4RSTM_Msk (0x1UL << HRTIM_FLTINR3_FLT4RSTM_Pos) /*!< 0x80000000 */
9876 #define HRTIM_FLTINR3_FLT4RSTM HRTIM_FLTINR3_FLT4RSTM_Msk /*!< Fault 4 Counter Reset Mode */
9877
9878 /******************* Bit definition for HRTIM_FLTINR4 register ***************/
9879 #define HRTIM_FLTINR4_FLT5BLKE_Pos (0U)
9880 #define HRTIM_FLTINR4_FLT5BLKE_Msk (0x1UL << HRTIM_FLTINR4_FLT5BLKE_Pos) /*!< 0x00000001 */
9881 #define HRTIM_FLTINR4_FLT5BLKE HRTIM_FLTINR4_FLT5BLKE_Msk /*!< Fault 5 Blanking Enable */
9882 #define HRTIM_FLTINR4_FLT5BLKS_Pos (1U)
9883 #define HRTIM_FLTINR4_FLT5BLKS_Msk (0x1UL << HRTIM_FLTINR4_FLT5BLKS_Pos) /*!< 0x00000002 */
9884 #define HRTIM_FLTINR4_FLT5BLKS HRTIM_FLTINR4_FLT5BLKS_Msk /*!< Fault 5 Blanking Source */
9885 #define HRTIM_FLTINR4_FLT5CNT_Pos (2U)
9886 #define HRTIM_FLTINR4_FLT5CNT_Msk (0xFUL << HRTIM_FLTINR4_FLT5CNT_Pos) /*!< 0x0000003C */
9887 #define HRTIM_FLTINR4_FLT5CNT HRTIM_FLTINR4_FLT5CNT_Msk /*!< Fault 5 Counter */
9888 #define HRTIM_FLTINR4_FLT5CNT_0 (0x1UL << HRTIM_FLTINR4_FLT5CNT_Pos) /*!< 0x00000004 */
9889 #define HRTIM_FLTINR4_FLT5CNT_1 (0x2UL << HRTIM_FLTINR4_FLT5CNT_Pos) /*!< 0x00000008 */
9890 #define HRTIM_FLTINR4_FLT5CNT_2 (0x4UL << HRTIM_FLTINR4_FLT5CNT_Pos) /*!< 0x00000010 */
9891 #define HRTIM_FLTINR4_FLT5CNT_3 (0x8UL << HRTIM_FLTINR4_FLT5CNT_Pos) /*!< 0x00000020 */
9892 #define HRTIM_FLTINR4_FLT5CRES_Pos (6U)
9893 #define HRTIM_FLTINR4_FLT5CRES_Msk (0x1UL << HRTIM_FLTINR4_FLT5CRES_Pos) /*!< 0x00000040 */
9894 #define HRTIM_FLTINR4_FLT5CRES HRTIM_FLTINR4_FLT5CRES_Msk /*!< Fault 5 Counter Reset */
9895 #define HRTIM_FLTINR4_FLT5RSTM_Pos (7U)
9896 #define HRTIM_FLTINR4_FLT5RSTM_Msk (0x1UL << HRTIM_FLTINR4_FLT5RSTM_Pos) /*!< 0x00000080 */
9897 #define HRTIM_FLTINR4_FLT5RSTM HRTIM_FLTINR4_FLT5RSTM_Msk /*!< Fault 5 Counter Reset Mode */
9898 #define HRTIM_FLTINR4_FLT6BLKE_Pos (8U)
9899 #define HRTIM_FLTINR4_FLT6BLKE_Msk (0x1UL << HRTIM_FLTINR4_FLT6BLKE_Pos) /*!< 0x00000100 */
9900 #define HRTIM_FLTINR4_FLT6BLKE HRTIM_FLTINR4_FLT6BLKE_Msk /*!< Fault 6 Blanking Enable */
9901 #define HRTIM_FLTINR4_FLT6BLKS_Pos (9U)
9902 #define HRTIM_FLTINR4_FLT6BLKS_Msk (0x1UL << HRTIM_FLTINR4_FLT6BLKS_Pos) /*!< 0x00000200 */
9903 #define HRTIM_FLTINR4_FLT6BLKS HRTIM_FLTINR4_FLT6BLKS_Msk /*!< Fault 6 Blanking Source */
9904 #define HRTIM_FLTINR4_FLT6CNT_Pos (10U)
9905 #define HRTIM_FLTINR4_FLT6CNT_Msk (0xFUL << HRTIM_FLTINR4_FLT6CNT_Pos) /*!< 0x00003C00 */
9906 #define HRTIM_FLTINR4_FLT6CNT HRTIM_FLTINR4_FLT6CNT_Msk /*!< Fault 6 Counter */
9907 #define HRTIM_FLTINR4_FLT6CNT_0 (0x1UL << HRTIM_FLTINR4_FLT6CNT_Pos) /*!< 0x00000400 */
9908 #define HRTIM_FLTINR4_FLT6CNT_1 (0x2UL << HRTIM_FLTINR4_FLT6CNT_Pos) /*!< 0x00000800 */
9909 #define HRTIM_FLTINR4_FLT6CNT_2 (0x4UL << HRTIM_FLTINR4_FLT6CNT_Pos) /*!< 0x00001000 */
9910 #define HRTIM_FLTINR4_FLT6CNT_3 (0x8UL << HRTIM_FLTINR4_FLT6CNT_Pos) /*!< 0x00002000 */
9911 #define HRTIM_FLTINR4_FLT6CRES_Pos (14U)
9912 #define HRTIM_FLTINR4_FLT6CRES_Msk (0x1UL << HRTIM_FLTINR4_FLT6CRES_Pos) /*!< 0x00004000 */
9913 #define HRTIM_FLTINR4_FLT6CRES HRTIM_FLTINR4_FLT6CRES_Msk /*!< Fault 6 Counter Reset */
9914 #define HRTIM_FLTINR4_FLT6RSTM_Pos (15U)
9915 #define HRTIM_FLTINR4_FLT6RSTM_Msk (0x1UL << HRTIM_FLTINR4_FLT6RSTM_Pos) /*!< 0x00008000 */
9916 #define HRTIM_FLTINR4_FLT6RSTM HRTIM_FLTINR4_FLT6RSTM_Msk /*!< Fault 6 Counter Reset Mode */
9917
9918 /******************* Bit definition for HRTIM_BDMUPR register ***************/
9919 #define HRTIM_BDMUPR_MCR_Pos (0U)
9920 #define HRTIM_BDMUPR_MCR_Msk (0x1UL << HRTIM_BDMUPR_MCR_Pos) /*!< 0x00000001 */
9921 #define HRTIM_BDMUPR_MCR HRTIM_BDMUPR_MCR_Msk /*!< MCR register update enable */
9922 #define HRTIM_BDMUPR_MICR_Pos (1U)
9923 #define HRTIM_BDMUPR_MICR_Msk (0x1UL << HRTIM_BDMUPR_MICR_Pos) /*!< 0x00000002 */
9924 #define HRTIM_BDMUPR_MICR HRTIM_BDMUPR_MICR_Msk /*!< MICR register update enable */
9925 #define HRTIM_BDMUPR_MDIER_Pos (2U)
9926 #define HRTIM_BDMUPR_MDIER_Msk (0x1UL << HRTIM_BDMUPR_MDIER_Pos) /*!< 0x00000004 */
9927 #define HRTIM_BDMUPR_MDIER HRTIM_BDMUPR_MDIER_Msk /*!< MDIER register update enable */
9928 #define HRTIM_BDMUPR_MCNT_Pos (3U)
9929 #define HRTIM_BDMUPR_MCNT_Msk (0x1UL << HRTIM_BDMUPR_MCNT_Pos) /*!< 0x00000008 */
9930 #define HRTIM_BDMUPR_MCNT HRTIM_BDMUPR_MCNT_Msk /*!< MCNT register update enable */
9931 #define HRTIM_BDMUPR_MPER_Pos (4U)
9932 #define HRTIM_BDMUPR_MPER_Msk (0x1UL << HRTIM_BDMUPR_MPER_Pos) /*!< 0x00000010 */
9933 #define HRTIM_BDMUPR_MPER HRTIM_BDMUPR_MPER_Msk /*!< MPER register update enable */
9934 #define HRTIM_BDMUPR_MREP_Pos (5U)
9935 #define HRTIM_BDMUPR_MREP_Msk (0x1UL << HRTIM_BDMUPR_MREP_Pos) /*!< 0x00000020 */
9936 #define HRTIM_BDMUPR_MREP HRTIM_BDMUPR_MREP_Msk /*!< MREP register update enable */
9937 #define HRTIM_BDMUPR_MCMP1_Pos (6U)
9938 #define HRTIM_BDMUPR_MCMP1_Msk (0x1UL << HRTIM_BDMUPR_MCMP1_Pos) /*!< 0x00000040 */
9939 #define HRTIM_BDMUPR_MCMP1 HRTIM_BDMUPR_MCMP1_Msk /*!< MCMP1 register update enable */
9940 #define HRTIM_BDMUPR_MCMP2_Pos (7U)
9941 #define HRTIM_BDMUPR_MCMP2_Msk (0x1UL << HRTIM_BDMUPR_MCMP2_Pos) /*!< 0x00000080 */
9942 #define HRTIM_BDMUPR_MCMP2 HRTIM_BDMUPR_MCMP2_Msk /*!< MCMP2 register update enable */
9943 #define HRTIM_BDMUPR_MCMP3_Pos (8U)
9944 #define HRTIM_BDMUPR_MCMP3_Msk (0x1UL << HRTIM_BDMUPR_MCMP3_Pos) /*!< 0x00000100 */
9945 #define HRTIM_BDMUPR_MCMP3 HRTIM_BDMUPR_MCMP3_Msk /*!< MCMP3 register update enable */
9946 #define HRTIM_BDMUPR_MCMP4_Pos (9U)
9947 #define HRTIM_BDMUPR_MCMP4_Msk (0x1UL << HRTIM_BDMUPR_MCMP4_Pos) /*!< 0x00000200 */
9948 #define HRTIM_BDMUPR_MCMP4 HRTIM_BDMUPR_MCMP4_Msk /*!< MPCMP4 register update enable */
9949
9950 /******************* Bit definition for HRTIM_BDTUPR register ***************/
9951 #define HRTIM_BDTUPR_TIMCR_Pos (0U)
9952 #define HRTIM_BDTUPR_TIMCR_Msk (0x1UL << HRTIM_BDTUPR_TIMCR_Pos) /*!< 0x00000001 */
9953 #define HRTIM_BDTUPR_TIMCR HRTIM_BDTUPR_TIMCR_Msk /*!< TIMCR register update enable */
9954 #define HRTIM_BDTUPR_TIMICR_Pos (1U)
9955 #define HRTIM_BDTUPR_TIMICR_Msk (0x1UL << HRTIM_BDTUPR_TIMICR_Pos) /*!< 0x00000002 */
9956 #define HRTIM_BDTUPR_TIMICR HRTIM_BDTUPR_TIMICR_Msk /*!< TIMICR register update enable */
9957 #define HRTIM_BDTUPR_TIMDIER_Pos (2U)
9958 #define HRTIM_BDTUPR_TIMDIER_Msk (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos) /*!< 0x00000004 */
9959 #define HRTIM_BDTUPR_TIMDIER HRTIM_BDTUPR_TIMDIER_Msk /*!< TIMDIER register update enable */
9960 #define HRTIM_BDTUPR_TIMCNT_Pos (3U)
9961 #define HRTIM_BDTUPR_TIMCNT_Msk (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos) /*!< 0x00000008 */
9962 #define HRTIM_BDTUPR_TIMCNT HRTIM_BDTUPR_TIMCNT_Msk /*!< TIMCNT register update enable */
9963 #define HRTIM_BDTUPR_TIMPER_Pos (4U)
9964 #define HRTIM_BDTUPR_TIMPER_Msk (0x1UL << HRTIM_BDTUPR_TIMPER_Pos) /*!< 0x00000010 */
9965 #define HRTIM_BDTUPR_TIMPER HRTIM_BDTUPR_TIMPER_Msk /*!< TIMPER register update enable */
9966 #define HRTIM_BDTUPR_TIMREP_Pos (5U)
9967 #define HRTIM_BDTUPR_TIMREP_Msk (0x1UL << HRTIM_BDTUPR_TIMREP_Pos) /*!< 0x00000020 */
9968 #define HRTIM_BDTUPR_TIMREP HRTIM_BDTUPR_TIMREP_Msk /*!< TIMREP register update enable */
9969 #define HRTIM_BDTUPR_TIMCMP1_Pos (6U)
9970 #define HRTIM_BDTUPR_TIMCMP1_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos) /*!< 0x00000040 */
9971 #define HRTIM_BDTUPR_TIMCMP1 HRTIM_BDTUPR_TIMCMP1_Msk /*!< TIMCMP1 register update enable */
9972 #define HRTIM_BDTUPR_TIMCMP2_Pos (7U)
9973 #define HRTIM_BDTUPR_TIMCMP2_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos) /*!< 0x00000080 */
9974 #define HRTIM_BDTUPR_TIMCMP2 HRTIM_BDTUPR_TIMCMP2_Msk /*!< TIMCMP2 register update enable */
9975 #define HRTIM_BDTUPR_TIMCMP3_Pos (8U)
9976 #define HRTIM_BDTUPR_TIMCMP3_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos) /*!< 0x00000100 */
9977 #define HRTIM_BDTUPR_TIMCMP3 HRTIM_BDTUPR_TIMCMP3_Msk /*!< TIMCMP3 register update enable */
9978 #define HRTIM_BDTUPR_TIMCMP4_Pos (9U)
9979 #define HRTIM_BDTUPR_TIMCMP4_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos) /*!< 0x00000200 */
9980 #define HRTIM_BDTUPR_TIMCMP4 HRTIM_BDTUPR_TIMCMP4_Msk /*!< TIMCMP4 register update enable */
9981 #define HRTIM_BDTUPR_TIMDTR_Pos (10U)
9982 #define HRTIM_BDTUPR_TIMDTR_Msk (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos) /*!< 0x00000400 */
9983 #define HRTIM_BDTUPR_TIMDTR HRTIM_BDTUPR_TIMDTR_Msk /*!< TIMDTR register update enable */
9984 #define HRTIM_BDTUPR_TIMSET1R_Pos (11U)
9985 #define HRTIM_BDTUPR_TIMSET1R_Msk (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos) /*!< 0x00000800 */
9986 #define HRTIM_BDTUPR_TIMSET1R HRTIM_BDTUPR_TIMSET1R_Msk /*!< TIMSET1R register update enable */
9987 #define HRTIM_BDTUPR_TIMRST1R_Pos (12U)
9988 #define HRTIM_BDTUPR_TIMRST1R_Msk (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos) /*!< 0x00001000 */
9989 #define HRTIM_BDTUPR_TIMRST1R HRTIM_BDTUPR_TIMRST1R_Msk /*!< TIMRST1R register update enable */
9990 #define HRTIM_BDTUPR_TIMSET2R_Pos (13U)
9991 #define HRTIM_BDTUPR_TIMSET2R_Msk (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos) /*!< 0x00002000 */
9992 #define HRTIM_BDTUPR_TIMSET2R HRTIM_BDTUPR_TIMSET2R_Msk /*!< TIMSET2R register update enable */
9993 #define HRTIM_BDTUPR_TIMRST2R_Pos (14U)
9994 #define HRTIM_BDTUPR_TIMRST2R_Msk (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos) /*!< 0x00004000 */
9995 #define HRTIM_BDTUPR_TIMRST2R HRTIM_BDTUPR_TIMRST2R_Msk /*!< TIMRST2R register update enable */
9996 #define HRTIM_BDTUPR_TIMEEFR1_Pos (15U)
9997 #define HRTIM_BDTUPR_TIMEEFR1_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos) /*!< 0x00008000 */
9998 #define HRTIM_BDTUPR_TIMEEFR1 HRTIM_BDTUPR_TIMEEFR1_Msk /*!< TIMEEFR1 register update enable */
9999 #define HRTIM_BDTUPR_TIMEEFR2_Pos (16U)
10000 #define HRTIM_BDTUPR_TIMEEFR2_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos) /*!< 0x00010000 */
10001 #define HRTIM_BDTUPR_TIMEEFR2 HRTIM_BDTUPR_TIMEEFR2_Msk /*!< TIMEEFR2 register update enable */
10002 #define HRTIM_BDTUPR_TIMRSTR_Pos (17U)
10003 #define HRTIM_BDTUPR_TIMRSTR_Msk (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos) /*!< 0x00020000 */
10004 #define HRTIM_BDTUPR_TIMRSTR HRTIM_BDTUPR_TIMRSTR_Msk /*!< TIMRSTR register update enable */
10005 #define HRTIM_BDTUPR_TIMCHPR_Pos (18U)
10006 #define HRTIM_BDTUPR_TIMCHPR_Msk (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos) /*!< 0x00040000 */
10007 #define HRTIM_BDTUPR_TIMCHPR HRTIM_BDTUPR_TIMCHPR_Msk /*!< TIMCHPR register update enable */
10008 #define HRTIM_BDTUPR_TIMOUTR_Pos (19U)
10009 #define HRTIM_BDTUPR_TIMOUTR_Msk (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos) /*!< 0x00080000 */
10010 #define HRTIM_BDTUPR_TIMOUTR HRTIM_BDTUPR_TIMOUTR_Msk /*!< TIMOUTR register update enable */
10011 #define HRTIM_BDTUPR_TIMFLTR_Pos (20U)
10012 #define HRTIM_BDTUPR_TIMFLTR_Msk (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos) /*!< 0x00100000 */
10013 #define HRTIM_BDTUPR_TIMFLTR HRTIM_BDTUPR_TIMFLTR_Msk /*!< TIMFLTR register update enable */
10014 #define HRTIM_BDTUPR_TIMCR2_Pos (21U)
10015 #define HRTIM_BDTUPR_TIMCR2_Msk (0x1UL << HRTIM_BDTUPR_TIMCR2_Pos) /*!< 0x00200000 */
10016 #define HRTIM_BDTUPR_TIMCR2 HRTIM_BDTUPR_TIMCR2_Msk /*!< TIMCR2 register update enable */
10017 #define HRTIM_BDTUPR_TIMEEFR3_Pos (22U)
10018 #define HRTIM_BDTUPR_TIMEEFR3_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR3_Pos) /*!< 0x00400000 */
10019 #define HRTIM_BDTUPR_TIMEEFR3 HRTIM_BDTUPR_TIMEEFR3_Msk /*!< TIMEEFR3 register update enable */
10020
10021 /******************* Bit definition for HRTIM_BDMADR register ***************/
10022 #define HRTIM_BDMADR_BDMADR_Pos (0U)
10023 #define HRTIM_BDMADR_BDMADR_Msk (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos)/*!< 0xFFFFFFFF */
10024 #define HRTIM_BDMADR_BDMADR HRTIM_BDMADR_BDMADR_Msk /*!< Burst DMA Data register */
10025
10026 /******************* Bit definition for HRTIM_ADC Extended Trigger register ***************/
10027 #define HRTIM_ADCER_AD5TRG_Pos (0U)
10028 #define HRTIM_ADCER_AD5TRG_Msk (0x1FUL << HRTIM_ADCER_AD5TRG_Pos) /*!< 0x0000001F */
10029 #define HRTIM_ADCER_AD5TRG HRTIM_ADCER_AD5TRG_Msk /*!< ADC5 trigger */
10030 #define HRTIM_ADCER_AD6TRG_Pos (5U)
10031 #define HRTIM_ADCER_AD6TRG_Msk (0x1FUL << HRTIM_ADCER_AD6TRG_Pos) /*!< 0x000003E0 */
10032 #define HRTIM_ADCER_AD6TRG HRTIM_ADCER_AD6TRG_Msk /*!< ADC6 trigger */
10033 #define HRTIM_ADCER_AD7TRG_Pos (10U)
10034 #define HRTIM_ADCER_AD7TRG_Msk (0x1FUL << HRTIM_ADCER_AD7TRG_Pos) /*!< 0x00007C00 */
10035 #define HRTIM_ADCER_AD7TRG HRTIM_ADCER_AD7TRG_Msk /*!< ADC7 trigger */
10036 #define HRTIM_ADCER_AD8TRG_Pos (16U)
10037 #define HRTIM_ADCER_AD8TRG_Msk (0x1FUL << HRTIM_ADCER_AD8TRG_Pos) /*!< 0x001F0000 */
10038 #define HRTIM_ADCER_AD8TRG HRTIM_ADCER_AD8TRG_Msk /*!< ADC8 trigger */
10039 #define HRTIM_ADCER_AD9TRG_Pos (21U)
10040 #define HRTIM_ADCER_AD9TRG_Msk (0x1FUL << HRTIM_ADCER_AD9TRG_Pos) /*!< 0x003E00000 */
10041 #define HRTIM_ADCER_AD9TRG HRTIM_ADCER_AD9TRG_Msk /*!< ADC9 trigger */
10042 #define HRTIM_ADCER_AD10TRG_Pos (26U)
10043 #define HRTIM_ADCER_AD10TRG_Msk (0x1FUL << HRTIM_ADCER_AD10TRG_Pos) /*!< 0x7C000000 */
10044 #define HRTIM_ADCER_AD10TRG HRTIM_ADCER_AD10TRG_Msk /*!< ADC10 trigger */
10045
10046 /******************* Bit definition for HRTIM_ADC Trigger Update register ***************/
10047 #define HRTIM_ADCUR_AD5USRC_Pos (0U)
10048 #define HRTIM_ADCUR_AD5USRC_Msk (0x7UL << HRTIM_ADCUR_AD5USRC_Pos) /*!< 0x00000007 */
10049 #define HRTIM_ADCUR_AD5USRC HRTIM_ADCUR_AD5USRC_Msk /*!< ADC5 trigger Update Source */
10050 #define HRTIM_ADCUR_AD6USRC_Pos (4U)
10051 #define HRTIM_ADCUR_AD6USRC_Msk (0x7UL << HRTIM_ADCUR_AD6USRC_Pos) /*!< 0x00000070 */
10052 #define HRTIM_ADCUR_AD6USRC HRTIM_ADCUR_AD6USRC_Msk /*!< ADC6 trigger Update Source */
10053 #define HRTIM_ADCUR_AD7USRC_Pos (8U)
10054 #define HRTIM_ADCUR_AD7USRC_Msk (0x7UL << HRTIM_ADCUR_AD7USRC_Pos) /*!< 0x00000700 */
10055 #define HRTIM_ADCUR_AD7USRC HRTIM_ADCUR_AD7USRC_Msk /*!< ADC7 trigger Update Source */
10056 #define HRTIM_ADCUR_AD8USRC_Pos (12U)
10057 #define HRTIM_ADCUR_AD8USRC_Msk (0x7UL << HRTIM_ADCUR_AD8USRC_Pos) /*!< 0x00007000 */
10058 #define HRTIM_ADCUR_AD8USRC HRTIM_ADCUR_AD8USRC_Msk /*!< ADC8 trigger Update Source */
10059 #define HRTIM_ADCUR_AD9USRC_Pos (16U)
10060 #define HRTIM_ADCUR_AD9USRC_Msk (0x7UL << HRTIM_ADCUR_AD9USRC_Pos) /*!< 0x000070000 */
10061 #define HRTIM_ADCUR_AD9USRC HRTIM_ADCUR_AD9USRC_Msk /*!< ADC9 trigger Update Source */
10062 #define HRTIM_ADCUR_AD10USRC_Pos (20U)
10063 #define HRTIM_ADCUR_AD10USRC_Msk (0x7UL << HRTIM_ADCUR_AD10USRC_Pos) /*!< 0x00700000 */
10064 #define HRTIM_ADCUR_AD10USRC HRTIM_ADCUR_AD10USRC_Msk /*!< ADC10 trigger Update Source */
10065
10066 /******************* Bit definition for HRTIM_ADCPS1 ADC Post Scaler register 1 ***************/
10067 #define HRTIM_ADCPS1_AD1PSC_Pos (0U)
10068 #define HRTIM_ADCPS1_AD1PSC_Msk (0x1FUL << HRTIM_ADCPS1_AD1PSC_Pos) /*!< 0x0000001F */
10069 #define HRTIM_ADCPS1_AD1PSC HRTIM_ADCPS1_AD1PSC_Msk /*!< ADC1 post scaler */
10070 #define HRTIM_ADCPS1_AD2PSC_Pos (6U)
10071 #define HRTIM_ADCPS1_AD2PSC_Msk (0x1FUL << HRTIM_ADCPS1_AD2PSC_Pos) /*!< 0x000007C0 */
10072 #define HRTIM_ADCPS1_AD2PSC HRTIM_ADCPS1_AD2PSC_Msk /*!< ADC2 post scaler */
10073 #define HRTIM_ADCPS1_AD3PSC_Pos (12U)
10074 #define HRTIM_ADCPS1_AD3PSC_Msk (0x1FUL << HRTIM_ADCPS1_AD3PSC_Pos) /*!< 0x0001F000 */
10075 #define HRTIM_ADCPS1_AD3PSC HRTIM_ADCPS1_AD3PSC_Msk /*!< ADC3 post scaler */
10076 #define HRTIM_ADCPS1_AD4PSC_Pos (18U)
10077 #define HRTIM_ADCPS1_AD4PSC_Msk (0x1FUL << HRTIM_ADCPS1_AD4PSC_Pos) /*!< 0x007C0000 */
10078 #define HRTIM_ADCPS1_AD4PSC HRTIM_ADCPS1_AD4PSC_Msk /*!< ADC4 post scaler */
10079 #define HRTIM_ADCPS1_AD5PSC_Pos (24U)
10080 #define HRTIM_ADCPS1_AD5PSC_Msk (0x1FUL << HRTIM_ADCPS1_AD5PSC_Pos) /*!< 0x1F000000 */
10081 #define HRTIM_ADCPS1_AD5PSC HRTIM_ADCPS1_AD5PSC_Msk /*!< ADC5 post scaler */
10082
10083 /******************* Bit definition for HRTIM_ADCPS2 ADC Post Scaler register 2 ***************/
10084 #define HRTIM_ADCPS2_AD6PSC_Pos (0U)
10085 #define HRTIM_ADCPS2_AD6PSC_Msk (0x1FUL << HRTIM_ADCPS2_AD6PSC_Pos) /*!< 0x0000001F */
10086 #define HRTIM_ADCPS2_AD6PSC HRTIM_ADCPS2_AD6PSC_Msk /*!< ADC6 post scaler */
10087 #define HRTIM_ADCPS2_AD7PSC_Pos (6U)
10088 #define HRTIM_ADCPS2_AD7PSC_Msk (0x1FUL << HRTIM_ADCPS2_AD7PSC_Pos) /*!< 0x000007C0 */
10089 #define HRTIM_ADCPS2_AD7PSC HRTIM_ADCPS2_AD7PSC_Msk /*!< ADC7 post scaler */
10090 #define HRTIM_ADCPS2_AD8PSC_Pos (12U)
10091 #define HRTIM_ADCPS2_AD8PSC_Msk (0x1FUL << HRTIM_ADCPS2_AD8PSC_Pos) /*!< 0x0001F000 */
10092 #define HRTIM_ADCPS2_AD8PSC HRTIM_ADCPS2_AD8PSC_Msk /*!< ADC8 post scaler */
10093 #define HRTIM_ADCPS2_AD9PSC_Pos (18U)
10094 #define HRTIM_ADCPS2_AD9PSC_Msk (0x1FUL << HRTIM_ADCPS2_AD9PSC_Pos) /*!< 0x007C0000 */
10095 #define HRTIM_ADCPS2_AD9PSC HRTIM_ADCPS2_AD9PSC_Msk /*!< ADC9 post scaler */
10096 #define HRTIM_ADCPS2_AD10PSC_Pos (24U)
10097 #define HRTIM_ADCPS2_AD10PSC_Msk (0x1FUL << HRTIM_ADCPS2_AD10PSC_Pos) /*!< 0x1F000000 */
10098 #define HRTIM_ADCPS2_AD10PSC HRTIM_ADCPS2_AD10PSC_Msk /*!< ADC10 post scaler */
10099
10100
10101 /******************************************************************************/
10102 /* */
10103 /* Inter-integrated Circuit Interface (I2C) */
10104 /* */
10105 /******************************************************************************/
10106 /******************* Bit definition for I2C_CR1 register *******************/
10107 #define I2C_CR1_PE_Pos (0U)
10108 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
10109 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
10110 #define I2C_CR1_TXIE_Pos (1U)
10111 #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
10112 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
10113 #define I2C_CR1_RXIE_Pos (2U)
10114 #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
10115 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
10116 #define I2C_CR1_ADDRIE_Pos (3U)
10117 #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
10118 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
10119 #define I2C_CR1_NACKIE_Pos (4U)
10120 #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
10121 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
10122 #define I2C_CR1_STOPIE_Pos (5U)
10123 #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
10124 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
10125 #define I2C_CR1_TCIE_Pos (6U)
10126 #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
10127 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
10128 #define I2C_CR1_ERRIE_Pos (7U)
10129 #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
10130 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
10131 #define I2C_CR1_DNF_Pos (8U)
10132 #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
10133 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
10134 #define I2C_CR1_ANFOFF_Pos (12U)
10135 #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
10136 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
10137 #define I2C_CR1_SWRST_Pos (13U)
10138 #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
10139 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
10140 #define I2C_CR1_TXDMAEN_Pos (14U)
10141 #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
10142 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
10143 #define I2C_CR1_RXDMAEN_Pos (15U)
10144 #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
10145 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
10146 #define I2C_CR1_SBC_Pos (16U)
10147 #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
10148 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
10149 #define I2C_CR1_NOSTRETCH_Pos (17U)
10150 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
10151 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
10152 #define I2C_CR1_WUPEN_Pos (18U)
10153 #define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
10154 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
10155 #define I2C_CR1_GCEN_Pos (19U)
10156 #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
10157 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
10158 #define I2C_CR1_SMBHEN_Pos (20U)
10159 #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
10160 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
10161 #define I2C_CR1_SMBDEN_Pos (21U)
10162 #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
10163 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
10164 #define I2C_CR1_ALERTEN_Pos (22U)
10165 #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
10166 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
10167 #define I2C_CR1_PECEN_Pos (23U)
10168 #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
10169 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
10170
10171 /****************** Bit definition for I2C_CR2 register ********************/
10172 #define I2C_CR2_SADD_Pos (0U)
10173 #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
10174 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
10175 #define I2C_CR2_RD_WRN_Pos (10U)
10176 #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
10177 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
10178 #define I2C_CR2_ADD10_Pos (11U)
10179 #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
10180 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
10181 #define I2C_CR2_HEAD10R_Pos (12U)
10182 #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
10183 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
10184 #define I2C_CR2_START_Pos (13U)
10185 #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
10186 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
10187 #define I2C_CR2_STOP_Pos (14U)
10188 #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
10189 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
10190 #define I2C_CR2_NACK_Pos (15U)
10191 #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
10192 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
10193 #define I2C_CR2_NBYTES_Pos (16U)
10194 #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
10195 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
10196 #define I2C_CR2_RELOAD_Pos (24U)
10197 #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
10198 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
10199 #define I2C_CR2_AUTOEND_Pos (25U)
10200 #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
10201 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
10202 #define I2C_CR2_PECBYTE_Pos (26U)
10203 #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
10204 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
10205
10206 /******************* Bit definition for I2C_OAR1 register ******************/
10207 #define I2C_OAR1_OA1_Pos (0U)
10208 #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
10209 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
10210 #define I2C_OAR1_OA1MODE_Pos (10U)
10211 #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
10212 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
10213 #define I2C_OAR1_OA1EN_Pos (15U)
10214 #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
10215 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
10216
10217 /******************* Bit definition for I2C_OAR2 register ******************/
10218 #define I2C_OAR2_OA2_Pos (1U)
10219 #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
10220 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
10221 #define I2C_OAR2_OA2MSK_Pos (8U)
10222 #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
10223 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
10224 #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
10225 #define I2C_OAR2_OA2MASK01_Pos (8U)
10226 #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
10227 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
10228 #define I2C_OAR2_OA2MASK02_Pos (9U)
10229 #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
10230 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
10231 #define I2C_OAR2_OA2MASK03_Pos (8U)
10232 #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
10233 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
10234 #define I2C_OAR2_OA2MASK04_Pos (10U)
10235 #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
10236 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
10237 #define I2C_OAR2_OA2MASK05_Pos (8U)
10238 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
10239 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
10240 #define I2C_OAR2_OA2MASK06_Pos (9U)
10241 #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
10242 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
10243 #define I2C_OAR2_OA2MASK07_Pos (8U)
10244 #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
10245 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
10246 #define I2C_OAR2_OA2EN_Pos (15U)
10247 #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
10248 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
10249
10250 /******************* Bit definition for I2C_TIMINGR register *******************/
10251 #define I2C_TIMINGR_SCLL_Pos (0U)
10252 #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
10253 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
10254 #define I2C_TIMINGR_SCLH_Pos (8U)
10255 #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
10256 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
10257 #define I2C_TIMINGR_SDADEL_Pos (16U)
10258 #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
10259 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
10260 #define I2C_TIMINGR_SCLDEL_Pos (20U)
10261 #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
10262 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
10263 #define I2C_TIMINGR_PRESC_Pos (28U)
10264 #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
10265 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
10266
10267 /******************* Bit definition for I2C_TIMEOUTR register *******************/
10268 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
10269 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
10270 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
10271 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
10272 #define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
10273 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
10274 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
10275 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
10276 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
10277 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
10278 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
10279 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
10280 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
10281 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
10282 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
10283
10284 /****************** Bit definition for I2C_ISR register *********************/
10285 #define I2C_ISR_TXE_Pos (0U)
10286 #define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
10287 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
10288 #define I2C_ISR_TXIS_Pos (1U)
10289 #define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
10290 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
10291 #define I2C_ISR_RXNE_Pos (2U)
10292 #define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
10293 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
10294 #define I2C_ISR_ADDR_Pos (3U)
10295 #define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
10296 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
10297 #define I2C_ISR_NACKF_Pos (4U)
10298 #define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
10299 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
10300 #define I2C_ISR_STOPF_Pos (5U)
10301 #define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
10302 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
10303 #define I2C_ISR_TC_Pos (6U)
10304 #define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
10305 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
10306 #define I2C_ISR_TCR_Pos (7U)
10307 #define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
10308 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
10309 #define I2C_ISR_BERR_Pos (8U)
10310 #define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
10311 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
10312 #define I2C_ISR_ARLO_Pos (9U)
10313 #define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
10314 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
10315 #define I2C_ISR_OVR_Pos (10U)
10316 #define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
10317 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
10318 #define I2C_ISR_PECERR_Pos (11U)
10319 #define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
10320 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
10321 #define I2C_ISR_TIMEOUT_Pos (12U)
10322 #define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
10323 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
10324 #define I2C_ISR_ALERT_Pos (13U)
10325 #define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
10326 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
10327 #define I2C_ISR_BUSY_Pos (15U)
10328 #define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
10329 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
10330 #define I2C_ISR_DIR_Pos (16U)
10331 #define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
10332 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
10333 #define I2C_ISR_ADDCODE_Pos (17U)
10334 #define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
10335 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
10336
10337 /****************** Bit definition for I2C_ICR register *********************/
10338 #define I2C_ICR_ADDRCF_Pos (3U)
10339 #define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
10340 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
10341 #define I2C_ICR_NACKCF_Pos (4U)
10342 #define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
10343 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
10344 #define I2C_ICR_STOPCF_Pos (5U)
10345 #define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
10346 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
10347 #define I2C_ICR_BERRCF_Pos (8U)
10348 #define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
10349 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
10350 #define I2C_ICR_ARLOCF_Pos (9U)
10351 #define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
10352 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
10353 #define I2C_ICR_OVRCF_Pos (10U)
10354 #define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
10355 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
10356 #define I2C_ICR_PECCF_Pos (11U)
10357 #define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
10358 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
10359 #define I2C_ICR_TIMOUTCF_Pos (12U)
10360 #define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
10361 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
10362 #define I2C_ICR_ALERTCF_Pos (13U)
10363 #define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
10364 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
10365
10366 /****************** Bit definition for I2C_PECR register *********************/
10367 #define I2C_PECR_PEC_Pos (0U)
10368 #define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
10369 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
10370
10371 /****************** Bit definition for I2C_RXDR register *********************/
10372 #define I2C_RXDR_RXDATA_Pos (0U)
10373 #define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
10374 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
10375
10376 /****************** Bit definition for I2C_TXDR register *********************/
10377 #define I2C_TXDR_TXDATA_Pos (0U)
10378 #define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
10379 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
10380
10381 /******************************************************************************/
10382 /* */
10383 /* Independent WATCHDOG */
10384 /* */
10385 /******************************************************************************/
10386 /******************* Bit definition for IWDG_KR register ********************/
10387 #define IWDG_KR_KEY_Pos (0U)
10388 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
10389 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
10390
10391 /******************* Bit definition for IWDG_PR register ********************/
10392 #define IWDG_PR_PR_Pos (0U)
10393 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
10394 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
10395 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
10396 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
10397 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
10398
10399 /******************* Bit definition for IWDG_RLR register *******************/
10400 #define IWDG_RLR_RL_Pos (0U)
10401 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
10402 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
10403
10404 /******************* Bit definition for IWDG_SR register ********************/
10405 #define IWDG_SR_PVU_Pos (0U)
10406 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
10407 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
10408 #define IWDG_SR_RVU_Pos (1U)
10409 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
10410 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
10411 #define IWDG_SR_WVU_Pos (2U)
10412 #define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
10413 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
10414
10415 /******************* Bit definition for IWDG_KR register ********************/
10416 #define IWDG_WINR_WIN_Pos (0U)
10417 #define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
10418 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
10419
10420 /******************************************************************************/
10421 /* */
10422 /* Operational Amplifier (OPAMP) */
10423 /* */
10424 /******************************************************************************/
10425 /********************* Bit definition for OPAMPx_CSR register ***************/
10426 #define OPAMP_CSR_OPAMPxEN_Pos (0U)
10427 #define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
10428 #define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
10429 #define OPAMP_CSR_FORCEVP_Pos (1U)
10430 #define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos) /*!< 0x00000002 */
10431 #define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */
10432 #define OPAMP_CSR_VPSEL_Pos (2U)
10433 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
10434 #define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverting input selection */
10435 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
10436 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
10437 #define OPAMP_CSR_USERTRIM_Pos (4U)
10438 #define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00000010 */
10439 #define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
10440 #define OPAMP_CSR_VMSEL_Pos (5U)
10441 #define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000060 */
10442 #define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
10443 #define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000020 */
10444 #define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000040 */
10445 #define OPAMP_CSR_HIGHSPEEDEN_Pos (7U)
10446 #define OPAMP_CSR_HIGHSPEEDEN_Msk (0x1UL << OPAMP_CSR_HIGHSPEEDEN_Pos) /*!< 0x00000080 */
10447 #define OPAMP_CSR_HIGHSPEEDEN OPAMP_CSR_HIGHSPEEDEN_Msk /*!< High speed mode enable */
10448 #define OPAMP_CSR_OPAMPINTEN_Pos (8U)
10449 #define OPAMP_CSR_OPAMPINTEN_Msk (0x1UL << OPAMP_CSR_OPAMPINTEN_Pos) /*!< 0x00000100 */
10450 #define OPAMP_CSR_OPAMPINTEN OPAMP_CSR_OPAMPINTEN_Msk /*!< Internal output enable */
10451 #define OPAMP_CSR_CALON_Pos (11U)
10452 #define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */
10453 #define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
10454 #define OPAMP_CSR_CALSEL_Pos (12U)
10455 #define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */
10456 #define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
10457 #define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */
10458 #define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
10459 #define OPAMP_CSR_PGGAIN_Pos (14U)
10460 #define OPAMP_CSR_PGGAIN_Msk (0x1FUL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x0007C000 */
10461 #define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Gain in PGA mode */
10462 #define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00004000 */
10463 #define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00008000 */
10464 #define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00010000 */
10465 #define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00020000 */
10466 #define OPAMP_CSR_PGGAIN_4 (0x10UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00040000 */
10467 #define OPAMP_CSR_TRIMOFFSETP_Pos (19U)
10468 #define OPAMP_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */
10469 #define OPAMP_CSR_TRIMOFFSETP OPAMP_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */
10470 #define OPAMP_CSR_TRIMOFFSETN_Pos (24U)
10471 #define OPAMP_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */
10472 #define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */
10473 #define OPAMP_CSR_OUTCAL_Pos (30U)
10474 #define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */
10475 #define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */
10476 #define OPAMP_CSR_LOCK_Pos (31U)
10477 #define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */
10478 #define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP control/status register lock */
10479
10480 /********************* Bit definition for OPAMPx_TCMR register ***************/
10481
10482 #define OPAMP_TCMR_VMSSEL_Pos (0U)
10483 #define OPAMP_TCMR_VMSSEL_Msk (0x1UL << OPAMP_TCMR_VMSSEL_Pos) /*!< 0x00000001 */
10484 #define OPAMP_TCMR_VMSSEL OPAMP_TCMR_VMSSEL_Msk /*!< Secondary inverting input selection */
10485 #define OPAMP_TCMR_VPSSEL_Pos (1U)
10486 #define OPAMP_TCMR_VPSSEL_Msk (0x3UL << OPAMP_TCMR_VPSSEL_Pos) /*!< 0x00000006 */
10487 #define OPAMP_TCMR_VPSSEL OPAMP_TCMR_VPSSEL_Msk /*!< Secondary non inverting input selection */
10488 #define OPAMP_TCMR_VPSSEL_0 (0x1UL << OPAMP_TCMR_VPSSEL_Pos) /*!< 0x00000002 */
10489 #define OPAMP_TCMR_VPSSEL_1 (0x2UL << OPAMP_TCMR_VPSSEL_Pos) /*!< 0x00000004 */
10490 #define OPAMP_TCMR_T1CMEN_Pos (3U)
10491 #define OPAMP_TCMR_T1CMEN_Msk (0x1UL << OPAMP_TCMR_T1CMEN_Pos) /*!< 0x00000008 */
10492 #define OPAMP_TCMR_T1CMEN OPAMP_TCMR_T1CMEN_Msk /*!< Timer 1 controlled mux mode enable */
10493 #define OPAMP_TCMR_T8CMEN_Pos (4U)
10494 #define OPAMP_TCMR_T8CMEN_Msk (0x1UL << OPAMP_TCMR_T8CMEN_Pos) /*!< 0x00000010 */
10495 #define OPAMP_TCMR_T8CMEN OPAMP_TCMR_T8CMEN_Msk /*!< Timer 8 controlled mux mode enable */
10496 #define OPAMP_TCMR_T20CMEN_Pos (5U)
10497 #define OPAMP_TCMR_T20CMEN_Msk (0x1UL << OPAMP_TCMR_T20CMEN_Pos) /*!< 0x00000020 */
10498 #define OPAMP_TCMR_T20CMEN OPAMP_TCMR_T20CMEN_Msk /*!< Timer 20 controlled mux mode enable */
10499 #define OPAMP_TCMR_LOCK_Pos (31U)
10500 #define OPAMP_TCMR_LOCK_Msk (0x1UL << OPAMP_TCMR_LOCK_Pos) /*!< 0x80000000 */
10501 #define OPAMP_TCMR_LOCK OPAMP_TCMR_LOCK_Msk /*!< OPAMP SW control register lock */
10502
10503
10504 /******************************************************************************/
10505 /* */
10506 /* Power Control */
10507 /* */
10508 /******************************************************************************/
10509
10510 /******************** Bit definition for PWR_CR1 register ********************/
10511
10512 #define PWR_CR1_LPR_Pos (14U)
10513 #define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos) /*!< 0x00004000 */
10514 #define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator low-power mode */
10515 #define PWR_CR1_VOS_Pos (9U)
10516 #define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos) /*!< 0x00000600 */
10517 #define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
10518 #define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos) /*!< 0x00000200 */
10519 #define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos) /*!< 0x00000400 */
10520 #define PWR_CR1_DBP_Pos (8U)
10521 #define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
10522 #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
10523 #define PWR_CR1_LPMS_Pos (0U)
10524 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
10525 #define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low-power mode selection field */
10526 #define PWR_CR1_LPMS_STOP0 (0x00000000U) /*!< Stop 0 mode */
10527 #define PWR_CR1_LPMS_STOP1_Pos (0U)
10528 #define PWR_CR1_LPMS_STOP1_Msk (0x1UL << PWR_CR1_LPMS_STOP1_Pos) /*!< 0x00000001 */
10529 #define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_Msk /*!< Stop 1 mode */
10530 #define PWR_CR1_LPMS_STANDBY_Pos (0U)
10531 #define PWR_CR1_LPMS_STANDBY_Msk (0x3UL << PWR_CR1_LPMS_STANDBY_Pos) /*!< 0x00000003 */
10532 #define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_Msk /*!< Stand-by mode */
10533 #define PWR_CR1_LPMS_SHUTDOWN_Pos (2U)
10534 #define PWR_CR1_LPMS_SHUTDOWN_Msk (0x1UL << PWR_CR1_LPMS_SHUTDOWN_Pos) /*!< 0x00000004 */
10535 #define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_Msk /*!< Shut-down mode */
10536
10537
10538 /******************** Bit definition for PWR_CR2 register ********************/
10539
10540 /*!< PVME Peripheral Voltage Monitor Enable */
10541 #define PWR_CR2_PVME_Pos (4U)
10542 #define PWR_CR2_PVME_Msk (0xFUL << PWR_CR2_PVME_Pos) /*!< 0x000000F0 */
10543 #define PWR_CR2_PVME PWR_CR2_PVME_Msk /*!< PVM bits field */
10544 #define PWR_CR2_PVME4_Pos (7U)
10545 #define PWR_CR2_PVME4_Msk (0x1UL << PWR_CR2_PVME4_Pos) /*!< 0x00000080 */
10546 #define PWR_CR2_PVME4 PWR_CR2_PVME4_Msk /*!< PVM 4 Enable */
10547 #define PWR_CR2_PVME3_Pos (6U)
10548 #define PWR_CR2_PVME3_Msk (0x1UL << PWR_CR2_PVME3_Pos) /*!< 0x00000040 */
10549 #define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk /*!< PVM 3 Enable */
10550 #define PWR_CR2_PVME2_Pos (5U)
10551 #define PWR_CR2_PVME2_Msk (0x1UL << PWR_CR2_PVME2_Pos) /*!< 0x00000020 */
10552 #define PWR_CR2_PVME2 PWR_CR2_PVME2_Msk /*!< PVM 2 Enable */
10553 #define PWR_CR2_PVME1_Pos (4U)
10554 #define PWR_CR2_PVME1_Msk (0x1UL << PWR_CR2_PVME1_Pos) /*!< 0x00000010 */
10555 #define PWR_CR2_PVME1 PWR_CR2_PVME1_Msk /*!< PVM 1 Enable */
10556
10557 /*!< PVD level configuration */
10558 #define PWR_CR2_PLS_Pos (1U)
10559 #define PWR_CR2_PLS_Msk (0x7UL << PWR_CR2_PLS_Pos) /*!< 0x0000000E */
10560 #define PWR_CR2_PLS PWR_CR2_PLS_Msk /*!< PVD level selection */
10561 #define PWR_CR2_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
10562 #define PWR_CR2_PLS_LEV1_Pos (1U)
10563 #define PWR_CR2_PLS_LEV1_Msk (0x1UL << PWR_CR2_PLS_LEV1_Pos) /*!< 0x00000002 */
10564 #define PWR_CR2_PLS_LEV1 PWR_CR2_PLS_LEV1_Msk /*!< PVD level 1 */
10565 #define PWR_CR2_PLS_LEV2_Pos (2U)
10566 #define PWR_CR2_PLS_LEV2_Msk (0x1UL << PWR_CR2_PLS_LEV2_Pos) /*!< 0x00000004 */
10567 #define PWR_CR2_PLS_LEV2 PWR_CR2_PLS_LEV2_Msk /*!< PVD level 2 */
10568 #define PWR_CR2_PLS_LEV3_Pos (1U)
10569 #define PWR_CR2_PLS_LEV3_Msk (0x3UL << PWR_CR2_PLS_LEV3_Pos) /*!< 0x00000006 */
10570 #define PWR_CR2_PLS_LEV3 PWR_CR2_PLS_LEV3_Msk /*!< PVD level 3 */
10571 #define PWR_CR2_PLS_LEV4_Pos (3U)
10572 #define PWR_CR2_PLS_LEV4_Msk (0x1UL << PWR_CR2_PLS_LEV4_Pos) /*!< 0x00000008 */
10573 #define PWR_CR2_PLS_LEV4 PWR_CR2_PLS_LEV4_Msk /*!< PVD level 4 */
10574 #define PWR_CR2_PLS_LEV5_Pos (1U)
10575 #define PWR_CR2_PLS_LEV5_Msk (0x5UL << PWR_CR2_PLS_LEV5_Pos) /*!< 0x0000000A */
10576 #define PWR_CR2_PLS_LEV5 PWR_CR2_PLS_LEV5_Msk /*!< PVD level 5 */
10577 #define PWR_CR2_PLS_LEV6_Pos (2U)
10578 #define PWR_CR2_PLS_LEV6_Msk (0x3UL << PWR_CR2_PLS_LEV6_Pos) /*!< 0x0000000C */
10579 #define PWR_CR2_PLS_LEV6 PWR_CR2_PLS_LEV6_Msk /*!< PVD level 6 */
10580 #define PWR_CR2_PLS_LEV7_Pos (1U)
10581 #define PWR_CR2_PLS_LEV7_Msk (0x7UL << PWR_CR2_PLS_LEV7_Pos) /*!< 0x0000000E */
10582 #define PWR_CR2_PLS_LEV7 PWR_CR2_PLS_LEV7_Msk /*!< PVD level 7 */
10583 #define PWR_CR2_PVDE_Pos (0U)
10584 #define PWR_CR2_PVDE_Msk (0x1UL << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */
10585 #define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
10586
10587 /******************** Bit definition for PWR_CR3 register ********************/
10588 #define PWR_CR3_EIWF_Pos (15U)
10589 #define PWR_CR3_EIWF_Msk (0x1UL << PWR_CR3_EIWF_Pos) /*!< 0x00008000 */
10590 #define PWR_CR3_EIWF PWR_CR3_EIWF_Msk /*!< Enable Internal Wake-up line */
10591 #define PWR_CR3_UCPD_DBDIS_Pos (14U)
10592 #define PWR_CR3_UCPD_DBDIS_Msk (0x1UL << PWR_CR3_UCPD_DBDIS_Pos) /*!< 0x00004000 */
10593 #define PWR_CR3_UCPD_DBDIS PWR_CR3_UCPD_DBDIS_Msk /*!< USB Type-C and Power Delivery Dead Battery disable. */
10594 #define PWR_CR3_UCPD_STDBY_Pos (13U)
10595 #define PWR_CR3_UCPD_STDBY_Msk (0x1UL << PWR_CR3_UCPD_STDBY_Pos) /*!< 0x00002000 */
10596 #define PWR_CR3_UCPD_STDBY PWR_CR3_UCPD_STDBY_Msk /*!< USB Type-C and Power Delivery standby mode. */
10597 #define PWR_CR3_APC_Pos (10U)
10598 #define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos) /*!< 0x00000400 */
10599 #define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
10600 #define PWR_CR3_RRS_Pos (8U)
10601 #define PWR_CR3_RRS_Msk (0x1UL << PWR_CR3_RRS_Pos) /*!< 0x00000100 */
10602 #define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 Retention in Stand-by mode */
10603 #define PWR_CR3_EWUP5_Pos (4U)
10604 #define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
10605 #define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk /*!< Enable Wake-Up Pin 5 */
10606 #define PWR_CR3_EWUP4_Pos (3U)
10607 #define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */
10608 #define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable Wake-Up Pin 4 */
10609 #define PWR_CR3_EWUP3_Pos (2U)
10610 #define PWR_CR3_EWUP3_Msk (0x1UL << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */
10611 #define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable Wake-Up Pin 3 */
10612 #define PWR_CR3_EWUP2_Pos (1U)
10613 #define PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */
10614 #define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable Wake-Up Pin 2 */
10615 #define PWR_CR3_EWUP1_Pos (0U)
10616 #define PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */
10617 #define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable Wake-Up Pin 1 */
10618 #define PWR_CR3_EWUP_Pos (0U)
10619 #define PWR_CR3_EWUP_Msk (0x1FUL << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
10620 #define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
10621
10622 /******************** Bit definition for PWR_CR4 register ********************/
10623 #define PWR_CR4_VBRS_Pos (9U)
10624 #define PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
10625 #define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */
10626 #define PWR_CR4_VBE_Pos (8U)
10627 #define PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos) /*!< 0x00000100 */
10628 #define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT Battery charging Enable */
10629 #define PWR_CR4_WP5_Pos (4U)
10630 #define PWR_CR4_WP5_Msk (0x1UL << PWR_CR4_WP5_Pos) /*!< 0x00000010 */
10631 #define PWR_CR4_WP5 PWR_CR4_WP5_Msk /*!< Wake-Up Pin 5 polarity */
10632 #define PWR_CR4_WP4_Pos (3U)
10633 #define PWR_CR4_WP4_Msk (0x1UL << PWR_CR4_WP4_Pos) /*!< 0x00000008 */
10634 #define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 polarity */
10635 #define PWR_CR4_WP3_Pos (2U)
10636 #define PWR_CR4_WP3_Msk (0x1UL << PWR_CR4_WP3_Pos) /*!< 0x00000004 */
10637 #define PWR_CR4_WP3 PWR_CR4_WP3_Msk /*!< Wake-Up Pin 3 polarity */
10638 #define PWR_CR4_WP2_Pos (1U)
10639 #define PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos) /*!< 0x00000002 */
10640 #define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 polarity */
10641 #define PWR_CR4_WP1_Pos (0U)
10642 #define PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos) /*!< 0x00000001 */
10643 #define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 polarity */
10644
10645 /******************** Bit definition for PWR_SR1 register ********************/
10646 #define PWR_SR1_WUFI_Pos (15U)
10647 #define PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */
10648 #define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wake-Up Flag Internal */
10649 #define PWR_SR1_SBF_Pos (8U)
10650 #define PWR_SR1_SBF_Msk (0x1UL << PWR_SR1_SBF_Pos) /*!< 0x00000100 */
10651 #define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Stand-By Flag */
10652 #define PWR_SR1_WUF_Pos (0U)
10653 #define PWR_SR1_WUF_Msk (0x1FUL << PWR_SR1_WUF_Pos) /*!< 0x0000001F */
10654 #define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wake-up Flags */
10655 #define PWR_SR1_WUF5_Pos (4U)
10656 #define PWR_SR1_WUF5_Msk (0x1UL << PWR_SR1_WUF5_Pos) /*!< 0x00000010 */
10657 #define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk /*!< Wake-up Flag 5 */
10658 #define PWR_SR1_WUF4_Pos (3U)
10659 #define PWR_SR1_WUF4_Msk (0x1UL << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */
10660 #define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wake-up Flag 4 */
10661 #define PWR_SR1_WUF3_Pos (2U)
10662 #define PWR_SR1_WUF3_Msk (0x1UL << PWR_SR1_WUF3_Pos) /*!< 0x00000004 */
10663 #define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk /*!< Wake-up Flag 3 */
10664 #define PWR_SR1_WUF2_Pos (1U)
10665 #define PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */
10666 #define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wake-up Flag 2 */
10667 #define PWR_SR1_WUF1_Pos (0U)
10668 #define PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */
10669 #define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wake-up Flag 1 */
10670
10671 /******************** Bit definition for PWR_SR2 register ********************/
10672 #define PWR_SR2_PVMO4_Pos (15U)
10673 #define PWR_SR2_PVMO4_Msk (0x1UL << PWR_SR2_PVMO4_Pos) /*!< 0x00008000 */
10674 #define PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk /*!< Peripheral Voltage Monitoring Output 4 */
10675 #define PWR_SR2_PVMO3_Pos (14U)
10676 #define PWR_SR2_PVMO3_Msk (0x1UL << PWR_SR2_PVMO3_Pos) /*!< 0x00004000 */
10677 #define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk /*!< Peripheral Voltage Monitoring Output 3 */
10678 #define PWR_SR2_PVMO2_Pos (13U)
10679 #define PWR_SR2_PVMO2_Msk (0x1UL << PWR_SR2_PVMO2_Pos) /*!< 0x00002000 */
10680 #define PWR_SR2_PVMO2 PWR_SR2_PVMO2_Msk /*!< Peripheral Voltage Monitoring Output 2 */
10681 #define PWR_SR2_PVMO1_Pos (12U)
10682 #define PWR_SR2_PVMO1_Msk (0x1UL << PWR_SR2_PVMO1_Pos) /*!< 0x00001000 */
10683 #define PWR_SR2_PVMO1 PWR_SR2_PVMO1_Msk /*!< Peripheral Voltage Monitoring Output 1 */
10684 #define PWR_SR2_PVDO_Pos (11U)
10685 #define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
10686 #define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power Voltage Detector Output */
10687 #define PWR_SR2_VOSF_Pos (10U)
10688 #define PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */
10689 #define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage Scaling Flag */
10690 #define PWR_SR2_REGLPF_Pos (9U)
10691 #define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */
10692 #define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power Regulator Flag */
10693 #define PWR_SR2_REGLPS_Pos (8U)
10694 #define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */
10695 #define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power Regulator Started */
10696
10697 /******************** Bit definition for PWR_SCR register ********************/
10698 #define PWR_SCR_CSBF_Pos (8U)
10699 #define PWR_SCR_CSBF_Msk (0x1UL << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */
10700 #define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Stand-By Flag */
10701 #define PWR_SCR_CWUF_Pos (0U)
10702 #define PWR_SCR_CWUF_Msk (0x1FUL << PWR_SCR_CWUF_Pos) /*!< 0x0000001F */
10703 #define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */
10704 #define PWR_SCR_CWUF5_Pos (4U)
10705 #define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
10706 #define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk /*!< Clear Wake-up Flag 5 */
10707 #define PWR_SCR_CWUF4_Pos (3U)
10708 #define PWR_SCR_CWUF4_Msk (0x1UL << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */
10709 #define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */
10710 #define PWR_SCR_CWUF3_Pos (2U)
10711 #define PWR_SCR_CWUF3_Msk (0x1UL << PWR_SCR_CWUF3_Pos) /*!< 0x00000004 */
10712 #define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up Flag 3 */
10713 #define PWR_SCR_CWUF2_Pos (1U)
10714 #define PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */
10715 #define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */
10716 #define PWR_SCR_CWUF1_Pos (0U)
10717 #define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */
10718 #define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */
10719
10720 /******************** Bit definition for PWR_PUCRA register ********************/
10721 #define PWR_PUCRA_PA15_Pos (15U)
10722 #define PWR_PUCRA_PA15_Msk (0x1UL << PWR_PUCRA_PA15_Pos) /*!< 0x00008000 */
10723 #define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Port PA15 Pull-Up set */
10724 #define PWR_PUCRA_PA13_Pos (13U)
10725 #define PWR_PUCRA_PA13_Msk (0x1UL << PWR_PUCRA_PA13_Pos) /*!< 0x00002000 */
10726 #define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Port PA13 Pull-Up set */
10727 #define PWR_PUCRA_PA12_Pos (12U)
10728 #define PWR_PUCRA_PA12_Msk (0x1UL << PWR_PUCRA_PA12_Pos) /*!< 0x00001000 */
10729 #define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Port PA12 Pull-Up set */
10730 #define PWR_PUCRA_PA11_Pos (11U)
10731 #define PWR_PUCRA_PA11_Msk (0x1UL << PWR_PUCRA_PA11_Pos) /*!< 0x00000800 */
10732 #define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Port PA11 Pull-Up set */
10733 #define PWR_PUCRA_PA10_Pos (10U)
10734 #define PWR_PUCRA_PA10_Msk (0x1UL << PWR_PUCRA_PA10_Pos) /*!< 0x00000400 */
10735 #define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Port PA10 Pull-Up set */
10736 #define PWR_PUCRA_PA9_Pos (9U)
10737 #define PWR_PUCRA_PA9_Msk (0x1UL << PWR_PUCRA_PA9_Pos) /*!< 0x00000200 */
10738 #define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Port PA9 Pull-Up set */
10739 #define PWR_PUCRA_PA8_Pos (8U)
10740 #define PWR_PUCRA_PA8_Msk (0x1UL << PWR_PUCRA_PA8_Pos) /*!< 0x00000100 */
10741 #define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Port PA8 Pull-Up set */
10742 #define PWR_PUCRA_PA7_Pos (7U)
10743 #define PWR_PUCRA_PA7_Msk (0x1UL << PWR_PUCRA_PA7_Pos) /*!< 0x00000080 */
10744 #define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Port PA7 Pull-Up set */
10745 #define PWR_PUCRA_PA6_Pos (6U)
10746 #define PWR_PUCRA_PA6_Msk (0x1UL << PWR_PUCRA_PA6_Pos) /*!< 0x00000040 */
10747 #define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Port PA6 Pull-Up set */
10748 #define PWR_PUCRA_PA5_Pos (5U)
10749 #define PWR_PUCRA_PA5_Msk (0x1UL << PWR_PUCRA_PA5_Pos) /*!< 0x00000020 */
10750 #define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Port PA5 Pull-Up set */
10751 #define PWR_PUCRA_PA4_Pos (4U)
10752 #define PWR_PUCRA_PA4_Msk (0x1UL << PWR_PUCRA_PA4_Pos) /*!< 0x00000010 */
10753 #define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Port PA4 Pull-Up set */
10754 #define PWR_PUCRA_PA3_Pos (3U)
10755 #define PWR_PUCRA_PA3_Msk (0x1UL << PWR_PUCRA_PA3_Pos) /*!< 0x00000008 */
10756 #define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Port PA3 Pull-Up set */
10757 #define PWR_PUCRA_PA2_Pos (2U)
10758 #define PWR_PUCRA_PA2_Msk (0x1UL << PWR_PUCRA_PA2_Pos) /*!< 0x00000004 */
10759 #define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Port PA2 Pull-Up set */
10760 #define PWR_PUCRA_PA1_Pos (1U)
10761 #define PWR_PUCRA_PA1_Msk (0x1UL << PWR_PUCRA_PA1_Pos) /*!< 0x00000002 */
10762 #define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Port PA1 Pull-Up set */
10763 #define PWR_PUCRA_PA0_Pos (0U)
10764 #define PWR_PUCRA_PA0_Msk (0x1UL << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */
10765 #define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Port PA0 Pull-Up set */
10766
10767 /******************** Bit definition for PWR_PDCRA register ********************/
10768 #define PWR_PDCRA_PA14_Pos (14U)
10769 #define PWR_PDCRA_PA14_Msk (0x1UL << PWR_PDCRA_PA14_Pos) /*!< 0x00004000 */
10770 #define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Port PA14 Pull-Down set */
10771 #define PWR_PDCRA_PA12_Pos (12U)
10772 #define PWR_PDCRA_PA12_Msk (0x1UL << PWR_PDCRA_PA12_Pos) /*!< 0x00001000 */
10773 #define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Port PA12 Pull-Down set */
10774 #define PWR_PDCRA_PA11_Pos (11U)
10775 #define PWR_PDCRA_PA11_Msk (0x1UL << PWR_PDCRA_PA11_Pos) /*!< 0x00000800 */
10776 #define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Port PA11 Pull-Down set */
10777 #define PWR_PDCRA_PA10_Pos (10U)
10778 #define PWR_PDCRA_PA10_Msk (0x1UL << PWR_PDCRA_PA10_Pos) /*!< 0x00000400 */
10779 #define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Port PA10 Pull-Down set */
10780 #define PWR_PDCRA_PA9_Pos (9U)
10781 #define PWR_PDCRA_PA9_Msk (0x1UL << PWR_PDCRA_PA9_Pos) /*!< 0x00000200 */
10782 #define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Port PA9 Pull-Down set */
10783 #define PWR_PDCRA_PA8_Pos (8U)
10784 #define PWR_PDCRA_PA8_Msk (0x1UL << PWR_PDCRA_PA8_Pos) /*!< 0x00000100 */
10785 #define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Port PA8 Pull-Down set */
10786 #define PWR_PDCRA_PA7_Pos (7U)
10787 #define PWR_PDCRA_PA7_Msk (0x1UL << PWR_PDCRA_PA7_Pos) /*!< 0x00000080 */
10788 #define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Port PA7 Pull-Down set */
10789 #define PWR_PDCRA_PA6_Pos (6U)
10790 #define PWR_PDCRA_PA6_Msk (0x1UL << PWR_PDCRA_PA6_Pos) /*!< 0x00000040 */
10791 #define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Port PA6 Pull-Down set */
10792 #define PWR_PDCRA_PA5_Pos (5U)
10793 #define PWR_PDCRA_PA5_Msk (0x1UL << PWR_PDCRA_PA5_Pos) /*!< 0x00000020 */
10794 #define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Port PA5 Pull-Down set */
10795 #define PWR_PDCRA_PA4_Pos (4U)
10796 #define PWR_PDCRA_PA4_Msk (0x1UL << PWR_PDCRA_PA4_Pos) /*!< 0x00000010 */
10797 #define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Port PA4 Pull-Down set */
10798 #define PWR_PDCRA_PA3_Pos (3U)
10799 #define PWR_PDCRA_PA3_Msk (0x1UL << PWR_PDCRA_PA3_Pos) /*!< 0x00000008 */
10800 #define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Port PA3 Pull-Down set */
10801 #define PWR_PDCRA_PA2_Pos (2U)
10802 #define PWR_PDCRA_PA2_Msk (0x1UL << PWR_PDCRA_PA2_Pos) /*!< 0x00000004 */
10803 #define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Port PA2 Pull-Down set */
10804 #define PWR_PDCRA_PA1_Pos (1U)
10805 #define PWR_PDCRA_PA1_Msk (0x1UL << PWR_PDCRA_PA1_Pos) /*!< 0x00000002 */
10806 #define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Port PA1 Pull-Down set */
10807 #define PWR_PDCRA_PA0_Pos (0U)
10808 #define PWR_PDCRA_PA0_Msk (0x1UL << PWR_PDCRA_PA0_Pos) /*!< 0x00000001 */
10809 #define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Port PA0 Pull-Down set */
10810
10811 /******************** Bit definition for PWR_PUCRB register ********************/
10812
10813 #define PWR_PUCRB_PB15_Pos (15U)
10814 #define PWR_PUCRB_PB15_Msk (0x1UL << PWR_PUCRB_PB15_Pos) /*!< 0x00008000 */
10815 #define PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk /*!< Port PB15 Pull-Up set */
10816 #define PWR_PUCRB_PB14_Pos (14U)
10817 #define PWR_PUCRB_PB14_Msk (0x1UL << PWR_PUCRB_PB14_Pos) /*!< 0x00004000 */
10818 #define PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk /*!< Port PB14 Pull-Up set */
10819 #define PWR_PUCRB_PB13_Pos (13U)
10820 #define PWR_PUCRB_PB13_Msk (0x1UL << PWR_PUCRB_PB13_Pos) /*!< 0x00002000 */
10821 #define PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk /*!< Port PB13 Pull-Up set */
10822 #define PWR_PUCRB_PB12_Pos (12U)
10823 #define PWR_PUCRB_PB12_Msk (0x1UL << PWR_PUCRB_PB12_Pos) /*!< 0x00001000 */
10824 #define PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk /*!< Port PB12 Pull-Up set */
10825 #define PWR_PUCRB_PB11_Pos (11U)
10826 #define PWR_PUCRB_PB11_Msk (0x1UL << PWR_PUCRB_PB11_Pos) /*!< 0x00000800 */
10827 #define PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk /*!< Port PB11 Pull-Up set */
10828 #define PWR_PUCRB_PB10_Pos (10U)
10829 #define PWR_PUCRB_PB10_Msk (0x1UL << PWR_PUCRB_PB10_Pos) /*!< 0x00000400 */
10830 #define PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk /*!< Port PB10 Pull-Up set */
10831 #define PWR_PUCRB_PB9_Pos (9U)
10832 #define PWR_PUCRB_PB9_Msk (0x1UL << PWR_PUCRB_PB9_Pos) /*!< 0x00000200 */
10833 #define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk /*!< Port PB9 Pull-Up set */
10834 #define PWR_PUCRB_PB8_Pos (8U)
10835 #define PWR_PUCRB_PB8_Msk (0x1UL << PWR_PUCRB_PB8_Pos) /*!< 0x00000100 */
10836 #define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk /*!< Port PB8 Pull-Up set */
10837 #define PWR_PUCRB_PB7_Pos (7U)
10838 #define PWR_PUCRB_PB7_Msk (0x1UL << PWR_PUCRB_PB7_Pos) /*!< 0x00000080 */
10839 #define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Port PB7 Pull-Up set */
10840 #define PWR_PUCRB_PB6_Pos (6U)
10841 #define PWR_PUCRB_PB6_Msk (0x1UL << PWR_PUCRB_PB6_Pos) /*!< 0x00000040 */
10842 #define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Port PB6 Pull-Up set */
10843 #define PWR_PUCRB_PB5_Pos (5U)
10844 #define PWR_PUCRB_PB5_Msk (0x1UL << PWR_PUCRB_PB5_Pos) /*!< 0x00000020 */
10845 #define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Port PB5 Pull-Up set */
10846 #define PWR_PUCRB_PB4_Pos (4U)
10847 #define PWR_PUCRB_PB4_Msk (0x1UL << PWR_PUCRB_PB4_Pos) /*!< 0x00000010 */
10848 #define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Port PB4 Pull-Up set */
10849 #define PWR_PUCRB_PB3_Pos (3U)
10850 #define PWR_PUCRB_PB3_Msk (0x1UL << PWR_PUCRB_PB3_Pos) /*!< 0x00000008 */
10851 #define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Port PB3 Pull-Up set */
10852 #define PWR_PUCRB_PB2_Pos (2U)
10853 #define PWR_PUCRB_PB2_Msk (0x1UL << PWR_PUCRB_PB2_Pos) /*!< 0x00000004 */
10854 #define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk /*!< Port PB2 Pull-Up set */
10855 #define PWR_PUCRB_PB1_Pos (1U)
10856 #define PWR_PUCRB_PB1_Msk (0x1UL << PWR_PUCRB_PB1_Pos) /*!< 0x00000002 */
10857 #define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Port PB1 Pull-Up set */
10858 #define PWR_PUCRB_PB0_Pos (0U)
10859 #define PWR_PUCRB_PB0_Msk (0x1UL << PWR_PUCRB_PB0_Pos) /*!< 0x00000001 */
10860 #define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Port PB0 Pull-Up set */
10861
10862 /******************** Bit definition for PWR_PDCRB register ********************/
10863 #define PWR_PDCRB_PB15_Pos (15U)
10864 #define PWR_PDCRB_PB15_Msk (0x1UL << PWR_PDCRB_PB15_Pos) /*!< 0x00008000 */
10865 #define PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk /*!< Port PB15 Pull-Down set */
10866 #define PWR_PDCRB_PB14_Pos (14U)
10867 #define PWR_PDCRB_PB14_Msk (0x1UL << PWR_PDCRB_PB14_Pos) /*!< 0x00004000 */
10868 #define PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk /*!< Port PB14 Pull-Down set */
10869 #define PWR_PDCRB_PB13_Pos (13U)
10870 #define PWR_PDCRB_PB13_Msk (0x1UL << PWR_PDCRB_PB13_Pos) /*!< 0x00002000 */
10871 #define PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk /*!< Port PB13 Pull-Down set */
10872 #define PWR_PDCRB_PB12_Pos (12U)
10873 #define PWR_PDCRB_PB12_Msk (0x1UL << PWR_PDCRB_PB12_Pos) /*!< 0x00001000 */
10874 #define PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk /*!< Port PB12 Pull-Down set */
10875 #define PWR_PDCRB_PB11_Pos (11U)
10876 #define PWR_PDCRB_PB11_Msk (0x1UL << PWR_PDCRB_PB11_Pos) /*!< 0x00000800 */
10877 #define PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk /*!< Port PB11 Pull-Down set */
10878 #define PWR_PDCRB_PB10_Pos (10U)
10879 #define PWR_PDCRB_PB10_Msk (0x1UL << PWR_PDCRB_PB10_Pos) /*!< 0x00000400 */
10880 #define PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk /*!< Port PB10 Pull-Down set */
10881 #define PWR_PDCRB_PB9_Pos (9U)
10882 #define PWR_PDCRB_PB9_Msk (0x1UL << PWR_PDCRB_PB9_Pos) /*!< 0x00000200 */
10883 #define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk /*!< Port PB9 Pull-Down set */
10884 #define PWR_PDCRB_PB8_Pos (8U)
10885 #define PWR_PDCRB_PB8_Msk (0x1UL << PWR_PDCRB_PB8_Pos) /*!< 0x00000100 */
10886 #define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk /*!< Port PB8 Pull-Down set */
10887 #define PWR_PDCRB_PB7_Pos (7U)
10888 #define PWR_PDCRB_PB7_Msk (0x1UL << PWR_PDCRB_PB7_Pos) /*!< 0x00000080 */
10889 #define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Port PB7 Pull-Down set */
10890 #define PWR_PDCRB_PB6_Pos (6U)
10891 #define PWR_PDCRB_PB6_Msk (0x1UL << PWR_PDCRB_PB6_Pos) /*!< 0x00000040 */
10892 #define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Port PB6 Pull-Down set */
10893 #define PWR_PDCRB_PB5_Pos (5U)
10894 #define PWR_PDCRB_PB5_Msk (0x1UL << PWR_PDCRB_PB5_Pos) /*!< 0x00000020 */
10895 #define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Port PB5 Pull-Down set */
10896 #define PWR_PDCRB_PB3_Pos (3U)
10897 #define PWR_PDCRB_PB3_Msk (0x1UL << PWR_PDCRB_PB3_Pos) /*!< 0x00000008 */
10898 #define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Port PB3 Pull-Down set */
10899 #define PWR_PDCRB_PB2_Pos (2U)
10900 #define PWR_PDCRB_PB2_Msk (0x1UL << PWR_PDCRB_PB2_Pos) /*!< 0x00000004 */
10901 #define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk /*!< Port PB2 Pull-Down set */
10902 #define PWR_PDCRB_PB1_Pos (1U)
10903 #define PWR_PDCRB_PB1_Msk (0x1UL << PWR_PDCRB_PB1_Pos) /*!< 0x00000002 */
10904 #define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Port PB1 Pull-Down set */
10905 #define PWR_PDCRB_PB0_Pos (0U)
10906 #define PWR_PDCRB_PB0_Msk (0x1UL << PWR_PDCRB_PB0_Pos) /*!< 0x00000001 */
10907 #define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Port PB0 Pull-Down set */
10908
10909 /******************** Bit definition for PWR_PUCRC register ********************/
10910 #define PWR_PUCRC_PC15_Pos (15U)
10911 #define PWR_PUCRC_PC15_Msk (0x1UL << PWR_PUCRC_PC15_Pos) /*!< 0x00008000 */
10912 #define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Port PC15 Pull-Up set */
10913 #define PWR_PUCRC_PC14_Pos (14U)
10914 #define PWR_PUCRC_PC14_Msk (0x1UL << PWR_PUCRC_PC14_Pos) /*!< 0x00004000 */
10915 #define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Port PC14 Pull-Up set */
10916 #define PWR_PUCRC_PC13_Pos (13U)
10917 #define PWR_PUCRC_PC13_Msk (0x1UL << PWR_PUCRC_PC13_Pos) /*!< 0x00002000 */
10918 #define PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk /*!< Port PC13 Pull-Up set */
10919 #define PWR_PUCRC_PC12_Pos (12U)
10920 #define PWR_PUCRC_PC12_Msk (0x1UL << PWR_PUCRC_PC12_Pos) /*!< 0x00001000 */
10921 #define PWR_PUCRC_PC12 PWR_PUCRC_PC12_Msk /*!< Port PC12 Pull-Up set */
10922 #define PWR_PUCRC_PC11_Pos (11U)
10923 #define PWR_PUCRC_PC11_Msk (0x1UL << PWR_PUCRC_PC11_Pos) /*!< 0x00000800 */
10924 #define PWR_PUCRC_PC11 PWR_PUCRC_PC11_Msk /*!< Port PC11 Pull-Up set */
10925 #define PWR_PUCRC_PC10_Pos (10U)
10926 #define PWR_PUCRC_PC10_Msk (0x1UL << PWR_PUCRC_PC10_Pos) /*!< 0x00000400 */
10927 #define PWR_PUCRC_PC10 PWR_PUCRC_PC10_Msk /*!< Port PC10 Pull-Up set */
10928 #define PWR_PUCRC_PC9_Pos (9U)
10929 #define PWR_PUCRC_PC9_Msk (0x1UL << PWR_PUCRC_PC9_Pos) /*!< 0x00000200 */
10930 #define PWR_PUCRC_PC9 PWR_PUCRC_PC9_Msk /*!< Port PC9 Pull-Up set */
10931 #define PWR_PUCRC_PC8_Pos (8U)
10932 #define PWR_PUCRC_PC8_Msk (0x1UL << PWR_PUCRC_PC8_Pos) /*!< 0x00000100 */
10933 #define PWR_PUCRC_PC8 PWR_PUCRC_PC8_Msk /*!< Port PC8 Pull-Up set */
10934 #define PWR_PUCRC_PC7_Pos (7U)
10935 #define PWR_PUCRC_PC7_Msk (0x1UL << PWR_PUCRC_PC7_Pos) /*!< 0x00000080 */
10936 #define PWR_PUCRC_PC7 PWR_PUCRC_PC7_Msk /*!< Port PC7 Pull-Up set */
10937 #define PWR_PUCRC_PC6_Pos (6U)
10938 #define PWR_PUCRC_PC6_Msk (0x1UL << PWR_PUCRC_PC6_Pos) /*!< 0x00000040 */
10939 #define PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk /*!< Port PC6 Pull-Up set */
10940 #define PWR_PUCRC_PC5_Pos (5U)
10941 #define PWR_PUCRC_PC5_Msk (0x1UL << PWR_PUCRC_PC5_Pos) /*!< 0x00000020 */
10942 #define PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk /*!< Port PC5 Pull-Up set */
10943 #define PWR_PUCRC_PC4_Pos (4U)
10944 #define PWR_PUCRC_PC4_Msk (0x1UL << PWR_PUCRC_PC4_Pos) /*!< 0x00000010 */
10945 #define PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk /*!< Port PC4 Pull-Up set */
10946 #define PWR_PUCRC_PC3_Pos (3U)
10947 #define PWR_PUCRC_PC3_Msk (0x1UL << PWR_PUCRC_PC3_Pos) /*!< 0x00000008 */
10948 #define PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk /*!< Port PC3 Pull-Up set */
10949 #define PWR_PUCRC_PC2_Pos (2U)
10950 #define PWR_PUCRC_PC2_Msk (0x1UL << PWR_PUCRC_PC2_Pos) /*!< 0x00000004 */
10951 #define PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk /*!< Port PC2 Pull-Up set */
10952 #define PWR_PUCRC_PC1_Pos (1U)
10953 #define PWR_PUCRC_PC1_Msk (0x1UL << PWR_PUCRC_PC1_Pos) /*!< 0x00000002 */
10954 #define PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk /*!< Port PC1 Pull-Up set */
10955 #define PWR_PUCRC_PC0_Pos (0U)
10956 #define PWR_PUCRC_PC0_Msk (0x1UL << PWR_PUCRC_PC0_Pos) /*!< 0x00000001 */
10957 #define PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk /*!< Port PC0 Pull-Up set */
10958
10959 /******************** Bit definition for PWR_PDCRC register ********************/
10960 #define PWR_PDCRC_PC15_Pos (15U)
10961 #define PWR_PDCRC_PC15_Msk (0x1UL << PWR_PDCRC_PC15_Pos) /*!< 0x00008000 */
10962 #define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Port PC15 Pull-Down set */
10963 #define PWR_PDCRC_PC14_Pos (14U)
10964 #define PWR_PDCRC_PC14_Msk (0x1UL << PWR_PDCRC_PC14_Pos) /*!< 0x00004000 */
10965 #define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Port PC14 Pull-Down set */
10966 #define PWR_PDCRC_PC13_Pos (13U)
10967 #define PWR_PDCRC_PC13_Msk (0x1UL << PWR_PDCRC_PC13_Pos) /*!< 0x00002000 */
10968 #define PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk /*!< Port PC13 Pull-Down set */
10969 #define PWR_PDCRC_PC12_Pos (12U)
10970 #define PWR_PDCRC_PC12_Msk (0x1UL << PWR_PDCRC_PC12_Pos) /*!< 0x00001000 */
10971 #define PWR_PDCRC_PC12 PWR_PDCRC_PC12_Msk /*!< Port PC12 Pull-Down set */
10972 #define PWR_PDCRC_PC11_Pos (11U)
10973 #define PWR_PDCRC_PC11_Msk (0x1UL << PWR_PDCRC_PC11_Pos) /*!< 0x00000800 */
10974 #define PWR_PDCRC_PC11 PWR_PDCRC_PC11_Msk /*!< Port PC11 Pull-Down set */
10975 #define PWR_PDCRC_PC10_Pos (10U)
10976 #define PWR_PDCRC_PC10_Msk (0x1UL << PWR_PDCRC_PC10_Pos) /*!< 0x00000400 */
10977 #define PWR_PDCRC_PC10 PWR_PDCRC_PC10_Msk /*!< Port PC10 Pull-Down set */
10978 #define PWR_PDCRC_PC9_Pos (9U)
10979 #define PWR_PDCRC_PC9_Msk (0x1UL << PWR_PDCRC_PC9_Pos) /*!< 0x00000200 */
10980 #define PWR_PDCRC_PC9 PWR_PDCRC_PC9_Msk /*!< Port PC9 Pull-Down set */
10981 #define PWR_PDCRC_PC8_Pos (8U)
10982 #define PWR_PDCRC_PC8_Msk (0x1UL << PWR_PDCRC_PC8_Pos) /*!< 0x00000100 */
10983 #define PWR_PDCRC_PC8 PWR_PDCRC_PC8_Msk /*!< Port PC8 Pull-Down set */
10984 #define PWR_PDCRC_PC7_Pos (7U)
10985 #define PWR_PDCRC_PC7_Msk (0x1UL << PWR_PDCRC_PC7_Pos) /*!< 0x00000080 */
10986 #define PWR_PDCRC_PC7 PWR_PDCRC_PC7_Msk /*!< Port PC7 Pull-Down set */
10987 #define PWR_PDCRC_PC6_Pos (6U)
10988 #define PWR_PDCRC_PC6_Msk (0x1UL << PWR_PDCRC_PC6_Pos) /*!< 0x00000040 */
10989 #define PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk /*!< Port PC6 Pull-Down set */
10990 #define PWR_PDCRC_PC5_Pos (5U)
10991 #define PWR_PDCRC_PC5_Msk (0x1UL << PWR_PDCRC_PC5_Pos) /*!< 0x00000020 */
10992 #define PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk /*!< Port PC5 Pull-Down set */
10993 #define PWR_PDCRC_PC4_Pos (4U)
10994 #define PWR_PDCRC_PC4_Msk (0x1UL << PWR_PDCRC_PC4_Pos) /*!< 0x00000010 */
10995 #define PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk /*!< Port PC4 Pull-Down set */
10996 #define PWR_PDCRC_PC3_Pos (3U)
10997 #define PWR_PDCRC_PC3_Msk (0x1UL << PWR_PDCRC_PC3_Pos) /*!< 0x00000008 */
10998 #define PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk /*!< Port PC3 Pull-Down set */
10999 #define PWR_PDCRC_PC2_Pos (2U)
11000 #define PWR_PDCRC_PC2_Msk (0x1UL << PWR_PDCRC_PC2_Pos) /*!< 0x00000004 */
11001 #define PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk /*!< Port PC2 Pull-Down set */
11002 #define PWR_PDCRC_PC1_Pos (1U)
11003 #define PWR_PDCRC_PC1_Msk (0x1UL << PWR_PDCRC_PC1_Pos) /*!< 0x00000002 */
11004 #define PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk /*!< Port PC1 Pull-Down set */
11005 #define PWR_PDCRC_PC0_Pos (0U)
11006 #define PWR_PDCRC_PC0_Msk (0x1UL << PWR_PDCRC_PC0_Pos) /*!< 0x00000001 */
11007 #define PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk /*!< Port PC0 Pull-Down set */
11008
11009 /******************** Bit definition for PWR_PUCRD register ********************/
11010 #define PWR_PUCRD_PD15_Pos (15U)
11011 #define PWR_PUCRD_PD15_Msk (0x1UL << PWR_PUCRD_PD15_Pos) /*!< 0x00008000 */
11012 #define PWR_PUCRD_PD15 PWR_PUCRD_PD15_Msk /*!< Port PD15 Pull-Up set */
11013 #define PWR_PUCRD_PD14_Pos (14U)
11014 #define PWR_PUCRD_PD14_Msk (0x1UL << PWR_PUCRD_PD14_Pos) /*!< 0x00004000 */
11015 #define PWR_PUCRD_PD14 PWR_PUCRD_PD14_Msk /*!< Port PD14 Pull-Up set */
11016 #define PWR_PUCRD_PD13_Pos (13U)
11017 #define PWR_PUCRD_PD13_Msk (0x1UL << PWR_PUCRD_PD13_Pos) /*!< 0x00002000 */
11018 #define PWR_PUCRD_PD13 PWR_PUCRD_PD13_Msk /*!< Port PD13 Pull-Up set */
11019 #define PWR_PUCRD_PD12_Pos (12U)
11020 #define PWR_PUCRD_PD12_Msk (0x1UL << PWR_PUCRD_PD12_Pos) /*!< 0x00001000 */
11021 #define PWR_PUCRD_PD12 PWR_PUCRD_PD12_Msk /*!< Port PD12 Pull-Up set */
11022 #define PWR_PUCRD_PD11_Pos (11U)
11023 #define PWR_PUCRD_PD11_Msk (0x1UL << PWR_PUCRD_PD11_Pos) /*!< 0x00000800 */
11024 #define PWR_PUCRD_PD11 PWR_PUCRD_PD11_Msk /*!< Port PD11 Pull-Up set */
11025 #define PWR_PUCRD_PD10_Pos (10U)
11026 #define PWR_PUCRD_PD10_Msk (0x1UL << PWR_PUCRD_PD10_Pos) /*!< 0x00000400 */
11027 #define PWR_PUCRD_PD10 PWR_PUCRD_PD10_Msk /*!< Port PD10 Pull-Up set */
11028 #define PWR_PUCRD_PD9_Pos (9U)
11029 #define PWR_PUCRD_PD9_Msk (0x1UL << PWR_PUCRD_PD9_Pos) /*!< 0x00000200 */
11030 #define PWR_PUCRD_PD9 PWR_PUCRD_PD9_Msk /*!< Port PD9 Pull-Up set */
11031 #define PWR_PUCRD_PD8_Pos (8U)
11032 #define PWR_PUCRD_PD8_Msk (0x1UL << PWR_PUCRD_PD8_Pos) /*!< 0x00000100 */
11033 #define PWR_PUCRD_PD8 PWR_PUCRD_PD8_Msk /*!< Port PD8 Pull-Up set */
11034 #define PWR_PUCRD_PD7_Pos (7U)
11035 #define PWR_PUCRD_PD7_Msk (0x1UL << PWR_PUCRD_PD7_Pos) /*!< 0x00000080 */
11036 #define PWR_PUCRD_PD7 PWR_PUCRD_PD7_Msk /*!< Port PD7 Pull-Up set */
11037 #define PWR_PUCRD_PD6_Pos (6U)
11038 #define PWR_PUCRD_PD6_Msk (0x1UL << PWR_PUCRD_PD6_Pos) /*!< 0x00000040 */
11039 #define PWR_PUCRD_PD6 PWR_PUCRD_PD6_Msk /*!< Port PD6 Pull-Up set */
11040 #define PWR_PUCRD_PD5_Pos (5U)
11041 #define PWR_PUCRD_PD5_Msk (0x1UL << PWR_PUCRD_PD5_Pos) /*!< 0x00000020 */
11042 #define PWR_PUCRD_PD5 PWR_PUCRD_PD5_Msk /*!< Port PD5 Pull-Up set */
11043 #define PWR_PUCRD_PD4_Pos (4U)
11044 #define PWR_PUCRD_PD4_Msk (0x1UL << PWR_PUCRD_PD4_Pos) /*!< 0x00000010 */
11045 #define PWR_PUCRD_PD4 PWR_PUCRD_PD4_Msk /*!< Port PD4 Pull-Up set */
11046 #define PWR_PUCRD_PD3_Pos (3U)
11047 #define PWR_PUCRD_PD3_Msk (0x1UL << PWR_PUCRD_PD3_Pos) /*!< 0x00000008 */
11048 #define PWR_PUCRD_PD3 PWR_PUCRD_PD3_Msk /*!< Port PD3 Pull-Up set */
11049 #define PWR_PUCRD_PD2_Pos (2U)
11050 #define PWR_PUCRD_PD2_Msk (0x1UL << PWR_PUCRD_PD2_Pos) /*!< 0x00000004 */
11051 #define PWR_PUCRD_PD2 PWR_PUCRD_PD2_Msk /*!< Port PD2 Pull-Up set */
11052 #define PWR_PUCRD_PD1_Pos (1U)
11053 #define PWR_PUCRD_PD1_Msk (0x1UL << PWR_PUCRD_PD1_Pos) /*!< 0x00000002 */
11054 #define PWR_PUCRD_PD1 PWR_PUCRD_PD1_Msk /*!< Port PD1 Pull-Up set */
11055 #define PWR_PUCRD_PD0_Pos (0U)
11056 #define PWR_PUCRD_PD0_Msk (0x1UL << PWR_PUCRD_PD0_Pos) /*!< 0x00000001 */
11057 #define PWR_PUCRD_PD0 PWR_PUCRD_PD0_Msk /*!< Port PD0 Pull-Up set */
11058
11059 /******************** Bit definition for PWR_PDCRD register ********************/
11060 #define PWR_PDCRD_PD15_Pos (15U)
11061 #define PWR_PDCRD_PD15_Msk (0x1UL << PWR_PDCRD_PD15_Pos) /*!< 0x00008000 */
11062 #define PWR_PDCRD_PD15 PWR_PDCRD_PD15_Msk /*!< Port PD15 Pull-Down set */
11063 #define PWR_PDCRD_PD14_Pos (14U)
11064 #define PWR_PDCRD_PD14_Msk (0x1UL << PWR_PDCRD_PD14_Pos) /*!< 0x00004000 */
11065 #define PWR_PDCRD_PD14 PWR_PDCRD_PD14_Msk /*!< Port PD14 Pull-Down set */
11066 #define PWR_PDCRD_PD13_Pos (13U)
11067 #define PWR_PDCRD_PD13_Msk (0x1UL << PWR_PDCRD_PD13_Pos) /*!< 0x00002000 */
11068 #define PWR_PDCRD_PD13 PWR_PDCRD_PD13_Msk /*!< Port PD13 Pull-Down set */
11069 #define PWR_PDCRD_PD12_Pos (12U)
11070 #define PWR_PDCRD_PD12_Msk (0x1UL << PWR_PDCRD_PD12_Pos) /*!< 0x00001000 */
11071 #define PWR_PDCRD_PD12 PWR_PDCRD_PD12_Msk /*!< Port PD12 Pull-Down set */
11072 #define PWR_PDCRD_PD11_Pos (11U)
11073 #define PWR_PDCRD_PD11_Msk (0x1UL << PWR_PDCRD_PD11_Pos) /*!< 0x00000800 */
11074 #define PWR_PDCRD_PD11 PWR_PDCRD_PD11_Msk /*!< Port PD11 Pull-Down set */
11075 #define PWR_PDCRD_PD10_Pos (10U)
11076 #define PWR_PDCRD_PD10_Msk (0x1UL << PWR_PDCRD_PD10_Pos) /*!< 0x00000400 */
11077 #define PWR_PDCRD_PD10 PWR_PDCRD_PD10_Msk /*!< Port PD10 Pull-Down set */
11078 #define PWR_PDCRD_PD9_Pos (9U)
11079 #define PWR_PDCRD_PD9_Msk (0x1UL << PWR_PDCRD_PD9_Pos) /*!< 0x00000200 */
11080 #define PWR_PDCRD_PD9 PWR_PDCRD_PD9_Msk /*!< Port PD9 Pull-Down set */
11081 #define PWR_PDCRD_PD8_Pos (8U)
11082 #define PWR_PDCRD_PD8_Msk (0x1UL << PWR_PDCRD_PD8_Pos) /*!< 0x00000100 */
11083 #define PWR_PDCRD_PD8 PWR_PDCRD_PD8_Msk /*!< Port PD8 Pull-Down set */
11084 #define PWR_PDCRD_PD7_Pos (7U)
11085 #define PWR_PDCRD_PD7_Msk (0x1UL << PWR_PDCRD_PD7_Pos) /*!< 0x00000080 */
11086 #define PWR_PDCRD_PD7 PWR_PDCRD_PD7_Msk /*!< Port PD7 Pull-Down set */
11087 #define PWR_PDCRD_PD6_Pos (6U)
11088 #define PWR_PDCRD_PD6_Msk (0x1UL << PWR_PDCRD_PD6_Pos) /*!< 0x00000040 */
11089 #define PWR_PDCRD_PD6 PWR_PDCRD_PD6_Msk /*!< Port PD6 Pull-Down set */
11090 #define PWR_PDCRD_PD5_Pos (5U)
11091 #define PWR_PDCRD_PD5_Msk (0x1UL << PWR_PDCRD_PD5_Pos) /*!< 0x00000020 */
11092 #define PWR_PDCRD_PD5 PWR_PDCRD_PD5_Msk /*!< Port PD5 Pull-Down set */
11093 #define PWR_PDCRD_PD4_Pos (4U)
11094 #define PWR_PDCRD_PD4_Msk (0x1UL << PWR_PDCRD_PD4_Pos) /*!< 0x00000010 */
11095 #define PWR_PDCRD_PD4 PWR_PDCRD_PD4_Msk /*!< Port PD4 Pull-Down set */
11096 #define PWR_PDCRD_PD3_Pos (3U)
11097 #define PWR_PDCRD_PD3_Msk (0x1UL << PWR_PDCRD_PD3_Pos) /*!< 0x00000008 */
11098 #define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk /*!< Port PD3 Pull-Down set */
11099 #define PWR_PDCRD_PD2_Pos (2U)
11100 #define PWR_PDCRD_PD2_Msk (0x1UL << PWR_PDCRD_PD2_Pos) /*!< 0x00000004 */
11101 #define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk /*!< Port PD2 Pull-Down set */
11102 #define PWR_PDCRD_PD1_Pos (1U)
11103 #define PWR_PDCRD_PD1_Msk (0x1UL << PWR_PDCRD_PD1_Pos) /*!< 0x00000002 */
11104 #define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk /*!< Port PD1 Pull-Down set */
11105 #define PWR_PDCRD_PD0_Pos (0U)
11106 #define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */
11107 #define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk /*!< Port PD0 Pull-Down set */
11108
11109 /******************** Bit definition for PWR_PUCRE register ********************/
11110 #define PWR_PUCRE_PE15_Pos (15U)
11111 #define PWR_PUCRE_PE15_Msk (0x1UL << PWR_PUCRE_PE15_Pos) /*!< 0x00008000 */
11112 #define PWR_PUCRE_PE15 PWR_PUCRE_PE15_Msk /*!< Port PE15 Pull-Up set */
11113 #define PWR_PUCRE_PE14_Pos (14U)
11114 #define PWR_PUCRE_PE14_Msk (0x1UL << PWR_PUCRE_PE14_Pos) /*!< 0x00004000 */
11115 #define PWR_PUCRE_PE14 PWR_PUCRE_PE14_Msk /*!< Port PE14 Pull-Up set */
11116 #define PWR_PUCRE_PE13_Pos (13U)
11117 #define PWR_PUCRE_PE13_Msk (0x1UL << PWR_PUCRE_PE13_Pos) /*!< 0x00002000 */
11118 #define PWR_PUCRE_PE13 PWR_PUCRE_PE13_Msk /*!< Port PE13 Pull-Up set */
11119 #define PWR_PUCRE_PE12_Pos (12U)
11120 #define PWR_PUCRE_PE12_Msk (0x1UL << PWR_PUCRE_PE12_Pos) /*!< 0x00001000 */
11121 #define PWR_PUCRE_PE12 PWR_PUCRE_PE12_Msk /*!< Port PE12 Pull-Up set */
11122 #define PWR_PUCRE_PE11_Pos (11U)
11123 #define PWR_PUCRE_PE11_Msk (0x1UL << PWR_PUCRE_PE11_Pos) /*!< 0x00000800 */
11124 #define PWR_PUCRE_PE11 PWR_PUCRE_PE11_Msk /*!< Port PE11 Pull-Up set */
11125 #define PWR_PUCRE_PE10_Pos (10U)
11126 #define PWR_PUCRE_PE10_Msk (0x1UL << PWR_PUCRE_PE10_Pos) /*!< 0x00000400 */
11127 #define PWR_PUCRE_PE10 PWR_PUCRE_PE10_Msk /*!< Port PE10 Pull-Up set */
11128 #define PWR_PUCRE_PE9_Pos (9U)
11129 #define PWR_PUCRE_PE9_Msk (0x1UL << PWR_PUCRE_PE9_Pos) /*!< 0x00000200 */
11130 #define PWR_PUCRE_PE9 PWR_PUCRE_PE9_Msk /*!< Port PE9 Pull-Up set */
11131 #define PWR_PUCRE_PE8_Pos (8U)
11132 #define PWR_PUCRE_PE8_Msk (0x1UL << PWR_PUCRE_PE8_Pos) /*!< 0x00000100 */
11133 #define PWR_PUCRE_PE8 PWR_PUCRE_PE8_Msk /*!< Port PE8 Pull-Up set */
11134 #define PWR_PUCRE_PE7_Pos (7U)
11135 #define PWR_PUCRE_PE7_Msk (0x1UL << PWR_PUCRE_PE7_Pos) /*!< 0x00000080 */
11136 #define PWR_PUCRE_PE7 PWR_PUCRE_PE7_Msk /*!< Port PE7 Pull-Up set */
11137 #define PWR_PUCRE_PE6_Pos (6U)
11138 #define PWR_PUCRE_PE6_Msk (0x1UL << PWR_PUCRE_PE6_Pos) /*!< 0x00000040 */
11139 #define PWR_PUCRE_PE6 PWR_PUCRE_PE6_Msk /*!< Port PE6 Pull-Up set */
11140 #define PWR_PUCRE_PE5_Pos (5U)
11141 #define PWR_PUCRE_PE5_Msk (0x1UL << PWR_PUCRE_PE5_Pos) /*!< 0x00000020 */
11142 #define PWR_PUCRE_PE5 PWR_PUCRE_PE5_Msk /*!< Port PE5 Pull-Up set */
11143 #define PWR_PUCRE_PE4_Pos (4U)
11144 #define PWR_PUCRE_PE4_Msk (0x1UL << PWR_PUCRE_PE4_Pos) /*!< 0x00000010 */
11145 #define PWR_PUCRE_PE4 PWR_PUCRE_PE4_Msk /*!< Port PE4 Pull-Up set */
11146 #define PWR_PUCRE_PE3_Pos (3U)
11147 #define PWR_PUCRE_PE3_Msk (0x1UL << PWR_PUCRE_PE3_Pos) /*!< 0x00000008 */
11148 #define PWR_PUCRE_PE3 PWR_PUCRE_PE3_Msk /*!< Port PE3 Pull-Up set */
11149 #define PWR_PUCRE_PE2_Pos (2U)
11150 #define PWR_PUCRE_PE2_Msk (0x1UL << PWR_PUCRE_PE2_Pos) /*!< 0x00000004 */
11151 #define PWR_PUCRE_PE2 PWR_PUCRE_PE2_Msk /*!< Port PE2 Pull-Up set */
11152 #define PWR_PUCRE_PE1_Pos (1U)
11153 #define PWR_PUCRE_PE1_Msk (0x1UL << PWR_PUCRE_PE1_Pos) /*!< 0x00000002 */
11154 #define PWR_PUCRE_PE1 PWR_PUCRE_PE1_Msk /*!< Port PE1 Pull-Up set */
11155 #define PWR_PUCRE_PE0_Pos (0U)
11156 #define PWR_PUCRE_PE0_Msk (0x1UL << PWR_PUCRE_PE0_Pos) /*!< 0x00000001 */
11157 #define PWR_PUCRE_PE0 PWR_PUCRE_PE0_Msk /*!< Port PE0 Pull-Up set */
11158
11159 /******************** Bit definition for PWR_PDCRE register ********************/
11160 #define PWR_PDCRE_PE15_Pos (15U)
11161 #define PWR_PDCRE_PE15_Msk (0x1UL << PWR_PDCRE_PE15_Pos) /*!< 0x00008000 */
11162 #define PWR_PDCRE_PE15 PWR_PDCRE_PE15_Msk /*!< Port PE15 Pull-Down set */
11163 #define PWR_PDCRE_PE14_Pos (14U)
11164 #define PWR_PDCRE_PE14_Msk (0x1UL << PWR_PDCRE_PE14_Pos) /*!< 0x00004000 */
11165 #define PWR_PDCRE_PE14 PWR_PDCRE_PE14_Msk /*!< Port PE14 Pull-Down set */
11166 #define PWR_PDCRE_PE13_Pos (13U)
11167 #define PWR_PDCRE_PE13_Msk (0x1UL << PWR_PDCRE_PE13_Pos) /*!< 0x00002000 */
11168 #define PWR_PDCRE_PE13 PWR_PDCRE_PE13_Msk /*!< Port PE13 Pull-Down set */
11169 #define PWR_PDCRE_PE12_Pos (12U)
11170 #define PWR_PDCRE_PE12_Msk (0x1UL << PWR_PDCRE_PE12_Pos) /*!< 0x00001000 */
11171 #define PWR_PDCRE_PE12 PWR_PDCRE_PE12_Msk /*!< Port PE12 Pull-Down set */
11172 #define PWR_PDCRE_PE11_Pos (11U)
11173 #define PWR_PDCRE_PE11_Msk (0x1UL << PWR_PDCRE_PE11_Pos) /*!< 0x00000800 */
11174 #define PWR_PDCRE_PE11 PWR_PDCRE_PE11_Msk /*!< Port PE11 Pull-Down set */
11175 #define PWR_PDCRE_PE10_Pos (10U)
11176 #define PWR_PDCRE_PE10_Msk (0x1UL << PWR_PDCRE_PE10_Pos) /*!< 0x00000400 */
11177 #define PWR_PDCRE_PE10 PWR_PDCRE_PE10_Msk /*!< Port PE10 Pull-Down set */
11178 #define PWR_PDCRE_PE9_Pos (9U)
11179 #define PWR_PDCRE_PE9_Msk (0x1UL << PWR_PDCRE_PE9_Pos) /*!< 0x00000200 */
11180 #define PWR_PDCRE_PE9 PWR_PDCRE_PE9_Msk /*!< Port PE9 Pull-Down set */
11181 #define PWR_PDCRE_PE8_Pos (8U)
11182 #define PWR_PDCRE_PE8_Msk (0x1UL << PWR_PDCRE_PE8_Pos) /*!< 0x00000100 */
11183 #define PWR_PDCRE_PE8 PWR_PDCRE_PE8_Msk /*!< Port PE8 Pull-Down set */
11184 #define PWR_PDCRE_PE7_Pos (7U)
11185 #define PWR_PDCRE_PE7_Msk (0x1UL << PWR_PDCRE_PE7_Pos) /*!< 0x00000080 */
11186 #define PWR_PDCRE_PE7 PWR_PDCRE_PE7_Msk /*!< Port PE7 Pull-Down set */
11187 #define PWR_PDCRE_PE6_Pos (6U)
11188 #define PWR_PDCRE_PE6_Msk (0x1UL << PWR_PDCRE_PE6_Pos) /*!< 0x00000040 */
11189 #define PWR_PDCRE_PE6 PWR_PDCRE_PE6_Msk /*!< Port PE6 Pull-Down set */
11190 #define PWR_PDCRE_PE5_Pos (5U)
11191 #define PWR_PDCRE_PE5_Msk (0x1UL << PWR_PDCRE_PE5_Pos) /*!< 0x00000020 */
11192 #define PWR_PDCRE_PE5 PWR_PDCRE_PE5_Msk /*!< Port PE5 Pull-Down set */
11193 #define PWR_PDCRE_PE4_Pos (4U)
11194 #define PWR_PDCRE_PE4_Msk (0x1UL << PWR_PDCRE_PE4_Pos) /*!< 0x00000010 */
11195 #define PWR_PDCRE_PE4 PWR_PDCRE_PE4_Msk /*!< Port PE4 Pull-Down set */
11196 #define PWR_PDCRE_PE3_Pos (3U)
11197 #define PWR_PDCRE_PE3_Msk (0x1UL << PWR_PDCRE_PE3_Pos) /*!< 0x00000008 */
11198 #define PWR_PDCRE_PE3 PWR_PDCRE_PE3_Msk /*!< Port PE3 Pull-Down set */
11199 #define PWR_PDCRE_PE2_Pos (2U)
11200 #define PWR_PDCRE_PE2_Msk (0x1UL << PWR_PDCRE_PE2_Pos) /*!< 0x00000004 */
11201 #define PWR_PDCRE_PE2 PWR_PDCRE_PE2_Msk /*!< Port PE2 Pull-Down set */
11202 #define PWR_PDCRE_PE1_Pos (1U)
11203 #define PWR_PDCRE_PE1_Msk (0x1UL << PWR_PDCRE_PE1_Pos) /*!< 0x00000002 */
11204 #define PWR_PDCRE_PE1 PWR_PDCRE_PE1_Msk /*!< Port PE1 Pull-Down set */
11205 #define PWR_PDCRE_PE0_Pos (0U)
11206 #define PWR_PDCRE_PE0_Msk (0x1UL << PWR_PDCRE_PE0_Pos) /*!< 0x00000001 */
11207 #define PWR_PDCRE_PE0 PWR_PDCRE_PE0_Msk /*!< Port PE0 Pull-Down set */
11208
11209 /******************** Bit definition for PWR_PUCRF register ********************/
11210 #define PWR_PUCRF_PF15_Pos (15U)
11211 #define PWR_PUCRF_PF15_Msk (0x1UL << PWR_PUCRF_PF15_Pos) /*!< 0x00008000 */
11212 #define PWR_PUCRF_PF15 PWR_PUCRF_PF15_Msk /*!< Port PF15 Pull-Up set */
11213 #define PWR_PUCRF_PF14_Pos (14U)
11214 #define PWR_PUCRF_PF14_Msk (0x1UL << PWR_PUCRF_PF14_Pos) /*!< 0x00004000 */
11215 #define PWR_PUCRF_PF14 PWR_PUCRF_PF14_Msk /*!< Port PF14 Pull-Up set */
11216 #define PWR_PUCRF_PF13_Pos (13U)
11217 #define PWR_PUCRF_PF13_Msk (0x1UL << PWR_PUCRF_PF13_Pos) /*!< 0x00002000 */
11218 #define PWR_PUCRF_PF13 PWR_PUCRF_PF13_Msk /*!< Port PF13 Pull-Up set */
11219 #define PWR_PUCRF_PF12_Pos (12U)
11220 #define PWR_PUCRF_PF12_Msk (0x1UL << PWR_PUCRF_PF12_Pos) /*!< 0x00001000 */
11221 #define PWR_PUCRF_PF12 PWR_PUCRF_PF12_Msk /*!< Port PF12 Pull-Up set */
11222 #define PWR_PUCRF_PF11_Pos (11U)
11223 #define PWR_PUCRF_PF11_Msk (0x1UL << PWR_PUCRF_PF11_Pos) /*!< 0x00000800 */
11224 #define PWR_PUCRF_PF11 PWR_PUCRF_PF11_Msk /*!< Port PF11 Pull-Up set */
11225 #define PWR_PUCRF_PF10_Pos (10U)
11226 #define PWR_PUCRF_PF10_Msk (0x1UL << PWR_PUCRF_PF10_Pos) /*!< 0x00000400 */
11227 #define PWR_PUCRF_PF10 PWR_PUCRF_PF10_Msk /*!< Port PF10 Pull-Up set */
11228 #define PWR_PUCRF_PF9_Pos (9U)
11229 #define PWR_PUCRF_PF9_Msk (0x1UL << PWR_PUCRF_PF9_Pos) /*!< 0x00000200 */
11230 #define PWR_PUCRF_PF9 PWR_PUCRF_PF9_Msk /*!< Port PF9 Pull-Up set */
11231 #define PWR_PUCRF_PF8_Pos (8U)
11232 #define PWR_PUCRF_PF8_Msk (0x1UL << PWR_PUCRF_PF8_Pos) /*!< 0x00000100 */
11233 #define PWR_PUCRF_PF8 PWR_PUCRF_PF8_Msk /*!< Port PF8 Pull-Up set */
11234 #define PWR_PUCRF_PF7_Pos (7U)
11235 #define PWR_PUCRF_PF7_Msk (0x1UL << PWR_PUCRF_PF7_Pos) /*!< 0x00000080 */
11236 #define PWR_PUCRF_PF7 PWR_PUCRF_PF7_Msk /*!< Port PF7 Pull-Up set */
11237 #define PWR_PUCRF_PF6_Pos (6U)
11238 #define PWR_PUCRF_PF6_Msk (0x1UL << PWR_PUCRF_PF6_Pos) /*!< 0x00000040 */
11239 #define PWR_PUCRF_PF6 PWR_PUCRF_PF6_Msk /*!< Port PF6 Pull-Up set */
11240 #define PWR_PUCRF_PF5_Pos (5U)
11241 #define PWR_PUCRF_PF5_Msk (0x1UL << PWR_PUCRF_PF5_Pos) /*!< 0x00000020 */
11242 #define PWR_PUCRF_PF5 PWR_PUCRF_PF5_Msk /*!< Port PF5 Pull-Up set */
11243 #define PWR_PUCRF_PF4_Pos (4U)
11244 #define PWR_PUCRF_PF4_Msk (0x1UL << PWR_PUCRF_PF4_Pos) /*!< 0x00000010 */
11245 #define PWR_PUCRF_PF4 PWR_PUCRF_PF4_Msk /*!< Port PF4 Pull-Up set */
11246 #define PWR_PUCRF_PF3_Pos (3U)
11247 #define PWR_PUCRF_PF3_Msk (0x1UL << PWR_PUCRF_PF3_Pos) /*!< 0x00000008 */
11248 #define PWR_PUCRF_PF3 PWR_PUCRF_PF3_Msk /*!< Port PF3 Pull-Up set */
11249 #define PWR_PUCRF_PF2_Pos (2U)
11250 #define PWR_PUCRF_PF2_Msk (0x1UL << PWR_PUCRF_PF2_Pos) /*!< 0x00000004 */
11251 #define PWR_PUCRF_PF2 PWR_PUCRF_PF2_Msk /*!< Port PF2 Pull-Up set */
11252 #define PWR_PUCRF_PF1_Pos (1U)
11253 #define PWR_PUCRF_PF1_Msk (0x1UL << PWR_PUCRF_PF1_Pos) /*!< 0x00000002 */
11254 #define PWR_PUCRF_PF1 PWR_PUCRF_PF1_Msk /*!< Port PF1 Pull-Up set */
11255 #define PWR_PUCRF_PF0_Pos (0U)
11256 #define PWR_PUCRF_PF0_Msk (0x1UL << PWR_PUCRF_PF0_Pos) /*!< 0x00000001 */
11257 #define PWR_PUCRF_PF0 PWR_PUCRF_PF0_Msk /*!< Port PF0 Pull-Up set */
11258
11259 /******************** Bit definition for PWR_PDCRF register ********************/
11260 #define PWR_PDCRF_PF15_Pos (15U)
11261 #define PWR_PDCRF_PF15_Msk (0x1UL << PWR_PDCRF_PF15_Pos) /*!< 0x00008000 */
11262 #define PWR_PDCRF_PF15 PWR_PDCRF_PF15_Msk /*!< Port PF15 Pull-Down set */
11263 #define PWR_PDCRF_PF14_Pos (14U)
11264 #define PWR_PDCRF_PF14_Msk (0x1UL << PWR_PDCRF_PF14_Pos) /*!< 0x00004000 */
11265 #define PWR_PDCRF_PF14 PWR_PDCRF_PF14_Msk /*!< Port PF14 Pull-Down set */
11266 #define PWR_PDCRF_PF13_Pos (13U)
11267 #define PWR_PDCRF_PF13_Msk (0x1UL << PWR_PDCRF_PF13_Pos) /*!< 0x00002000 */
11268 #define PWR_PDCRF_PF13 PWR_PDCRF_PF13_Msk /*!< Port PF13 Pull-Down set */
11269 #define PWR_PDCRF_PF12_Pos (12U)
11270 #define PWR_PDCRF_PF12_Msk (0x1UL << PWR_PDCRF_PF12_Pos) /*!< 0x00001000 */
11271 #define PWR_PDCRF_PF12 PWR_PDCRF_PF12_Msk /*!< Port PF12 Pull-Down set */
11272 #define PWR_PDCRF_PF11_Pos (11U)
11273 #define PWR_PDCRF_PF11_Msk (0x1UL << PWR_PDCRF_PF11_Pos) /*!< 0x00000800 */
11274 #define PWR_PDCRF_PF11 PWR_PDCRF_PF11_Msk /*!< Port PF11 Pull-Down set */
11275 #define PWR_PDCRF_PF10_Pos (10U)
11276 #define PWR_PDCRF_PF10_Msk (0x1UL << PWR_PDCRF_PF10_Pos) /*!< 0x00000400 */
11277 #define PWR_PDCRF_PF10 PWR_PDCRF_PF10_Msk /*!< Port PF10 Pull-Down set */
11278 #define PWR_PDCRF_PF9_Pos (9U)
11279 #define PWR_PDCRF_PF9_Msk (0x1UL << PWR_PDCRF_PF9_Pos) /*!< 0x00000200 */
11280 #define PWR_PDCRF_PF9 PWR_PDCRF_PF9_Msk /*!< Port PF9 Pull-Down set */
11281 #define PWR_PDCRF_PF8_Pos (8U)
11282 #define PWR_PDCRF_PF8_Msk (0x1UL << PWR_PDCRF_PF8_Pos) /*!< 0x00000100 */
11283 #define PWR_PDCRF_PF8 PWR_PDCRF_PF8_Msk /*!< Port PF8 Pull-Down set */
11284 #define PWR_PDCRF_PF7_Pos (7U)
11285 #define PWR_PDCRF_PF7_Msk (0x1UL << PWR_PDCRF_PF7_Pos) /*!< 0x00000080 */
11286 #define PWR_PDCRF_PF7 PWR_PDCRF_PF7_Msk /*!< Port PF7 Pull-Down set */
11287 #define PWR_PDCRF_PF6_Pos (6U)
11288 #define PWR_PDCRF_PF6_Msk (0x1UL << PWR_PDCRF_PF6_Pos) /*!< 0x00000040 */
11289 #define PWR_PDCRF_PF6 PWR_PDCRF_PF6_Msk /*!< Port PF6 Pull-Down set */
11290 #define PWR_PDCRF_PF5_Pos (5U)
11291 #define PWR_PDCRF_PF5_Msk (0x1UL << PWR_PDCRF_PF5_Pos) /*!< 0x00000020 */
11292 #define PWR_PDCRF_PF5 PWR_PDCRF_PF5_Msk /*!< Port PF5 Pull-Down set */
11293 #define PWR_PDCRF_PF4_Pos (4U)
11294 #define PWR_PDCRF_PF4_Msk (0x1UL << PWR_PDCRF_PF4_Pos) /*!< 0x00000010 */
11295 #define PWR_PDCRF_PF4 PWR_PDCRF_PF4_Msk /*!< Port PF4 Pull-Down set */
11296 #define PWR_PDCRF_PF3_Pos (3U)
11297 #define PWR_PDCRF_PF3_Msk (0x1UL << PWR_PDCRF_PF3_Pos) /*!< 0x00000008 */
11298 #define PWR_PDCRF_PF3 PWR_PDCRF_PF3_Msk /*!< Port PF3 Pull-Down set */
11299 #define PWR_PDCRF_PF2_Pos (2U)
11300 #define PWR_PDCRF_PF2_Msk (0x1UL << PWR_PDCRF_PF2_Pos) /*!< 0x00000004 */
11301 #define PWR_PDCRF_PF2 PWR_PDCRF_PF2_Msk /*!< Port PF2 Pull-Down set */
11302 #define PWR_PDCRF_PF1_Pos (1U)
11303 #define PWR_PDCRF_PF1_Msk (0x1UL << PWR_PDCRF_PF1_Pos) /*!< 0x00000002 */
11304 #define PWR_PDCRF_PF1 PWR_PDCRF_PF1_Msk /*!< Port PF1 Pull-Down set */
11305 #define PWR_PDCRF_PF0_Pos (0U)
11306 #define PWR_PDCRF_PF0_Msk (0x1UL << PWR_PDCRF_PF0_Pos) /*!< 0x00000001 */
11307 #define PWR_PDCRF_PF0 PWR_PDCRF_PF0_Msk /*!< Port PF0 Pull-Down set */
11308
11309 /******************** Bit definition for PWR_PUCRG register ********************/
11310 #define PWR_PUCRG_PG15_Pos (15U)
11311 #define PWR_PUCRG_PG15_Msk (0x1UL << PWR_PUCRG_PG15_Pos) /*!< 0x00008000 */
11312 #define PWR_PUCRG_PG15 PWR_PUCRG_PG15_Msk /*!< Port PG15 Pull-Up set */
11313 #define PWR_PUCRG_PG14_Pos (14U)
11314 #define PWR_PUCRG_PG14_Msk (0x1UL << PWR_PUCRG_PG14_Pos) /*!< 0x00004000 */
11315 #define PWR_PUCRG_PG14 PWR_PUCRG_PG14_Msk /*!< Port PG14 Pull-Up set */
11316 #define PWR_PUCRG_PG13_Pos (13U)
11317 #define PWR_PUCRG_PG13_Msk (0x1UL << PWR_PUCRG_PG13_Pos) /*!< 0x00002000 */
11318 #define PWR_PUCRG_PG13 PWR_PUCRG_PG13_Msk /*!< Port PG13 Pull-Up set */
11319 #define PWR_PUCRG_PG12_Pos (12U)
11320 #define PWR_PUCRG_PG12_Msk (0x1UL << PWR_PUCRG_PG12_Pos) /*!< 0x00001000 */
11321 #define PWR_PUCRG_PG12 PWR_PUCRG_PG12_Msk /*!< Port PG12 Pull-Up set */
11322 #define PWR_PUCRG_PG11_Pos (11U)
11323 #define PWR_PUCRG_PG11_Msk (0x1UL << PWR_PUCRG_PG11_Pos) /*!< 0x00000800 */
11324 #define PWR_PUCRG_PG11 PWR_PUCRG_PG11_Msk /*!< Port PG11 Pull-Up set */
11325 #define PWR_PUCRG_PG10_Pos (10U)
11326 #define PWR_PUCRG_PG10_Msk (0x1UL << PWR_PUCRG_PG10_Pos) /*!< 0x00000400 */
11327 #define PWR_PUCRG_PG10 PWR_PUCRG_PG10_Msk /*!< Port PG10 Pull-Up set */
11328 #define PWR_PUCRG_PG9_Pos (9U)
11329 #define PWR_PUCRG_PG9_Msk (0x1UL << PWR_PUCRG_PG9_Pos) /*!< 0x00000200 */
11330 #define PWR_PUCRG_PG9 PWR_PUCRG_PG9_Msk /*!< Port PG9 Pull-Up set */
11331 #define PWR_PUCRG_PG8_Pos (8U)
11332 #define PWR_PUCRG_PG8_Msk (0x1UL << PWR_PUCRG_PG8_Pos) /*!< 0x00000100 */
11333 #define PWR_PUCRG_PG8 PWR_PUCRG_PG8_Msk /*!< Port PG8 Pull-Up set */
11334 #define PWR_PUCRG_PG7_Pos (7U)
11335 #define PWR_PUCRG_PG7_Msk (0x1UL << PWR_PUCRG_PG7_Pos) /*!< 0x00000080 */
11336 #define PWR_PUCRG_PG7 PWR_PUCRG_PG7_Msk /*!< Port PG7 Pull-Up set */
11337 #define PWR_PUCRG_PG6_Pos (6U)
11338 #define PWR_PUCRG_PG6_Msk (0x1UL << PWR_PUCRG_PG6_Pos) /*!< 0x00000040 */
11339 #define PWR_PUCRG_PG6 PWR_PUCRG_PG6_Msk /*!< Port PG6 Pull-Up set */
11340 #define PWR_PUCRG_PG5_Pos (5U)
11341 #define PWR_PUCRG_PG5_Msk (0x1UL << PWR_PUCRG_PG5_Pos) /*!< 0x00000020 */
11342 #define PWR_PUCRG_PG5 PWR_PUCRG_PG5_Msk /*!< Port PG5 Pull-Up set */
11343 #define PWR_PUCRG_PG4_Pos (4U)
11344 #define PWR_PUCRG_PG4_Msk (0x1UL << PWR_PUCRG_PG4_Pos) /*!< 0x00000010 */
11345 #define PWR_PUCRG_PG4 PWR_PUCRG_PG4_Msk /*!< Port PG4 Pull-Up set */
11346 #define PWR_PUCRG_PG3_Pos (3U)
11347 #define PWR_PUCRG_PG3_Msk (0x1UL << PWR_PUCRG_PG3_Pos) /*!< 0x00000008 */
11348 #define PWR_PUCRG_PG3 PWR_PUCRG_PG3_Msk /*!< Port PG3 Pull-Up set */
11349 #define PWR_PUCRG_PG2_Pos (2U)
11350 #define PWR_PUCRG_PG2_Msk (0x1UL << PWR_PUCRG_PG2_Pos) /*!< 0x00000004 */
11351 #define PWR_PUCRG_PG2 PWR_PUCRG_PG2_Msk /*!< Port PG2 Pull-Up set */
11352 #define PWR_PUCRG_PG1_Pos (1U)
11353 #define PWR_PUCRG_PG1_Msk (0x1UL << PWR_PUCRG_PG1_Pos) /*!< 0x00000002 */
11354 #define PWR_PUCRG_PG1 PWR_PUCRG_PG1_Msk /*!< Port PG1 Pull-Up set */
11355 #define PWR_PUCRG_PG0_Pos (0U)
11356 #define PWR_PUCRG_PG0_Msk (0x1UL << PWR_PUCRG_PG0_Pos) /*!< 0x00000001 */
11357 #define PWR_PUCRG_PG0 PWR_PUCRG_PG0_Msk /*!< Port PG0 Pull-Up set */
11358
11359 /******************** Bit definition for PWR_PDCRG register ********************/
11360 #define PWR_PDCRG_PG10_Pos (10U)
11361 #define PWR_PDCRG_PG10_Msk (0x1UL << PWR_PDCRG_PG10_Pos) /*!< 0x00000400 */
11362 #define PWR_PDCRG_PG10 PWR_PDCRG_PG10_Msk /*!< Port PG10 Pull-Down set */
11363 #define PWR_PDCRG_PG9_Pos (9U)
11364 #define PWR_PDCRG_PG9_Msk (0x1UL << PWR_PDCRG_PG9_Pos) /*!< 0x00000200 */
11365 #define PWR_PDCRG_PG9 PWR_PDCRG_PG9_Msk /*!< Port PG9 Pull-Down set */
11366 #define PWR_PDCRG_PG8_Pos (8U)
11367 #define PWR_PDCRG_PG8_Msk (0x1UL << PWR_PDCRG_PG8_Pos) /*!< 0x00000100 */
11368 #define PWR_PDCRG_PG8 PWR_PDCRG_PG8_Msk /*!< Port PG8 Pull-Down set */
11369 #define PWR_PDCRG_PG7_Pos (7U)
11370 #define PWR_PDCRG_PG7_Msk (0x1UL << PWR_PDCRG_PG7_Pos) /*!< 0x00000080 */
11371 #define PWR_PDCRG_PG7 PWR_PDCRG_PG7_Msk /*!< Port PG7 Pull-Down set */
11372 #define PWR_PDCRG_PG6_Pos (6U)
11373 #define PWR_PDCRG_PG6_Msk (0x1UL << PWR_PDCRG_PG6_Pos) /*!< 0x00000040 */
11374 #define PWR_PDCRG_PG6 PWR_PDCRG_PG6_Msk /*!< Port PG6 Pull-Down set */
11375 #define PWR_PDCRG_PG5_Pos (5U)
11376 #define PWR_PDCRG_PG5_Msk (0x1UL << PWR_PDCRG_PG5_Pos) /*!< 0x00000020 */
11377 #define PWR_PDCRG_PG5 PWR_PDCRG_PG5_Msk /*!< Port PG5 Pull-Down set */
11378 #define PWR_PDCRG_PG4_Pos (4U)
11379 #define PWR_PDCRG_PG4_Msk (0x1UL << PWR_PDCRG_PG4_Pos) /*!< 0x00000010 */
11380 #define PWR_PDCRG_PG4 PWR_PDCRG_PG4_Msk /*!< Port PG4 Pull-Down set */
11381 #define PWR_PDCRG_PG3_Pos (3U)
11382 #define PWR_PDCRG_PG3_Msk (0x1UL << PWR_PDCRG_PG3_Pos) /*!< 0x00000008 */
11383 #define PWR_PDCRG_PG3 PWR_PDCRG_PG3_Msk /*!< Port PG3 Pull-Down set */
11384 #define PWR_PDCRG_PG2_Pos (2U)
11385 #define PWR_PDCRG_PG2_Msk (0x1UL << PWR_PDCRG_PG2_Pos) /*!< 0x00000004 */
11386 #define PWR_PDCRG_PG2 PWR_PDCRG_PG2_Msk /*!< Port PG2 Pull-Down set */
11387 #define PWR_PDCRG_PG1_Pos (1U)
11388 #define PWR_PDCRG_PG1_Msk (0x1UL << PWR_PDCRG_PG1_Pos) /*!< 0x00000002 */
11389 #define PWR_PDCRG_PG1 PWR_PDCRG_PG1_Msk /*!< Port PG1 Pull-Down set */
11390 #define PWR_PDCRG_PG0_Pos (0U)
11391 #define PWR_PDCRG_PG0_Msk (0x1UL << PWR_PDCRG_PG0_Pos) /*!< 0x00000001 */
11392 #define PWR_PDCRG_PG0 PWR_PDCRG_PG0_Msk /*!< Port PG0 Pull-Down set */
11393
11394 /******************** Bit definition for PWR_CR5 register ********************/
11395 #define PWR_CR5_R1MODE_Pos (8U)
11396 #define PWR_CR5_R1MODE_Msk (0x1U << PWR_CR5_R1MODE_Pos) /*!< 0x00000100 */
11397 #define PWR_CR5_R1MODE PWR_CR5_R1MODE_Msk /*!< selection for Main Regulator in Range1 */
11398
11399 /******************************************************************************/
11400 /* */
11401 /* QUADSPI */
11402 /* */
11403 /******************************************************************************/
11404 /***************** Bit definition for QUADSPI_CR register *******************/
11405 #define QUADSPI_CR_EN_Pos (0U)
11406 #define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
11407 #define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
11408 #define QUADSPI_CR_ABORT_Pos (1U)
11409 #define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
11410 #define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
11411 #define QUADSPI_CR_DMAEN_Pos (2U)
11412 #define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
11413 #define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
11414 #define QUADSPI_CR_TCEN_Pos (3U)
11415 #define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
11416 #define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
11417 #define QUADSPI_CR_SSHIFT_Pos (4U)
11418 #define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
11419 #define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< Sample Shift */
11420 #define QUADSPI_CR_DFM_Pos (6U)
11421 #define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
11422 #define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual-flash mode */
11423 #define QUADSPI_CR_FSEL_Pos (7U)
11424 #define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
11425 #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash memory selection */
11426 #define QUADSPI_CR_FTHRES_Pos (8U)
11427 #define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
11428 #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
11429 #define QUADSPI_CR_TEIE_Pos (16U)
11430 #define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
11431 #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
11432 #define QUADSPI_CR_TCIE_Pos (17U)
11433 #define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
11434 #define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
11435 #define QUADSPI_CR_FTIE_Pos (18U)
11436 #define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
11437 #define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
11438 #define QUADSPI_CR_SMIE_Pos (19U)
11439 #define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
11440 #define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
11441 #define QUADSPI_CR_TOIE_Pos (20U)
11442 #define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
11443 #define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
11444 #define QUADSPI_CR_APMS_Pos (22U)
11445 #define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
11446 #define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Automatic Polling Mode Stop */
11447 #define QUADSPI_CR_PMM_Pos (23U)
11448 #define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
11449 #define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
11450 #define QUADSPI_CR_PRESCALER_Pos (24U)
11451 #define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
11452 #define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
11453
11454 /***************** Bit definition for QUADSPI_DCR register ******************/
11455 #define QUADSPI_DCR_CKMODE_Pos (0U)
11456 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
11457 #define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
11458 #define QUADSPI_DCR_CSHT_Pos (8U)
11459 #define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
11460 #define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
11461 #define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
11462 #define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
11463 #define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
11464 #define QUADSPI_DCR_FSIZE_Pos (16U)
11465 #define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
11466 #define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
11467
11468 /****************** Bit definition for QUADSPI_SR register *******************/
11469 #define QUADSPI_SR_TEF_Pos (0U)
11470 #define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
11471 #define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
11472 #define QUADSPI_SR_TCF_Pos (1U)
11473 #define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
11474 #define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
11475 #define QUADSPI_SR_FTF_Pos (2U)
11476 #define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
11477 #define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
11478 #define QUADSPI_SR_SMF_Pos (3U)
11479 #define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
11480 #define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
11481 #define QUADSPI_SR_TOF_Pos (4U)
11482 #define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
11483 #define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
11484 #define QUADSPI_SR_BUSY_Pos (5U)
11485 #define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
11486 #define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
11487 #define QUADSPI_SR_FLEVEL_Pos (8U)
11488 #define QUADSPI_SR_FLEVEL_Msk (0x1FUL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001F00 */
11489 #define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
11490
11491 /****************** Bit definition for QUADSPI_FCR register ******************/
11492 #define QUADSPI_FCR_CTEF_Pos (0U)
11493 #define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
11494 #define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
11495 #define QUADSPI_FCR_CTCF_Pos (1U)
11496 #define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
11497 #define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
11498 #define QUADSPI_FCR_CSMF_Pos (3U)
11499 #define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
11500 #define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
11501 #define QUADSPI_FCR_CTOF_Pos (4U)
11502 #define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
11503 #define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
11504
11505 /****************** Bit definition for QUADSPI_DLR register ******************/
11506 #define QUADSPI_DLR_DL_Pos (0U)
11507 #define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
11508 #define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
11509
11510 /****************** Bit definition for QUADSPI_CCR register ******************/
11511 #define QUADSPI_CCR_INSTRUCTION_Pos (0U)
11512 #define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
11513 #define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
11514 #define QUADSPI_CCR_IMODE_Pos (8U)
11515 #define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
11516 #define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
11517 #define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
11518 #define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
11519 #define QUADSPI_CCR_ADMODE_Pos (10U)
11520 #define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
11521 #define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
11522 #define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
11523 #define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
11524 #define QUADSPI_CCR_ADSIZE_Pos (12U)
11525 #define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
11526 #define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
11527 #define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
11528 #define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
11529 #define QUADSPI_CCR_ABMODE_Pos (14U)
11530 #define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
11531 #define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
11532 #define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
11533 #define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
11534 #define QUADSPI_CCR_ABSIZE_Pos (16U)
11535 #define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
11536 #define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
11537 #define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
11538 #define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
11539 #define QUADSPI_CCR_DCYC_Pos (18U)
11540 #define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
11541 #define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
11542 #define QUADSPI_CCR_DMODE_Pos (24U)
11543 #define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
11544 #define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
11545 #define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
11546 #define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
11547 #define QUADSPI_CCR_FMODE_Pos (26U)
11548 #define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
11549 #define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
11550 #define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
11551 #define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
11552 #define QUADSPI_CCR_SIOO_Pos (28U)
11553 #define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
11554 #define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
11555 #define QUADSPI_CCR_DHHC_Pos (30U)
11556 #define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
11557 #define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: DDR hold */
11558 #define QUADSPI_CCR_DDRM_Pos (31U)
11559 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
11560 #define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
11561
11562 /****************** Bit definition for QUADSPI_AR register *******************/
11563 #define QUADSPI_AR_ADDRESS_Pos (0U)
11564 #define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos)/*!< 0xFFFFFFFF */
11565 #define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
11566
11567 /****************** Bit definition for QUADSPI_ABR register ******************/
11568 #define QUADSPI_ABR_ALTERNATE_Pos (0U)
11569 #define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos)/*!< 0xFFFFFFFF */
11570 #define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
11571
11572 /****************** Bit definition for QUADSPI_DR register *******************/
11573 #define QUADSPI_DR_DATA_Pos (0U)
11574 #define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
11575 #define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
11576
11577 /****************** Bit definition for QUADSPI_PSMKR register ****************/
11578 #define QUADSPI_PSMKR_MASK_Pos (0U)
11579 #define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos)/*!< 0xFFFFFFFF */
11580 #define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
11581
11582 /****************** Bit definition for QUADSPI_PSMAR register ****************/
11583 #define QUADSPI_PSMAR_MATCH_Pos (0U)
11584 #define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos)/*!< 0xFFFFFFFF */
11585 #define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
11586
11587 /****************** Bit definition for QUADSPI_PIR register *****************/
11588 #define QUADSPI_PIR_INTERVAL_Pos (0U)
11589 #define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
11590 #define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
11591
11592 /****************** Bit definition for QUADSPI_LPTR register *****************/
11593 #define QUADSPI_LPTR_TIMEOUT_Pos (0U)
11594 #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
11595 #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
11596
11597 /******************************************************************************/
11598 /* */
11599 /* Reset and Clock Control */
11600 /* */
11601 /******************************************************************************/
11602 /*
11603 * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
11604 */
11605
11606 #define RCC_HSI48_SUPPORT
11607 #define RCC_PLLP_DIV_2_31_SUPPORT
11608
11609 /******************** Bit definition for RCC_CR register ********************/
11610 #define RCC_CR_HSION_Pos (8U)
11611 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000100 */
11612 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */
11613 #define RCC_CR_HSIKERON_Pos (9U)
11614 #define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */
11615 #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
11616 #define RCC_CR_HSIRDY_Pos (10U)
11617 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */
11618 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */
11619
11620 #define RCC_CR_HSEON_Pos (16U)
11621 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
11622 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */
11623 #define RCC_CR_HSERDY_Pos (17U)
11624 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
11625 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */
11626 #define RCC_CR_HSEBYP_Pos (18U)
11627 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
11628 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */
11629 #define RCC_CR_CSSON_Pos (19U)
11630 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
11631 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */
11632
11633 #define RCC_CR_PLLON_Pos (24U)
11634 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
11635 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
11636 #define RCC_CR_PLLRDY_Pos (25U)
11637 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
11638 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
11639
11640 /******************** Bit definition for RCC_ICSCR register ***************/
11641 /*!< HSICAL configuration */
11642 #define RCC_ICSCR_HSICAL_Pos (16U)
11643 #define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00FF0000 */
11644 #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */
11645 #define RCC_ICSCR_HSICAL_0 (0x01UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00010000 */
11646 #define RCC_ICSCR_HSICAL_1 (0x02UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00020000 */
11647 #define RCC_ICSCR_HSICAL_2 (0x04UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00040000 */
11648 #define RCC_ICSCR_HSICAL_3 (0x08UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00080000 */
11649 #define RCC_ICSCR_HSICAL_4 (0x10UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00100000 */
11650 #define RCC_ICSCR_HSICAL_5 (0x20UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00200000 */
11651 #define RCC_ICSCR_HSICAL_6 (0x40UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00400000 */
11652 #define RCC_ICSCR_HSICAL_7 (0x80UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00800000 */
11653
11654 /*!< HSITRIM configuration */
11655 #define RCC_ICSCR_HSITRIM_Pos (24U)
11656 #define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
11657 #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
11658 #define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
11659 #define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
11660 #define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
11661 #define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
11662 #define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
11663 #define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
11664 #define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
11665
11666 /******************** Bit definition for RCC_CFGR register ******************/
11667 /*!< SW configuration */
11668 #define RCC_CFGR_SW_Pos (0U)
11669 #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
11670 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
11671 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
11672 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
11673
11674 #define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI16 oscillator selection as system clock */
11675 #define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE oscillator selection as system clock */
11676 #define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selection as system clock */
11677
11678 /*!< SWS configuration */
11679 #define RCC_CFGR_SWS_Pos (2U)
11680 #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
11681 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
11682 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
11683 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
11684
11685 #define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI16 oscillator used as system clock */
11686 #define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
11687 #define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
11688
11689 /*!< HPRE configuration */
11690 #define RCC_CFGR_HPRE_Pos (4U)
11691 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
11692 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
11693 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
11694 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
11695 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
11696 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
11697
11698 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
11699 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
11700 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
11701 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
11702 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
11703 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
11704 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
11705 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
11706 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
11707
11708 /*!< PPRE1 configuration */
11709 #define RCC_CFGR_PPRE1_Pos (8U)
11710 #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
11711 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB2 prescaler) */
11712 #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
11713 #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
11714 #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
11715
11716 #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
11717 #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
11718 #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
11719 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
11720 #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
11721
11722 /*!< PPRE2 configuration */
11723 #define RCC_CFGR_PPRE2_Pos (11U)
11724 #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
11725 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
11726 #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
11727 #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
11728 #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
11729
11730 #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
11731 #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
11732 #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
11733 #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
11734 #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
11735
11736 /*!< MCOSEL configuration */
11737 #define RCC_CFGR_MCOSEL_Pos (24U)
11738 #define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
11739 #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [3:0] bits (Clock output selection) */
11740 #define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
11741 #define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
11742 #define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
11743 #define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
11744
11745 #define RCC_CFGR_MCOPRE_Pos (28U)
11746 #define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
11747 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
11748 #define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
11749 #define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
11750 #define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
11751
11752 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
11753 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
11754 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
11755 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
11756 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
11757
11758 /* Legacy aliases */
11759 #define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE
11760 #define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1
11761 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2
11762 #define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4
11763 #define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8
11764 #define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16
11765
11766 /******************** Bit definition for RCC_PLLCFGR register ***************/
11767 #define RCC_PLLCFGR_PLLSRC_Pos (0U)
11768 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
11769 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
11770 #define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
11771 #define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
11772
11773 #define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)
11774 #define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos)/*!< 0x00000002 */
11775 #define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk /*!< HSI16 oscillator source clock selected */
11776 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)
11777 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)/*!< 0x00000003 */
11778 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk /*!< HSE oscillator source clock selected */
11779
11780 #define RCC_PLLCFGR_PLLM_Pos (4U)
11781 #define RCC_PLLCFGR_PLLM_Msk (0xFUL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x000000F0 */
11782 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
11783 #define RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
11784 #define RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
11785 #define RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */
11786 #define RCC_PLLCFGR_PLLM_3 (0x8UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000080 */
11787
11788 #define RCC_PLLCFGR_PLLN_Pos (8U)
11789 #define RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */
11790 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
11791 #define RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
11792 #define RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
11793 #define RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
11794 #define RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
11795 #define RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
11796 #define RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
11797 #define RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
11798
11799 #define RCC_PLLCFGR_PLLPEN_Pos (16U)
11800 #define RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
11801 #define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk
11802 #define RCC_PLLCFGR_PLLP_Pos (17U)
11803 #define RCC_PLLCFGR_PLLP_Msk (0x1UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
11804 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
11805 #define RCC_PLLCFGR_PLLQEN_Pos (20U)
11806 #define RCC_PLLCFGR_PLLQEN_Msk (0x1UL << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */
11807 #define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk
11808
11809 #define RCC_PLLCFGR_PLLQ_Pos (21U)
11810 #define RCC_PLLCFGR_PLLQ_Msk (0x3UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00600000 */
11811 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
11812 #define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00200000 */
11813 #define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00400000 */
11814
11815 #define RCC_PLLCFGR_PLLREN_Pos (24U)
11816 #define RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */
11817 #define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk
11818 #define RCC_PLLCFGR_PLLR_Pos (25U)
11819 #define RCC_PLLCFGR_PLLR_Msk (0x3UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x06000000 */
11820 #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
11821 #define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x02000000 */
11822 #define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x04000000 */
11823
11824 #define RCC_PLLCFGR_PLLPDIV_Pos (27U)
11825 #define RCC_PLLCFGR_PLLPDIV_Msk (0x1FUL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0xF8000000 */
11826 #define RCC_PLLCFGR_PLLPDIV RCC_PLLCFGR_PLLPDIV_Msk
11827 #define RCC_PLLCFGR_PLLPDIV_0 (0x01UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x08000000 */
11828 #define RCC_PLLCFGR_PLLPDIV_1 (0x02UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x10000000 */
11829 #define RCC_PLLCFGR_PLLPDIV_2 (0x04UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x20000000 */
11830 #define RCC_PLLCFGR_PLLPDIV_3 (0x08UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x40000000 */
11831 #define RCC_PLLCFGR_PLLPDIV_4 (0x10UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x80000000 */
11832
11833 /******************** Bit definition for RCC_CIER register ******************/
11834 #define RCC_CIER_LSIRDYIE_Pos (0U)
11835 #define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
11836 #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
11837 #define RCC_CIER_LSERDYIE_Pos (1U)
11838 #define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
11839 #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
11840 #define RCC_CIER_HSIRDYIE_Pos (3U)
11841 #define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */
11842 #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
11843 #define RCC_CIER_HSERDYIE_Pos (4U)
11844 #define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */
11845 #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
11846 #define RCC_CIER_PLLRDYIE_Pos (5U)
11847 #define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */
11848 #define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
11849 #define RCC_CIER_LSECSSIE_Pos (9U)
11850 #define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
11851 #define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
11852 #define RCC_CIER_HSI48RDYIE_Pos (10U)
11853 #define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos)/*!< 0x00000400 */
11854 #define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
11855
11856 /******************** Bit definition for RCC_CIFR register ******************/
11857 #define RCC_CIFR_LSIRDYF_Pos (0U)
11858 #define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
11859 #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
11860 #define RCC_CIFR_LSERDYF_Pos (1U)
11861 #define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
11862 #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
11863 #define RCC_CIFR_HSIRDYF_Pos (3U)
11864 #define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */
11865 #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
11866 #define RCC_CIFR_HSERDYF_Pos (4U)
11867 #define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */
11868 #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
11869 #define RCC_CIFR_PLLRDYF_Pos (5U)
11870 #define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */
11871 #define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
11872 #define RCC_CIFR_CSSF_Pos (8U)
11873 #define RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */
11874 #define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk
11875 #define RCC_CIFR_LSECSSF_Pos (9U)
11876 #define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
11877 #define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
11878 #define RCC_CIFR_HSI48RDYF_Pos (10U)
11879 #define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000400 */
11880 #define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
11881
11882 /******************** Bit definition for RCC_CICR register ******************/
11883 #define RCC_CICR_LSIRDYC_Pos (0U)
11884 #define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
11885 #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
11886 #define RCC_CICR_LSERDYC_Pos (1U)
11887 #define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
11888 #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
11889 #define RCC_CICR_HSIRDYC_Pos (3U)
11890 #define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */
11891 #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
11892 #define RCC_CICR_HSERDYC_Pos (4U)
11893 #define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */
11894 #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
11895 #define RCC_CICR_PLLRDYC_Pos (5U)
11896 #define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */
11897 #define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
11898 #define RCC_CICR_CSSC_Pos (8U)
11899 #define RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */
11900 #define RCC_CICR_CSSC RCC_CICR_CSSC_Msk
11901 #define RCC_CICR_LSECSSC_Pos (9U)
11902 #define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
11903 #define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
11904 #define RCC_CICR_HSI48RDYC_Pos (10U)
11905 #define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000400 */
11906 #define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
11907
11908 /******************** Bit definition for RCC_AHB1RSTR register **************/
11909 #define RCC_AHB1RSTR_DMA1RST_Pos (0U)
11910 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)/*!< 0x00000001 */
11911 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
11912 #define RCC_AHB1RSTR_DMA2RST_Pos (1U)
11913 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)/*!< 0x00000002 */
11914 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
11915 #define RCC_AHB1RSTR_DMAMUX1RST_Pos (2U)
11916 #define RCC_AHB1RSTR_DMAMUX1RST_Msk (0x1UL << RCC_AHB1RSTR_DMAMUX1RST_Pos)/*!< 0x00000004 */
11917 #define RCC_AHB1RSTR_DMAMUX1RST RCC_AHB1RSTR_DMAMUX1RST_Msk
11918 #define RCC_AHB1RSTR_CORDICRST_Pos (3U)
11919 #define RCC_AHB1RSTR_CORDICRST_Msk (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos)/*!< 0x00000008 */
11920 #define RCC_AHB1RSTR_CORDICRST RCC_AHB1RSTR_CORDICRST_Msk
11921 #define RCC_AHB1RSTR_FMACRST_Pos (4U)
11922 #define RCC_AHB1RSTR_FMACRST_Msk (0x1UL << RCC_AHB1RSTR_FMACRST_Pos) /*!< 0x00000010 */
11923 #define RCC_AHB1RSTR_FMACRST RCC_AHB1RSTR_FMACRST_Msk
11924 #define RCC_AHB1RSTR_FLASHRST_Pos (8U)
11925 #define RCC_AHB1RSTR_FLASHRST_Msk (0x1UL << RCC_AHB1RSTR_FLASHRST_Pos)/*!< 0x00000100 */
11926 #define RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk
11927 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
11928 #define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)/*!< 0x00001000 */
11929 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
11930
11931 /******************** Bit definition for RCC_AHB2RSTR register **************/
11932 #define RCC_AHB2RSTR_GPIOARST_Pos (0U)
11933 #define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)/*!< 0x00000001 */
11934 #define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk
11935 #define RCC_AHB2RSTR_GPIOBRST_Pos (1U)
11936 #define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)/*!< 0x00000002 */
11937 #define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk
11938 #define RCC_AHB2RSTR_GPIOCRST_Pos (2U)
11939 #define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)/*!< 0x00000004 */
11940 #define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk
11941 #define RCC_AHB2RSTR_GPIODRST_Pos (3U)
11942 #define RCC_AHB2RSTR_GPIODRST_Msk (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos)/*!< 0x00000008 */
11943 #define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk
11944 #define RCC_AHB2RSTR_GPIOERST_Pos (4U)
11945 #define RCC_AHB2RSTR_GPIOERST_Msk (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos)/*!< 0x00000010 */
11946 #define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk
11947 #define RCC_AHB2RSTR_GPIOFRST_Pos (5U)
11948 #define RCC_AHB2RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOFRST_Pos)/*!< 0x00000020 */
11949 #define RCC_AHB2RSTR_GPIOFRST RCC_AHB2RSTR_GPIOFRST_Msk
11950 #define RCC_AHB2RSTR_GPIOGRST_Pos (6U)
11951 #define RCC_AHB2RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOGRST_Pos)/*!< 0x00000040 */
11952 #define RCC_AHB2RSTR_GPIOGRST RCC_AHB2RSTR_GPIOGRST_Msk
11953 #define RCC_AHB2RSTR_ADC12RST_Pos (13U)
11954 #define RCC_AHB2RSTR_ADC12RST_Msk (0x1UL << RCC_AHB2RSTR_ADC12RST_Pos)/*!< 0x00002000 */
11955 #define RCC_AHB2RSTR_ADC12RST RCC_AHB2RSTR_ADC12RST_Msk
11956 #define RCC_AHB2RSTR_ADC345RST_Pos (14U)
11957 #define RCC_AHB2RSTR_ADC345RST_Msk (0x1UL << RCC_AHB2RSTR_ADC345RST_Pos)/*!< 0x00004000 */
11958 #define RCC_AHB2RSTR_ADC345RST RCC_AHB2RSTR_ADC345RST_Msk
11959 #define RCC_AHB2RSTR_DAC1RST_Pos (16U)
11960 #define RCC_AHB2RSTR_DAC1RST_Msk (0x1UL << RCC_AHB2RSTR_DAC1RST_Pos)/*!< 0x00010000 */
11961 #define RCC_AHB2RSTR_DAC1RST RCC_AHB2RSTR_DAC1RST_Msk
11962 #define RCC_AHB2RSTR_DAC2RST_Pos (17U)
11963 #define RCC_AHB2RSTR_DAC2RST_Msk (0x1UL << RCC_AHB2RSTR_DAC2RST_Pos)/*!< 0x00020000 */
11964 #define RCC_AHB2RSTR_DAC2RST RCC_AHB2RSTR_DAC2RST_Msk
11965 #define RCC_AHB2RSTR_DAC3RST_Pos (18U)
11966 #define RCC_AHB2RSTR_DAC3RST_Msk (0x1UL << RCC_AHB2RSTR_DAC3RST_Pos)/*!< 0x00040000 */
11967 #define RCC_AHB2RSTR_DAC3RST RCC_AHB2RSTR_DAC3RST_Msk
11968 #define RCC_AHB2RSTR_DAC4RST_Pos (19U)
11969 #define RCC_AHB2RSTR_DAC4RST_Msk (0x1UL << RCC_AHB2RSTR_DAC4RST_Pos)/*!< 0x00080000 */
11970 #define RCC_AHB2RSTR_DAC4RST RCC_AHB2RSTR_DAC4RST_Msk
11971 #define RCC_AHB2RSTR_RNGRST_Pos (26U)
11972 #define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)/*!< 0x04000000 */
11973 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
11974
11975 /******************** Bit definition for RCC_AHB3RSTR register **************/
11976 #define RCC_AHB3RSTR_FMCRST_Pos (0U)
11977 #define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)/*!< 0x00000001 */
11978 #define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
11979 #define RCC_AHB3RSTR_QSPIRST_Pos (8U)
11980 #define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)/*!< 0x00000100 */
11981 #define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
11982
11983 /******************** Bit definition for RCC_APB1RSTR1 register **************/
11984 #define RCC_APB1RSTR1_TIM2RST_Pos (0U)
11985 #define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)/*!< 0x00000001 */
11986 #define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk
11987 #define RCC_APB1RSTR1_TIM3RST_Pos (1U)
11988 #define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos)/*!< 0x00000002 */
11989 #define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk
11990 #define RCC_APB1RSTR1_TIM4RST_Pos (2U)
11991 #define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)/*!< 0x00000004 */
11992 #define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk
11993 #define RCC_APB1RSTR1_TIM5RST_Pos (3U)
11994 #define RCC_APB1RSTR1_TIM5RST_Msk (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos)/*!< 0x00000008 */
11995 #define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk
11996 #define RCC_APB1RSTR1_TIM6RST_Pos (4U)
11997 #define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)/*!< 0x00000010 */
11998 #define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk
11999 #define RCC_APB1RSTR1_TIM7RST_Pos (5U)
12000 #define RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)/*!< 0x00000020 */
12001 #define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk
12002 #define RCC_APB1RSTR1_CRSRST_Pos (8U)
12003 #define RCC_APB1RSTR1_CRSRST_Msk (0x1UL << RCC_APB1RSTR1_CRSRST_Pos)/*!< 0x00000100 */
12004 #define RCC_APB1RSTR1_CRSRST RCC_APB1RSTR1_CRSRST_Msk
12005 #define RCC_APB1RSTR1_SPI2RST_Pos (14U)
12006 #define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)/*!< 0x00004000 */
12007 #define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk
12008 #define RCC_APB1RSTR1_SPI3RST_Pos (15U)
12009 #define RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos)/*!< 0x00008000 */
12010 #define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk
12011 #define RCC_APB1RSTR1_USART2RST_Pos (17U)
12012 #define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */
12013 #define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk
12014 #define RCC_APB1RSTR1_USART3RST_Pos (18U)
12015 #define RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)/*!< 0x00040000 */
12016 #define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk
12017 #define RCC_APB1RSTR1_UART4RST_Pos (19U)
12018 #define RCC_APB1RSTR1_UART4RST_Msk (0x1UL << RCC_APB1RSTR1_UART4RST_Pos)/*!< 0x00080000 */
12019 #define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk
12020 #define RCC_APB1RSTR1_UART5RST_Pos (20U)
12021 #define RCC_APB1RSTR1_UART5RST_Msk (0x1UL << RCC_APB1RSTR1_UART5RST_Pos)/*!< 0x00100000 */
12022 #define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk
12023 #define RCC_APB1RSTR1_I2C1RST_Pos (21U)
12024 #define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)/*!< 0x00200000 */
12025 #define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk
12026 #define RCC_APB1RSTR1_I2C2RST_Pos (22U)
12027 #define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)/*!< 0x00400000 */
12028 #define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk
12029 #define RCC_APB1RSTR1_USBRST_Pos (23U)
12030 #define RCC_APB1RSTR1_USBRST_Msk (0x1UL << RCC_APB1RSTR1_USBRST_Pos)/*!< 0x00800000 */
12031 #define RCC_APB1RSTR1_USBRST RCC_APB1RSTR1_USBRST_Msk
12032 #define RCC_APB1RSTR1_FDCANRST_Pos (25U)
12033 #define RCC_APB1RSTR1_FDCANRST_Msk (0x1UL << RCC_APB1RSTR1_FDCANRST_Pos)/*!< 0x02000000 */
12034 #define RCC_APB1RSTR1_FDCANRST RCC_APB1RSTR1_FDCANRST_Msk
12035 #define RCC_APB1RSTR1_PWRRST_Pos (28U)
12036 #define RCC_APB1RSTR1_PWRRST_Msk (0x1UL << RCC_APB1RSTR1_PWRRST_Pos)/*!< 0x10000000 */
12037 #define RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk
12038 #define RCC_APB1RSTR1_I2C3RST_Pos (30U)
12039 #define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)/*!< 0x40000000 */
12040 #define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk
12041 #define RCC_APB1RSTR1_LPTIM1RST_Pos (31U)
12042 #define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x80000000 */
12043 #define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk
12044
12045 /******************** Bit definition for RCC_APB1RSTR2 register **************/
12046 #define RCC_APB1RSTR2_LPUART1RST_Pos (0U)
12047 #define RCC_APB1RSTR2_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)/*!< 0x00000001 */
12048 #define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk
12049 #define RCC_APB1RSTR2_I2C4RST_Pos (1U)
12050 #define RCC_APB1RSTR2_I2C4RST_Msk (0x1UL << RCC_APB1RSTR2_I2C4RST_Pos)/*!< 0x00000002 */
12051 #define RCC_APB1RSTR2_I2C4RST RCC_APB1RSTR2_I2C4RST_Msk
12052 #define RCC_APB1RSTR2_UCPD1RST_Pos (8U)
12053 #define RCC_APB1RSTR2_UCPD1RST_Msk (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos)/*!< 0x00000100 */
12054 #define RCC_APB1RSTR2_UCPD1RST RCC_APB1RSTR2_UCPD1RST_Msk
12055
12056 /******************** Bit definition for RCC_APB2RSTR register **************/
12057 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
12058 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)/*!< 0x00000001 */
12059 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
12060 #define RCC_APB2RSTR_TIM1RST_Pos (11U)
12061 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)/*!< 0x00000800 */
12062 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
12063 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
12064 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)/*!< 0x00001000 */
12065 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
12066 #define RCC_APB2RSTR_TIM8RST_Pos (13U)
12067 #define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)/*!< 0x00002000 */
12068 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
12069 #define RCC_APB2RSTR_USART1RST_Pos (14U)
12070 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)/*!< 0x00004000 */
12071 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
12072 #define RCC_APB2RSTR_SPI4RST_Pos (15U)
12073 #define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)/*!< 0x00008000 */
12074 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
12075 #define RCC_APB2RSTR_TIM15RST_Pos (16U)
12076 #define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)/*!< 0x00010000 */
12077 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
12078 #define RCC_APB2RSTR_TIM16RST_Pos (17U)
12079 #define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)/*!< 0x00020000 */
12080 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
12081 #define RCC_APB2RSTR_TIM17RST_Pos (18U)
12082 #define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)/*!< 0x00040000 */
12083 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
12084 #define RCC_APB2RSTR_TIM20RST_Pos (20U)
12085 #define RCC_APB2RSTR_TIM20RST_Msk (0x1UL << RCC_APB2RSTR_TIM20RST_Pos)/*!< 0x00100000 */
12086 #define RCC_APB2RSTR_TIM20RST RCC_APB2RSTR_TIM20RST_Msk
12087 #define RCC_APB2RSTR_SAI1RST_Pos (21U)
12088 #define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)/*!< 0x00200000 */
12089 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
12090 #define RCC_APB2RSTR_HRTIM1RST_Pos (26U)
12091 #define RCC_APB2RSTR_HRTIM1RST_Msk (0x1UL << RCC_APB2RSTR_HRTIM1RST_Pos)/*!< 0x04000000 */
12092 #define RCC_APB2RSTR_HRTIM1RST RCC_APB2RSTR_HRTIM1RST_Msk
12093
12094 /******************** Bit definition for RCC_AHB1ENR register ***************/
12095 #define RCC_AHB1ENR_DMA1EN_Pos (0U)
12096 #define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
12097 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
12098 #define RCC_AHB1ENR_DMA2EN_Pos (1U)
12099 #define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
12100 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
12101 #define RCC_AHB1ENR_DMAMUX1EN_Pos (2U)
12102 #define RCC_AHB1ENR_DMAMUX1EN_Msk (0x1UL << RCC_AHB1ENR_DMAMUX1EN_Pos)/*!< 0x00000004 */
12103 #define RCC_AHB1ENR_DMAMUX1EN RCC_AHB1ENR_DMAMUX1EN_Msk
12104 #define RCC_AHB1ENR_CORDICEN_Pos (3U)
12105 #define RCC_AHB1ENR_CORDICEN_Msk (0x1UL << RCC_AHB1ENR_CORDICEN_Pos)/*!< 0x00000008 */
12106 #define RCC_AHB1ENR_CORDICEN RCC_AHB1ENR_CORDICEN_Msk
12107 #define RCC_AHB1ENR_FMACEN_Pos (4U)
12108 #define RCC_AHB1ENR_FMACEN_Msk (0x1UL << RCC_AHB1ENR_FMACEN_Pos) /*!< 0x00000010 */
12109 #define RCC_AHB1ENR_FMACEN RCC_AHB1ENR_FMACEN_Msk
12110 #define RCC_AHB1ENR_FLASHEN_Pos (8U)
12111 #define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos)/*!< 0x00000100 */
12112 #define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk
12113 #define RCC_AHB1ENR_CRCEN_Pos (12U)
12114 #define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
12115 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
12116
12117 /******************** Bit definition for RCC_AHB2ENR register ***************/
12118 #define RCC_AHB2ENR_GPIOAEN_Pos (0U)
12119 #define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos)/*!< 0x00000001 */
12120 #define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk
12121 #define RCC_AHB2ENR_GPIOBEN_Pos (1U)
12122 #define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos)/*!< 0x00000002 */
12123 #define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk
12124 #define RCC_AHB2ENR_GPIOCEN_Pos (2U)
12125 #define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos)/*!< 0x00000004 */
12126 #define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk
12127 #define RCC_AHB2ENR_GPIODEN_Pos (3U)
12128 #define RCC_AHB2ENR_GPIODEN_Msk (0x1UL << RCC_AHB2ENR_GPIODEN_Pos)/*!< 0x00000008 */
12129 #define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk
12130 #define RCC_AHB2ENR_GPIOEEN_Pos (4U)
12131 #define RCC_AHB2ENR_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos)/*!< 0x00000010 */
12132 #define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk
12133 #define RCC_AHB2ENR_GPIOFEN_Pos (5U)
12134 #define RCC_AHB2ENR_GPIOFEN_Msk (0x1UL << RCC_AHB2ENR_GPIOFEN_Pos)/*!< 0x00000020 */
12135 #define RCC_AHB2ENR_GPIOFEN RCC_AHB2ENR_GPIOFEN_Msk
12136 #define RCC_AHB2ENR_GPIOGEN_Pos (6U)
12137 #define RCC_AHB2ENR_GPIOGEN_Msk (0x1UL << RCC_AHB2ENR_GPIOGEN_Pos)/*!< 0x00000040 */
12138 #define RCC_AHB2ENR_GPIOGEN RCC_AHB2ENR_GPIOGEN_Msk
12139 #define RCC_AHB2ENR_ADC12EN_Pos (13U)
12140 #define RCC_AHB2ENR_ADC12EN_Msk (0x1UL << RCC_AHB2ENR_ADC12EN_Pos) /*!< 0x00002000 */
12141 #define RCC_AHB2ENR_ADC12EN RCC_AHB2ENR_ADC12EN_Msk
12142 #define RCC_AHB2ENR_ADC345EN_Pos (14U)
12143 #define RCC_AHB2ENR_ADC345EN_Msk (0x1UL << RCC_AHB2ENR_ADC345EN_Pos) /*!< 0x00004000 */
12144 #define RCC_AHB2ENR_ADC345EN RCC_AHB2ENR_ADC345EN_Msk
12145 #define RCC_AHB2ENR_DAC1EN_Pos (16U)
12146 #define RCC_AHB2ENR_DAC1EN_Msk (0x1UL << RCC_AHB2ENR_DAC1EN_Pos) /*!< 0x00010000 */
12147 #define RCC_AHB2ENR_DAC1EN RCC_AHB2ENR_DAC1EN_Msk
12148 #define RCC_AHB2ENR_DAC2EN_Pos (17U)
12149 #define RCC_AHB2ENR_DAC2EN_Msk (0x1UL << RCC_AHB2ENR_DAC2EN_Pos) /*!< 0x00020000 */
12150 #define RCC_AHB2ENR_DAC2EN RCC_AHB2ENR_DAC2EN_Msk
12151 #define RCC_AHB2ENR_DAC3EN_Pos (18U)
12152 #define RCC_AHB2ENR_DAC3EN_Msk (0x1UL << RCC_AHB2ENR_DAC3EN_Pos) /*!< 0x00040000 */
12153 #define RCC_AHB2ENR_DAC3EN RCC_AHB2ENR_DAC3EN_Msk
12154 #define RCC_AHB2ENR_DAC4EN_Pos (19U)
12155 #define RCC_AHB2ENR_DAC4EN_Msk (0x1UL << RCC_AHB2ENR_DAC4EN_Pos) /*!< 0x00080000 */
12156 #define RCC_AHB2ENR_DAC4EN RCC_AHB2ENR_DAC4EN_Msk
12157 #define RCC_AHB2ENR_RNGEN_Pos (26U)
12158 #define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x04000000 */
12159 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
12160
12161 /******************** Bit definition for RCC_AHB3ENR register ***************/
12162 #define RCC_AHB3ENR_FMCEN_Pos (0U)
12163 #define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
12164 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
12165 #define RCC_AHB3ENR_QSPIEN_Pos (8U)
12166 #define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000100 */
12167 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
12168
12169 /******************** Bit definition for RCC_APB1ENR1 register ***************/
12170 #define RCC_APB1ENR1_TIM2EN_Pos (0U)
12171 #define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)/*!< 0x00000001 */
12172 #define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk
12173 #define RCC_APB1ENR1_TIM3EN_Pos (1U)
12174 #define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos)/*!< 0x00000002 */
12175 #define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk
12176 #define RCC_APB1ENR1_TIM4EN_Pos (2U)
12177 #define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)/*!< 0x00000004 */
12178 #define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk
12179 #define RCC_APB1ENR1_TIM5EN_Pos (3U)
12180 #define RCC_APB1ENR1_TIM5EN_Msk (0x1UL << RCC_APB1ENR1_TIM5EN_Pos)/*!< 0x00000008 */
12181 #define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk
12182 #define RCC_APB1ENR1_TIM6EN_Pos (4U)
12183 #define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)/*!< 0x00000010 */
12184 #define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk
12185 #define RCC_APB1ENR1_TIM7EN_Pos (5U)
12186 #define RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)/*!< 0x00000020 */
12187 #define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk
12188 #define RCC_APB1ENR1_CRSEN_Pos (8U)
12189 #define RCC_APB1ENR1_CRSEN_Msk (0x1UL << RCC_APB1ENR1_CRSEN_Pos) /*!< 0x00000100 */
12190 #define RCC_APB1ENR1_CRSEN RCC_APB1ENR1_CRSEN_Msk
12191 #define RCC_APB1ENR1_RTCAPBEN_Pos (10U)
12192 #define RCC_APB1ENR1_RTCAPBEN_Msk (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos)/*!< 0x00000400 */
12193 #define RCC_APB1ENR1_RTCAPBEN RCC_APB1ENR1_RTCAPBEN_Msk
12194 #define RCC_APB1ENR1_WWDGEN_Pos (11U)
12195 #define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)/*!< 0x00000800 */
12196 #define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk
12197 #define RCC_APB1ENR1_SPI2EN_Pos (14U)
12198 #define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)/*!< 0x00004000 */
12199 #define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk
12200 #define RCC_APB1ENR1_SPI3EN_Pos (15U)
12201 #define RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos)/*!< 0x00008000 */
12202 #define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk
12203 #define RCC_APB1ENR1_USART2EN_Pos (17U)
12204 #define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos)/*!< 0x00020000 */
12205 #define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk
12206 #define RCC_APB1ENR1_USART3EN_Pos (18U)
12207 #define RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos)/*!< 0x00040000 */
12208 #define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk
12209 #define RCC_APB1ENR1_UART4EN_Pos (19U)
12210 #define RCC_APB1ENR1_UART4EN_Msk (0x1UL << RCC_APB1ENR1_UART4EN_Pos)/*!< 0x00080000 */
12211 #define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk
12212 #define RCC_APB1ENR1_UART5EN_Pos (20U)
12213 #define RCC_APB1ENR1_UART5EN_Msk (0x1UL << RCC_APB1ENR1_UART5EN_Pos)/*!< 0x00100000 */
12214 #define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk
12215 #define RCC_APB1ENR1_I2C1EN_Pos (21U)
12216 #define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)/*!< 0x00200000 */
12217 #define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk
12218 #define RCC_APB1ENR1_I2C2EN_Pos (22U)
12219 #define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)/*!< 0x00400000 */
12220 #define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk
12221 #define RCC_APB1ENR1_USBEN_Pos (23U)
12222 #define RCC_APB1ENR1_USBEN_Msk (0x1UL << RCC_APB1ENR1_USBEN_Pos)/*!< 0x00800000 */
12223 #define RCC_APB1ENR1_USBEN RCC_APB1ENR1_USBEN_Msk
12224 #define RCC_APB1ENR1_FDCANEN_Pos (25U)
12225 #define RCC_APB1ENR1_FDCANEN_Msk (0x1UL << RCC_APB1ENR1_FDCANEN_Pos)/*!< 0x02000000 */
12226 #define RCC_APB1ENR1_FDCANEN RCC_APB1ENR1_FDCANEN_Msk
12227 #define RCC_APB1ENR1_PWREN_Pos (28U)
12228 #define RCC_APB1ENR1_PWREN_Msk (0x1UL << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */
12229 #define RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk
12230 #define RCC_APB1ENR1_I2C3EN_Pos (30U)
12231 #define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos)/*!< 0x40000000 */
12232 #define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk
12233 #define RCC_APB1ENR1_LPTIM1EN_Pos (31U)
12234 #define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)/*!< 0x80000000 */
12235 #define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk
12236
12237 /******************** Bit definition for RCC_APB1RSTR2 register **************/
12238 #define RCC_APB1ENR2_LPUART1EN_Pos (0U)
12239 #define RCC_APB1ENR2_LPUART1EN_Msk (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)/*!< 0x00000001 */
12240 #define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk
12241 #define RCC_APB1ENR2_I2C4EN_Pos (1U)
12242 #define RCC_APB1ENR2_I2C4EN_Msk (0x1UL << RCC_APB1ENR2_I2C4EN_Pos)/*!< 0x00000002 */
12243 #define RCC_APB1ENR2_I2C4EN RCC_APB1ENR2_I2C4EN_Msk
12244 #define RCC_APB1ENR2_UCPD1EN_Pos (8U)
12245 #define RCC_APB1ENR2_UCPD1EN_Msk (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos)/*!< 0x00000100 */
12246 #define RCC_APB1ENR2_UCPD1EN RCC_APB1ENR2_UCPD1EN_Msk
12247
12248 /******************** Bit definition for RCC_APB2ENR register ***************/
12249 #define RCC_APB2ENR_SYSCFGEN_Pos (0U)
12250 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)/*!< 0x00000001 */
12251 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
12252 #define RCC_APB2ENR_TIM1EN_Pos (11U)
12253 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
12254 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
12255 #define RCC_APB2ENR_SPI1EN_Pos (12U)
12256 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
12257 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
12258 #define RCC_APB2ENR_TIM8EN_Pos (13U)
12259 #define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */
12260 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
12261 #define RCC_APB2ENR_USART1EN_Pos (14U)
12262 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)/*!< 0x00004000 */
12263 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
12264 #define RCC_APB2ENR_SPI4EN_Pos (15U)
12265 #define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00008000 */
12266 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
12267 #define RCC_APB2ENR_TIM15EN_Pos (16U)
12268 #define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos)/*!< 0x00010000 */
12269 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
12270 #define RCC_APB2ENR_TIM16EN_Pos (17U)
12271 #define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos)/*!< 0x00020000 */
12272 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
12273 #define RCC_APB2ENR_TIM17EN_Pos (18U)
12274 #define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)/*!< 0x00040000 */
12275 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
12276 #define RCC_APB2ENR_TIM20EN_Pos (20U)
12277 #define RCC_APB2ENR_TIM20EN_Msk (0x1UL << RCC_APB2ENR_TIM20EN_Pos)/*!< 0x00100000 */
12278 #define RCC_APB2ENR_TIM20EN RCC_APB2ENR_TIM20EN_Msk
12279 #define RCC_APB2ENR_SAI1EN_Pos (21U)
12280 #define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)/*!< 0x00200000 */
12281 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
12282 #define RCC_APB2ENR_HRTIM1EN_Pos (26U)
12283 #define RCC_APB2ENR_HRTIM1EN_Msk (0x1UL << RCC_APB2ENR_HRTIM1EN_Pos)/*!< 0x04000000 */
12284 #define RCC_APB2ENR_HRTIM1EN RCC_APB2ENR_HRTIM1EN_Msk
12285
12286 /******************** Bit definition for RCC_AHB1SMENR register ***************/
12287 #define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
12288 #define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)/*!< 0x00000001 */
12289 #define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk
12290 #define RCC_AHB1SMENR_DMA2SMEN_Pos (1U)
12291 #define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)/*!< 0x00000002 */
12292 #define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk
12293 #define RCC_AHB1SMENR_DMAMUX1SMEN_Pos (2U)
12294 #define RCC_AHB1SMENR_DMAMUX1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMAMUX1SMEN_Pos)/*!< 0x00000004 */
12295 #define RCC_AHB1SMENR_DMAMUX1SMEN RCC_AHB1SMENR_DMAMUX1SMEN_Msk
12296 #define RCC_AHB1SMENR_CORDICSMEN_Pos (3U)
12297 #define RCC_AHB1SMENR_CORDICSMEN_Msk (0x1UL << RCC_AHB1SMENR_CORDICSMEN_Pos)/*!< 0x00000008 */
12298 #define RCC_AHB1SMENR_CORDICSMEN RCC_AHB1SMENR_CORDICSMEN_Msk
12299 #define RCC_AHB1SMENR_FMACSMEN_Pos (4U)
12300 #define RCC_AHB1SMENR_FMACSMEN_Msk (0x1UL << RCC_AHB1SMENR_FMACSMEN_Pos) /*!< 0x00000010 */
12301 #define RCC_AHB1SMENR_FMACSMEN RCC_AHB1SMENR_FMACSMEN_Msk
12302 #define RCC_AHB1SMENR_FLASHSMEN_Pos (8U)
12303 #define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos)/*!< 0x00000100 */
12304 #define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk
12305 #define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U)
12306 #define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos)/*!< 0x00000200 */
12307 #define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk
12308 #define RCC_AHB1SMENR_CRCSMEN_Pos (12U)
12309 #define RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)/*!< 0x00001000 */
12310 #define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk
12311
12312 /******************** Bit definition for RCC_AHB2SMENR register *************/
12313 #define RCC_AHB2SMENR_GPIOASMEN_Pos (0U)
12314 #define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)/*!< 0x00000001 */
12315 #define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk
12316 #define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U)
12317 #define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)/*!< 0x00000002 */
12318 #define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk
12319 #define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U)
12320 #define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)/*!< 0x00000004 */
12321 #define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk
12322 #define RCC_AHB2SMENR_GPIODSMEN_Pos (3U)
12323 #define RCC_AHB2SMENR_GPIODSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIODSMEN_Pos)/*!< 0x00000008 */
12324 #define RCC_AHB2SMENR_GPIODSMEN RCC_AHB2SMENR_GPIODSMEN_Msk
12325 #define RCC_AHB2SMENR_GPIOESMEN_Pos (4U)
12326 #define RCC_AHB2SMENR_GPIOESMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOESMEN_Pos)/*!< 0x00000010 */
12327 #define RCC_AHB2SMENR_GPIOESMEN RCC_AHB2SMENR_GPIOESMEN_Msk
12328 #define RCC_AHB2SMENR_GPIOFSMEN_Pos (5U)
12329 #define RCC_AHB2SMENR_GPIOFSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOFSMEN_Pos)/*!< 0x00000020 */
12330 #define RCC_AHB2SMENR_GPIOFSMEN RCC_AHB2SMENR_GPIOFSMEN_Msk
12331 #define RCC_AHB2SMENR_GPIOGSMEN_Pos (6U)
12332 #define RCC_AHB2SMENR_GPIOGSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOGSMEN_Pos)/*!< 0x00000040 */
12333 #define RCC_AHB2SMENR_GPIOGSMEN RCC_AHB2SMENR_GPIOGSMEN_Msk
12334 #define RCC_AHB2SMENR_CCMSRAMSMEN_Pos (9U)
12335 #define RCC_AHB2SMENR_CCMSRAMSMEN_Msk (0x1UL << RCC_AHB2SMENR_CCMSRAMSMEN_Pos) /*!< 0x00000200 */
12336 #define RCC_AHB2SMENR_CCMSRAMSMEN RCC_AHB2SMENR_CCMSRAMSMEN_Msk
12337 #define RCC_AHB2SMENR_SRAM2SMEN_Pos (10U)
12338 #define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos)/*!< 0x00000400 */
12339 #define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk
12340 #define RCC_AHB2SMENR_ADC12SMEN_Pos (13U)
12341 #define RCC_AHB2SMENR_ADC12SMEN_Msk (0x1UL << RCC_AHB2SMENR_ADC12SMEN_Pos)/*!< 0x00002000 */
12342 #define RCC_AHB2SMENR_ADC12SMEN RCC_AHB2SMENR_ADC12SMEN_Msk
12343 #define RCC_AHB2SMENR_ADC345SMEN_Pos (14U)
12344 #define RCC_AHB2SMENR_ADC345SMEN_Msk (0x1UL << RCC_AHB2SMENR_ADC345SMEN_Pos)/*!< 0x00004000 */
12345 #define RCC_AHB2SMENR_ADC345SMEN RCC_AHB2SMENR_ADC345SMEN_Msk
12346 #define RCC_AHB2SMENR_DAC1SMEN_Pos (16U)
12347 #define RCC_AHB2SMENR_DAC1SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC1SMEN_Pos)/*!< 0x00010000 */
12348 #define RCC_AHB2SMENR_DAC1SMEN RCC_AHB2SMENR_DAC1SMEN_Msk
12349 #define RCC_AHB2SMENR_DAC2SMEN_Pos (17U)
12350 #define RCC_AHB2SMENR_DAC2SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC2SMEN_Pos)/*!< 0x00020000 */
12351 #define RCC_AHB2SMENR_DAC2SMEN RCC_AHB2SMENR_DAC2SMEN_Msk
12352 #define RCC_AHB2SMENR_DAC3SMEN_Pos (18U)
12353 #define RCC_AHB2SMENR_DAC3SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC3SMEN_Pos)/*!< 0x00040000 */
12354 #define RCC_AHB2SMENR_DAC3SMEN RCC_AHB2SMENR_DAC3SMEN_Msk
12355 #define RCC_AHB2SMENR_DAC4SMEN_Pos (19U)
12356 #define RCC_AHB2SMENR_DAC4SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC4SMEN_Pos)/*!< 0x00080000 */
12357 #define RCC_AHB2SMENR_DAC4SMEN RCC_AHB2SMENR_DAC4SMEN_Msk
12358 #define RCC_AHB2SMENR_RNGSMEN_Pos (26U)
12359 #define RCC_AHB2SMENR_RNGSMEN_Msk (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos)/*!< 0x04000000 */
12360 #define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk
12361
12362 /******************** Bit definition for RCC_AHB3SMENR register *************/
12363 #define RCC_AHB3SMENR_FMCSMEN_Pos (0U)
12364 #define RCC_AHB3SMENR_FMCSMEN_Msk (0x1UL << RCC_AHB3SMENR_FMCSMEN_Pos)/*!< 0x00000001 */
12365 #define RCC_AHB3SMENR_FMCSMEN RCC_AHB3SMENR_FMCSMEN_Msk
12366 #define RCC_AHB3SMENR_QSPISMEN_Pos (8U)
12367 #define RCC_AHB3SMENR_QSPISMEN_Msk (0x1UL << RCC_AHB3SMENR_QSPISMEN_Pos)/*!< 0x00000100 */
12368 #define RCC_AHB3SMENR_QSPISMEN RCC_AHB3SMENR_QSPISMEN_Msk
12369
12370 /******************** Bit definition for RCC_APB1SMENR1 register *************/
12371 #define RCC_APB1SMENR1_TIM2SMEN_Pos (0U)
12372 #define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)/*!< 0x00000001 */
12373 #define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk
12374 #define RCC_APB1SMENR1_TIM3SMEN_Pos (1U)
12375 #define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos)/*!< 0x00000002 */
12376 #define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk
12377 #define RCC_APB1SMENR1_TIM4SMEN_Pos (2U)
12378 #define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos)/*!< 0x00000004 */
12379 #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk
12380 #define RCC_APB1SMENR1_TIM5SMEN_Pos (3U)
12381 #define RCC_APB1SMENR1_TIM5SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM5SMEN_Pos)/*!< 0x00000008 */
12382 #define RCC_APB1SMENR1_TIM5SMEN RCC_APB1SMENR1_TIM5SMEN_Msk
12383 #define RCC_APB1SMENR1_TIM6SMEN_Pos (4U)
12384 #define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos)/*!< 0x00000010 */
12385 #define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk
12386 #define RCC_APB1SMENR1_TIM7SMEN_Pos (5U)
12387 #define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos)/*!< 0x00000020 */
12388 #define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk
12389 #define RCC_APB1SMENR1_CRSSMEN_Pos (8U)
12390 #define RCC_APB1SMENR1_CRSSMEN_Msk (0x1UL << RCC_APB1SMENR1_CRSSMEN_Pos)/*!< 0x00000100 */
12391 #define RCC_APB1SMENR1_CRSSMEN RCC_APB1SMENR1_CRSSMEN_Msk
12392 #define RCC_APB1SMENR1_RTCAPBSMEN_Pos (10U)
12393 #define RCC_APB1SMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos)/*!< 0x00000400 */
12394 #define RCC_APB1SMENR1_RTCAPBSMEN RCC_APB1SMENR1_RTCAPBSMEN_Msk
12395 #define RCC_APB1SMENR1_WWDGSMEN_Pos (11U)
12396 #define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)/*!< 0x00000800 */
12397 #define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk
12398 #define RCC_APB1SMENR1_SPI2SMEN_Pos (14U)
12399 #define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)/*!< 0x00004000 */
12400 #define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk
12401 #define RCC_APB1SMENR1_SPI3SMEN_Pos (15U)
12402 #define RCC_APB1SMENR1_SPI3SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI3SMEN_Pos)/*!< 0x00008000 */
12403 #define RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk
12404 #define RCC_APB1SMENR1_USART2SMEN_Pos (17U)
12405 #define RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)/*!< 0x00020000 */
12406 #define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk
12407 #define RCC_APB1SMENR1_USART3SMEN_Pos (18U)
12408 #define RCC_APB1SMENR1_USART3SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos)/*!< 0x00040000 */
12409 #define RCC_APB1SMENR1_USART3SMEN RCC_APB1SMENR1_USART3SMEN_Msk
12410 #define RCC_APB1SMENR1_UART4SMEN_Pos (19U)
12411 #define RCC_APB1SMENR1_UART4SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART4SMEN_Pos)/*!< 0x00080000 */
12412 #define RCC_APB1SMENR1_UART4SMEN RCC_APB1SMENR1_UART4SMEN_Msk
12413 #define RCC_APB1SMENR1_UART5SMEN_Pos (20U)
12414 #define RCC_APB1SMENR1_UART5SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART5SMEN_Pos)/*!< 0x00100000 */
12415 #define RCC_APB1SMENR1_UART5SMEN RCC_APB1SMENR1_UART5SMEN_Msk
12416 #define RCC_APB1SMENR1_I2C1SMEN_Pos (21U)
12417 #define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)/*!< 0x00200000 */
12418 #define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk
12419 #define RCC_APB1SMENR1_I2C2SMEN_Pos (22U)
12420 #define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)/*!< 0x00400000 */
12421 #define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk
12422 #define RCC_APB1SMENR1_USBSMEN_Pos (23U)
12423 #define RCC_APB1SMENR1_USBSMEN_Msk (0x1UL << RCC_APB1SMENR1_USBSMEN_Pos)/*!< 0x00800000 */
12424 #define RCC_APB1SMENR1_USBSMEN RCC_APB1SMENR1_USBSMEN_Msk
12425 #define RCC_APB1SMENR1_FDCANSMEN_Pos (25U)
12426 #define RCC_APB1SMENR1_FDCANSMEN_Msk (0x1UL << RCC_APB1SMENR1_FDCANSMEN_Pos)/*!< 0x02000000 */
12427 #define RCC_APB1SMENR1_FDCANSMEN RCC_APB1SMENR1_FDCANSMEN_Msk
12428 #define RCC_APB1SMENR1_PWRSMEN_Pos (28U)
12429 #define RCC_APB1SMENR1_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR1_PWRSMEN_Pos)/*!< 0x10000000 */
12430 #define RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk
12431 #define RCC_APB1SMENR1_I2C3SMEN_Pos (30U)
12432 #define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos)/*!< 0x40000000 */
12433 #define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk
12434 #define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U)
12435 #define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)/*!< 0x80000000 */
12436 #define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk
12437
12438 /******************** Bit definition for RCC_APB1SMENR2 register *************/
12439 #define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U)
12440 #define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)/*!< 0x00000001 */
12441 #define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk
12442 #define RCC_APB1SMENR2_I2C4SMEN_Pos (1U)
12443 #define RCC_APB1SMENR2_I2C4SMEN_Msk (0x1UL << RCC_APB1SMENR2_I2C4SMEN_Pos)/*!< 0x00000002 */
12444 #define RCC_APB1SMENR2_I2C4SMEN RCC_APB1SMENR2_I2C4SMEN_Msk
12445 #define RCC_APB1SMENR2_UCPD1SMEN_Pos (8U)
12446 #define RCC_APB1SMENR2_UCPD1SMEN_Msk (0x1UL << RCC_APB1SMENR2_UCPD1SMEN_Pos)/*!< 0x00000100 */
12447 #define RCC_APB1SMENR2_UCPD1SMEN RCC_APB1SMENR2_UCPD1SMEN_Msk
12448
12449 /******************** Bit definition for RCC_APB2SMENR register *************/
12450 #define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
12451 #define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos)/*!< 0x00000001 */
12452 #define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk
12453 #define RCC_APB2SMENR_TIM1SMEN_Pos (11U)
12454 #define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)/*!< 0x00000800 */
12455 #define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk
12456 #define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
12457 #define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)/*!< 0x00001000 */
12458 #define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk
12459 #define RCC_APB2SMENR_TIM8SMEN_Pos (13U)
12460 #define RCC_APB2SMENR_TIM8SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM8SMEN_Pos)/*!< 0x00002000 */
12461 #define RCC_APB2SMENR_TIM8SMEN RCC_APB2SMENR_TIM8SMEN_Msk
12462 #define RCC_APB2SMENR_USART1SMEN_Pos (14U)
12463 #define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)/*!< 0x00004000 */
12464 #define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk
12465 #define RCC_APB2SMENR_SPI4SMEN_Pos (15U)
12466 #define RCC_APB2SMENR_SPI4SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI4SMEN_Pos)/*!< 0x00008000 */
12467 #define RCC_APB2SMENR_SPI4SMEN RCC_APB2SMENR_SPI4SMEN_Msk
12468 #define RCC_APB2SMENR_TIM15SMEN_Pos (16U)
12469 #define RCC_APB2SMENR_TIM15SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos)/*!< 0x00010000 */
12470 #define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk
12471 #define RCC_APB2SMENR_TIM16SMEN_Pos (17U)
12472 #define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)/*!< 0x00020000 */
12473 #define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk
12474 #define RCC_APB2SMENR_TIM17SMEN_Pos (18U)
12475 #define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */
12476 #define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk
12477 #define RCC_APB2SMENR_TIM20SMEN_Pos (20U)
12478 #define RCC_APB2SMENR_TIM20SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM20SMEN_Pos)/*!< 0x00100000 */
12479 #define RCC_APB2SMENR_TIM20SMEN RCC_APB2SMENR_TIM20SMEN_Msk
12480 #define RCC_APB2SMENR_SAI1SMEN_Pos (21U)
12481 #define RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos)/*!< 0x00200000 */
12482 #define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk
12483 #define RCC_APB2SMENR_HRTIM1SMEN_Pos (26U)
12484 #define RCC_APB2SMENR_HRTIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_HRTIM1SMEN_Pos)/*!< 0x04000000 */
12485 #define RCC_APB2SMENR_HRTIM1SMEN RCC_APB2SMENR_HRTIM1SMEN_Msk
12486
12487 /******************** Bit definition for RCC_CCIPR register ******************/
12488 #define RCC_CCIPR_USART1SEL_Pos (0U)
12489 #define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000003 */
12490 #define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk
12491 #define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000001 */
12492 #define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000002 */
12493
12494 #define RCC_CCIPR_USART2SEL_Pos (2U)
12495 #define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x0000000C */
12496 #define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk
12497 #define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000004 */
12498 #define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000008 */
12499
12500 #define RCC_CCIPR_USART3SEL_Pos (4U)
12501 #define RCC_CCIPR_USART3SEL_Msk (0x3UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000030 */
12502 #define RCC_CCIPR_USART3SEL RCC_CCIPR_USART3SEL_Msk
12503 #define RCC_CCIPR_USART3SEL_0 (0x1UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000010 */
12504 #define RCC_CCIPR_USART3SEL_1 (0x2UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000020 */
12505
12506 #define RCC_CCIPR_UART4SEL_Pos (6U)
12507 #define RCC_CCIPR_UART4SEL_Msk (0x3UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x000000C0 */
12508 #define RCC_CCIPR_UART4SEL RCC_CCIPR_UART4SEL_Msk
12509 #define RCC_CCIPR_UART4SEL_0 (0x1UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000040 */
12510 #define RCC_CCIPR_UART4SEL_1 (0x2UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000080 */
12511
12512 #define RCC_CCIPR_UART5SEL_Pos (8U)
12513 #define RCC_CCIPR_UART5SEL_Msk (0x3UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000300 */
12514 #define RCC_CCIPR_UART5SEL RCC_CCIPR_UART5SEL_Msk
12515 #define RCC_CCIPR_UART5SEL_0 (0x1UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000100 */
12516 #define RCC_CCIPR_UART5SEL_1 (0x2UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000200 */
12517
12518 #define RCC_CCIPR_LPUART1SEL_Pos (10U)
12519 #define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000C00 */
12520 #define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk
12521 #define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000400 */
12522 #define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000800 */
12523
12524 #define RCC_CCIPR_I2C1SEL_Pos (12U)
12525 #define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
12526 #define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk
12527 #define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
12528 #define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
12529
12530 #define RCC_CCIPR_I2C2SEL_Pos (14U)
12531 #define RCC_CCIPR_I2C2SEL_Msk (0x3UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x0000C000 */
12532 #define RCC_CCIPR_I2C2SEL RCC_CCIPR_I2C2SEL_Msk
12533 #define RCC_CCIPR_I2C2SEL_0 (0x1UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00004000 */
12534 #define RCC_CCIPR_I2C2SEL_1 (0x2UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00008000 */
12535
12536 #define RCC_CCIPR_I2C3SEL_Pos (16U)
12537 #define RCC_CCIPR_I2C3SEL_Msk (0x3UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */
12538 #define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk
12539 #define RCC_CCIPR_I2C3SEL_0 (0x1UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */
12540 #define RCC_CCIPR_I2C3SEL_1 (0x2UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */
12541
12542 #define RCC_CCIPR_LPTIM1SEL_Pos (18U)
12543 #define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x000C0000 */
12544 #define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk
12545 #define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00040000 */
12546 #define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00080000 */
12547
12548 #define RCC_CCIPR_SAI1SEL_Pos (20U)
12549 #define RCC_CCIPR_SAI1SEL_Msk (0x3UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00300000 */
12550 #define RCC_CCIPR_SAI1SEL RCC_CCIPR_SAI1SEL_Msk
12551 #define RCC_CCIPR_SAI1SEL_0 (0x1UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00100000 */
12552 #define RCC_CCIPR_SAI1SEL_1 (0x2UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00200000 */
12553
12554 #define RCC_CCIPR_I2S23SEL_Pos (22U)
12555 #define RCC_CCIPR_I2S23SEL_Msk (0x3UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00C00000 */
12556 #define RCC_CCIPR_I2S23SEL RCC_CCIPR_I2S23SEL_Msk
12557 #define RCC_CCIPR_I2S23SEL_0 (0x1UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00400000 */
12558 #define RCC_CCIPR_I2S23SEL_1 (0x2UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00800000 */
12559
12560 #define RCC_CCIPR_FDCANSEL_Pos (24U)
12561 #define RCC_CCIPR_FDCANSEL_Msk (0x3UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x03000000 */
12562 #define RCC_CCIPR_FDCANSEL RCC_CCIPR_FDCANSEL_Msk
12563 #define RCC_CCIPR_FDCANSEL_0 (0x1UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x01000000 */
12564 #define RCC_CCIPR_FDCANSEL_1 (0x2UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x02000000 */
12565
12566 #define RCC_CCIPR_CLK48SEL_Pos (26U)
12567 #define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */
12568 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
12569 #define RCC_CCIPR_CLK48SEL_0 (0x1UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */
12570 #define RCC_CCIPR_CLK48SEL_1 (0x2UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */
12571
12572 #define RCC_CCIPR_ADC12SEL_Pos (28U)
12573 #define RCC_CCIPR_ADC12SEL_Msk (0x3UL << RCC_CCIPR_ADC12SEL_Pos) /*!< 0x30000000 */
12574 #define RCC_CCIPR_ADC12SEL RCC_CCIPR_ADC12SEL_Msk
12575 #define RCC_CCIPR_ADC12SEL_0 (0x1UL << RCC_CCIPR_ADC12SEL_Pos) /*!< 0x10000000 */
12576 #define RCC_CCIPR_ADC12SEL_1 (0x2UL << RCC_CCIPR_ADC12SEL_Pos) /*!< 0x20000000 */
12577
12578 #define RCC_CCIPR_ADC345SEL_Pos (30U)
12579 #define RCC_CCIPR_ADC345SEL_Msk (0x3UL << RCC_CCIPR_ADC345SEL_Pos) /*!< 0x80000000 */
12580 #define RCC_CCIPR_ADC345SEL RCC_CCIPR_ADC345SEL_Msk
12581 #define RCC_CCIPR_ADC345SEL_0 (0x1UL << RCC_CCIPR_ADC345SEL_Pos) /*!< 0x40000000 */
12582 #define RCC_CCIPR_ADC345SEL_1 (0x2UL << RCC_CCIPR_ADC345SEL_Pos) /*!< 0x80000000 */
12583
12584 /******************** Bit definition for RCC_BDCR register ******************/
12585 #define RCC_BDCR_LSEON_Pos (0U)
12586 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
12587 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
12588 #define RCC_BDCR_LSERDY_Pos (1U)
12589 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
12590 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
12591 #define RCC_BDCR_LSEBYP_Pos (2U)
12592 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
12593 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
12594
12595 #define RCC_BDCR_LSEDRV_Pos (3U)
12596 #define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
12597 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
12598 #define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
12599 #define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
12600
12601 #define RCC_BDCR_LSECSSON_Pos (5U)
12602 #define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
12603 #define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
12604 #define RCC_BDCR_LSECSSD_Pos (6U)
12605 #define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
12606 #define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
12607
12608 #define RCC_BDCR_RTCSEL_Pos (8U)
12609 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
12610 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
12611 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
12612 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
12613
12614 #define RCC_BDCR_RTCEN_Pos (15U)
12615 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
12616 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
12617 #define RCC_BDCR_BDRST_Pos (16U)
12618 #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
12619 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
12620 #define RCC_BDCR_LSCOEN_Pos (24U)
12621 #define RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */
12622 #define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk
12623 #define RCC_BDCR_LSCOSEL_Pos (25U)
12624 #define RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */
12625 #define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk
12626
12627 /******************** Bit definition for RCC_CSR register *******************/
12628 #define RCC_CSR_LSION_Pos (0U)
12629 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
12630 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
12631 #define RCC_CSR_LSIRDY_Pos (1U)
12632 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
12633 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
12634
12635 #define RCC_CSR_RMVF_Pos (23U)
12636 #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
12637 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
12638 #define RCC_CSR_OBLRSTF_Pos (25U)
12639 #define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
12640 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
12641 #define RCC_CSR_PINRSTF_Pos (26U)
12642 #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
12643 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
12644 #define RCC_CSR_BORRSTF_Pos (27U)
12645 #define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */
12646 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
12647 #define RCC_CSR_SFTRSTF_Pos (28U)
12648 #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
12649 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
12650 #define RCC_CSR_IWDGRSTF_Pos (29U)
12651 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
12652 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
12653 #define RCC_CSR_WWDGRSTF_Pos (30U)
12654 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
12655 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
12656 #define RCC_CSR_LPWRRSTF_Pos (31U)
12657 #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
12658 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
12659
12660 /******************** Bit definition for RCC_CRRCR register *****************/
12661 #define RCC_CRRCR_HSI48ON_Pos (0U)
12662 #define RCC_CRRCR_HSI48ON_Msk (0x1UL << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */
12663 #define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk
12664 #define RCC_CRRCR_HSI48RDY_Pos (1U)
12665 #define RCC_CRRCR_HSI48RDY_Msk (0x1UL << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
12666 #define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk
12667
12668 /*!< HSI48CAL configuration */
12669 #define RCC_CRRCR_HSI48CAL_Pos (7U)
12670 #define RCC_CRRCR_HSI48CAL_Msk (0x1FFUL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x0000FF80 */
12671 #define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[8:0] bits */
12672 #define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000080 */
12673 #define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000100 */
12674 #define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000200 */
12675 #define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000400 */
12676 #define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000800 */
12677 #define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00001000 */
12678 #define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00002000 */
12679 #define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00004000 */
12680 #define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00008000 */
12681
12682 /******************** Bit definition for RCC_CCIPR2 register ******************/
12683 #define RCC_CCIPR2_I2C4SEL_Pos (0U)
12684 #define RCC_CCIPR2_I2C4SEL_Msk (0x3UL << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000003 */
12685 #define RCC_CCIPR2_I2C4SEL RCC_CCIPR2_I2C4SEL_Msk
12686 #define RCC_CCIPR2_I2C4SEL_0 (0x1UL << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000001 */
12687 #define RCC_CCIPR2_I2C4SEL_1 (0x2UL << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000002 */
12688
12689 #define RCC_CCIPR2_QSPISEL_Pos (20U)
12690 #define RCC_CCIPR2_QSPISEL_Msk (0x3UL << RCC_CCIPR2_QSPISEL_Pos) /*!< 0x00030000 */
12691 #define RCC_CCIPR2_QSPISEL RCC_CCIPR2_QSPISEL_Msk
12692 #define RCC_CCIPR2_QSPISEL_0 (0x1UL << RCC_CCIPR2_QSPISEL_Pos) /*!< 0x00010000 */
12693 #define RCC_CCIPR2_QSPISEL_1 (0x2UL << RCC_CCIPR2_QSPISEL_Pos) /*!< 0x00020000 */
12694
12695 /******************************************************************************/
12696 /* */
12697 /* RNG */
12698 /* */
12699 /******************************************************************************/
12700 /******************** Bits definition for RNG_CR register *******************/
12701 #define RNG_CR_RNGEN_Pos (2U)
12702 #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
12703 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
12704 #define RNG_CR_IE_Pos (3U)
12705 #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
12706 #define RNG_CR_IE RNG_CR_IE_Msk
12707 #define RNG_CR_CED_Pos (5U)
12708 #define RNG_CR_CED_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000020 */
12709 #define RNG_CR_CED RNG_CR_IE_Msk
12710
12711 /******************** Bits definition for RNG_SR register *******************/
12712 #define RNG_SR_DRDY_Pos (0U)
12713 #define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
12714 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
12715 #define RNG_SR_CECS_Pos (1U)
12716 #define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
12717 #define RNG_SR_CECS RNG_SR_CECS_Msk
12718 #define RNG_SR_SECS_Pos (2U)
12719 #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
12720 #define RNG_SR_SECS RNG_SR_SECS_Msk
12721 #define RNG_SR_CEIS_Pos (5U)
12722 #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
12723 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
12724 #define RNG_SR_SEIS_Pos (6U)
12725 #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
12726 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
12727
12728 /******************************************************************************/
12729 /* */
12730 /* Real-Time Clock (RTC) */
12731 /* */
12732 /******************************************************************************/
12733
12734 /******************** Bits definition for RTC_TR register *******************/
12735 #define RTC_TR_PM_Pos (22U)
12736 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
12737 #define RTC_TR_PM RTC_TR_PM_Msk
12738 #define RTC_TR_HT_Pos (20U)
12739 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
12740 #define RTC_TR_HT RTC_TR_HT_Msk
12741 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
12742 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
12743 #define RTC_TR_HU_Pos (16U)
12744 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
12745 #define RTC_TR_HU RTC_TR_HU_Msk
12746 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
12747 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
12748 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
12749 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
12750 #define RTC_TR_MNT_Pos (12U)
12751 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
12752 #define RTC_TR_MNT RTC_TR_MNT_Msk
12753 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
12754 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
12755 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
12756 #define RTC_TR_MNU_Pos (8U)
12757 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
12758 #define RTC_TR_MNU RTC_TR_MNU_Msk
12759 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
12760 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
12761 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
12762 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
12763 #define RTC_TR_ST_Pos (4U)
12764 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
12765 #define RTC_TR_ST RTC_TR_ST_Msk
12766 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
12767 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
12768 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
12769 #define RTC_TR_SU_Pos (0U)
12770 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
12771 #define RTC_TR_SU RTC_TR_SU_Msk
12772 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
12773 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
12774 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
12775 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
12776
12777 /******************** Bits definition for RTC_DR register *******************/
12778 #define RTC_DR_YT_Pos (20U)
12779 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
12780 #define RTC_DR_YT RTC_DR_YT_Msk
12781 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
12782 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
12783 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
12784 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
12785 #define RTC_DR_YU_Pos (16U)
12786 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
12787 #define RTC_DR_YU RTC_DR_YU_Msk
12788 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
12789 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
12790 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
12791 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
12792 #define RTC_DR_WDU_Pos (13U)
12793 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
12794 #define RTC_DR_WDU RTC_DR_WDU_Msk
12795 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
12796 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
12797 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
12798 #define RTC_DR_MT_Pos (12U)
12799 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
12800 #define RTC_DR_MT RTC_DR_MT_Msk
12801 #define RTC_DR_MU_Pos (8U)
12802 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
12803 #define RTC_DR_MU RTC_DR_MU_Msk
12804 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
12805 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
12806 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
12807 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
12808 #define RTC_DR_DT_Pos (4U)
12809 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
12810 #define RTC_DR_DT RTC_DR_DT_Msk
12811 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
12812 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
12813 #define RTC_DR_DU_Pos (0U)
12814 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
12815 #define RTC_DR_DU RTC_DR_DU_Msk
12816 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
12817 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
12818 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
12819 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
12820
12821 /******************** Bits definition for RTC_SSR register ******************/
12822 #define RTC_SSR_SS_Pos (0U)
12823 #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
12824 #define RTC_SSR_SS RTC_SSR_SS_Msk
12825
12826 /******************** Bits definition for RTC_ICSR register ******************/
12827 #define RTC_ICSR_RECALPF_Pos (16U)
12828 #define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */
12829 #define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk
12830 #define RTC_ICSR_INIT_Pos (7U)
12831 #define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */
12832 #define RTC_ICSR_INIT RTC_ICSR_INIT_Msk
12833 #define RTC_ICSR_INITF_Pos (6U)
12834 #define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */
12835 #define RTC_ICSR_INITF RTC_ICSR_INITF_Msk
12836 #define RTC_ICSR_RSF_Pos (5U)
12837 #define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */
12838 #define RTC_ICSR_RSF RTC_ICSR_RSF_Msk
12839 #define RTC_ICSR_INITS_Pos (4U)
12840 #define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */
12841 #define RTC_ICSR_INITS RTC_ICSR_INITS_Msk
12842 #define RTC_ICSR_SHPF_Pos (3U)
12843 #define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */
12844 #define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk
12845 #define RTC_ICSR_WUTWF_Pos (2U)
12846 #define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */
12847 #define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk
12848 #define RTC_ICSR_ALRBWF_Pos (1U)
12849 #define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */
12850 #define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk
12851 #define RTC_ICSR_ALRAWF_Pos (0U)
12852 #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */
12853 #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk
12854
12855 /******************** Bits definition for RTC_PRER register *****************/
12856 #define RTC_PRER_PREDIV_A_Pos (16U)
12857 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
12858 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
12859 #define RTC_PRER_PREDIV_S_Pos (0U)
12860 #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
12861 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
12862
12863 /******************** Bits definition for RTC_WUTR register *****************/
12864 #define RTC_WUTR_WUT_Pos (0U)
12865 #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
12866 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
12867
12868 /******************** Bits definition for RTC_CR register *******************/
12869 #define RTC_CR_OUT2EN_Pos (31U)
12870 #define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */
12871 #define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!<RTC_OUT2 output enable */
12872 #define RTC_CR_TAMPALRM_TYPE_Pos (30U)
12873 #define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */
12874 #define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!<TAMPALARM output type */
12875 #define RTC_CR_TAMPALRM_PU_Pos (29U)
12876 #define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */
12877 #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!<TAMPALARM output pull-up config */
12878 #define RTC_CR_TAMPOE_Pos (26U)
12879 #define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */
12880 #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk /*!<Tamper detection output enable on TAMPALARM */
12881 #define RTC_CR_TAMPTS_Pos (25U)
12882 #define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */
12883 #define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!<Activate timestamp on tamper detection event */
12884 #define RTC_CR_ITSE_Pos (24U)
12885 #define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
12886 #define RTC_CR_ITSE RTC_CR_ITSE_Msk /*!<Timestamp on internal event enable */
12887 #define RTC_CR_COE_Pos (23U)
12888 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
12889 #define RTC_CR_COE RTC_CR_COE_Msk
12890 #define RTC_CR_OSEL_Pos (21U)
12891 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
12892 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
12893 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
12894 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
12895 #define RTC_CR_POL_Pos (20U)
12896 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
12897 #define RTC_CR_POL RTC_CR_POL_Msk
12898 #define RTC_CR_COSEL_Pos (19U)
12899 #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
12900 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
12901 #define RTC_CR_BKP_Pos (18U)
12902 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
12903 #define RTC_CR_BKP RTC_CR_BKP_Msk
12904 #define RTC_CR_SUB1H_Pos (17U)
12905 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
12906 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
12907 #define RTC_CR_ADD1H_Pos (16U)
12908 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
12909 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
12910 #define RTC_CR_TSIE_Pos (15U)
12911 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
12912 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
12913 #define RTC_CR_WUTIE_Pos (14U)
12914 #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
12915 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
12916 #define RTC_CR_ALRBIE_Pos (13U)
12917 #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
12918 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
12919 #define RTC_CR_ALRAIE_Pos (12U)
12920 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
12921 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
12922 #define RTC_CR_TSE_Pos (11U)
12923 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
12924 #define RTC_CR_TSE RTC_CR_TSE_Msk
12925 #define RTC_CR_WUTE_Pos (10U)
12926 #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
12927 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
12928 #define RTC_CR_ALRBE_Pos (9U)
12929 #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
12930 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
12931 #define RTC_CR_ALRAE_Pos (8U)
12932 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
12933 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
12934 #define RTC_CR_FMT_Pos (6U)
12935 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
12936 #define RTC_CR_FMT RTC_CR_FMT_Msk
12937 #define RTC_CR_BYPSHAD_Pos (5U)
12938 #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
12939 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
12940 #define RTC_CR_REFCKON_Pos (4U)
12941 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
12942 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
12943 #define RTC_CR_TSEDGE_Pos (3U)
12944 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
12945 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
12946 #define RTC_CR_WUCKSEL_Pos (0U)
12947 #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
12948 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
12949 #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
12950 #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
12951 #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
12952
12953 /******************** Bits definition for RTC_WPR register ******************/
12954 #define RTC_WPR_KEY_Pos (0U)
12955 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
12956 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
12957
12958 /******************** Bits definition for RTC_CALR register *****************/
12959 #define RTC_CALR_CALP_Pos (15U)
12960 #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
12961 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
12962 #define RTC_CALR_CALW8_Pos (14U)
12963 #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
12964 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
12965 #define RTC_CALR_CALW16_Pos (13U)
12966 #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
12967 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
12968 #define RTC_CALR_CALM_Pos (0U)
12969 #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
12970 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
12971 #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
12972 #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
12973 #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
12974 #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
12975 #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
12976 #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
12977 #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
12978 #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
12979 #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
12980
12981 /******************** Bits definition for RTC_SHIFTR register ***************/
12982 #define RTC_SHIFTR_SUBFS_Pos (0U)
12983 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
12984 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
12985 #define RTC_SHIFTR_ADD1S_Pos (31U)
12986 #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
12987 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
12988
12989 /******************** Bits definition for RTC_TSTR register *****************/
12990 #define RTC_TSTR_PM_Pos (22U)
12991 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
12992 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
12993 #define RTC_TSTR_HT_Pos (20U)
12994 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
12995 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
12996 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
12997 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
12998 #define RTC_TSTR_HU_Pos (16U)
12999 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
13000 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
13001 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
13002 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
13003 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
13004 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
13005 #define RTC_TSTR_MNT_Pos (12U)
13006 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
13007 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
13008 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
13009 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
13010 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
13011 #define RTC_TSTR_MNU_Pos (8U)
13012 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
13013 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
13014 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
13015 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
13016 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
13017 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
13018 #define RTC_TSTR_ST_Pos (4U)
13019 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
13020 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
13021 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
13022 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
13023 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
13024 #define RTC_TSTR_SU_Pos (0U)
13025 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
13026 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
13027 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
13028 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
13029 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
13030 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
13031
13032 /******************** Bits definition for RTC_TSDR register *****************/
13033 #define RTC_TSDR_WDU_Pos (13U)
13034 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
13035 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
13036 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
13037 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
13038 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
13039 #define RTC_TSDR_MT_Pos (12U)
13040 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
13041 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
13042 #define RTC_TSDR_MU_Pos (8U)
13043 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
13044 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
13045 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
13046 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
13047 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
13048 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
13049 #define RTC_TSDR_DT_Pos (4U)
13050 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
13051 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
13052 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
13053 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
13054 #define RTC_TSDR_DU_Pos (0U)
13055 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
13056 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
13057 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
13058 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
13059 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
13060 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
13061
13062 /******************** Bits definition for RTC_TSSSR register ****************/
13063 #define RTC_TSSSR_SS_Pos (0U)
13064 #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
13065 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
13066
13067 /******************** Bits definition for RTC_ALRMAR register ***************/
13068 #define RTC_ALRMAR_MSK4_Pos (31U)
13069 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
13070 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
13071 #define RTC_ALRMAR_WDSEL_Pos (30U)
13072 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
13073 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
13074 #define RTC_ALRMAR_DT_Pos (28U)
13075 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
13076 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
13077 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
13078 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
13079 #define RTC_ALRMAR_DU_Pos (24U)
13080 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
13081 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
13082 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
13083 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
13084 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
13085 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
13086 #define RTC_ALRMAR_MSK3_Pos (23U)
13087 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
13088 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
13089 #define RTC_ALRMAR_PM_Pos (22U)
13090 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
13091 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
13092 #define RTC_ALRMAR_HT_Pos (20U)
13093 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
13094 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
13095 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
13096 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
13097 #define RTC_ALRMAR_HU_Pos (16U)
13098 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
13099 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
13100 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
13101 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
13102 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
13103 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
13104 #define RTC_ALRMAR_MSK2_Pos (15U)
13105 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
13106 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
13107 #define RTC_ALRMAR_MNT_Pos (12U)
13108 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
13109 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
13110 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
13111 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
13112 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
13113 #define RTC_ALRMAR_MNU_Pos (8U)
13114 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
13115 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
13116 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
13117 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
13118 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
13119 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
13120 #define RTC_ALRMAR_MSK1_Pos (7U)
13121 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
13122 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
13123 #define RTC_ALRMAR_ST_Pos (4U)
13124 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
13125 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
13126 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
13127 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
13128 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
13129 #define RTC_ALRMAR_SU_Pos (0U)
13130 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
13131 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
13132 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
13133 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
13134 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
13135 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
13136
13137 /******************** Bits definition for RTC_ALRMASSR register *************/
13138 #define RTC_ALRMASSR_MASKSS_Pos (24U)
13139 #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
13140 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
13141 #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
13142 #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
13143 #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
13144 #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
13145 #define RTC_ALRMASSR_SS_Pos (0U)
13146 #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
13147 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
13148
13149 /******************** Bits definition for RTC_ALRMBR register ***************/
13150 #define RTC_ALRMBR_MSK4_Pos (31U)
13151 #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
13152 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
13153 #define RTC_ALRMBR_WDSEL_Pos (30U)
13154 #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
13155 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
13156 #define RTC_ALRMBR_DT_Pos (28U)
13157 #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
13158 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
13159 #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
13160 #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
13161 #define RTC_ALRMBR_DU_Pos (24U)
13162 #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
13163 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
13164 #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
13165 #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
13166 #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
13167 #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
13168 #define RTC_ALRMBR_MSK3_Pos (23U)
13169 #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
13170 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
13171 #define RTC_ALRMBR_PM_Pos (22U)
13172 #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
13173 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
13174 #define RTC_ALRMBR_HT_Pos (20U)
13175 #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
13176 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
13177 #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
13178 #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
13179 #define RTC_ALRMBR_HU_Pos (16U)
13180 #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
13181 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
13182 #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
13183 #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
13184 #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
13185 #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
13186 #define RTC_ALRMBR_MSK2_Pos (15U)
13187 #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
13188 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
13189 #define RTC_ALRMBR_MNT_Pos (12U)
13190 #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
13191 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
13192 #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
13193 #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
13194 #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
13195 #define RTC_ALRMBR_MNU_Pos (8U)
13196 #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
13197 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
13198 #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
13199 #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
13200 #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
13201 #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
13202 #define RTC_ALRMBR_MSK1_Pos (7U)
13203 #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
13204 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
13205 #define RTC_ALRMBR_ST_Pos (4U)
13206 #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
13207 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
13208 #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
13209 #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
13210 #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
13211 #define RTC_ALRMBR_SU_Pos (0U)
13212 #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
13213 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
13214 #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
13215 #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
13216 #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
13217 #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
13218
13219 /******************** Bits definition for RTC_ALRMASSR register *************/
13220 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
13221 #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
13222 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
13223 #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
13224 #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
13225 #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
13226 #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
13227 #define RTC_ALRMBSSR_SS_Pos (0U)
13228 #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
13229 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
13230
13231 /******************** Bits definition for RTC_SR register *******************/
13232 #define RTC_SR_ITSF_Pos (5U)
13233 #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */
13234 #define RTC_SR_ITSF RTC_SR_ITSF_Msk
13235 #define RTC_SR_TSOVF_Pos (4U)
13236 #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */
13237 #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk
13238 #define RTC_SR_TSF_Pos (3U)
13239 #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */
13240 #define RTC_SR_TSF RTC_SR_TSF_Msk
13241 #define RTC_SR_WUTF_Pos (2U)
13242 #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */
13243 #define RTC_SR_WUTF RTC_SR_WUTF_Msk
13244 #define RTC_SR_ALRBF_Pos (1U)
13245 #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */
13246 #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk
13247 #define RTC_SR_ALRAF_Pos (0U)
13248 #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */
13249 #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk
13250
13251 /******************** Bits definition for RTC_MISR register *****************/
13252 #define RTC_MISR_ITSMF_Pos (5U)
13253 #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */
13254 #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk
13255 #define RTC_MISR_TSOVMF_Pos (4U)
13256 #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */
13257 #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk
13258 #define RTC_MISR_TSMF_Pos (3U)
13259 #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */
13260 #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk
13261 #define RTC_MISR_WUTMF_Pos (2U)
13262 #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */
13263 #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk
13264 #define RTC_MISR_ALRBMF_Pos (1U)
13265 #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */
13266 #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk
13267 #define RTC_MISR_ALRAMF_Pos (0U)
13268 #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */
13269 #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk
13270
13271 /******************** Bits definition for RTC_SCR register ******************/
13272 #define RTC_SCR_CITSF_Pos (5U)
13273 #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */
13274 #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk
13275 #define RTC_SCR_CTSOVF_Pos (4U)
13276 #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */
13277 #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk
13278 #define RTC_SCR_CTSF_Pos (3U)
13279 #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */
13280 #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk
13281 #define RTC_SCR_CWUTF_Pos (2U)
13282 #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */
13283 #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk
13284 #define RTC_SCR_CALRBF_Pos (1U)
13285 #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */
13286 #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk
13287 #define RTC_SCR_CALRAF_Pos (0U)
13288 #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
13289 #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
13290
13291 /******************************************************************************/
13292 /* */
13293 /* Tamper and backup register (TAMP) */
13294 /* */
13295 /******************************************************************************/
13296 /******************** Bits definition for TAMP_CR1 register *****************/
13297 #define TAMP_CR1_TAMP1E_Pos (0U)
13298 #define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */
13299 #define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk
13300 #define TAMP_CR1_TAMP2E_Pos (1U)
13301 #define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */
13302 #define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk
13303 #define TAMP_CR1_TAMP3E_Pos (2U)
13304 #define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */
13305 #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk
13306 #define TAMP_CR1_ITAMP3E_Pos (18U)
13307 #define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */
13308 #define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk
13309 #define TAMP_CR1_ITAMP4E_Pos (19U)
13310 #define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */
13311 #define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk
13312 #define TAMP_CR1_ITAMP5E_Pos (20U)
13313 #define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */
13314 #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk
13315 #define TAMP_CR1_ITAMP6E_Pos (21U)
13316 #define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */
13317 #define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk
13318
13319 /******************** Bits definition for TAMP_CR2 register *****************/
13320 #define TAMP_CR2_TAMP1NOERASE_Pos (0U)
13321 #define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */
13322 #define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk
13323 #define TAMP_CR2_TAMP2NOERASE_Pos (1U)
13324 #define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */
13325 #define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk
13326 #define TAMP_CR2_TAMP3NOERASE_Pos (2U)
13327 #define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */
13328 #define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk
13329 #define TAMP_CR2_TAMP1MF_Pos (16U)
13330 #define TAMP_CR2_TAMP1MF_Msk (0x1UL << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */
13331 #define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk
13332 #define TAMP_CR2_TAMP2MF_Pos (17U)
13333 #define TAMP_CR2_TAMP2MF_Msk (0x1UL << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */
13334 #define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk
13335 #define TAMP_CR2_TAMP3MF_Pos (18U)
13336 #define TAMP_CR2_TAMP3MF_Msk (0x1UL << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */
13337 #define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk
13338 #define TAMP_CR2_TAMP1TRG_Pos (24U)
13339 #define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */
13340 #define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk
13341 #define TAMP_CR2_TAMP2TRG_Pos (25U)
13342 #define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */
13343 #define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk
13344 #define TAMP_CR2_TAMP3TRG_Pos (26U)
13345 #define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */
13346 #define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
13347
13348 /******************** Bits definition for TAMP_FLTCR register ***************/
13349 #define TAMP_FLTCR_TAMPFREQ_0 ((uint32_t)0x00000001)
13350 #define TAMP_FLTCR_TAMPFREQ_1 ((uint32_t)0x00000002)
13351 #define TAMP_FLTCR_TAMPFREQ_2 ((uint32_t)0x00000004)
13352 #define TAMP_FLTCR_TAMPFREQ_Pos (0U)
13353 #define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
13354 #define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
13355 #define TAMP_FLTCR_TAMPFLT_0 ((uint32_t)0x00000008)
13356 #define TAMP_FLTCR_TAMPFLT_1 ((uint32_t)0x00000010)
13357 #define TAMP_FLTCR_TAMPFLT_Pos (3U)
13358 #define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
13359 #define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
13360 #define TAMP_FLTCR_TAMPPRCH_0 ((uint32_t)0x00000020)
13361 #define TAMP_FLTCR_TAMPPRCH_1 ((uint32_t)0x00000040)
13362 #define TAMP_FLTCR_TAMPPRCH_Pos (5U)
13363 #define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
13364 #define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
13365 #define TAMP_FLTCR_TAMPPUDIS_Pos (7U)
13366 #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */
13367 #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk
13368
13369 /******************** Bits definition for TAMP_IER register *****************/
13370 #define TAMP_IER_TAMP1IE_Pos (0U)
13371 #define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */
13372 #define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk
13373 #define TAMP_IER_TAMP2IE_Pos (1U)
13374 #define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */
13375 #define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk
13376 #define TAMP_IER_TAMP3IE_Pos (2U)
13377 #define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */
13378 #define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk
13379 #define TAMP_IER_ITAMP3IE_Pos (18U)
13380 #define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */
13381 #define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk
13382 #define TAMP_IER_ITAMP4IE_Pos (19U)
13383 #define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */
13384 #define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk
13385 #define TAMP_IER_ITAMP5IE_Pos (20U)
13386 #define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */
13387 #define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk
13388 #define TAMP_IER_ITAMP6IE_Pos (21U)
13389 #define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */
13390 #define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk
13391
13392 /******************** Bits definition for TAMP_SR register ******************/
13393 #define TAMP_SR_TAMP1F_Pos (0U)
13394 #define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */
13395 #define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk
13396 #define TAMP_SR_TAMP2F_Pos (1U)
13397 #define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */
13398 #define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk
13399 #define TAMP_SR_TAMP3F_Pos (2U)
13400 #define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */
13401 #define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk
13402 #define TAMP_SR_ITAMP3F_Pos (18U)
13403 #define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */
13404 #define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk
13405 #define TAMP_SR_ITAMP4F_Pos (19U)
13406 #define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */
13407 #define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk
13408 #define TAMP_SR_ITAMP5F_Pos (20U)
13409 #define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */
13410 #define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk
13411 #define TAMP_SR_ITAMP6F_Pos (21U)
13412 #define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */
13413 #define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk
13414
13415 /******************** Bits definition for TAMP_MISR register ****************/
13416 #define TAMP_MISR_TAMP1MF_Pos (0U)
13417 #define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */
13418 #define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk
13419 #define TAMP_MISR_TAMP2MF_Pos (1U)
13420 #define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */
13421 #define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk
13422 #define TAMP_MISR_TAMP3MF_Pos (2U)
13423 #define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */
13424 #define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk
13425 #define TAMP_MISR_ITAMP3MF_Pos (18U)
13426 #define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */
13427 #define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk
13428 #define TAMP_MISR_ITAMP4MF_Pos (19U)
13429 #define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */
13430 #define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk
13431 #define TAMP_MISR_ITAMP5MF_Pos (20U)
13432 #define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */
13433 #define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk
13434 #define TAMP_MISR_ITAMP6MF_Pos (21U)
13435 #define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */
13436 #define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk
13437
13438 /******************** Bits definition for TAMP_SCR register *****************/
13439 #define TAMP_SCR_CTAMP1F_Pos (0U)
13440 #define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */
13441 #define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk
13442 #define TAMP_SCR_CTAMP2F_Pos (1U)
13443 #define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */
13444 #define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk
13445 #define TAMP_SCR_CTAMP3F_Pos (2U)
13446 #define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */
13447 #define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk
13448 #define TAMP_SCR_CITAMP3F_Pos (18U)
13449 #define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */
13450 #define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk
13451 #define TAMP_SCR_CITAMP4F_Pos (19U)
13452 #define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */
13453 #define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk
13454 #define TAMP_SCR_CITAMP5F_Pos (20U)
13455 #define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */
13456 #define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk
13457 #define TAMP_SCR_CITAMP6F_Pos (21U)
13458 #define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */
13459 #define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk
13460
13461 /******************** Bits definition for TAMP_BKP0R register ***************/
13462 #define TAMP_BKP0R_Pos (0U)
13463 #define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */
13464 #define TAMP_BKP0R TAMP_BKP0R_Msk
13465
13466 /******************** Bits definition for TAMP_BKP1R register ***************/
13467 #define TAMP_BKP1R_Pos (0U)
13468 #define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */
13469 #define TAMP_BKP1R TAMP_BKP1R_Msk
13470
13471 /******************** Bits definition for TAMP_BKP2R register ***************/
13472 #define TAMP_BKP2R_Pos (0U)
13473 #define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */
13474 #define TAMP_BKP2R TAMP_BKP2R_Msk
13475
13476 /******************** Bits definition for TAMP_BKP3R register ***************/
13477 #define TAMP_BKP3R_Pos (0U)
13478 #define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */
13479 #define TAMP_BKP3R TAMP_BKP3R_Msk
13480
13481 /******************** Bits definition for TAMP_BKP4R register ***************/
13482 #define TAMP_BKP4R_Pos (0U)
13483 #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
13484 #define TAMP_BKP4R TAMP_BKP4R_Msk
13485
13486 /******************** Bits definition for TAMP_BKP5R register ***************/
13487 #define TAMP_BKP5R_Pos (0U)
13488 #define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */
13489 #define TAMP_BKP5R TAMP_BKP5R_Msk
13490
13491 /******************** Bits definition for TAMP_BKP6R register ***************/
13492 #define TAMP_BKP6R_Pos (0U)
13493 #define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */
13494 #define TAMP_BKP6R TAMP_BKP6R_Msk
13495
13496 /******************** Bits definition for TAMP_BKP7R register ***************/
13497 #define TAMP_BKP7R_Pos (0U)
13498 #define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */
13499 #define TAMP_BKP7R TAMP_BKP7R_Msk
13500
13501 /******************** Bits definition for TAMP_BKP8R register ***************/
13502 #define TAMP_BKP8R_Pos (0U)
13503 #define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */
13504 #define TAMP_BKP8R TAMP_BKP8R_Msk
13505
13506 /******************** Bits definition for TAMP_BKP9R register ***************/
13507 #define TAMP_BKP9R_Pos (0U)
13508 #define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */
13509 #define TAMP_BKP9R TAMP_BKP9R_Msk
13510
13511 /******************** Bits definition for TAMP_BKP10R register ***************/
13512 #define TAMP_BKP10R_Pos (0U)
13513 #define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */
13514 #define TAMP_BKP10R TAMP_BKP10R_Msk
13515
13516 /******************** Bits definition for TAMP_BKP11R register ***************/
13517 #define TAMP_BKP11R_Pos (0U)
13518 #define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */
13519 #define TAMP_BKP11R TAMP_BKP11R_Msk
13520
13521 /******************** Bits definition for TAMP_BKP12R register ***************/
13522 #define TAMP_BKP12R_Pos (0U)
13523 #define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */
13524 #define TAMP_BKP12R TAMP_BKP12R_Msk
13525
13526 /******************** Bits definition for TAMP_BKP13R register ***************/
13527 #define TAMP_BKP13R_Pos (0U)
13528 #define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */
13529 #define TAMP_BKP13R TAMP_BKP13R_Msk
13530
13531 /******************** Bits definition for TAMP_BKP14R register ***************/
13532 #define TAMP_BKP14R_Pos (0U)
13533 #define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */
13534 #define TAMP_BKP14R TAMP_BKP14R_Msk
13535
13536 /******************** Bits definition for TAMP_BKP15R register ***************/
13537 #define TAMP_BKP15R_Pos (0U)
13538 #define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */
13539 #define TAMP_BKP15R TAMP_BKP15R_Msk
13540
13541 /******************** Bits definition for TAMP_BKP16R register ***************/
13542 #define TAMP_BKP16R_Pos (0U)
13543 #define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */
13544 #define TAMP_BKP16R TAMP_BKP16R_Msk
13545
13546 /******************** Bits definition for TAMP_BKP17R register ***************/
13547 #define TAMP_BKP17R_Pos (0U)
13548 #define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */
13549 #define TAMP_BKP17R TAMP_BKP17R_Msk
13550
13551 /******************** Bits definition for TAMP_BKP18R register ***************/
13552 #define TAMP_BKP18R_Pos (0U)
13553 #define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */
13554 #define TAMP_BKP18R TAMP_BKP18R_Msk
13555
13556 /******************** Bits definition for TAMP_BKP19R register ***************/
13557 #define TAMP_BKP19R_Pos (0U)
13558 #define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */
13559 #define TAMP_BKP19R TAMP_BKP19R_Msk
13560
13561 /******************** Bits definition for TAMP_BKP20R register ***************/
13562 #define TAMP_BKP20R_Pos (0U)
13563 #define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */
13564 #define TAMP_BKP20R TAMP_BKP20R_Msk
13565
13566 /******************** Bits definition for TAMP_BKP21R register ***************/
13567 #define TAMP_BKP21R_Pos (0U)
13568 #define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */
13569 #define TAMP_BKP21R TAMP_BKP21R_Msk
13570
13571 /******************** Bits definition for TAMP_BKP22R register ***************/
13572 #define TAMP_BKP22R_Pos (0U)
13573 #define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */
13574 #define TAMP_BKP22R TAMP_BKP22R_Msk
13575
13576 /******************** Bits definition for TAMP_BKP23R register ***************/
13577 #define TAMP_BKP23R_Pos (0U)
13578 #define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */
13579 #define TAMP_BKP23R TAMP_BKP23R_Msk
13580
13581 /******************** Bits definition for TAMP_BKP24R register ***************/
13582 #define TAMP_BKP24R_Pos (0U)
13583 #define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */
13584 #define TAMP_BKP24R TAMP_BKP24R_Msk
13585
13586 /******************** Bits definition for TAMP_BKP25R register ***************/
13587 #define TAMP_BKP25R_Pos (0U)
13588 #define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */
13589 #define TAMP_BKP25R TAMP_BKP25R_Msk
13590
13591 /******************** Bits definition for TAMP_BKP26R register ***************/
13592 #define TAMP_BKP26R_Pos (0U)
13593 #define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */
13594 #define TAMP_BKP26R TAMP_BKP26R_Msk
13595
13596 /******************** Bits definition for TAMP_BKP27R register ***************/
13597 #define TAMP_BKP27R_Pos (0U)
13598 #define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */
13599 #define TAMP_BKP27R TAMP_BKP27R_Msk
13600
13601 /******************** Bits definition for TAMP_BKP28R register ***************/
13602 #define TAMP_BKP28R_Pos (0U)
13603 #define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */
13604 #define TAMP_BKP28R TAMP_BKP28R_Msk
13605
13606 /******************** Bits definition for TAMP_BKP29R register ***************/
13607 #define TAMP_BKP29R_Pos (0U)
13608 #define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */
13609 #define TAMP_BKP29R TAMP_BKP29R_Msk
13610
13611 /******************** Bits definition for TAMP_BKP30R register ***************/
13612 #define TAMP_BKP30R_Pos (0U)
13613 #define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */
13614 #define TAMP_BKP30R TAMP_BKP30R_Msk
13615
13616 /******************** Bits definition for TAMP_BKP31R register ***************/
13617 #define TAMP_BKP31R_Pos (0U)
13618 #define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */
13619 #define TAMP_BKP31R TAMP_BKP31R_Msk
13620
13621
13622 /******************************************************************************/
13623 /* */
13624 /* Serial Audio Interface */
13625 /* */
13626 /******************************************************************************/
13627 /******************** Bit definition for SAI_GCR register *******************/
13628 #define SAI_GCR_SYNCIN_Pos (0U)
13629 #define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
13630 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
13631 #define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
13632 #define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
13633
13634 #define SAI_GCR_SYNCOUT_Pos (4U)
13635 #define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
13636 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
13637 #define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
13638 #define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
13639
13640 /******************* Bit definition for SAI_xCR1 register *******************/
13641 #define SAI_xCR1_MODE_Pos (0U)
13642 #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
13643 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
13644 #define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
13645 #define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
13646
13647 #define SAI_xCR1_PRTCFG_Pos (2U)
13648 #define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
13649 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
13650 #define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
13651 #define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
13652
13653 #define SAI_xCR1_DS_Pos (5U)
13654 #define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
13655 #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
13656 #define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
13657 #define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
13658 #define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
13659
13660 #define SAI_xCR1_LSBFIRST_Pos (8U)
13661 #define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
13662 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
13663 #define SAI_xCR1_CKSTR_Pos (9U)
13664 #define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
13665 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
13666
13667 #define SAI_xCR1_SYNCEN_Pos (10U)
13668 #define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
13669 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
13670 #define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
13671 #define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
13672
13673 #define SAI_xCR1_MONO_Pos (12U)
13674 #define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
13675 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
13676 #define SAI_xCR1_OUTDRIV_Pos (13U)
13677 #define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
13678 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
13679 #define SAI_xCR1_SAIEN_Pos (16U)
13680 #define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
13681 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
13682 #define SAI_xCR1_DMAEN_Pos (17U)
13683 #define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
13684 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
13685 #define SAI_xCR1_NODIV_Pos (19U)
13686 #define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
13687 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
13688
13689 #define SAI_xCR1_MCKDIV_Pos (20U)
13690 #define SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos) /*!< 0x03F00000 */
13691 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[5:0] (Master ClocK Divider) */
13692 #define SAI_xCR1_MCKDIV_0 (0x00100000U) /*!<Bit 0 */
13693 #define SAI_xCR1_MCKDIV_1 (0x00200000U) /*!<Bit 1 */
13694 #define SAI_xCR1_MCKDIV_2 (0x00400000U) /*!<Bit 2 */
13695 #define SAI_xCR1_MCKDIV_3 (0x00800000U) /*!<Bit 3 */
13696 #define SAI_xCR1_MCKDIV_4 (0x01000000U) /*!<Bit 4 */
13697 #define SAI_xCR1_MCKDIV_5 (0x02000000U) /*!<Bit 5 */
13698
13699 #define SAI_xCR1_OSR_Pos (26U)
13700 #define SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos) /*!< 0x04000000 */
13701 #define SAI_xCR1_OSR SAI_xCR1_OSR_Msk /*!<Oversampling ratio for master clock */
13702
13703 #define SAI_xCR1_MCKEN_Pos (27U)
13704 #define SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos) /*!< 0x08000000 */
13705 #define SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk /*!<Master clock generation enable */
13706
13707 /******************* Bit definition for SAI_xCR2 register *******************/
13708 #define SAI_xCR2_FTH_Pos (0U)
13709 #define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
13710 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
13711 #define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
13712 #define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
13713 #define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
13714
13715 #define SAI_xCR2_FFLUSH_Pos (3U)
13716 #define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
13717 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
13718 #define SAI_xCR2_TRIS_Pos (4U)
13719 #define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
13720 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
13721 #define SAI_xCR2_MUTE_Pos (5U)
13722 #define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
13723 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
13724 #define SAI_xCR2_MUTEVAL_Pos (6U)
13725 #define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
13726 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
13727
13728
13729 #define SAI_xCR2_MUTECNT_Pos (7U)
13730 #define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
13731 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
13732 #define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
13733 #define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
13734 #define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
13735 #define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
13736 #define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
13737 #define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
13738
13739 #define SAI_xCR2_CPL_Pos (13U)
13740 #define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
13741 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!<CPL mode */
13742 #define SAI_xCR2_COMP_Pos (14U)
13743 #define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
13744 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
13745 #define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
13746 #define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
13747
13748
13749 /****************** Bit definition for SAI_xFRCR register *******************/
13750 #define SAI_xFRCR_FRL_Pos (0U)
13751 #define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
13752 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */
13753 #define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
13754 #define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
13755 #define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
13756 #define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
13757 #define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
13758 #define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
13759 #define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
13760 #define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
13761
13762 #define SAI_xFRCR_FSALL_Pos (8U)
13763 #define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
13764 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */
13765 #define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
13766 #define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
13767 #define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
13768 #define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
13769 #define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
13770 #define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
13771 #define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
13772
13773 #define SAI_xFRCR_FSDEF_Pos (16U)
13774 #define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
13775 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
13776 #define SAI_xFRCR_FSPOL_Pos (17U)
13777 #define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
13778 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
13779 #define SAI_xFRCR_FSOFF_Pos (18U)
13780 #define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
13781 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
13782
13783 /****************** Bit definition for SAI_xSLOTR register *******************/
13784 #define SAI_xSLOTR_FBOFF_Pos (0U)
13785 #define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
13786 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
13787 #define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
13788 #define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
13789 #define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
13790 #define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
13791 #define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
13792
13793 #define SAI_xSLOTR_SLOTSZ_Pos (6U)
13794 #define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
13795 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
13796 #define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
13797 #define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
13798
13799 #define SAI_xSLOTR_NBSLOT_Pos (8U)
13800 #define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
13801 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
13802 #define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
13803 #define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
13804 #define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
13805 #define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
13806
13807 #define SAI_xSLOTR_SLOTEN_Pos (16U)
13808 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
13809 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
13810
13811 /******************* Bit definition for SAI_xIMR register *******************/
13812 #define SAI_xIMR_OVRUDRIE_Pos (0U)
13813 #define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
13814 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
13815 #define SAI_xIMR_MUTEDETIE_Pos (1U)
13816 #define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
13817 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
13818 #define SAI_xIMR_WCKCFGIE_Pos (2U)
13819 #define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
13820 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
13821 #define SAI_xIMR_FREQIE_Pos (3U)
13822 #define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
13823 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
13824 #define SAI_xIMR_CNRDYIE_Pos (4U)
13825 #define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
13826 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
13827 #define SAI_xIMR_AFSDETIE_Pos (5U)
13828 #define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
13829 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
13830 #define SAI_xIMR_LFSDETIE_Pos (6U)
13831 #define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
13832 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
13833
13834 /******************** Bit definition for SAI_xSR register *******************/
13835 #define SAI_xSR_OVRUDR_Pos (0U)
13836 #define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
13837 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
13838 #define SAI_xSR_MUTEDET_Pos (1U)
13839 #define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
13840 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
13841 #define SAI_xSR_WCKCFG_Pos (2U)
13842 #define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
13843 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
13844 #define SAI_xSR_FREQ_Pos (3U)
13845 #define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
13846 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
13847 #define SAI_xSR_CNRDY_Pos (4U)
13848 #define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
13849 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
13850 #define SAI_xSR_AFSDET_Pos (5U)
13851 #define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
13852 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
13853 #define SAI_xSR_LFSDET_Pos (6U)
13854 #define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
13855 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
13856
13857 #define SAI_xSR_FLVL_Pos (16U)
13858 #define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
13859 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
13860 #define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
13861 #define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
13862 #define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
13863
13864 /****************** Bit definition for SAI_xCLRFR register ******************/
13865 #define SAI_xCLRFR_COVRUDR_Pos (0U)
13866 #define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
13867 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
13868 #define SAI_xCLRFR_CMUTEDET_Pos (1U)
13869 #define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
13870 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
13871 #define SAI_xCLRFR_CWCKCFG_Pos (2U)
13872 #define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
13873 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
13874 #define SAI_xCLRFR_CFREQ_Pos (3U)
13875 #define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
13876 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
13877 #define SAI_xCLRFR_CCNRDY_Pos (4U)
13878 #define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
13879 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
13880 #define SAI_xCLRFR_CAFSDET_Pos (5U)
13881 #define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
13882 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
13883 #define SAI_xCLRFR_CLFSDET_Pos (6U)
13884 #define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
13885 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
13886
13887 /****************** Bit definition for SAI_xDR register ******************/
13888 #define SAI_xDR_DATA_Pos (0U)
13889 #define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
13890 #define SAI_xDR_DATA SAI_xDR_DATA_Msk
13891
13892 /****************** Bit definition for SAI_PDMCR register *******************/
13893 #define SAI_PDMCR_PDMEN_Pos (0U)
13894 #define SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos) /*!< 0x00000001 */
13895 #define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk /*!<PDM enable */
13896
13897 #define SAI_PDMCR_MICNBR_Pos (4U)
13898 #define SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000030 */
13899 #define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk /*!<MICNBR[1:0] (Number of microphones) */
13900 #define SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000010 */
13901 #define SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000020 */
13902
13903 #define SAI_PDMCR_CKEN1_Pos (8U)
13904 #define SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos) /*!< 0x00000100 */
13905 #define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk /*!<Clock 1 enable */
13906 #define SAI_PDMCR_CKEN2_Pos (9U)
13907 #define SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos) /*!< 0x00000200 */
13908 #define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk /*!<Clock 2 enable */
13909 #define SAI_PDMCR_CKEN3_Pos (10U)
13910 #define SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos) /*!< 0x00000400 */
13911 #define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk /*!<Clock 3 enable */
13912 #define SAI_PDMCR_CKEN4_Pos (11U)
13913 #define SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos) /*!< 0x00000800 */
13914 #define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk /*!<Clock 4 enable */
13915
13916 /****************** Bit definition for SAI_PDMDLY register ******************/
13917 #define SAI_PDMDLY_DLYM1L_Pos (0U)
13918 #define SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000007 */
13919 #define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
13920 #define SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000001 */
13921 #define SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000002 */
13922 #define SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000004 */
13923
13924 #define SAI_PDMDLY_DLYM1R_Pos (4U)
13925 #define SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000070 */
13926 #define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
13927 #define SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000010 */
13928 #define SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000020 */
13929 #define SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000040 */
13930
13931 #define SAI_PDMDLY_DLYM2L_Pos (8U)
13932 #define SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000700 */
13933 #define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
13934 #define SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000100 */
13935 #define SAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000200 */
13936 #define SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000400 */
13937
13938 #define SAI_PDMDLY_DLYM2R_Pos (12U)
13939 #define SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00007000 */
13940 #define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2) */
13941 #define SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00001000 */
13942 #define SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00002000 */
13943 #define SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00004000 */
13944
13945 #define SAI_PDMDLY_DLYM3L_Pos (16U)
13946 #define SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00070000 */
13947 #define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3) */
13948 #define SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00010000 */
13949 #define SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00020000 */
13950 #define SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00040000 */
13951
13952 #define SAI_PDMDLY_DLYM3R_Pos (20U)
13953 #define SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00700000 */
13954 #define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3) */
13955 #define SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00100000 */
13956 #define SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00200000 */
13957 #define SAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00400000 */
13958
13959 #define SAI_PDMDLY_DLYM4L_Pos (24U)
13960 #define SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x07000000 */
13961 #define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4) */
13962 #define SAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x01000000 */
13963 #define SAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x02000000 */
13964 #define SAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x04000000 */
13965
13966 #define SAI_PDMDLY_DLYM4R_Pos (28U)
13967 #define SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x70000000 */
13968 #define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4) */
13969 #define SAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x10000000 */
13970 #define SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x20000000 */
13971 #define SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x40000000 */
13972
13973
13974 /******************************************************************************/
13975 /* */
13976 /* Serial Peripheral Interface (SPI) */
13977 /* */
13978 /******************************************************************************/
13979 /*
13980 * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
13981 */
13982 #define SPI_I2S_SUPPORT /*!< I2S support */
13983
13984 /******************* Bit definition for SPI_CR1 register ********************/
13985 #define SPI_CR1_CPHA_Pos (0U)
13986 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
13987 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
13988 #define SPI_CR1_CPOL_Pos (1U)
13989 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
13990 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
13991 #define SPI_CR1_MSTR_Pos (2U)
13992 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
13993 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
13994
13995 #define SPI_CR1_BR_Pos (3U)
13996 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
13997 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
13998 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
13999 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
14000 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
14001
14002 #define SPI_CR1_SPE_Pos (6U)
14003 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
14004 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
14005 #define SPI_CR1_LSBFIRST_Pos (7U)
14006 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
14007 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
14008 #define SPI_CR1_SSI_Pos (8U)
14009 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
14010 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
14011 #define SPI_CR1_SSM_Pos (9U)
14012 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
14013 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
14014 #define SPI_CR1_RXONLY_Pos (10U)
14015 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
14016 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
14017 #define SPI_CR1_CRCL_Pos (11U)
14018 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
14019 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
14020 #define SPI_CR1_CRCNEXT_Pos (12U)
14021 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
14022 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
14023 #define SPI_CR1_CRCEN_Pos (13U)
14024 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
14025 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
14026 #define SPI_CR1_BIDIOE_Pos (14U)
14027 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
14028 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
14029 #define SPI_CR1_BIDIMODE_Pos (15U)
14030 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
14031 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
14032
14033 /******************* Bit definition for SPI_CR2 register ********************/
14034 #define SPI_CR2_RXDMAEN_Pos (0U)
14035 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
14036 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
14037 #define SPI_CR2_TXDMAEN_Pos (1U)
14038 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
14039 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
14040 #define SPI_CR2_SSOE_Pos (2U)
14041 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
14042 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
14043 #define SPI_CR2_NSSP_Pos (3U)
14044 #define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
14045 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
14046 #define SPI_CR2_FRF_Pos (4U)
14047 #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
14048 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
14049 #define SPI_CR2_ERRIE_Pos (5U)
14050 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
14051 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
14052 #define SPI_CR2_RXNEIE_Pos (6U)
14053 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
14054 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
14055 #define SPI_CR2_TXEIE_Pos (7U)
14056 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
14057 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
14058 #define SPI_CR2_DS_Pos (8U)
14059 #define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
14060 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
14061 #define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */
14062 #define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */
14063 #define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */
14064 #define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */
14065 #define SPI_CR2_FRXTH_Pos (12U)
14066 #define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
14067 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
14068 #define SPI_CR2_LDMARX_Pos (13U)
14069 #define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
14070 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
14071 #define SPI_CR2_LDMATX_Pos (14U)
14072 #define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
14073 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
14074
14075 /******************** Bit definition for SPI_SR register ********************/
14076 #define SPI_SR_RXNE_Pos (0U)
14077 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
14078 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
14079 #define SPI_SR_TXE_Pos (1U)
14080 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
14081 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
14082 #define SPI_SR_CHSIDE_Pos (2U)
14083 #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
14084 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
14085 #define SPI_SR_UDR_Pos (3U)
14086 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
14087 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
14088 #define SPI_SR_CRCERR_Pos (4U)
14089 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
14090 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
14091 #define SPI_SR_MODF_Pos (5U)
14092 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
14093 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
14094 #define SPI_SR_OVR_Pos (6U)
14095 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
14096 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
14097 #define SPI_SR_BSY_Pos (7U)
14098 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
14099 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
14100 #define SPI_SR_FRE_Pos (8U)
14101 #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
14102 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
14103 #define SPI_SR_FRLVL_Pos (9U)
14104 #define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
14105 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
14106 #define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
14107 #define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
14108 #define SPI_SR_FTLVL_Pos (11U)
14109 #define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
14110 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
14111 #define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
14112 #define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
14113
14114 /******************** Bit definition for SPI_DR register ********************/
14115 #define SPI_DR_DR_Pos (0U)
14116 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
14117 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
14118
14119 /******************* Bit definition for SPI_CRCPR register ******************/
14120 #define SPI_CRCPR_CRCPOLY_Pos (0U)
14121 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
14122 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
14123
14124 /****************** Bit definition for SPI_RXCRCR register ******************/
14125 #define SPI_RXCRCR_RXCRC_Pos (0U)
14126 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
14127 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
14128
14129 /****************** Bit definition for SPI_TXCRCR register ******************/
14130 #define SPI_TXCRCR_TXCRC_Pos (0U)
14131 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
14132 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
14133
14134 /****************** Bit definition for SPI_I2SCFGR register *****************/
14135 #define SPI_I2SCFGR_CHLEN_Pos (0U)
14136 #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
14137 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
14138 #define SPI_I2SCFGR_DATLEN_Pos (1U)
14139 #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
14140 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
14141 #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
14142 #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
14143 #define SPI_I2SCFGR_CKPOL_Pos (3U)
14144 #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
14145 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
14146 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
14147 #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
14148 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
14149 #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
14150 #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
14151 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
14152 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
14153 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
14154 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
14155 #define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
14156 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
14157 #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
14158 #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
14159 #define SPI_I2SCFGR_I2SE_Pos (10U)
14160 #define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
14161 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
14162 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
14163 #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
14164 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
14165 #define SPI_I2SCFGR_ASTRTEN_Pos (12U)
14166 #define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
14167 #define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
14168
14169 /****************** Bit definition for SPI_I2SPR register *******************/
14170 #define SPI_I2SPR_I2SDIV_Pos (0U)
14171 #define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
14172 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
14173 #define SPI_I2SPR_ODD_Pos (8U)
14174 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
14175 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
14176 #define SPI_I2SPR_MCKOE_Pos (9U)
14177 #define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
14178 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
14179
14180 /******************************************************************************/
14181 /* */
14182 /* SYSCFG */
14183 /* */
14184 /******************************************************************************/
14185 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
14186 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
14187 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
14188 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
14189 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
14190 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
14191 #define SYSCFG_MEMRMP_MEM_MODE_2 (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
14192
14193 #define SYSCFG_MEMRMP_FB_MODE_Pos (8U)
14194 #define SYSCFG_MEMRMP_FB_MODE_Msk (0x1UL << SYSCFG_MEMRMP_FB_MODE_Pos) /*!< 0x00000100 */
14195 #define SYSCFG_MEMRMP_FB_MODE SYSCFG_MEMRMP_FB_MODE_Msk /*!< User Flash Bank mode selection */
14196
14197 /****************** Bit definition for SYSCFG_CFGR1 register ******************/
14198 #define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
14199 #define SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */
14200 #define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
14201 #define SYSCFG_CFGR1_ANASWVDD_Pos (9U)
14202 #define SYSCFG_CFGR1_ANASWVDD_Msk (0x1UL << SYSCFG_CFGR1_ANASWVDD_Pos) /*!< 0x00000200 */
14203 #define SYSCFG_CFGR1_ANASWVDD SYSCFG_CFGR1_ANASWVDD_Msk /*!< GPIO analog switch control voltage selection */
14204 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
14205 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)/*!< 0x00010000 */
14206 #define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
14207 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
14208 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)/*!< 0x00020000 */
14209 #define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
14210 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
14211 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)/*!< 0x00040000 */
14212 #define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
14213 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
14214 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)/*!< 0x00080000 */
14215 #define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
14216 #define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
14217 #define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
14218 #define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
14219 #define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)
14220 #define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */
14221 #define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
14222 #define SYSCFG_CFGR1_I2C3_FMP_Pos (22U)
14223 #define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos) /*!< 0x00400000 */
14224 #define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
14225 #define SYSCFG_CFGR1_I2C4_FMP_Pos (23U)
14226 #define SYSCFG_CFGR1_I2C4_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C4_FMP_Pos) /*!< 0x00800000 */
14227 #define SYSCFG_CFGR1_I2C4_FMP SYSCFG_CFGR1_I2C4_FMP_Msk /*!< I2C4 Fast mode plus */
14228 #define SYSCFG_CFGR1_FPU_IE_0 (0x04000000U) /*!< Invalid operation Interrupt enable */
14229 #define SYSCFG_CFGR1_FPU_IE_1 (0x08000000U) /*!< Divide-by-zero Interrupt enable */
14230 #define SYSCFG_CFGR1_FPU_IE_2 (0x10000000U) /*!< Underflow Interrupt enable */
14231 #define SYSCFG_CFGR1_FPU_IE_3 (0x20000000U) /*!< Overflow Interrupt enable */
14232 #define SYSCFG_CFGR1_FPU_IE_4 (0x40000000U) /*!< Input denormal Interrupt enable */
14233 #define SYSCFG_CFGR1_FPU_IE_5 (0x80000000U) /*!< Inexact Interrupt enable (interrupt disabled at reset) */
14234
14235 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
14236 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
14237 #define SYSCFG_EXTICR1_EXTI0_Msk (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
14238 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
14239 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
14240 #define SYSCFG_EXTICR1_EXTI1_Msk (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
14241 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
14242 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
14243 #define SYSCFG_EXTICR1_EXTI2_Msk (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
14244 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
14245 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
14246 #define SYSCFG_EXTICR1_EXTI3_Msk (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
14247 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
14248
14249 /**
14250 * @brief EXTI0 configuration
14251 */
14252 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!<PA[0] pin */
14253 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
14254 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
14255 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
14256 #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
14257 #define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
14258 #define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
14259
14260 /**
14261 * @brief EXTI1 configuration
14262 */
14263 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!<PA[1] pin */
14264 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
14265 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
14266 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
14267 #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
14268 #define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
14269 #define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
14270
14271 /**
14272 * @brief EXTI2 configuration
14273 */
14274 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!<PA[2] pin */
14275 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
14276 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
14277 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
14278 #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
14279 #define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
14280 #define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
14281
14282 /**
14283 * @brief EXTI3 configuration
14284 */
14285 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!<PA[3] pin */
14286 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
14287 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
14288 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
14289 #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
14290 #define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
14291 #define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
14292
14293 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
14294 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
14295 #define SYSCFG_EXTICR2_EXTI4_Msk (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
14296 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
14297 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
14298 #define SYSCFG_EXTICR2_EXTI5_Msk (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
14299 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
14300 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
14301 #define SYSCFG_EXTICR2_EXTI6_Msk (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
14302 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
14303 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
14304 #define SYSCFG_EXTICR2_EXTI7_Msk (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
14305 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
14306
14307 /**
14308 * @brief EXTI4 configuration
14309 */
14310 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!<PA[4] pin */
14311 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
14312 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
14313 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
14314 #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
14315 #define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
14316 #define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
14317
14318 /**
14319 * @brief EXTI5 configuration
14320 */
14321 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!<PA[5] pin */
14322 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
14323 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
14324 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
14325 #define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
14326 #define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
14327 #define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
14328
14329 /**
14330 * @brief EXTI6 configuration
14331 */
14332 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!<PA[6] pin */
14333 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
14334 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
14335 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
14336 #define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
14337 #define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
14338 #define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
14339
14340 /**
14341 * @brief EXTI7 configuration
14342 */
14343 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!<PA[7] pin */
14344 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
14345 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
14346 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
14347 #define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
14348 #define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
14349 #define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
14350
14351 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
14352 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
14353 #define SYSCFG_EXTICR3_EXTI8_Msk (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
14354 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
14355 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
14356 #define SYSCFG_EXTICR3_EXTI9_Msk (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
14357 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
14358 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
14359 #define SYSCFG_EXTICR3_EXTI10_Msk (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
14360 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
14361 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
14362 #define SYSCFG_EXTICR3_EXTI11_Msk (0x7UL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
14363 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
14364
14365 /**
14366 * @brief EXTI8 configuration
14367 */
14368 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!<PA[8] pin */
14369 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
14370 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
14371 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
14372 #define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
14373 #define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
14374 #define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
14375
14376 /**
14377 * @brief EXTI9 configuration
14378 */
14379 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!<PA[9] pin */
14380 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
14381 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
14382 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
14383 #define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
14384 #define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
14385 #define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
14386
14387 /**
14388 * @brief EXTI10 configuration
14389 */
14390 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!<PA[10] pin */
14391 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
14392 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
14393 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
14394 #define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
14395 #define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
14396
14397 /**
14398 * @brief EXTI11 configuration
14399 */
14400 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!<PA[11] pin */
14401 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
14402 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
14403 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
14404 #define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
14405 #define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
14406
14407 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
14408 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
14409 #define SYSCFG_EXTICR4_EXTI12_Msk (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */
14410 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
14411 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
14412 #define SYSCFG_EXTICR4_EXTI13_Msk (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x00000070 */
14413 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
14414 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
14415 #define SYSCFG_EXTICR4_EXTI14_Msk (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000700 */
14416 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
14417 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
14418 #define SYSCFG_EXTICR4_EXTI15_Msk (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x00007000 */
14419 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
14420
14421 /**
14422 * @brief EXTI12 configuration
14423 */
14424 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!<PA[12] pin */
14425 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
14426 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
14427 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
14428 #define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
14429 #define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
14430
14431 /**
14432 * @brief EXTI13 configuration
14433 */
14434 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!<PA[13] pin */
14435 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
14436 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
14437 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
14438 #define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
14439 #define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
14440
14441 /**
14442 * @brief EXTI14 configuration
14443 */
14444 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!<PA[14] pin */
14445 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
14446 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
14447 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
14448 #define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
14449 #define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
14450
14451 /**
14452 * @brief EXTI15 configuration
14453 */
14454 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!<PA[15] pin */
14455 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
14456 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
14457 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
14458 #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
14459 #define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
14460
14461 /****************** Bit definition for SYSCFG_SCSR register ****************/
14462 #define SYSCFG_SCSR_CCMER_Pos (0U)
14463 #define SYSCFG_SCSR_CCMER_Msk (0x1UL << SYSCFG_SCSR_CCMER_Pos) /*!< 0x00000001 */
14464 #define SYSCFG_SCSR_CCMER SYSCFG_SCSR_CCMER_Msk /*!< CCMSRAM Erase Request */
14465 #define SYSCFG_SCSR_CCMBSY_Pos (1U)
14466 #define SYSCFG_SCSR_CCMBSY_Msk (0x1UL << SYSCFG_SCSR_CCMBSY_Pos) /*!< 0x00000002 */
14467 #define SYSCFG_SCSR_CCMBSY SYSCFG_SCSR_CCMBSY_Msk /*!< CCMSRAM Erase Ongoing */
14468
14469 /****************** Bit definition for SYSCFG_CFGR2 register ****************/
14470 #define SYSCFG_CFGR2_CLL_Pos (0U)
14471 #define SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */
14472 #define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Core Lockup Lock */
14473 #define SYSCFG_CFGR2_SPL_Pos (1U)
14474 #define SYSCFG_CFGR2_SPL_Msk (0x1UL << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */
14475 #define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< SRAM Parity Lock*/
14476 #define SYSCFG_CFGR2_PVDL_Pos (2U)
14477 #define SYSCFG_CFGR2_PVDL_Msk (0x1UL << SYSCFG_CFGR2_PVDL_Pos) /*!< 0x00000004 */
14478 #define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk /*!< PVD Lock */
14479 #define SYSCFG_CFGR2_ECCL_Pos (3U)
14480 #define SYSCFG_CFGR2_ECCL_Msk (0x1UL << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */
14481 #define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECC Lock*/
14482 #define SYSCFG_CFGR2_SPF_Pos (8U)
14483 #define SYSCFG_CFGR2_SPF_Msk (0x1UL << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */
14484 #define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM Parity Flag */
14485
14486 /****************** Bit definition for SYSCFG_SWPR register ****************/
14487 #define SYSCFG_SWPR_PAGE0_Pos (0U)
14488 #define SYSCFG_SWPR_PAGE0_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
14489 #define SYSCFG_SWPR_PAGE0 (uint32_t)(SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
14490 #define SYSCFG_SWPR_PAGE1_Pos (1U)
14491 #define SYSCFG_SWPR_PAGE1_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
14492 #define SYSCFG_SWPR_PAGE1 (uint32_t)(SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
14493 #define SYSCFG_SWPR_PAGE2_Pos (2U)
14494 #define SYSCFG_SWPR_PAGE2_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
14495 #define SYSCFG_SWPR_PAGE2 (uint32_t)(SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
14496 #define SYSCFG_SWPR_PAGE3_Pos (3U)
14497 #define SYSCFG_SWPR_PAGE3_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
14498 #define SYSCFG_SWPR_PAGE3 (uint32_t)(SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
14499 #define SYSCFG_SWPR_PAGE4_Pos (4U)
14500 #define SYSCFG_SWPR_PAGE4_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
14501 #define SYSCFG_SWPR_PAGE4 (uint32_t)(SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
14502 #define SYSCFG_SWPR_PAGE5_Pos (5U)
14503 #define SYSCFG_SWPR_PAGE5_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
14504 #define SYSCFG_SWPR_PAGE5 (uint32_t)(SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
14505 #define SYSCFG_SWPR_PAGE6_Pos (6U)
14506 #define SYSCFG_SWPR_PAGE6_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
14507 #define SYSCFG_SWPR_PAGE6 (uint32_t)(SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
14508 #define SYSCFG_SWPR_PAGE7_Pos (7U)
14509 #define SYSCFG_SWPR_PAGE7_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
14510 #define SYSCFG_SWPR_PAGE7 (uint32_t)(SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
14511 #define SYSCFG_SWPR_PAGE8_Pos (8U)
14512 #define SYSCFG_SWPR_PAGE8_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
14513 #define SYSCFG_SWPR_PAGE8 (uint32_t)(SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
14514 #define SYSCFG_SWPR_PAGE9_Pos (9U)
14515 #define SYSCFG_SWPR_PAGE9_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
14516 #define SYSCFG_SWPR_PAGE9 (uint32_t)(SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
14517 #define SYSCFG_SWPR_PAGE10_Pos (10U)
14518 #define SYSCFG_SWPR_PAGE10_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
14519 #define SYSCFG_SWPR_PAGE10 (uint32_t)(SYSCFG_SWPR_PAGE10_Msk) /*!< CCMSRAM Write protection page 10*/
14520 #define SYSCFG_SWPR_PAGE11_Pos (11U)
14521 #define SYSCFG_SWPR_PAGE11_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
14522 #define SYSCFG_SWPR_PAGE11 (uint32_t)(SYSCFG_SWPR_PAGE11_Msk) /*!< CCMSRAM Write protection page 11*/
14523 #define SYSCFG_SWPR_PAGE12_Pos (12U)
14524 #define SYSCFG_SWPR_PAGE12_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
14525 #define SYSCFG_SWPR_PAGE12 (uint32_t)(SYSCFG_SWPR_PAGE12_Msk) /*!< CCMSRAM Write protection page 12*/
14526 #define SYSCFG_SWPR_PAGE13_Pos (13U)
14527 #define SYSCFG_SWPR_PAGE13_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
14528 #define SYSCFG_SWPR_PAGE13 (uint32_t)(SYSCFG_SWPR_PAGE13_Msk) /*!< CCMSRAM Write protection page 13*/
14529 #define SYSCFG_SWPR_PAGE14_Pos (14U)
14530 #define SYSCFG_SWPR_PAGE14_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
14531 #define SYSCFG_SWPR_PAGE14 (uint32_t)(SYSCFG_SWPR_PAGE14_Msk) /*!< CCMSRAM Write protection page 14*/
14532 #define SYSCFG_SWPR_PAGE15_Pos (15U)
14533 #define SYSCFG_SWPR_PAGE15_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
14534 #define SYSCFG_SWPR_PAGE15 (uint32_t)(SYSCFG_SWPR_PAGE15_Msk) /*!< CCMSRAM Write protection page 15*/
14535 #define SYSCFG_SWPR_PAGE16_Pos (16U)
14536 #define SYSCFG_SWPR_PAGE16_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
14537 #define SYSCFG_SWPR_PAGE16 (uint32_t)(SYSCFG_SWPR_PAGE16_Msk) /*!< CCMSRAM Write protection page 16*/
14538 #define SYSCFG_SWPR_PAGE17_Pos (17U)
14539 #define SYSCFG_SWPR_PAGE17_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
14540 #define SYSCFG_SWPR_PAGE17 (uint32_t)(SYSCFG_SWPR_PAGE17_Msk) /*!< CCMSRAM Write protection page 17*/
14541 #define SYSCFG_SWPR_PAGE18_Pos (18U)
14542 #define SYSCFG_SWPR_PAGE18_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
14543 #define SYSCFG_SWPR_PAGE18 (uint32_t)(SYSCFG_SWPR_PAGE18_Msk) /*!< CCMSRAM Write protection page 18*/
14544 #define SYSCFG_SWPR_PAGE19_Pos (19U)
14545 #define SYSCFG_SWPR_PAGE19_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
14546 #define SYSCFG_SWPR_PAGE19 (uint32_t)(SYSCFG_SWPR_PAGE19_Msk) /*!< CCMSRAM Write protection page 19*/
14547 #define SYSCFG_SWPR_PAGE20_Pos (20U)
14548 #define SYSCFG_SWPR_PAGE20_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
14549 #define SYSCFG_SWPR_PAGE20 (uint32_t)(SYSCFG_SWPR_PAGE20_Msk) /*!< CCMSRAM Write protection page 20*/
14550 #define SYSCFG_SWPR_PAGE21_Pos (21U)
14551 #define SYSCFG_SWPR_PAGE21_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
14552 #define SYSCFG_SWPR_PAGE21 (uint32_t)(SYSCFG_SWPR_PAGE21_Msk) /*!< CCMSRAM Write protection page 21*/
14553 #define SYSCFG_SWPR_PAGE22_Pos (22U)
14554 #define SYSCFG_SWPR_PAGE22_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
14555 #define SYSCFG_SWPR_PAGE22 (uint32_t)(SYSCFG_SWPR_PAGE22_Msk) /*!< CCMSRAM Write protection page 22*/
14556 #define SYSCFG_SWPR_PAGE23_Pos (23U)
14557 #define SYSCFG_SWPR_PAGE23_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
14558 #define SYSCFG_SWPR_PAGE23 (uint32_t)(SYSCFG_SWPR_PAGE23_Msk) /*!< CCMSRAM Write protection page 23*/
14559 #define SYSCFG_SWPR_PAGE24_Pos (24U)
14560 #define SYSCFG_SWPR_PAGE24_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
14561 #define SYSCFG_SWPR_PAGE24 (uint32_t)(SYSCFG_SWPR_PAGE24_Msk) /*!< CCMSRAM Write protection page 24*/
14562 #define SYSCFG_SWPR_PAGE25_Pos (25U)
14563 #define SYSCFG_SWPR_PAGE25_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
14564 #define SYSCFG_SWPR_PAGE25 (uint32_t)(SYSCFG_SWPR_PAGE25_Msk) /*!< CCMSRAM Write protection page 25*/
14565 #define SYSCFG_SWPR_PAGE26_Pos (26U)
14566 #define SYSCFG_SWPR_PAGE26_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
14567 #define SYSCFG_SWPR_PAGE26 (uint32_t)(SYSCFG_SWPR_PAGE26_Msk) /*!< CCMSRAM Write protection page 26*/
14568 #define SYSCFG_SWPR_PAGE27_Pos (27U)
14569 #define SYSCFG_SWPR_PAGE27_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
14570 #define SYSCFG_SWPR_PAGE27 (uint32_t)(SYSCFG_SWPR_PAGE27_Msk) /*!< CCMSRAM Write protection page 27*/
14571 #define SYSCFG_SWPR_PAGE28_Pos (28U)
14572 #define SYSCFG_SWPR_PAGE28_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
14573 #define SYSCFG_SWPR_PAGE28 (uint32_t)(SYSCFG_SWPR_PAGE28_Msk) /*!< CCMSRAM Write protection page 28*/
14574 #define SYSCFG_SWPR_PAGE29_Pos (29U)
14575 #define SYSCFG_SWPR_PAGE29_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
14576 #define SYSCFG_SWPR_PAGE29 (uint32_t)(SYSCFG_SWPR_PAGE29_Msk) /*!< CCMSRAM Write protection page 29*/
14577 #define SYSCFG_SWPR_PAGE30_Pos (30U)
14578 #define SYSCFG_SWPR_PAGE30_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
14579 #define SYSCFG_SWPR_PAGE30 (uint32_t)(SYSCFG_SWPR_PAGE30_Msk) /*!< CCMSRAM Write protection page 30*/
14580 #define SYSCFG_SWPR_PAGE31_Pos (31U)
14581 #define SYSCFG_SWPR_PAGE31_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
14582 #define SYSCFG_SWPR_PAGE31 (uint32_t)(SYSCFG_SWPR_PAGE31_Msk) /*!< CCMSRAM Write protection page 31*/
14583 /****************** Bit definition for SYSCFG_SKR register ****************/
14584 #define SYSCFG_SKR_KEY_Pos (0U)
14585 #define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
14586 #define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk /*!< CCMSRAM write protection key for software erase */
14587
14588 /******************************************************************************/
14589 /* */
14590 /* TIM */
14591 /* */
14592 /******************************************************************************/
14593 /******************* Bit definition for TIM_CR1 register ********************/
14594 #define TIM_CR1_CEN_Pos (0U)
14595 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
14596 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
14597 #define TIM_CR1_UDIS_Pos (1U)
14598 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
14599 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
14600 #define TIM_CR1_URS_Pos (2U)
14601 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
14602 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
14603 #define TIM_CR1_OPM_Pos (3U)
14604 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
14605 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
14606 #define TIM_CR1_DIR_Pos (4U)
14607 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
14608 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
14609
14610 #define TIM_CR1_CMS_Pos (5U)
14611 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
14612 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
14613 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
14614 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
14615
14616 #define TIM_CR1_ARPE_Pos (7U)
14617 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
14618 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
14619
14620 #define TIM_CR1_CKD_Pos (8U)
14621 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
14622 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
14623 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
14624 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
14625
14626 #define TIM_CR1_UIFREMAP_Pos (11U)
14627 #define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
14628 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
14629
14630 #define TIM_CR1_DITHEN_Pos (12U)
14631 #define TIM_CR1_DITHEN_Msk (0x1UL << TIM_CR1_DITHEN_Pos) /*!< 0x00001000 */
14632 #define TIM_CR1_DITHEN TIM_CR1_DITHEN_Msk /*!<Dithering enable */
14633
14634 /******************* Bit definition for TIM_CR2 register ********************/
14635 #define TIM_CR2_CCPC_Pos (0U)
14636 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
14637 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
14638 #define TIM_CR2_CCUS_Pos (2U)
14639 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
14640 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
14641 #define TIM_CR2_CCDS_Pos (3U)
14642 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
14643 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
14644
14645 #define TIM_CR2_MMS_Pos (4U)
14646 #define TIM_CR2_MMS_Msk (0x200007UL << TIM_CR2_MMS_Pos) /*!< 0x02000070 */
14647 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[3:0] bits (Master Mode Selection) */
14648 #define TIM_CR2_MMS_0 (0x000001UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
14649 #define TIM_CR2_MMS_1 (0x000002UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
14650 #define TIM_CR2_MMS_2 (0x000004UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
14651 #define TIM_CR2_MMS_3 (0x200000UL << TIM_CR2_MMS_Pos) /*!< 0x02000000 */
14652
14653 #define TIM_CR2_TI1S_Pos (7U)
14654 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
14655 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
14656 #define TIM_CR2_OIS1_Pos (8U)
14657 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
14658 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
14659 #define TIM_CR2_OIS1N_Pos (9U)
14660 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
14661 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
14662 #define TIM_CR2_OIS2_Pos (10U)
14663 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
14664 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
14665 #define TIM_CR2_OIS2N_Pos (11U)
14666 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
14667 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
14668 #define TIM_CR2_OIS3_Pos (12U)
14669 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
14670 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
14671 #define TIM_CR2_OIS3N_Pos (13U)
14672 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
14673 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
14674 #define TIM_CR2_OIS4_Pos (14U)
14675 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
14676 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
14677 #define TIM_CR2_OIS4N_Pos (15U)
14678 #define TIM_CR2_OIS4N_Msk (0x1UL << TIM_CR2_OIS4N_Pos) /*!< 0x00008000 */
14679 #define TIM_CR2_OIS4N TIM_CR2_OIS4N_Msk /*!<Output Idle state 4 (OC4N output) */
14680 #define TIM_CR2_OIS5_Pos (16U)
14681 #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
14682 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */
14683 #define TIM_CR2_OIS6_Pos (18U)
14684 #define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
14685 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */
14686
14687 #define TIM_CR2_MMS2_Pos (20U)
14688 #define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
14689 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
14690 #define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
14691 #define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
14692 #define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
14693 #define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
14694
14695 /******************* Bit definition for TIM_SMCR register *******************/
14696 #define TIM_SMCR_SMS_Pos (0U)
14697 #define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
14698 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
14699 #define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
14700 #define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
14701 #define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
14702 #define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
14703
14704 #define TIM_SMCR_OCCS_Pos (3U)
14705 #define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
14706 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
14707
14708 #define TIM_SMCR_TS_Pos (4U)
14709 #define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) /*!< 0x00300070 */
14710 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
14711 #define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
14712 #define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
14713 #define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
14714 #define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos) /*!< 0x00100000 */
14715 #define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos) /*!< 0x00200000 */
14716
14717 #define TIM_SMCR_MSM_Pos (7U)
14718 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
14719 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
14720
14721 #define TIM_SMCR_ETF_Pos (8U)
14722 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
14723 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
14724 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
14725 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
14726 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
14727 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
14728
14729 #define TIM_SMCR_ETPS_Pos (12U)
14730 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
14731 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
14732 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
14733 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
14734
14735 #define TIM_SMCR_ECE_Pos (14U)
14736 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
14737 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
14738 #define TIM_SMCR_ETP_Pos (15U)
14739 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
14740 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
14741
14742 #define TIM_SMCR_SMSPE_Pos (24U)
14743 #define TIM_SMCR_SMSPE_Msk (0x1UL << TIM_SMCR_SMSPE_Pos) /*!< 0x02000000 */
14744 #define TIM_SMCR_SMSPE TIM_SMCR_SMSPE_Msk /*!<SMS preload enable */
14745
14746 #define TIM_SMCR_SMSPS_Pos (25U)
14747 #define TIM_SMCR_SMSPS_Msk (0x1UL << TIM_SMCR_SMSPS_Pos) /*!< 0x04000000 */
14748 #define TIM_SMCR_SMSPS TIM_SMCR_SMSPS_Msk /*!<SMS preload source */
14749
14750 /******************* Bit definition for TIM_DIER register *******************/
14751 #define TIM_DIER_UIE_Pos (0U)
14752 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
14753 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
14754 #define TIM_DIER_CC1IE_Pos (1U)
14755 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
14756 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
14757 #define TIM_DIER_CC2IE_Pos (2U)
14758 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
14759 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
14760 #define TIM_DIER_CC3IE_Pos (3U)
14761 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
14762 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
14763 #define TIM_DIER_CC4IE_Pos (4U)
14764 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
14765 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
14766 #define TIM_DIER_COMIE_Pos (5U)
14767 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
14768 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
14769 #define TIM_DIER_TIE_Pos (6U)
14770 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
14771 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
14772 #define TIM_DIER_BIE_Pos (7U)
14773 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
14774 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
14775 #define TIM_DIER_UDE_Pos (8U)
14776 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
14777 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
14778 #define TIM_DIER_CC1DE_Pos (9U)
14779 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
14780 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
14781 #define TIM_DIER_CC2DE_Pos (10U)
14782 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
14783 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
14784 #define TIM_DIER_CC3DE_Pos (11U)
14785 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
14786 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
14787 #define TIM_DIER_CC4DE_Pos (12U)
14788 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
14789 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
14790 #define TIM_DIER_COMDE_Pos (13U)
14791 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
14792 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
14793 #define TIM_DIER_TDE_Pos (14U)
14794 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
14795 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
14796 #define TIM_DIER_IDXIE_Pos (20U)
14797 #define TIM_DIER_IDXIE_Msk (0x1UL << TIM_DIER_IDXIE_Pos) /*!< 0x00100000 */
14798 #define TIM_DIER_IDXIE TIM_DIER_IDXIE_Msk /*!<Encoder index interrupt enable */
14799 #define TIM_DIER_DIRIE_Pos (21U)
14800 #define TIM_DIER_DIRIE_Msk (0x1UL << TIM_DIER_DIRIE_Pos) /*!< 0x00200000 */
14801 #define TIM_DIER_DIRIE TIM_DIER_DIRIE_Msk /*!<Encoder direction change interrupt enable */
14802 #define TIM_DIER_IERRIE_Pos (22U)
14803 #define TIM_DIER_IERRIE_Msk (0x1UL << TIM_DIER_IERRIE_Pos) /*!< 0x00400000 */
14804 #define TIM_DIER_IERRIE TIM_DIER_IERRIE_Msk /*!<Encoder index error enable */
14805 #define TIM_DIER_TERRIE_Pos (23U)
14806 #define TIM_DIER_TERRIE_Msk (0x1UL << TIM_DIER_TERRIE_Pos) /*!< 0x00800000 */
14807 #define TIM_DIER_TERRIE TIM_DIER_TERRIE_Msk /*!<Encoder transition error enable */
14808
14809 /******************** Bit definition for TIM_SR register ********************/
14810 #define TIM_SR_UIF_Pos (0U)
14811 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
14812 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
14813 #define TIM_SR_CC1IF_Pos (1U)
14814 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
14815 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
14816 #define TIM_SR_CC2IF_Pos (2U)
14817 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
14818 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
14819 #define TIM_SR_CC3IF_Pos (3U)
14820 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
14821 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
14822 #define TIM_SR_CC4IF_Pos (4U)
14823 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
14824 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
14825 #define TIM_SR_COMIF_Pos (5U)
14826 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
14827 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
14828 #define TIM_SR_TIF_Pos (6U)
14829 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
14830 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
14831 #define TIM_SR_BIF_Pos (7U)
14832 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
14833 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
14834 #define TIM_SR_B2IF_Pos (8U)
14835 #define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
14836 #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */
14837 #define TIM_SR_CC1OF_Pos (9U)
14838 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
14839 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
14840 #define TIM_SR_CC2OF_Pos (10U)
14841 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
14842 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
14843 #define TIM_SR_CC3OF_Pos (11U)
14844 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
14845 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
14846 #define TIM_SR_CC4OF_Pos (12U)
14847 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
14848 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
14849 #define TIM_SR_SBIF_Pos (13U)
14850 #define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
14851 #define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
14852 #define TIM_SR_CC5IF_Pos (16U)
14853 #define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
14854 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
14855 #define TIM_SR_CC6IF_Pos (17U)
14856 #define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
14857 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
14858 #define TIM_SR_IDXF_Pos (20U)
14859 #define TIM_SR_IDXF_Msk (0x1UL << TIM_SR_IDXF_Pos) /*!< 0x00100000 */
14860 #define TIM_SR_IDXF TIM_SR_IDXF_Msk /*!<Encoder index interrupt flag */
14861 #define TIM_SR_DIRF_Pos (21U)
14862 #define TIM_SR_DIRF_Msk (0x1UL << TIM_SR_DIRF_Pos) /*!< 0x00200000 */
14863 #define TIM_SR_DIRF TIM_SR_DIRF_Msk /*!<Encoder direction change interrupt flag */
14864 #define TIM_SR_IERRF_Pos (22U)
14865 #define TIM_SR_IERRF_Msk (0x1UL << TIM_SR_IERRF_Pos) /*!< 0x00400000 */
14866 #define TIM_SR_IERRF TIM_SR_IERRF_Msk /*!<Encoder index error flag */
14867 #define TIM_SR_TERRF_Pos (23U)
14868 #define TIM_SR_TERRF_Msk (0x1UL << TIM_SR_TERRF_Pos) /*!< 0x00800000 */
14869 #define TIM_SR_TERRF TIM_SR_TERRF_Msk /*!<Encoder transition error flag */
14870
14871 /******************* Bit definition for TIM_EGR register ********************/
14872 #define TIM_EGR_UG_Pos (0U)
14873 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
14874 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
14875 #define TIM_EGR_CC1G_Pos (1U)
14876 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
14877 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
14878 #define TIM_EGR_CC2G_Pos (2U)
14879 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
14880 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
14881 #define TIM_EGR_CC3G_Pos (3U)
14882 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
14883 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
14884 #define TIM_EGR_CC4G_Pos (4U)
14885 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
14886 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
14887 #define TIM_EGR_COMG_Pos (5U)
14888 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
14889 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
14890 #define TIM_EGR_TG_Pos (6U)
14891 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
14892 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
14893 #define TIM_EGR_BG_Pos (7U)
14894 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */
14895 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
14896 #define TIM_EGR_B2G_Pos (8U)
14897 #define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
14898 #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */
14899
14900
14901 /****************** Bit definition for TIM_CCMR1 register *******************/
14902 #define TIM_CCMR1_CC1S_Pos (0U)
14903 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
14904 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
14905 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
14906 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
14907
14908 #define TIM_CCMR1_OC1FE_Pos (2U)
14909 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
14910 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
14911 #define TIM_CCMR1_OC1PE_Pos (3U)
14912 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
14913 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
14914
14915 #define TIM_CCMR1_OC1M_Pos (4U)
14916 #define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
14917 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
14918 #define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
14919 #define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
14920 #define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
14921 #define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
14922
14923 #define TIM_CCMR1_OC1CE_Pos (7U)
14924 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
14925 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */
14926
14927 #define TIM_CCMR1_CC2S_Pos (8U)
14928 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
14929 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
14930 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
14931 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
14932
14933 #define TIM_CCMR1_OC2FE_Pos (10U)
14934 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
14935 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
14936 #define TIM_CCMR1_OC2PE_Pos (11U)
14937 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
14938 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
14939
14940 #define TIM_CCMR1_OC2M_Pos (12U)
14941 #define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
14942 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
14943 #define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
14944 #define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
14945 #define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
14946 #define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
14947
14948 #define TIM_CCMR1_OC2CE_Pos (15U)
14949 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
14950 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
14951
14952 /*----------------------------------------------------------------------------*/
14953 #define TIM_CCMR1_IC1PSC_Pos (2U)
14954 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
14955 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
14956 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
14957 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
14958
14959 #define TIM_CCMR1_IC1F_Pos (4U)
14960 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
14961 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
14962 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
14963 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
14964 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
14965 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
14966
14967 #define TIM_CCMR1_IC2PSC_Pos (10U)
14968 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
14969 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
14970 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
14971 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
14972
14973 #define TIM_CCMR1_IC2F_Pos (12U)
14974 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
14975 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
14976 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
14977 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
14978 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
14979 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
14980
14981 /****************** Bit definition for TIM_CCMR2 register *******************/
14982 #define TIM_CCMR2_CC3S_Pos (0U)
14983 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
14984 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
14985 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
14986 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
14987
14988 #define TIM_CCMR2_OC3FE_Pos (2U)
14989 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
14990 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
14991 #define TIM_CCMR2_OC3PE_Pos (3U)
14992 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
14993 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
14994
14995 #define TIM_CCMR2_OC3M_Pos (4U)
14996 #define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
14997 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
14998 #define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
14999 #define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
15000 #define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
15001 #define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
15002
15003 #define TIM_CCMR2_OC3CE_Pos (7U)
15004 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
15005 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
15006
15007 #define TIM_CCMR2_CC4S_Pos (8U)
15008 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
15009 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
15010 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
15011 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
15012
15013 #define TIM_CCMR2_OC4FE_Pos (10U)
15014 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
15015 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
15016 #define TIM_CCMR2_OC4PE_Pos (11U)
15017 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
15018 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
15019
15020 #define TIM_CCMR2_OC4M_Pos (12U)
15021 #define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
15022 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
15023 #define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
15024 #define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
15025 #define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
15026 #define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
15027
15028 #define TIM_CCMR2_OC4CE_Pos (15U)
15029 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
15030 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
15031
15032 /*----------------------------------------------------------------------------*/
15033 #define TIM_CCMR2_IC3PSC_Pos (2U)
15034 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
15035 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
15036 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
15037 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
15038
15039 #define TIM_CCMR2_IC3F_Pos (4U)
15040 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
15041 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
15042 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
15043 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
15044 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
15045 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
15046
15047 #define TIM_CCMR2_IC4PSC_Pos (10U)
15048 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
15049 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
15050 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
15051 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
15052
15053 #define TIM_CCMR2_IC4F_Pos (12U)
15054 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
15055 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
15056 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
15057 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
15058 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
15059 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
15060
15061 /****************** Bit definition for TIM_CCMR3 register *******************/
15062 #define TIM_CCMR3_OC5FE_Pos (2U)
15063 #define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
15064 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
15065 #define TIM_CCMR3_OC5PE_Pos (3U)
15066 #define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
15067 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
15068
15069 #define TIM_CCMR3_OC5M_Pos (4U)
15070 #define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
15071 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
15072 #define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
15073 #define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
15074 #define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
15075 #define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
15076
15077 #define TIM_CCMR3_OC5CE_Pos (7U)
15078 #define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
15079 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
15080
15081 #define TIM_CCMR3_OC6FE_Pos (10U)
15082 #define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
15083 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
15084 #define TIM_CCMR3_OC6PE_Pos (11U)
15085 #define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
15086 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */
15087
15088 #define TIM_CCMR3_OC6M_Pos (12U)
15089 #define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
15090 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
15091 #define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
15092 #define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
15093 #define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
15094 #define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
15095
15096 #define TIM_CCMR3_OC6CE_Pos (15U)
15097 #define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
15098 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */
15099
15100 /******************* Bit definition for TIM_CCER register *******************/
15101 #define TIM_CCER_CC1E_Pos (0U)
15102 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
15103 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
15104 #define TIM_CCER_CC1P_Pos (1U)
15105 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
15106 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
15107 #define TIM_CCER_CC1NE_Pos (2U)
15108 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
15109 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
15110 #define TIM_CCER_CC1NP_Pos (3U)
15111 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
15112 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
15113 #define TIM_CCER_CC2E_Pos (4U)
15114 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
15115 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
15116 #define TIM_CCER_CC2P_Pos (5U)
15117 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
15118 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
15119 #define TIM_CCER_CC2NE_Pos (6U)
15120 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
15121 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
15122 #define TIM_CCER_CC2NP_Pos (7U)
15123 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
15124 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
15125 #define TIM_CCER_CC3E_Pos (8U)
15126 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
15127 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
15128 #define TIM_CCER_CC3P_Pos (9U)
15129 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
15130 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
15131 #define TIM_CCER_CC3NE_Pos (10U)
15132 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
15133 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
15134 #define TIM_CCER_CC3NP_Pos (11U)
15135 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
15136 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
15137 #define TIM_CCER_CC4E_Pos (12U)
15138 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
15139 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
15140 #define TIM_CCER_CC4P_Pos (13U)
15141 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
15142 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
15143 #define TIM_CCER_CC4NE_Pos (14U)
15144 #define TIM_CCER_CC4NE_Msk (0x1UL << TIM_CCER_CC4NE_Pos) /*!< 0x00004000 */
15145 #define TIM_CCER_CC4NE TIM_CCER_CC4NE_Msk /*!<Capture/Compare 4 Complementary output enable */
15146 #define TIM_CCER_CC4NP_Pos (15U)
15147 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
15148 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
15149 #define TIM_CCER_CC5E_Pos (16U)
15150 #define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
15151 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
15152 #define TIM_CCER_CC5P_Pos (17U)
15153 #define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
15154 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
15155 #define TIM_CCER_CC6E_Pos (20U)
15156 #define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
15157 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
15158 #define TIM_CCER_CC6P_Pos (21U)
15159 #define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
15160 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
15161
15162 /******************* Bit definition for TIM_CNT register ********************/
15163 #define TIM_CNT_CNT_Pos (0U)
15164 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
15165 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
15166 #define TIM_CNT_UIFCPY_Pos (31U)
15167 #define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
15168 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
15169
15170 /******************* Bit definition for TIM_PSC register ********************/
15171 #define TIM_PSC_PSC_Pos (0U)
15172 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
15173 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
15174
15175 /******************* Bit definition for TIM_ARR register ********************/
15176 #define TIM_ARR_ARR_Pos (0U)
15177 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
15178 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
15179
15180 /******************* Bit definition for TIM_RCR register ********************/
15181 #define TIM_RCR_REP_Pos (0U)
15182 #define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
15183 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
15184
15185 /******************* Bit definition for TIM_CCR1 register *******************/
15186 #define TIM_CCR1_CCR1_Pos (0U)
15187 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
15188 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
15189
15190 /******************* Bit definition for TIM_CCR2 register *******************/
15191 #define TIM_CCR2_CCR2_Pos (0U)
15192 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
15193 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
15194
15195 /******************* Bit definition for TIM_CCR3 register *******************/
15196 #define TIM_CCR3_CCR3_Pos (0U)
15197 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
15198 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
15199
15200 /******************* Bit definition for TIM_CCR4 register *******************/
15201 #define TIM_CCR4_CCR4_Pos (0U)
15202 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
15203 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
15204
15205 /******************* Bit definition for TIM_CCR5 register *******************/
15206 #define TIM_CCR5_CCR5_Pos (0U)
15207 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
15208 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
15209 #define TIM_CCR5_GC5C1_Pos (29U)
15210 #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
15211 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
15212 #define TIM_CCR5_GC5C2_Pos (30U)
15213 #define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
15214 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
15215 #define TIM_CCR5_GC5C3_Pos (31U)
15216 #define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
15217 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
15218
15219 /******************* Bit definition for TIM_CCR6 register *******************/
15220 #define TIM_CCR6_CCR6_Pos (0U)
15221 #define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
15222 #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
15223
15224 /******************* Bit definition for TIM_BDTR register *******************/
15225 #define TIM_BDTR_DTG_Pos (0U)
15226 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
15227 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
15228 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
15229 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
15230 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
15231 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
15232 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
15233 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
15234 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
15235 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
15236
15237 #define TIM_BDTR_LOCK_Pos (8U)
15238 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
15239 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
15240 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
15241 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
15242
15243 #define TIM_BDTR_OSSI_Pos (10U)
15244 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
15245 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
15246 #define TIM_BDTR_OSSR_Pos (11U)
15247 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
15248 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
15249 #define TIM_BDTR_BKE_Pos (12U)
15250 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
15251 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */
15252 #define TIM_BDTR_BKP_Pos (13U)
15253 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
15254 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */
15255 #define TIM_BDTR_AOE_Pos (14U)
15256 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
15257 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
15258 #define TIM_BDTR_MOE_Pos (15U)
15259 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
15260 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
15261
15262 #define TIM_BDTR_BKF_Pos (16U)
15263 #define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
15264 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */
15265 #define TIM_BDTR_BK2F_Pos (20U)
15266 #define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
15267 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */
15268
15269 #define TIM_BDTR_BK2E_Pos (24U)
15270 #define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
15271 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */
15272 #define TIM_BDTR_BK2P_Pos (25U)
15273 #define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
15274 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */
15275
15276 #define TIM_BDTR_BKDSRM_Pos (26U)
15277 #define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
15278 #define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */
15279 #define TIM_BDTR_BK2DSRM_Pos (27U)
15280 #define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
15281 #define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */
15282
15283 #define TIM_BDTR_BKBID_Pos (28U)
15284 #define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
15285 #define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break BIDirectional */
15286 #define TIM_BDTR_BK2BID_Pos (29U)
15287 #define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
15288 #define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 BIDirectional */
15289
15290 /******************* Bit definition for TIM_DCR register ********************/
15291 #define TIM_DCR_DBA_Pos (0U)
15292 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
15293 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
15294 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
15295 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
15296 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
15297 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
15298 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
15299
15300 #define TIM_DCR_DBL_Pos (8U)
15301 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
15302 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
15303 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
15304 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
15305 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
15306 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
15307 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
15308
15309 /******************* Bit definition for TIM1_AF1 register *******************/
15310 #define TIM1_AF1_BKINE_Pos (0U)
15311 #define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */
15312 #define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BRK BKIN input enable */
15313 #define TIM1_AF1_BKCMP1E_Pos (1U)
15314 #define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
15315 #define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */
15316 #define TIM1_AF1_BKCMP2E_Pos (2U)
15317 #define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
15318 #define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */
15319 #define TIM1_AF1_BKCMP3E_Pos (3U)
15320 #define TIM1_AF1_BKCMP3E_Msk (0x1UL << TIM1_AF1_BKCMP3E_Pos) /*!< 0x00000008 */
15321 #define TIM1_AF1_BKCMP3E TIM1_AF1_BKCMP3E_Msk /*!<BRK COMP3 enable */
15322 #define TIM1_AF1_BKCMP4E_Pos (4U)
15323 #define TIM1_AF1_BKCMP4E_Msk (0x1UL << TIM1_AF1_BKCMP4E_Pos) /*!< 0x00000010 */
15324 #define TIM1_AF1_BKCMP4E TIM1_AF1_BKCMP4E_Msk /*!<BRK COMP4 enable */
15325 #define TIM1_AF1_BKCMP5E_Pos (5U)
15326 #define TIM1_AF1_BKCMP5E_Msk (0x1UL << TIM1_AF1_BKCMP5E_Pos) /*!< 0x00000020 */
15327 #define TIM1_AF1_BKCMP5E TIM1_AF1_BKCMP5E_Msk /*!<BRK COMP5 enable */
15328 #define TIM1_AF1_BKCMP6E_Pos (6U)
15329 #define TIM1_AF1_BKCMP6E_Msk (0x1UL << TIM1_AF1_BKCMP6E_Pos) /*!< 0x00000040 */
15330 #define TIM1_AF1_BKCMP6E TIM1_AF1_BKCMP6E_Msk /*!<BRK COMP6 enable */
15331 #define TIM1_AF1_BKCMP7E_Pos (7U)
15332 #define TIM1_AF1_BKCMP7E_Msk (0x1UL << TIM1_AF1_BKCMP7E_Pos) /*!< 0x00000080 */
15333 #define TIM1_AF1_BKCMP7E TIM1_AF1_BKCMP7E_Msk /*!<BRK COMP7 enable */
15334 #define TIM1_AF1_BKINP_Pos (9U)
15335 #define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */
15336 #define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
15337 #define TIM1_AF1_BKCMP1P_Pos (10U)
15338 #define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
15339 #define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
15340 #define TIM1_AF1_BKCMP2P_Pos (11U)
15341 #define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
15342 #define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
15343 #define TIM1_AF1_BKCMP3P_Pos (12U)
15344 #define TIM1_AF1_BKCMP3P_Msk (0x1UL << TIM1_AF1_BKCMP3P_Pos) /*!< 0x00001000 */
15345 #define TIM1_AF1_BKCMP3P TIM1_AF1_BKCMP3P_Msk /*!<BRK COMP3 input polarity */
15346 #define TIM1_AF1_BKCMP4P_Pos (13U)
15347 #define TIM1_AF1_BKCMP4P_Msk (0x1UL << TIM1_AF1_BKCMP4P_Pos) /*!< 0x00002000 */
15348 #define TIM1_AF1_BKCMP4P TIM1_AF1_BKCMP4P_Msk /*!<BRK COMP4 input polarity */
15349 #define TIM1_AF1_ETRSEL_Pos (14U)
15350 #define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
15351 #define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
15352 #define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00004000 */
15353 #define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */
15354 #define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00010000 */
15355 #define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */
15356
15357 /******************* Bit definition for TIM1_AF2 register *********************/
15358 #define TIM1_AF2_BK2INE_Pos (0U)
15359 #define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */
15360 #define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BRK2 BKIN input enable */
15361 #define TIM1_AF2_BK2CMP1E_Pos (1U)
15362 #define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */
15363 #define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
15364 #define TIM1_AF2_BK2CMP2E_Pos (2U)
15365 #define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */
15366 #define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
15367 #define TIM1_AF2_BK2CMP3E_Pos (3U)
15368 #define TIM1_AF2_BK2CMP3E_Msk (0x1UL << TIM1_AF2_BK2CMP3E_Pos) /*!< 0x00000008 */
15369 #define TIM1_AF2_BK2CMP3E TIM1_AF2_BK2CMP3E_Msk /*!<BRK2 COMP3 enable */
15370 #define TIM1_AF2_BK2CMP4E_Pos (4U)
15371 #define TIM1_AF2_BK2CMP4E_Msk (0x1UL << TIM1_AF2_BK2CMP4E_Pos) /*!< 0x00000010 */
15372 #define TIM1_AF2_BK2CMP4E TIM1_AF2_BK2CMP4E_Msk /*!<BRK2 COMP4 enable */
15373 #define TIM1_AF2_BK2CMP5E_Pos (5U)
15374 #define TIM1_AF2_BK2CMP5E_Msk (0x1UL << TIM1_AF2_BK2CMP5E_Pos) /*!< 0x00000020 */
15375 #define TIM1_AF2_BK2CMP5E TIM1_AF2_BK2CMP5E_Msk /*!<BRK2 COMP5 enable */
15376 #define TIM1_AF2_BK2CMP6E_Pos (6U)
15377 #define TIM1_AF2_BK2CMP6E_Msk (0x1UL << TIM1_AF2_BK2CMP6E_Pos) /*!< 0x00000040 */
15378 #define TIM1_AF2_BK2CMP6E TIM1_AF2_BK2CMP6E_Msk /*!<BRK2 COMP6 enable */
15379 #define TIM1_AF2_BK2CMP7E_Pos (7U)
15380 #define TIM1_AF2_BK2CMP7E_Msk (0x1UL << TIM1_AF2_BK2CMP7E_Pos) /*!< 0x00000080 */
15381 #define TIM1_AF2_BK2CMP7E TIM1_AF2_BK2CMP7E_Msk /*!<BRK2 COMP7 enable */
15382 #define TIM1_AF2_BK2INP_Pos (9U)
15383 #define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */
15384 #define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRK2 BKIN input polarity */
15385 #define TIM1_AF2_BK2CMP1P_Pos (10U)
15386 #define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */
15387 #define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
15388 #define TIM1_AF2_BK2CMP2P_Pos (11U)
15389 #define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */
15390 #define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
15391 #define TIM1_AF2_BK2CMP3P_Pos (12U)
15392 #define TIM1_AF2_BK2CMP3P_Msk (0x1UL << TIM1_AF2_BK2CMP3P_Pos) /*!< 0x00000400 */
15393 #define TIM1_AF2_BK2CMP3P TIM1_AF2_BK2CMP3P_Msk /*!<BRK2 COMP3 input polarity */
15394 #define TIM1_AF2_BK2CMP4P_Pos (13U)
15395 #define TIM1_AF2_BK2CMP4P_Msk (0x1UL << TIM1_AF2_BK2CMP4P_Pos) /*!< 0x00000800 */
15396 #define TIM1_AF2_BK2CMP4P TIM1_AF2_BK2CMP4P_Msk /*!<BRK2 COMP4 input polarity */
15397 #define TIM1_AF2_OCRSEL_Pos (16U)
15398 #define TIM1_AF2_OCRSEL_Msk (0x7UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00070000 */
15399 #define TIM1_AF2_OCRSEL TIM1_AF2_OCRSEL_Msk /*!<BRK2 COMP2 input polarity */
15400 #define TIM1_AF2_OCRSEL_0 (0x1UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00010000 */
15401 #define TIM1_AF2_OCRSEL_1 (0x2UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00020000 */
15402 #define TIM1_AF2_OCRSEL_2 (0x4UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00040000 */
15403
15404 /******************* Bit definition for TIM_OR register *********************/
15405 #define TIM_OR_HSE32EN_Pos (0U)
15406 #define TIM_OR_HSE32EN_Msk (0x1UL << TIM_OR_HSE32EN_Pos) /*!< 0x00000001 */
15407 #define TIM_OR_HSE32EN TIM_OR_HSE32EN_Msk /*!< HSE/32 clock enable */
15408
15409 /******************* Bit definition for TIM_TISEL register *********************/
15410 #define TIM_TISEL_TI1SEL_Pos (0U)
15411 #define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
15412 #define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
15413 #define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
15414 #define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
15415 #define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
15416 #define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
15417
15418 #define TIM_TISEL_TI2SEL_Pos (8U)
15419 #define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
15420 #define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
15421 #define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
15422 #define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
15423 #define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
15424 #define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
15425
15426 #define TIM_TISEL_TI3SEL_Pos (16U)
15427 #define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
15428 #define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/
15429 #define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
15430 #define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
15431 #define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
15432 #define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
15433
15434 #define TIM_TISEL_TI4SEL_Pos (24U)
15435 #define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
15436 #define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/
15437 #define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
15438 #define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
15439 #define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
15440 #define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
15441
15442 /******************* Bit definition for TIM_DTR2 register *********************/
15443 #define TIM_DTR2_DTGF_Pos (0U)
15444 #define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F */
15445 #define TIM_DTR2_DTGF TIM_DTR2_DTGF_Msk /*!<DTGF[7:0] bits (Deadtime falling edge generator setup)*/
15446 #define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001 */
15447 #define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002 */
15448 #define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004 */
15449 #define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008 */
15450 #define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010 */
15451 #define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020 */
15452 #define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040 */
15453 #define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080 */
15454
15455 #define TIM_DTR2_DTAE_Pos (16U)
15456 #define TIM_DTR2_DTAE_Msk (0x1UL << TIM_DTR2_DTAE_Pos) /*!< 0x00004000 */
15457 #define TIM_DTR2_DTAE TIM_DTR2_DTAE_Msk /*!<Deadtime asymmetric enable */
15458 #define TIM_DTR2_DTPE_Pos (17U)
15459 #define TIM_DTR2_DTPE_Msk (0x1UL << TIM_DTR2_DTPE_Pos) /*!< 0x00008000 */
15460 #define TIM_DTR2_DTPE TIM_DTR2_DTPE_Msk /*!<Deadtime prelaod enable */
15461
15462 /******************* Bit definition for TIM_ECR register *********************/
15463 #define TIM_ECR_IE_Pos (0U)
15464 #define TIM_ECR_IE_Msk (0x1UL << TIM_ECR_IE_Pos) /*!< 0x00000001 */
15465 #define TIM_ECR_IE TIM_ECR_IE_Msk /*!<Index enable */
15466
15467 #define TIM_ECR_IDIR_Pos (1U)
15468 #define TIM_ECR_IDIR_Msk (0x3UL << TIM_ECR_IDIR_Pos) /*!< 0x00000006 */
15469 #define TIM_ECR_IDIR TIM_ECR_IDIR_Msk /*!<IDIR[1:0] bits (Index direction)*/
15470 #define TIM_ECR_IDIR_0 (0x01UL << TIM_ECR_IDIR_Pos) /*!< 0x00000001 */
15471 #define TIM_ECR_IDIR_1 (0x02UL << TIM_ECR_IDIR_Pos) /*!< 0x00000002 */
15472
15473 #define TIM_ECR_FIDX_Pos (5U)
15474 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
15475 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index enable */
15476
15477 #define TIM_ECR_IPOS_Pos (6U)
15478 #define TIM_ECR_IPOS_Msk (0x3UL << TIM_ECR_IPOS_Pos) /*!< 0x0000000C0 */
15479 #define TIM_ECR_IPOS TIM_ECR_IPOS_Msk /*!<IPOS[1:0] bits (Index positioning)*/
15480 #define TIM_ECR_IPOS_0 (0x01UL << TIM_ECR_IPOS_Pos) /*!< 0x00000001 */
15481 #define TIM_ECR_IPOS_1 (0x02UL << TIM_ECR_IPOS_Pos) /*!< 0x00000002 */
15482
15483 #define TIM_ECR_PW_Pos (16U)
15484 #define TIM_ECR_PW_Msk (0xFFUL << TIM_ECR_PW_Pos) /*!< 0x00FF0000 */
15485 #define TIM_ECR_PW TIM_ECR_PW_Msk /*!<PW[7:0] bits (Pulse width)*/
15486 #define TIM_ECR_PW_0 (0x01UL << TIM_ECR_PW_Pos) /*!< 0x00010000 */
15487 #define TIM_ECR_PW_1 (0x02UL << TIM_ECR_PW_Pos) /*!< 0x00020000 */
15488 #define TIM_ECR_PW_2 (0x04UL << TIM_ECR_PW_Pos) /*!< 0x00040000 */
15489 #define TIM_ECR_PW_3 (0x08UL << TIM_ECR_PW_Pos) /*!< 0x00080000 */
15490 #define TIM_ECR_PW_4 (0x10UL << TIM_ECR_PW_Pos) /*!< 0x00100000 */
15491 #define TIM_ECR_PW_5 (0x20UL << TIM_ECR_PW_Pos) /*!< 0x00200000 */
15492 #define TIM_ECR_PW_6 (0x40UL << TIM_ECR_PW_Pos) /*!< 0x00400000 */
15493 #define TIM_ECR_PW_7 (0x80UL << TIM_ECR_PW_Pos) /*!< 0x00800000 */
15494
15495 #define TIM_ECR_PWPRSC_Pos (24U)
15496 #define TIM_ECR_PWPRSC_Msk (0x7UL << TIM_ECR_PWPRSC_Pos) /*!< 0x07000000 */
15497 #define TIM_ECR_PWPRSC TIM_ECR_PWPRSC_Msk /*!<PWPRSC[2:0] bits (Pulse width prescaler)*/
15498 #define TIM_ECR_PWPRSC_0 (0x01UL << TIM_ECR_PWPRSC_Pos) /*!< 0x01000000 */
15499 #define TIM_ECR_PWPRSC_1 (0x02UL << TIM_ECR_PWPRSC_Pos) /*!< 0x02000000 */
15500 #define TIM_ECR_PWPRSC_2 (0x04UL << TIM_ECR_PWPRSC_Pos) /*!< 0x04000000 */
15501
15502 /******************* Bit definition for TIM_DMAR register *******************/
15503 #define TIM_DMAR_DMAB_Pos (0U)
15504 #define TIM_DMAR_DMAB_Msk (0xFFFFFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0xFFFFFFFF */
15505 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
15506
15507 /******************************************************************************/
15508 /* */
15509 /* Low Power Timer (LPTIM) */
15510 /* */
15511 /******************************************************************************/
15512 /****************** Bit definition for LPTIM_ISR register *******************/
15513 #define LPTIM_ISR_CMPM_Pos (0U)
15514 #define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
15515 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
15516 #define LPTIM_ISR_ARRM_Pos (1U)
15517 #define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
15518 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
15519 #define LPTIM_ISR_EXTTRIG_Pos (2U)
15520 #define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
15521 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
15522 #define LPTIM_ISR_CMPOK_Pos (3U)
15523 #define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
15524 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
15525 #define LPTIM_ISR_ARROK_Pos (4U)
15526 #define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
15527 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
15528 #define LPTIM_ISR_UP_Pos (5U)
15529 #define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
15530 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
15531 #define LPTIM_ISR_DOWN_Pos (6U)
15532 #define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
15533 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
15534
15535 /****************** Bit definition for LPTIM_ICR register *******************/
15536 #define LPTIM_ICR_CMPMCF_Pos (0U)
15537 #define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
15538 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
15539 #define LPTIM_ICR_ARRMCF_Pos (1U)
15540 #define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
15541 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
15542 #define LPTIM_ICR_EXTTRIGCF_Pos (2U)
15543 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
15544 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
15545 #define LPTIM_ICR_CMPOKCF_Pos (3U)
15546 #define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
15547 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
15548 #define LPTIM_ICR_ARROKCF_Pos (4U)
15549 #define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
15550 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
15551 #define LPTIM_ICR_UPCF_Pos (5U)
15552 #define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
15553 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
15554 #define LPTIM_ICR_DOWNCF_Pos (6U)
15555 #define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
15556 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
15557
15558 /****************** Bit definition for LPTIM_IER register ********************/
15559 #define LPTIM_IER_CMPMIE_Pos (0U)
15560 #define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
15561 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
15562 #define LPTIM_IER_ARRMIE_Pos (1U)
15563 #define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
15564 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
15565 #define LPTIM_IER_EXTTRIGIE_Pos (2U)
15566 #define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
15567 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
15568 #define LPTIM_IER_CMPOKIE_Pos (3U)
15569 #define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
15570 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
15571 #define LPTIM_IER_ARROKIE_Pos (4U)
15572 #define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
15573 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
15574 #define LPTIM_IER_UPIE_Pos (5U)
15575 #define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
15576 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
15577 #define LPTIM_IER_DOWNIE_Pos (6U)
15578 #define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
15579 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
15580
15581 /****************** Bit definition for LPTIM_CFGR register *******************/
15582 #define LPTIM_CFGR_CKSEL_Pos (0U)
15583 #define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
15584 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
15585
15586 #define LPTIM_CFGR_CKPOL_Pos (1U)
15587 #define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
15588 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
15589 #define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
15590 #define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
15591
15592 #define LPTIM_CFGR_CKFLT_Pos (3U)
15593 #define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
15594 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
15595 #define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
15596 #define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
15597
15598 #define LPTIM_CFGR_TRGFLT_Pos (6U)
15599 #define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
15600 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
15601 #define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
15602 #define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
15603
15604 #define LPTIM_CFGR_PRESC_Pos (9U)
15605 #define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
15606 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
15607 #define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
15608 #define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
15609 #define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
15610
15611 #define LPTIM_CFGR_TRIGSEL_Pos (13U)
15612 #define LPTIM_CFGR_TRIGSEL_Msk (0x10007UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0200E000 */
15613 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
15614 #define LPTIM_CFGR_TRIGSEL_0 (0x00001UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
15615 #define LPTIM_CFGR_TRIGSEL_1 (0x00002UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
15616 #define LPTIM_CFGR_TRIGSEL_2 (0x00004UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
15617 #define LPTIM_CFGR_TRIGSEL_3 (0x10000UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x02000000 */
15618
15619 #define LPTIM_CFGR_TRIGEN_Pos (17U)
15620 #define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
15621 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
15622 #define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
15623 #define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
15624
15625 #define LPTIM_CFGR_TIMOUT_Pos (19U)
15626 #define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
15627 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
15628 #define LPTIM_CFGR_WAVE_Pos (20U)
15629 #define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
15630 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
15631 #define LPTIM_CFGR_WAVPOL_Pos (21U)
15632 #define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
15633 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
15634 #define LPTIM_CFGR_PRELOAD_Pos (22U)
15635 #define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
15636 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
15637 #define LPTIM_CFGR_COUNTMODE_Pos (23U)
15638 #define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
15639 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
15640 #define LPTIM_CFGR_ENC_Pos (24U)
15641 #define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
15642 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
15643
15644 /****************** Bit definition for LPTIM_CR register ********************/
15645 #define LPTIM_CR_ENABLE_Pos (0U)
15646 #define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
15647 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
15648 #define LPTIM_CR_SNGSTRT_Pos (1U)
15649 #define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
15650 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
15651 #define LPTIM_CR_CNTSTRT_Pos (2U)
15652 #define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
15653 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
15654 #define LPTIM_CR_COUNTRST_Pos (3U)
15655 #define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */
15656 #define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Counter reset */
15657 #define LPTIM_CR_RSTARE_Pos (4U)
15658 #define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */
15659 #define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Reset after read enable */
15660
15661 /****************** Bit definition for LPTIM_CMP register *******************/
15662 #define LPTIM_CMP_CMP_Pos (0U)
15663 #define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
15664 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
15665
15666 /****************** Bit definition for LPTIM_ARR register *******************/
15667 #define LPTIM_ARR_ARR_Pos (0U)
15668 #define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
15669 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
15670
15671 /****************** Bit definition for LPTIM_CNT register *******************/
15672 #define LPTIM_CNT_CNT_Pos (0U)
15673 #define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
15674 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
15675
15676 /****************** Bit definition for LPTIM_OR register *******************/
15677 #define LPTIM_OR_IN1_Pos (0U)
15678 #define LPTIM_OR_IN1_Msk (0xDUL << LPTIM_OR_IN1_Pos) /*!< 0x0000000D */
15679 #define LPTIM_OR_IN1 LPTIM_OR_IN1_Msk /*!< IN1[2:0] bits (Remap selection) */
15680 #define LPTIM_OR_IN1_0 (0x1UL << LPTIM_OR_IN1_Pos) /*!< 0x00000001 */
15681 #define LPTIM_OR_IN1_1 (0x4UL << LPTIM_OR_IN1_Pos) /*!< 0x00000004 */
15682 #define LPTIM_OR_IN1_2 (0x8UL << LPTIM_OR_IN1_Pos) /*!< 0x00000008 */
15683
15684 #define LPTIM_OR_IN2_Pos (1U)
15685 #define LPTIM_OR_IN2_Msk (0x19UL << LPTIM_OR_IN2_Pos) /*!< 0x00000032 */
15686 #define LPTIM_OR_IN2 LPTIM_OR_IN2_Msk /*!< IN2[2:0] bits (Remap selection) */
15687 #define LPTIM_OR_IN2_0 (0x1UL << LPTIM_OR_IN2_Pos) /*!< 0x00000002 */
15688 #define LPTIM_OR_IN2_1 (0x8UL << LPTIM_OR_IN2_Pos) /*!< 0x00000010 */
15689 #define LPTIM_OR_IN2_2 (0x10UL << LPTIM_OR_IN2_Pos) /*!< 0x00000020 */
15690 /******************************************************************************/
15691 /* */
15692 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
15693 /* */
15694 /******************************************************************************/
15695 /****************** Bit definition for USART_CR1 register *******************/
15696 #define USART_CR1_UE_Pos (0U)
15697 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
15698 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
15699 #define USART_CR1_UESM_Pos (1U)
15700 #define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
15701 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
15702 #define USART_CR1_RE_Pos (2U)
15703 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
15704 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
15705 #define USART_CR1_TE_Pos (3U)
15706 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
15707 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
15708 #define USART_CR1_IDLEIE_Pos (4U)
15709 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
15710 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
15711 #define USART_CR1_RXNEIE_Pos (5U)
15712 #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
15713 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
15714 #define USART_CR1_RXNEIE_RXFNEIE_Pos USART_CR1_RXNEIE_Pos
15715 #define USART_CR1_RXNEIE_RXFNEIE_Msk USART_CR1_RXNEIE_Msk /*!< 0x00000020 */
15716 #define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_Msk /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
15717 #define USART_CR1_TCIE_Pos (6U)
15718 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
15719 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
15720 #define USART_CR1_TXEIE_Pos (7U)
15721 #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
15722 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
15723 #define USART_CR1_TXEIE_TXFNFIE_Pos USART_CR1_TXEIE_Pos
15724 #define USART_CR1_TXEIE_TXFNFIE_Msk USART_CR1_TXEIE_Msk /*!< 0x00000080 */
15725 #define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_Msk /*!< TXE and TX FIFO Not Full Interrupt Enable */
15726 #define USART_CR1_PEIE_Pos (8U)
15727 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
15728 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
15729 #define USART_CR1_PS_Pos (9U)
15730 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
15731 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
15732 #define USART_CR1_PCE_Pos (10U)
15733 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
15734 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
15735 #define USART_CR1_WAKE_Pos (11U)
15736 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
15737 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
15738 #define USART_CR1_M_Pos (12U)
15739 #define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
15740 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
15741 #define USART_CR1_M0_Pos (12U)
15742 #define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
15743 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
15744 #define USART_CR1_MME_Pos (13U)
15745 #define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
15746 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
15747 #define USART_CR1_CMIE_Pos (14U)
15748 #define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
15749 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
15750 #define USART_CR1_OVER8_Pos (15U)
15751 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
15752 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
15753 #define USART_CR1_DEDT_Pos (16U)
15754 #define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
15755 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
15756 #define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
15757 #define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
15758 #define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
15759 #define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
15760 #define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
15761 #define USART_CR1_DEAT_Pos (21U)
15762 #define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
15763 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
15764 #define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
15765 #define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
15766 #define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
15767 #define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
15768 #define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
15769 #define USART_CR1_RTOIE_Pos (26U)
15770 #define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
15771 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
15772 #define USART_CR1_EOBIE_Pos (27U)
15773 #define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
15774 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
15775 #define USART_CR1_M1_Pos (28U)
15776 #define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
15777 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
15778 #define USART_CR1_FIFOEN_Pos (29U)
15779 #define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */
15780 #define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */
15781 #define USART_CR1_TXFEIE_Pos (30U)
15782 #define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */
15783 #define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */
15784 #define USART_CR1_RXFFIE_Pos (31U)
15785 #define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */
15786 #define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */
15787
15788 /****************** Bit definition for USART_CR2 register *******************/
15789 #define USART_CR2_SLVEN_Pos (0U)
15790 #define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */
15791 #define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode enable */
15792 #define USART_CR2_DIS_NSS_Pos (3U)
15793 #define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */
15794 #define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< Slave Select (NSS) pin management */
15795 #define USART_CR2_ADDM7_Pos (4U)
15796 #define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
15797 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
15798 #define USART_CR2_LBDL_Pos (5U)
15799 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
15800 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
15801 #define USART_CR2_LBDIE_Pos (6U)
15802 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
15803 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
15804 #define USART_CR2_LBCL_Pos (8U)
15805 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
15806 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
15807 #define USART_CR2_CPHA_Pos (9U)
15808 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
15809 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
15810 #define USART_CR2_CPOL_Pos (10U)
15811 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
15812 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
15813 #define USART_CR2_CLKEN_Pos (11U)
15814 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
15815 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
15816 #define USART_CR2_STOP_Pos (12U)
15817 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
15818 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
15819 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
15820 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
15821 #define USART_CR2_LINEN_Pos (14U)
15822 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
15823 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
15824 #define USART_CR2_SWAP_Pos (15U)
15825 #define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
15826 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
15827 #define USART_CR2_RXINV_Pos (16U)
15828 #define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
15829 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
15830 #define USART_CR2_TXINV_Pos (17U)
15831 #define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
15832 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
15833 #define USART_CR2_DATAINV_Pos (18U)
15834 #define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
15835 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
15836 #define USART_CR2_MSBFIRST_Pos (19U)
15837 #define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
15838 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
15839 #define USART_CR2_ABREN_Pos (20U)
15840 #define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
15841 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
15842 #define USART_CR2_ABRMODE_Pos (21U)
15843 #define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
15844 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
15845 #define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
15846 #define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
15847 #define USART_CR2_RTOEN_Pos (23U)
15848 #define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
15849 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
15850 #define USART_CR2_ADD_Pos (24U)
15851 #define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
15852 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
15853
15854 /****************** Bit definition for USART_CR3 register *******************/
15855 #define USART_CR3_EIE_Pos (0U)
15856 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
15857 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
15858 #define USART_CR3_IREN_Pos (1U)
15859 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
15860 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
15861 #define USART_CR3_IRLP_Pos (2U)
15862 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
15863 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
15864 #define USART_CR3_HDSEL_Pos (3U)
15865 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
15866 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
15867 #define USART_CR3_NACK_Pos (4U)
15868 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
15869 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
15870 #define USART_CR3_SCEN_Pos (5U)
15871 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
15872 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
15873 #define USART_CR3_DMAR_Pos (6U)
15874 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
15875 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
15876 #define USART_CR3_DMAT_Pos (7U)
15877 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
15878 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
15879 #define USART_CR3_RTSE_Pos (8U)
15880 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
15881 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
15882 #define USART_CR3_CTSE_Pos (9U)
15883 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
15884 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
15885 #define USART_CR3_CTSIE_Pos (10U)
15886 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
15887 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
15888 #define USART_CR3_ONEBIT_Pos (11U)
15889 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
15890 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
15891 #define USART_CR3_OVRDIS_Pos (12U)
15892 #define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
15893 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
15894 #define USART_CR3_DDRE_Pos (13U)
15895 #define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
15896 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
15897 #define USART_CR3_DEM_Pos (14U)
15898 #define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
15899 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
15900 #define USART_CR3_DEP_Pos (15U)
15901 #define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
15902 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
15903 #define USART_CR3_SCARCNT_Pos (17U)
15904 #define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
15905 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
15906 #define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
15907 #define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
15908 #define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
15909 #define USART_CR3_WUS_Pos (20U)
15910 #define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
15911 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
15912 #define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
15913 #define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
15914 #define USART_CR3_WUFIE_Pos (22U)
15915 #define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
15916 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
15917 #define USART_CR3_TXFTIE_Pos (23U)
15918 #define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */
15919 #define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */
15920 #define USART_CR3_TCBGTIE_Pos (24U)
15921 #define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
15922 #define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */
15923 #define USART_CR3_RXFTCFG_Pos (25U)
15924 #define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */
15925 #define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFIFO FIFO threshold configuration */
15926 #define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */
15927 #define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */
15928 #define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */
15929 #define USART_CR3_RXFTIE_Pos (28U)
15930 #define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */
15931 #define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */
15932 #define USART_CR3_TXFTCFG_Pos (29U)
15933 #define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */
15934 #define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFIFO threshold configuration */
15935 #define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */
15936 #define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */
15937 #define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */
15938
15939 /****************** Bit definition for USART_BRR register *******************/
15940 #define USART_BRR_LPUART_Pos (0U)
15941 #define USART_BRR_LPUART_Msk (0xFFFFFUL << USART_BRR_LPUART_Pos) /*!< 0x000FFFFF */
15942 #define USART_BRR_LPUART USART_BRR_LPUART_Msk /*!< LPUART Baud rate register [19:0] */
15943 #define USART_BRR_BRR_Pos (0U)
15944 #define USART_BRR_BRR_Msk (0xFFFFUL << USART_BRR_BRR_Pos) /*!< 0x0000FFFF */
15945 #define USART_BRR_BRR USART_BRR_BRR_Msk /*!< USART Baud rate register [15:0] */
15946
15947 /****************** Bit definition for USART_GTPR register ******************/
15948 #define USART_GTPR_PSC_Pos (0U)
15949 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
15950 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
15951 #define USART_GTPR_GT_Pos (8U)
15952 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
15953 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
15954
15955 /******************* Bit definition for USART_RTOR register *****************/
15956 #define USART_RTOR_RTO_Pos (0U)
15957 #define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
15958 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
15959 #define USART_RTOR_BLEN_Pos (24U)
15960 #define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
15961 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
15962
15963 /******************* Bit definition for USART_RQR register ******************/
15964 #define USART_RQR_ABRRQ_Pos (0U)
15965 #define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
15966 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
15967 #define USART_RQR_SBKRQ_Pos (1U)
15968 #define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
15969 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
15970 #define USART_RQR_MMRQ_Pos (2U)
15971 #define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
15972 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
15973 #define USART_RQR_RXFRQ_Pos (3U)
15974 #define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
15975 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
15976 #define USART_RQR_TXFRQ_Pos (4U)
15977 #define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
15978 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
15979
15980 /******************* Bit definition for USART_ISR register ******************/
15981 #define USART_ISR_PE_Pos (0U)
15982 #define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
15983 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
15984 #define USART_ISR_FE_Pos (1U)
15985 #define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
15986 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
15987 #define USART_ISR_NE_Pos (2U)
15988 #define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
15989 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
15990 #define USART_ISR_ORE_Pos (3U)
15991 #define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
15992 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
15993 #define USART_ISR_IDLE_Pos (4U)
15994 #define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
15995 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
15996 #define USART_ISR_RXNE_Pos (5U)
15997 #define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
15998 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
15999 #define USART_ISR_RXNE_RXFNE_Pos USART_ISR_RXNE_Pos
16000 #define USART_ISR_RXNE_RXFNE_Msk USART_ISR_RXNE_Msk /*!< 0x00000020 */
16001 #define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_Msk /*!< Read Data Register or RX FIFO Not Empty */
16002 #define USART_ISR_TC_Pos (6U)
16003 #define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
16004 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
16005 #define USART_ISR_TXE_Pos (7U)
16006 #define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */
16007 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
16008 #define USART_ISR_TXE_TXFNF_Pos USART_ISR_TXE_Pos
16009 #define USART_ISR_TXE_TXFNF_Msk USART_ISR_TXE_Msk /*!< 0x00000080 */
16010 #define USART_ISR_TXE_TXFNF USART_ISR_TXE_Msk /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
16011 #define USART_ISR_LBDF_Pos (8U)
16012 #define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
16013 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
16014 #define USART_ISR_CTSIF_Pos (9U)
16015 #define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
16016 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
16017 #define USART_ISR_CTS_Pos (10U)
16018 #define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
16019 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
16020 #define USART_ISR_RTOF_Pos (11U)
16021 #define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
16022 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
16023 #define USART_ISR_EOBF_Pos (12U)
16024 #define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
16025 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
16026 #define USART_ISR_UDR_Pos (13U)
16027 #define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) /*!< 0x00002000 */
16028 #define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI slave underrun error flag */
16029 #define USART_ISR_ABRE_Pos (14U)
16030 #define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
16031 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
16032 #define USART_ISR_ABRF_Pos (15U)
16033 #define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
16034 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
16035 #define USART_ISR_BUSY_Pos (16U)
16036 #define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
16037 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
16038 #define USART_ISR_CMF_Pos (17U)
16039 #define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
16040 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
16041 #define USART_ISR_SBKF_Pos (18U)
16042 #define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
16043 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
16044 #define USART_ISR_RWU_Pos (19U)
16045 #define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
16046 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
16047 #define USART_ISR_WUF_Pos (20U)
16048 #define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
16049 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
16050 #define USART_ISR_TEACK_Pos (21U)
16051 #define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
16052 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
16053 #define USART_ISR_REACK_Pos (22U)
16054 #define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
16055 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
16056 #define USART_ISR_TXFE_Pos (23U)
16057 #define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) /*!< 0x00800000 */
16058 #define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty */
16059 #define USART_ISR_RXFF_Pos (24U)
16060 #define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) /*!< 0x01000000 */
16061 #define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full */
16062 #define USART_ISR_TCBGT_Pos (25U)
16063 #define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
16064 #define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time completion */
16065 #define USART_ISR_RXFT_Pos (26U)
16066 #define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) /*!< 0x04000000 */
16067 #define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO threshold flag */
16068 #define USART_ISR_TXFT_Pos (27U)
16069 #define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) /*!< 0x08000000 */
16070 #define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO threshold flag */
16071
16072 /******************* Bit definition for USART_ICR register ******************/
16073 #define USART_ICR_PECF_Pos (0U)
16074 #define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
16075 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
16076 #define USART_ICR_FECF_Pos (1U)
16077 #define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
16078 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
16079 #define USART_ICR_NECF_Pos (2U)
16080 #define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */
16081 #define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise detected Clear Flag */
16082 #define USART_ICR_ORECF_Pos (3U)
16083 #define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
16084 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
16085 #define USART_ICR_IDLECF_Pos (4U)
16086 #define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
16087 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
16088 #define USART_ICR_TXFECF_Pos (5U)
16089 #define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */
16090 #define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO empty Clear flag */
16091 #define USART_ICR_TCCF_Pos (6U)
16092 #define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
16093 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
16094 #define USART_ICR_TCBGTCF_Pos (7U)
16095 #define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
16096 #define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */
16097 #define USART_ICR_LBDCF_Pos (8U)
16098 #define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
16099 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
16100 #define USART_ICR_CTSCF_Pos (9U)
16101 #define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
16102 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
16103 #define USART_ICR_RTOCF_Pos (11U)
16104 #define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
16105 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
16106 #define USART_ICR_EOBCF_Pos (12U)
16107 #define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
16108 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
16109 #define USART_ICR_UDRCF_Pos (13U)
16110 #define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */
16111 #define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI Slave Underrun Clear Flag */
16112 #define USART_ICR_CMCF_Pos (17U)
16113 #define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
16114 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
16115 #define USART_ICR_WUCF_Pos (20U)
16116 #define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
16117 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
16118
16119 /******************* Bit definition for USART_RDR register ******************/
16120 #define USART_RDR_RDR_Pos (0U)
16121 #define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
16122 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
16123
16124 /******************* Bit definition for USART_TDR register ******************/
16125 #define USART_TDR_TDR_Pos (0U)
16126 #define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
16127 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
16128
16129 /******************* Bit definition for USART_PRESC register ****************/
16130 #define USART_PRESC_PRESCALER_Pos (0U)
16131 #define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */
16132 #define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */
16133 #define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */
16134 #define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */
16135 #define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
16136 #define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
16137
16138 /******************************************************************************/
16139 /* */
16140 /* VREFBUF */
16141 /* */
16142 /******************************************************************************/
16143 /******************* Bit definition for VREFBUF_CSR register ****************/
16144 #define VREFBUF_CSR_ENVR_Pos (0U)
16145 #define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
16146 #define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
16147 #define VREFBUF_CSR_HIZ_Pos (1U)
16148 #define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
16149 #define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
16150 #define VREFBUF_CSR_VRR_Pos (3U)
16151 #define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
16152 #define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
16153 #define VREFBUF_CSR_VRS_Pos (4U)
16154 #define VREFBUF_CSR_VRS_Msk (0x3UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000030 */
16155 #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<VRS[5:0] bits (Voltage reference scale) */
16156 #define VREFBUF_CSR_VRS_0 (0x1UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000010 */
16157 #define VREFBUF_CSR_VRS_1 (0x2UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000020 */
16158
16159 /******************* Bit definition for VREFBUF_CCR register ******************/
16160 #define VREFBUF_CCR_TRIM_Pos (0U)
16161 #define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
16162 #define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
16163
16164 /******************************************************************************/
16165 /* */
16166 /* USB Device FS Endpoint registers */
16167 /* */
16168 /******************************************************************************/
16169 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
16170 #define USB_EP1R (USB_BASE + 0x0x00000004) /*!< endpoint 1 register address */
16171 #define USB_EP2R (USB_BASE + 0x0x00000008) /*!< endpoint 2 register address */
16172 #define USB_EP3R (USB_BASE + 0x0x0000000C) /*!< endpoint 3 register address */
16173 #define USB_EP4R (USB_BASE + 0x0x00000010) /*!< endpoint 4 register address */
16174 #define USB_EP5R (USB_BASE + 0x0x00000014) /*!< endpoint 5 register address */
16175 #define USB_EP6R (USB_BASE + 0x0x00000018) /*!< endpoint 6 register address */
16176 #define USB_EP7R (USB_BASE + 0x0x0000001C) /*!< endpoint 7 register address */
16177
16178 /* bit positions */
16179 #define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
16180 #define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
16181 #define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
16182 #define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
16183 #define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
16184 #define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
16185 #define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
16186 #define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
16187 #define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
16188 #define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
16189
16190 /* EndPoint REGister MASK (no toggle fields) */
16191 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
16192 /*!< EP_TYPE[1:0] EndPoint TYPE */
16193 #define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
16194 #define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
16195 #define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
16196 #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
16197 #define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
16198 #define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
16199
16200 #define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
16201 /*!< STAT_TX[1:0] STATus for TX transfer */
16202 #define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
16203 #define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
16204 #define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
16205 #define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
16206 #define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
16207 #define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
16208 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
16209 /*!< STAT_RX[1:0] STATus for RX transfer */
16210 #define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
16211 #define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
16212 #define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
16213 #define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
16214 #define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
16215 #define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
16216 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
16217
16218 /******************************************************************************/
16219 /* */
16220 /* USB Device FS General registers */
16221 /* */
16222 /******************************************************************************/
16223 #define USB_CNTR (USB_BASE + 0x00000040U) /*!< Control register */
16224 #define USB_ISTR (USB_BASE + 0x00000044U) /*!< Interrupt status register */
16225 #define USB_FNR (USB_BASE + 0x00000048U) /*!< Frame number register */
16226 #define USB_DADDR (USB_BASE + 0x0000004CU) /*!< Device address register */
16227 #define USB_BTABLE (USB_BASE + 0x00000050U) /*!< Buffer Table address register */
16228 #define USB_LPMCSR (USB_BASE + 0x00000054U) /*!< LPM Control and Status register */
16229 #define USB_BCDR (USB_BASE + 0x00000058U) /*!< Battery Charging detector register*/
16230
16231 /****************** Bits definition for USB_CNTR register *******************/
16232 #define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
16233 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
16234 #define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
16235 #define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
16236 #define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
16237 #define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
16238 #define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
16239 #define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
16240 #define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */
16241 #define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */
16242 #define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
16243 #define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
16244 #define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
16245 #define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
16246 #define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
16247
16248 /****************** Bits definition for USB_ISTR register *******************/
16249 #define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
16250 #define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
16251 #define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */
16252 #define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
16253 #define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
16254 #define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
16255 #define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
16256 #define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
16257 #define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
16258 #define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
16259 #define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
16260
16261 #define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
16262 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
16263 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
16264 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
16265 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
16266 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
16267 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
16268 #define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
16269 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
16270
16271 /****************** Bits definition for USB_FNR register ********************/
16272 #define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
16273 #define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
16274 #define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
16275 #define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
16276 #define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
16277
16278 /****************** Bits definition for USB_DADDR register ****************/
16279 #define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< ADD[6:0] bits (Device Address) */
16280 #define USB_DADDR_ADD0 ((uint8_t)0x01U) /*!< Bit 0 */
16281 #define USB_DADDR_ADD1 ((uint8_t)0x02U) /*!< Bit 1 */
16282 #define USB_DADDR_ADD2 ((uint8_t)0x04U) /*!< Bit 2 */
16283 #define USB_DADDR_ADD3 ((uint8_t)0x08U) /*!< Bit 3 */
16284 #define USB_DADDR_ADD4 ((uint8_t)0x10U) /*!< Bit 4 */
16285 #define USB_DADDR_ADD5 ((uint8_t)0x20U) /*!< Bit 5 */
16286 #define USB_DADDR_ADD6 ((uint8_t)0x40U) /*!< Bit 6 */
16287
16288 #define USB_DADDR_EF ((uint8_t)0x80U) /*!< Enable Function */
16289
16290 /****************** Bit definition for USB_BTABLE register ******************/
16291 #define USB_BTABLE_BTABLE ((uint16_t)0xFFF8U) /*!< Buffer Table */
16292
16293 /****************** Bits definition for USB_BCDR register *******************/
16294 #define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */
16295 #define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */
16296 #define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */
16297 #define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */
16298 #define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */
16299 #define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */
16300 #define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */
16301 #define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */
16302 #define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */
16303
16304 /******************* Bit definition for LPMCSR register *********************/
16305 #define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */
16306 #define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/
16307 #define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */
16308 #define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */
16309
16310 /*!< Buffer descriptor table */
16311 /***************** Bit definition for USB_ADDR0_TX register *****************/
16312 #define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
16313 #define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos)/*!< 0x0000FFFE */
16314 #define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */
16315
16316 /***************** Bit definition for USB_ADDR1_TX register *****************/
16317 #define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
16318 #define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos)/*!< 0x0000FFFE */
16319 #define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */
16320
16321 /***************** Bit definition for USB_ADDR2_TX register *****************/
16322 #define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
16323 #define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos)/*!< 0x0000FFFE */
16324 #define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */
16325
16326 /***************** Bit definition for USB_ADDR3_TX register *****************/
16327 #define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
16328 #define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos)/*!< 0x0000FFFE */
16329 #define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */
16330
16331 /***************** Bit definition for USB_ADDR4_TX register *****************/
16332 #define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
16333 #define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos)/*!< 0x0000FFFE */
16334 #define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */
16335
16336 /***************** Bit definition for USB_ADDR5_TX register *****************/
16337 #define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
16338 #define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos)/*!< 0x0000FFFE */
16339 #define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */
16340
16341 /***************** Bit definition for USB_ADDR6_TX register *****************/
16342 #define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
16343 #define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos)/*!< 0x0000FFFE */
16344 #define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */
16345
16346 /***************** Bit definition for USB_ADDR7_TX register *****************/
16347 #define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
16348 #define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos)/*!< 0x0000FFFE */
16349 #define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */
16350
16351 /*----------------------------------------------------------------------------*/
16352
16353 /***************** Bit definition for USB_COUNT0_TX register ****************/
16354 #define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
16355 #define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos)/*!< 0x000003FF */
16356 #define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */
16357
16358 /***************** Bit definition for USB_COUNT1_TX register ****************/
16359 #define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
16360 #define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos)/*!< 0x000003FF */
16361 #define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */
16362
16363 /***************** Bit definition for USB_COUNT2_TX register ****************/
16364 #define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
16365 #define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos)/*!< 0x000003FF */
16366 #define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */
16367
16368 /***************** Bit definition for USB_COUNT3_TX register ****************/
16369 #define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
16370 #define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos)/*!< 0x000003FF */
16371 #define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */
16372
16373 /***************** Bit definition for USB_COUNT4_TX register ****************/
16374 #define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
16375 #define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos)/*!< 0x000003FF */
16376 #define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */
16377
16378 /***************** Bit definition for USB_COUNT5_TX register ****************/
16379 #define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
16380 #define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos)/*!< 0x000003FF */
16381 #define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */
16382
16383 /***************** Bit definition for USB_COUNT6_TX register ****************/
16384 #define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
16385 #define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos)/*!< 0x000003FF */
16386 #define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */
16387
16388 /***************** Bit definition for USB_COUNT7_TX register ****************/
16389 #define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
16390 #define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos)/*!< 0x000003FF */
16391 #define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */
16392
16393 /*----------------------------------------------------------------------------*/
16394
16395 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/
16396 #define USB_COUNT0_TX_0_COUNT0_TX_0 (0x000003FFU) /*!< Transmission Byte Count 0 (low) */
16397
16398 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/
16399 #define USB_COUNT0_TX_1_COUNT0_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 0 (high) */
16400
16401 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/
16402 #define USB_COUNT1_TX_0_COUNT1_TX_0 (0x000003FFU) /*!< Transmission Byte Count 1 (low) */
16403
16404 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/
16405 #define USB_COUNT1_TX_1_COUNT1_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 1 (high) */
16406
16407 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/
16408 #define USB_COUNT2_TX_0_COUNT2_TX_0 (0x000003FFU) /*!< Transmission Byte Count 2 (low) */
16409
16410 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/
16411 #define USB_COUNT2_TX_1_COUNT2_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 2 (high) */
16412
16413 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/
16414 #define USB_COUNT3_TX_0_COUNT3_TX_0 (0x000003FFU) /*!< Transmission Byte Count 3 (low) */
16415
16416 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/
16417 #define USB_COUNT3_TX_1_COUNT3_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 3 (high) */
16418
16419 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/
16420 #define USB_COUNT4_TX_0_COUNT4_TX_0 (0x000003FFU) /*!< Transmission Byte Count 4 (low) */
16421
16422 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/
16423 #define USB_COUNT4_TX_1_COUNT4_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 4 (high) */
16424
16425 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/
16426 #define USB_COUNT5_TX_0_COUNT5_TX_0 (0x000003FFU) /*!< Transmission Byte Count 5 (low) */
16427
16428 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/
16429 #define USB_COUNT5_TX_1_COUNT5_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 5 (high) */
16430
16431 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/
16432 #define USB_COUNT6_TX_0_COUNT6_TX_0 (0x000003FFU) /*!< Transmission Byte Count 6 (low) */
16433
16434 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/
16435 #define USB_COUNT6_TX_1_COUNT6_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 6 (high) */
16436
16437 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/
16438 #define USB_COUNT7_TX_0_COUNT7_TX_0 (0x000003FFU) /*!< Transmission Byte Count 7 (low) */
16439
16440 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/
16441 #define USB_COUNT7_TX_1_COUNT7_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 7 (high) */
16442
16443 /*----------------------------------------------------------------------------*/
16444
16445 /***************** Bit definition for USB_ADDR0_RX register *****************/
16446 #define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
16447 #define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos)/*!< 0x0000FFFE */
16448 #define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */
16449
16450 /***************** Bit definition for USB_ADDR1_RX register *****************/
16451 #define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
16452 #define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos)/*!< 0x0000FFFE */
16453 #define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */
16454
16455 /***************** Bit definition for USB_ADDR2_RX register *****************/
16456 #define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
16457 #define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos)/*!< 0x0000FFFE */
16458 #define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */
16459
16460 /***************** Bit definition for USB_ADDR3_RX register *****************/
16461 #define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
16462 #define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos)/*!< 0x0000FFFE */
16463 #define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */
16464
16465 /***************** Bit definition for USB_ADDR4_RX register *****************/
16466 #define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
16467 #define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos)/*!< 0x0000FFFE */
16468 #define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */
16469
16470 /***************** Bit definition for USB_ADDR5_RX register *****************/
16471 #define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
16472 #define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos)/*!< 0x0000FFFE */
16473 #define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */
16474
16475 /***************** Bit definition for USB_ADDR6_RX register *****************/
16476 #define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
16477 #define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos)/*!< 0x0000FFFE */
16478 #define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */
16479
16480 /***************** Bit definition for USB_ADDR7_RX register *****************/
16481 #define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
16482 #define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos)/*!< 0x0000FFFE */
16483 #define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */
16484
16485 /*----------------------------------------------------------------------------*/
16486
16487 /***************** Bit definition for USB_COUNT0_RX register ****************/
16488 #define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
16489 #define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos)/*!< 0x000003FF */
16490 #define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */
16491
16492 #define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
16493 #define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
16494 #define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
16495 #define USB_COUNT0_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
16496 #define USB_COUNT0_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
16497 #define USB_COUNT0_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
16498 #define USB_COUNT0_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
16499 #define USB_COUNT0_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
16500
16501 #define USB_COUNT0_RX_BLSIZE_Pos (15U)
16502 #define USB_COUNT0_RX_BLSIZE_Msk (0x1UL << USB_COUNT0_RX_BLSIZE_Pos)/*!< 0x00008000 */
16503 #define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */
16504
16505 /***************** Bit definition for USB_COUNT1_RX register ****************/
16506 #define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
16507 #define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos)/*!< 0x000003FF */
16508 #define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */
16509
16510 #define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
16511 #define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
16512 #define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
16513 #define USB_COUNT1_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
16514 #define USB_COUNT1_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
16515 #define USB_COUNT1_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
16516 #define USB_COUNT1_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
16517 #define USB_COUNT1_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
16518
16519 #define USB_COUNT1_RX_BLSIZE_Pos (15U)
16520 #define USB_COUNT1_RX_BLSIZE_Msk (0x1UL << USB_COUNT1_RX_BLSIZE_Pos)/*!< 0x00008000 */
16521 #define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */
16522
16523 /***************** Bit definition for USB_COUNT2_RX register ****************/
16524 #define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
16525 #define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos)/*!< 0x000003FF */
16526 #define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */
16527
16528 #define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
16529 #define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
16530 #define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
16531 #define USB_COUNT2_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
16532 #define USB_COUNT2_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
16533 #define USB_COUNT2_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
16534 #define USB_COUNT2_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
16535 #define USB_COUNT2_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
16536
16537 #define USB_COUNT2_RX_BLSIZE_Pos (15U)
16538 #define USB_COUNT2_RX_BLSIZE_Msk (0x1UL << USB_COUNT2_RX_BLSIZE_Pos)/*!< 0x00008000 */
16539 #define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */
16540
16541 /***************** Bit definition for USB_COUNT3_RX register ****************/
16542 #define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
16543 #define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos)/*!< 0x000003FF */
16544 #define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */
16545
16546 #define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
16547 #define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
16548 #define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
16549 #define USB_COUNT3_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
16550 #define USB_COUNT3_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
16551 #define USB_COUNT3_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
16552 #define USB_COUNT3_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
16553 #define USB_COUNT3_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
16554
16555 #define USB_COUNT3_RX_BLSIZE_Pos (15U)
16556 #define USB_COUNT3_RX_BLSIZE_Msk (0x1UL << USB_COUNT3_RX_BLSIZE_Pos)/*!< 0x00008000 */
16557 #define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */
16558
16559 /***************** Bit definition for USB_COUNT4_RX register ****************/
16560 #define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
16561 #define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos)/*!< 0x000003FF */
16562 #define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */
16563
16564 #define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
16565 #define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
16566 #define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
16567 #define USB_COUNT4_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
16568 #define USB_COUNT4_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
16569 #define USB_COUNT4_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
16570 #define USB_COUNT4_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
16571 #define USB_COUNT4_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
16572
16573 #define USB_COUNT4_RX_BLSIZE_Pos (15U)
16574 #define USB_COUNT4_RX_BLSIZE_Msk (0x1UL << USB_COUNT4_RX_BLSIZE_Pos)/*!< 0x00008000 */
16575 #define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */
16576
16577 /***************** Bit definition for USB_COUNT5_RX register ****************/
16578 #define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
16579 #define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos)/*!< 0x000003FF */
16580 #define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */
16581
16582 #define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
16583 #define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
16584 #define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
16585 #define USB_COUNT5_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
16586 #define USB_COUNT5_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
16587 #define USB_COUNT5_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
16588 #define USB_COUNT5_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
16589 #define USB_COUNT5_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
16590
16591 #define USB_COUNT5_RX_BLSIZE_Pos (15U)
16592 #define USB_COUNT5_RX_BLSIZE_Msk (0x1UL << USB_COUNT5_RX_BLSIZE_Pos)/*!< 0x00008000 */
16593 #define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */
16594
16595 /***************** Bit definition for USB_COUNT6_RX register ****************/
16596 #define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
16597 #define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos)/*!< 0x000003FF */
16598 #define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */
16599
16600 #define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
16601 #define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
16602 #define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
16603 #define USB_COUNT6_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
16604 #define USB_COUNT6_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
16605 #define USB_COUNT6_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
16606 #define USB_COUNT6_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
16607 #define USB_COUNT6_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
16608
16609 #define USB_COUNT6_RX_BLSIZE_Pos (15U)
16610 #define USB_COUNT6_RX_BLSIZE_Msk (0x1UL << USB_COUNT6_RX_BLSIZE_Pos)/*!< 0x00008000 */
16611 #define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */
16612
16613 /***************** Bit definition for USB_COUNT7_RX register ****************/
16614 #define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
16615 #define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos)/*!< 0x000003FF */
16616 #define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */
16617
16618 #define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
16619 #define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
16620 #define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
16621 #define USB_COUNT7_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
16622 #define USB_COUNT7_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
16623 #define USB_COUNT7_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
16624 #define USB_COUNT7_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
16625 #define USB_COUNT7_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
16626
16627 #define USB_COUNT7_RX_BLSIZE_Pos (15U)
16628 #define USB_COUNT7_RX_BLSIZE_Msk (0x1UL << USB_COUNT7_RX_BLSIZE_Pos)/*!< 0x00008000 */
16629 #define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */
16630
16631 /*----------------------------------------------------------------------------*/
16632
16633 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/
16634 #define USB_COUNT0_RX_0_COUNT0_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
16635
16636 #define USB_COUNT0_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
16637 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
16638 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
16639 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
16640 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
16641 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
16642
16643 #define USB_COUNT0_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
16644
16645 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/
16646 #define USB_COUNT0_RX_1_COUNT0_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
16647
16648 #define USB_COUNT0_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
16649 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 1 */
16650 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
16651 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
16652 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
16653 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
16654
16655 #define USB_COUNT0_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
16656
16657 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/
16658 #define USB_COUNT1_RX_0_COUNT1_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
16659
16660 #define USB_COUNT1_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
16661 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
16662 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
16663 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
16664 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
16665 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
16666
16667 #define USB_COUNT1_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
16668
16669 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/
16670 #define USB_COUNT1_RX_1_COUNT1_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
16671
16672 #define USB_COUNT1_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
16673 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
16674 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
16675 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
16676 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
16677 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
16678
16679 #define USB_COUNT1_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
16680
16681 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/
16682 #define USB_COUNT2_RX_0_COUNT2_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
16683
16684 #define USB_COUNT2_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
16685 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
16686 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
16687 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
16688 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
16689 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
16690
16691 #define USB_COUNT2_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
16692
16693 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/
16694 #define USB_COUNT2_RX_1_COUNT2_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
16695
16696 #define USB_COUNT2_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
16697 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
16698 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
16699 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
16700 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
16701 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
16702
16703 #define USB_COUNT2_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
16704
16705 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/
16706 #define USB_COUNT3_RX_0_COUNT3_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
16707
16708 #define USB_COUNT3_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
16709 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
16710 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
16711 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
16712 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
16713 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
16714
16715 #define USB_COUNT3_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
16716
16717 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/
16718 #define USB_COUNT3_RX_1_COUNT3_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
16719
16720 #define USB_COUNT3_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
16721 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
16722 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
16723 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
16724 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
16725 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
16726
16727 #define USB_COUNT3_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
16728
16729 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/
16730 #define USB_COUNT4_RX_0_COUNT4_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
16731
16732 #define USB_COUNT4_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
16733 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
16734 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
16735 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
16736 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
16737 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
16738
16739 #define USB_COUNT4_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
16740
16741 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/
16742 #define USB_COUNT4_RX_1_COUNT4_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
16743
16744 #define USB_COUNT4_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
16745 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
16746 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
16747 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
16748 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
16749 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
16750
16751 #define USB_COUNT4_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
16752
16753 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/
16754 #define USB_COUNT5_RX_0_COUNT5_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
16755
16756 #define USB_COUNT5_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
16757 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
16758 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
16759 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
16760 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
16761 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
16762
16763 #define USB_COUNT5_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
16764
16765 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/
16766 #define USB_COUNT5_RX_1_COUNT5_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
16767
16768 #define USB_COUNT5_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
16769 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
16770 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
16771 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
16772 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
16773 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
16774
16775 #define USB_COUNT5_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
16776
16777 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/
16778 #define USB_COUNT6_RX_0_COUNT6_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
16779
16780 #define USB_COUNT6_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
16781 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
16782 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
16783 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
16784 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
16785 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
16786
16787 #define USB_COUNT6_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
16788
16789 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/
16790 #define USB_COUNT6_RX_1_COUNT6_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
16791
16792 #define USB_COUNT6_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
16793 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
16794 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
16795 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
16796 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
16797 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
16798
16799 #define USB_COUNT6_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
16800
16801 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/
16802 #define USB_COUNT7_RX_0_COUNT7_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
16803
16804 #define USB_COUNT7_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
16805 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
16806 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
16807 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
16808 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
16809 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
16810
16811 #define USB_COUNT7_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
16812
16813 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/
16814 #define USB_COUNT7_RX_1_COUNT7_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
16815
16816 #define USB_COUNT7_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
16817 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
16818 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
16819 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
16820 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
16821 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
16822
16823 #define USB_COUNT7_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
16824
16825 /******************************************************************************/
16826 /* */
16827 /* UCPD */
16828 /* */
16829 /******************************************************************************/
16830 /******************** Bits definition for UCPD_CFG1 register *******************/
16831 #define UCPD_CFG1_HBITCLKDIV_Pos (0U)
16832 #define UCPD_CFG1_HBITCLKDIV_Msk (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x0000003F */
16833 #define UCPD_CFG1_HBITCLKDIV UCPD_CFG1_HBITCLKDIV_Msk /*!< Number of cycles (minus 1) for a half bit clock */
16834 #define UCPD_CFG1_HBITCLKDIV_0 (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000001 */
16835 #define UCPD_CFG1_HBITCLKDIV_1 (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000002 */
16836 #define UCPD_CFG1_HBITCLKDIV_2 (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000004 */
16837 #define UCPD_CFG1_HBITCLKDIV_3 (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000008 */
16838 #define UCPD_CFG1_HBITCLKDIV_4 (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000010 */
16839 #define UCPD_CFG1_HBITCLKDIV_5 (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000020 */
16840 #define UCPD_CFG1_IFRGAP_Pos (6U)
16841 #define UCPD_CFG1_IFRGAP_Msk (0x1FUL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x000007C0 */
16842 #define UCPD_CFG1_IFRGAP UCPD_CFG1_IFRGAP_Msk /*!< Clock divider value to generates Interframe gap */
16843 #define UCPD_CFG1_IFRGAP_0 (0x01UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000040 */
16844 #define UCPD_CFG1_IFRGAP_1 (0x02UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000080 */
16845 #define UCPD_CFG1_IFRGAP_2 (0x04UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000100 */
16846 #define UCPD_CFG1_IFRGAP_3 (0x08UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000200 */
16847 #define UCPD_CFG1_IFRGAP_4 (0x10UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000400 */
16848 #define UCPD_CFG1_TRANSWIN_Pos (11U)
16849 #define UCPD_CFG1_TRANSWIN_Msk (0x1FUL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x0000F800 */
16850 #define UCPD_CFG1_TRANSWIN UCPD_CFG1_TRANSWIN_Msk /*!< Number of cycles (minus 1) of the half bit clock */
16851 #define UCPD_CFG1_TRANSWIN_0 (0x01UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00000800 */
16852 #define UCPD_CFG1_TRANSWIN_1 (0x02UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00001000 */
16853 #define UCPD_CFG1_TRANSWIN_2 (0x04UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00002000 */
16854 #define UCPD_CFG1_TRANSWIN_3 (0x08UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00004000 */
16855 #define UCPD_CFG1_TRANSWIN_4 (0x10UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00008000 */
16856 #define UCPD_CFG1_PSC_UCPDCLK_Pos (17U)
16857 #define UCPD_CFG1_PSC_UCPDCLK_Msk (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x000E0000 */
16858 #define UCPD_CFG1_PSC_UCPDCLK UCPD_CFG1_PSC_UCPDCLK_Msk /*!< Prescaler for UCPDCLK */
16859 #define UCPD_CFG1_PSC_UCPDCLK_0 (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00020000 */
16860 #define UCPD_CFG1_PSC_UCPDCLK_1 (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00040000 */
16861 #define UCPD_CFG1_PSC_UCPDCLK_2 (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00080000 */
16862 #define UCPD_CFG1_RXORDSETEN_Pos (20U)
16863 #define UCPD_CFG1_RXORDSETEN_Msk (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x1FF00000 */
16864 #define UCPD_CFG1_RXORDSETEN UCPD_CFG1_RXORDSETEN_Msk /*!< Receiver ordered set detection enable */
16865 #define UCPD_CFG1_RXORDSETEN_0 (0x001UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00100000 */
16866 #define UCPD_CFG1_RXORDSETEN_1 (0x002UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00200000 */
16867 #define UCPD_CFG1_RXORDSETEN_2 (0x004UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00400000 */
16868 #define UCPD_CFG1_RXORDSETEN_3 (0x008UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00800000 */
16869 #define UCPD_CFG1_RXORDSETEN_4 (0x010UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x01000000 */
16870 #define UCPD_CFG1_RXORDSETEN_5 (0x020UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x02000000 */
16871 #define UCPD_CFG1_RXORDSETEN_6 (0x040UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x04000000 */
16872 #define UCPD_CFG1_RXORDSETEN_7 (0x080UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x08000000 */
16873 #define UCPD_CFG1_RXORDSETEN_8 (0x100UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x10000000 */
16874 #define UCPD_CFG1_TXDMAEN_Pos (29U)
16875 #define UCPD_CFG1_TXDMAEN_Msk (0x1UL << UCPD_CFG1_TXDMAEN_Pos) /*!< 0x20000000 */
16876 #define UCPD_CFG1_TXDMAEN UCPD_CFG1_TXDMAEN_Msk /*!< DMA transmission requests enable */
16877 #define UCPD_CFG1_RXDMAEN_Pos (30U)
16878 #define UCPD_CFG1_RXDMAEN_Msk (0x1UL << UCPD_CFG1_RXDMAEN_Pos) /*!< 0x40000000 */
16879 #define UCPD_CFG1_RXDMAEN UCPD_CFG1_RXDMAEN_Msk /*!< DMA reception requests enable */
16880 #define UCPD_CFG1_UCPDEN_Pos (31U)
16881 #define UCPD_CFG1_UCPDEN_Msk (0x1UL << UCPD_CFG1_UCPDEN_Pos) /*!< 0x80000000 */
16882 #define UCPD_CFG1_UCPDEN UCPD_CFG1_UCPDEN_Msk /*!< USB Power Delivery Block Enable */
16883
16884 /******************** Bits definition for UCPD_CFG2 register *******************/
16885 #define UCPD_CFG2_RXFILTDIS_Pos (0U)
16886 #define UCPD_CFG2_RXFILTDIS_Msk (0x1UL << UCPD_CFG2_RXFILTDIS_Pos) /*!< 0x00000001 */
16887 #define UCPD_CFG2_RXFILTDIS UCPD_CFG2_RXFILTDIS_Msk /*!< Enables an Rx pre-filter for the BMC decoder */
16888 #define UCPD_CFG2_RXFILT2N3_Pos (1U)
16889 #define UCPD_CFG2_RXFILT2N3_Msk (0x1UL << UCPD_CFG2_RXFILT2N3_Pos) /*!< 0x00000002 */
16890 #define UCPD_CFG2_RXFILT2N3 UCPD_CFG2_RXFILT2N3_Msk /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */
16891 #define UCPD_CFG2_FORCECLK_Pos (2U)
16892 #define UCPD_CFG2_FORCECLK_Msk (0x1UL << UCPD_CFG2_FORCECLK_Pos) /*!< 0x00000004 */
16893 #define UCPD_CFG2_FORCECLK UCPD_CFG2_FORCECLK_Msk /*!< Controls forcing of the clock request UCPDCLK_REQ */
16894 #define UCPD_CFG2_WUPEN_Pos (3U)
16895 #define UCPD_CFG2_WUPEN_Msk (0x1UL << UCPD_CFG2_WUPEN_Pos) /*!< 0x00000008 */
16896 #define UCPD_CFG2_WUPEN UCPD_CFG2_WUPEN_Msk /*!< Wakeup from STOP enable */
16897
16898 /******************** Bits definition for UCPD_CR register ********************/
16899 #define UCPD_CR_TXMODE_Pos (0U)
16900 #define UCPD_CR_TXMODE_Msk (0x3UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000003 */
16901 #define UCPD_CR_TXMODE UCPD_CR_TXMODE_Msk /*!< Type of Tx packet */
16902 #define UCPD_CR_TXMODE_0 (0x1UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000001 */
16903 #define UCPD_CR_TXMODE_1 (0x2UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000002 */
16904 #define UCPD_CR_TXSEND_Pos (2U)
16905 #define UCPD_CR_TXSEND_Msk (0x1UL << UCPD_CR_TXSEND_Pos) /*!< 0x00000004 */
16906 #define UCPD_CR_TXSEND UCPD_CR_TXSEND_Msk /*!< Type of Tx packet */
16907 #define UCPD_CR_TXHRST_Pos (3U)
16908 #define UCPD_CR_TXHRST_Msk (0x1UL << UCPD_CR_TXHRST_Pos) /*!< 0x00000008 */
16909 #define UCPD_CR_TXHRST UCPD_CR_TXHRST_Msk /*!< Command to send a Tx Hard Reset */
16910 #define UCPD_CR_RXMODE_Pos (4U)
16911 #define UCPD_CR_RXMODE_Msk (0x1UL << UCPD_CR_RXMODE_Pos) /*!< 0x00000010 */
16912 #define UCPD_CR_RXMODE UCPD_CR_RXMODE_Msk /*!< Receiver mode */
16913 #define UCPD_CR_PHYRXEN_Pos (5U)
16914 #define UCPD_CR_PHYRXEN_Msk (0x1UL << UCPD_CR_PHYRXEN_Pos) /*!< 0x00000020 */
16915 #define UCPD_CR_PHYRXEN UCPD_CR_PHYRXEN_Msk /*!< Controls enable of USB Power Delivery receiver */
16916 #define UCPD_CR_PHYCCSEL_Pos (6U)
16917 #define UCPD_CR_PHYCCSEL_Msk (0x1UL << UCPD_CR_PHYCCSEL_Pos) /*!< 0x00000040 */
16918 #define UCPD_CR_PHYCCSEL UCPD_CR_PHYCCSEL_Msk /*!< */
16919 #define UCPD_CR_ANASUBMODE_Pos (7U)
16920 #define UCPD_CR_ANASUBMODE_Msk (0x3UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000180 */
16921 #define UCPD_CR_ANASUBMODE UCPD_CR_ANASUBMODE_Msk /*!< Analog PHY sub-mode */
16922 #define UCPD_CR_ANASUBMODE_0 (0x1UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000080 */
16923 #define UCPD_CR_ANASUBMODE_1 (0x2UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000100 */
16924 #define UCPD_CR_ANAMODE_Pos (9U)
16925 #define UCPD_CR_ANAMODE_Msk (0x1UL << UCPD_CR_ANAMODE_Pos) /*!< 0x00000200 */
16926 #define UCPD_CR_ANAMODE UCPD_CR_ANAMODE_Msk /*!< Analog PHY working mode */
16927 #define UCPD_CR_CCENABLE_Pos (10U)
16928 #define UCPD_CR_CCENABLE_Msk (0x3UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000C00 */
16929 #define UCPD_CR_CCENABLE UCPD_CR_CCENABLE_Msk /*!< */
16930 #define UCPD_CR_CCENABLE_0 (0x1UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000400 */
16931 #define UCPD_CR_CCENABLE_1 (0x2UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000800 */
16932 #define UCPD_CR_FRSRXEN_Pos (16U)
16933 #define UCPD_CR_FRSRXEN_Msk (0x1UL << UCPD_CR_FRSRXEN_Pos) /*!< 0x00010000 */
16934 #define UCPD_CR_FRSRXEN UCPD_CR_FRSRXEN_Msk /*!< Enable FRS request detection function */
16935 #define UCPD_CR_FRSTX_Pos (17U)
16936 #define UCPD_CR_FRSTX_Msk (0x1UL << UCPD_CR_FRSTX_Pos) /*!< 0x00020000 */
16937 #define UCPD_CR_FRSTX UCPD_CR_FRSTX_Msk /*!< Signal Fast Role Swap request */
16938 #define UCPD_CR_RDCH_Pos (18U)
16939 #define UCPD_CR_RDCH_Msk (0x1UL << UCPD_CR_RDCH_Pos) /*!< 0x00040000 */
16940 #define UCPD_CR_RDCH UCPD_CR_RDCH_Msk /*!< */
16941 #define UCPD_CR_CC1TCDIS_Pos (20U)
16942 #define UCPD_CR_CC1TCDIS_Msk (0x1UL << UCPD_CR_CC1TCDIS_Pos) /*!< 0x00100000 */
16943 #define UCPD_CR_CC1TCDIS UCPD_CR_CC1TCDIS_Msk /*!< The bit allows the Type-C detector for CC0 to be disabled. */
16944 #define UCPD_CR_CC2TCDIS_Pos (21U)
16945 #define UCPD_CR_CC2TCDIS_Msk (0x1UL << UCPD_CR_CC2TCDIS_Pos) /*!< 0x00200000 */
16946 #define UCPD_CR_CC2TCDIS UCPD_CR_CC2TCDIS_Msk /*!< The bit allows the Type-C detector for CC2 to be disabled. */
16947
16948 /******************** Bits definition for UCPD_IMR register *******************/
16949 #define UCPD_IMR_TXISIE_Pos (0U)
16950 #define UCPD_IMR_TXISIE_Msk (0x1UL << UCPD_IMR_TXISIE_Pos) /*!< 0x00000001 */
16951 #define UCPD_IMR_TXISIE UCPD_IMR_TXISIE_Msk /*!< Enable TXIS interrupt */
16952 #define UCPD_IMR_TXMSGDISCIE_Pos (1U)
16953 #define UCPD_IMR_TXMSGDISCIE_Msk (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos) /*!< 0x00000002 */
16954 #define UCPD_IMR_TXMSGDISCIE UCPD_IMR_TXMSGDISCIE_Msk /*!< Enable TXMSGDISC interrupt */
16955 #define UCPD_IMR_TXMSGSENTIE_Pos (2U)
16956 #define UCPD_IMR_TXMSGSENTIE_Msk (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos) /*!< 0x00000004 */
16957 #define UCPD_IMR_TXMSGSENTIE UCPD_IMR_TXMSGSENTIE_Msk /*!< Enable TXMSGSENT interrupt */
16958 #define UCPD_IMR_TXMSGABTIE_Pos (3U)
16959 #define UCPD_IMR_TXMSGABTIE_Msk (0x1UL << UCPD_IMR_TXMSGABTIE_Pos) /*!< 0x00000008 */
16960 #define UCPD_IMR_TXMSGABTIE UCPD_IMR_TXMSGABTIE_Msk /*!< Enable TXMSGABT interrupt */
16961 #define UCPD_IMR_HRSTDISCIE_Pos (4U)
16962 #define UCPD_IMR_HRSTDISCIE_Msk (0x1UL << UCPD_IMR_HRSTDISCIE_Pos) /*!< 0x00000010 */
16963 #define UCPD_IMR_HRSTDISCIE UCPD_IMR_HRSTDISCIE_Msk /*!< Enable HRSTDISC interrupt */
16964 #define UCPD_IMR_HRSTSENTIE_Pos (5U)
16965 #define UCPD_IMR_HRSTSENTIE_Msk (0x1UL << UCPD_IMR_HRSTSENTIE_Pos) /*!< 0x00000020 */
16966 #define UCPD_IMR_HRSTSENTIE UCPD_IMR_HRSTSENTIE_Msk /*!< Enable HRSTSENT interrupt */
16967 #define UCPD_IMR_TXUNDIE_Pos (6U)
16968 #define UCPD_IMR_TXUNDIE_Msk (0x1UL << UCPD_IMR_TXUNDIE_Pos) /*!< 0x00000040 */
16969 #define UCPD_IMR_TXUNDIE UCPD_IMR_TXUNDIE_Msk /*!< Enable TXUND interrupt */
16970 #define UCPD_IMR_RXNEIE_Pos (8U)
16971 #define UCPD_IMR_RXNEIE_Msk (0x1UL << UCPD_IMR_RXNEIE_Pos) /*!< 0x00000100 */
16972 #define UCPD_IMR_RXNEIE UCPD_IMR_RXNEIE_Msk /*!< Enable RXNE interrupt */
16973 #define UCPD_IMR_RXORDDETIE_Pos (9U)
16974 #define UCPD_IMR_RXORDDETIE_Msk (0x1UL << UCPD_IMR_RXORDDETIE_Pos) /*!< 0x00000200 */
16975 #define UCPD_IMR_RXORDDETIE UCPD_IMR_RXORDDETIE_Msk /*!< Enable RXORDDET interrupt */
16976 #define UCPD_IMR_RXHRSTDETIE_Pos (10U)
16977 #define UCPD_IMR_RXHRSTDETIE_Msk (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos) /*!< 0x00000400 */
16978 #define UCPD_IMR_RXHRSTDETIE UCPD_IMR_RXHRSTDETIE_Msk /*!< Enable RXHRSTDET interrupt */
16979 #define UCPD_IMR_RXOVRIE_Pos (11U)
16980 #define UCPD_IMR_RXOVRIE_Msk (0x1UL << UCPD_IMR_RXOVRIE_Pos) /*!< 0x00000800 */
16981 #define UCPD_IMR_RXOVRIE UCPD_IMR_RXOVRIE_Msk /*!< Enable RXOVR interrupt */
16982 #define UCPD_IMR_RXMSGENDIE_Pos (12U)
16983 #define UCPD_IMR_RXMSGENDIE_Msk (0x1UL << UCPD_IMR_RXMSGENDIE_Pos) /*!< 0x00001000 */
16984 #define UCPD_IMR_RXMSGENDIE UCPD_IMR_RXMSGENDIE_Msk /*!< Enable RXMSGEND interrupt */
16985 #define UCPD_IMR_TYPECEVT1IE_Pos (14U)
16986 #define UCPD_IMR_TYPECEVT1IE_Msk (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos) /*!< 0x00004000 */
16987 #define UCPD_IMR_TYPECEVT1IE UCPD_IMR_TYPECEVT1IE_Msk /*!< Enable TYPECEVT1IE interrupt */
16988 #define UCPD_IMR_TYPECEVT2IE_Pos (15U)
16989 #define UCPD_IMR_TYPECEVT2IE_Msk (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos) /*!< 0x00008000 */
16990 #define UCPD_IMR_TYPECEVT2IE UCPD_IMR_TYPECEVT2IE_Msk /*!< Enable TYPECEVT2IE interrupt */
16991 #define UCPD_IMR_FRSEVTIE_Pos (20U)
16992 #define UCPD_IMR_FRSEVTIE_Msk (0x1UL << UCPD_IMR_FRSEVTIE_Pos) /*!< 0x00100000 */
16993 #define UCPD_IMR_FRSEVTIE UCPD_IMR_FRSEVTIE_Msk /*!< Fast Role Swap interrupt */
16994
16995 /******************** Bits definition for UCPD_SR register ********************/
16996 #define UCPD_SR_TXIS_Pos (0U)
16997 #define UCPD_SR_TXIS_Msk (0x1UL << UCPD_SR_TXIS_Pos) /*!< 0x00000001 */
16998 #define UCPD_SR_TXIS UCPD_SR_TXIS_Msk /*!< Transmit interrupt status */
16999 #define UCPD_SR_TXMSGDISC_Pos (1U)
17000 #define UCPD_SR_TXMSGDISC_Msk (0x1UL << UCPD_SR_TXMSGDISC_Pos) /*!< 0x00000002 */
17001 #define UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC_Msk /*!< Transmit message discarded interrupt */
17002 #define UCPD_SR_TXMSGSENT_Pos (2U)
17003 #define UCPD_SR_TXMSGSENT_Msk (0x1UL << UCPD_SR_TXMSGSENT_Pos) /*!< 0x00000004 */
17004 #define UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT_Msk /*!< Transmit message sent interrupt */
17005 #define UCPD_SR_TXMSGABT_Pos (3U)
17006 #define UCPD_SR_TXMSGABT_Msk (0x1UL << UCPD_SR_TXMSGABT_Pos) /*!< 0x00000008 */
17007 #define UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT_Msk /*!< Transmit message abort interrupt */
17008 #define UCPD_SR_HRSTDISC_Pos (4U)
17009 #define UCPD_SR_HRSTDISC_Msk (0x1UL << UCPD_SR_HRSTDISC_Pos) /*!< 0x00000010 */
17010 #define UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC_Msk /*!< HRST discarded interrupt */
17011 #define UCPD_SR_HRSTSENT_Pos (5U)
17012 #define UCPD_SR_HRSTSENT_Msk (0x1UL << UCPD_SR_HRSTSENT_Pos) /*!< 0x00000020 */
17013 #define UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT_Msk /*!< HRST sent interrupt */
17014 #define UCPD_SR_TXUND_Pos (6U)
17015 #define UCPD_SR_TXUND_Msk (0x1UL << UCPD_SR_TXUND_Pos) /*!< 0x00000040 */
17016 #define UCPD_SR_TXUND UCPD_SR_TXUND_Msk /*!< Tx data underrun condition interrupt */
17017 #define UCPD_SR_RXNE_Pos (8U)
17018 #define UCPD_SR_RXNE_Msk (0x1UL << UCPD_SR_RXNE_Pos) /*!< 0x00000100 */
17019 #define UCPD_SR_RXNE UCPD_SR_RXNE_Msk /*!< Receive data register not empty interrupt */
17020 #define UCPD_SR_RXORDDET_Pos (9U)
17021 #define UCPD_SR_RXORDDET_Msk (0x1UL << UCPD_SR_RXORDDET_Pos) /*!< 0x00000200 */
17022 #define UCPD_SR_RXORDDET UCPD_SR_RXORDDET_Msk /*!< Rx ordered set (4 K-codes) detected interrupt */
17023 #define UCPD_SR_RXHRSTDET_Pos (10U)
17024 #define UCPD_SR_RXHRSTDET_Msk (0x1UL << UCPD_SR_RXHRSTDET_Pos) /*!< 0x00000400 */
17025 #define UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET_Msk /*!< Rx Hard Reset detect interrupt */
17026 #define UCPD_SR_RXOVR_Pos (11U)
17027 #define UCPD_SR_RXOVR_Msk (0x1UL << UCPD_SR_RXOVR_Pos) /*!< 0x00000800 */
17028 #define UCPD_SR_RXOVR UCPD_SR_RXOVR_Msk /*!< Rx data overflow interrupt */
17029 #define UCPD_SR_RXMSGEND_Pos (12U)
17030 #define UCPD_SR_RXMSGEND_Msk (0x1UL << UCPD_SR_RXMSGEND_Pos) /*!< 0x00001000 */
17031 #define UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND_Msk /*!< Rx message received */
17032 #define UCPD_SR_RXERR_Pos (13U)
17033 #define UCPD_SR_RXERR_Msk (0x1UL << UCPD_SR_RXERR_Pos) /*!< 0x00002000 */
17034 #define UCPD_SR_RXERR UCPD_SR_RXERR_Msk /*!< RX Error */
17035 #define UCPD_SR_TYPECEVT1_Pos (14U)
17036 #define UCPD_SR_TYPECEVT1_Msk (0x1UL << UCPD_SR_TYPECEVT1_Pos) /*!< 0x00004000 */
17037 #define UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1_Msk /*!< Type C voltage level event on CC1 */
17038 #define UCPD_SR_TYPECEVT2_Pos (15U)
17039 #define UCPD_SR_TYPECEVT2_Msk (0x1UL << UCPD_SR_TYPECEVT2_Pos) /*!< 0x00008000 */
17040 #define UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2_Msk /*!< Type C voltage level event on CC2 */
17041 #define UCPD_SR_TYPEC_VSTATE_CC1_Pos (16U)
17042 #define UCPD_SR_TYPEC_VSTATE_CC1_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00030000 */
17043 #define UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1_Msk /*!< Status of DC level on CC1 pin */
17044 #define UCPD_SR_TYPEC_VSTATE_CC1_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00010000 */
17045 #define UCPD_SR_TYPEC_VSTATE_CC1_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00020000 */
17046 #define UCPD_SR_TYPEC_VSTATE_CC2_Pos (18U)
17047 #define UCPD_SR_TYPEC_VSTATE_CC2_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x000C0000 */
17048 #define UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2_Msk /*!<Status of DC level on CC2 pin */
17049 #define UCPD_SR_TYPEC_VSTATE_CC2_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00040000 */
17050 #define UCPD_SR_TYPEC_VSTATE_CC2_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00080000 */
17051 #define UCPD_SR_FRSEVT_Pos (20U)
17052 #define UCPD_SR_FRSEVT_Msk (0x1UL << UCPD_SR_FRSEVT_Pos) /*!< 0x00100000 */
17053 #define UCPD_SR_FRSEVT UCPD_SR_FRSEVT_Msk /*!< Fast Role Swap detection event */
17054
17055 /******************** Bits definition for UCPD_ICR register *******************/
17056 #define UCPD_ICR_TXMSGDISCCF_Pos (1U)
17057 #define UCPD_ICR_TXMSGDISCCF_Msk (0x1UL << UCPD_ICR_TXMSGDISCCF_Pos) /*!< 0x00000002 */
17058 #define UCPD_ICR_TXMSGDISCCF UCPD_ICR_TXMSGDISCCF_Msk /*!< Tx message discarded flag (TXMSGDISC) clear */
17059 #define UCPD_ICR_TXMSGSENTCF_Pos (2U)
17060 #define UCPD_ICR_TXMSGSENTCF_Msk (0x1UL << UCPD_ICR_TXMSGSENTCF_Pos) /*!< 0x00000004 */
17061 #define UCPD_ICR_TXMSGSENTCF UCPD_ICR_TXMSGSENTCF_Msk /*!< Tx message sent flag (TXMSGSENT) clear */
17062 #define UCPD_ICR_TXMSGABTCF_Pos (3U)
17063 #define UCPD_ICR_TXMSGABTCF_Msk (0x1UL << UCPD_ICR_TXMSGABTCF_Pos) /*!< 0x00000008 */
17064 #define UCPD_ICR_TXMSGABTCF UCPD_ICR_TXMSGABTCF_Msk /*!< Tx message abort flag (TXMSGABT) clear */
17065 #define UCPD_ICR_HRSTDISCCF_Pos (4U)
17066 #define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */
17067 #define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset discarded flag (HRSTDISC) clear */
17068 #define UCPD_ICR_HRSTSENTCF_Pos (5U)
17069 #define UCPD_ICR_HRSTSENTCF_Msk (0x1UL << UCPD_ICR_HRSTSENTCF_Pos) /*!< 0x00000020 */
17070 #define UCPD_ICR_HRSTSENTCF UCPD_ICR_HRSTSENTCF_Msk /*!< Hard reset sent flag (HRSTSENT) clear */
17071 #define UCPD_ICR_TXUNDCF_Pos (6U)
17072 #define UCPD_ICR_TXUNDCF_Msk (0x1UL << UCPD_ICR_TXUNDCF_Pos) /*!< 0x00000040 */
17073 #define UCPD_ICR_TXUNDCF UCPD_ICR_TXUNDCF_Msk /*!< Tx underflow flag (TXUND) clear */
17074 #define UCPD_ICR_RXORDDETCF_Pos (9U)
17075 #define UCPD_ICR_RXORDDETCF_Msk (0x1UL << UCPD_ICR_RXORDDETCF_Pos) /*!< 0x00000200 */
17076 #define UCPD_ICR_RXORDDETCF UCPD_ICR_RXORDDETCF_Msk /*!< Rx ordered set detect flag (RXORDDET) clear */
17077 #define UCPD_ICR_RXHRSTDETCF_Pos (10U)
17078 #define UCPD_ICR_RXHRSTDETCF_Msk (0x1UL << UCPD_ICR_RXHRSTDETCF_Pos) /*!< 0x00000400 */
17079 #define UCPD_ICR_RXHRSTDETCF UCPD_ICR_RXHRSTDETCF_Msk /*!< Rx Hard Reset detected flag (RXHRSTDET) clear */
17080 #define UCPD_ICR_RXOVRCF_Pos (11U)
17081 #define UCPD_ICR_RXOVRCF_Msk (0x1UL << UCPD_ICR_RXOVRCF_Pos) /*!< 0x00000800 */
17082 #define UCPD_ICR_RXOVRCF UCPD_ICR_RXOVRCF_Msk /*!< Rx overflow flag (RXOVR) clear */
17083 #define UCPD_ICR_RXMSGENDCF_Pos (12U)
17084 #define UCPD_ICR_RXMSGENDCF_Msk (0x1UL << UCPD_ICR_RXMSGENDCF_Pos) /*!< 0x00001000 */
17085 #define UCPD_ICR_RXMSGENDCF UCPD_ICR_RXMSGENDCF_Msk /*!< Rx message received flag (RXMSGEND) clear */
17086 #define UCPD_ICR_TYPECEVT1CF_Pos (14U)
17087 #define UCPD_ICR_TYPECEVT1CF_Msk (0x1UL << UCPD_ICR_TYPECEVT1CF_Pos) /*!< 0x00004000 */
17088 #define UCPD_ICR_TYPECEVT1CF UCPD_ICR_TYPECEVT1CF_Msk /*!< TypeC event (CC1) flag (TYPECEVT1) clear */
17089 #define UCPD_ICR_TYPECEVT2CF_Pos (15U)
17090 #define UCPD_ICR_TYPECEVT2CF_Msk (0x1UL << UCPD_ICR_TYPECEVT2CF_Pos) /*!< 0x00008000 */
17091 #define UCPD_ICR_TYPECEVT2CF UCPD_ICR_TYPECEVT2CF_Msk /*!< TypeC event (CC2) flag (TYPECEVT2) clear */
17092 #define UCPD_ICR_FRSEVTCF_Pos (20U)
17093 #define UCPD_ICR_FRSEVTCF_Msk (0x1UL << UCPD_ICR_FRSEVTCF_Pos) /*!< 0x00100000 */
17094 #define UCPD_ICR_FRSEVTCF UCPD_ICR_FRSEVTCF_Msk /*!< Fast Role Swap event flag clear */
17095
17096 /******************** Bits definition for UCPD_TXORDSET register **************/
17097 #define UCPD_TX_ORDSET_TXORDSET_Pos (0U)
17098 #define UCPD_TX_ORDSET_TXORDSET_Msk (0xFFFFFUL << UCPD_TX_ORDSET_TXORDSET_Pos)/*!< 0x000FFFFF */
17099 #define UCPD_TX_ORDSET_TXORDSET UCPD_TX_ORDSET_TXORDSET_Msk /*!< Tx Ordered Set */
17100
17101 /******************** Bits definition for UCPD_TXPAYSZ register ****************/
17102 #define UCPD_TX_PAYSZ_TXPAYSZ_Pos (0U)
17103 #define UCPD_TX_PAYSZ_TXPAYSZ_Msk (0x3FFUL << UCPD_TX_PAYSZ_TXPAYSZ_Pos)/*!< 0x000003FF */
17104 #define UCPD_TX_PAYSZ_TXPAYSZ UCPD_TX_PAYSZ_TXPAYSZ_Msk /*!< Tx payload size in bytes */
17105
17106 /******************** Bits definition for UCPD_TXDR register *******************/
17107 #define UCPD_TXDR_TXDATA_Pos (0U)
17108 #define UCPD_TXDR_TXDATA_Msk (0xFFUL << UCPD_TXDR_TXDATA_Pos) /*!< 0x000000FF */
17109 #define UCPD_TXDR_TXDATA UCPD_TXDR_TXDATA_Msk /*!< Tx Data Register */
17110
17111 /******************** Bits definition for UCPD_RXORDSET register **************/
17112 #define UCPD_RX_ORDSET_RXORDSET_Pos (0U)
17113 #define UCPD_RX_ORDSET_RXORDSET_Msk (0x7UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000007 */
17114 #define UCPD_RX_ORDSET_RXORDSET UCPD_RX_ORDSET_RXORDSET_Msk /*!< Rx Ordered Set Code detected */
17115 #define UCPD_RX_ORDSET_RXORDSET_0 (0x1UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000001 */
17116 #define UCPD_RX_ORDSET_RXORDSET_1 (0x2UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000002 */
17117 #define UCPD_RX_ORDSET_RXORDSET_2 (0x4UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000004 */
17118 #define UCPD_RX_ORDSET_RXSOP3OF4_Pos (3U)
17119 #define UCPD_RX_ORDSET_RXSOP3OF4_Msk (0x1UL << UCPD_RX_ORDSET_RXSOP3OF4_Pos)/*!< 0x00000008 */
17120 #define UCPD_RX_ORDSET_RXSOP3OF4 UCPD_RX_ORDSET_RXSOP3OF4_Msk /*!< Rx Ordered Set Debug indication */
17121 #define UCPD_RX_ORDSET_RXSOPKINVALID_Pos (4U)
17122 #define UCPD_RX_ORDSET_RXSOPKINVALID_Msk (0x7UL << UCPD_RX_ORDSET_RXSOPKINVALID_Pos)/*!< 0x00000070 */
17123 #define UCPD_RX_ORDSET_RXSOPKINVALID UCPD_RX_ORDSET_RXSOPKINVALID_Msk /*!< Rx Ordered Set corrupted K-Codes (Debug) */
17124
17125 /******************** Bits definition for UCPD_RXPAYSZ register ****************/
17126 #define UCPD_RX_PAYSZ_RXPAYSZ_Pos (0U)
17127 #define UCPD_RX_PAYSZ_RXPAYSZ_Msk (0x3FFUL << UCPD_RX_PAYSZ_RXPAYSZ_Pos)/*!< 0x000003FF */
17128 #define UCPD_RX_PAYSZ_RXPAYSZ UCPD_RX_PAYSZ_RXPAYSZ_Msk /*!< Rx payload size in bytes */
17129
17130 /******************** Bits definition for UCPD_RXDR register *******************/
17131 #define UCPD_RXDR_RXDATA_Pos (0U)
17132 #define UCPD_RXDR_RXDATA_Msk (0xFFUL << UCPD_RXDR_RXDATA_Pos) /*!< 0x000000FF */
17133 #define UCPD_RXDR_RXDATA UCPD_RXDR_RXDATA_Msk /*!< 8-bit receive data */
17134
17135 /******************** Bits definition for UCPD_RXORDEXT1 register **************/
17136 #define UCPD_RX_ORDEXT1_RXSOPX1_Pos (0U)
17137 #define UCPD_RX_ORDEXT1_RXSOPX1_Msk (0xFFFFFUL << UCPD_RX_ORDEXT1_RXSOPX1_Pos)/*!< 0x000FFFFF */
17138 #define UCPD_RX_ORDEXT1_RXSOPX1 UCPD_RX_ORDEXT1_RXSOPX1_Msk /*!< RX Ordered Set Extension Register 1 */
17139
17140 /******************** Bits definition for UCPD_RXORDEXT2 register **************/
17141 #define UCPD_RX_ORDEXT2_RXSOPX2_Pos (0U)
17142 #define UCPD_RX_ORDEXT2_RXSOPX2_Msk (0xFFFFFUL << UCPD_RX_ORDEXT2_RXSOPX2_Pos)/*!< 0x000FFFFF */
17143 #define UCPD_RX_ORDEXT2_RXSOPX2 UCPD_RX_ORDEXT2_RXSOPX2_Msk /*!< RX Ordered Set Extension Register 1 */
17144
17145 /******************************************************************************/
17146 /* */
17147 /* Window WATCHDOG */
17148 /* */
17149 /******************************************************************************/
17150 /******************* Bit definition for WWDG_CR register ********************/
17151 #define WWDG_CR_T_Pos (0U)
17152 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
17153 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
17154 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
17155 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
17156 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
17157 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
17158 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
17159 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
17160 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
17161
17162 #define WWDG_CR_WDGA_Pos (7U)
17163 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
17164 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
17165
17166 /******************* Bit definition for WWDG_CFR register *******************/
17167 #define WWDG_CFR_W_Pos (0U)
17168 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
17169 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
17170 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
17171 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
17172 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
17173 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
17174 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
17175 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
17176 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
17177
17178 #define WWDG_CFR_WDGTB_Pos (11U)
17179 #define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00003800 */
17180 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[2:0] bits (Timer Base) */
17181 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000800 */
17182 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00001000 */
17183 #define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00002000 */
17184
17185 #define WWDG_CFR_EWI_Pos (9U)
17186 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
17187 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
17188
17189 /******************* Bit definition for WWDG_SR register ********************/
17190 #define WWDG_SR_EWIF_Pos (0U)
17191 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
17192 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
17193
17194 /**
17195 * @}
17196 */
17197
17198 /**
17199 * @}
17200 */
17201
17202 /** @addtogroup Exported_macros
17203 * @{
17204 */
17205
17206 /******************************* ADC Instances ********************************/
17207 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
17208 ((INSTANCE) == ADC2) || \
17209 ((INSTANCE) == ADC3) || \
17210 ((INSTANCE) == ADC4) || \
17211 ((INSTANCE) == ADC5))
17212
17213 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
17214 ((INSTANCE) == ADC3))
17215
17216 #define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) || \
17217 ((INSTANCE) == ADC345_COMMON) )
17218
17219
17220
17221 /******************************** FDCAN Instances ******************************/
17222 #define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1) || \
17223 ((INSTANCE) == FDCAN2) || \
17224 ((INSTANCE) == FDCAN3))
17225
17226 #define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN_CONFIG)
17227 /******************************** COMP Instances ******************************/
17228 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
17229 ((INSTANCE) == COMP2) || \
17230 ((INSTANCE) == COMP3) || \
17231 ((INSTANCE) == COMP4) || \
17232 ((INSTANCE) == COMP5) || \
17233 ((INSTANCE) == COMP6) || \
17234 ((INSTANCE) == COMP7))
17235
17236 /******************************* CORDIC Instances *****************************/
17237 #define IS_CORDIC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CORDIC)
17238
17239 /******************************* CRC Instances ********************************/
17240 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
17241
17242 /******************************* DAC Instances ********************************/
17243 #define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1) || \
17244 ((INSTANCE) == DAC2) || \
17245 ((INSTANCE) == DAC3) || \
17246 ((INSTANCE) == DAC4))
17247
17248
17249 /******************************** DMA Instances *******************************/
17250 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
17251 ((INSTANCE) == DMA1_Channel2) || \
17252 ((INSTANCE) == DMA1_Channel3) || \
17253 ((INSTANCE) == DMA1_Channel4) || \
17254 ((INSTANCE) == DMA1_Channel5) || \
17255 ((INSTANCE) == DMA1_Channel6) || \
17256 ((INSTANCE) == DMA1_Channel7) || \
17257 ((INSTANCE) == DMA1_Channel8) || \
17258 ((INSTANCE) == DMA2_Channel1) || \
17259 ((INSTANCE) == DMA2_Channel2) || \
17260 ((INSTANCE) == DMA2_Channel3) || \
17261 ((INSTANCE) == DMA2_Channel4) || \
17262 ((INSTANCE) == DMA2_Channel5) || \
17263 ((INSTANCE) == DMA2_Channel6) || \
17264 ((INSTANCE) == DMA2_Channel7) || \
17265 ((INSTANCE) == DMA2_Channel8))
17266
17267 #define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
17268 ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
17269 ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
17270 ((INSTANCE) == DMAMUX1_RequestGenerator3))
17271
17272 /******************************* FMAC Instances *******************************/
17273 #define IS_FMAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FMAC)
17274
17275 /******************************* GPIO Instances *******************************/
17276 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
17277 ((INSTANCE) == GPIOB) || \
17278 ((INSTANCE) == GPIOC) || \
17279 ((INSTANCE) == GPIOD) || \
17280 ((INSTANCE) == GPIOE) || \
17281 ((INSTANCE) == GPIOF) || \
17282 ((INSTANCE) == GPIOG))
17283
17284 /******************************* GPIO AF Instances ****************************/
17285 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
17286
17287 /**************************** GPIO Lock Instances *****************************/
17288 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
17289
17290 /******************************** I2C Instances *******************************/
17291 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
17292 ((INSTANCE) == I2C2) || \
17293 ((INSTANCE) == I2C3) || \
17294 ((INSTANCE) == I2C4))
17295
17296 /****************** I2C Instances : wakeup capability from stop modes *********/
17297 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
17298
17299 /****************************** OPAMP Instances *******************************/
17300 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
17301 ((INSTANCE) == OPAMP2) || \
17302 ((INSTANCE) == OPAMP3) || \
17303 ((INSTANCE) == OPAMP4) || \
17304 ((INSTANCE) == OPAMP5) || \
17305 ((INSTANCE) == OPAMP6))
17306
17307 /******************************** PCD Instances *******************************/
17308 #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
17309
17310 /******************************* QSPI Instances *******************************/
17311 #define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI)
17312
17313 /******************************* RNG Instances ********************************/
17314 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
17315
17316 /****************************** RTC Instances *********************************/
17317 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
17318
17319 #define IS_TAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TAMP)
17320
17321 /****************************** SMBUS Instances *******************************/
17322 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
17323 ((INSTANCE) == I2C2) || \
17324 ((INSTANCE) == I2C3) || \
17325 ((INSTANCE) == I2C4))
17326
17327 /******************************** SAI Instances *******************************/
17328 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || ((INSTANCE) == SAI1_Block_B))
17329
17330 /******************************** SPI Instances *******************************/
17331 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
17332 ((INSTANCE) == SPI2) || \
17333 ((INSTANCE) == SPI3) || \
17334 ((INSTANCE) == SPI4))
17335
17336 /******************************** I2S Instances *******************************/
17337 #define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI2) || \
17338 ((__INSTANCE__) == SPI3))
17339
17340 /****************** LPTIM Instances : All supported instances *****************/
17341 #define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
17342
17343 /****************** LPTIM Instances : supporting encoder interface **************/
17344 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
17345
17346 /****************** LPTIM Instances : All supported instances *****************/
17347 #define IS_LPTIM_ENCODER_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
17348
17349 /****************** TIM Instances : All supported instances *******************/
17350 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17351 ((INSTANCE) == TIM2) || \
17352 ((INSTANCE) == TIM3) || \
17353 ((INSTANCE) == TIM4) || \
17354 ((INSTANCE) == TIM5) || \
17355 ((INSTANCE) == TIM6) || \
17356 ((INSTANCE) == TIM7) || \
17357 ((INSTANCE) == TIM8) || \
17358 ((INSTANCE) == TIM15) || \
17359 ((INSTANCE) == TIM16) || \
17360 ((INSTANCE) == TIM17) || \
17361 ((INSTANCE) == TIM20))
17362
17363 /****************** TIM Instances : supporting 32 bits counter ****************/
17364
17365 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
17366 ((INSTANCE) == TIM5))
17367
17368 /****************** TIM Instances : supporting the break function *************/
17369 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17370 ((INSTANCE) == TIM8) || \
17371 ((INSTANCE) == TIM15) || \
17372 ((INSTANCE) == TIM16) || \
17373 ((INSTANCE) == TIM17) || \
17374 ((INSTANCE) == TIM20))
17375
17376 /************** TIM Instances : supporting Break source selection *************/
17377 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17378 ((INSTANCE) == TIM8) || \
17379 ((INSTANCE) == TIM15) || \
17380 ((INSTANCE) == TIM16) || \
17381 ((INSTANCE) == TIM17) || \
17382 ((INSTANCE) == TIM20))
17383
17384 /****************** TIM Instances : supporting 2 break inputs *****************/
17385 #define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17386 ((INSTANCE) == TIM8) || \
17387 ((INSTANCE) == TIM20))
17388
17389 /************* TIM Instances : at least 1 capture/compare channel *************/
17390 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17391 ((INSTANCE) == TIM2) || \
17392 ((INSTANCE) == TIM3) || \
17393 ((INSTANCE) == TIM4) || \
17394 ((INSTANCE) == TIM5) || \
17395 ((INSTANCE) == TIM8) || \
17396 ((INSTANCE) == TIM15) || \
17397 ((INSTANCE) == TIM16) || \
17398 ((INSTANCE) == TIM17) || \
17399 ((INSTANCE) == TIM20))
17400
17401 /************ TIM Instances : at least 2 capture/compare channels *************/
17402 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17403 ((INSTANCE) == TIM2) || \
17404 ((INSTANCE) == TIM3) || \
17405 ((INSTANCE) == TIM4) || \
17406 ((INSTANCE) == TIM5) || \
17407 ((INSTANCE) == TIM8) || \
17408 ((INSTANCE) == TIM15) || \
17409 ((INSTANCE) == TIM20))
17410
17411 /************ TIM Instances : at least 3 capture/compare channels *************/
17412 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17413 ((INSTANCE) == TIM2) || \
17414 ((INSTANCE) == TIM3) || \
17415 ((INSTANCE) == TIM4) || \
17416 ((INSTANCE) == TIM5) || \
17417 ((INSTANCE) == TIM8) || \
17418 ((INSTANCE) == TIM20))
17419
17420 /************ TIM Instances : at least 4 capture/compare channels *************/
17421 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17422 ((INSTANCE) == TIM2) || \
17423 ((INSTANCE) == TIM3) || \
17424 ((INSTANCE) == TIM4) || \
17425 ((INSTANCE) == TIM5) || \
17426 ((INSTANCE) == TIM8) || \
17427 ((INSTANCE) == TIM20))
17428
17429 /****************** TIM Instances : at least 5 capture/compare channels *******/
17430 #define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17431 ((INSTANCE) == TIM8) || \
17432 ((INSTANCE) == TIM20))
17433
17434 /****************** TIM Instances : at least 6 capture/compare channels *******/
17435 #define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17436 ((INSTANCE) == TIM8) || \
17437 ((INSTANCE) == TIM20))
17438
17439 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
17440 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17441 ((INSTANCE) == TIM8) || \
17442 ((INSTANCE) == TIM15) || \
17443 ((INSTANCE) == TIM16) || \
17444 ((INSTANCE) == TIM17) || \
17445 ((INSTANCE) == TIM20))
17446
17447 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
17448 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17449 ((INSTANCE) == TIM2) || \
17450 ((INSTANCE) == TIM3) || \
17451 ((INSTANCE) == TIM4) || \
17452 ((INSTANCE) == TIM5) || \
17453 ((INSTANCE) == TIM6) || \
17454 ((INSTANCE) == TIM7) || \
17455 ((INSTANCE) == TIM8) || \
17456 ((INSTANCE) == TIM15) || \
17457 ((INSTANCE) == TIM16) || \
17458 ((INSTANCE) == TIM17) || \
17459 ((INSTANCE) == TIM20))
17460
17461 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
17462 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17463 ((INSTANCE) == TIM2) || \
17464 ((INSTANCE) == TIM3) || \
17465 ((INSTANCE) == TIM4) || \
17466 ((INSTANCE) == TIM5) || \
17467 ((INSTANCE) == TIM8) || \
17468 ((INSTANCE) == TIM15) || \
17469 ((INSTANCE) == TIM16) || \
17470 ((INSTANCE) == TIM17) || \
17471 ((INSTANCE) == TIM20))
17472
17473 /******************** TIM Instances : DMA burst feature ***********************/
17474 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17475 ((INSTANCE) == TIM2) || \
17476 ((INSTANCE) == TIM3) || \
17477 ((INSTANCE) == TIM4) || \
17478 ((INSTANCE) == TIM5) || \
17479 ((INSTANCE) == TIM8) || \
17480 ((INSTANCE) == TIM15) || \
17481 ((INSTANCE) == TIM16) || \
17482 ((INSTANCE) == TIM17) || \
17483 ((INSTANCE) == TIM20))
17484
17485 /******************* TIM Instances : output(s) available **********************/
17486 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
17487 ((((INSTANCE) == TIM1) && \
17488 (((CHANNEL) == TIM_CHANNEL_1) || \
17489 ((CHANNEL) == TIM_CHANNEL_2) || \
17490 ((CHANNEL) == TIM_CHANNEL_3) || \
17491 ((CHANNEL) == TIM_CHANNEL_4) || \
17492 ((CHANNEL) == TIM_CHANNEL_5) || \
17493 ((CHANNEL) == TIM_CHANNEL_6))) \
17494 || \
17495 (((INSTANCE) == TIM2) && \
17496 (((CHANNEL) == TIM_CHANNEL_1) || \
17497 ((CHANNEL) == TIM_CHANNEL_2) || \
17498 ((CHANNEL) == TIM_CHANNEL_3) || \
17499 ((CHANNEL) == TIM_CHANNEL_4))) \
17500 || \
17501 (((INSTANCE) == TIM3) && \
17502 (((CHANNEL) == TIM_CHANNEL_1) || \
17503 ((CHANNEL) == TIM_CHANNEL_2) || \
17504 ((CHANNEL) == TIM_CHANNEL_3) || \
17505 ((CHANNEL) == TIM_CHANNEL_4))) \
17506 || \
17507 (((INSTANCE) == TIM4) && \
17508 (((CHANNEL) == TIM_CHANNEL_1) || \
17509 ((CHANNEL) == TIM_CHANNEL_2) || \
17510 ((CHANNEL) == TIM_CHANNEL_3) || \
17511 ((CHANNEL) == TIM_CHANNEL_4))) \
17512 || \
17513 (((INSTANCE) == TIM5) && \
17514 (((CHANNEL) == TIM_CHANNEL_1) || \
17515 ((CHANNEL) == TIM_CHANNEL_2) || \
17516 ((CHANNEL) == TIM_CHANNEL_3) || \
17517 ((CHANNEL) == TIM_CHANNEL_4))) \
17518 || \
17519 (((INSTANCE) == TIM8) && \
17520 (((CHANNEL) == TIM_CHANNEL_1) || \
17521 ((CHANNEL) == TIM_CHANNEL_2) || \
17522 ((CHANNEL) == TIM_CHANNEL_3) || \
17523 ((CHANNEL) == TIM_CHANNEL_4) || \
17524 ((CHANNEL) == TIM_CHANNEL_5) || \
17525 ((CHANNEL) == TIM_CHANNEL_6))) \
17526 || \
17527 (((INSTANCE) == TIM15) && \
17528 (((CHANNEL) == TIM_CHANNEL_1) || \
17529 ((CHANNEL) == TIM_CHANNEL_2))) \
17530 || \
17531 (((INSTANCE) == TIM16) && \
17532 (((CHANNEL) == TIM_CHANNEL_1))) \
17533 || \
17534 (((INSTANCE) == TIM17) && \
17535 (((CHANNEL) == TIM_CHANNEL_1))) \
17536 || \
17537 (((INSTANCE) == TIM20) && \
17538 (((CHANNEL) == TIM_CHANNEL_1) || \
17539 ((CHANNEL) == TIM_CHANNEL_2) || \
17540 ((CHANNEL) == TIM_CHANNEL_3) || \
17541 ((CHANNEL) == TIM_CHANNEL_4) || \
17542 ((CHANNEL) == TIM_CHANNEL_5) || \
17543 ((CHANNEL) == TIM_CHANNEL_6))))
17544
17545 /****************** TIM Instances : supporting complementary output(s) ********/
17546 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
17547 ((((INSTANCE) == TIM1) && \
17548 (((CHANNEL) == TIM_CHANNEL_1) || \
17549 ((CHANNEL) == TIM_CHANNEL_2) || \
17550 ((CHANNEL) == TIM_CHANNEL_3) || \
17551 ((CHANNEL) == TIM_CHANNEL_4))) \
17552 || \
17553 (((INSTANCE) == TIM8) && \
17554 (((CHANNEL) == TIM_CHANNEL_1) || \
17555 ((CHANNEL) == TIM_CHANNEL_2) || \
17556 ((CHANNEL) == TIM_CHANNEL_3) || \
17557 ((CHANNEL) == TIM_CHANNEL_4))) \
17558 || \
17559 (((INSTANCE) == TIM15) && \
17560 ((CHANNEL) == TIM_CHANNEL_1)) \
17561 || \
17562 (((INSTANCE) == TIM16) && \
17563 ((CHANNEL) == TIM_CHANNEL_1)) \
17564 || \
17565 (((INSTANCE) == TIM17) && \
17566 ((CHANNEL) == TIM_CHANNEL_1)) \
17567 || \
17568 (((INSTANCE) == TIM20) && \
17569 (((CHANNEL) == TIM_CHANNEL_1) || \
17570 ((CHANNEL) == TIM_CHANNEL_2) || \
17571 ((CHANNEL) == TIM_CHANNEL_3) || \
17572 ((CHANNEL) == TIM_CHANNEL_4))))
17573
17574 /****************** TIM Instances : supporting clock division *****************/
17575 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17576 ((INSTANCE) == TIM2) || \
17577 ((INSTANCE) == TIM3) || \
17578 ((INSTANCE) == TIM4) || \
17579 ((INSTANCE) == TIM5) || \
17580 ((INSTANCE) == TIM8) || \
17581 ((INSTANCE) == TIM15) || \
17582 ((INSTANCE) == TIM16) || \
17583 ((INSTANCE) == TIM17) || \
17584 ((INSTANCE) == TIM20))
17585
17586 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
17587 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17588 ((INSTANCE) == TIM2) || \
17589 ((INSTANCE) == TIM3) || \
17590 ((INSTANCE) == TIM4) || \
17591 ((INSTANCE) == TIM5) || \
17592 ((INSTANCE) == TIM8) || \
17593 ((INSTANCE) == TIM20))
17594
17595 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
17596 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17597 ((INSTANCE) == TIM2) || \
17598 ((INSTANCE) == TIM3) || \
17599 ((INSTANCE) == TIM4) || \
17600 ((INSTANCE) == TIM5) || \
17601 ((INSTANCE) == TIM8) || \
17602 ((INSTANCE) == TIM20))
17603
17604 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
17605 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17606 ((INSTANCE) == TIM2) || \
17607 ((INSTANCE) == TIM3) || \
17608 ((INSTANCE) == TIM4) || \
17609 ((INSTANCE) == TIM5) || \
17610 ((INSTANCE) == TIM8) || \
17611 ((INSTANCE) == TIM15)|| \
17612 ((INSTANCE) == TIM20))
17613
17614 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
17615 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17616 ((INSTANCE) == TIM2) || \
17617 ((INSTANCE) == TIM3) || \
17618 ((INSTANCE) == TIM4) || \
17619 ((INSTANCE) == TIM5) || \
17620 ((INSTANCE) == TIM8) || \
17621 ((INSTANCE) == TIM15)|| \
17622 ((INSTANCE) == TIM20))
17623
17624 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
17625 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17626 ((INSTANCE) == TIM8) || \
17627 ((INSTANCE) == TIM20))
17628
17629 /****************** TIM Instances : supporting commutation event generation ***/
17630 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17631 ((INSTANCE) == TIM8) || \
17632 ((INSTANCE) == TIM15) || \
17633 ((INSTANCE) == TIM16) || \
17634 ((INSTANCE) == TIM17) || \
17635 ((INSTANCE) == TIM20))
17636
17637 /****************** TIM Instances : supporting counting mode selection ********/
17638 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17639 ((INSTANCE) == TIM2) || \
17640 ((INSTANCE) == TIM3) || \
17641 ((INSTANCE) == TIM4) || \
17642 ((INSTANCE) == TIM5) || \
17643 ((INSTANCE) == TIM8) || \
17644 ((INSTANCE) == TIM20))
17645
17646 /****************** TIM Instances : supporting encoder interface **************/
17647 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17648 ((INSTANCE) == TIM2) || \
17649 ((INSTANCE) == TIM3) || \
17650 ((INSTANCE) == TIM4) || \
17651 ((INSTANCE) == TIM5) || \
17652 ((INSTANCE) == TIM8) || \
17653 ((INSTANCE) == TIM20))
17654
17655 /****************** TIM Instances : supporting Hall sensor interface **********/
17656 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17657 ((INSTANCE) == TIM2) || \
17658 ((INSTANCE) == TIM3) || \
17659 ((INSTANCE) == TIM4) || \
17660 ((INSTANCE) == TIM5) || \
17661 ((INSTANCE) == TIM8) || \
17662 ((INSTANCE) == TIM15) || \
17663 ((INSTANCE) == TIM20))
17664
17665 /**************** TIM Instances : external trigger input available ************/
17666 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17667 ((INSTANCE) == TIM2) || \
17668 ((INSTANCE) == TIM3) || \
17669 ((INSTANCE) == TIM4) || \
17670 ((INSTANCE) == TIM5) || \
17671 ((INSTANCE) == TIM8) || \
17672 ((INSTANCE) == TIM20))
17673
17674 /************* TIM Instances : supporting ETR source selection ***************/
17675 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17676 ((INSTANCE) == TIM2) || \
17677 ((INSTANCE) == TIM3) || \
17678 ((INSTANCE) == TIM4) || \
17679 ((INSTANCE) == TIM5) || \
17680 ((INSTANCE) == TIM8) || \
17681 ((INSTANCE) == TIM20))
17682
17683 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
17684 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17685 ((INSTANCE) == TIM2) || \
17686 ((INSTANCE) == TIM3) || \
17687 ((INSTANCE) == TIM4) || \
17688 ((INSTANCE) == TIM5) || \
17689 ((INSTANCE) == TIM6) || \
17690 ((INSTANCE) == TIM7) || \
17691 ((INSTANCE) == TIM8) || \
17692 ((INSTANCE) == TIM15) || \
17693 ((INSTANCE) == TIM20))
17694
17695 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
17696 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17697 ((INSTANCE) == TIM2) || \
17698 ((INSTANCE) == TIM3) || \
17699 ((INSTANCE) == TIM4) || \
17700 ((INSTANCE) == TIM5) || \
17701 ((INSTANCE) == TIM8) || \
17702 ((INSTANCE) == TIM15) || \
17703 ((INSTANCE) == TIM20))
17704
17705 /****************** TIM Instances : supporting OCxREF clear *******************/
17706 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17707 ((INSTANCE) == TIM2) || \
17708 ((INSTANCE) == TIM3) || \
17709 ((INSTANCE) == TIM4) || \
17710 ((INSTANCE) == TIM5) || \
17711 ((INSTANCE) == TIM8) || \
17712 ((INSTANCE) == TIM15) || \
17713 ((INSTANCE) == TIM16) || \
17714 ((INSTANCE) == TIM17) || \
17715 ((INSTANCE) == TIM20))
17716
17717
17718 /****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
17719 #define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17720 ((INSTANCE) == TIM2) || \
17721 ((INSTANCE) == TIM3) || \
17722 ((INSTANCE) == TIM8) || \
17723 ((INSTANCE) == TIM15) || \
17724 ((INSTANCE) == TIM16) || \
17725 ((INSTANCE) == TIM17) || \
17726 ((INSTANCE) == TIM20))
17727
17728 /****************** TIM Instances : remapping capability **********************/
17729 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17730 ((INSTANCE) == TIM2) || \
17731 ((INSTANCE) == TIM3) || \
17732 ((INSTANCE) == TIM4) || \
17733 ((INSTANCE) == TIM5) || \
17734 ((INSTANCE) == TIM8) || \
17735 ((INSTANCE) == TIM20))
17736
17737 /****************** TIM Instances : supporting repetition counter *************/
17738 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17739 ((INSTANCE) == TIM8) || \
17740 ((INSTANCE) == TIM15) || \
17741 ((INSTANCE) == TIM16) || \
17742 ((INSTANCE) == TIM17) || \
17743 ((INSTANCE) == TIM20))
17744
17745 /****************** TIM Instances : supporting synchronization ****************/
17746 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
17747
17748 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
17749 #define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17750 ((INSTANCE) == TIM8) || \
17751 ((INSTANCE) == TIM20))
17752
17753 /******************* TIM Instances : Timer input XOR function *****************/
17754 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17755 ((INSTANCE) == TIM2) || \
17756 ((INSTANCE) == TIM3) || \
17757 ((INSTANCE) == TIM4) || \
17758 ((INSTANCE) == TIM5) || \
17759 ((INSTANCE) == TIM8) || \
17760 ((INSTANCE) == TIM15) || \
17761 ((INSTANCE) == TIM20))
17762
17763 /******************* TIM Instances : Timer input selection ********************/
17764 #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17765 ((INSTANCE) == TIM2) || \
17766 ((INSTANCE) == TIM3) || \
17767 ((INSTANCE) == TIM4) || \
17768 ((INSTANCE) == TIM5) || \
17769 ((INSTANCE) == TIM8) || \
17770 ((INSTANCE) == TIM15) || \
17771 ((INSTANCE) == TIM16) || \
17772 ((INSTANCE) == TIM17) || \
17773 ((INSTANCE) == TIM20))
17774
17775
17776 /****************** TIM Instances : Advanced timer instances *******************/
17777 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17778 ((INSTANCE) == TIM8) || \
17779 ((INSTANCE) == TIM20))
17780
17781
17782 /****************** TIM Instances : supporting HSE/32 request instances *******************/
17783 #define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16) || \
17784 ((INSTANCE) == TIM17))
17785
17786 /****************************** HRTIM Instances *******************************/
17787 #define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))
17788
17789 /******************** USART Instances : Synchronous mode **********************/
17790 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
17791 ((INSTANCE) == USART2) || \
17792 ((INSTANCE) == USART3))
17793
17794 /******************** UART Instances : Asynchronous mode **********************/
17795 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
17796 ((INSTANCE) == USART2) || \
17797 ((INSTANCE) == USART3) || \
17798 ((INSTANCE) == UART4) || \
17799 ((INSTANCE) == UART5))
17800
17801 /*********************** UART Instances : FIFO mode ***************************/
17802 #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
17803 ((INSTANCE) == USART2) || \
17804 ((INSTANCE) == USART3) || \
17805 ((INSTANCE) == UART4) || \
17806 ((INSTANCE) == UART5) || \
17807 ((INSTANCE) == LPUART1))
17808
17809 /*********************** UART Instances : SPI Slave mode **********************/
17810 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
17811 ((INSTANCE) == USART2) || \
17812 ((INSTANCE) == USART3))
17813
17814 /****************** UART Instances : Auto Baud Rate detection ****************/
17815 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
17816 ((INSTANCE) == USART2) || \
17817 ((INSTANCE) == USART3) || \
17818 ((INSTANCE) == UART4) || \
17819 ((INSTANCE) == UART5))
17820
17821 /****************** UART Instances : Driver Enable *****************/
17822 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
17823 ((INSTANCE) == USART2) || \
17824 ((INSTANCE) == USART3) || \
17825 ((INSTANCE) == UART4) || \
17826 ((INSTANCE) == UART5) || \
17827 ((INSTANCE) == LPUART1))
17828
17829 /******************** UART Instances : Half-Duplex mode **********************/
17830 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
17831 ((INSTANCE) == USART2) || \
17832 ((INSTANCE) == USART3) || \
17833 ((INSTANCE) == UART4) || \
17834 ((INSTANCE) == UART5) || \
17835 ((INSTANCE) == LPUART1))
17836
17837 /****************** UART Instances : Hardware Flow control ********************/
17838 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
17839 ((INSTANCE) == USART2) || \
17840 ((INSTANCE) == USART3) || \
17841 ((INSTANCE) == UART4) || \
17842 ((INSTANCE) == UART5) || \
17843 ((INSTANCE) == LPUART1))
17844
17845 /******************** UART Instances : LIN mode **********************/
17846 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
17847 ((INSTANCE) == USART2) || \
17848 ((INSTANCE) == USART3) || \
17849 ((INSTANCE) == UART4) || \
17850 ((INSTANCE) == UART5))
17851
17852 /******************** UART Instances : Wake-up from Stop mode **********************/
17853 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
17854 ((INSTANCE) == USART2) || \
17855 ((INSTANCE) == USART3) || \
17856 ((INSTANCE) == UART4) || \
17857 ((INSTANCE) == UART5) || \
17858 ((INSTANCE) == LPUART1))
17859
17860 /*********************** UART Instances : IRDA mode ***************************/
17861 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
17862 ((INSTANCE) == USART2) || \
17863 ((INSTANCE) == USART3) || \
17864 ((INSTANCE) == UART4) || \
17865 ((INSTANCE) == UART5))
17866
17867 /********************* USART Instances : Smard card mode ***********************/
17868 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
17869 ((INSTANCE) == USART2) || \
17870 ((INSTANCE) == USART3))
17871
17872 /******************** LPUART Instance *****************************************/
17873 #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
17874
17875 /****************************** IWDG Instances ********************************/
17876 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
17877
17878 /****************************** WWDG Instances ********************************/
17879 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
17880
17881 /****************************** UCPD Instances ********************************/
17882 #define IS_UCPD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == UCPD1)
17883
17884 /******************************* USB Instances *******************************/
17885 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
17886
17887 /**
17888 * @}
17889 */
17890
17891
17892 /******************************************************************************/
17893 /* For a painless codes migration between the STM32G4xx device product */
17894 /* lines, the aliases defined below are put in place to overcome the */
17895 /* differences in the interrupt handlers and IRQn definitions. */
17896 /* No need to update developed interrupt code when moving across */
17897 /* product lines within the same STM32G4 Family */
17898 /******************************************************************************/
17899
17900 /* Aliases for __IRQn */
17901
17902 /* Aliases for __IRQHandler */
17903
17904 #ifdef __cplusplus
17905 }
17906 #endif /* __cplusplus */
17907
17908 #endif /* __STM32G474xx_H */
17909
17910 /**
17911 * @}
17912 */
17913
17914 /**
17915 * @}
17916 */
17917
17918 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/