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Merge pull request #11270 from haslinghuis/rename_attr
[betaflight.git] / lib / main / STM32G4 / Drivers / CMSIS / Device / ST / STM32G4xx / Include / stm32gbk1cb.h
blob12797b0e28de8f0be467573a6af8594de0866dc1
1 /**
2 ******************************************************************************
3 * @file stm32gbk1cb.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32GBK1CB Device Peripheral Access Layer Header File.
6 *
7 * This file contains:
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral’s registers hardware
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
16 * All rights reserved.</center></h2>
17 *
18 * This software component is licensed by ST under BSD 3-Clause license,
19 * the "License"; You may not use this file except in compliance with the
20 * License. You may obtain a copy of the License at:
21 * opensource.org/licenses/BSD-3-Clause
22 *
23 ******************************************************************************
24 */
25
26 /** @addtogroup CMSIS_Device
27 * @{
28 */
29
30 /** @addtogroup stm32gbk1cb
31 * @{
32 */
33
34 #ifndef __STM32GBK1CB_H
35 #define __STM32GBK1CB_H
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif /* __cplusplus */
40
41 /** @addtogroup Configuration_section_for_CMSIS
42 * @{
43 */
44
45 /**
46 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
47 */
48 #define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
49 #define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */
50 #define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */
51 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
52 #define __FPU_PRESENT 1 /*!< FPU present */
53
54 /**
55 * @}
56 */
57
58 /** @addtogroup Peripheral_interrupt_number_definition
59 * @{
60 */
61
62 /**
63 * @brief STM32G4XX Interrupt Number Definition, according to the selected device
64 * in @ref Library_configuration_section
65 */
66 typedef enum
67 {
68 /****** Cortex-M4 Processor Exceptions Numbers *********************************************************************************/
69 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
70 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
71 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
72 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
73 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
74 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
75 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
76 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
77 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
78 /****** STM32 specific Interrupt Numbers ***************************************************************************************/
79 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
80 PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
81 RTC_TAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI */
82 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
83 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
84 RCC_IRQn = 5, /*!< RCC global Interrupt */
85 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
86 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
87 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
88 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
89 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
90 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
91 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
92 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
93 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
94 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
95 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
96 ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
97 USB_HP_IRQn = 19, /*!< USB HP Interrupt */
98 USB_LP_IRQn = 20, /*!< USB LP Interrupt */
99 FDCAN1_IT0_IRQn = 21, /*!< FDCAN1 IT0 Interrupt */
100 FDCAN1_IT1_IRQn = 22, /*!< FDCAN1 IT1 Interrupt */
101 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
102 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt */
103 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */
104 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */
105 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
106 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
107 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
108 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
109 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
110 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
111 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
112 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
113 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
114 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
115 USART1_IRQn = 37, /*!< USART1 global Interrupt */
116 USART2_IRQn = 38, /*!< USART2 global Interrupt */
117 USART3_IRQn = 39, /*!< USART3 global Interrupt */
118 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
119 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
120 USBWakeUp_IRQn = 42, /*!< USB Wakeup through EXTI line Interrupt */
121 TIM8_BRK_IRQn = 43, /*!< TIM8 Break, Transition error and Index error Interrupt */
122 TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
123 TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt */
124 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
125 LPTIM1_IRQn = 49, /*!< LP TIM1 Interrupt */
126 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
127 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&3 underrun error interrupts */
128 TIM7_IRQn = 55, /*!< TIM7 global interrupts */
129 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
130 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
131 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
132 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
133 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
134 UCPD1_IRQn = 63, /*!< UCPD global Interrupt */
135 COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 Interrupts */
136 COMP4_IRQn = 65, /*!< COMP4 */
137 CRS_IRQn = 75, /*!< CRS global interrupt */
138 SAI1_IRQn = 76, /*!< Serial Audio Interface global interrupt */
139 FPU_IRQn = 81, /*!< FPU global interrupt */
140 RNG_IRQn = 90, /*!< RNG global interrupt */
141 LPUART1_IRQn = 91, /*!< LP UART 1 Interrupt */
142 I2C3_EV_IRQn = 92, /*!< I2C3 Event Interrupt */
143 I2C3_ER_IRQn = 93, /*!< I2C3 Error interrupt */
144 DMAMUX_OVR_IRQn = 94, /*!< DMAMUX overrun global interrupt */
145 DMA2_Channel6_IRQn = 97, /*!< DMA2 Channel 6 interrupt */
146 CORDIC_IRQn = 100, /*!< CORDIC global Interrupt */
147 FMAC_IRQn = 101 /*!< FMAC global Interrupt */
148 } IRQn_Type;
149
150 /**
151 * @}
152 */
153
154 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
155 #include "system_stm32g4xx.h"
156 #include <stdint.h>
157
158 /** @addtogroup Peripheral_registers_structures
159 * @{
160 */
161
162 /**
163 * @brief Analog to Digital Converter
164 */
165
166 typedef struct
167 {
168 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
169 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
170 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
171 __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
172 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
173 __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
174 __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
175 uint32_t RESERVED1; /*!< Reserved, 0x1C */
176 __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
177 __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
178 __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
179 uint32_t RESERVED2; /*!< Reserved, 0x2C */
180 __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
181 __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
182 __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
183 __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
184 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
185 uint32_t RESERVED3; /*!< Reserved, 0x44 */
186 uint32_t RESERVED4; /*!< Reserved, 0x48 */
187 __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
188 uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
189 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
190 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
191 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
192 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
193 uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
194 __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
195 __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
196 __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
197 __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
198 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
199 __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */
200 __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
201 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
202 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
203 __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
204 __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
205 uint32_t RESERVED10[2];/*!< Reserved, 0x0B8 - 0x0BC */
206 __IO uint32_t GCOMP; /*!< ADC calibration factors, Address offset: 0xC0 */
207 } ADC_TypeDef;
208
209 typedef struct
210 {
211 __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */
212 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */
213 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */
214 __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */
215 } ADC_Common_TypeDef;
216
217 /**
218 * @brief FD Controller Area Network
219 */
220
221 typedef struct
222 {
223 __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
224 __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
225 uint32_t RESERVED1; /*!< Reserved, 0x008 */
226 __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
227 __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
228 __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
229 __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
230 __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
231 __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
232 __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
233 __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
234 __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
235 uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
236 __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
237 __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
238 __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
239 uint32_t RESERVED3; /*!< Reserved, 0x04C */
240 __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
241 __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
242 __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
243 __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
244 uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
245 __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
246 __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */
247 __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */
248 uint32_t RESERVED5; /*!< Reserved, 0x08C */
249 __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */
250 __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */
251 __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */
252 __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */
253 uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */
254 __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
255 __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
256 __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */
257 __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */
258 __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */
259 __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */
260 __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */
261 __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */
262 __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */
263 __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */
264 __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */
265 } FDCAN_GlobalTypeDef;
266
267 /**
268 * @brief FD Controller Area Network Configuration
269 */
270
271 typedef struct
272 {
273 __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */
274 } FDCAN_Config_TypeDef;
275
276 /**
277 * @brief Comparator
278 */
279
280 typedef struct
281 {
282 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
283 } COMP_TypeDef;
284
285 /**
286 * @brief CRC calculation unit
287 */
288
289 typedef struct
290 {
291 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
292 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
293 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
294 uint32_t RESERVED0; /*!< Reserved, 0x0C */
295 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
296 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
297 } CRC_TypeDef;
298
299 /**
300 * @brief Clock Recovery System
301 */
302 typedef struct
303 {
304 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
305 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
306 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
307 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
308 } CRS_TypeDef;
309
310 /**
311 * @brief Digital to Analog Converter
312 */
313
314 typedef struct
315 {
316 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
317 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
318 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
319 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
320 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
321 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
322 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
323 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
324 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
325 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
326 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
327 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
328 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
329 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
330 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
331 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
332 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
333 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
334 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
335 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
336 __IO uint32_t RESERVED[2];
337 __IO uint32_t STR1; /*!< DAC Sawtooth register, Address offset: 0x58 */
338 __IO uint32_t STR2; /*!< DAC Sawtooth register, Address offset: 0x5C */
339 __IO uint32_t STMODR; /*!< DAC Sawtooth Mode register, Address offset: 0x60 */
340 } DAC_TypeDef;
341
342 /**
343 * @brief Debug MCU
344 */
345
346 typedef struct
347 {
348 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
349 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
350 __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
351 __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
352 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
353 } DBGMCU_TypeDef;
354
355 /**
356 * @brief DMA Controller
357 */
358
359 typedef struct
360 {
361 __IO uint32_t CCR; /*!< DMA channel x configuration register */
362 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
363 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
364 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
365 } DMA_Channel_TypeDef;
366
367 typedef struct
368 {
369 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
370 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
371 } DMA_TypeDef;
372
373 /**
374 * @brief DMA Multiplexer
375 */
376
377 typedef struct
378 {
379 __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */
380 }DMAMUX_Channel_TypeDef;
381
382 typedef struct
383 {
384 __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */
385 __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */
386 }DMAMUX_ChannelStatus_TypeDef;
387
388 typedef struct
389 {
390 __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */
391 }DMAMUX_RequestGen_TypeDef;
392
393 typedef struct
394 {
395 __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */
396 __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */
397 }DMAMUX_RequestGenStatus_TypeDef;
398
399 /**
400 * @brief External Interrupt/Event Controller
401 */
402
403 typedef struct
404 {
405 __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */
406 __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */
407 __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */
408 __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */
409 __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */
410 __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */
411 uint32_t RESERVED1; /*!< Reserved, 0x18 */
412 uint32_t RESERVED2; /*!< Reserved, 0x1C */
413 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */
414 __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */
415 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */
416 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */
417 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */
418 __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */
419 } EXTI_TypeDef;
420
421 /**
422 * @brief FLASH Registers
423 */
424
425 typedef struct
426 {
427 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
428 __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */
429 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */
430 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */
431 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */
432 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */
433 __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
434 uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */
435 __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */
436 __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
437 __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
438 __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
439 __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
440 uint32_t RESERVED2[15]; /*!< Reserved2, Address offset: 0x34 */
441 __IO uint32_t SEC1R; /*!< FLASH Securable memory register bank1, Address offset: 0x70 */
442 } FLASH_TypeDef;
443
444 /**
445 * @brief FMAC
446 */
447 typedef struct
448 {
449 __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */
450 __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */
451 __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */
452 __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */
453 __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */
454 __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */
455 __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */
456 __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */
457 } FMAC_TypeDef;
458
459
460 /**
461 * @brief General Purpose I/O
462 */
463
464 typedef struct
465 {
466 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
467 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
468 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
469 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
470 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
471 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
472 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
473 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
474 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
475 __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
476 } GPIO_TypeDef;
477
478 /**
479 * @brief Inter-integrated Circuit Interface
480 */
481
482 typedef struct
483 {
484 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
485 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
486 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
487 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
488 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
489 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
490 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
491 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
492 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
493 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
494 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
495 } I2C_TypeDef;
496
497 /**
498 * @brief Independent WATCHDOG
499 */
500
501 typedef struct
502 {
503 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
504 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
505 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
506 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
507 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
508 } IWDG_TypeDef;
509
510 /**
511 * @brief LPTIMER
512 */
513
514 typedef struct
515 {
516 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
517 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
518 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
519 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
520 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
521 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
522 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
523 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
524 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
525 } LPTIM_TypeDef;
526
527 /**
528 * @brief Operational Amplifier (OPAMP)
529 */
530
531 typedef struct
532 {
533 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
534 __IO uint32_t RESERVED[5]; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
535 __IO uint32_t TCMR; /*!< OPAMP timer controlled mux mode register, Address offset: 0x18 */
536 } OPAMP_TypeDef;
537
538 /**
539 * @brief Power Control
540 */
541
542 typedef struct
543 {
544 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
545 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
546 __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
547 __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */
548 __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */
549 __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */
550 __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */
551 uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */
552 __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */
553 __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
554 __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */
555 __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
556 __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */
557 __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
558 __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */
559 __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
560 __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */
561 __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
562 __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */
563 __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */
564 __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */
565 __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */
566 uint32_t RESERVED1[10]; /*!< Reserved Address offset: 0x58 - 0x7C */
567 __IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */
568 } PWR_TypeDef;
569
570
571 /**
572 * @brief Reset and Clock Control
573 */
574
575 typedef struct
576 {
577 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
578 __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */
579 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
580 __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */
581 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */
582 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
583 __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */
584 __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */
585 __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */
586 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */
587 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
588 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
589 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */
590 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */
591 __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
592 __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
593 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
594 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x44 */
595 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
596 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
597 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */
598 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x54 */
599 __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
600 __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
601 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
602 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x64 */
603 __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
604 __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
605 __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
606 uint32_t RESERVED7; /*!< Reserved, Address offset: 0x74 */
607 __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
608 __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
609 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
610 uint32_t RESERVED8; /*!< Reserved, Address offset: 0x84 */
611 __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */
612 uint32_t RESERVED9; /*!< Reserved, Address offset: 0x8C */
613 __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */
614 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */
615 __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */
616 __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */
617 } RCC_TypeDef;
618
619 /**
620 * @brief Real-Time Clock
621 */
622 /*
623 * @brief Specific device feature definitions
624 */
625 #define RTC_TAMP_INT_6_SUPPORT
626 #define RTC_TAMP_INT_NB 4u
627
628 #define RTC_TAMP_NB 3u
629 #define RTC_BACKUP_NB 16u
630
631
632 typedef struct
633 {
634 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
635 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
636 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */
637 __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
638 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
639 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
640 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
641 uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */
642 uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */
643 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
644 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
645 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
646 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
647 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
648 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
649 uint32_t RESERVED2; /*!< Reserved Address offset: 0x3C */
650 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
651 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
652 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */
653 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */
654 __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */
655 __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */
656 uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */
657 __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */
658 } RTC_TypeDef;
659
660 /**
661 * @brief Tamper and backup registers
662 */
663
664 typedef struct
665 {
666 __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */
667 __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */
668 uint32_t RESERVED0; /*!< no configuration register 3, Address offset: 0x08 */
669 __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */
670 uint32_t RESERVED1[6]; /*!< Reserved Address offset: 0x10 - 0x24 */
671 uint32_t RESERVED2; /*!< Reserved Address offset: 0x28 */
672 __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */
673 __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */
674 __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register Address offset: 0x34 */
675 uint32_t RESERVED3; /*!< Reserved Address offset: 0x38 */
676 __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */
677 uint32_t RESERVED4[48]; /*!< Reserved Address offset: 0x040 - 0xFC */
678 __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
679 __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
680 __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
681 __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */
682 __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */
683 __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */
684 __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */
685 __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */
686 __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */
687 __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */
688 __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */
689 __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */
690 __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */
691 __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */
692 __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */
693 __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */
694 } TAMP_TypeDef;
695
696 /**
697 * @brief Serial Audio Interface
698 */
699
700 typedef struct
701 {
702 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
703 uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */
704 __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
705 __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
706 } SAI_TypeDef;
707
708 typedef struct
709 {
710 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
711 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
712 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
713 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
714 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
715 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
716 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
717 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
718 } SAI_Block_TypeDef;
719
720 /**
721 * @brief Serial Peripheral Interface
722 */
723
724 typedef struct
725 {
726 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
727 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
728 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
729 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
730 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
731 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
732 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
733 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
734 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
735 } SPI_TypeDef;
736
737 /**
738 * @brief System configuration controller
739 */
740
741 typedef struct
742 {
743 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
744 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
745 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
746 __IO uint32_t SCSR; /*!< SYSCFG CCMSRAM control and status register, Address offset: 0x18 */
747 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */
748 __IO uint32_t SWPR; /*!< SYSCFG CCMSRAM write protection register, Address offset: 0x20 */
749 __IO uint32_t SKR; /*!< SYSCFG CCMSRAM Key Register, Address offset: 0x24 */
750 } SYSCFG_TypeDef;
751
752 /**
753 * @brief TIM
754 */
755
756 typedef struct
757 {
758 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
759 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
760 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
761 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
762 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
763 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
764 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
765 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
766 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
767 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
768 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
769 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
770 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
771 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
772 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
773 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
774 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
775 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
776 __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */
777 __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */
778 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */
779 __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */
780 __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */
781 __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */
782 __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
783 __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
784 __IO uint32_t OR ; /*!< TIM option register, Address offset: 0x68 */
785 uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */
786 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */
787 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */
788 } TIM_TypeDef;
789
790 /**
791 * @brief Universal Synchronous Asynchronous Receiver Transmitter
792 */
793 typedef struct
794 {
795 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
796 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
797 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
798 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
799 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
800 __IO uint32_t RTOR; /*!< USART Receiver Timeout register, Address offset: 0x14 */
801 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
802 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
803 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
804 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
805 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
806 __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
807 } USART_TypeDef;
808
809 /**
810 * @brief Universal Serial Bus Full Speed Device
811 */
812
813 typedef struct
814 {
815 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
816 __IO uint16_t RESERVED0; /*!< Reserved */
817 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
818 __IO uint16_t RESERVED1; /*!< Reserved */
819 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
820 __IO uint16_t RESERVED2; /*!< Reserved */
821 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
822 __IO uint16_t RESERVED3; /*!< Reserved */
823 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
824 __IO uint16_t RESERVED4; /*!< Reserved */
825 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
826 __IO uint16_t RESERVED5; /*!< Reserved */
827 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
828 __IO uint16_t RESERVED6; /*!< Reserved */
829 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
830 __IO uint16_t RESERVED7[17]; /*!< Reserved */
831 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
832 __IO uint16_t RESERVED8; /*!< Reserved */
833 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
834 __IO uint16_t RESERVED9; /*!< Reserved */
835 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
836 __IO uint16_t RESERVEDA; /*!< Reserved */
837 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
838 __IO uint16_t RESERVEDB; /*!< Reserved */
839 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
840 __IO uint16_t RESERVEDC; /*!< Reserved */
841 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
842 __IO uint16_t RESERVEDD; /*!< Reserved */
843 __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
844 __IO uint16_t RESERVEDE; /*!< Reserved */
845 } USB_TypeDef;
846
847
848 /**
849 * @brief Window WATCHDOG
850 */
851
852 typedef struct
853 {
854 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
855 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
856 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
857 } WWDG_TypeDef;
858
859
860 /**
861 * @brief RNG
862 */
863 typedef struct
864 {
865 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
866 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
867 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
868 } RNG_TypeDef;
869
870 /**
871 * @brief CORDIC
872 */
873
874 typedef struct
875 {
876 __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */
877 __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */
878 __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */
879 } CORDIC_TypeDef;
880
881 /**
882 * @brief UCPD
883 */
884
885 typedef struct
886 {
887 __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */
888 __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */
889 __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */
890 __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */
891 __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */
892 __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */
893 __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */
894 __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */
895 __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */
896 __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */
897 __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */
898 __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */
899 __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */
900 __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */
901 __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */
902 } UCPD_TypeDef;
903
904
905 /** @addtogroup Peripheral_memory_map
906 * @{
907 */
908
909 #define FLASH_BASE (0x08000000UL) /*!< FLASH (up to 128 kB) base address */
910 #define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 16 KB) base address */
911 #define SRAM2_BASE (0x20004000UL) /*!< SRAM2(6 KB) base address */
912 #define CCMSRAM_BASE (0x10000000UL) /*!< CCMSRAM(10 KB) base address */
913 #define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
914
915 #define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(16 KB) base address in the bit-band region */
916 #define SRAM2_BB_BASE (0x22080000UL) /*!< SRAM2(6 KB) base address in the bit-band region */
917 #define CCMSRAM_BB_BASE (0x220B0000UL) /*!< CCMSRAM(10 KB) base address in the bit-band region */
918 #define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */
919 /* Legacy defines */
920 #define SRAM_BASE SRAM1_BASE
921 #define SRAM_BB_BASE SRAM1_BB_BASE
922
923 #define SRAM1_SIZE_MAX (0x00004000UL) /*!< maximum SRAM1 size (up to 16 KBytes) */
924 #define SRAM2_SIZE (0x00001800UL) /*!< SRAM2 size (6 KBytes) */
925 #define CCMSRAM_SIZE (0x00002800UL) /*!< CCMSRAM size (10 KBytes) */
926
927 /*!< Peripheral memory map */
928 #define APB1PERIPH_BASE PERIPH_BASE
929 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
930 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
931 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
932
933
934 /*!< APB1 peripherals */
935 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
936 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
937 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
938 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
939 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
940 #define CRS_BASE (APB1PERIPH_BASE + 0x2000UL)
941 #define TAMP_BASE (APB1PERIPH_BASE + 0x2400UL)
942 #define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
943 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
944 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
945 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
946 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
947 #define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
948 #define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
949 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
950 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
951 #define USB_BASE (APB1PERIPH_BASE + 0x5C00UL) /*!< USB_IP Peripheral Registers base address */
952 #define USB_PMAADDR (APB1PERIPH_BASE + 0x6000UL) /*!< USB_IP Packet Memory Area base address */
953 #define FDCAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
954 #define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0x6500UL) /*!< FDCAN configuration registers base address */
955 #define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
956 #define I2C3_BASE (APB1PERIPH_BASE + 0x7800UL)
957 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL)
958 #define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL)
959 #define UCPD1_BASE (APB1PERIPH_BASE + 0xA000UL)
960 #define SRAMCAN_BASE (APB1PERIPH_BASE + 0xA400UL)
961
962 /*!< APB2 peripherals */
963 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL)
964 #define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL)
965 #define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL)
966 #define COMP3_BASE (APB2PERIPH_BASE + 0x0208UL)
967 #define COMP4_BASE (APB2PERIPH_BASE + 0x020CUL)
968 #define OPAMP_BASE (APB2PERIPH_BASE + 0x0300UL)
969 #define OPAMP1_BASE (APB2PERIPH_BASE + 0x0300UL)
970 #define OPAMP2_BASE (APB2PERIPH_BASE + 0x0304UL)
971 #define OPAMP3_BASE (APB2PERIPH_BASE + 0x0308UL)
972
973 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL)
974 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL)
975 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
976 #define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL)
977 #define USART1_BASE (APB2PERIPH_BASE + 0x3800UL)
978 #define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL)
979 #define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL)
980 #define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL)
981 #define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL)
982 #define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL)
983 #define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL)
984
985 /*!< AHB1 peripherals */
986 #define DMA1_BASE (AHB1PERIPH_BASE)
987 #define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL)
988 #define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL)
989 #define CORDIC_BASE (AHB1PERIPH_BASE + 0x0C00UL)
990 #define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL)
991 #define FMAC_BASE (AHB1PERIPH_BASE + 0x1400UL)
992 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL)
993 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
994
995 #define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL)
996 #define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL)
997 #define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL)
998 #define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL)
999 #define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL)
1000 #define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL)
1001
1002 #define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL)
1003 #define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL)
1004 #define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL)
1005 #define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL)
1006 #define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL)
1007 #define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL)
1008
1009 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
1010 #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)
1011 #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)
1012 #define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)
1013 #define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)
1014 #define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)
1015 #define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0020UL)
1016 #define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0024UL)
1017 #define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0028UL)
1018 #define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x002CUL)
1019 #define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0030UL)
1020 #define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x0034UL)
1021 #define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)
1022 #define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)
1023 #define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)
1024 #define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)
1025
1026 #define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)
1027 #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)
1028
1029 /*!< AHB2 peripherals */
1030 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL)
1031 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL)
1032 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL)
1033 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL)
1034 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL)
1035 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL)
1036 #define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL)
1037
1038 #define ADC1_BASE (AHB2PERIPH_BASE + 0x08000000UL)
1039 #define ADC2_BASE (AHB2PERIPH_BASE + 0x08000100UL)
1040 #define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08000300UL)
1041
1042 #define DAC_BASE (AHB2PERIPH_BASE + 0x08000800UL)
1043 #define DAC1_BASE (AHB2PERIPH_BASE + 0x08000800UL)
1044 #define DAC3_BASE (AHB2PERIPH_BASE + 0x08001000UL)
1045
1046 #define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL)
1047 /* Debug MCU registers base address */
1048 #define DBGMCU_BASE (0xE0042000UL)
1049
1050 #define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */
1051 #define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */
1052 #define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */
1053 /**
1054 * @}
1055 */
1056
1057 /** @addtogroup Peripheral_declaration
1058 * @{
1059 */
1060 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1061 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1062 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1063 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1064 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1065 #define CRS ((CRS_TypeDef *) CRS_BASE)
1066 #define TAMP ((TAMP_TypeDef *) TAMP_BASE)
1067 #define RTC ((RTC_TypeDef *) RTC_BASE)
1068 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1069 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1070 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1071 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1072 #define USART2 ((USART_TypeDef *) USART2_BASE)
1073 #define USART3 ((USART_TypeDef *) USART3_BASE)
1074 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1075 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1076 #define USB ((USB_TypeDef *) USB_BASE)
1077 #define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
1078 #define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE)
1079 #define PWR ((PWR_TypeDef *) PWR_BASE)
1080 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1081 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1082 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
1083 #define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE)
1084
1085 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1086 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
1087 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
1088 #define COMP3 ((COMP_TypeDef *) COMP3_BASE)
1089 #define COMP4 ((COMP_TypeDef *) COMP4_BASE)
1090
1091 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
1092 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
1093 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
1094 #define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)
1095
1096 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1097 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1098 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1099 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1100 #define USART1 ((USART_TypeDef *) USART1_BASE)
1101 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
1102 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
1103 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
1104 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1105 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1106 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1107 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1108 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1109 #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
1110 #define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE)
1111 #define RCC ((RCC_TypeDef *) RCC_BASE)
1112 #define FMAC ((FMAC_TypeDef *) FMAC_BASE)
1113 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1114 #define CRC ((CRC_TypeDef *) CRC_BASE)
1115
1116 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1117 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1118 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1119 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1120 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1121 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1122 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1123 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1124 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1125 #define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
1126 #define DAC ((DAC_TypeDef *) DAC_BASE)
1127 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
1128 #define DAC3 ((DAC_TypeDef *) DAC3_BASE)
1129 #define RNG ((RNG_TypeDef *) RNG_BASE)
1130
1131 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
1132 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
1133 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
1134 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
1135 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
1136 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
1137
1138 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
1139 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
1140 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
1141 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
1142 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
1143 #define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
1144
1145 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
1146 #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
1147 #define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
1148 #define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
1149 #define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
1150 #define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
1151 #define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
1152 #define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
1153 #define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
1154 #define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
1155 #define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
1156 #define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
1157
1158 #define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
1159 #define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
1160 #define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
1161 #define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
1162
1163 #define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
1164 #define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
1165
1166
1167
1168 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1169
1170 /**
1171 * @}
1172 */
1173
1174 /** @addtogroup Exported_constants
1175 * @{
1176 */
1177
1178 /** @addtogroup Peripheral_Registers_Bits_Definition
1179 * @{
1180 */
1181
1182 /******************************************************************************/
1183 /* Peripheral Registers_Bits_Definition */
1184 /******************************************************************************/
1185
1186 /******************************************************************************/
1187 /* */
1188 /* Analog to Digital Converter */
1189 /* */
1190 /******************************************************************************/
1191
1192 /*
1193 * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
1194 */
1195 #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
1196
1197 /******************** Bit definition for ADC_ISR register *******************/
1198 #define ADC_ISR_ADRDY_Pos (0U)
1199 #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
1200 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
1201 #define ADC_ISR_EOSMP_Pos (1U)
1202 #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
1203 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
1204 #define ADC_ISR_EOC_Pos (2U)
1205 #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
1206 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
1207 #define ADC_ISR_EOS_Pos (3U)
1208 #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
1209 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
1210 #define ADC_ISR_OVR_Pos (4U)
1211 #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
1212 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
1213 #define ADC_ISR_JEOC_Pos (5U)
1214 #define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
1215 #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
1216 #define ADC_ISR_JEOS_Pos (6U)
1217 #define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
1218 #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
1219 #define ADC_ISR_AWD1_Pos (7U)
1220 #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
1221 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
1222 #define ADC_ISR_AWD2_Pos (8U)
1223 #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
1224 #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
1225 #define ADC_ISR_AWD3_Pos (9U)
1226 #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
1227 #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
1228 #define ADC_ISR_JQOVF_Pos (10U)
1229 #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
1230 #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
1231
1232 /******************** Bit definition for ADC_IER register *******************/
1233 #define ADC_IER_ADRDYIE_Pos (0U)
1234 #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
1235 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
1236 #define ADC_IER_EOSMPIE_Pos (1U)
1237 #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
1238 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
1239 #define ADC_IER_EOCIE_Pos (2U)
1240 #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
1241 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
1242 #define ADC_IER_EOSIE_Pos (3U)
1243 #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
1244 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
1245 #define ADC_IER_OVRIE_Pos (4U)
1246 #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
1247 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
1248 #define ADC_IER_JEOCIE_Pos (5U)
1249 #define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
1250 #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
1251 #define ADC_IER_JEOSIE_Pos (6U)
1252 #define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
1253 #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
1254 #define ADC_IER_AWD1IE_Pos (7U)
1255 #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
1256 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
1257 #define ADC_IER_AWD2IE_Pos (8U)
1258 #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
1259 #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
1260 #define ADC_IER_AWD3IE_Pos (9U)
1261 #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
1262 #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
1263 #define ADC_IER_JQOVFIE_Pos (10U)
1264 #define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
1265 #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
1266
1267 /******************** Bit definition for ADC_CR register ********************/
1268 #define ADC_CR_ADEN_Pos (0U)
1269 #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
1270 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
1271 #define ADC_CR_ADDIS_Pos (1U)
1272 #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
1273 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
1274 #define ADC_CR_ADSTART_Pos (2U)
1275 #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
1276 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
1277 #define ADC_CR_JADSTART_Pos (3U)
1278 #define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
1279 #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
1280 #define ADC_CR_ADSTP_Pos (4U)
1281 #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
1282 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
1283 #define ADC_CR_JADSTP_Pos (5U)
1284 #define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
1285 #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
1286 #define ADC_CR_ADVREGEN_Pos (28U)
1287 #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
1288 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
1289 #define ADC_CR_DEEPPWD_Pos (29U)
1290 #define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
1291 #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */
1292 #define ADC_CR_ADCALDIF_Pos (30U)
1293 #define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
1294 #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
1295 #define ADC_CR_ADCAL_Pos (31U)
1296 #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
1297 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
1298
1299 /******************** Bit definition for ADC_CFGR register ******************/
1300 #define ADC_CFGR_DMAEN_Pos (0U)
1301 #define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
1302 #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */
1303 #define ADC_CFGR_DMACFG_Pos (1U)
1304 #define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
1305 #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */
1306
1307 #define ADC_CFGR_RES_Pos (3U)
1308 #define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
1309 #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
1310 #define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
1311 #define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
1312
1313 #define ADC_CFGR_EXTSEL_Pos (5U)
1314 #define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */
1315 #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
1316 #define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */
1317 #define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
1318 #define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
1319 #define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
1320 #define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
1321
1322 #define ADC_CFGR_EXTEN_Pos (10U)
1323 #define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
1324 #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
1325 #define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
1326 #define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
1327
1328 #define ADC_CFGR_OVRMOD_Pos (12U)
1329 #define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
1330 #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
1331 #define ADC_CFGR_CONT_Pos (13U)
1332 #define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
1333 #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
1334 #define ADC_CFGR_AUTDLY_Pos (14U)
1335 #define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
1336 #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
1337 #define ADC_CFGR_ALIGN_Pos (15U)
1338 #define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */
1339 #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
1340 #define ADC_CFGR_DISCEN_Pos (16U)
1341 #define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
1342 #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
1343
1344 #define ADC_CFGR_DISCNUM_Pos (17U)
1345 #define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
1346 #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
1347 #define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
1348 #define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
1349 #define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
1350
1351 #define ADC_CFGR_JDISCEN_Pos (20U)
1352 #define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
1353 #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
1354 #define ADC_CFGR_JQM_Pos (21U)
1355 #define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
1356 #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
1357 #define ADC_CFGR_AWD1SGL_Pos (22U)
1358 #define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
1359 #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
1360 #define ADC_CFGR_AWD1EN_Pos (23U)
1361 #define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
1362 #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
1363 #define ADC_CFGR_JAWD1EN_Pos (24U)
1364 #define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
1365 #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
1366 #define ADC_CFGR_JAUTO_Pos (25U)
1367 #define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
1368 #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
1369
1370 #define ADC_CFGR_AWD1CH_Pos (26U)
1371 #define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
1372 #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
1373 #define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
1374 #define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
1375 #define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
1376 #define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
1377 #define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
1378
1379 #define ADC_CFGR_JQDIS_Pos (31U)
1380 #define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
1381 #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */
1382
1383 /******************** Bit definition for ADC_CFGR2 register *****************/
1384 #define ADC_CFGR2_ROVSE_Pos (0U)
1385 #define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
1386 #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
1387 #define ADC_CFGR2_JOVSE_Pos (1U)
1388 #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
1389 #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */
1390
1391 #define ADC_CFGR2_OVSR_Pos (2U)
1392 #define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
1393 #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
1394 #define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
1395 #define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
1396 #define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
1397
1398 #define ADC_CFGR2_OVSS_Pos (5U)
1399 #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
1400 #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
1401 #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
1402 #define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
1403 #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
1404 #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
1405
1406 #define ADC_CFGR2_TROVS_Pos (9U)
1407 #define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
1408 #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
1409 #define ADC_CFGR2_ROVSM_Pos (10U)
1410 #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
1411 #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
1412
1413 #define ADC_CFGR2_GCOMP_Pos (16U)
1414 #define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */
1415 #define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */
1416
1417 #define ADC_CFGR2_SWTRIG_Pos (25U)
1418 #define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */
1419 #define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */
1420 #define ADC_CFGR2_BULB_Pos (26U)
1421 #define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */
1422 #define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */
1423 #define ADC_CFGR2_SMPTRIG_Pos (27U)
1424 #define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */
1425 #define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */
1426
1427 #define ADC_CFGR2_LFTRIG_Pos (29U)
1428 #define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */
1429 #define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low Frequency Trigger */
1430
1431 /******************** Bit definition for ADC_SMPR1 register *****************/
1432 #define ADC_SMPR1_SMP0_Pos (0U)
1433 #define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
1434 #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
1435 #define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
1436 #define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
1437 #define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
1438
1439 #define ADC_SMPR1_SMP1_Pos (3U)
1440 #define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
1441 #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
1442 #define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
1443 #define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
1444 #define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
1445
1446 #define ADC_SMPR1_SMP2_Pos (6U)
1447 #define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
1448 #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
1449 #define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
1450 #define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
1451 #define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
1452
1453 #define ADC_SMPR1_SMP3_Pos (9U)
1454 #define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
1455 #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
1456 #define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
1457 #define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
1458 #define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
1459
1460 #define ADC_SMPR1_SMP4_Pos (12U)
1461 #define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
1462 #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
1463 #define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
1464 #define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
1465 #define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
1466
1467 #define ADC_SMPR1_SMP5_Pos (15U)
1468 #define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
1469 #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
1470 #define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
1471 #define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
1472 #define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
1473
1474 #define ADC_SMPR1_SMP6_Pos (18U)
1475 #define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
1476 #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
1477 #define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
1478 #define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
1479 #define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
1480
1481 #define ADC_SMPR1_SMP7_Pos (21U)
1482 #define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
1483 #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
1484 #define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
1485 #define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
1486 #define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
1487
1488 #define ADC_SMPR1_SMP8_Pos (24U)
1489 #define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
1490 #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
1491 #define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
1492 #define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
1493 #define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
1494
1495 #define ADC_SMPR1_SMP9_Pos (27U)
1496 #define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
1497 #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
1498 #define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
1499 #define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
1500 #define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
1501
1502 #define ADC_SMPR1_SMPPLUS_Pos (31U)
1503 #define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */
1504 #define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */
1505
1506 /******************** Bit definition for ADC_SMPR2 register *****************/
1507 #define ADC_SMPR2_SMP10_Pos (0U)
1508 #define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
1509 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
1510 #define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
1511 #define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
1512 #define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
1513
1514 #define ADC_SMPR2_SMP11_Pos (3U)
1515 #define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
1516 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
1517 #define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
1518 #define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
1519 #define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
1520
1521 #define ADC_SMPR2_SMP12_Pos (6U)
1522 #define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
1523 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
1524 #define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
1525 #define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
1526 #define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
1527
1528 #define ADC_SMPR2_SMP13_Pos (9U)
1529 #define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
1530 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
1531 #define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
1532 #define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
1533 #define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
1534
1535 #define ADC_SMPR2_SMP14_Pos (12U)
1536 #define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
1537 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
1538 #define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
1539 #define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
1540 #define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
1541
1542 #define ADC_SMPR2_SMP15_Pos (15U)
1543 #define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
1544 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
1545 #define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
1546 #define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
1547 #define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
1548
1549 #define ADC_SMPR2_SMP16_Pos (18U)
1550 #define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
1551 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
1552 #define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
1553 #define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
1554 #define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
1555
1556 #define ADC_SMPR2_SMP17_Pos (21U)
1557 #define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
1558 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
1559 #define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
1560 #define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
1561 #define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
1562
1563 #define ADC_SMPR2_SMP18_Pos (24U)
1564 #define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
1565 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
1566 #define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
1567 #define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
1568 #define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
1569
1570 /******************** Bit definition for ADC_TR1 register *******************/
1571 #define ADC_TR1_LT1_Pos (0U)
1572 #define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
1573 #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
1574
1575 #define ADC_TR1_AWDFILT_Pos (12U)
1576 #define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */
1577 #define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */
1578 #define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */
1579 #define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */
1580 #define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */
1581
1582 #define ADC_TR1_HT1_Pos (16U)
1583 #define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
1584 #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */
1585
1586 /******************** Bit definition for ADC_TR2 register *******************/
1587 #define ADC_TR2_LT2_Pos (0U)
1588 #define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
1589 #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
1590
1591 #define ADC_TR2_HT2_Pos (16U)
1592 #define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
1593 #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
1594
1595 /******************** Bit definition for ADC_TR3 register *******************/
1596 #define ADC_TR3_LT3_Pos (0U)
1597 #define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
1598 #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
1599
1600 #define ADC_TR3_HT3_Pos (16U)
1601 #define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
1602 #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
1603
1604 /******************** Bit definition for ADC_SQR1 register ******************/
1605 #define ADC_SQR1_L_Pos (0U)
1606 #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
1607 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
1608 #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
1609 #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
1610 #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
1611 #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */
1612
1613 #define ADC_SQR1_SQ1_Pos (6U)
1614 #define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
1615 #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
1616 #define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
1617 #define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
1618 #define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
1619 #define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
1620 #define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
1621
1622 #define ADC_SQR1_SQ2_Pos (12U)
1623 #define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
1624 #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
1625 #define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
1626 #define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
1627 #define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
1628 #define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
1629 #define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
1630
1631 #define ADC_SQR1_SQ3_Pos (18U)
1632 #define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
1633 #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
1634 #define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
1635 #define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
1636 #define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
1637 #define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
1638 #define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
1639
1640 #define ADC_SQR1_SQ4_Pos (24U)
1641 #define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
1642 #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
1643 #define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
1644 #define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
1645 #define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
1646 #define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
1647 #define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
1648
1649 /******************** Bit definition for ADC_SQR2 register ******************/
1650 #define ADC_SQR2_SQ5_Pos (0U)
1651 #define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
1652 #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
1653 #define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
1654 #define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
1655 #define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
1656 #define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
1657 #define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
1658
1659 #define ADC_SQR2_SQ6_Pos (6U)
1660 #define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
1661 #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
1662 #define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
1663 #define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
1664 #define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
1665 #define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
1666 #define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
1667
1668 #define ADC_SQR2_SQ7_Pos (12U)
1669 #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
1670 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
1671 #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
1672 #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
1673 #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
1674 #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
1675 #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
1676
1677 #define ADC_SQR2_SQ8_Pos (18U)
1678 #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
1679 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
1680 #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
1681 #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
1682 #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
1683 #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
1684 #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
1685
1686 #define ADC_SQR2_SQ9_Pos (24U)
1687 #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
1688 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
1689 #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
1690 #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
1691 #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
1692 #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
1693 #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
1694
1695 /******************** Bit definition for ADC_SQR3 register ******************/
1696 #define ADC_SQR3_SQ10_Pos (0U)
1697 #define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
1698 #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
1699 #define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
1700 #define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
1701 #define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
1702 #define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
1703 #define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
1704
1705 #define ADC_SQR3_SQ11_Pos (6U)
1706 #define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
1707 #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
1708 #define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
1709 #define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
1710 #define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
1711 #define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
1712 #define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
1713
1714 #define ADC_SQR3_SQ12_Pos (12U)
1715 #define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
1716 #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
1717 #define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
1718 #define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
1719 #define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
1720 #define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
1721 #define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
1722
1723 #define ADC_SQR3_SQ13_Pos (18U)
1724 #define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
1725 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
1726 #define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
1727 #define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
1728 #define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
1729 #define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
1730 #define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
1731
1732 #define ADC_SQR3_SQ14_Pos (24U)
1733 #define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
1734 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
1735 #define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
1736 #define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
1737 #define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
1738 #define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
1739 #define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
1740
1741 /******************** Bit definition for ADC_SQR4 register ******************/
1742 #define ADC_SQR4_SQ15_Pos (0U)
1743 #define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
1744 #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
1745 #define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
1746 #define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
1747 #define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
1748 #define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
1749 #define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
1750
1751 #define ADC_SQR4_SQ16_Pos (6U)
1752 #define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
1753 #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
1754 #define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
1755 #define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
1756 #define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
1757 #define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
1758 #define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
1759
1760 /******************** Bit definition for ADC_DR register ********************/
1761 #define ADC_DR_RDATA_Pos (0U)
1762 #define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
1763 #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
1764
1765 /******************** Bit definition for ADC_JSQR register ******************/
1766 #define ADC_JSQR_JL_Pos (0U)
1767 #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
1768 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
1769 #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
1770 #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
1771
1772 #define ADC_JSQR_JEXTSEL_Pos (2U)
1773 #define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
1774 #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
1775 #define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
1776 #define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
1777 #define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
1778 #define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
1779 #define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
1780
1781 #define ADC_JSQR_JEXTEN_Pos (7U)
1782 #define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
1783 #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
1784 #define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
1785 #define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
1786
1787 #define ADC_JSQR_JSQ1_Pos (9U)
1788 #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
1789 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
1790 #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
1791 #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
1792 #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
1793 #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
1794 #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
1795
1796 #define ADC_JSQR_JSQ2_Pos (15U)
1797 #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
1798 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
1799 #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
1800 #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
1801 #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
1802 #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
1803 #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
1804
1805 #define ADC_JSQR_JSQ3_Pos (21U)
1806 #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
1807 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
1808 #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
1809 #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
1810 #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
1811 #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
1812 #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
1813
1814 #define ADC_JSQR_JSQ4_Pos (27U)
1815 #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
1816 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
1817 #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
1818 #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
1819 #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
1820 #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
1821 #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
1822
1823 /******************** Bit definition for ADC_OFR1 register ******************/
1824 #define ADC_OFR1_OFFSET1_Pos (0U)
1825 #define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
1826 #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
1827
1828 #define ADC_OFR1_OFFSETPOS_Pos (24U)
1829 #define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */
1830 #define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */
1831 #define ADC_OFR1_SATEN_Pos (25U)
1832 #define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */
1833 #define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */
1834
1835 #define ADC_OFR1_OFFSET1_CH_Pos (26U)
1836 #define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
1837 #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
1838 #define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
1839 #define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
1840 #define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
1841 #define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
1842 #define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
1843
1844 #define ADC_OFR1_OFFSET1_EN_Pos (31U)
1845 #define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
1846 #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
1847
1848 /******************** Bit definition for ADC_OFR2 register ******************/
1849 #define ADC_OFR2_OFFSET2_Pos (0U)
1850 #define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
1851 #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
1852
1853 #define ADC_OFR2_OFFSETPOS_Pos (24U)
1854 #define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */
1855 #define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */
1856 #define ADC_OFR2_SATEN_Pos (25U)
1857 #define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */
1858 #define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */
1859
1860 #define ADC_OFR2_OFFSET2_CH_Pos (26U)
1861 #define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
1862 #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
1863 #define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
1864 #define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
1865 #define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
1866 #define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
1867 #define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
1868
1869 #define ADC_OFR2_OFFSET2_EN_Pos (31U)
1870 #define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
1871 #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
1872
1873 /******************** Bit definition for ADC_OFR3 register ******************/
1874 #define ADC_OFR3_OFFSET3_Pos (0U)
1875 #define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
1876 #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
1877
1878 #define ADC_OFR3_OFFSETPOS_Pos (24U)
1879 #define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */
1880 #define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */
1881 #define ADC_OFR3_SATEN_Pos (25U)
1882 #define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */
1883 #define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */
1884
1885 #define ADC_OFR3_OFFSET3_CH_Pos (26U)
1886 #define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
1887 #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
1888 #define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
1889 #define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
1890 #define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
1891 #define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
1892 #define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
1893
1894 #define ADC_OFR3_OFFSET3_EN_Pos (31U)
1895 #define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
1896 #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
1897
1898 /******************** Bit definition for ADC_OFR4 register ******************/
1899 #define ADC_OFR4_OFFSET4_Pos (0U)
1900 #define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
1901 #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
1902
1903 #define ADC_OFR4_OFFSETPOS_Pos (24U)
1904 #define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */
1905 #define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */
1906 #define ADC_OFR4_SATEN_Pos (25U)
1907 #define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */
1908 #define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */
1909
1910 #define ADC_OFR4_OFFSET4_CH_Pos (26U)
1911 #define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
1912 #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
1913 #define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
1914 #define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
1915 #define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
1916 #define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
1917 #define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
1918
1919 #define ADC_OFR4_OFFSET4_EN_Pos (31U)
1920 #define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
1921 #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
1922
1923 /******************** Bit definition for ADC_JDR1 register ******************/
1924 #define ADC_JDR1_JDATA_Pos (0U)
1925 #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
1926 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
1927
1928 /******************** Bit definition for ADC_JDR2 register ******************/
1929 #define ADC_JDR2_JDATA_Pos (0U)
1930 #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
1931 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
1932
1933 /******************** Bit definition for ADC_JDR3 register ******************/
1934 #define ADC_JDR3_JDATA_Pos (0U)
1935 #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
1936 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
1937
1938 /******************** Bit definition for ADC_JDR4 register ******************/
1939 #define ADC_JDR4_JDATA_Pos (0U)
1940 #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
1941 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
1942
1943 /******************** Bit definition for ADC_AWD2CR register ****************/
1944 #define ADC_AWD2CR_AWD2CH_Pos (0U)
1945 #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
1946 #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
1947 #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
1948 #define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
1949 #define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
1950 #define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
1951 #define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
1952 #define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
1953 #define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
1954 #define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
1955 #define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
1956 #define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
1957 #define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
1958 #define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
1959 #define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
1960 #define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
1961 #define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
1962 #define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
1963 #define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
1964 #define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
1965 #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
1966
1967 /******************** Bit definition for ADC_AWD3CR register ****************/
1968 #define ADC_AWD3CR_AWD3CH_Pos (0U)
1969 #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
1970 #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
1971 #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
1972 #define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
1973 #define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
1974 #define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
1975 #define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
1976 #define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
1977 #define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
1978 #define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
1979 #define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
1980 #define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
1981 #define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
1982 #define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
1983 #define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
1984 #define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
1985 #define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
1986 #define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
1987 #define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
1988 #define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
1989 #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
1990
1991 /******************** Bit definition for ADC_DIFSEL register ****************/
1992 #define ADC_DIFSEL_DIFSEL_Pos (0U)
1993 #define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
1994 #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
1995 #define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
1996 #define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
1997 #define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
1998 #define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
1999 #define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
2000 #define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
2001 #define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
2002 #define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
2003 #define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
2004 #define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
2005 #define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
2006 #define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
2007 #define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
2008 #define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
2009 #define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
2010 #define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
2011 #define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
2012 #define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
2013 #define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
2014
2015 /******************** Bit definition for ADC_CALFACT register ***************/
2016 #define ADC_CALFACT_CALFACT_S_Pos (0U)
2017 #define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
2018 #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
2019 #define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
2020 #define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
2021 #define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
2022 #define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
2023 #define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
2024 #define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
2025 #define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */
2026
2027 #define ADC_CALFACT_CALFACT_D_Pos (16U)
2028 #define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
2029 #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
2030 #define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
2031 #define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
2032 #define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
2033 #define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
2034 #define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
2035 #define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
2036 #define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */
2037
2038 /******************** Bit definition for ADC_GCOMP register *****************/
2039 #define ADC_GCOMP_GCOMPCOEFF_Pos (0U)
2040 #define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */
2041 #define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Gain Compensation Coefficient */
2042
2043 /************************* ADC Common registers *****************************/
2044 /******************** Bit definition for ADC_CSR register *******************/
2045 #define ADC_CSR_ADRDY_MST_Pos (0U)
2046 #define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
2047 #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */
2048 #define ADC_CSR_EOSMP_MST_Pos (1U)
2049 #define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
2050 #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */
2051 #define ADC_CSR_EOC_MST_Pos (2U)
2052 #define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
2053 #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */
2054 #define ADC_CSR_EOS_MST_Pos (3U)
2055 #define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
2056 #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */
2057 #define ADC_CSR_OVR_MST_Pos (4U)
2058 #define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
2059 #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */
2060 #define ADC_CSR_JEOC_MST_Pos (5U)
2061 #define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
2062 #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */
2063 #define ADC_CSR_JEOS_MST_Pos (6U)
2064 #define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
2065 #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */
2066 #define ADC_CSR_AWD1_MST_Pos (7U)
2067 #define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
2068 #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */
2069 #define ADC_CSR_AWD2_MST_Pos (8U)
2070 #define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
2071 #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */
2072 #define ADC_CSR_AWD3_MST_Pos (9U)
2073 #define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
2074 #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */
2075 #define ADC_CSR_JQOVF_MST_Pos (10U)
2076 #define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
2077 #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */
2078
2079 #define ADC_CSR_ADRDY_SLV_Pos (16U)
2080 #define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
2081 #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */
2082 #define ADC_CSR_EOSMP_SLV_Pos (17U)
2083 #define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
2084 #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */
2085 #define ADC_CSR_EOC_SLV_Pos (18U)
2086 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
2087 #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */
2088 #define ADC_CSR_EOS_SLV_Pos (19U)
2089 #define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
2090 #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */
2091 #define ADC_CSR_OVR_SLV_Pos (20U)
2092 #define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
2093 #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */
2094 #define ADC_CSR_JEOC_SLV_Pos (21U)
2095 #define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
2096 #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */
2097 #define ADC_CSR_JEOS_SLV_Pos (22U)
2098 #define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
2099 #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */
2100 #define ADC_CSR_AWD1_SLV_Pos (23U)
2101 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
2102 #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */
2103 #define ADC_CSR_AWD2_SLV_Pos (24U)
2104 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
2105 #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */
2106 #define ADC_CSR_AWD3_SLV_Pos (25U)
2107 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
2108 #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */
2109 #define ADC_CSR_JQOVF_SLV_Pos (26U)
2110 #define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
2111 #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */
2112
2113 /******************** Bit definition for ADC_CCR register *******************/
2114 #define ADC_CCR_DUAL_Pos (0U)
2115 #define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
2116 #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */
2117 #define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
2118 #define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
2119 #define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
2120 #define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
2121 #define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
2122
2123 #define ADC_CCR_DELAY_Pos (8U)
2124 #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
2125 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */
2126 #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
2127 #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
2128 #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
2129 #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
2130
2131 #define ADC_CCR_DMACFG_Pos (13U)
2132 #define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */
2133 #define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */
2134
2135 #define ADC_CCR_MDMA_Pos (14U)
2136 #define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */
2137 #define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */
2138 #define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */
2139 #define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */
2140
2141 #define ADC_CCR_CKMODE_Pos (16U)
2142 #define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
2143 #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
2144 #define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
2145 #define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
2146
2147 #define ADC_CCR_PRESC_Pos (18U)
2148 #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
2149 #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
2150 #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
2151 #define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
2152 #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
2153 #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
2154
2155 #define ADC_CCR_VREFEN_Pos (22U)
2156 #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
2157 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
2158 #define ADC_CCR_VSENSESEL_Pos (23U)
2159 #define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos) /*!< 0x00800000 */
2160 #define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk /*!< ADC internal path to temperature sensor enable */
2161 #define ADC_CCR_VBATSEL_Pos (24U)
2162 #define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos) /*!< 0x01000000 */
2163 #define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk /*!< ADC internal path to battery voltage enable */
2164
2165 /******************** Bit definition for ADC_CDR register *******************/
2166 #define ADC_CDR_RDATA_MST_Pos (0U)
2167 #define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
2168 #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
2169
2170 #define ADC_CDR_RDATA_SLV_Pos (16U)
2171 #define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
2172 #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
2173
2174
2175 /******************************************************************************/
2176 /* */
2177 /* Analog Comparators (COMP) */
2178 /* */
2179 /******************************************************************************/
2180 /********************** Bit definition for COMP_CSR register ****************/
2181 #define COMP_CSR_EN_Pos (0U)
2182 #define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */
2183 #define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */
2184
2185 #define COMP_CSR_DEGLITCHEN_Pos (1U)
2186 #define COMP_CSR_DEGLITCHEN_Msk (0x1UL << COMP_CSR_DEGLITCHEN_Pos) /*!< 0x00000002 */
2187 #define COMP_CSR_DEGLITCHEN COMP_CSR_DEGLITCHEN_Msk /*!< Comparator deglitcher enable */
2188
2189 #define COMP_CSR_INMSEL_Pos (4U)
2190 #define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */
2191 #define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */
2192 #define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */
2193 #define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */
2194 #define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */
2195 #define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */
2196
2197 #define COMP_CSR_INPSEL_Pos (8U)
2198 #define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */
2199 #define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */
2200
2201 #define COMP_CSR_POLARITY_Pos (15U)
2202 #define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */
2203 #define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */
2204
2205 #define COMP_CSR_HYST_Pos (16U)
2206 #define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos) /*!< 0x00070000 */
2207 #define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */
2208 #define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */
2209 #define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */
2210 #define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos) /*!< 0x00040000 */
2211
2212 #define COMP_CSR_BLANKING_Pos (19U)
2213 #define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */
2214 #define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */
2215 #define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
2216 #define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
2217 #define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */
2218
2219 #define COMP_CSR_BRGEN_Pos (22U)
2220 #define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */
2221 #define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */
2222
2223 #define COMP_CSR_SCALEN_Pos (23U)
2224 #define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */
2225 #define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */
2226
2227 #define COMP_CSR_VALUE_Pos (30U)
2228 #define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
2229 #define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */
2230
2231 #define COMP_CSR_LOCK_Pos (31U)
2232 #define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */
2233 #define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */
2234
2235 /******************************************************************************/
2236 /* */
2237 /* CORDIC calculation unit */
2238 /* */
2239 /******************************************************************************/
2240 /******************* Bit definition for CORDIC_CSR register *****************/
2241 #define CORDIC_CSR_FUNC_Pos (0U)
2242 #define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */
2243 #define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */
2244 #define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */
2245 #define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */
2246 #define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */
2247 #define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */
2248 #define CORDIC_CSR_PRECISION_Pos (4U)
2249 #define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */
2250 #define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */
2251 #define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */
2252 #define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */
2253 #define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */
2254 #define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */
2255 #define CORDIC_CSR_SCALE_Pos (8U)
2256 #define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */
2257 #define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */
2258 #define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */
2259 #define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */
2260 #define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */
2261 #define CORDIC_CSR_IEN_Pos (16U)
2262 #define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */
2263 #define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */
2264 #define CORDIC_CSR_DMAREN_Pos (17U)
2265 #define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */
2266 #define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */
2267 #define CORDIC_CSR_DMAWEN_Pos (18U)
2268 #define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */
2269 #define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */
2270 #define CORDIC_CSR_NRES_Pos (19U)
2271 #define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */
2272 #define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */
2273 #define CORDIC_CSR_NARGS_Pos (20U)
2274 #define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */
2275 #define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */
2276 #define CORDIC_CSR_RESSIZE_Pos (21U)
2277 #define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */
2278 #define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */
2279 #define CORDIC_CSR_ARGSIZE_Pos (22U)
2280 #define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */
2281 #define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */
2282 #define CORDIC_CSR_RRDY_Pos (31U)
2283 #define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */
2284 #define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */
2285
2286 /******************* Bit definition for CORDIC_WDATA register ***************/
2287 #define CORDIC_WDATA_ARG_Pos (0U)
2288 #define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */
2289 #define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */
2290
2291 /******************* Bit definition for CORDIC_RDATA register ***************/
2292 #define CORDIC_RDATA_RES_Pos (0U)
2293 #define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */
2294 #define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */
2295
2296
2297 /******************************************************************************/
2298 /* */
2299 /* CRC calculation unit */
2300 /* */
2301 /******************************************************************************/
2302 /******************* Bit definition for CRC_DR register *********************/
2303 #define CRC_DR_DR_Pos (0U)
2304 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
2305 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
2306
2307 /******************* Bit definition for CRC_IDR register ********************/
2308 #define CRC_IDR_IDR_Pos (0U)
2309 #define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
2310 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */
2311
2312 /******************** Bit definition for CRC_CR register ********************/
2313 #define CRC_CR_RESET_Pos (0U)
2314 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
2315 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
2316 #define CRC_CR_POLYSIZE_Pos (3U)
2317 #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
2318 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
2319 #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
2320 #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
2321 #define CRC_CR_REV_IN_Pos (5U)
2322 #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
2323 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
2324 #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
2325 #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
2326 #define CRC_CR_REV_OUT_Pos (7U)
2327 #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
2328 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
2329
2330 /******************* Bit definition for CRC_INIT register *******************/
2331 #define CRC_INIT_INIT_Pos (0U)
2332 #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
2333 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
2334
2335 /******************* Bit definition for CRC_POL register ********************/
2336 #define CRC_POL_POL_Pos (0U)
2337 #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
2338 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
2339
2340 /******************************************************************************/
2341 /* */
2342 /* CRS Clock Recovery System */
2343 /******************************************************************************/
2344
2345 /******************* Bit definition for CRS_CR register *********************/
2346 #define CRS_CR_SYNCOKIE_Pos (0U)
2347 #define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
2348 #define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
2349 #define CRS_CR_SYNCWARNIE_Pos (1U)
2350 #define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
2351 #define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
2352 #define CRS_CR_ERRIE_Pos (2U)
2353 #define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
2354 #define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
2355 #define CRS_CR_ESYNCIE_Pos (3U)
2356 #define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
2357 #define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
2358 #define CRS_CR_CEN_Pos (5U)
2359 #define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */
2360 #define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
2361 #define CRS_CR_AUTOTRIMEN_Pos (6U)
2362 #define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
2363 #define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
2364 #define CRS_CR_SWSYNC_Pos (7U)
2365 #define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
2366 #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
2367 #define CRS_CR_TRIM_Pos (8U)
2368 #define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */
2369 #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
2370
2371 /******************* Bit definition for CRS_CFGR register *********************/
2372 #define CRS_CFGR_RELOAD_Pos (0U)
2373 #define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
2374 #define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
2375 #define CRS_CFGR_FELIM_Pos (16U)
2376 #define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
2377 #define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
2378
2379 #define CRS_CFGR_SYNCDIV_Pos (24U)
2380 #define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
2381 #define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
2382 #define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
2383 #define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
2384 #define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
2385
2386 #define CRS_CFGR_SYNCSRC_Pos (28U)
2387 #define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
2388 #define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
2389 #define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
2390 #define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
2391
2392 #define CRS_CFGR_SYNCPOL_Pos (31U)
2393 #define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
2394 #define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
2395
2396 /******************* Bit definition for CRS_ISR register *********************/
2397 #define CRS_ISR_SYNCOKF_Pos (0U)
2398 #define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
2399 #define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
2400 #define CRS_ISR_SYNCWARNF_Pos (1U)
2401 #define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
2402 #define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
2403 #define CRS_ISR_ERRF_Pos (2U)
2404 #define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
2405 #define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
2406 #define CRS_ISR_ESYNCF_Pos (3U)
2407 #define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
2408 #define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
2409 #define CRS_ISR_SYNCERR_Pos (8U)
2410 #define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
2411 #define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
2412 #define CRS_ISR_SYNCMISS_Pos (9U)
2413 #define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
2414 #define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
2415 #define CRS_ISR_TRIMOVF_Pos (10U)
2416 #define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
2417 #define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
2418 #define CRS_ISR_FEDIR_Pos (15U)
2419 #define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
2420 #define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
2421 #define CRS_ISR_FECAP_Pos (16U)
2422 #define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
2423 #define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
2424
2425 /******************* Bit definition for CRS_ICR register *********************/
2426 #define CRS_ICR_SYNCOKC_Pos (0U)
2427 #define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
2428 #define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
2429 #define CRS_ICR_SYNCWARNC_Pos (1U)
2430 #define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
2431 #define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
2432 #define CRS_ICR_ERRC_Pos (2U)
2433 #define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
2434 #define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
2435 #define CRS_ICR_ESYNCC_Pos (3U)
2436 #define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
2437 #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
2438
2439 /******************************************************************************/
2440 /* */
2441 /* Digital to Analog Converter */
2442 /* */
2443 /******************************************************************************/
2444 /*
2445 * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
2446 */
2447 #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
2448
2449 /******************** Bit definition for DAC_CR register ********************/
2450 #define DAC_CR_EN1_Pos (0U)
2451 #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
2452 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
2453 #define DAC_CR_TEN1_Pos (1U)
2454 #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */
2455 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
2456
2457 #define DAC_CR_TSEL1_Pos (2U)
2458 #define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */
2459 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
2460 #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */
2461 #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
2462 #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
2463 #define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
2464
2465 #define DAC_CR_WAVE1_Pos (6U)
2466 #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
2467 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
2468 #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
2469 #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
2470
2471 #define DAC_CR_MAMP1_Pos (8U)
2472 #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
2473 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
2474 #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
2475 #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
2476 #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
2477 #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
2478
2479 #define DAC_CR_DMAEN1_Pos (12U)
2480 #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
2481 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
2482 #define DAC_CR_DMAUDRIE1_Pos (13U)
2483 #define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
2484 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
2485 #define DAC_CR_CEN1_Pos (14U)
2486 #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
2487 #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
2488
2489 #define DAC_CR_HFSEL_Pos (15U)
2490 #define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */
2491 #define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!<DAC channel 1 and 2 high frequency mode enable >*/
2492
2493 #define DAC_CR_EN2_Pos (16U)
2494 #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
2495 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
2496 #define DAC_CR_TEN2_Pos (17U)
2497 #define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00020000 */
2498 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
2499
2500 #define DAC_CR_TSEL2_Pos (18U)
2501 #define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */
2502 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[3:0] (DAC channel2 Trigger selection) */
2503 #define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */
2504 #define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
2505 #define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
2506 #define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
2507
2508 #define DAC_CR_WAVE2_Pos (22U)
2509 #define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
2510 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
2511 #define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
2512 #define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
2513
2514 #define DAC_CR_MAMP2_Pos (24U)
2515 #define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
2516 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
2517 #define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
2518 #define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
2519 #define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
2520 #define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
2521
2522 #define DAC_CR_DMAEN2_Pos (28U)
2523 #define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
2524 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
2525 #define DAC_CR_DMAUDRIE2_Pos (29U)
2526 #define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
2527 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
2528 #define DAC_CR_CEN2_Pos (30U)
2529 #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
2530 #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
2531
2532 /***************** Bit definition for DAC_SWTRIGR register ******************/
2533 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
2534 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
2535 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
2536 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
2537 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
2538 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
2539 #define DAC_SWTRIGR_SWTRIGB1_Pos (16U)
2540 #define DAC_SWTRIGR_SWTRIGB1_Msk (0x1UL << DAC_SWTRIGR_SWTRIGB1_Pos) /*!< 0x00010000 */
2541 #define DAC_SWTRIGR_SWTRIGB1 DAC_SWTRIGR_SWTRIGB1_Msk /*!<DAC channel1 software trigger B */
2542 #define DAC_SWTRIGR_SWTRIGB2_Pos (17U)
2543 #define DAC_SWTRIGR_SWTRIGB2_Msk (0x1UL << DAC_SWTRIGR_SWTRIGB2_Pos) /*!< 0x00020000 */
2544 #define DAC_SWTRIGR_SWTRIGB2 DAC_SWTRIGR_SWTRIGB2_Msk /*!<DAC channel2 software trigger B */
2545
2546 /***************** Bit definition for DAC_DHR12R1 register ******************/
2547 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
2548 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
2549 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
2550 #define DAC_DHR12R1_DACC1DHRB_Pos (16U)
2551 #define DAC_DHR12R1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x0FFF0000 */
2552 #define DAC_DHR12R1_DACC1DHRB DAC_DHR12R1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Right-aligned data B */
2553
2554 /***************** Bit definition for DAC_DHR12L1 register ******************/
2555 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
2556 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
2557 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
2558 #define DAC_DHR12L1_DACC1DHRB_Pos (20U)
2559 #define DAC_DHR12L1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0xFFF00000 */
2560 #define DAC_DHR12L1_DACC1DHRB DAC_DHR12L1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Left aligned data B */
2561
2562 /****************** Bit definition for DAC_DHR8R1 register ******************/
2563 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
2564 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
2565 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
2566 #define DAC_DHR8R1_DACC1DHRB_Pos (8U)
2567 #define DAC_DHR8R1_DACC1DHRB_Msk (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x0000FF00 */
2568 #define DAC_DHR8R1_DACC1DHRB DAC_DHR8R1_DACC1DHRB_Msk /*!<DAC channel1 8-bit Right aligned data B */
2569
2570 /***************** Bit definition for DAC_DHR12R2 register ******************/
2571 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
2572 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
2573 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
2574 #define DAC_DHR12R2_DACC2DHRB_Pos (16U)
2575 #define DAC_DHR12R2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHRB_Pos) /*!< 0x0FFF0000 */
2576 #define DAC_DHR12R2_DACC2DHRB DAC_DHR12R2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Right-aligned data B */
2577
2578 /***************** Bit definition for DAC_DHR12L2 register ******************/
2579 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
2580 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
2581 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
2582 #define DAC_DHR12L2_DACC2DHRB_Pos (20U)
2583 #define DAC_DHR12L2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHRB_Pos) /*!< 0xFFF00000 */
2584 #define DAC_DHR12L2_DACC2DHRB DAC_DHR12L2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Left aligned data B */
2585
2586 /****************** Bit definition for DAC_DHR8R2 register ******************/
2587 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
2588 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
2589 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
2590 #define DAC_DHR8R2_DACC2DHRB_Pos (8U)
2591 #define DAC_DHR8R2_DACC2DHRB_Msk (0xFFUL << DAC_DHR8R2_DACC2DHRB_Pos) /*!< 0x0000FF00 */
2592 #define DAC_DHR8R2_DACC2DHRB DAC_DHR8R2_DACC2DHRB_Msk /*!<DAC channel2 8-bit Right aligned data B */
2593
2594 /***************** Bit definition for DAC_DHR12RD register ******************/
2595 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
2596 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
2597 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
2598 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
2599 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
2600 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
2601
2602 /***************** Bit definition for DAC_DHR12LD register ******************/
2603 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
2604 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
2605 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
2606 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
2607 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
2608 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
2609
2610 /****************** Bit definition for DAC_DHR8RD register ******************/
2611 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
2612 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
2613 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
2614 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
2615 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
2616 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
2617
2618 /******************* Bit definition for DAC_DOR1 register *******************/
2619 #define DAC_DOR1_DACC1DOR_Pos (0U)
2620 #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
2621 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
2622 #define DAC_DOR1_DACC1DORB_Pos (16U)
2623 #define DAC_DOR1_DACC1DORB_Msk (0xFFFUL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x0FFF0000 */
2624 #define DAC_DOR1_DACC1DORB DAC_DOR1_DACC1DORB_Msk /*!<DAC channel1 data output B */
2625
2626 /******************* Bit definition for DAC_DOR2 register *******************/
2627 #define DAC_DOR2_DACC2DOR_Pos (0U)
2628 #define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
2629 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
2630 #define DAC_DOR2_DACC2DORB_Pos (16U)
2631 #define DAC_DOR2_DACC2DORB_Msk (0xFFFUL << DAC_DOR2_DACC2DORB_Pos) /*!< 0x0FFF0000 */
2632 #define DAC_DOR2_DACC2DORB DAC_DOR2_DACC2DORB_Msk /*!<DAC channel2 data output B */
2633
2634 /******************** Bit definition for DAC_SR register ********************/
2635 #define DAC_SR_DAC1RDY_Pos (11U)
2636 #define DAC_SR_DAC1RDY_Msk (0x1UL << DAC_SR_DAC1RDY_Pos) /*!< 0x00000800 */
2637 #define DAC_SR_DAC1RDY DAC_SR_DAC1RDY_Msk /*!<DAC channel 1 ready status bit */
2638 #define DAC_SR_DORSTAT1_Pos (12U)
2639 #define DAC_SR_DORSTAT1_Msk (0x1UL << DAC_SR_DORSTAT1_Pos) /*!< 0x00001000 */
2640 #define DAC_SR_DORSTAT1 DAC_SR_DORSTAT1_Msk /*!<DAC channel 1 output register status bit */
2641 #define DAC_SR_DMAUDR1_Pos (13U)
2642 #define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
2643 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
2644 #define DAC_SR_CAL_FLAG1_Pos (14U)
2645 #define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
2646 #define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
2647 #define DAC_SR_BWST1_Pos (15U)
2648 #define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */
2649 #define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
2650
2651
2652 #define DAC_SR_DAC2RDY_Pos (27U)
2653 #define DAC_SR_DAC2RDY_Msk (0x1UL << DAC_SR_DAC2RDY_Pos) /*!< 0x08000000 */
2654 #define DAC_SR_DAC2RDY DAC_SR_DAC2RDY_Msk /*!<DAC channel 2 ready status bit */
2655 #define DAC_SR_DORSTAT2_Pos (28U)
2656 #define DAC_SR_DORSTAT2_Msk (0x1UL << DAC_SR_DORSTAT2_Pos) /*!< 0x10000000 */
2657 #define DAC_SR_DORSTAT2 DAC_SR_DORSTAT2_Msk /*!<DAC channel 2 output register status bit */
2658 #define DAC_SR_DMAUDR2_Pos (29U)
2659 #define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
2660 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
2661 #define DAC_SR_CAL_FLAG2_Pos (30U)
2662 #define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
2663 #define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
2664 #define DAC_SR_BWST2_Pos (31U)
2665 #define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
2666 #define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
2667
2668 /******************* Bit definition for DAC_CCR register ********************/
2669 #define DAC_CCR_OTRIM1_Pos (0U)
2670 #define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
2671 #define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
2672 #define DAC_CCR_OTRIM2_Pos (16U)
2673 #define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
2674 #define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
2675
2676 /******************* Bit definition for DAC_MCR register *******************/
2677 #define DAC_MCR_MODE1_Pos (0U)
2678 #define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
2679 #define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
2680 #define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
2681 #define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
2682 #define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
2683
2684 #define DAC_MCR_DMADOUBLE1_Pos (8U)
2685 #define DAC_MCR_DMADOUBLE1_Msk (0x1UL << DAC_MCR_DMADOUBLE1_Pos) /*!< 0x00000100 */
2686 #define DAC_MCR_DMADOUBLE1 DAC_MCR_DMADOUBLE1_Msk /*!<DAC Channel 1 DMA double data mode */
2687
2688 #define DAC_MCR_SINFORMAT1_Pos (9U)
2689 #define DAC_MCR_SINFORMAT1_Msk (0x1UL << DAC_MCR_SINFORMAT1_Pos) /*!< 0x00000200 */
2690 #define DAC_MCR_SINFORMAT1 DAC_MCR_SINFORMAT1_Msk /*!<DAC Channel 1 enable signed format */
2691
2692 #define DAC_MCR_HFSEL_Pos (14U)
2693 #define DAC_MCR_HFSEL_Msk (0x3UL << DAC_MCR_HFSEL_Pos) /*!< 0x0000C000 */
2694 #define DAC_MCR_HFSEL DAC_MCR_HFSEL_Msk /*!<HFSEL[1:0] (High Frequency interface mode selection) */
2695 #define DAC_MCR_HFSEL_0 (0x1UL << DAC_MCR_HFSEL_Pos) /*!< 0x00004000 */
2696 #define DAC_MCR_HFSEL_1 (0x2UL << DAC_MCR_HFSEL_Pos) /*!< 0x00008000 */
2697
2698 #define DAC_MCR_MODE2_Pos (16U)
2699 #define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
2700 #define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
2701 #define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
2702 #define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
2703 #define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
2704
2705 #define DAC_MCR_DMADOUBLE2_Pos (24U)
2706 #define DAC_MCR_DMADOUBLE2_Msk (0x1UL << DAC_MCR_DMADOUBLE2_Pos) /*!< 0x01000000 */
2707 #define DAC_MCR_DMADOUBLE2 DAC_MCR_DMADOUBLE2_Msk /*!<DAC Channel 2 DMA double data mode */
2708
2709 #define DAC_MCR_SINFORMAT2_Pos (25U)
2710 #define DAC_MCR_SINFORMAT2_Msk (0x1UL << DAC_MCR_SINFORMAT2_Pos) /*!< 0x02000000 */
2711 #define DAC_MCR_SINFORMAT2 DAC_MCR_SINFORMAT2_Msk /*!<DAC Channel 2 enable signed format */
2712
2713 /****************** Bit definition for DAC_SHSR1 register ******************/
2714 #define DAC_SHSR1_TSAMPLE1_Pos (0U)
2715 #define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
2716 #define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
2717
2718 /****************** Bit definition for DAC_SHSR2 register ******************/
2719 #define DAC_SHSR2_TSAMPLE2_Pos (0U)
2720 #define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
2721 #define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
2722
2723 /****************** Bit definition for DAC_SHHR register ******************/
2724 #define DAC_SHHR_THOLD1_Pos (0U)
2725 #define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
2726 #define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
2727 #define DAC_SHHR_THOLD2_Pos (16U)
2728 #define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
2729 #define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
2730
2731 /****************** Bit definition for DAC_SHRR register ******************/
2732 #define DAC_SHRR_TREFRESH1_Pos (0U)
2733 #define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
2734 #define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
2735 #define DAC_SHRR_TREFRESH2_Pos (16U)
2736 #define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
2737 #define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
2738
2739 /****************** Bit definition for DAC_STR1 register ******************/
2740 #define DAC_STR1_STRSTDATA1_Pos (0U)
2741 #define DAC_STR1_STRSTDATA1_Msk (0xFFFUL << DAC_STR1_STRSTDATA1_Pos) /*!< 0x00000FFF */
2742 #define DAC_STR1_STRSTDATA1 DAC_STR1_STRSTDATA1_Msk /*!<DAC Channel 1 Sawtooth starting value */
2743 #define DAC_STR1_STDIR1_Pos (12U)
2744 #define DAC_STR1_STDIR1_Msk (0x1UL << DAC_STR1_STDIR1_Pos) /*!< 0x00001000 */
2745 #define DAC_STR1_STDIR1 DAC_STR1_STDIR1_Msk /*!<DAC Channel 1 Sawtooth direction setting */
2746
2747 #define DAC_STR1_STINCDATA1_Pos (16U)
2748 #define DAC_STR1_STINCDATA1_Msk (0xFFFFUL << DAC_STR1_STINCDATA1_Pos) /*!< 0xFFFF0000 */
2749 #define DAC_STR1_STINCDATA1 DAC_STR1_STINCDATA1_Msk /*!<DAC Channel 1 Sawtooth increment value (12.4 bit format) */
2750
2751 /****************** Bit definition for DAC_STR2 register ******************/
2752 #define DAC_STR2_STRSTDATA2_Pos (0U)
2753 #define DAC_STR2_STRSTDATA2_Msk (0xFFFUL << DAC_STR2_STRSTDATA2_Pos) /*!< 0x00000FFF */
2754 #define DAC_STR2_STRSTDATA2 DAC_STR2_STRSTDATA2_Msk /*!<DAC Channel 2 Sawtooth starting value */
2755 #define DAC_STR2_STDIR2_Pos (12U)
2756 #define DAC_STR2_STDIR2_Msk (0x1UL << DAC_STR2_STDIR2_Pos) /*!< 0x00001000 */
2757 #define DAC_STR2_STDIR2 DAC_STR2_STDIR2_Msk /*!<DAC Channel 2 Sawtooth direction setting */
2758
2759 #define DAC_STR2_STINCDATA2_Pos (16U)
2760 #define DAC_STR2_STINCDATA2_Msk (0xFFFFUL << DAC_STR2_STINCDATA2_Pos) /*!< 0xFFFF0000 */
2761 #define DAC_STR2_STINCDATA2 DAC_STR2_STINCDATA2_Msk /*!<DAC Channel 2 Sawtooth increment value (12.4 bit format) */
2762
2763 /****************** Bit definition for DAC_STMODR register ****************/
2764 #define DAC_STMODR_STRSTTRIGSEL1_Pos (0U)
2765 #define DAC_STMODR_STRSTTRIGSEL1_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x0000000F */
2766 #define DAC_STMODR_STRSTTRIGSEL1 DAC_STMODR_STRSTTRIGSEL1_Msk /*!<STRSTTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
2767 #define DAC_STMODR_STRSTTRIGSEL1_0 (0x1UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000001 */
2768 #define DAC_STMODR_STRSTTRIGSEL1_1 (0x2UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000002 */
2769 #define DAC_STMODR_STRSTTRIGSEL1_2 (0x4UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000004 */
2770 #define DAC_STMODR_STRSTTRIGSEL1_3 (0x8UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000008 */
2771
2772 #define DAC_STMODR_STINCTRIGSEL1_Pos (8U)
2773 #define DAC_STMODR_STINCTRIGSEL1_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x0000000F */
2774 #define DAC_STMODR_STINCTRIGSEL1 DAC_STMODR_STINCTRIGSEL1_Msk /*!<STINCTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
2775 #define DAC_STMODR_STINCTRIGSEL1_0 (0x1UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000001 */
2776 #define DAC_STMODR_STINCTRIGSEL1_1 (0x2UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000002 */
2777 #define DAC_STMODR_STINCTRIGSEL1_2 (0x4UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000004 */
2778 #define DAC_STMODR_STINCTRIGSEL1_3 (0x8UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000008 */
2779
2780 #define DAC_STMODR_STRSTTRIGSEL2_Pos (16U)
2781 #define DAC_STMODR_STRSTTRIGSEL2_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x0000000F */
2782 #define DAC_STMODR_STRSTTRIGSEL2 DAC_STMODR_STRSTTRIGSEL2_Msk /*!<STRSTTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
2783 #define DAC_STMODR_STRSTTRIGSEL2_0 (0x1UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000001 */
2784 #define DAC_STMODR_STRSTTRIGSEL2_1 (0x2UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000002 */
2785 #define DAC_STMODR_STRSTTRIGSEL2_2 (0x4UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000004 */
2786 #define DAC_STMODR_STRSTTRIGSEL2_3 (0x8UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000008 */
2787
2788 #define DAC_STMODR_STINCTRIGSEL2_Pos (24U)
2789 #define DAC_STMODR_STINCTRIGSEL2_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x0000000F */
2790 #define DAC_STMODR_STINCTRIGSEL2 DAC_STMODR_STINCTRIGSEL2_Msk /*!<STINCTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
2791 #define DAC_STMODR_STINCTRIGSEL2_0 (0x1UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000001 */
2792 #define DAC_STMODR_STINCTRIGSEL2_1 (0x2UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000002 */
2793 #define DAC_STMODR_STINCTRIGSEL2_2 (0x4UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000004 */
2794 #define DAC_STMODR_STINCTRIGSEL2_3 (0x8UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000008 */
2795
2796 /******************************************************************************/
2797 /* */
2798 /* Debug MCU */
2799 /* */
2800 /******************************************************************************/
2801 /******************** Bit definition for DBGMCU_IDCODE register *************/
2802 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
2803 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)/*!< 0x00000FFF */
2804 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
2805 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
2806 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)/*!< 0xFFFF0000 */
2807 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
2808
2809 /******************** Bit definition for DBGMCU_CR register *****************/
2810 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
2811 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)/*!< 0x00000001 */
2812 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
2813 #define DBGMCU_CR_DBG_STOP_Pos (1U)
2814 #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)/*!< 0x00000002 */
2815 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
2816 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
2817 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)/*!< 0x00000004 */
2818 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
2819 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
2820 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)/*!< 0x00000020 */
2821 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
2822
2823 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
2824 #define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x000000C0 */
2825 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
2826 #define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000040 */
2827 #define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000080 */
2828
2829 /******************** Bit definition for DBGMCU_APB1FZR1 register ***********/
2830 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U)
2831 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)/*!< 0x00000001 */
2832 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
2833 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos (1U)
2834 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos)/*!< 0x00000002 */
2835 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
2836 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U)
2837 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)/*!< 0x00000004 */
2838 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
2839 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U)
2840 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)/*!< 0x00000010 */
2841 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
2842 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U)
2843 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos)/*!< 0x00000020 */
2844 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
2845 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U)
2846 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)/*!< 0x00000400 */
2847 #define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
2848 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U)
2849 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)/*!< 0x00000800 */
2850 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
2851 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U)
2852 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)/*!< 0x00001000 */
2853 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
2854 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U)
2855 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)/*!< 0x00200000 */
2856 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
2857 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos (22U)
2858 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)/*!< 0x00400000 */
2859 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
2860 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (30U)
2861 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos)/*!< 0x40000000 */
2862 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
2863 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)
2864 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)/*!< 0x80000000 */
2865 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
2866
2867 /******************** Bit definition for DBGMCU_APB1FZR2 register **********/
2868
2869 /******************** Bit definition for DBGMCU_APB2FZ register ************/
2870 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
2871 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos)/*!< 0x00000800 */
2872 #define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
2873 #define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U)
2874 #define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos)/*!< 0x00002000 */
2875 #define DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk
2876 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U)
2877 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos)/*!< 0x00010000 */
2878 #define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
2879 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U)
2880 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */
2881 #define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
2882 #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U)
2883 #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */
2884 #define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
2885
2886 /******************************************************************************/
2887 /* */
2888 /* DMA Controller (DMA) */
2889 /* */
2890 /******************************************************************************/
2891
2892 /******************* Bit definition for DMA_ISR register ********************/
2893 #define DMA_ISR_GIF1_Pos (0U)
2894 #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
2895 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
2896 #define DMA_ISR_TCIF1_Pos (1U)
2897 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
2898 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
2899 #define DMA_ISR_HTIF1_Pos (2U)
2900 #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
2901 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
2902 #define DMA_ISR_TEIF1_Pos (3U)
2903 #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
2904 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
2905 #define DMA_ISR_GIF2_Pos (4U)
2906 #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
2907 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
2908 #define DMA_ISR_TCIF2_Pos (5U)
2909 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
2910 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
2911 #define DMA_ISR_HTIF2_Pos (6U)
2912 #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
2913 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
2914 #define DMA_ISR_TEIF2_Pos (7U)
2915 #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
2916 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
2917 #define DMA_ISR_GIF3_Pos (8U)
2918 #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
2919 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
2920 #define DMA_ISR_TCIF3_Pos (9U)
2921 #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
2922 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
2923 #define DMA_ISR_HTIF3_Pos (10U)
2924 #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
2925 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
2926 #define DMA_ISR_TEIF3_Pos (11U)
2927 #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
2928 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
2929 #define DMA_ISR_GIF4_Pos (12U)
2930 #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
2931 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
2932 #define DMA_ISR_TCIF4_Pos (13U)
2933 #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
2934 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
2935 #define DMA_ISR_HTIF4_Pos (14U)
2936 #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
2937 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
2938 #define DMA_ISR_TEIF4_Pos (15U)
2939 #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
2940 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
2941 #define DMA_ISR_GIF5_Pos (16U)
2942 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
2943 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
2944 #define DMA_ISR_TCIF5_Pos (17U)
2945 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
2946 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
2947 #define DMA_ISR_HTIF5_Pos (18U)
2948 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
2949 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
2950 #define DMA_ISR_TEIF5_Pos (19U)
2951 #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
2952 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
2953 #define DMA_ISR_GIF6_Pos (20U)
2954 #define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
2955 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
2956 #define DMA_ISR_TCIF6_Pos (21U)
2957 #define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
2958 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
2959 #define DMA_ISR_HTIF6_Pos (22U)
2960 #define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
2961 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
2962 #define DMA_ISR_TEIF6_Pos (23U)
2963 #define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
2964 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
2965
2966 /******************* Bit definition for DMA_IFCR register *******************/
2967 #define DMA_IFCR_CGIF1_Pos (0U)
2968 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
2969 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */
2970 #define DMA_IFCR_CTCIF1_Pos (1U)
2971 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
2972 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
2973 #define DMA_IFCR_CHTIF1_Pos (2U)
2974 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
2975 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
2976 #define DMA_IFCR_CTEIF1_Pos (3U)
2977 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
2978 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
2979 #define DMA_IFCR_CGIF2_Pos (4U)
2980 #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
2981 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
2982 #define DMA_IFCR_CTCIF2_Pos (5U)
2983 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
2984 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
2985 #define DMA_IFCR_CHTIF2_Pos (6U)
2986 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
2987 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
2988 #define DMA_IFCR_CTEIF2_Pos (7U)
2989 #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
2990 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
2991 #define DMA_IFCR_CGIF3_Pos (8U)
2992 #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
2993 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
2994 #define DMA_IFCR_CTCIF3_Pos (9U)
2995 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
2996 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
2997 #define DMA_IFCR_CHTIF3_Pos (10U)
2998 #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
2999 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
3000 #define DMA_IFCR_CTEIF3_Pos (11U)
3001 #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
3002 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
3003 #define DMA_IFCR_CGIF4_Pos (12U)
3004 #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
3005 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
3006 #define DMA_IFCR_CTCIF4_Pos (13U)
3007 #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
3008 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
3009 #define DMA_IFCR_CHTIF4_Pos (14U)
3010 #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
3011 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
3012 #define DMA_IFCR_CTEIF4_Pos (15U)
3013 #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
3014 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
3015 #define DMA_IFCR_CGIF5_Pos (16U)
3016 #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
3017 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
3018 #define DMA_IFCR_CTCIF5_Pos (17U)
3019 #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
3020 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
3021 #define DMA_IFCR_CHTIF5_Pos (18U)
3022 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
3023 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
3024 #define DMA_IFCR_CTEIF5_Pos (19U)
3025 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
3026 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
3027 #define DMA_IFCR_CGIF6_Pos (20U)
3028 #define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
3029 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
3030 #define DMA_IFCR_CTCIF6_Pos (21U)
3031 #define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
3032 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
3033 #define DMA_IFCR_CHTIF6_Pos (22U)
3034 #define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
3035 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
3036 #define DMA_IFCR_CTEIF6_Pos (23U)
3037 #define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
3038 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
3039
3040 /******************* Bit definition for DMA_CCR register ********************/
3041 #define DMA_CCR_EN_Pos (0U)
3042 #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
3043 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
3044 #define DMA_CCR_TCIE_Pos (1U)
3045 #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
3046 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
3047 #define DMA_CCR_HTIE_Pos (2U)
3048 #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
3049 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
3050 #define DMA_CCR_TEIE_Pos (3U)
3051 #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
3052 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
3053 #define DMA_CCR_DIR_Pos (4U)
3054 #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
3055 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
3056 #define DMA_CCR_CIRC_Pos (5U)
3057 #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
3058 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
3059 #define DMA_CCR_PINC_Pos (6U)
3060 #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
3061 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
3062 #define DMA_CCR_MINC_Pos (7U)
3063 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
3064 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
3065
3066 #define DMA_CCR_PSIZE_Pos (8U)
3067 #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
3068 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
3069 #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
3070 #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
3071
3072 #define DMA_CCR_MSIZE_Pos (10U)
3073 #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
3074 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
3075 #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
3076 #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
3077
3078 #define DMA_CCR_PL_Pos (12U)
3079 #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
3080 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
3081 #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
3082 #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
3083
3084 #define DMA_CCR_MEM2MEM_Pos (14U)
3085 #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
3086 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
3087
3088 /****************** Bit definition for DMA_CNDTR register *******************/
3089 #define DMA_CNDTR_NDT_Pos (0U)
3090 #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
3091 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
3092
3093 /****************** Bit definition for DMA_CPAR register ********************/
3094 #define DMA_CPAR_PA_Pos (0U)
3095 #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
3096 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
3097
3098 /****************** Bit definition for DMA_CMAR register ********************/
3099 #define DMA_CMAR_MA_Pos (0U)
3100 #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
3101 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
3102
3103 /******************************************************************************/
3104 /* */
3105 /* DMAMUX Controller */
3106 /* */
3107 /******************************************************************************/
3108
3109 /******************** Bits definition for DMAMUX_CxCR register **************/
3110 #define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
3111 #define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x000000FF */
3112 #define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk
3113 #define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */
3114 #define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000002 */
3115 #define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000004 */
3116 #define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000008 */
3117 #define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000010 */
3118 #define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */
3119 #define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */
3120 #define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000080 */
3121
3122 #define DMAMUX_CxCR_SOIE_Pos (8U)
3123 #define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos)/*!< 0x00000100 */
3124 #define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk
3125
3126 #define DMAMUX_CxCR_EGE_Pos (9U)
3127 #define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos)/*!< 0x00000200 */
3128 #define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk
3129
3130 #define DMAMUX_CxCR_SE_Pos (16U)
3131 #define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos)/*!< 0x00010000 */
3132 #define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk
3133
3134 #define DMAMUX_CxCR_SPOL_Pos (17U)
3135 #define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00060000 */
3136 #define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk
3137 #define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00020000 */
3138 #define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00040000 */
3139
3140 #define DMAMUX_CxCR_NBREQ_Pos (19U)
3141 #define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00F80000 */
3142 #define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk
3143 #define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00080000 */
3144 #define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00100000 */
3145 #define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00200000 */
3146 #define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00400000 */
3147 #define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00800000 */
3148
3149 #define DMAMUX_CxCR_SYNC_ID_Pos (24U)
3150 #define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x1F000000 */
3151 #define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk
3152 #define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x01000000 */
3153 #define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x02000000 */
3154 #define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x04000000 */
3155 #define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x08000000 */
3156 #define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x10000000 */
3157
3158 /******************** Bits definition for DMAMUX_CSR register ****************/
3159 #define DMAMUX_CSR_SOF0_Pos (0U)
3160 #define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos)/*!< 0x00000001 */
3161 #define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk
3162 #define DMAMUX_CSR_SOF1_Pos (1U)
3163 #define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos)/*!< 0x00000002 */
3164 #define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk
3165 #define DMAMUX_CSR_SOF2_Pos (2U)
3166 #define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos)/*!< 0x00000004 */
3167 #define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk
3168 #define DMAMUX_CSR_SOF3_Pos (3U)
3169 #define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos)/*!< 0x00000008 */
3170 #define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk
3171 #define DMAMUX_CSR_SOF4_Pos (4U)
3172 #define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos)/*!< 0x00000010 */
3173 #define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk
3174 #define DMAMUX_CSR_SOF5_Pos (5U)
3175 #define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos)/*!< 0x00000020 */
3176 #define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk
3177 #define DMAMUX_CSR_SOF6_Pos (6U)
3178 #define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos)/*!< 0x00000040 */
3179 #define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk
3180 #define DMAMUX_CSR_SOF7_Pos (7U)
3181 #define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos)/*!< 0x00000080 */
3182 #define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk
3183 #define DMAMUX_CSR_SOF8_Pos (8U)
3184 #define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos)/*!< 0x00000100 */
3185 #define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk
3186 #define DMAMUX_CSR_SOF9_Pos (9U)
3187 #define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos)/*!< 0x00000200 */
3188 #define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk
3189 #define DMAMUX_CSR_SOF10_Pos (10U)
3190 #define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos)/*!< 0x00000400 */
3191 #define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk
3192 #define DMAMUX_CSR_SOF11_Pos (11U)
3193 #define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos)/*!< 0x00000800 */
3194 #define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk
3195
3196 /******************** Bits definition for DMAMUX_CFR register ****************/
3197 #define DMAMUX_CFR_CSOF0_Pos (0U)
3198 #define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos)/*!< 0x00000001 */
3199 #define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk
3200 #define DMAMUX_CFR_CSOF1_Pos (1U)
3201 #define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos)/*!< 0x00000002 */
3202 #define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk
3203 #define DMAMUX_CFR_CSOF2_Pos (2U)
3204 #define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos)/*!< 0x00000004 */
3205 #define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk
3206 #define DMAMUX_CFR_CSOF3_Pos (3U)
3207 #define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos)/*!< 0x00000008 */
3208 #define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk
3209 #define DMAMUX_CFR_CSOF4_Pos (4U)
3210 #define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos)/*!< 0x00000010 */
3211 #define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk
3212 #define DMAMUX_CFR_CSOF5_Pos (5U)
3213 #define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos)/*!< 0x00000020 */
3214 #define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk
3215 #define DMAMUX_CFR_CSOF6_Pos (6U)
3216 #define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos)/*!< 0x00000040 */
3217 #define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk
3218 #define DMAMUX_CFR_CSOF7_Pos (7U)
3219 #define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos)/*!< 0x00000080 */
3220 #define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk
3221 #define DMAMUX_CFR_CSOF8_Pos (8U)
3222 #define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos)/*!< 0x00000100 */
3223 #define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk
3224 #define DMAMUX_CFR_CSOF9_Pos (9U)
3225 #define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos)/*!< 0x00000200 */
3226 #define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk
3227 #define DMAMUX_CFR_CSOF10_Pos (10U)
3228 #define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos)/*!< 0x00000400 */
3229 #define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk
3230 #define DMAMUX_CFR_CSOF11_Pos (11U)
3231 #define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos)/*!< 0x00000800 */
3232 #define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk
3233
3234 /******************** Bits definition for DMAMUX_RGxCR register ************/
3235 #define DMAMUX_RGxCR_SIG_ID_Pos (0U)
3236 #define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x0000001F */
3237 #define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk
3238 #define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000001 */
3239 #define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000002 */
3240 #define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000004 */
3241 #define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000008 */
3242 #define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000010 */
3243
3244 #define DMAMUX_RGxCR_OIE_Pos (8U)
3245 #define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos)/*!< 0x00000100 */
3246 #define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk
3247
3248 #define DMAMUX_RGxCR_GE_Pos (16U)
3249 #define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos)/*!< 0x00010000 */
3250 #define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk
3251
3252 #define DMAMUX_RGxCR_GPOL_Pos (17U)
3253 #define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00060000 */
3254 #define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk
3255 #define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00020000 */
3256 #define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00040000 */
3257
3258 #define DMAMUX_RGxCR_GNBREQ_Pos (19U)
3259 #define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00F80000 */
3260 #define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk
3261 #define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00080000 */
3262 #define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00100000 */
3263 #define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00200000 */
3264 #define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00400000 */
3265 #define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00800000 */
3266
3267 /******************** Bits definition for DMAMUX_RGSR register **************/
3268 #define DMAMUX_RGSR_OF0_Pos (0U)
3269 #define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos)/*!< 0x00000001 */
3270 #define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk
3271 #define DMAMUX_RGSR_OF1_Pos (1U)
3272 #define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos)/*!< 0x00000002 */
3273 #define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk
3274 #define DMAMUX_RGSR_OF2_Pos (2U)
3275 #define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos)/*!< 0x00000004 */
3276 #define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk
3277 #define DMAMUX_RGSR_OF3_Pos (3U)
3278 #define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos)/*!< 0x00000008 */
3279 #define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk
3280
3281 /******************** Bits definition for DMAMUX_RGCFR register ************/
3282 #define DMAMUX_RGCFR_COF0_Pos (0U)
3283 #define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos)/*!< 0x00000001 */
3284 #define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk
3285 #define DMAMUX_RGCFR_COF1_Pos (1U)
3286 #define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos)/*!< 0x00000002 */
3287 #define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk
3288 #define DMAMUX_RGCFR_COF2_Pos (2U)
3289 #define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos)/*!< 0x00000004 */
3290 #define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk
3291 #define DMAMUX_RGCFR_COF3_Pos (3U)
3292 #define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos)/*!< 0x00000008 */
3293 #define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk
3294
3295 /******************** Bits definition for DMAMUX_IPHW_CFGR2 ******************/
3296 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos (0U)
3297 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos)/*!< 0x00000001 */
3298 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk
3299 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos (1U)
3300 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos)/*!< 0x00000002 */
3301 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk
3302 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos (2U)
3303 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos)/*!< 0x00000004 */
3304 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk
3305 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos (3U)
3306 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos)/*!< 0x00000008 */
3307 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk
3308 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos (4U)
3309 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos)/*!< 0x00000010 */
3310 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk
3311 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos (5U)
3312 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos)/*!< 0x00000020 */
3313 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk
3314 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos (6U)
3315 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos)/*!< 0x00000040 */
3316 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk
3317 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos (7U)
3318 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos)/*!< 0x00000080 */
3319 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk
3320
3321 /******************** Bits definition for DMAMUX_IPHW_CFGR1 ******************/
3322 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos (0U)
3323 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos)/*!< 0x00000001 */
3324 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk
3325 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos (1U)
3326 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos)/*!< 0x00000002 */
3327 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk
3328 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos (2U)
3329 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos)/*!< 0x00000004 */
3330 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk
3331 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos (3U)
3332 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos)/*!< 0x00000008 */
3333 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk
3334 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos (4U)
3335 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos)/*!< 0x00000010 */
3336 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk
3337 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos (5U)
3338 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos)/*!< 0x00000020 */
3339 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk
3340 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos (6U)
3341 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos)/*!< 0x00000040 */
3342 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk
3343 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos (7U)
3344 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos)/*!< 0x00000080 */
3345 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk
3346 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos (8U)
3347 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos)/*!< 0x00000100 */
3348 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk
3349 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos (9U)
3350 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos)/*!< 0x00000200 */
3351 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk
3352 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos (10U)
3353 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos)/*!< 0x00000400 */
3354 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk
3355 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos (11U)
3356 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos)/*!< 0x00000800 */
3357 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk
3358 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos (12U)
3359 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos)/*!< 0x00001000 */
3360 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk
3361 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos (13U)
3362 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos)/*!< 0x00002000 */
3363 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk
3364 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos (14U)
3365 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos)/*!< 0x00004000 */
3366 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk
3367 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos (15U)
3368 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos)/*!< 0x00008000 */
3369 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk
3370 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos (16U)
3371 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos)/*!< 0x00010000 */
3372 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk
3373 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos (17U)
3374 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos)/*!< 0x00020000 */
3375 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk
3376 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos (18U)
3377 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos)/*!< 0x00040000 */
3378 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk
3379 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos (19U)
3380 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos)/*!< 0x00080000 */
3381 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk
3382 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos (20U)
3383 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos)/*!< 0x00100000 */
3384 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk
3385 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos (21U)
3386 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos)/*!< 0x00200000 */
3387 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk
3388 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos (22U)
3389 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos)/*!< 0x00400000 */
3390 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk
3391 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos (23U)
3392 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos)/*!< 0x00800000 */
3393 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk
3394 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos (24U)
3395 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos)/*!< 0x01000000 */
3396 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk
3397 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos (25U)
3398 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos)/*!< 0x02000000 */
3399 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk
3400 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos (26U)
3401 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos)/*!< 0x04000000 */
3402 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk
3403 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos (27U)
3404 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos)/*!< 0x08000000 */
3405 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk
3406 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos (28U)
3407 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos)/*!< 0x10000000 */
3408 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk
3409 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos (29U)
3410 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos)/*!< 0x20000000 */
3411 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk
3412 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos (30U)
3413 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos)/*!< 0x40000000 */
3414 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk
3415 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos (31U)
3416 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos)/*!< 0x80000000 */
3417 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk
3418
3419
3420 /******************************************************************************/
3421 /* */
3422 /* External Interrupt/Event Controller */
3423 /* */
3424 /******************************************************************************/
3425 /******************* Bit definition for EXTI_IMR1 register ******************/
3426 #define EXTI_IMR1_IM0_Pos (0U)
3427 #define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
3428 #define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
3429 #define EXTI_IMR1_IM1_Pos (1U)
3430 #define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
3431 #define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
3432 #define EXTI_IMR1_IM2_Pos (2U)
3433 #define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
3434 #define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
3435 #define EXTI_IMR1_IM3_Pos (3U)
3436 #define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
3437 #define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
3438 #define EXTI_IMR1_IM4_Pos (4U)
3439 #define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
3440 #define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
3441 #define EXTI_IMR1_IM5_Pos (5U)
3442 #define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
3443 #define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
3444 #define EXTI_IMR1_IM6_Pos (6U)
3445 #define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
3446 #define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
3447 #define EXTI_IMR1_IM7_Pos (7U)
3448 #define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
3449 #define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
3450 #define EXTI_IMR1_IM8_Pos (8U)
3451 #define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
3452 #define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
3453 #define EXTI_IMR1_IM9_Pos (9U)
3454 #define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
3455 #define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
3456 #define EXTI_IMR1_IM10_Pos (10U)
3457 #define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
3458 #define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
3459 #define EXTI_IMR1_IM11_Pos (11U)
3460 #define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
3461 #define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
3462 #define EXTI_IMR1_IM12_Pos (12U)
3463 #define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
3464 #define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
3465 #define EXTI_IMR1_IM13_Pos (13U)
3466 #define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
3467 #define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
3468 #define EXTI_IMR1_IM14_Pos (14U)
3469 #define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
3470 #define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
3471 #define EXTI_IMR1_IM15_Pos (15U)
3472 #define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
3473 #define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
3474 #define EXTI_IMR1_IM16_Pos (16U)
3475 #define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
3476 #define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
3477 #define EXTI_IMR1_IM17_Pos (17U)
3478 #define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
3479 #define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
3480 #define EXTI_IMR1_IM18_Pos (18U)
3481 #define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
3482 #define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
3483 #define EXTI_IMR1_IM19_Pos (19U)
3484 #define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
3485 #define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
3486 #define EXTI_IMR1_IM20_Pos (20U)
3487 #define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
3488 #define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
3489 #define EXTI_IMR1_IM21_Pos (21U)
3490 #define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
3491 #define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
3492 #define EXTI_IMR1_IM22_Pos (22U)
3493 #define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
3494 #define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
3495 #define EXTI_IMR1_IM23_Pos (23U)
3496 #define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
3497 #define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
3498 #define EXTI_IMR1_IM24_Pos (24U)
3499 #define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
3500 #define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
3501 #define EXTI_IMR1_IM25_Pos (25U)
3502 #define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
3503 #define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
3504 #define EXTI_IMR1_IM26_Pos (26U)
3505 #define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
3506 #define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
3507 #define EXTI_IMR1_IM27_Pos (27U)
3508 #define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
3509 #define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
3510 #define EXTI_IMR1_IM28_Pos (28U)
3511 #define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
3512 #define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
3513 #define EXTI_IMR1_IM29_Pos (29U)
3514 #define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
3515 #define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
3516 #define EXTI_IMR1_IM30_Pos (30U)
3517 #define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
3518 #define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
3519 #define EXTI_IMR1_IM_Pos (0U)
3520 #define EXTI_IMR1_IM_Msk (0x7FFFFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0x7FFFFFFF */
3521 #define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
3522
3523 /******************* Bit definition for EXTI_EMR1 register ******************/
3524 #define EXTI_EMR1_EM0_Pos (0U)
3525 #define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
3526 #define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
3527 #define EXTI_EMR1_EM1_Pos (1U)
3528 #define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
3529 #define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
3530 #define EXTI_EMR1_EM2_Pos (2U)
3531 #define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
3532 #define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
3533 #define EXTI_EMR1_EM3_Pos (3U)
3534 #define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
3535 #define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
3536 #define EXTI_EMR1_EM4_Pos (4U)
3537 #define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
3538 #define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
3539 #define EXTI_EMR1_EM5_Pos (5U)
3540 #define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
3541 #define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
3542 #define EXTI_EMR1_EM6_Pos (6U)
3543 #define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
3544 #define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
3545 #define EXTI_EMR1_EM7_Pos (7U)
3546 #define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
3547 #define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
3548 #define EXTI_EMR1_EM8_Pos (8U)
3549 #define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
3550 #define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
3551 #define EXTI_EMR1_EM9_Pos (9U)
3552 #define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
3553 #define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
3554 #define EXTI_EMR1_EM10_Pos (10U)
3555 #define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
3556 #define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
3557 #define EXTI_EMR1_EM11_Pos (11U)
3558 #define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
3559 #define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
3560 #define EXTI_EMR1_EM12_Pos (12U)
3561 #define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
3562 #define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
3563 #define EXTI_EMR1_EM13_Pos (13U)
3564 #define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
3565 #define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
3566 #define EXTI_EMR1_EM14_Pos (14U)
3567 #define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
3568 #define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
3569 #define EXTI_EMR1_EM15_Pos (15U)
3570 #define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
3571 #define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
3572 #define EXTI_EMR1_EM16_Pos (16U)
3573 #define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
3574 #define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
3575 #define EXTI_EMR1_EM17_Pos (17U)
3576 #define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
3577 #define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
3578 #define EXTI_EMR1_EM18_Pos (18U)
3579 #define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
3580 #define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
3581 #define EXTI_EMR1_EM19_Pos (19U)
3582 #define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
3583 #define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
3584 #define EXTI_EMR1_EM20_Pos (20U)
3585 #define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
3586 #define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
3587 #define EXTI_EMR1_EM21_Pos (21U)
3588 #define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
3589 #define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
3590 #define EXTI_EMR1_EM22_Pos (22U)
3591 #define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
3592 #define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
3593 #define EXTI_EMR1_EM23_Pos (23U)
3594 #define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
3595 #define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
3596 #define EXTI_EMR1_EM24_Pos (24U)
3597 #define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
3598 #define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
3599 #define EXTI_EMR1_EM25_Pos (25U)
3600 #define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
3601 #define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
3602 #define EXTI_EMR1_EM26_Pos (26U)
3603 #define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
3604 #define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
3605 #define EXTI_EMR1_EM27_Pos (27U)
3606 #define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
3607 #define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
3608 #define EXTI_EMR1_EM28_Pos (28U)
3609 #define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
3610 #define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
3611 #define EXTI_EMR1_EM29_Pos (29U)
3612 #define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
3613 #define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
3614 #define EXTI_EMR1_EM30_Pos (30U)
3615 #define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
3616 #define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
3617
3618 /****************** Bit definition for EXTI_RTSR1 register ******************/
3619 #define EXTI_RTSR1_RT0_Pos (0U)
3620 #define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
3621 #define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
3622 #define EXTI_RTSR1_RT1_Pos (1U)
3623 #define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
3624 #define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
3625 #define EXTI_RTSR1_RT2_Pos (2U)
3626 #define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
3627 #define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
3628 #define EXTI_RTSR1_RT3_Pos (3U)
3629 #define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
3630 #define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
3631 #define EXTI_RTSR1_RT4_Pos (4U)
3632 #define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
3633 #define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
3634 #define EXTI_RTSR1_RT5_Pos (5U)
3635 #define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
3636 #define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
3637 #define EXTI_RTSR1_RT6_Pos (6U)
3638 #define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
3639 #define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
3640 #define EXTI_RTSR1_RT7_Pos (7U)
3641 #define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
3642 #define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
3643 #define EXTI_RTSR1_RT8_Pos (8U)
3644 #define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
3645 #define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
3646 #define EXTI_RTSR1_RT9_Pos (9U)
3647 #define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
3648 #define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
3649 #define EXTI_RTSR1_RT10_Pos (10U)
3650 #define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
3651 #define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
3652 #define EXTI_RTSR1_RT11_Pos (11U)
3653 #define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
3654 #define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
3655 #define EXTI_RTSR1_RT12_Pos (12U)
3656 #define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
3657 #define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
3658 #define EXTI_RTSR1_RT13_Pos (13U)
3659 #define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
3660 #define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
3661 #define EXTI_RTSR1_RT14_Pos (14U)
3662 #define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
3663 #define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
3664 #define EXTI_RTSR1_RT15_Pos (15U)
3665 #define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
3666 #define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
3667 #define EXTI_RTSR1_RT16_Pos (16U)
3668 #define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */
3669 #define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
3670 #define EXTI_RTSR1_RT17_Pos (17U)
3671 #define EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos) /*!< 0x00020000 */
3672 #define EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
3673 #define EXTI_RTSR1_RT19_Pos (19U)
3674 #define EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */
3675 #define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
3676 #define EXTI_RTSR1_RT20_Pos (20U)
3677 #define EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */
3678 #define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
3679 #define EXTI_RTSR1_RT21_Pos (21U)
3680 #define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */
3681 #define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
3682 #define EXTI_RTSR1_RT22_Pos (22U)
3683 #define EXTI_RTSR1_RT22_Msk (0x1UL << EXTI_RTSR1_RT22_Pos) /*!< 0x00400000 */
3684 #define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
3685 #define EXTI_RTSR1_RT29_Pos (29U)
3686 #define EXTI_RTSR1_RT29_Msk (0x1UL << EXTI_RTSR1_RT29_Pos) /*!< 0x20000000 */
3687 #define EXTI_RTSR1_RT29 EXTI_RTSR1_RT29_Msk /*!< Rising trigger event configuration bit of line 29 */
3688 #define EXTI_RTSR1_RT30_Pos (30U)
3689 #define EXTI_RTSR1_RT30_Msk (0x1UL << EXTI_RTSR1_RT30_Pos) /*!< 0x40000000 */
3690 #define EXTI_RTSR1_RT30 EXTI_RTSR1_RT30_Msk /*!< Rising trigger event configuration bit of line 30 */
3691
3692 /****************** Bit definition for EXTI_FTSR1 register ******************/
3693 #define EXTI_FTSR1_FT0_Pos (0U)
3694 #define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
3695 #define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
3696 #define EXTI_FTSR1_FT1_Pos (1U)
3697 #define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
3698 #define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
3699 #define EXTI_FTSR1_FT2_Pos (2U)
3700 #define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
3701 #define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
3702 #define EXTI_FTSR1_FT3_Pos (3U)
3703 #define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
3704 #define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
3705 #define EXTI_FTSR1_FT4_Pos (4U)
3706 #define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
3707 #define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
3708 #define EXTI_FTSR1_FT5_Pos (5U)
3709 #define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
3710 #define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
3711 #define EXTI_FTSR1_FT6_Pos (6U)
3712 #define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
3713 #define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
3714 #define EXTI_FTSR1_FT7_Pos (7U)
3715 #define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
3716 #define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
3717 #define EXTI_FTSR1_FT8_Pos (8U)
3718 #define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
3719 #define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
3720 #define EXTI_FTSR1_FT9_Pos (9U)
3721 #define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
3722 #define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
3723 #define EXTI_FTSR1_FT10_Pos (10U)
3724 #define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
3725 #define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
3726 #define EXTI_FTSR1_FT11_Pos (11U)
3727 #define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
3728 #define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
3729 #define EXTI_FTSR1_FT12_Pos (12U)
3730 #define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
3731 #define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
3732 #define EXTI_FTSR1_FT13_Pos (13U)
3733 #define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
3734 #define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
3735 #define EXTI_FTSR1_FT14_Pos (14U)
3736 #define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
3737 #define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
3738 #define EXTI_FTSR1_FT15_Pos (15U)
3739 #define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
3740 #define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
3741 #define EXTI_FTSR1_FT16_Pos (16U)
3742 #define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */
3743 #define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
3744 #define EXTI_FTSR1_FT17_Pos (17U)
3745 #define EXTI_FTSR1_FT17_Msk (0x1UL << EXTI_FTSR1_FT17_Pos) /*!< 0x00020000 */
3746 #define EXTI_FTSR1_FT17 EXTI_FTSR1_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
3747 #define EXTI_FTSR1_FT19_Pos (19U)
3748 #define EXTI_FTSR1_FT19_Msk (0x1UL << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */
3749 #define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
3750 #define EXTI_FTSR1_FT20_Pos (20U)
3751 #define EXTI_FTSR1_FT20_Msk (0x1UL << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */
3752 #define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
3753 #define EXTI_FTSR1_FT21_Pos (21U)
3754 #define EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */
3755 #define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
3756 #define EXTI_FTSR1_FT22_Pos (22U)
3757 #define EXTI_FTSR1_FT22_Msk (0x1UL << EXTI_FTSR1_FT22_Pos) /*!< 0x00400000 */
3758 #define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
3759 #define EXTI_FTSR1_FT29_Pos (29U)
3760 #define EXTI_FTSR1_FT29_Msk (0x1UL << EXTI_FTSR1_FT29_Pos) /*!< 0x20000000 */
3761 #define EXTI_FTSR1_FT29 EXTI_FTSR1_FT29_Msk /*!< Falling trigger event configuration bit of line 29 */
3762 #define EXTI_FTSR1_FT30_Pos (30U)
3763 #define EXTI_FTSR1_FT30_Msk (0x1UL << EXTI_FTSR1_FT30_Pos) /*!< 0x40000000 */
3764 #define EXTI_FTSR1_FT30 EXTI_FTSR1_FT30_Msk /*!< Falling trigger event configuration bit of line 30 */
3765
3766 /****************** Bit definition for EXTI_SWIER1 register *****************/
3767 #define EXTI_SWIER1_SWI0_Pos (0U)
3768 #define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
3769 #define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
3770 #define EXTI_SWIER1_SWI1_Pos (1U)
3771 #define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
3772 #define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
3773 #define EXTI_SWIER1_SWI2_Pos (2U)
3774 #define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
3775 #define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
3776 #define EXTI_SWIER1_SWI3_Pos (3U)
3777 #define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
3778 #define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
3779 #define EXTI_SWIER1_SWI4_Pos (4U)
3780 #define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
3781 #define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
3782 #define EXTI_SWIER1_SWI5_Pos (5U)
3783 #define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
3784 #define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
3785 #define EXTI_SWIER1_SWI6_Pos (6U)
3786 #define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
3787 #define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
3788 #define EXTI_SWIER1_SWI7_Pos (7U)
3789 #define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
3790 #define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
3791 #define EXTI_SWIER1_SWI8_Pos (8U)
3792 #define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
3793 #define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
3794 #define EXTI_SWIER1_SWI9_Pos (9U)
3795 #define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
3796 #define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
3797 #define EXTI_SWIER1_SWI10_Pos (10U)
3798 #define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
3799 #define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
3800 #define EXTI_SWIER1_SWI11_Pos (11U)
3801 #define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
3802 #define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
3803 #define EXTI_SWIER1_SWI12_Pos (12U)
3804 #define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
3805 #define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
3806 #define EXTI_SWIER1_SWI13_Pos (13U)
3807 #define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
3808 #define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
3809 #define EXTI_SWIER1_SWI14_Pos (14U)
3810 #define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
3811 #define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
3812 #define EXTI_SWIER1_SWI15_Pos (15U)
3813 #define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
3814 #define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
3815 #define EXTI_SWIER1_SWI16_Pos (16U)
3816 #define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */
3817 #define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */
3818 #define EXTI_SWIER1_SWI17_Pos (17U)
3819 #define EXTI_SWIER1_SWI17_Msk (0x1UL << EXTI_SWIER1_SWI17_Pos) /*!< 0x00020000 */
3820 #define EXTI_SWIER1_SWI17 EXTI_SWIER1_SWI17_Msk /*!< Software Interrupt on line 17 */
3821 #define EXTI_SWIER1_SWI19_Pos (19U)
3822 #define EXTI_SWIER1_SWI19_Msk (0x1UL << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */
3823 #define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */
3824 #define EXTI_SWIER1_SWI20_Pos (20U)
3825 #define EXTI_SWIER1_SWI20_Msk (0x1UL << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */
3826 #define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */
3827 #define EXTI_SWIER1_SWI21_Pos (21U)
3828 #define EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */
3829 #define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */
3830 #define EXTI_SWIER1_SWI22_Pos (22U)
3831 #define EXTI_SWIER1_SWI22_Msk (0x1UL << EXTI_SWIER1_SWI22_Pos) /*!< 0x00400000 */
3832 #define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk /*!< Software Interrupt on line 22 */
3833 #define EXTI_SWIER1_SWI29_Pos (29U)
3834 #define EXTI_SWIER1_SWI29_Msk (0x1UL << EXTI_SWIER1_SWI29_Pos) /*!< 0x20000000 */
3835 #define EXTI_SWIER1_SWI29 EXTI_SWIER1_SWI29_Msk /*!< Software Interrupt on line 29 */
3836 #define EXTI_SWIER1_SWI30_Pos (30U)
3837 #define EXTI_SWIER1_SWI30_Msk (0x1UL << EXTI_SWIER1_SWI30_Pos) /*!< 0x40000000 */
3838 #define EXTI_SWIER1_SWI30 EXTI_SWIER1_SWI30_Msk /*!< Software Interrupt on line 30 */
3839
3840 /******************* Bit definition for EXTI_PR1 register *******************/
3841 #define EXTI_PR1_PIF0_Pos (0U)
3842 #define EXTI_PR1_PIF0_Msk (0x1UL << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */
3843 #define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */
3844 #define EXTI_PR1_PIF1_Pos (1U)
3845 #define EXTI_PR1_PIF1_Msk (0x1UL << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */
3846 #define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */
3847 #define EXTI_PR1_PIF2_Pos (2U)
3848 #define EXTI_PR1_PIF2_Msk (0x1UL << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */
3849 #define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */
3850 #define EXTI_PR1_PIF3_Pos (3U)
3851 #define EXTI_PR1_PIF3_Msk (0x1UL << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */
3852 #define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */
3853 #define EXTI_PR1_PIF4_Pos (4U)
3854 #define EXTI_PR1_PIF4_Msk (0x1UL << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */
3855 #define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */
3856 #define EXTI_PR1_PIF5_Pos (5U)
3857 #define EXTI_PR1_PIF5_Msk (0x1UL << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */
3858 #define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */
3859 #define EXTI_PR1_PIF6_Pos (6U)
3860 #define EXTI_PR1_PIF6_Msk (0x1UL << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */
3861 #define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */
3862 #define EXTI_PR1_PIF7_Pos (7U)
3863 #define EXTI_PR1_PIF7_Msk (0x1UL << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */
3864 #define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */
3865 #define EXTI_PR1_PIF8_Pos (8U)
3866 #define EXTI_PR1_PIF8_Msk (0x1UL << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */
3867 #define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */
3868 #define EXTI_PR1_PIF9_Pos (9U)
3869 #define EXTI_PR1_PIF9_Msk (0x1UL << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */
3870 #define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */
3871 #define EXTI_PR1_PIF10_Pos (10U)
3872 #define EXTI_PR1_PIF10_Msk (0x1UL << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */
3873 #define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */
3874 #define EXTI_PR1_PIF11_Pos (11U)
3875 #define EXTI_PR1_PIF11_Msk (0x1UL << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */
3876 #define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */
3877 #define EXTI_PR1_PIF12_Pos (12U)
3878 #define EXTI_PR1_PIF12_Msk (0x1UL << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */
3879 #define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */
3880 #define EXTI_PR1_PIF13_Pos (13U)
3881 #define EXTI_PR1_PIF13_Msk (0x1UL << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */
3882 #define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */
3883 #define EXTI_PR1_PIF14_Pos (14U)
3884 #define EXTI_PR1_PIF14_Msk (0x1UL << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */
3885 #define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */
3886 #define EXTI_PR1_PIF15_Pos (15U)
3887 #define EXTI_PR1_PIF15_Msk (0x1UL << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */
3888 #define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */
3889 #define EXTI_PR1_PIF16_Pos (16U)
3890 #define EXTI_PR1_PIF16_Msk (0x1UL << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */
3891 #define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */
3892 #define EXTI_PR1_PIF17_Pos (17U)
3893 #define EXTI_PR1_PIF17_Msk (0x1UL << EXTI_PR1_PIF17_Pos) /*!< 0x00020000 */
3894 #define EXTI_PR1_PIF17 EXTI_PR1_PIF17_Msk /*!< Pending bit for line 17 */
3895 #define EXTI_PR1_PIF19_Pos (19U)
3896 #define EXTI_PR1_PIF19_Msk (0x1UL << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */
3897 #define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */
3898 #define EXTI_PR1_PIF20_Pos (20U)
3899 #define EXTI_PR1_PIF20_Msk (0x1UL << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */
3900 #define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */
3901 #define EXTI_PR1_PIF21_Pos (21U)
3902 #define EXTI_PR1_PIF21_Msk (0x1UL << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */
3903 #define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */
3904 #define EXTI_PR1_PIF22_Pos (22U)
3905 #define EXTI_PR1_PIF22_Msk (0x1UL << EXTI_PR1_PIF22_Pos) /*!< 0x00400000 */
3906 #define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk /*!< Pending bit for line 22 */
3907 #define EXTI_PR1_PIF29_Pos (29U)
3908 #define EXTI_PR1_PIF29_Msk (0x1UL << EXTI_PR1_PIF29_Pos) /*!< 0x20000000 */
3909 #define EXTI_PR1_PIF29 EXTI_PR1_PIF29_Msk /*!< Pending bit for line 29 */
3910 #define EXTI_PR1_PIF30_Pos (30U)
3911 #define EXTI_PR1_PIF30_Msk (0x1UL << EXTI_PR1_PIF30_Pos) /*!< 0x40000000 */
3912 #define EXTI_PR1_PIF30 EXTI_PR1_PIF30_Msk /*!< Pending bit for line 30 */
3913
3914 /******************* Bit definition for EXTI_IMR2 register ******************/
3915 #define EXTI_IMR2_IM34_Pos (2U)
3916 #define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
3917 #define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
3918 #define EXTI_IMR2_IM36_Pos (4U)
3919 #define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
3920 #define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
3921 #define EXTI_IMR2_IM37_Pos (5U)
3922 #define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
3923 #define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
3924 #define EXTI_IMR2_IM38_Pos (6U)
3925 #define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
3926 #define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
3927 #define EXTI_IMR2_IM39_Pos (7U)
3928 #define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
3929 #define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
3930 #define EXTI_IMR2_IM40_Pos (8U)
3931 #define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
3932 #define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
3933 #define EXTI_IMR2_IM41_Pos (9U)
3934 #define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos) /*!< 0x00000200 */
3935 #define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk /*!< Interrupt Mask on line 41 */
3936 #define EXTI_IMR2_IM_Pos (0U)
3937 #define EXTI_IMR2_IM_Msk (0x3F4UL << EXTI_IMR2_IM_Pos) /*!< 0x000003F4 */
3938 #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
3939
3940 /******************* Bit definition for EXTI_EMR2 register ******************/
3941 #define EXTI_EMR2_EM34_Pos (2U)
3942 #define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
3943 #define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */
3944 #define EXTI_EMR2_EM36_Pos (4U)
3945 #define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
3946 #define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
3947 #define EXTI_EMR2_EM37_Pos (5U)
3948 #define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
3949 #define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
3950 #define EXTI_EMR2_EM38_Pos (6U)
3951 #define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
3952 #define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
3953 #define EXTI_EMR2_EM39_Pos (7U)
3954 #define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
3955 #define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
3956 #define EXTI_EMR2_EM40_Pos (8U)
3957 #define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
3958 #define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40 */
3959 #define EXTI_EMR2_EM41_Pos (9U)
3960 #define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos) /*!< 0x00000200 */
3961 #define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk /*!< Event Mask on line 41 */
3962 #define EXTI_EMR2_EM_Pos (0U)
3963 #define EXTI_EMR2_EM_Msk (0x3F4UL << EXTI_EMR2_EM_Pos) /*!< 0x000003F4 */
3964 #define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
3965
3966 /****************** Bit definition for EXTI_RTSR2 register ******************/
3967 #define EXTI_RTSR2_RT38_Pos (6U)
3968 #define EXTI_RTSR2_RT38_Msk (0x1UL << EXTI_RTSR2_RT38_Pos) /*!< 0x00000040 */
3969 #define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger event configuration bit of line 38 */
3970 #define EXTI_RTSR2_RT39_Pos (7U)
3971 #define EXTI_RTSR2_RT39_Msk (0x1UL << EXTI_RTSR2_RT39_Pos) /*!< 0x00000080 */
3972 #define EXTI_RTSR2_RT39 EXTI_RTSR2_RT39_Msk /*!< Rising trigger event configuration bit of line 39 */
3973 #define EXTI_RTSR2_RT40_Pos (8U)
3974 #define EXTI_RTSR2_RT40_Msk (0x1UL << EXTI_RTSR2_RT40_Pos) /*!< 0x00000100 */
3975 #define EXTI_RTSR2_RT40 EXTI_RTSR2_RT40_Msk /*!< Rising trigger event configuration bit of line 40 */
3976 #define EXTI_RTSR2_RT41_Pos (9U)
3977 #define EXTI_RTSR2_RT41_Msk (0x1UL << EXTI_RTSR2_RT41_Pos) /*!< 0x00000200 */
3978 #define EXTI_RTSR2_RT41 EXTI_RTSR2_RT41_Msk /*!< Rising trigger event configuration bit of line 41 */
3979
3980 /****************** Bit definition for EXTI_FTSR2 register ******************/
3981 #define EXTI_FTSR2_FT38_Pos (6U)
3982 #define EXTI_FTSR2_FT38_Msk (0x1UL << EXTI_FTSR2_FT38_Pos) /*!< 0x00000040 */
3983 #define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger event configuration bit of line 37 */
3984 #define EXTI_FTSR2_FT39_Pos (7U)
3985 #define EXTI_FTSR2_FT39_Msk (0x1UL << EXTI_FTSR2_FT39_Pos) /*!< 0x00000080 */
3986 #define EXTI_FTSR2_FT39 EXTI_FTSR2_FT39_Msk /*!< Falling trigger event configuration bit of line 39 */
3987 #define EXTI_FTSR2_FT40_Pos (8U)
3988 #define EXTI_FTSR2_FT40_Msk (0x1UL << EXTI_FTSR2_FT40_Pos) /*!< 0x00000100 */
3989 #define EXTI_FTSR2_FT40 EXTI_FTSR2_FT40_Msk /*!< Falling trigger event configuration bit of line 40 */
3990 #define EXTI_FTSR2_FT41_Pos (9U)
3991 #define EXTI_FTSR2_FT41_Msk (0x1UL << EXTI_FTSR2_FT41_Pos) /*!< 0x00000200 */
3992 #define EXTI_FTSR2_FT41 EXTI_FTSR2_FT41_Msk /*!< Falling trigger event configuration bit of line 41 */
3993
3994 /****************** Bit definition for EXTI_SWIER2 register *****************/
3995 #define EXTI_SWIER2_SWI38_Pos (6U)
3996 #define EXTI_SWIER2_SWI38_Msk (0x1UL << EXTI_SWIER2_SWI38_Pos) /*!< 0x00000040 */
3997 #define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */
3998 #define EXTI_SWIER2_SWI39_Pos (7U)
3999 #define EXTI_SWIER2_SWI39_Msk (0x1UL << EXTI_SWIER2_SWI39_Pos) /*!< 0x00000080 */
4000 #define EXTI_SWIER2_SWI39 EXTI_SWIER2_SWI39_Msk /*!< Software Interrupt on line 39 */
4001 #define EXTI_SWIER2_SWI40_Pos (8U)
4002 #define EXTI_SWIER2_SWI40_Msk (0x1UL << EXTI_SWIER2_SWI40_Pos) /*!< 0x00000100 */
4003 #define EXTI_SWIER2_SWI40 EXTI_SWIER2_SWI40_Msk /*!< Software Interrupt on line 40 */
4004 #define EXTI_SWIER2_SWI41_Pos (9U)
4005 #define EXTI_SWIER2_SWI41_Msk (0x1UL << EXTI_SWIER2_SWI41_Pos) /*!< 0x00000200 */
4006 #define EXTI_SWIER2_SWI41 EXTI_SWIER2_SWI41_Msk /*!< Software Interrupt on line 41 */
4007
4008 /******************* Bit definition for EXTI_PR2 register *******************/
4009 #define EXTI_PR2_PIF38_Pos (6U)
4010 #define EXTI_PR2_PIF38_Msk (0x1UL << EXTI_PR2_PIF38_Pos) /*!< 0x00000040 */
4011 #define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk /*!< Pending bit for line 38 */
4012 #define EXTI_PR2_PIF39_Pos (7U)
4013 #define EXTI_PR2_PIF39_Msk (0x1UL << EXTI_PR2_PIF39_Pos) /*!< 0x00000080 */
4014 #define EXTI_PR2_PIF39 EXTI_PR2_PIF39_Msk /*!< Pending bit for line 39 */
4015 #define EXTI_PR2_PIF40_Pos (8U)
4016 #define EXTI_PR2_PIF40_Msk (0x1UL << EXTI_PR2_PIF40_Pos) /*!< 0x00000100 */
4017 #define EXTI_PR2_PIF40 EXTI_PR2_PIF40_Msk /*!< Pending bit for line 40 */
4018 #define EXTI_PR2_PIF41_Pos (9U)
4019 #define EXTI_PR2_PIF41_Msk (0x1UL << EXTI_PR2_PIF41_Pos) /*!< 0x00000200 */
4020 #define EXTI_PR2_PIF41 EXTI_PR2_PIF41_Msk /*!< Pending bit for line 41 */
4021
4022 /******************************************************************************/
4023 /* */
4024 /* Flexible Datarate Controller Area Network */
4025 /* */
4026 /******************************************************************************/
4027 /*!<FDCAN control and status registers */
4028 /***************** Bit definition for FDCAN_CREL register *******************/
4029 #define FDCAN_CREL_DAY_Pos (0U)
4030 #define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos) /*!< 0x000000FF */
4031 #define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk /*!<Timestamp Day */
4032 #define FDCAN_CREL_MON_Pos (8U)
4033 #define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos) /*!< 0x0000FF00 */
4034 #define FDCAN_CREL_MON FDCAN_CREL_MON_Msk /*!<Timestamp Month */
4035 #define FDCAN_CREL_YEAR_Pos (16U)
4036 #define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos) /*!< 0x000F0000 */
4037 #define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk /*!<Timestamp Year */
4038 #define FDCAN_CREL_SUBSTEP_Pos (20U)
4039 #define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
4040 #define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
4041 #define FDCAN_CREL_STEP_Pos (24U)
4042 #define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos) /*!< 0x0F000000 */
4043 #define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk /*!<Step of Core release */
4044 #define FDCAN_CREL_REL_Pos (28U)
4045 #define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos) /*!< 0xF0000000 */
4046 #define FDCAN_CREL_REL FDCAN_CREL_REL_Msk /*!<Core release */
4047
4048 /***************** Bit definition for FDCAN_ENDN register *******************/
4049 #define FDCAN_ENDN_ETV_Pos (0U)
4050 #define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
4051 #define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
4052
4053 /***************** Bit definition for FDCAN_DBTP register *******************/
4054 #define FDCAN_DBTP_DSJW_Pos (0U)
4055 #define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos) /*!< 0x0000000F */
4056 #define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk /*!<Synchronization Jump Width */
4057 #define FDCAN_DBTP_DTSEG2_Pos (4U)
4058 #define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos) /*!< 0x000000F0 */
4059 #define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk /*!<Data time segment after sample point */
4060 #define FDCAN_DBTP_DTSEG1_Pos (8U)
4061 #define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos) /*!< 0x00001F00 */
4062 #define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk /*!<Data time segment before sample point */
4063 #define FDCAN_DBTP_DBRP_Pos (16U)
4064 #define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos) /*!< 0x001F0000 */
4065 #define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk /*!<Data BIt Rate Prescaler */
4066 #define FDCAN_DBTP_TDC_Pos (23U)
4067 #define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos) /*!< 0x00800000 */
4068 #define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk /*!<Transceiver Delay Compensation */
4069
4070 /***************** Bit definition for FDCAN_TEST register *******************/
4071 #define FDCAN_TEST_LBCK_Pos (4U)
4072 #define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos) /*!< 0x00000010 */
4073 #define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk /*!<Loop Back mode */
4074 #define FDCAN_TEST_TX_Pos (5U)
4075 #define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos) /*!< 0x00000060 */
4076 #define FDCAN_TEST_TX FDCAN_TEST_TX_Msk /*!<Control of Transmit Pin */
4077 #define FDCAN_TEST_RX_Pos (7U)
4078 #define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos) /*!< 0x00000080 */
4079 #define FDCAN_TEST_RX FDCAN_TEST_RX_Msk /*!<Receive Pin */
4080
4081 /***************** Bit definition for FDCAN_RWD register ********************/
4082 #define FDCAN_RWD_WDC_Pos (0U)
4083 #define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos) /*!< 0x000000FF */
4084 #define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk /*!<Watchdog configuration */
4085 #define FDCAN_RWD_WDV_Pos (8U)
4086 #define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos) /*!< 0x0000FF00 */
4087 #define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk /*!<Watchdog value */
4088
4089 /***************** Bit definition for FDCAN_CCCR register ********************/
4090 #define FDCAN_CCCR_INIT_Pos (0U)
4091 #define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos) /*!< 0x00000001 */
4092 #define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk /*!<Initialization */
4093 #define FDCAN_CCCR_CCE_Pos (1U)
4094 #define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos) /*!< 0x00000002 */
4095 #define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk /*!<Configuration Change Enable */
4096 #define FDCAN_CCCR_ASM_Pos (2U)
4097 #define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos) /*!< 0x00000004 */
4098 #define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk /*!<ASM Restricted Operation Mode */
4099 #define FDCAN_CCCR_CSA_Pos (3U)
4100 #define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos) /*!< 0x00000008 */
4101 #define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk /*!<Clock Stop Acknowledge */
4102 #define FDCAN_CCCR_CSR_Pos (4U)
4103 #define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos) /*!< 0x00000010 */
4104 #define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk /*!<Clock Stop Request */
4105 #define FDCAN_CCCR_MON_Pos (5U)
4106 #define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos) /*!< 0x00000020 */
4107 #define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk /*!<Bus Monitoring Mode */
4108 #define FDCAN_CCCR_DAR_Pos (6U)
4109 #define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos) /*!< 0x00000040 */
4110 #define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk /*!<Disable Automatic Retransmission */
4111 #define FDCAN_CCCR_TEST_Pos (7U)
4112 #define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos) /*!< 0x00000080 */
4113 #define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk /*!<Test Mode Enable */
4114 #define FDCAN_CCCR_FDOE_Pos (8U)
4115 #define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos) /*!< 0x00000100 */
4116 #define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk /*!<FD Operation Enable */
4117 #define FDCAN_CCCR_BRSE_Pos (9U)
4118 #define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos) /*!< 0x00000200 */
4119 #define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk /*!<FDCAN Bit Rate Switching */
4120 #define FDCAN_CCCR_PXHD_Pos (12U)
4121 #define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos) /*!< 0x00001000 */
4122 #define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk /*!<Protocol Exception Handling Disable */
4123 #define FDCAN_CCCR_EFBI_Pos (13U)
4124 #define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos) /*!< 0x00002000 */
4125 #define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk /*!<Edge Filtering during Bus Integration */
4126 #define FDCAN_CCCR_TXP_Pos (14U)
4127 #define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos) /*!< 0x00004000 */
4128 #define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk /*!<Two CAN bit times Pause */
4129 #define FDCAN_CCCR_NISO_Pos (15U)
4130 #define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos) /*!< 0x00008000 */
4131 #define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk /*!<Non ISO Operation */
4132
4133 /***************** Bit definition for FDCAN_NBTP register ********************/
4134 #define FDCAN_NBTP_NTSEG2_Pos (0U)
4135 #define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos) /*!< 0x0000007F */
4136 #define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk /*!<Nominal Time segment after sample point */
4137 #define FDCAN_NBTP_NTSEG1_Pos (8U)
4138 #define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos) /*!< 0x0000FF00 */
4139 #define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk /*!<Nominal Time segment before sample point */
4140 #define FDCAN_NBTP_NBRP_Pos (16U)
4141 #define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos) /*!< 0x01FF0000 */
4142 #define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk /*!<Bit Rate Prescaler */
4143 #define FDCAN_NBTP_NSJW_Pos (25U)
4144 #define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos) /*!< 0xFE000000 */
4145 #define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk /*!<Nominal (Re)Synchronization Jump Width */
4146
4147 /***************** Bit definition for FDCAN_TSCC register ********************/
4148 #define FDCAN_TSCC_TSS_Pos (0U)
4149 #define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos) /*!< 0x00000003 */
4150 #define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk /*!<Timestamp Select */
4151 #define FDCAN_TSCC_TCP_Pos (16U)
4152 #define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos) /*!< 0x000F0000 */
4153 #define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk /*!<Timestamp Counter Prescaler */
4154
4155 /***************** Bit definition for FDCAN_TSCV register ********************/
4156 #define FDCAN_TSCV_TSC_Pos (0U)
4157 #define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos) /*!< 0x0000FFFF */
4158 #define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk /*!<Timestamp Counter */
4159
4160 /***************** Bit definition for FDCAN_TOCC register ********************/
4161 #define FDCAN_TOCC_ETOC_Pos (0U)
4162 #define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos) /*!< 0x00000001 */
4163 #define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk /*!<Enable Timeout Counter */
4164 #define FDCAN_TOCC_TOS_Pos (1U)
4165 #define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos) /*!< 0x00000006 */
4166 #define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk /*!<Timeout Select */
4167 #define FDCAN_TOCC_TOP_Pos (16U)
4168 #define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos) /*!< 0xFFFF0000 */
4169 #define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk /*!<Timeout Period */
4170
4171 /***************** Bit definition for FDCAN_TOCV register ********************/
4172 #define FDCAN_TOCV_TOC_Pos (0U)
4173 #define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos) /*!< 0x0000FFFF */
4174 #define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk /*!<Timeout Counter */
4175
4176 /***************** Bit definition for FDCAN_ECR register *********************/
4177 #define FDCAN_ECR_TEC_Pos (0U)
4178 #define FDCAN_ECR_TEC_Msk (0xFFUL << FDCAN_ECR_TEC_Pos) /*!< 0x000000FF */
4179 #define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk /*!<Transmit Error Counter */
4180 #define FDCAN_ECR_REC_Pos (8U)
4181 #define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos) /*!< 0x00007F00 */
4182 #define FDCAN_ECR_REC FDCAN_ECR_REC_Msk /*!<Receive Error Counter */
4183 #define FDCAN_ECR_RP_Pos (15U)
4184 #define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos) /*!< 0x00008000 */
4185 #define FDCAN_ECR_RP FDCAN_ECR_RP_Msk /*!<Receive Error Passive */
4186 #define FDCAN_ECR_CEL_Pos (16U)
4187 #define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos) /*!< 0x00FF0000 */
4188 #define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk /*!<CAN Error Logging */
4189
4190 /***************** Bit definition for FDCAN_PSR register *********************/
4191 #define FDCAN_PSR_LEC_Pos (0U)
4192 #define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos) /*!< 0x00000007 */
4193 #define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk /*!<Last Error Code */
4194 #define FDCAN_PSR_ACT_Pos (3U)
4195 #define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos) /*!< 0x00000018 */
4196 #define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk /*!<Activity */
4197 #define FDCAN_PSR_EP_Pos (5U)
4198 #define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos) /*!< 0x00000020 */
4199 #define FDCAN_PSR_EP FDCAN_PSR_EP_Msk /*!<Error Passive */
4200 #define FDCAN_PSR_EW_Pos (6U)
4201 #define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos) /*!< 0x00000040 */
4202 #define FDCAN_PSR_EW FDCAN_PSR_EW_Msk /*!<Warning Status */
4203 #define FDCAN_PSR_BO_Pos (7U)
4204 #define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos) /*!< 0x00000080 */
4205 #define FDCAN_PSR_BO FDCAN_PSR_BO_Msk /*!<Bus_Off Status */
4206 #define FDCAN_PSR_DLEC_Pos (8U)
4207 #define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos) /*!< 0x00000700 */
4208 #define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk /*!<Data Last Error Code */
4209 #define FDCAN_PSR_RESI_Pos (11U)
4210 #define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos) /*!< 0x00000800 */
4211 #define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk /*!<ESI flag of last received FDCAN Message */
4212 #define FDCAN_PSR_RBRS_Pos (12U)
4213 #define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos) /*!< 0x00001000 */
4214 #define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk /*!<BRS flag of last received FDCAN Message */
4215 #define FDCAN_PSR_REDL_Pos (13U)
4216 #define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos) /*!< 0x00002000 */
4217 #define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk /*!<Received FDCAN Message */
4218 #define FDCAN_PSR_PXE_Pos (14U)
4219 #define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos) /*!< 0x00004000 */
4220 #define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk /*!<Protocol Exception Event */
4221 #define FDCAN_PSR_TDCV_Pos (16U)
4222 #define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos) /*!< 0x007F0000 */
4223 #define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk /*!<Transmitter Delay Compensation Value */
4224
4225 /***************** Bit definition for FDCAN_TDCR register ********************/
4226 #define FDCAN_TDCR_TDCF_Pos (0U)
4227 #define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos) /*!< 0x0000007F */
4228 #define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk /*!<Transmitter Delay Compensation Filter */
4229 #define FDCAN_TDCR_TDCO_Pos (8U)
4230 #define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos) /*!< 0x00007F00 */
4231 #define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk /*!<Transmitter Delay Compensation Offset */
4232
4233 /***************** Bit definition for FDCAN_IR register **********************/
4234 #define FDCAN_IR_RF0N_Pos (0U)
4235 #define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos) /*!< 0x00000001 */
4236 #define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk /*!<Rx FIFO 0 New Message */
4237 #define FDCAN_IR_RF0F_Pos (1U)
4238 #define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos) /*!< 0x00000002 */
4239 #define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk /*!<Rx FIFO 0 Full */
4240 #define FDCAN_IR_RF0L_Pos (2U)
4241 #define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos) /*!< 0x00000004 */
4242 #define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
4243 #define FDCAN_IR_RF1N_Pos (3U)
4244 #define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos) /*!< 0x00000008 */
4245 #define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk /*!<Rx FIFO 1 New Message */
4246 #define FDCAN_IR_RF1F_Pos (4U)
4247 #define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos) /*!< 0x00000010 */
4248 #define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk /*!<Rx FIFO 1 Full */
4249 #define FDCAN_IR_RF1L_Pos (5U)
4250 #define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos) /*!< 0x00000020 */
4251 #define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
4252 #define FDCAN_IR_HPM_Pos (6U)
4253 #define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos) /*!< 0x00000040 */
4254 #define FDCAN_IR_HPM FDCAN_IR_HPM_Msk /*!<High Priority Message */
4255 #define FDCAN_IR_TC_Pos (7U)
4256 #define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos) /*!< 0x00000080 */
4257 #define FDCAN_IR_TC FDCAN_IR_TC_Msk /*!<Transmission Completed */
4258 #define FDCAN_IR_TCF_Pos (8U)
4259 #define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos) /*!< 0x00000100 */
4260 #define FDCAN_IR_TCF FDCAN_IR_TCF_Msk /*!<Transmission Cancellation Finished */
4261 #define FDCAN_IR_TFE_Pos (9U)
4262 #define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos) /*!< 0x00000200 */
4263 #define FDCAN_IR_TFE FDCAN_IR_TFE_Msk /*!<Tx FIFO Empty */
4264 #define FDCAN_IR_TEFN_Pos (10U)
4265 #define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos) /*!< 0x00000400 */
4266 #define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk /*!<Tx Event FIFO New Entry */
4267 #define FDCAN_IR_TEFF_Pos (11U)
4268 #define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos) /*!< 0x00000800 */
4269 #define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk /*!<Tx Event FIFO Full */
4270 #define FDCAN_IR_TEFL_Pos (12U)
4271 #define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos) /*!< 0x00001000 */
4272 #define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk /*!<Tx Event FIFO Element Lost */
4273 #define FDCAN_IR_TSW_Pos (13U)
4274 #define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos) /*!< 0x00002000 */
4275 #define FDCAN_IR_TSW FDCAN_IR_TSW_Msk /*!<Timestamp Wraparound */
4276 #define FDCAN_IR_MRAF_Pos (14U)
4277 #define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos) /*!< 0x00004000 */
4278 #define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk /*!<Message RAM Access Failure */
4279 #define FDCAN_IR_TOO_Pos (15U)
4280 #define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos) /*!< 0x00008000 */
4281 #define FDCAN_IR_TOO FDCAN_IR_TOO_Msk /*!<Timeout Occurred */
4282 #define FDCAN_IR_ELO_Pos (16U)
4283 #define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos) /*!< 0x00010000 */
4284 #define FDCAN_IR_ELO FDCAN_IR_ELO_Msk /*!<Error Logging Overflow */
4285 #define FDCAN_IR_EP_Pos (17U)
4286 #define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos) /*!< 0x00020000 */
4287 #define FDCAN_IR_EP FDCAN_IR_EP_Msk /*!<Error Passive */
4288 #define FDCAN_IR_EW_Pos (18U)
4289 #define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos) /*!< 0x00040000 */
4290 #define FDCAN_IR_EW FDCAN_IR_EW_Msk /*!<Warning Status */
4291 #define FDCAN_IR_BO_Pos (19U)
4292 #define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos) /*!< 0x00080000 */
4293 #define FDCAN_IR_BO FDCAN_IR_BO_Msk /*!<Bus_Off Status */
4294 #define FDCAN_IR_WDI_Pos (20U)
4295 #define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos) /*!< 0x00100000 */
4296 #define FDCAN_IR_WDI FDCAN_IR_WDI_Msk /*!<Watchdog Interrupt */
4297 #define FDCAN_IR_PEA_Pos (21U)
4298 #define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos) /*!< 0x00200000 */
4299 #define FDCAN_IR_PEA FDCAN_IR_PEA_Msk /*!<Protocol Error in Arbitration Phase */
4300 #define FDCAN_IR_PED_Pos (22U)
4301 #define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos) /*!< 0x00400000 */
4302 #define FDCAN_IR_PED FDCAN_IR_PED_Msk /*!<Protocol Error in Data Phase */
4303 #define FDCAN_IR_ARA_Pos (23U)
4304 #define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos) /*!< 0x00800000 */
4305 #define FDCAN_IR_ARA FDCAN_IR_ARA_Msk /*!<Access to Reserved Address */
4306
4307 /***************** Bit definition for FDCAN_IE register **********************/
4308 #define FDCAN_IE_RF0NE_Pos (0U)
4309 #define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos) /*!< 0x00000001 */
4310 #define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk /*!<Rx FIFO 0 New Message Enable */
4311 #define FDCAN_IE_RF0FE_Pos (1U)
4312 #define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos) /*!< 0x00000002 */
4313 #define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk /*!<Rx FIFO 0 Full Enable */
4314 #define FDCAN_IE_RF0LE_Pos (2U)
4315 #define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos) /*!< 0x00000004 */
4316 #define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk /*!<Rx FIFO 0 Message Lost Enable */
4317 #define FDCAN_IE_RF1NE_Pos (3U)
4318 #define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos) /*!< 0x00000008 */
4319 #define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk /*!<Rx FIFO 1 New Message Enable */
4320 #define FDCAN_IE_RF1FE_Pos (4U)
4321 #define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos) /*!< 0x00000010 */
4322 #define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk /*!<Rx FIFO 1 Full Enable */
4323 #define FDCAN_IE_RF1LE_Pos (5U)
4324 #define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos) /*!< 0x00000020 */
4325 #define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk /*!<Rx FIFO 1 Message Lost Enable */
4326 #define FDCAN_IE_HPME_Pos (6U)
4327 #define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos) /*!< 0x00000040 */
4328 #define FDCAN_IE_HPME FDCAN_IE_HPME_Msk /*!<High Priority Message Enable */
4329 #define FDCAN_IE_TCE_Pos (7U)
4330 #define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos) /*!< 0x00000080 */
4331 #define FDCAN_IE_TCE FDCAN_IE_TCE_Msk /*!<Transmission Completed Enable */
4332 #define FDCAN_IE_TCFE_Pos (8U)
4333 #define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos) /*!< 0x00000100 */
4334 #define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk /*!<Transmission Cancellation Finished Enable*/
4335 #define FDCAN_IE_TFEE_Pos (9U)
4336 #define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos) /*!< 0x00000200 */
4337 #define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk /*!<Tx FIFO Empty Enable */
4338 #define FDCAN_IE_TEFNE_Pos (10U)
4339 #define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos) /*!< 0x00000400 */
4340 #define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk /*!<Tx Event FIFO New Entry Enable */
4341 #define FDCAN_IE_TEFFE_Pos (11U)
4342 #define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos) /*!< 0x00000800 */
4343 #define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk /*!<Tx Event FIFO Full Enable */
4344 #define FDCAN_IE_TEFLE_Pos (12U)
4345 #define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos) /*!< 0x00001000 */
4346 #define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk /*!<Tx Event FIFO Element Lost Enable */
4347 #define FDCAN_IE_TSWE_Pos (13U)
4348 #define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos) /*!< 0x00002000 */
4349 #define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk /*!<Timestamp Wraparound Enable */
4350 #define FDCAN_IE_MRAFE_Pos (14U)
4351 #define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos) /*!< 0x00004000 */
4352 #define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk /*!<Message RAM Access Failure Enable */
4353 #define FDCAN_IE_TOOE_Pos (15U)
4354 #define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos) /*!< 0x00008000 */
4355 #define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk /*!<Timeout Occurred Enable */
4356 #define FDCAN_IE_ELOE_Pos (16U)
4357 #define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos) /*!< 0x00010000 */
4358 #define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk /*!<Error Logging Overflow Enable */
4359 #define FDCAN_IE_EPE_Pos (17U)
4360 #define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos) /*!< 0x00020000 */
4361 #define FDCAN_IE_EPE FDCAN_IE_EPE_Msk /*!<Error Passive Enable */
4362 #define FDCAN_IE_EWE_Pos (18U)
4363 #define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos) /*!< 0x00040000 */
4364 #define FDCAN_IE_EWE FDCAN_IE_EWE_Msk /*!<Warning Status Enable */
4365 #define FDCAN_IE_BOE_Pos (19U)
4366 #define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos) /*!< 0x00080000 */
4367 #define FDCAN_IE_BOE FDCAN_IE_BOE_Msk /*!<Bus_Off Status Enable */
4368 #define FDCAN_IE_WDIE_Pos (20U)
4369 #define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos) /*!< 0x00100000 */
4370 #define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk /*!<Watchdog Interrupt Enable */
4371 #define FDCAN_IE_PEAE_Pos (21U)
4372 #define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos) /*!< 0x00200000 */
4373 #define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk /*!<Protocol Error in Arbitration Phase Enable*/
4374 #define FDCAN_IE_PEDE_Pos (22U)
4375 #define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos) /*!< 0x00400000 */
4376 #define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk /*!<Protocol Error in Data Phase Enable */
4377 #define FDCAN_IE_ARAE_Pos (23U)
4378 #define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos) /*!< 0x00800000 */
4379 #define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk /*!<Access to Reserved Address Enable */
4380
4381 /***************** Bit definition for FDCAN_ILS register **********************/
4382 #define FDCAN_ILS_RXFIFO0_Pos (0U)
4383 #define FDCAN_ILS_RXFIFO0_Msk (0x1UL << FDCAN_ILS_RXFIFO0_Pos) /*!< 0x00000001 */
4384 #define FDCAN_ILS_RXFIFO0 FDCAN_ILS_RXFIFO0_Msk /*!<Rx FIFO 0 Message Lost
4385 Rx FIFO 0 is Full
4386 Rx FIFO 0 Has New Message */
4387 #define FDCAN_ILS_RXFIFO1_Pos (1U)
4388 #define FDCAN_ILS_RXFIFO1_Msk (0x1UL << FDCAN_ILS_RXFIFO1_Pos) /*!< 0x00000002 */
4389 #define FDCAN_ILS_RXFIFO1 FDCAN_ILS_RXFIFO1_Msk /*!<Rx FIFO 1 Message Lost
4390 Rx FIFO 1 is Full
4391 Rx FIFO 1 Has New Message */
4392 #define FDCAN_ILS_SMSG_Pos (2U)
4393 #define FDCAN_ILS_SMSG_Msk (0x1UL << FDCAN_ILS_SMSG_Pos) /*!< 0x00000004 */
4394 #define FDCAN_ILS_SMSG FDCAN_ILS_SMSG_Msk /*!<Transmission Cancellation Finished
4395 Transmission Completed
4396 High Priority Message */
4397 #define FDCAN_ILS_TFERR_Pos (3U)
4398 #define FDCAN_ILS_TFERR_Msk (0x1UL << FDCAN_ILS_TFERR_Pos) /*!< 0x00000008 */
4399 #define FDCAN_ILS_TFERR FDCAN_ILS_TFERR_Msk /*!<Tx Event FIFO Element Lost
4400 Tx Event FIFO Full
4401 Tx Event FIFO New Entry
4402 Tx FIFO Empty Interrupt Line */
4403 #define FDCAN_ILS_MISC_Pos (4U)
4404 #define FDCAN_ILS_MISC_Msk (0x1UL << FDCAN_ILS_MISC_Pos) /*!< 0x00000010 */
4405 #define FDCAN_ILS_MISC FDCAN_ILS_MISC_Msk /*!<Timeout Occurred
4406 Message RAM Access Failure
4407 Timestamp Wraparound */
4408 #define FDCAN_ILS_BERR_Pos (5U)
4409 #define FDCAN_ILS_BERR_Msk (0x1UL << FDCAN_ILS_BERR_Pos) /*!< 0x00000020 */
4410 #define FDCAN_ILS_BERR FDCAN_ILS_BERR_Msk /*!<Error Passive
4411 Error Logging Overflow */
4412 #define FDCAN_ILS_PERR_Pos (6U)
4413 #define FDCAN_ILS_PERR_Msk (0x1UL << FDCAN_ILS_PERR_Pos) /*!< 0x00000040 */
4414 #define FDCAN_ILS_PERR FDCAN_ILS_PERR_Msk /*!<Access to Reserved Address Line
4415 Protocol Error in Data Phase Line
4416 Protocol Error in Arbitration Phase Line
4417 Watchdog Interrupt Line
4418 Bus_Off Status
4419 Warning Status */
4420
4421 /***************** Bit definition for FDCAN_ILE register **********************/
4422 #define FDCAN_ILE_EINT0_Pos (0U)
4423 #define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos) /*!< 0x00000001 */
4424 #define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk /*!<Enable Interrupt Line 0 */
4425 #define FDCAN_ILE_EINT1_Pos (1U)
4426 #define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos) /*!< 0x00000002 */
4427 #define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk /*!<Enable Interrupt Line 1 */
4428
4429 /***************** Bit definition for FDCAN_RXGFC register ********************/
4430 #define FDCAN_RXGFC_RRFE_Pos (0U)
4431 #define FDCAN_RXGFC_RRFE_Msk (0x1UL << FDCAN_RXGFC_RRFE_Pos) /*!< 0x00000001 */
4432 #define FDCAN_RXGFC_RRFE FDCAN_RXGFC_RRFE_Msk /*!<Reject Remote Frames Extended */
4433 #define FDCAN_RXGFC_RRFS_Pos (1U)
4434 #define FDCAN_RXGFC_RRFS_Msk (0x1UL << FDCAN_RXGFC_RRFS_Pos) /*!< 0x00000002 */
4435 #define FDCAN_RXGFC_RRFS FDCAN_RXGFC_RRFS_Msk /*!<Reject Remote Frames Standard */
4436 #define FDCAN_RXGFC_ANFE_Pos (2U)
4437 #define FDCAN_RXGFC_ANFE_Msk (0x3UL << FDCAN_RXGFC_ANFE_Pos) /*!< 0x0000000C */
4438 #define FDCAN_RXGFC_ANFE FDCAN_RXGFC_ANFE_Msk /*!<Accept Non-matching Frames Extended */
4439 #define FDCAN_RXGFC_ANFS_Pos (4U)
4440 #define FDCAN_RXGFC_ANFS_Msk (0x3UL << FDCAN_RXGFC_ANFS_Pos) /*!< 0x00000030 */
4441 #define FDCAN_RXGFC_ANFS FDCAN_RXGFC_ANFS_Msk /*!<Accept Non-matching Frames Standard */
4442 #define FDCAN_RXGFC_F1OM_Pos (8U)
4443 #define FDCAN_RXGFC_F1OM_Msk (0x1UL << FDCAN_RXGFC_F1OM_Pos) /*!< 0x00000100 */
4444 #define FDCAN_RXGFC_F1OM FDCAN_RXGFC_F1OM_Msk /*!<FIFO 1 operation mode */
4445 #define FDCAN_RXGFC_F0OM_Pos (9U)
4446 #define FDCAN_RXGFC_F0OM_Msk (0x1UL << FDCAN_RXGFC_F0OM_Pos) /*!< 0x00000200 */
4447 #define FDCAN_RXGFC_F0OM FDCAN_RXGFC_F0OM_Msk /*!<FIFO 0 operation mode */
4448 #define FDCAN_RXGFC_LSS_Pos (16U)
4449 #define FDCAN_RXGFC_LSS_Msk (0x1FUL << FDCAN_RXGFC_LSS_Pos) /*!< 0x001F0000 */
4450 #define FDCAN_RXGFC_LSS FDCAN_RXGFC_LSS_Msk /*!<List Size Standard */
4451 #define FDCAN_RXGFC_LSE_Pos (24U)
4452 #define FDCAN_RXGFC_LSE_Msk (0xFUL << FDCAN_RXGFC_LSE_Pos) /*!< 0x0F000000 */
4453 #define FDCAN_RXGFC_LSE FDCAN_RXGFC_LSE_Msk /*!<List Size Extended */
4454
4455 /***************** Bit definition for FDCAN_XIDAM register ********************/
4456 #define FDCAN_XIDAM_EIDM_Pos (0U)
4457 #define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos) /*!< 0x1FFFFFFF */
4458 #define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk /*!<Extended ID Mask */
4459
4460 /***************** Bit definition for FDCAN_HPMS register *********************/
4461 #define FDCAN_HPMS_BIDX_Pos (0U)
4462 #define FDCAN_HPMS_BIDX_Msk (0x7UL << FDCAN_HPMS_BIDX_Pos) /*!< 0x00000007 */
4463 #define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk /*!<Buffer Index */
4464 #define FDCAN_HPMS_MSI_Pos (6U)
4465 #define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos) /*!< 0x000000C0 */
4466 #define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk /*!<Message Storage Indicator */
4467 #define FDCAN_HPMS_FIDX_Pos (8U)
4468 #define FDCAN_HPMS_FIDX_Msk (0x1FUL << FDCAN_HPMS_FIDX_Pos) /*!< 0x00001F00 */
4469 #define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk /*!<Filter Index */
4470 #define FDCAN_HPMS_FLST_Pos (15U)
4471 #define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos) /*!< 0x00008000 */
4472 #define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk /*!<Filter List */
4473
4474 /***************** Bit definition for FDCAN_RXF0S register ********************/
4475 #define FDCAN_RXF0S_F0FL_Pos (0U)
4476 #define FDCAN_RXF0S_F0FL_Msk (0xFUL << FDCAN_RXF0S_F0FL_Pos) /*!< 0x0000000F */
4477 #define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk /*!<Rx FIFO 0 Fill Level */
4478 #define FDCAN_RXF0S_F0GI_Pos (8U)
4479 #define FDCAN_RXF0S_F0GI_Msk (0x3UL << FDCAN_RXF0S_F0GI_Pos) /*!< 0x00000300 */
4480 #define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk /*!<Rx FIFO 0 Get Index */
4481 #define FDCAN_RXF0S_F0PI_Pos (16U)
4482 #define FDCAN_RXF0S_F0PI_Msk (0x3UL << FDCAN_RXF0S_F0PI_Pos) /*!< 0x00030000 */
4483 #define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk /*!<Rx FIFO 0 Put Index */
4484 #define FDCAN_RXF0S_F0F_Pos (24U)
4485 #define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos) /*!< 0x01000000 */
4486 #define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk /*!<Rx FIFO 0 Full */
4487 #define FDCAN_RXF0S_RF0L_Pos (25U)
4488 #define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos) /*!< 0x02000000 */
4489 #define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
4490
4491 /***************** Bit definition for FDCAN_RXF0A register ********************/
4492 #define FDCAN_RXF0A_F0AI_Pos (0U)
4493 #define FDCAN_RXF0A_F0AI_Msk (0x7UL << FDCAN_RXF0A_F0AI_Pos) /*!< 0x00000007 */
4494 #define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk /*!<Rx FIFO 0 Acknowledge Index */
4495
4496 /***************** Bit definition for FDCAN_RXF1S register ********************/
4497 #define FDCAN_RXF1S_F1FL_Pos (0U)
4498 #define FDCAN_RXF1S_F1FL_Msk (0xFUL << FDCAN_RXF1S_F1FL_Pos) /*!< 0x0000000F */
4499 #define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk /*!<Rx FIFO 1 Fill Level */
4500 #define FDCAN_RXF1S_F1GI_Pos (8U)
4501 #define FDCAN_RXF1S_F1GI_Msk (0x3UL << FDCAN_RXF1S_F1GI_Pos) /*!< 0x00000300 */
4502 #define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk /*!<Rx FIFO 1 Get Index */
4503 #define FDCAN_RXF1S_F1PI_Pos (16U)
4504 #define FDCAN_RXF1S_F1PI_Msk (0x3UL << FDCAN_RXF1S_F1PI_Pos) /*!< 0x00030000 */
4505 #define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk /*!<Rx FIFO 1 Put Index */
4506 #define FDCAN_RXF1S_F1F_Pos (24U)
4507 #define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos) /*!< 0x01000000 */
4508 #define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk /*!<Rx FIFO 1 Full */
4509 #define FDCAN_RXF1S_RF1L_Pos (25U)
4510 #define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos) /*!< 0x02000000 */
4511 #define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
4512
4513 /***************** Bit definition for FDCAN_RXF1A register ********************/
4514 #define FDCAN_RXF1A_F1AI_Pos (0U)
4515 #define FDCAN_RXF1A_F1AI_Msk (0x7UL << FDCAN_RXF1A_F1AI_Pos) /*!< 0x00000007 */
4516 #define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk /*!<Rx FIFO 1 Acknowledge Index */
4517
4518 /***************** Bit definition for FDCAN_TXBC register *********************/
4519 #define FDCAN_TXBC_TFQM_Pos (24U)
4520 #define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos) /*!< 0x01000000 */
4521 #define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk /*!<Tx FIFO/Queue Mode */
4522
4523 /***************** Bit definition for FDCAN_TXFQS register *********************/
4524 #define FDCAN_TXFQS_TFFL_Pos (0U)
4525 #define FDCAN_TXFQS_TFFL_Msk (0x7UL << FDCAN_TXFQS_TFFL_Pos) /*!< 0x00000007 */
4526 #define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk /*!<Tx FIFO Free Level */
4527 #define FDCAN_TXFQS_TFGI_Pos (8U)
4528 #define FDCAN_TXFQS_TFGI_Msk (0x3UL << FDCAN_TXFQS_TFGI_Pos) /*!< 0x00000300 */
4529 #define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk /*!<Tx FIFO Get Index */
4530 #define FDCAN_TXFQS_TFQPI_Pos (16U)
4531 #define FDCAN_TXFQS_TFQPI_Msk (0x3UL << FDCAN_TXFQS_TFQPI_Pos) /*!< 0x00030000 */
4532 #define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk /*!<Tx FIFO/Queue Put Index */
4533 #define FDCAN_TXFQS_TFQF_Pos (21U)
4534 #define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos) /*!< 0x00200000 */
4535 #define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk /*!<Tx FIFO/Queue Full */
4536
4537 /***************** Bit definition for FDCAN_TXBRP register *********************/
4538 #define FDCAN_TXBRP_TRP_Pos (0U)
4539 #define FDCAN_TXBRP_TRP_Msk (0x7UL << FDCAN_TXBRP_TRP_Pos) /*!< 0x00000007 */
4540 #define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk /*!<Transmission Request Pending */
4541
4542 /***************** Bit definition for FDCAN_TXBAR register *********************/
4543 #define FDCAN_TXBAR_AR_Pos (0U)
4544 #define FDCAN_TXBAR_AR_Msk (0x7UL << FDCAN_TXBAR_AR_Pos) /*!< 0x00000007 */
4545 #define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk /*!<Add Request */
4546
4547 /***************** Bit definition for FDCAN_TXBCR register *********************/
4548 #define FDCAN_TXBCR_CR_Pos (0U)
4549 #define FDCAN_TXBCR_CR_Msk (0x7UL << FDCAN_TXBCR_CR_Pos) /*!< 0x00000007 */
4550 #define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk /*!<Cancellation Request */
4551
4552 /***************** Bit definition for FDCAN_TXBTO register *********************/
4553 #define FDCAN_TXBTO_TO_Pos (0U)
4554 #define FDCAN_TXBTO_TO_Msk (0x7UL << FDCAN_TXBTO_TO_Pos) /*!< 0x00000007 */
4555 #define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk /*!<Transmission Occurred */
4556
4557 /***************** Bit definition for FDCAN_TXBCF register *********************/
4558 #define FDCAN_TXBCF_CF_Pos (0U)
4559 #define FDCAN_TXBCF_CF_Msk (0x7UL << FDCAN_TXBCF_CF_Pos) /*!< 0x00000007 */
4560 #define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk /*!<Cancellation Finished */
4561
4562 /***************** Bit definition for FDCAN_TXBTIE register ********************/
4563 #define FDCAN_TXBTIE_TIE_Pos (0U)
4564 #define FDCAN_TXBTIE_TIE_Msk (0x7UL << FDCAN_TXBTIE_TIE_Pos) /*!< 0x00000007 */
4565 #define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk /*!<Transmission Interrupt Enable */
4566
4567 /***************** Bit definition for FDCAN_ TXBCIE register *******************/
4568 #define FDCAN_TXBCIE_CFIE_Pos (0U)
4569 #define FDCAN_TXBCIE_CFIE_Msk (0x7UL << FDCAN_TXBCIE_CFIE_Pos) /*!< 0x00000007 */
4570 #define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk /*!<Cancellation Finished Interrupt Enable */
4571
4572 /***************** Bit definition for FDCAN_TXEFS register *********************/
4573 #define FDCAN_TXEFS_EFFL_Pos (0U)
4574 #define FDCAN_TXEFS_EFFL_Msk (0x7UL << FDCAN_TXEFS_EFFL_Pos) /*!< 0x00000007 */
4575 #define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk /*!<Event FIFO Fill Level */
4576 #define FDCAN_TXEFS_EFGI_Pos (8U)
4577 #define FDCAN_TXEFS_EFGI_Msk (0x3UL << FDCAN_TXEFS_EFGI_Pos) /*!< 0x00000300 */
4578 #define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk /*!<Event FIFO Get Index */
4579 #define FDCAN_TXEFS_EFPI_Pos (16U)
4580 #define FDCAN_TXEFS_EFPI_Msk (0x3UL << FDCAN_TXEFS_EFPI_Pos) /*!< 0x00030000 */
4581 #define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk /*!<Event FIFO Put Index */
4582 #define FDCAN_TXEFS_EFF_Pos (24U)
4583 #define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos) /*!< 0x01000000 */
4584 #define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk /*!<Event FIFO Full */
4585 #define FDCAN_TXEFS_TEFL_Pos (25U)
4586 #define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos) /*!< 0x02000000 */
4587 #define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk /*!<Tx Event FIFO Element Lost */
4588
4589 /***************** Bit definition for FDCAN_TXEFA register *********************/
4590 #define FDCAN_TXEFA_EFAI_Pos (0U)
4591 #define FDCAN_TXEFA_EFAI_Msk (0x3UL << FDCAN_TXEFA_EFAI_Pos) /*!< 0x00000003 */
4592 #define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk /*!<Event FIFO Acknowledge Index */
4593
4594
4595 /*!<FDCAN config registers */
4596 /***************** Bit definition for FDCAN_CKDIV register *********************/
4597 #define FDCAN_CKDIV_PDIV_Pos (0U)
4598 #define FDCAN_CKDIV_PDIV_Msk (0xFUL << FDCAN_CKDIV_PDIV_Pos) /*!< 0x0000000F */
4599 #define FDCAN_CKDIV_PDIV FDCAN_CKDIV_PDIV_Msk /*!<Input Clock Divider */
4600
4601 /******************************************************************************/
4602 /* */
4603 /* FLASH */
4604 /* */
4605 /******************************************************************************/
4606 /******************* Bits definition for FLASH_ACR register *****************/
4607 #define FLASH_ACR_LATENCY_Pos (0U)
4608 #define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
4609 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
4610 #define FLASH_ACR_LATENCY_0WS (0x00000000U)
4611 #define FLASH_ACR_LATENCY_1WS (0x00000001U)
4612 #define FLASH_ACR_LATENCY_2WS (0x00000002U)
4613 #define FLASH_ACR_LATENCY_3WS (0x00000003U)
4614 #define FLASH_ACR_LATENCY_4WS (0x00000004U)
4615 #define FLASH_ACR_LATENCY_5WS (0x00000005U)
4616 #define FLASH_ACR_LATENCY_6WS (0x00000006U)
4617 #define FLASH_ACR_LATENCY_7WS (0x00000007U)
4618 #define FLASH_ACR_LATENCY_8WS (0x00000008U)
4619 #define FLASH_ACR_LATENCY_9WS (0x00000009U)
4620 #define FLASH_ACR_LATENCY_10WS (0x0000000AU)
4621 #define FLASH_ACR_LATENCY_11WS (0x0000000BU)
4622 #define FLASH_ACR_LATENCY_12WS (0x0000000CU)
4623 #define FLASH_ACR_LATENCY_13WS (0x0000000DU)
4624 #define FLASH_ACR_LATENCY_14WS (0x0000000EU)
4625 #define FLASH_ACR_LATENCY_15WS (0x0000000FU)
4626 #define FLASH_ACR_PRFTEN_Pos (8U)
4627 #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
4628 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
4629 #define FLASH_ACR_ICEN_Pos (9U)
4630 #define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
4631 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
4632 #define FLASH_ACR_DCEN_Pos (10U)
4633 #define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
4634 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
4635 #define FLASH_ACR_ICRST_Pos (11U)
4636 #define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
4637 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
4638 #define FLASH_ACR_DCRST_Pos (12U)
4639 #define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
4640 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
4641 #define FLASH_ACR_RUN_PD_Pos (13U)
4642 #define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00002000 */
4643 #define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash power down mode during run */
4644 #define FLASH_ACR_SLEEP_PD_Pos (14U)
4645 #define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */
4646 #define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power down mode during sleep */
4647 #define FLASH_ACR_DBG_SWEN_Pos (18U)
4648 #define FLASH_ACR_DBG_SWEN_Msk (0x1UL << FLASH_ACR_DBG_SWEN_Pos) /*!< 0x00040000 */
4649 #define FLASH_ACR_DBG_SWEN FLASH_ACR_DBG_SWEN_Msk /*!< Software disable for debugger */
4650
4651 /******************* Bits definition for FLASH_SR register ******************/
4652 #define FLASH_SR_EOP_Pos (0U)
4653 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
4654 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
4655 #define FLASH_SR_OPERR_Pos (1U)
4656 #define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
4657 #define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
4658 #define FLASH_SR_PROGERR_Pos (3U)
4659 #define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */
4660 #define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
4661 #define FLASH_SR_WRPERR_Pos (4U)
4662 #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
4663 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
4664 #define FLASH_SR_PGAERR_Pos (5U)
4665 #define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
4666 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
4667 #define FLASH_SR_SIZERR_Pos (6U)
4668 #define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */
4669 #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
4670 #define FLASH_SR_PGSERR_Pos (7U)
4671 #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
4672 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
4673 #define FLASH_SR_MISERR_Pos (8U)
4674 #define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */
4675 #define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
4676 #define FLASH_SR_FASTERR_Pos (9U)
4677 #define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */
4678 #define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
4679 #define FLASH_SR_RDERR_Pos (14U)
4680 #define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */
4681 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
4682 #define FLASH_SR_OPTVERR_Pos (15U)
4683 #define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */
4684 #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
4685 #define FLASH_SR_BSY_Pos (16U)
4686 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
4687 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
4688
4689 /******************* Bits definition for FLASH_CR register ******************/
4690 #define FLASH_CR_PG_Pos (0U)
4691 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */
4692 #define FLASH_CR_PG FLASH_CR_PG_Msk
4693 #define FLASH_CR_PER_Pos (1U)
4694 #define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */
4695 #define FLASH_CR_PER FLASH_CR_PER_Msk
4696 #define FLASH_CR_MER1_Pos (2U)
4697 #define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
4698 #define FLASH_CR_MER1 FLASH_CR_MER1_Msk
4699 #define FLASH_CR_PNB_Pos (3U)
4700 #define FLASH_CR_PNB_Msk (0x3FUL << FLASH_CR_PNB_Pos) /*!< 0x000001F8 */
4701 #define FLASH_CR_PNB FLASH_CR_PNB_Msk
4702 #define FLASH_CR_STRT_Pos (16U)
4703 #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
4704 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
4705 #define FLASH_CR_OPTSTRT_Pos (17U)
4706 #define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
4707 #define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
4708 #define FLASH_CR_FSTPG_Pos (18U)
4709 #define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
4710 #define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
4711 #define FLASH_CR_EOPIE_Pos (24U)
4712 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
4713 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
4714 #define FLASH_CR_ERRIE_Pos (25U)
4715 #define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
4716 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
4717 #define FLASH_CR_RDERRIE_Pos (26U)
4718 #define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */
4719 #define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
4720 #define FLASH_CR_OBL_LAUNCH_Pos (27U)
4721 #define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
4722 #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
4723 #define FLASH_CR_SEC_PROT1_Pos (28U)
4724 #define FLASH_CR_SEC_PROT1_Msk (0x1UL << FLASH_CR_SEC_PROT1_Pos) /*!< 0x10000000 */
4725 #define FLASH_CR_SEC_PROT1 FLASH_CR_SEC_PROT1_Msk
4726 #define FLASH_CR_OPTLOCK_Pos (30U)
4727 #define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
4728 #define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
4729 #define FLASH_CR_LOCK_Pos (31U)
4730 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
4731 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
4732
4733 /******************* Bits definition for FLASH_ECCR register ***************/
4734 #define FLASH_ECCR_ADDR_ECC_Pos (0U)
4735 #define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFFUL << FLASH_ECCR_ADDR_ECC_Pos)/*!< 0x0003FFFF */
4736 #define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
4737 #define FLASH_ECCR_SYSF_ECC_Pos (22U)
4738 #define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */
4739 #define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
4740 #define FLASH_ECCR_ECCIE_Pos (24U)
4741 #define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */
4742 #define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk
4743 #define FLASH_ECCR_ECCC_Pos (30U)
4744 #define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
4745 #define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
4746 #define FLASH_ECCR_ECCD_Pos (31U)
4747 #define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
4748 #define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
4749
4750 /******************* Bits definition for FLASH_OPTR register ***************/
4751 #define FLASH_OPTR_RDP_Pos (0U)
4752 #define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
4753 #define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
4754 #define FLASH_OPTR_BOR_LEV_Pos (8U)
4755 #define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */
4756 #define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk
4757 #define FLASH_OPTR_BOR_LEV_0 (0x0UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000000 */
4758 #define FLASH_OPTR_BOR_LEV_1 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */
4759 #define FLASH_OPTR_BOR_LEV_2 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */
4760 #define FLASH_OPTR_BOR_LEV_3 (0x3UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000300 */
4761 #define FLASH_OPTR_BOR_LEV_4 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */
4762 #define FLASH_OPTR_nRST_STOP_Pos (12U)
4763 #define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */
4764 #define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
4765 #define FLASH_OPTR_nRST_STDBY_Pos (13U)
4766 #define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
4767 #define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
4768 #define FLASH_OPTR_nRST_SHDW_Pos (14U)
4769 #define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */
4770 #define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
4771 #define FLASH_OPTR_IWDG_SW_Pos (16U)
4772 #define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
4773 #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
4774 #define FLASH_OPTR_IWDG_STOP_Pos (17U)
4775 #define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
4776 #define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
4777 #define FLASH_OPTR_IWDG_STDBY_Pos (18U)
4778 #define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
4779 #define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
4780 #define FLASH_OPTR_WWDG_SW_Pos (19U)
4781 #define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
4782 #define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
4783 #define FLASH_OPTR_nBOOT1_Pos (23U)
4784 #define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */
4785 #define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
4786 #define FLASH_OPTR_SRAM_PE_Pos (24U)
4787 #define FLASH_OPTR_SRAM_PE_Msk (0x1UL << FLASH_OPTR_SRAM_PE_Pos) /*!< 0x01000000 */
4788 #define FLASH_OPTR_SRAM_PE FLASH_OPTR_SRAM_PE_Msk
4789 #define FLASH_OPTR_CCMSRAM_RST_Pos (25U)
4790 #define FLASH_OPTR_CCMSRAM_RST_Msk (0x1UL << FLASH_OPTR_CCMSRAM_RST_Pos)/*!< 0x02000000 */
4791 #define FLASH_OPTR_CCMSRAM_RST FLASH_OPTR_CCMSRAM_RST_Msk
4792 #define FLASH_OPTR_nSWBOOT0_Pos (26U)
4793 #define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */
4794 #define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk
4795 #define FLASH_OPTR_nBOOT0_Pos (27U)
4796 #define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */
4797 #define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk
4798 #define FLASH_OPTR_NRST_MODE_Pos (28U)
4799 #define FLASH_OPTR_NRST_MODE_Msk (0x3UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x30000000 */
4800 #define FLASH_OPTR_NRST_MODE FLASH_OPTR_NRST_MODE_Msk
4801 #define FLASH_OPTR_NRST_MODE_0 (0x1UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x10000000 */
4802 #define FLASH_OPTR_NRST_MODE_1 (0x2UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x20000000 */
4803 #define FLASH_OPTR_IRHEN_Pos (30U)
4804 #define FLASH_OPTR_IRHEN_Msk (0x1UL << FLASH_OPTR_IRHEN_Pos) /*!< 0x40000000 */
4805 #define FLASH_OPTR_IRHEN FLASH_OPTR_IRHEN_Msk
4806
4807 /****************** Bits definition for FLASH_PCROP1SR register **********/
4808 #define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U)
4809 #define FLASH_PCROP1SR_PCROP1_STRT_Msk (0x3FFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos)/*!< 0x00003FFF */
4810 #define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk
4811
4812 /****************** Bits definition for FLASH_PCROP1ER register ***********/
4813 #define FLASH_PCROP1ER_PCROP1_END_Pos (0U)
4814 #define FLASH_PCROP1ER_PCROP1_END_Msk (0x3FFFUL << FLASH_PCROP1ER_PCROP1_END_Pos)/*!< 0x00003FFF */
4815 #define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk
4816 #define FLASH_PCROP1ER_PCROP_RDP_Pos (31U)
4817 #define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos)/*!< 0x80000000 */
4818 #define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk
4819
4820 /****************** Bits definition for FLASH_WRP1AR register ***************/
4821 #define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
4822 #define FLASH_WRP1AR_WRP1A_STRT_Msk (0x3FUL << FLASH_WRP1AR_WRP1A_STRT_Pos)/*!< 0x0000003F */
4823 #define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
4824 #define FLASH_WRP1AR_WRP1A_END_Pos (16U)
4825 #define FLASH_WRP1AR_WRP1A_END_Msk (0x3FUL << FLASH_WRP1AR_WRP1A_END_Pos)/*!< 0x003F0000 */
4826 #define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
4827
4828 /****************** Bits definition for FLASH_WRPB1R register ***************/
4829 #define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
4830 #define FLASH_WRP1BR_WRP1B_STRT_Msk (0x3FUL << FLASH_WRP1BR_WRP1B_STRT_Pos)/*!< 0x0000003F */
4831 #define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
4832 #define FLASH_WRP1BR_WRP1B_END_Pos (16U)
4833 #define FLASH_WRP1BR_WRP1B_END_Msk (0x3FUL << FLASH_WRP1BR_WRP1B_END_Pos)/*!< 0x003F0000 */
4834 #define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
4835
4836
4837 /****************** Bits definition for FLASH_SEC1R register **************/
4838 #define FLASH_SEC1R_SEC_SIZE1_Pos (0U)
4839 #define FLASH_SEC1R_SEC_SIZE1_Msk (0x7FUL << FLASH_SEC1R_SEC_SIZE1_Pos)/*!< 0x0000007F */
4840 #define FLASH_SEC1R_SEC_SIZE1 FLASH_SEC1R_SEC_SIZE1_Msk
4841 #define FLASH_SEC1R_BOOT_LOCK_Pos (16U)
4842 #define FLASH_SEC1R_BOOT_LOCK_Msk (0x1UL << FLASH_SEC1R_BOOT_LOCK_Pos)/*!< 0x00010000 */
4843 #define FLASH_SEC1R_BOOT_LOCK FLASH_SEC1R_BOOT_LOCK_Msk
4844
4845
4846 /******************************************************************************/
4847 /* */
4848 /* Filter Mathematical ACcelerator unit (FMAC) */
4849 /* */
4850 /******************************************************************************/
4851 /***************** Bit definition for FMAC_X1BUFCFG register ****************/
4852 #define FMAC_X1BUFCFG_X1_BASE_Pos (0U)
4853 #define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */
4854 #define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */
4855 #define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U)
4856 #define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos)/*!< 0x0000FF00 */
4857 #define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */
4858 #define FMAC_X1BUFCFG_FULL_WM_Pos (24U)
4859 #define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */
4860 #define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */
4861 /***************** Bit definition for FMAC_X2BUFCFG register ****************/
4862 #define FMAC_X2BUFCFG_X2_BASE_Pos (0U)
4863 #define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */
4864 #define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */
4865 #define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U)
4866 #define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos)/*!< 0x0000FF00 */
4867 #define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */
4868 /***************** Bit definition for FMAC_YBUFCFG register *****************/
4869 #define FMAC_YBUFCFG_Y_BASE_Pos (0U)
4870 #define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */
4871 #define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */
4872 #define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8U)
4873 #define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */
4874 #define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */
4875 #define FMAC_YBUFCFG_EMPTY_WM_Pos (24U)
4876 #define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */
4877 #define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */
4878 /****************** Bit definition for FMAC_PARAM register ******************/
4879 #define FMAC_PARAM_P_Pos (0U)
4880 #define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */
4881 #define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */
4882 #define FMAC_PARAM_Q_Pos (8U)
4883 #define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */
4884 #define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */
4885 #define FMAC_PARAM_R_Pos (16U)
4886 #define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */
4887 #define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */
4888 #define FMAC_PARAM_FUNC_Pos (24U)
4889 #define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */
4890 #define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */
4891 #define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */
4892 #define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */
4893 #define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */
4894 #define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */
4895 #define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */
4896 #define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */
4897 #define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */
4898 #define FMAC_PARAM_START_Pos (31U)
4899 #define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */
4900 #define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */
4901 /******************** Bit definition for FMAC_CR register *******************/
4902 #define FMAC_CR_RIEN_Pos (0U)
4903 #define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */
4904 #define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */
4905 #define FMAC_CR_WIEN_Pos (1U)
4906 #define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */
4907 #define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */
4908 #define FMAC_CR_OVFLIEN_Pos (2U)
4909 #define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */
4910 #define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */
4911 #define FMAC_CR_UNFLIEN_Pos (3U)
4912 #define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */
4913 #define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */
4914 #define FMAC_CR_SATIEN_Pos (4U)
4915 #define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */
4916 #define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */
4917 #define FMAC_CR_DMAREN_Pos (8U)
4918 #define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */
4919 #define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */
4920 #define FMAC_CR_DMAWEN_Pos (9U)
4921 #define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */
4922 #define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */
4923 #define FMAC_CR_CLIPEN_Pos (15U)
4924 #define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */
4925 #define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */
4926 #define FMAC_CR_RESET_Pos (16U)
4927 #define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */
4928 #define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */
4929 /******************* Bit definition for FMAC_SR register ********************/
4930 #define FMAC_SR_YEMPTY_Pos (0U)
4931 #define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */
4932 #define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */
4933 #define FMAC_SR_X1FULL_Pos (1U)
4934 #define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */
4935 #define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */
4936 #define FMAC_SR_OVFL_Pos (8U)
4937 #define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */
4938 #define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */
4939 #define FMAC_SR_UNFL_Pos (9U)
4940 #define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */
4941 #define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */
4942 #define FMAC_SR_SAT_Pos (10U)
4943 #define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */
4944 #define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */
4945 /****************** Bit definition for FMAC_WDATA register ******************/
4946 #define FMAC_WDATA_WDATA_Pos (0U)
4947 #define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */
4948 #define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */
4949 /****************** Bit definition for FMACX_RDATA register *****************/
4950 #define FMAC_RDATA_RDATA_Pos (0U)
4951 #define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */
4952 #define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */
4953
4954
4955 /******************************************************************************/
4956 /* */
4957 /* General Purpose IOs (GPIO) */
4958 /* */
4959 /******************************************************************************/
4960 /****************** Bits definition for GPIO_MODER register *****************/
4961 #define GPIO_MODER_MODE0_Pos (0U)
4962 #define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
4963 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
4964 #define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
4965 #define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
4966 #define GPIO_MODER_MODE1_Pos (2U)
4967 #define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
4968 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
4969 #define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
4970 #define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
4971 #define GPIO_MODER_MODE2_Pos (4U)
4972 #define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
4973 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
4974 #define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
4975 #define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
4976 #define GPIO_MODER_MODE3_Pos (6U)
4977 #define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
4978 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
4979 #define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
4980 #define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
4981 #define GPIO_MODER_MODE4_Pos (8U)
4982 #define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
4983 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
4984 #define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
4985 #define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
4986 #define GPIO_MODER_MODE5_Pos (10U)
4987 #define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
4988 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
4989 #define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
4990 #define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
4991 #define GPIO_MODER_MODE6_Pos (12U)
4992 #define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
4993 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
4994 #define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
4995 #define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
4996 #define GPIO_MODER_MODE7_Pos (14U)
4997 #define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
4998 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
4999 #define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
5000 #define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
5001 #define GPIO_MODER_MODE8_Pos (16U)
5002 #define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
5003 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
5004 #define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
5005 #define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
5006 #define GPIO_MODER_MODE9_Pos (18U)
5007 #define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
5008 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
5009 #define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
5010 #define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
5011 #define GPIO_MODER_MODE10_Pos (20U)
5012 #define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
5013 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
5014 #define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
5015 #define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
5016 #define GPIO_MODER_MODE11_Pos (22U)
5017 #define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
5018 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
5019 #define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
5020 #define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
5021 #define GPIO_MODER_MODE12_Pos (24U)
5022 #define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
5023 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
5024 #define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
5025 #define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
5026 #define GPIO_MODER_MODE13_Pos (26U)
5027 #define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
5028 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
5029 #define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
5030 #define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
5031 #define GPIO_MODER_MODE14_Pos (28U)
5032 #define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
5033 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
5034 #define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
5035 #define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
5036 #define GPIO_MODER_MODE15_Pos (30U)
5037 #define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
5038 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
5039 #define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
5040 #define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
5041
5042 /* Legacy defines */
5043 #define GPIO_MODER_MODER0 GPIO_MODER_MODE0
5044 #define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
5045 #define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
5046 #define GPIO_MODER_MODER1 GPIO_MODER_MODE1
5047 #define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
5048 #define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
5049 #define GPIO_MODER_MODER2 GPIO_MODER_MODE2
5050 #define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
5051 #define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
5052 #define GPIO_MODER_MODER3 GPIO_MODER_MODE3
5053 #define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
5054 #define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
5055 #define GPIO_MODER_MODER4 GPIO_MODER_MODE4
5056 #define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
5057 #define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
5058 #define GPIO_MODER_MODER5 GPIO_MODER_MODE5
5059 #define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
5060 #define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
5061 #define GPIO_MODER_MODER6 GPIO_MODER_MODE6
5062 #define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
5063 #define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
5064 #define GPIO_MODER_MODER7 GPIO_MODER_MODE7
5065 #define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
5066 #define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
5067 #define GPIO_MODER_MODER8 GPIO_MODER_MODE8
5068 #define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
5069 #define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
5070 #define GPIO_MODER_MODER9 GPIO_MODER_MODE9
5071 #define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
5072 #define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
5073 #define GPIO_MODER_MODER10 GPIO_MODER_MODE10
5074 #define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
5075 #define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
5076 #define GPIO_MODER_MODER11 GPIO_MODER_MODE11
5077 #define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
5078 #define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
5079 #define GPIO_MODER_MODER12 GPIO_MODER_MODE12
5080 #define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
5081 #define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
5082 #define GPIO_MODER_MODER13 GPIO_MODER_MODE13
5083 #define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
5084 #define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
5085 #define GPIO_MODER_MODER14 GPIO_MODER_MODE14
5086 #define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
5087 #define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
5088 #define GPIO_MODER_MODER15 GPIO_MODER_MODE15
5089 #define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
5090 #define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
5091
5092 /****************** Bits definition for GPIO_OTYPER register ****************/
5093 #define GPIO_OTYPER_OT0_Pos (0U)
5094 #define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
5095 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
5096 #define GPIO_OTYPER_OT1_Pos (1U)
5097 #define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
5098 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
5099 #define GPIO_OTYPER_OT2_Pos (2U)
5100 #define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
5101 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
5102 #define GPIO_OTYPER_OT3_Pos (3U)
5103 #define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
5104 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
5105 #define GPIO_OTYPER_OT4_Pos (4U)
5106 #define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
5107 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
5108 #define GPIO_OTYPER_OT5_Pos (5U)
5109 #define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
5110 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
5111 #define GPIO_OTYPER_OT6_Pos (6U)
5112 #define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
5113 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
5114 #define GPIO_OTYPER_OT7_Pos (7U)
5115 #define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
5116 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
5117 #define GPIO_OTYPER_OT8_Pos (8U)
5118 #define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
5119 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
5120 #define GPIO_OTYPER_OT9_Pos (9U)
5121 #define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
5122 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
5123 #define GPIO_OTYPER_OT10_Pos (10U)
5124 #define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
5125 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
5126 #define GPIO_OTYPER_OT11_Pos (11U)
5127 #define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
5128 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
5129 #define GPIO_OTYPER_OT12_Pos (12U)
5130 #define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
5131 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
5132 #define GPIO_OTYPER_OT13_Pos (13U)
5133 #define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
5134 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
5135 #define GPIO_OTYPER_OT14_Pos (14U)
5136 #define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
5137 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
5138 #define GPIO_OTYPER_OT15_Pos (15U)
5139 #define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
5140 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
5141
5142 /* Legacy defines */
5143 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
5144 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
5145 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
5146 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
5147 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
5148 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
5149 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
5150 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
5151 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
5152 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
5153 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
5154 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
5155 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
5156 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
5157 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
5158 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
5159
5160 /****************** Bits definition for GPIO_OSPEEDR register ***************/
5161 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
5162 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
5163 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
5164 #define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
5165 #define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
5166 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
5167 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
5168 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
5169 #define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
5170 #define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
5171 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
5172 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
5173 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
5174 #define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
5175 #define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
5176 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
5177 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
5178 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
5179 #define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
5180 #define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
5181 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
5182 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
5183 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
5184 #define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
5185 #define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
5186 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
5187 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
5188 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
5189 #define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
5190 #define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
5191 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
5192 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
5193 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
5194 #define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
5195 #define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
5196 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
5197 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
5198 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
5199 #define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
5200 #define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
5201 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
5202 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
5203 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
5204 #define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
5205 #define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
5206 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
5207 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
5208 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
5209 #define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
5210 #define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
5211 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
5212 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
5213 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
5214 #define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
5215 #define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
5216 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
5217 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
5218 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
5219 #define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
5220 #define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
5221 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
5222 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
5223 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
5224 #define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
5225 #define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
5226 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
5227 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
5228 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
5229 #define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
5230 #define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
5231 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
5232 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
5233 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
5234 #define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
5235 #define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
5236 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
5237 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
5238 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
5239 #define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
5240 #define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
5241
5242 /* Legacy defines */
5243 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
5244 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
5245 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
5246 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
5247 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
5248 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
5249 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
5250 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
5251 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
5252 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
5253 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
5254 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
5255 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
5256 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
5257 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
5258 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
5259 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
5260 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
5261 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
5262 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
5263 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
5264 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
5265 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
5266 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
5267 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
5268 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
5269 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
5270 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
5271 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
5272 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
5273 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
5274 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
5275 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
5276 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
5277 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
5278 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
5279 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
5280 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
5281 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
5282 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
5283 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
5284 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
5285 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
5286 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
5287 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
5288 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
5289 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
5290 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
5291
5292 /****************** Bits definition for GPIO_PUPDR register *****************/
5293 #define GPIO_PUPDR_PUPD0_Pos (0U)
5294 #define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
5295 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
5296 #define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
5297 #define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
5298 #define GPIO_PUPDR_PUPD1_Pos (2U)
5299 #define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
5300 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
5301 #define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
5302 #define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
5303 #define GPIO_PUPDR_PUPD2_Pos (4U)
5304 #define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
5305 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
5306 #define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
5307 #define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
5308 #define GPIO_PUPDR_PUPD3_Pos (6U)
5309 #define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
5310 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
5311 #define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
5312 #define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
5313 #define GPIO_PUPDR_PUPD4_Pos (8U)
5314 #define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
5315 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
5316 #define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
5317 #define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
5318 #define GPIO_PUPDR_PUPD5_Pos (10U)
5319 #define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
5320 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
5321 #define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
5322 #define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
5323 #define GPIO_PUPDR_PUPD6_Pos (12U)
5324 #define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
5325 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
5326 #define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
5327 #define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
5328 #define GPIO_PUPDR_PUPD7_Pos (14U)
5329 #define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
5330 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
5331 #define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
5332 #define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
5333 #define GPIO_PUPDR_PUPD8_Pos (16U)
5334 #define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
5335 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
5336 #define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
5337 #define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
5338 #define GPIO_PUPDR_PUPD9_Pos (18U)
5339 #define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
5340 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
5341 #define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
5342 #define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
5343 #define GPIO_PUPDR_PUPD10_Pos (20U)
5344 #define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
5345 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
5346 #define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
5347 #define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
5348 #define GPIO_PUPDR_PUPD11_Pos (22U)
5349 #define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
5350 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
5351 #define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
5352 #define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
5353 #define GPIO_PUPDR_PUPD12_Pos (24U)
5354 #define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
5355 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
5356 #define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
5357 #define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
5358 #define GPIO_PUPDR_PUPD13_Pos (26U)
5359 #define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
5360 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
5361 #define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
5362 #define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
5363 #define GPIO_PUPDR_PUPD14_Pos (28U)
5364 #define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
5365 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
5366 #define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
5367 #define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
5368 #define GPIO_PUPDR_PUPD15_Pos (30U)
5369 #define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
5370 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
5371 #define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
5372 #define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
5373
5374 /* Legacy defines */
5375 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
5376 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
5377 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
5378 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
5379 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
5380 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
5381 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
5382 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
5383 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
5384 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
5385 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
5386 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
5387 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
5388 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
5389 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
5390 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
5391 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
5392 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
5393 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
5394 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
5395 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
5396 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
5397 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
5398 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
5399 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
5400 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
5401 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
5402 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
5403 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
5404 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
5405 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
5406 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
5407 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
5408 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
5409 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
5410 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
5411 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
5412 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
5413 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
5414 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
5415 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
5416 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
5417 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
5418 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
5419 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
5420 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
5421 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
5422 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
5423
5424 /****************** Bits definition for GPIO_IDR register *******************/
5425 #define GPIO_IDR_ID0_Pos (0U)
5426 #define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
5427 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
5428 #define GPIO_IDR_ID1_Pos (1U)
5429 #define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
5430 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
5431 #define GPIO_IDR_ID2_Pos (2U)
5432 #define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
5433 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
5434 #define GPIO_IDR_ID3_Pos (3U)
5435 #define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
5436 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
5437 #define GPIO_IDR_ID4_Pos (4U)
5438 #define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
5439 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
5440 #define GPIO_IDR_ID5_Pos (5U)
5441 #define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
5442 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
5443 #define GPIO_IDR_ID6_Pos (6U)
5444 #define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
5445 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
5446 #define GPIO_IDR_ID7_Pos (7U)
5447 #define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
5448 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
5449 #define GPIO_IDR_ID8_Pos (8U)
5450 #define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
5451 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
5452 #define GPIO_IDR_ID9_Pos (9U)
5453 #define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
5454 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
5455 #define GPIO_IDR_ID10_Pos (10U)
5456 #define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
5457 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
5458 #define GPIO_IDR_ID11_Pos (11U)
5459 #define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
5460 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
5461 #define GPIO_IDR_ID12_Pos (12U)
5462 #define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
5463 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
5464 #define GPIO_IDR_ID13_Pos (13U)
5465 #define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
5466 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
5467 #define GPIO_IDR_ID14_Pos (14U)
5468 #define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
5469 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
5470 #define GPIO_IDR_ID15_Pos (15U)
5471 #define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
5472 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
5473
5474 /* Legacy defines */
5475 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
5476 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
5477 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
5478 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
5479 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
5480 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
5481 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
5482 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
5483 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
5484 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
5485 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
5486 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
5487 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
5488 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
5489 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
5490 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
5491
5492 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
5493 #define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0
5494 #define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1
5495 #define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2
5496 #define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3
5497 #define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4
5498 #define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5
5499 #define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6
5500 #define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7
5501 #define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8
5502 #define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9
5503 #define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10
5504 #define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11
5505 #define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12
5506 #define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13
5507 #define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14
5508 #define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15
5509
5510 /****************** Bits definition for GPIO_ODR register *******************/
5511 #define GPIO_ODR_OD0_Pos (0U)
5512 #define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
5513 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
5514 #define GPIO_ODR_OD1_Pos (1U)
5515 #define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
5516 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
5517 #define GPIO_ODR_OD2_Pos (2U)
5518 #define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
5519 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
5520 #define GPIO_ODR_OD3_Pos (3U)
5521 #define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
5522 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
5523 #define GPIO_ODR_OD4_Pos (4U)
5524 #define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
5525 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
5526 #define GPIO_ODR_OD5_Pos (5U)
5527 #define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
5528 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
5529 #define GPIO_ODR_OD6_Pos (6U)
5530 #define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
5531 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
5532 #define GPIO_ODR_OD7_Pos (7U)
5533 #define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
5534 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
5535 #define GPIO_ODR_OD8_Pos (8U)
5536 #define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
5537 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
5538 #define GPIO_ODR_OD9_Pos (9U)
5539 #define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
5540 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
5541 #define GPIO_ODR_OD10_Pos (10U)
5542 #define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
5543 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
5544 #define GPIO_ODR_OD11_Pos (11U)
5545 #define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
5546 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
5547 #define GPIO_ODR_OD12_Pos (12U)
5548 #define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
5549 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
5550 #define GPIO_ODR_OD13_Pos (13U)
5551 #define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
5552 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
5553 #define GPIO_ODR_OD14_Pos (14U)
5554 #define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
5555 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
5556 #define GPIO_ODR_OD15_Pos (15U)
5557 #define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
5558 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
5559
5560 /* Legacy defines */
5561 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
5562 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
5563 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
5564 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
5565 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
5566 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
5567 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
5568 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
5569 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
5570 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
5571 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
5572 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
5573 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
5574 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
5575 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
5576 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
5577
5578 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
5579 #define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0
5580 #define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1
5581 #define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2
5582 #define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3
5583 #define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4
5584 #define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5
5585 #define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6
5586 #define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7
5587 #define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8
5588 #define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9
5589 #define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10
5590 #define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11
5591 #define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12
5592 #define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13
5593 #define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14
5594 #define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15
5595
5596 /****************** Bits definition for GPIO_BSRR register ******************/
5597 #define GPIO_BSRR_BS0_Pos (0U)
5598 #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
5599 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
5600 #define GPIO_BSRR_BS1_Pos (1U)
5601 #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
5602 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
5603 #define GPIO_BSRR_BS2_Pos (2U)
5604 #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
5605 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
5606 #define GPIO_BSRR_BS3_Pos (3U)
5607 #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
5608 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
5609 #define GPIO_BSRR_BS4_Pos (4U)
5610 #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
5611 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
5612 #define GPIO_BSRR_BS5_Pos (5U)
5613 #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
5614 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
5615 #define GPIO_BSRR_BS6_Pos (6U)
5616 #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
5617 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
5618 #define GPIO_BSRR_BS7_Pos (7U)
5619 #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
5620 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
5621 #define GPIO_BSRR_BS8_Pos (8U)
5622 #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
5623 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
5624 #define GPIO_BSRR_BS9_Pos (9U)
5625 #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
5626 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
5627 #define GPIO_BSRR_BS10_Pos (10U)
5628 #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
5629 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
5630 #define GPIO_BSRR_BS11_Pos (11U)
5631 #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
5632 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
5633 #define GPIO_BSRR_BS12_Pos (12U)
5634 #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
5635 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
5636 #define GPIO_BSRR_BS13_Pos (13U)
5637 #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
5638 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
5639 #define GPIO_BSRR_BS14_Pos (14U)
5640 #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
5641 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
5642 #define GPIO_BSRR_BS15_Pos (15U)
5643 #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
5644 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
5645 #define GPIO_BSRR_BR0_Pos (16U)
5646 #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
5647 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
5648 #define GPIO_BSRR_BR1_Pos (17U)
5649 #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
5650 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
5651 #define GPIO_BSRR_BR2_Pos (18U)
5652 #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
5653 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
5654 #define GPIO_BSRR_BR3_Pos (19U)
5655 #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
5656 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
5657 #define GPIO_BSRR_BR4_Pos (20U)
5658 #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
5659 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
5660 #define GPIO_BSRR_BR5_Pos (21U)
5661 #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
5662 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
5663 #define GPIO_BSRR_BR6_Pos (22U)
5664 #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
5665 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
5666 #define GPIO_BSRR_BR7_Pos (23U)
5667 #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
5668 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
5669 #define GPIO_BSRR_BR8_Pos (24U)
5670 #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
5671 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
5672 #define GPIO_BSRR_BR9_Pos (25U)
5673 #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
5674 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
5675 #define GPIO_BSRR_BR10_Pos (26U)
5676 #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
5677 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
5678 #define GPIO_BSRR_BR11_Pos (27U)
5679 #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
5680 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
5681 #define GPIO_BSRR_BR12_Pos (28U)
5682 #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
5683 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
5684 #define GPIO_BSRR_BR13_Pos (29U)
5685 #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
5686 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
5687 #define GPIO_BSRR_BR14_Pos (30U)
5688 #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
5689 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
5690 #define GPIO_BSRR_BR15_Pos (31U)
5691 #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
5692 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
5693
5694 /* Legacy defines */
5695 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
5696 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
5697 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
5698 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
5699 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
5700 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
5701 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
5702 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
5703 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
5704 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
5705 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
5706 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
5707 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
5708 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
5709 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
5710 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
5711 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
5712 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
5713 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
5714 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
5715 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
5716 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
5717 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
5718 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
5719 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
5720 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
5721 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
5722 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
5723 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
5724 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
5725 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
5726 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
5727
5728 /****************** Bit definition for GPIO_LCKR register *********************/
5729 #define GPIO_LCKR_LCK0_Pos (0U)
5730 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
5731 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
5732 #define GPIO_LCKR_LCK1_Pos (1U)
5733 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
5734 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
5735 #define GPIO_LCKR_LCK2_Pos (2U)
5736 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
5737 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
5738 #define GPIO_LCKR_LCK3_Pos (3U)
5739 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
5740 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
5741 #define GPIO_LCKR_LCK4_Pos (4U)
5742 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
5743 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
5744 #define GPIO_LCKR_LCK5_Pos (5U)
5745 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
5746 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
5747 #define GPIO_LCKR_LCK6_Pos (6U)
5748 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
5749 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
5750 #define GPIO_LCKR_LCK7_Pos (7U)
5751 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
5752 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
5753 #define GPIO_LCKR_LCK8_Pos (8U)
5754 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
5755 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
5756 #define GPIO_LCKR_LCK9_Pos (9U)
5757 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
5758 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
5759 #define GPIO_LCKR_LCK10_Pos (10U)
5760 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
5761 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
5762 #define GPIO_LCKR_LCK11_Pos (11U)
5763 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
5764 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
5765 #define GPIO_LCKR_LCK12_Pos (12U)
5766 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
5767 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
5768 #define GPIO_LCKR_LCK13_Pos (13U)
5769 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
5770 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
5771 #define GPIO_LCKR_LCK14_Pos (14U)
5772 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
5773 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
5774 #define GPIO_LCKR_LCK15_Pos (15U)
5775 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
5776 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
5777 #define GPIO_LCKR_LCKK_Pos (16U)
5778 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
5779 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
5780
5781 /****************** Bit definition for GPIO_AFRL register *********************/
5782 #define GPIO_AFRL_AFSEL0_Pos (0U)
5783 #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
5784 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
5785 #define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
5786 #define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
5787 #define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
5788 #define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
5789 #define GPIO_AFRL_AFSEL1_Pos (4U)
5790 #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
5791 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
5792 #define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
5793 #define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
5794 #define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
5795 #define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
5796 #define GPIO_AFRL_AFSEL2_Pos (8U)
5797 #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
5798 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
5799 #define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
5800 #define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
5801 #define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
5802 #define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
5803 #define GPIO_AFRL_AFSEL3_Pos (12U)
5804 #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
5805 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
5806 #define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
5807 #define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
5808 #define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
5809 #define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
5810 #define GPIO_AFRL_AFSEL4_Pos (16U)
5811 #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
5812 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
5813 #define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
5814 #define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
5815 #define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
5816 #define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
5817 #define GPIO_AFRL_AFSEL5_Pos (20U)
5818 #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
5819 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
5820 #define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
5821 #define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
5822 #define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
5823 #define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
5824 #define GPIO_AFRL_AFSEL6_Pos (24U)
5825 #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
5826 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
5827 #define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
5828 #define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
5829 #define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
5830 #define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
5831 #define GPIO_AFRL_AFSEL7_Pos (28U)
5832 #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
5833 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
5834 #define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
5835 #define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
5836 #define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
5837 #define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
5838
5839 /* Legacy defines */
5840 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
5841 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
5842 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
5843 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
5844 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
5845 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
5846 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
5847 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
5848
5849 /****************** Bit definition for GPIO_AFRH register *********************/
5850 #define GPIO_AFRH_AFSEL8_Pos (0U)
5851 #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
5852 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
5853 #define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
5854 #define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
5855 #define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
5856 #define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
5857 #define GPIO_AFRH_AFSEL9_Pos (4U)
5858 #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
5859 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
5860 #define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
5861 #define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
5862 #define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
5863 #define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
5864 #define GPIO_AFRH_AFSEL10_Pos (8U)
5865 #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
5866 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
5867 #define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
5868 #define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
5869 #define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
5870 #define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
5871 #define GPIO_AFRH_AFSEL11_Pos (12U)
5872 #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
5873 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
5874 #define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
5875 #define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
5876 #define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
5877 #define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
5878 #define GPIO_AFRH_AFSEL12_Pos (16U)
5879 #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
5880 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
5881 #define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
5882 #define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
5883 #define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
5884 #define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
5885 #define GPIO_AFRH_AFSEL13_Pos (20U)
5886 #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
5887 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
5888 #define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
5889 #define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
5890 #define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
5891 #define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
5892 #define GPIO_AFRH_AFSEL14_Pos (24U)
5893 #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
5894 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
5895 #define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
5896 #define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
5897 #define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
5898 #define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
5899 #define GPIO_AFRH_AFSEL15_Pos (28U)
5900 #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
5901 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
5902 #define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
5903 #define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
5904 #define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
5905 #define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
5906
5907 /* Legacy defines */
5908 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
5909 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
5910 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
5911 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
5912 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
5913 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
5914 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
5915 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
5916
5917 /****************** Bits definition for GPIO_BRR register ******************/
5918 #define GPIO_BRR_BR0_Pos (0U)
5919 #define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
5920 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
5921 #define GPIO_BRR_BR1_Pos (1U)
5922 #define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
5923 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
5924 #define GPIO_BRR_BR2_Pos (2U)
5925 #define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
5926 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
5927 #define GPIO_BRR_BR3_Pos (3U)
5928 #define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
5929 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
5930 #define GPIO_BRR_BR4_Pos (4U)
5931 #define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
5932 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
5933 #define GPIO_BRR_BR5_Pos (5U)
5934 #define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
5935 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
5936 #define GPIO_BRR_BR6_Pos (6U)
5937 #define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
5938 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
5939 #define GPIO_BRR_BR7_Pos (7U)
5940 #define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
5941 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
5942 #define GPIO_BRR_BR8_Pos (8U)
5943 #define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
5944 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
5945 #define GPIO_BRR_BR9_Pos (9U)
5946 #define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
5947 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
5948 #define GPIO_BRR_BR10_Pos (10U)
5949 #define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
5950 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
5951 #define GPIO_BRR_BR11_Pos (11U)
5952 #define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
5953 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
5954 #define GPIO_BRR_BR12_Pos (12U)
5955 #define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
5956 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
5957 #define GPIO_BRR_BR13_Pos (13U)
5958 #define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
5959 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
5960 #define GPIO_BRR_BR14_Pos (14U)
5961 #define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
5962 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
5963 #define GPIO_BRR_BR15_Pos (15U)
5964 #define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
5965 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
5966
5967 /* Legacy defines */
5968 #define GPIO_BRR_BR_0 GPIO_BRR_BR0
5969 #define GPIO_BRR_BR_1 GPIO_BRR_BR1
5970 #define GPIO_BRR_BR_2 GPIO_BRR_BR2
5971 #define GPIO_BRR_BR_3 GPIO_BRR_BR3
5972 #define GPIO_BRR_BR_4 GPIO_BRR_BR4
5973 #define GPIO_BRR_BR_5 GPIO_BRR_BR5
5974 #define GPIO_BRR_BR_6 GPIO_BRR_BR6
5975 #define GPIO_BRR_BR_7 GPIO_BRR_BR7
5976 #define GPIO_BRR_BR_8 GPIO_BRR_BR8
5977 #define GPIO_BRR_BR_9 GPIO_BRR_BR9
5978 #define GPIO_BRR_BR_10 GPIO_BRR_BR10
5979 #define GPIO_BRR_BR_11 GPIO_BRR_BR11
5980 #define GPIO_BRR_BR_12 GPIO_BRR_BR12
5981 #define GPIO_BRR_BR_13 GPIO_BRR_BR13
5982 #define GPIO_BRR_BR_14 GPIO_BRR_BR14
5983 #define GPIO_BRR_BR_15 GPIO_BRR_BR15
5984
5985
5986 /******************************************************************************/
5987 /* */
5988 /* Inter-integrated Circuit Interface (I2C) */
5989 /* */
5990 /******************************************************************************/
5991 /******************* Bit definition for I2C_CR1 register *******************/
5992 #define I2C_CR1_PE_Pos (0U)
5993 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
5994 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
5995 #define I2C_CR1_TXIE_Pos (1U)
5996 #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
5997 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
5998 #define I2C_CR1_RXIE_Pos (2U)
5999 #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
6000 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
6001 #define I2C_CR1_ADDRIE_Pos (3U)
6002 #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
6003 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
6004 #define I2C_CR1_NACKIE_Pos (4U)
6005 #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
6006 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
6007 #define I2C_CR1_STOPIE_Pos (5U)
6008 #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
6009 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
6010 #define I2C_CR1_TCIE_Pos (6U)
6011 #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
6012 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
6013 #define I2C_CR1_ERRIE_Pos (7U)
6014 #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
6015 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
6016 #define I2C_CR1_DNF_Pos (8U)
6017 #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
6018 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
6019 #define I2C_CR1_ANFOFF_Pos (12U)
6020 #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
6021 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
6022 #define I2C_CR1_SWRST_Pos (13U)
6023 #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
6024 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
6025 #define I2C_CR1_TXDMAEN_Pos (14U)
6026 #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
6027 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
6028 #define I2C_CR1_RXDMAEN_Pos (15U)
6029 #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
6030 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
6031 #define I2C_CR1_SBC_Pos (16U)
6032 #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
6033 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
6034 #define I2C_CR1_NOSTRETCH_Pos (17U)
6035 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
6036 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
6037 #define I2C_CR1_WUPEN_Pos (18U)
6038 #define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
6039 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
6040 #define I2C_CR1_GCEN_Pos (19U)
6041 #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
6042 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
6043 #define I2C_CR1_SMBHEN_Pos (20U)
6044 #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
6045 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
6046 #define I2C_CR1_SMBDEN_Pos (21U)
6047 #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
6048 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
6049 #define I2C_CR1_ALERTEN_Pos (22U)
6050 #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
6051 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
6052 #define I2C_CR1_PECEN_Pos (23U)
6053 #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
6054 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
6055
6056 /****************** Bit definition for I2C_CR2 register ********************/
6057 #define I2C_CR2_SADD_Pos (0U)
6058 #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
6059 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
6060 #define I2C_CR2_RD_WRN_Pos (10U)
6061 #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
6062 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
6063 #define I2C_CR2_ADD10_Pos (11U)
6064 #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
6065 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
6066 #define I2C_CR2_HEAD10R_Pos (12U)
6067 #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
6068 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
6069 #define I2C_CR2_START_Pos (13U)
6070 #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
6071 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
6072 #define I2C_CR2_STOP_Pos (14U)
6073 #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
6074 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
6075 #define I2C_CR2_NACK_Pos (15U)
6076 #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
6077 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
6078 #define I2C_CR2_NBYTES_Pos (16U)
6079 #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
6080 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
6081 #define I2C_CR2_RELOAD_Pos (24U)
6082 #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
6083 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
6084 #define I2C_CR2_AUTOEND_Pos (25U)
6085 #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
6086 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
6087 #define I2C_CR2_PECBYTE_Pos (26U)
6088 #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
6089 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
6090
6091 /******************* Bit definition for I2C_OAR1 register ******************/
6092 #define I2C_OAR1_OA1_Pos (0U)
6093 #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
6094 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
6095 #define I2C_OAR1_OA1MODE_Pos (10U)
6096 #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
6097 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
6098 #define I2C_OAR1_OA1EN_Pos (15U)
6099 #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
6100 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
6101
6102 /******************* Bit definition for I2C_OAR2 register ******************/
6103 #define I2C_OAR2_OA2_Pos (1U)
6104 #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
6105 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
6106 #define I2C_OAR2_OA2MSK_Pos (8U)
6107 #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
6108 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
6109 #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
6110 #define I2C_OAR2_OA2MASK01_Pos (8U)
6111 #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
6112 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
6113 #define I2C_OAR2_OA2MASK02_Pos (9U)
6114 #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
6115 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
6116 #define I2C_OAR2_OA2MASK03_Pos (8U)
6117 #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
6118 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
6119 #define I2C_OAR2_OA2MASK04_Pos (10U)
6120 #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
6121 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
6122 #define I2C_OAR2_OA2MASK05_Pos (8U)
6123 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
6124 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
6125 #define I2C_OAR2_OA2MASK06_Pos (9U)
6126 #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
6127 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
6128 #define I2C_OAR2_OA2MASK07_Pos (8U)
6129 #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
6130 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
6131 #define I2C_OAR2_OA2EN_Pos (15U)
6132 #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
6133 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
6134
6135 /******************* Bit definition for I2C_TIMINGR register *******************/
6136 #define I2C_TIMINGR_SCLL_Pos (0U)
6137 #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
6138 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
6139 #define I2C_TIMINGR_SCLH_Pos (8U)
6140 #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
6141 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
6142 #define I2C_TIMINGR_SDADEL_Pos (16U)
6143 #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
6144 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
6145 #define I2C_TIMINGR_SCLDEL_Pos (20U)
6146 #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
6147 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
6148 #define I2C_TIMINGR_PRESC_Pos (28U)
6149 #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
6150 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
6151
6152 /******************* Bit definition for I2C_TIMEOUTR register *******************/
6153 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
6154 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
6155 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
6156 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
6157 #define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
6158 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
6159 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
6160 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
6161 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
6162 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
6163 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
6164 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
6165 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
6166 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
6167 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
6168
6169 /****************** Bit definition for I2C_ISR register *********************/
6170 #define I2C_ISR_TXE_Pos (0U)
6171 #define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
6172 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
6173 #define I2C_ISR_TXIS_Pos (1U)
6174 #define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
6175 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
6176 #define I2C_ISR_RXNE_Pos (2U)
6177 #define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
6178 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
6179 #define I2C_ISR_ADDR_Pos (3U)
6180 #define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
6181 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
6182 #define I2C_ISR_NACKF_Pos (4U)
6183 #define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
6184 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
6185 #define I2C_ISR_STOPF_Pos (5U)
6186 #define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
6187 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
6188 #define I2C_ISR_TC_Pos (6U)
6189 #define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
6190 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
6191 #define I2C_ISR_TCR_Pos (7U)
6192 #define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
6193 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
6194 #define I2C_ISR_BERR_Pos (8U)
6195 #define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
6196 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
6197 #define I2C_ISR_ARLO_Pos (9U)
6198 #define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
6199 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
6200 #define I2C_ISR_OVR_Pos (10U)
6201 #define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
6202 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
6203 #define I2C_ISR_PECERR_Pos (11U)
6204 #define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
6205 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
6206 #define I2C_ISR_TIMEOUT_Pos (12U)
6207 #define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
6208 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
6209 #define I2C_ISR_ALERT_Pos (13U)
6210 #define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
6211 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
6212 #define I2C_ISR_BUSY_Pos (15U)
6213 #define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
6214 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
6215 #define I2C_ISR_DIR_Pos (16U)
6216 #define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
6217 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
6218 #define I2C_ISR_ADDCODE_Pos (17U)
6219 #define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
6220 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
6221
6222 /****************** Bit definition for I2C_ICR register *********************/
6223 #define I2C_ICR_ADDRCF_Pos (3U)
6224 #define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
6225 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
6226 #define I2C_ICR_NACKCF_Pos (4U)
6227 #define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
6228 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
6229 #define I2C_ICR_STOPCF_Pos (5U)
6230 #define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
6231 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
6232 #define I2C_ICR_BERRCF_Pos (8U)
6233 #define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
6234 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
6235 #define I2C_ICR_ARLOCF_Pos (9U)
6236 #define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
6237 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
6238 #define I2C_ICR_OVRCF_Pos (10U)
6239 #define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
6240 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
6241 #define I2C_ICR_PECCF_Pos (11U)
6242 #define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
6243 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
6244 #define I2C_ICR_TIMOUTCF_Pos (12U)
6245 #define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
6246 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
6247 #define I2C_ICR_ALERTCF_Pos (13U)
6248 #define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
6249 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
6250
6251 /****************** Bit definition for I2C_PECR register *********************/
6252 #define I2C_PECR_PEC_Pos (0U)
6253 #define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
6254 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
6255
6256 /****************** Bit definition for I2C_RXDR register *********************/
6257 #define I2C_RXDR_RXDATA_Pos (0U)
6258 #define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
6259 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
6260
6261 /****************** Bit definition for I2C_TXDR register *********************/
6262 #define I2C_TXDR_TXDATA_Pos (0U)
6263 #define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
6264 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
6265
6266 /******************************************************************************/
6267 /* */
6268 /* Independent WATCHDOG */
6269 /* */
6270 /******************************************************************************/
6271 /******************* Bit definition for IWDG_KR register ********************/
6272 #define IWDG_KR_KEY_Pos (0U)
6273 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
6274 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
6275
6276 /******************* Bit definition for IWDG_PR register ********************/
6277 #define IWDG_PR_PR_Pos (0U)
6278 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
6279 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
6280 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
6281 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
6282 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
6283
6284 /******************* Bit definition for IWDG_RLR register *******************/
6285 #define IWDG_RLR_RL_Pos (0U)
6286 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
6287 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
6288
6289 /******************* Bit definition for IWDG_SR register ********************/
6290 #define IWDG_SR_PVU_Pos (0U)
6291 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
6292 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
6293 #define IWDG_SR_RVU_Pos (1U)
6294 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
6295 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
6296 #define IWDG_SR_WVU_Pos (2U)
6297 #define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
6298 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
6299
6300 /******************* Bit definition for IWDG_KR register ********************/
6301 #define IWDG_WINR_WIN_Pos (0U)
6302 #define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
6303 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
6304
6305 /******************************************************************************/
6306 /* */
6307 /* Operational Amplifier (OPAMP) */
6308 /* */
6309 /******************************************************************************/
6310 /********************* Bit definition for OPAMPx_CSR register ***************/
6311 #define OPAMP_CSR_OPAMPxEN_Pos (0U)
6312 #define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
6313 #define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
6314 #define OPAMP_CSR_FORCEVP_Pos (1U)
6315 #define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos) /*!< 0x00000002 */
6316 #define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */
6317 #define OPAMP_CSR_VPSEL_Pos (2U)
6318 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
6319 #define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverting input selection */
6320 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
6321 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
6322 #define OPAMP_CSR_USERTRIM_Pos (4U)
6323 #define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00000010 */
6324 #define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
6325 #define OPAMP_CSR_VMSEL_Pos (5U)
6326 #define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000060 */
6327 #define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
6328 #define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000020 */
6329 #define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000040 */
6330 #define OPAMP_CSR_HIGHSPEEDEN_Pos (7U)
6331 #define OPAMP_CSR_HIGHSPEEDEN_Msk (0x1UL << OPAMP_CSR_HIGHSPEEDEN_Pos) /*!< 0x00000080 */
6332 #define OPAMP_CSR_HIGHSPEEDEN OPAMP_CSR_HIGHSPEEDEN_Msk /*!< High speed mode enable */
6333 #define OPAMP_CSR_OPAMPINTEN_Pos (8U)
6334 #define OPAMP_CSR_OPAMPINTEN_Msk (0x1UL << OPAMP_CSR_OPAMPINTEN_Pos) /*!< 0x00000100 */
6335 #define OPAMP_CSR_OPAMPINTEN OPAMP_CSR_OPAMPINTEN_Msk /*!< Internal output enable */
6336 #define OPAMP_CSR_CALON_Pos (11U)
6337 #define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */
6338 #define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
6339 #define OPAMP_CSR_CALSEL_Pos (12U)
6340 #define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */
6341 #define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
6342 #define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */
6343 #define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
6344 #define OPAMP_CSR_PGGAIN_Pos (14U)
6345 #define OPAMP_CSR_PGGAIN_Msk (0x1FUL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x0007C000 */
6346 #define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Gain in PGA mode */
6347 #define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00004000 */
6348 #define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00008000 */
6349 #define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00010000 */
6350 #define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00020000 */
6351 #define OPAMP_CSR_PGGAIN_4 (0x10UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00040000 */
6352 #define OPAMP_CSR_TRIMOFFSETP_Pos (19U)
6353 #define OPAMP_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */
6354 #define OPAMP_CSR_TRIMOFFSETP OPAMP_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */
6355 #define OPAMP_CSR_TRIMOFFSETN_Pos (24U)
6356 #define OPAMP_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */
6357 #define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */
6358 #define OPAMP_CSR_OUTCAL_Pos (30U)
6359 #define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */
6360 #define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */
6361 #define OPAMP_CSR_LOCK_Pos (31U)
6362 #define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */
6363 #define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP control/status register lock */
6364
6365 /********************* Bit definition for OPAMPx_TCMR register ***************/
6366
6367 #define OPAMP_TCMR_VMSSEL_Pos (0U)
6368 #define OPAMP_TCMR_VMSSEL_Msk (0x1UL << OPAMP_TCMR_VMSSEL_Pos) /*!< 0x00000001 */
6369 #define OPAMP_TCMR_VMSSEL OPAMP_TCMR_VMSSEL_Msk /*!< Secondary inverting input selection */
6370 #define OPAMP_TCMR_VPSSEL_Pos (1U)
6371 #define OPAMP_TCMR_VPSSEL_Msk (0x3UL << OPAMP_TCMR_VPSSEL_Pos) /*!< 0x00000006 */
6372 #define OPAMP_TCMR_VPSSEL OPAMP_TCMR_VPSSEL_Msk /*!< Secondary non inverting input selection */
6373 #define OPAMP_TCMR_VPSSEL_0 (0x1UL << OPAMP_TCMR_VPSSEL_Pos) /*!< 0x00000002 */
6374 #define OPAMP_TCMR_VPSSEL_1 (0x2UL << OPAMP_TCMR_VPSSEL_Pos) /*!< 0x00000004 */
6375 #define OPAMP_TCMR_T1CMEN_Pos (3U)
6376 #define OPAMP_TCMR_T1CMEN_Msk (0x1UL << OPAMP_TCMR_T1CMEN_Pos) /*!< 0x00000008 */
6377 #define OPAMP_TCMR_T1CMEN OPAMP_TCMR_T1CMEN_Msk /*!< Timer 1 controlled mux mode enable */
6378 #define OPAMP_TCMR_T8CMEN_Pos (4U)
6379 #define OPAMP_TCMR_T8CMEN_Msk (0x1UL << OPAMP_TCMR_T8CMEN_Pos) /*!< 0x00000010 */
6380 #define OPAMP_TCMR_T8CMEN OPAMP_TCMR_T8CMEN_Msk /*!< Timer 8 controlled mux mode enable */
6381 #define OPAMP_TCMR_T20CMEN_Pos (5U)
6382 #define OPAMP_TCMR_T20CMEN_Msk (0x1UL << OPAMP_TCMR_T20CMEN_Pos) /*!< 0x00000020 */
6383 #define OPAMP_TCMR_T20CMEN OPAMP_TCMR_T20CMEN_Msk /*!< Timer 20 controlled mux mode enable */
6384 #define OPAMP_TCMR_LOCK_Pos (31U)
6385 #define OPAMP_TCMR_LOCK_Msk (0x1UL << OPAMP_TCMR_LOCK_Pos) /*!< 0x80000000 */
6386 #define OPAMP_TCMR_LOCK OPAMP_TCMR_LOCK_Msk /*!< OPAMP SW control register lock */
6387
6388
6389 /******************************************************************************/
6390 /* */
6391 /* Power Control */
6392 /* */
6393 /******************************************************************************/
6394
6395 /******************** Bit definition for PWR_CR1 register ********************/
6396
6397 #define PWR_CR1_LPR_Pos (14U)
6398 #define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos) /*!< 0x00004000 */
6399 #define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator low-power mode */
6400 #define PWR_CR1_VOS_Pos (9U)
6401 #define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos) /*!< 0x00000600 */
6402 #define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
6403 #define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos) /*!< 0x00000200 */
6404 #define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos) /*!< 0x00000400 */
6405 #define PWR_CR1_DBP_Pos (8U)
6406 #define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
6407 #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
6408 #define PWR_CR1_LPMS_Pos (0U)
6409 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
6410 #define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low-power mode selection field */
6411 #define PWR_CR1_LPMS_STOP0 (0x00000000U) /*!< Stop 0 mode */
6412 #define PWR_CR1_LPMS_STOP1_Pos (0U)
6413 #define PWR_CR1_LPMS_STOP1_Msk (0x1UL << PWR_CR1_LPMS_STOP1_Pos) /*!< 0x00000001 */
6414 #define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_Msk /*!< Stop 1 mode */
6415 #define PWR_CR1_LPMS_STANDBY_Pos (0U)
6416 #define PWR_CR1_LPMS_STANDBY_Msk (0x3UL << PWR_CR1_LPMS_STANDBY_Pos) /*!< 0x00000003 */
6417 #define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_Msk /*!< Stand-by mode */
6418 #define PWR_CR1_LPMS_SHUTDOWN_Pos (2U)
6419 #define PWR_CR1_LPMS_SHUTDOWN_Msk (0x1UL << PWR_CR1_LPMS_SHUTDOWN_Pos) /*!< 0x00000004 */
6420 #define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_Msk /*!< Shut-down mode */
6421
6422
6423 /******************** Bit definition for PWR_CR2 register ********************/
6424
6425 /*!< PVME Peripheral Voltage Monitor Enable */
6426 #define PWR_CR2_PVME_Pos (4U)
6427 #define PWR_CR2_PVME_Msk (0xFUL << PWR_CR2_PVME_Pos) /*!< 0x000000F0 */
6428 #define PWR_CR2_PVME PWR_CR2_PVME_Msk /*!< PVM bits field */
6429 #define PWR_CR2_PVME4_Pos (7U)
6430 #define PWR_CR2_PVME4_Msk (0x1UL << PWR_CR2_PVME4_Pos) /*!< 0x00000080 */
6431 #define PWR_CR2_PVME4 PWR_CR2_PVME4_Msk /*!< PVM 4 Enable */
6432 #define PWR_CR2_PVME3_Pos (6U)
6433 #define PWR_CR2_PVME3_Msk (0x1UL << PWR_CR2_PVME3_Pos) /*!< 0x00000040 */
6434 #define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk /*!< PVM 3 Enable */
6435 #define PWR_CR2_PVME2_Pos (5U)
6436 #define PWR_CR2_PVME2_Msk (0x1UL << PWR_CR2_PVME2_Pos) /*!< 0x00000020 */
6437 #define PWR_CR2_PVME2 PWR_CR2_PVME2_Msk /*!< PVM 2 Enable */
6438 #define PWR_CR2_PVME1_Pos (4U)
6439 #define PWR_CR2_PVME1_Msk (0x1UL << PWR_CR2_PVME1_Pos) /*!< 0x00000010 */
6440 #define PWR_CR2_PVME1 PWR_CR2_PVME1_Msk /*!< PVM 1 Enable */
6441
6442 /*!< PVD level configuration */
6443 #define PWR_CR2_PLS_Pos (1U)
6444 #define PWR_CR2_PLS_Msk (0x7UL << PWR_CR2_PLS_Pos) /*!< 0x0000000E */
6445 #define PWR_CR2_PLS PWR_CR2_PLS_Msk /*!< PVD level selection */
6446 #define PWR_CR2_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
6447 #define PWR_CR2_PLS_LEV1_Pos (1U)
6448 #define PWR_CR2_PLS_LEV1_Msk (0x1UL << PWR_CR2_PLS_LEV1_Pos) /*!< 0x00000002 */
6449 #define PWR_CR2_PLS_LEV1 PWR_CR2_PLS_LEV1_Msk /*!< PVD level 1 */
6450 #define PWR_CR2_PLS_LEV2_Pos (2U)
6451 #define PWR_CR2_PLS_LEV2_Msk (0x1UL << PWR_CR2_PLS_LEV2_Pos) /*!< 0x00000004 */
6452 #define PWR_CR2_PLS_LEV2 PWR_CR2_PLS_LEV2_Msk /*!< PVD level 2 */
6453 #define PWR_CR2_PLS_LEV3_Pos (1U)
6454 #define PWR_CR2_PLS_LEV3_Msk (0x3UL << PWR_CR2_PLS_LEV3_Pos) /*!< 0x00000006 */
6455 #define PWR_CR2_PLS_LEV3 PWR_CR2_PLS_LEV3_Msk /*!< PVD level 3 */
6456 #define PWR_CR2_PLS_LEV4_Pos (3U)
6457 #define PWR_CR2_PLS_LEV4_Msk (0x1UL << PWR_CR2_PLS_LEV4_Pos) /*!< 0x00000008 */
6458 #define PWR_CR2_PLS_LEV4 PWR_CR2_PLS_LEV4_Msk /*!< PVD level 4 */
6459 #define PWR_CR2_PLS_LEV5_Pos (1U)
6460 #define PWR_CR2_PLS_LEV5_Msk (0x5UL << PWR_CR2_PLS_LEV5_Pos) /*!< 0x0000000A */
6461 #define PWR_CR2_PLS_LEV5 PWR_CR2_PLS_LEV5_Msk /*!< PVD level 5 */
6462 #define PWR_CR2_PLS_LEV6_Pos (2U)
6463 #define PWR_CR2_PLS_LEV6_Msk (0x3UL << PWR_CR2_PLS_LEV6_Pos) /*!< 0x0000000C */
6464 #define PWR_CR2_PLS_LEV6 PWR_CR2_PLS_LEV6_Msk /*!< PVD level 6 */
6465 #define PWR_CR2_PLS_LEV7_Pos (1U)
6466 #define PWR_CR2_PLS_LEV7_Msk (0x7UL << PWR_CR2_PLS_LEV7_Pos) /*!< 0x0000000E */
6467 #define PWR_CR2_PLS_LEV7 PWR_CR2_PLS_LEV7_Msk /*!< PVD level 7 */
6468 #define PWR_CR2_PVDE_Pos (0U)
6469 #define PWR_CR2_PVDE_Msk (0x1UL << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */
6470 #define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
6471
6472 /******************** Bit definition for PWR_CR3 register ********************/
6473 #define PWR_CR3_EIWF_Pos (15U)
6474 #define PWR_CR3_EIWF_Msk (0x1UL << PWR_CR3_EIWF_Pos) /*!< 0x00008000 */
6475 #define PWR_CR3_EIWF PWR_CR3_EIWF_Msk /*!< Enable Internal Wake-up line */
6476 #define PWR_CR3_UCPD_DBDIS_Pos (14U)
6477 #define PWR_CR3_UCPD_DBDIS_Msk (0x1UL << PWR_CR3_UCPD_DBDIS_Pos) /*!< 0x00004000 */
6478 #define PWR_CR3_UCPD_DBDIS PWR_CR3_UCPD_DBDIS_Msk /*!< USB Type-C and Power Delivery Dead Battery disable. */
6479 #define PWR_CR3_UCPD_STDBY_Pos (13U)
6480 #define PWR_CR3_UCPD_STDBY_Msk (0x1UL << PWR_CR3_UCPD_STDBY_Pos) /*!< 0x00002000 */
6481 #define PWR_CR3_UCPD_STDBY PWR_CR3_UCPD_STDBY_Msk /*!< USB Type-C and Power Delivery standby mode. */
6482 #define PWR_CR3_APC_Pos (10U)
6483 #define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos) /*!< 0x00000400 */
6484 #define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
6485 #define PWR_CR3_RRS_Pos (8U)
6486 #define PWR_CR3_RRS_Msk (0x1UL << PWR_CR3_RRS_Pos) /*!< 0x00000100 */
6487 #define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 Retention in Stand-by mode */
6488 #define PWR_CR3_EWUP5_Pos (4U)
6489 #define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
6490 #define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk /*!< Enable Wake-Up Pin 5 */
6491 #define PWR_CR3_EWUP4_Pos (3U)
6492 #define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */
6493 #define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable Wake-Up Pin 4 */
6494 #define PWR_CR3_EWUP3_Pos (2U)
6495 #define PWR_CR3_EWUP3_Msk (0x1UL << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */
6496 #define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable Wake-Up Pin 3 */
6497 #define PWR_CR3_EWUP2_Pos (1U)
6498 #define PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */
6499 #define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable Wake-Up Pin 2 */
6500 #define PWR_CR3_EWUP1_Pos (0U)
6501 #define PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */
6502 #define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable Wake-Up Pin 1 */
6503 #define PWR_CR3_EWUP_Pos (0U)
6504 #define PWR_CR3_EWUP_Msk (0x1FUL << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
6505 #define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
6506
6507 /******************** Bit definition for PWR_CR4 register ********************/
6508 #define PWR_CR4_VBRS_Pos (9U)
6509 #define PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
6510 #define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */
6511 #define PWR_CR4_VBE_Pos (8U)
6512 #define PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos) /*!< 0x00000100 */
6513 #define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT Battery charging Enable */
6514 #define PWR_CR4_WP5_Pos (4U)
6515 #define PWR_CR4_WP5_Msk (0x1UL << PWR_CR4_WP5_Pos) /*!< 0x00000010 */
6516 #define PWR_CR4_WP5 PWR_CR4_WP5_Msk /*!< Wake-Up Pin 5 polarity */
6517 #define PWR_CR4_WP4_Pos (3U)
6518 #define PWR_CR4_WP4_Msk (0x1UL << PWR_CR4_WP4_Pos) /*!< 0x00000008 */
6519 #define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 polarity */
6520 #define PWR_CR4_WP3_Pos (2U)
6521 #define PWR_CR4_WP3_Msk (0x1UL << PWR_CR4_WP3_Pos) /*!< 0x00000004 */
6522 #define PWR_CR4_WP3 PWR_CR4_WP3_Msk /*!< Wake-Up Pin 3 polarity */
6523 #define PWR_CR4_WP2_Pos (1U)
6524 #define PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos) /*!< 0x00000002 */
6525 #define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 polarity */
6526 #define PWR_CR4_WP1_Pos (0U)
6527 #define PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos) /*!< 0x00000001 */
6528 #define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 polarity */
6529
6530 /******************** Bit definition for PWR_SR1 register ********************/
6531 #define PWR_SR1_WUFI_Pos (15U)
6532 #define PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */
6533 #define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wake-Up Flag Internal */
6534 #define PWR_SR1_SBF_Pos (8U)
6535 #define PWR_SR1_SBF_Msk (0x1UL << PWR_SR1_SBF_Pos) /*!< 0x00000100 */
6536 #define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Stand-By Flag */
6537 #define PWR_SR1_WUF_Pos (0U)
6538 #define PWR_SR1_WUF_Msk (0x1FUL << PWR_SR1_WUF_Pos) /*!< 0x0000001F */
6539 #define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wake-up Flags */
6540 #define PWR_SR1_WUF5_Pos (4U)
6541 #define PWR_SR1_WUF5_Msk (0x1UL << PWR_SR1_WUF5_Pos) /*!< 0x00000010 */
6542 #define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk /*!< Wake-up Flag 5 */
6543 #define PWR_SR1_WUF4_Pos (3U)
6544 #define PWR_SR1_WUF4_Msk (0x1UL << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */
6545 #define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wake-up Flag 4 */
6546 #define PWR_SR1_WUF3_Pos (2U)
6547 #define PWR_SR1_WUF3_Msk (0x1UL << PWR_SR1_WUF3_Pos) /*!< 0x00000004 */
6548 #define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk /*!< Wake-up Flag 3 */
6549 #define PWR_SR1_WUF2_Pos (1U)
6550 #define PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */
6551 #define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wake-up Flag 2 */
6552 #define PWR_SR1_WUF1_Pos (0U)
6553 #define PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */
6554 #define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wake-up Flag 1 */
6555
6556 /******************** Bit definition for PWR_SR2 register ********************/
6557 #define PWR_SR2_PVMO4_Pos (15U)
6558 #define PWR_SR2_PVMO4_Msk (0x1UL << PWR_SR2_PVMO4_Pos) /*!< 0x00008000 */
6559 #define PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk /*!< Peripheral Voltage Monitoring Output 4 */
6560 #define PWR_SR2_PVMO3_Pos (14U)
6561 #define PWR_SR2_PVMO3_Msk (0x1UL << PWR_SR2_PVMO3_Pos) /*!< 0x00004000 */
6562 #define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk /*!< Peripheral Voltage Monitoring Output 3 */
6563 #define PWR_SR2_PVMO2_Pos (13U)
6564 #define PWR_SR2_PVMO2_Msk (0x1UL << PWR_SR2_PVMO2_Pos) /*!< 0x00002000 */
6565 #define PWR_SR2_PVMO2 PWR_SR2_PVMO2_Msk /*!< Peripheral Voltage Monitoring Output 2 */
6566 #define PWR_SR2_PVMO1_Pos (12U)
6567 #define PWR_SR2_PVMO1_Msk (0x1UL << PWR_SR2_PVMO1_Pos) /*!< 0x00001000 */
6568 #define PWR_SR2_PVMO1 PWR_SR2_PVMO1_Msk /*!< Peripheral Voltage Monitoring Output 1 */
6569 #define PWR_SR2_PVDO_Pos (11U)
6570 #define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
6571 #define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power Voltage Detector Output */
6572 #define PWR_SR2_VOSF_Pos (10U)
6573 #define PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */
6574 #define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage Scaling Flag */
6575 #define PWR_SR2_REGLPF_Pos (9U)
6576 #define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */
6577 #define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power Regulator Flag */
6578 #define PWR_SR2_REGLPS_Pos (8U)
6579 #define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */
6580 #define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power Regulator Started */
6581
6582 /******************** Bit definition for PWR_SCR register ********************/
6583 #define PWR_SCR_CSBF_Pos (8U)
6584 #define PWR_SCR_CSBF_Msk (0x1UL << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */
6585 #define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Stand-By Flag */
6586 #define PWR_SCR_CWUF_Pos (0U)
6587 #define PWR_SCR_CWUF_Msk (0x1FUL << PWR_SCR_CWUF_Pos) /*!< 0x0000001F */
6588 #define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */
6589 #define PWR_SCR_CWUF5_Pos (4U)
6590 #define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
6591 #define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk /*!< Clear Wake-up Flag 5 */
6592 #define PWR_SCR_CWUF4_Pos (3U)
6593 #define PWR_SCR_CWUF4_Msk (0x1UL << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */
6594 #define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */
6595 #define PWR_SCR_CWUF3_Pos (2U)
6596 #define PWR_SCR_CWUF3_Msk (0x1UL << PWR_SCR_CWUF3_Pos) /*!< 0x00000004 */
6597 #define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up Flag 3 */
6598 #define PWR_SCR_CWUF2_Pos (1U)
6599 #define PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */
6600 #define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */
6601 #define PWR_SCR_CWUF1_Pos (0U)
6602 #define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */
6603 #define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */
6604
6605 /******************** Bit definition for PWR_PUCRA register ********************/
6606 #define PWR_PUCRA_PA15_Pos (15U)
6607 #define PWR_PUCRA_PA15_Msk (0x1UL << PWR_PUCRA_PA15_Pos) /*!< 0x00008000 */
6608 #define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Port PA15 Pull-Up set */
6609 #define PWR_PUCRA_PA13_Pos (13U)
6610 #define PWR_PUCRA_PA13_Msk (0x1UL << PWR_PUCRA_PA13_Pos) /*!< 0x00002000 */
6611 #define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Port PA13 Pull-Up set */
6612 #define PWR_PUCRA_PA12_Pos (12U)
6613 #define PWR_PUCRA_PA12_Msk (0x1UL << PWR_PUCRA_PA12_Pos) /*!< 0x00001000 */
6614 #define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Port PA12 Pull-Up set */
6615 #define PWR_PUCRA_PA11_Pos (11U)
6616 #define PWR_PUCRA_PA11_Msk (0x1UL << PWR_PUCRA_PA11_Pos) /*!< 0x00000800 */
6617 #define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Port PA11 Pull-Up set */
6618 #define PWR_PUCRA_PA10_Pos (10U)
6619 #define PWR_PUCRA_PA10_Msk (0x1UL << PWR_PUCRA_PA10_Pos) /*!< 0x00000400 */
6620 #define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Port PA10 Pull-Up set */
6621 #define PWR_PUCRA_PA9_Pos (9U)
6622 #define PWR_PUCRA_PA9_Msk (0x1UL << PWR_PUCRA_PA9_Pos) /*!< 0x00000200 */
6623 #define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Port PA9 Pull-Up set */
6624 #define PWR_PUCRA_PA8_Pos (8U)
6625 #define PWR_PUCRA_PA8_Msk (0x1UL << PWR_PUCRA_PA8_Pos) /*!< 0x00000100 */
6626 #define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Port PA8 Pull-Up set */
6627 #define PWR_PUCRA_PA7_Pos (7U)
6628 #define PWR_PUCRA_PA7_Msk (0x1UL << PWR_PUCRA_PA7_Pos) /*!< 0x00000080 */
6629 #define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Port PA7 Pull-Up set */
6630 #define PWR_PUCRA_PA6_Pos (6U)
6631 #define PWR_PUCRA_PA6_Msk (0x1UL << PWR_PUCRA_PA6_Pos) /*!< 0x00000040 */
6632 #define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Port PA6 Pull-Up set */
6633 #define PWR_PUCRA_PA5_Pos (5U)
6634 #define PWR_PUCRA_PA5_Msk (0x1UL << PWR_PUCRA_PA5_Pos) /*!< 0x00000020 */
6635 #define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Port PA5 Pull-Up set */
6636 #define PWR_PUCRA_PA4_Pos (4U)
6637 #define PWR_PUCRA_PA4_Msk (0x1UL << PWR_PUCRA_PA4_Pos) /*!< 0x00000010 */
6638 #define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Port PA4 Pull-Up set */
6639 #define PWR_PUCRA_PA3_Pos (3U)
6640 #define PWR_PUCRA_PA3_Msk (0x1UL << PWR_PUCRA_PA3_Pos) /*!< 0x00000008 */
6641 #define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Port PA3 Pull-Up set */
6642 #define PWR_PUCRA_PA2_Pos (2U)
6643 #define PWR_PUCRA_PA2_Msk (0x1UL << PWR_PUCRA_PA2_Pos) /*!< 0x00000004 */
6644 #define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Port PA2 Pull-Up set */
6645 #define PWR_PUCRA_PA1_Pos (1U)
6646 #define PWR_PUCRA_PA1_Msk (0x1UL << PWR_PUCRA_PA1_Pos) /*!< 0x00000002 */
6647 #define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Port PA1 Pull-Up set */
6648 #define PWR_PUCRA_PA0_Pos (0U)
6649 #define PWR_PUCRA_PA0_Msk (0x1UL << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */
6650 #define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Port PA0 Pull-Up set */
6651
6652 /******************** Bit definition for PWR_PDCRA register ********************/
6653 #define PWR_PDCRA_PA14_Pos (14U)
6654 #define PWR_PDCRA_PA14_Msk (0x1UL << PWR_PDCRA_PA14_Pos) /*!< 0x00004000 */
6655 #define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Port PA14 Pull-Down set */
6656 #define PWR_PDCRA_PA12_Pos (12U)
6657 #define PWR_PDCRA_PA12_Msk (0x1UL << PWR_PDCRA_PA12_Pos) /*!< 0x00001000 */
6658 #define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Port PA12 Pull-Down set */
6659 #define PWR_PDCRA_PA11_Pos (11U)
6660 #define PWR_PDCRA_PA11_Msk (0x1UL << PWR_PDCRA_PA11_Pos) /*!< 0x00000800 */
6661 #define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Port PA11 Pull-Down set */
6662 #define PWR_PDCRA_PA10_Pos (10U)
6663 #define PWR_PDCRA_PA10_Msk (0x1UL << PWR_PDCRA_PA10_Pos) /*!< 0x00000400 */
6664 #define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Port PA10 Pull-Down set */
6665 #define PWR_PDCRA_PA9_Pos (9U)
6666 #define PWR_PDCRA_PA9_Msk (0x1UL << PWR_PDCRA_PA9_Pos) /*!< 0x00000200 */
6667 #define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Port PA9 Pull-Down set */
6668 #define PWR_PDCRA_PA8_Pos (8U)
6669 #define PWR_PDCRA_PA8_Msk (0x1UL << PWR_PDCRA_PA8_Pos) /*!< 0x00000100 */
6670 #define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Port PA8 Pull-Down set */
6671 #define PWR_PDCRA_PA7_Pos (7U)
6672 #define PWR_PDCRA_PA7_Msk (0x1UL << PWR_PDCRA_PA7_Pos) /*!< 0x00000080 */
6673 #define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Port PA7 Pull-Down set */
6674 #define PWR_PDCRA_PA6_Pos (6U)
6675 #define PWR_PDCRA_PA6_Msk (0x1UL << PWR_PDCRA_PA6_Pos) /*!< 0x00000040 */
6676 #define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Port PA6 Pull-Down set */
6677 #define PWR_PDCRA_PA5_Pos (5U)
6678 #define PWR_PDCRA_PA5_Msk (0x1UL << PWR_PDCRA_PA5_Pos) /*!< 0x00000020 */
6679 #define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Port PA5 Pull-Down set */
6680 #define PWR_PDCRA_PA4_Pos (4U)
6681 #define PWR_PDCRA_PA4_Msk (0x1UL << PWR_PDCRA_PA4_Pos) /*!< 0x00000010 */
6682 #define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Port PA4 Pull-Down set */
6683 #define PWR_PDCRA_PA3_Pos (3U)
6684 #define PWR_PDCRA_PA3_Msk (0x1UL << PWR_PDCRA_PA3_Pos) /*!< 0x00000008 */
6685 #define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Port PA3 Pull-Down set */
6686 #define PWR_PDCRA_PA2_Pos (2U)
6687 #define PWR_PDCRA_PA2_Msk (0x1UL << PWR_PDCRA_PA2_Pos) /*!< 0x00000004 */
6688 #define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Port PA2 Pull-Down set */
6689 #define PWR_PDCRA_PA1_Pos (1U)
6690 #define PWR_PDCRA_PA1_Msk (0x1UL << PWR_PDCRA_PA1_Pos) /*!< 0x00000002 */
6691 #define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Port PA1 Pull-Down set */
6692 #define PWR_PDCRA_PA0_Pos (0U)
6693 #define PWR_PDCRA_PA0_Msk (0x1UL << PWR_PDCRA_PA0_Pos) /*!< 0x00000001 */
6694 #define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Port PA0 Pull-Down set */
6695
6696 /******************** Bit definition for PWR_PUCRB register ********************/
6697
6698 #define PWR_PUCRB_PB15_Pos (15U)
6699 #define PWR_PUCRB_PB15_Msk (0x1UL << PWR_PUCRB_PB15_Pos) /*!< 0x00008000 */
6700 #define PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk /*!< Port PB15 Pull-Up set */
6701 #define PWR_PUCRB_PB14_Pos (14U)
6702 #define PWR_PUCRB_PB14_Msk (0x1UL << PWR_PUCRB_PB14_Pos) /*!< 0x00004000 */
6703 #define PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk /*!< Port PB14 Pull-Up set */
6704 #define PWR_PUCRB_PB13_Pos (13U)
6705 #define PWR_PUCRB_PB13_Msk (0x1UL << PWR_PUCRB_PB13_Pos) /*!< 0x00002000 */
6706 #define PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk /*!< Port PB13 Pull-Up set */
6707 #define PWR_PUCRB_PB12_Pos (12U)
6708 #define PWR_PUCRB_PB12_Msk (0x1UL << PWR_PUCRB_PB12_Pos) /*!< 0x00001000 */
6709 #define PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk /*!< Port PB12 Pull-Up set */
6710 #define PWR_PUCRB_PB11_Pos (11U)
6711 #define PWR_PUCRB_PB11_Msk (0x1UL << PWR_PUCRB_PB11_Pos) /*!< 0x00000800 */
6712 #define PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk /*!< Port PB11 Pull-Up set */
6713 #define PWR_PUCRB_PB10_Pos (10U)
6714 #define PWR_PUCRB_PB10_Msk (0x1UL << PWR_PUCRB_PB10_Pos) /*!< 0x00000400 */
6715 #define PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk /*!< Port PB10 Pull-Up set */
6716 #define PWR_PUCRB_PB9_Pos (9U)
6717 #define PWR_PUCRB_PB9_Msk (0x1UL << PWR_PUCRB_PB9_Pos) /*!< 0x00000200 */
6718 #define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk /*!< Port PB9 Pull-Up set */
6719 #define PWR_PUCRB_PB8_Pos (8U)
6720 #define PWR_PUCRB_PB8_Msk (0x1UL << PWR_PUCRB_PB8_Pos) /*!< 0x00000100 */
6721 #define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk /*!< Port PB8 Pull-Up set */
6722 #define PWR_PUCRB_PB7_Pos (7U)
6723 #define PWR_PUCRB_PB7_Msk (0x1UL << PWR_PUCRB_PB7_Pos) /*!< 0x00000080 */
6724 #define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Port PB7 Pull-Up set */
6725 #define PWR_PUCRB_PB6_Pos (6U)
6726 #define PWR_PUCRB_PB6_Msk (0x1UL << PWR_PUCRB_PB6_Pos) /*!< 0x00000040 */
6727 #define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Port PB6 Pull-Up set */
6728 #define PWR_PUCRB_PB5_Pos (5U)
6729 #define PWR_PUCRB_PB5_Msk (0x1UL << PWR_PUCRB_PB5_Pos) /*!< 0x00000020 */
6730 #define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Port PB5 Pull-Up set */
6731 #define PWR_PUCRB_PB4_Pos (4U)
6732 #define PWR_PUCRB_PB4_Msk (0x1UL << PWR_PUCRB_PB4_Pos) /*!< 0x00000010 */
6733 #define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Port PB4 Pull-Up set */
6734 #define PWR_PUCRB_PB3_Pos (3U)
6735 #define PWR_PUCRB_PB3_Msk (0x1UL << PWR_PUCRB_PB3_Pos) /*!< 0x00000008 */
6736 #define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Port PB3 Pull-Up set */
6737 #define PWR_PUCRB_PB2_Pos (2U)
6738 #define PWR_PUCRB_PB2_Msk (0x1UL << PWR_PUCRB_PB2_Pos) /*!< 0x00000004 */
6739 #define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk /*!< Port PB2 Pull-Up set */
6740 #define PWR_PUCRB_PB1_Pos (1U)
6741 #define PWR_PUCRB_PB1_Msk (0x1UL << PWR_PUCRB_PB1_Pos) /*!< 0x00000002 */
6742 #define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Port PB1 Pull-Up set */
6743 #define PWR_PUCRB_PB0_Pos (0U)
6744 #define PWR_PUCRB_PB0_Msk (0x1UL << PWR_PUCRB_PB0_Pos) /*!< 0x00000001 */
6745 #define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Port PB0 Pull-Up set */
6746
6747 /******************** Bit definition for PWR_PDCRB register ********************/
6748 #define PWR_PDCRB_PB15_Pos (15U)
6749 #define PWR_PDCRB_PB15_Msk (0x1UL << PWR_PDCRB_PB15_Pos) /*!< 0x00008000 */
6750 #define PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk /*!< Port PB15 Pull-Down set */
6751 #define PWR_PDCRB_PB14_Pos (14U)
6752 #define PWR_PDCRB_PB14_Msk (0x1UL << PWR_PDCRB_PB14_Pos) /*!< 0x00004000 */
6753 #define PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk /*!< Port PB14 Pull-Down set */
6754 #define PWR_PDCRB_PB13_Pos (13U)
6755 #define PWR_PDCRB_PB13_Msk (0x1UL << PWR_PDCRB_PB13_Pos) /*!< 0x00002000 */
6756 #define PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk /*!< Port PB13 Pull-Down set */
6757 #define PWR_PDCRB_PB12_Pos (12U)
6758 #define PWR_PDCRB_PB12_Msk (0x1UL << PWR_PDCRB_PB12_Pos) /*!< 0x00001000 */
6759 #define PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk /*!< Port PB12 Pull-Down set */
6760 #define PWR_PDCRB_PB11_Pos (11U)
6761 #define PWR_PDCRB_PB11_Msk (0x1UL << PWR_PDCRB_PB11_Pos) /*!< 0x00000800 */
6762 #define PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk /*!< Port PB11 Pull-Down set */
6763 #define PWR_PDCRB_PB10_Pos (10U)
6764 #define PWR_PDCRB_PB10_Msk (0x1UL << PWR_PDCRB_PB10_Pos) /*!< 0x00000400 */
6765 #define PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk /*!< Port PB10 Pull-Down set */
6766 #define PWR_PDCRB_PB9_Pos (9U)
6767 #define PWR_PDCRB_PB9_Msk (0x1UL << PWR_PDCRB_PB9_Pos) /*!< 0x00000200 */
6768 #define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk /*!< Port PB9 Pull-Down set */
6769 #define PWR_PDCRB_PB8_Pos (8U)
6770 #define PWR_PDCRB_PB8_Msk (0x1UL << PWR_PDCRB_PB8_Pos) /*!< 0x00000100 */
6771 #define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk /*!< Port PB8 Pull-Down set */
6772 #define PWR_PDCRB_PB7_Pos (7U)
6773 #define PWR_PDCRB_PB7_Msk (0x1UL << PWR_PDCRB_PB7_Pos) /*!< 0x00000080 */
6774 #define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Port PB7 Pull-Down set */
6775 #define PWR_PDCRB_PB6_Pos (6U)
6776 #define PWR_PDCRB_PB6_Msk (0x1UL << PWR_PDCRB_PB6_Pos) /*!< 0x00000040 */
6777 #define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Port PB6 Pull-Down set */
6778 #define PWR_PDCRB_PB5_Pos (5U)
6779 #define PWR_PDCRB_PB5_Msk (0x1UL << PWR_PDCRB_PB5_Pos) /*!< 0x00000020 */
6780 #define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Port PB5 Pull-Down set */
6781 #define PWR_PDCRB_PB3_Pos (3U)
6782 #define PWR_PDCRB_PB3_Msk (0x1UL << PWR_PDCRB_PB3_Pos) /*!< 0x00000008 */
6783 #define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Port PB3 Pull-Down set */
6784 #define PWR_PDCRB_PB2_Pos (2U)
6785 #define PWR_PDCRB_PB2_Msk (0x1UL << PWR_PDCRB_PB2_Pos) /*!< 0x00000004 */
6786 #define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk /*!< Port PB2 Pull-Down set */
6787 #define PWR_PDCRB_PB1_Pos (1U)
6788 #define PWR_PDCRB_PB1_Msk (0x1UL << PWR_PDCRB_PB1_Pos) /*!< 0x00000002 */
6789 #define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Port PB1 Pull-Down set */
6790 #define PWR_PDCRB_PB0_Pos (0U)
6791 #define PWR_PDCRB_PB0_Msk (0x1UL << PWR_PDCRB_PB0_Pos) /*!< 0x00000001 */
6792 #define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Port PB0 Pull-Down set */
6793
6794 /******************** Bit definition for PWR_PUCRC register ********************/
6795 #define PWR_PUCRC_PC15_Pos (15U)
6796 #define PWR_PUCRC_PC15_Msk (0x1UL << PWR_PUCRC_PC15_Pos) /*!< 0x00008000 */
6797 #define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Port PC15 Pull-Up set */
6798 #define PWR_PUCRC_PC14_Pos (14U)
6799 #define PWR_PUCRC_PC14_Msk (0x1UL << PWR_PUCRC_PC14_Pos) /*!< 0x00004000 */
6800 #define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Port PC14 Pull-Up set */
6801 #define PWR_PUCRC_PC13_Pos (13U)
6802 #define PWR_PUCRC_PC13_Msk (0x1UL << PWR_PUCRC_PC13_Pos) /*!< 0x00002000 */
6803 #define PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk /*!< Port PC13 Pull-Up set */
6804 #define PWR_PUCRC_PC12_Pos (12U)
6805 #define PWR_PUCRC_PC12_Msk (0x1UL << PWR_PUCRC_PC12_Pos) /*!< 0x00001000 */
6806 #define PWR_PUCRC_PC12 PWR_PUCRC_PC12_Msk /*!< Port PC12 Pull-Up set */
6807 #define PWR_PUCRC_PC11_Pos (11U)
6808 #define PWR_PUCRC_PC11_Msk (0x1UL << PWR_PUCRC_PC11_Pos) /*!< 0x00000800 */
6809 #define PWR_PUCRC_PC11 PWR_PUCRC_PC11_Msk /*!< Port PC11 Pull-Up set */
6810 #define PWR_PUCRC_PC10_Pos (10U)
6811 #define PWR_PUCRC_PC10_Msk (0x1UL << PWR_PUCRC_PC10_Pos) /*!< 0x00000400 */
6812 #define PWR_PUCRC_PC10 PWR_PUCRC_PC10_Msk /*!< Port PC10 Pull-Up set */
6813 #define PWR_PUCRC_PC9_Pos (9U)
6814 #define PWR_PUCRC_PC9_Msk (0x1UL << PWR_PUCRC_PC9_Pos) /*!< 0x00000200 */
6815 #define PWR_PUCRC_PC9 PWR_PUCRC_PC9_Msk /*!< Port PC9 Pull-Up set */
6816 #define PWR_PUCRC_PC8_Pos (8U)
6817 #define PWR_PUCRC_PC8_Msk (0x1UL << PWR_PUCRC_PC8_Pos) /*!< 0x00000100 */
6818 #define PWR_PUCRC_PC8 PWR_PUCRC_PC8_Msk /*!< Port PC8 Pull-Up set */
6819 #define PWR_PUCRC_PC7_Pos (7U)
6820 #define PWR_PUCRC_PC7_Msk (0x1UL << PWR_PUCRC_PC7_Pos) /*!< 0x00000080 */
6821 #define PWR_PUCRC_PC7 PWR_PUCRC_PC7_Msk /*!< Port PC7 Pull-Up set */
6822 #define PWR_PUCRC_PC6_Pos (6U)
6823 #define PWR_PUCRC_PC6_Msk (0x1UL << PWR_PUCRC_PC6_Pos) /*!< 0x00000040 */
6824 #define PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk /*!< Port PC6 Pull-Up set */
6825 #define PWR_PUCRC_PC5_Pos (5U)
6826 #define PWR_PUCRC_PC5_Msk (0x1UL << PWR_PUCRC_PC5_Pos) /*!< 0x00000020 */
6827 #define PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk /*!< Port PC5 Pull-Up set */
6828 #define PWR_PUCRC_PC4_Pos (4U)
6829 #define PWR_PUCRC_PC4_Msk (0x1UL << PWR_PUCRC_PC4_Pos) /*!< 0x00000010 */
6830 #define PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk /*!< Port PC4 Pull-Up set */
6831 #define PWR_PUCRC_PC3_Pos (3U)
6832 #define PWR_PUCRC_PC3_Msk (0x1UL << PWR_PUCRC_PC3_Pos) /*!< 0x00000008 */
6833 #define PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk /*!< Port PC3 Pull-Up set */
6834 #define PWR_PUCRC_PC2_Pos (2U)
6835 #define PWR_PUCRC_PC2_Msk (0x1UL << PWR_PUCRC_PC2_Pos) /*!< 0x00000004 */
6836 #define PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk /*!< Port PC2 Pull-Up set */
6837 #define PWR_PUCRC_PC1_Pos (1U)
6838 #define PWR_PUCRC_PC1_Msk (0x1UL << PWR_PUCRC_PC1_Pos) /*!< 0x00000002 */
6839 #define PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk /*!< Port PC1 Pull-Up set */
6840 #define PWR_PUCRC_PC0_Pos (0U)
6841 #define PWR_PUCRC_PC0_Msk (0x1UL << PWR_PUCRC_PC0_Pos) /*!< 0x00000001 */
6842 #define PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk /*!< Port PC0 Pull-Up set */
6843
6844 /******************** Bit definition for PWR_PDCRC register ********************/
6845 #define PWR_PDCRC_PC15_Pos (15U)
6846 #define PWR_PDCRC_PC15_Msk (0x1UL << PWR_PDCRC_PC15_Pos) /*!< 0x00008000 */
6847 #define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Port PC15 Pull-Down set */
6848 #define PWR_PDCRC_PC14_Pos (14U)
6849 #define PWR_PDCRC_PC14_Msk (0x1UL << PWR_PDCRC_PC14_Pos) /*!< 0x00004000 */
6850 #define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Port PC14 Pull-Down set */
6851 #define PWR_PDCRC_PC13_Pos (13U)
6852 #define PWR_PDCRC_PC13_Msk (0x1UL << PWR_PDCRC_PC13_Pos) /*!< 0x00002000 */
6853 #define PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk /*!< Port PC13 Pull-Down set */
6854 #define PWR_PDCRC_PC12_Pos (12U)
6855 #define PWR_PDCRC_PC12_Msk (0x1UL << PWR_PDCRC_PC12_Pos) /*!< 0x00001000 */
6856 #define PWR_PDCRC_PC12 PWR_PDCRC_PC12_Msk /*!< Port PC12 Pull-Down set */
6857 #define PWR_PDCRC_PC11_Pos (11U)
6858 #define PWR_PDCRC_PC11_Msk (0x1UL << PWR_PDCRC_PC11_Pos) /*!< 0x00000800 */
6859 #define PWR_PDCRC_PC11 PWR_PDCRC_PC11_Msk /*!< Port PC11 Pull-Down set */
6860 #define PWR_PDCRC_PC10_Pos (10U)
6861 #define PWR_PDCRC_PC10_Msk (0x1UL << PWR_PDCRC_PC10_Pos) /*!< 0x00000400 */
6862 #define PWR_PDCRC_PC10 PWR_PDCRC_PC10_Msk /*!< Port PC10 Pull-Down set */
6863 #define PWR_PDCRC_PC9_Pos (9U)
6864 #define PWR_PDCRC_PC9_Msk (0x1UL << PWR_PDCRC_PC9_Pos) /*!< 0x00000200 */
6865 #define PWR_PDCRC_PC9 PWR_PDCRC_PC9_Msk /*!< Port PC9 Pull-Down set */
6866 #define PWR_PDCRC_PC8_Pos (8U)
6867 #define PWR_PDCRC_PC8_Msk (0x1UL << PWR_PDCRC_PC8_Pos) /*!< 0x00000100 */
6868 #define PWR_PDCRC_PC8 PWR_PDCRC_PC8_Msk /*!< Port PC8 Pull-Down set */
6869 #define PWR_PDCRC_PC7_Pos (7U)
6870 #define PWR_PDCRC_PC7_Msk (0x1UL << PWR_PDCRC_PC7_Pos) /*!< 0x00000080 */
6871 #define PWR_PDCRC_PC7 PWR_PDCRC_PC7_Msk /*!< Port PC7 Pull-Down set */
6872 #define PWR_PDCRC_PC6_Pos (6U)
6873 #define PWR_PDCRC_PC6_Msk (0x1UL << PWR_PDCRC_PC6_Pos) /*!< 0x00000040 */
6874 #define PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk /*!< Port PC6 Pull-Down set */
6875 #define PWR_PDCRC_PC5_Pos (5U)
6876 #define PWR_PDCRC_PC5_Msk (0x1UL << PWR_PDCRC_PC5_Pos) /*!< 0x00000020 */
6877 #define PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk /*!< Port PC5 Pull-Down set */
6878 #define PWR_PDCRC_PC4_Pos (4U)
6879 #define PWR_PDCRC_PC4_Msk (0x1UL << PWR_PDCRC_PC4_Pos) /*!< 0x00000010 */
6880 #define PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk /*!< Port PC4 Pull-Down set */
6881 #define PWR_PDCRC_PC3_Pos (3U)
6882 #define PWR_PDCRC_PC3_Msk (0x1UL << PWR_PDCRC_PC3_Pos) /*!< 0x00000008 */
6883 #define PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk /*!< Port PC3 Pull-Down set */
6884 #define PWR_PDCRC_PC2_Pos (2U)
6885 #define PWR_PDCRC_PC2_Msk (0x1UL << PWR_PDCRC_PC2_Pos) /*!< 0x00000004 */
6886 #define PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk /*!< Port PC2 Pull-Down set */
6887 #define PWR_PDCRC_PC1_Pos (1U)
6888 #define PWR_PDCRC_PC1_Msk (0x1UL << PWR_PDCRC_PC1_Pos) /*!< 0x00000002 */
6889 #define PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk /*!< Port PC1 Pull-Down set */
6890 #define PWR_PDCRC_PC0_Pos (0U)
6891 #define PWR_PDCRC_PC0_Msk (0x1UL << PWR_PDCRC_PC0_Pos) /*!< 0x00000001 */
6892 #define PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk /*!< Port PC0 Pull-Down set */
6893
6894 /******************** Bit definition for PWR_PUCRD register ********************/
6895 #define PWR_PUCRD_PD15_Pos (15U)
6896 #define PWR_PUCRD_PD15_Msk (0x1UL << PWR_PUCRD_PD15_Pos) /*!< 0x00008000 */
6897 #define PWR_PUCRD_PD15 PWR_PUCRD_PD15_Msk /*!< Port PD15 Pull-Up set */
6898 #define PWR_PUCRD_PD14_Pos (14U)
6899 #define PWR_PUCRD_PD14_Msk (0x1UL << PWR_PUCRD_PD14_Pos) /*!< 0x00004000 */
6900 #define PWR_PUCRD_PD14 PWR_PUCRD_PD14_Msk /*!< Port PD14 Pull-Up set */
6901 #define PWR_PUCRD_PD13_Pos (13U)
6902 #define PWR_PUCRD_PD13_Msk (0x1UL << PWR_PUCRD_PD13_Pos) /*!< 0x00002000 */
6903 #define PWR_PUCRD_PD13 PWR_PUCRD_PD13_Msk /*!< Port PD13 Pull-Up set */
6904 #define PWR_PUCRD_PD12_Pos (12U)
6905 #define PWR_PUCRD_PD12_Msk (0x1UL << PWR_PUCRD_PD12_Pos) /*!< 0x00001000 */
6906 #define PWR_PUCRD_PD12 PWR_PUCRD_PD12_Msk /*!< Port PD12 Pull-Up set */
6907 #define PWR_PUCRD_PD11_Pos (11U)
6908 #define PWR_PUCRD_PD11_Msk (0x1UL << PWR_PUCRD_PD11_Pos) /*!< 0x00000800 */
6909 #define PWR_PUCRD_PD11 PWR_PUCRD_PD11_Msk /*!< Port PD11 Pull-Up set */
6910 #define PWR_PUCRD_PD10_Pos (10U)
6911 #define PWR_PUCRD_PD10_Msk (0x1UL << PWR_PUCRD_PD10_Pos) /*!< 0x00000400 */
6912 #define PWR_PUCRD_PD10 PWR_PUCRD_PD10_Msk /*!< Port PD10 Pull-Up set */
6913 #define PWR_PUCRD_PD9_Pos (9U)
6914 #define PWR_PUCRD_PD9_Msk (0x1UL << PWR_PUCRD_PD9_Pos) /*!< 0x00000200 */
6915 #define PWR_PUCRD_PD9 PWR_PUCRD_PD9_Msk /*!< Port PD9 Pull-Up set */
6916 #define PWR_PUCRD_PD8_Pos (8U)
6917 #define PWR_PUCRD_PD8_Msk (0x1UL << PWR_PUCRD_PD8_Pos) /*!< 0x00000100 */
6918 #define PWR_PUCRD_PD8 PWR_PUCRD_PD8_Msk /*!< Port PD8 Pull-Up set */
6919 #define PWR_PUCRD_PD7_Pos (7U)
6920 #define PWR_PUCRD_PD7_Msk (0x1UL << PWR_PUCRD_PD7_Pos) /*!< 0x00000080 */
6921 #define PWR_PUCRD_PD7 PWR_PUCRD_PD7_Msk /*!< Port PD7 Pull-Up set */
6922 #define PWR_PUCRD_PD6_Pos (6U)
6923 #define PWR_PUCRD_PD6_Msk (0x1UL << PWR_PUCRD_PD6_Pos) /*!< 0x00000040 */
6924 #define PWR_PUCRD_PD6 PWR_PUCRD_PD6_Msk /*!< Port PD6 Pull-Up set */
6925 #define PWR_PUCRD_PD5_Pos (5U)
6926 #define PWR_PUCRD_PD5_Msk (0x1UL << PWR_PUCRD_PD5_Pos) /*!< 0x00000020 */
6927 #define PWR_PUCRD_PD5 PWR_PUCRD_PD5_Msk /*!< Port PD5 Pull-Up set */
6928 #define PWR_PUCRD_PD4_Pos (4U)
6929 #define PWR_PUCRD_PD4_Msk (0x1UL << PWR_PUCRD_PD4_Pos) /*!< 0x00000010 */
6930 #define PWR_PUCRD_PD4 PWR_PUCRD_PD4_Msk /*!< Port PD4 Pull-Up set */
6931 #define PWR_PUCRD_PD3_Pos (3U)
6932 #define PWR_PUCRD_PD3_Msk (0x1UL << PWR_PUCRD_PD3_Pos) /*!< 0x00000008 */
6933 #define PWR_PUCRD_PD3 PWR_PUCRD_PD3_Msk /*!< Port PD3 Pull-Up set */
6934 #define PWR_PUCRD_PD2_Pos (2U)
6935 #define PWR_PUCRD_PD2_Msk (0x1UL << PWR_PUCRD_PD2_Pos) /*!< 0x00000004 */
6936 #define PWR_PUCRD_PD2 PWR_PUCRD_PD2_Msk /*!< Port PD2 Pull-Up set */
6937 #define PWR_PUCRD_PD1_Pos (1U)
6938 #define PWR_PUCRD_PD1_Msk (0x1UL << PWR_PUCRD_PD1_Pos) /*!< 0x00000002 */
6939 #define PWR_PUCRD_PD1 PWR_PUCRD_PD1_Msk /*!< Port PD1 Pull-Up set */
6940 #define PWR_PUCRD_PD0_Pos (0U)
6941 #define PWR_PUCRD_PD0_Msk (0x1UL << PWR_PUCRD_PD0_Pos) /*!< 0x00000001 */
6942 #define PWR_PUCRD_PD0 PWR_PUCRD_PD0_Msk /*!< Port PD0 Pull-Up set */
6943
6944 /******************** Bit definition for PWR_PDCRD register ********************/
6945 #define PWR_PDCRD_PD15_Pos (15U)
6946 #define PWR_PDCRD_PD15_Msk (0x1UL << PWR_PDCRD_PD15_Pos) /*!< 0x00008000 */
6947 #define PWR_PDCRD_PD15 PWR_PDCRD_PD15_Msk /*!< Port PD15 Pull-Down set */
6948 #define PWR_PDCRD_PD14_Pos (14U)
6949 #define PWR_PDCRD_PD14_Msk (0x1UL << PWR_PDCRD_PD14_Pos) /*!< 0x00004000 */
6950 #define PWR_PDCRD_PD14 PWR_PDCRD_PD14_Msk /*!< Port PD14 Pull-Down set */
6951 #define PWR_PDCRD_PD13_Pos (13U)
6952 #define PWR_PDCRD_PD13_Msk (0x1UL << PWR_PDCRD_PD13_Pos) /*!< 0x00002000 */
6953 #define PWR_PDCRD_PD13 PWR_PDCRD_PD13_Msk /*!< Port PD13 Pull-Down set */
6954 #define PWR_PDCRD_PD12_Pos (12U)
6955 #define PWR_PDCRD_PD12_Msk (0x1UL << PWR_PDCRD_PD12_Pos) /*!< 0x00001000 */
6956 #define PWR_PDCRD_PD12 PWR_PDCRD_PD12_Msk /*!< Port PD12 Pull-Down set */
6957 #define PWR_PDCRD_PD11_Pos (11U)
6958 #define PWR_PDCRD_PD11_Msk (0x1UL << PWR_PDCRD_PD11_Pos) /*!< 0x00000800 */
6959 #define PWR_PDCRD_PD11 PWR_PDCRD_PD11_Msk /*!< Port PD11 Pull-Down set */
6960 #define PWR_PDCRD_PD10_Pos (10U)
6961 #define PWR_PDCRD_PD10_Msk (0x1UL << PWR_PDCRD_PD10_Pos) /*!< 0x00000400 */
6962 #define PWR_PDCRD_PD10 PWR_PDCRD_PD10_Msk /*!< Port PD10 Pull-Down set */
6963 #define PWR_PDCRD_PD9_Pos (9U)
6964 #define PWR_PDCRD_PD9_Msk (0x1UL << PWR_PDCRD_PD9_Pos) /*!< 0x00000200 */
6965 #define PWR_PDCRD_PD9 PWR_PDCRD_PD9_Msk /*!< Port PD9 Pull-Down set */
6966 #define PWR_PDCRD_PD8_Pos (8U)
6967 #define PWR_PDCRD_PD8_Msk (0x1UL << PWR_PDCRD_PD8_Pos) /*!< 0x00000100 */
6968 #define PWR_PDCRD_PD8 PWR_PDCRD_PD8_Msk /*!< Port PD8 Pull-Down set */
6969 #define PWR_PDCRD_PD7_Pos (7U)
6970 #define PWR_PDCRD_PD7_Msk (0x1UL << PWR_PDCRD_PD7_Pos) /*!< 0x00000080 */
6971 #define PWR_PDCRD_PD7 PWR_PDCRD_PD7_Msk /*!< Port PD7 Pull-Down set */
6972 #define PWR_PDCRD_PD6_Pos (6U)
6973 #define PWR_PDCRD_PD6_Msk (0x1UL << PWR_PDCRD_PD6_Pos) /*!< 0x00000040 */
6974 #define PWR_PDCRD_PD6 PWR_PDCRD_PD6_Msk /*!< Port PD6 Pull-Down set */
6975 #define PWR_PDCRD_PD5_Pos (5U)
6976 #define PWR_PDCRD_PD5_Msk (0x1UL << PWR_PDCRD_PD5_Pos) /*!< 0x00000020 */
6977 #define PWR_PDCRD_PD5 PWR_PDCRD_PD5_Msk /*!< Port PD5 Pull-Down set */
6978 #define PWR_PDCRD_PD4_Pos (4U)
6979 #define PWR_PDCRD_PD4_Msk (0x1UL << PWR_PDCRD_PD4_Pos) /*!< 0x00000010 */
6980 #define PWR_PDCRD_PD4 PWR_PDCRD_PD4_Msk /*!< Port PD4 Pull-Down set */
6981 #define PWR_PDCRD_PD3_Pos (3U)
6982 #define PWR_PDCRD_PD3_Msk (0x1UL << PWR_PDCRD_PD3_Pos) /*!< 0x00000008 */
6983 #define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk /*!< Port PD3 Pull-Down set */
6984 #define PWR_PDCRD_PD2_Pos (2U)
6985 #define PWR_PDCRD_PD2_Msk (0x1UL << PWR_PDCRD_PD2_Pos) /*!< 0x00000004 */
6986 #define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk /*!< Port PD2 Pull-Down set */
6987 #define PWR_PDCRD_PD1_Pos (1U)
6988 #define PWR_PDCRD_PD1_Msk (0x1UL << PWR_PDCRD_PD1_Pos) /*!< 0x00000002 */
6989 #define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk /*!< Port PD1 Pull-Down set */
6990 #define PWR_PDCRD_PD0_Pos (0U)
6991 #define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */
6992 #define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk /*!< Port PD0 Pull-Down set */
6993
6994 /******************** Bit definition for PWR_PUCRE register ********************/
6995 #define PWR_PUCRE_PE15_Pos (15U)
6996 #define PWR_PUCRE_PE15_Msk (0x1UL << PWR_PUCRE_PE15_Pos) /*!< 0x00008000 */
6997 #define PWR_PUCRE_PE15 PWR_PUCRE_PE15_Msk /*!< Port PE15 Pull-Up set */
6998 #define PWR_PUCRE_PE14_Pos (14U)
6999 #define PWR_PUCRE_PE14_Msk (0x1UL << PWR_PUCRE_PE14_Pos) /*!< 0x00004000 */
7000 #define PWR_PUCRE_PE14 PWR_PUCRE_PE14_Msk /*!< Port PE14 Pull-Up set */
7001 #define PWR_PUCRE_PE13_Pos (13U)
7002 #define PWR_PUCRE_PE13_Msk (0x1UL << PWR_PUCRE_PE13_Pos) /*!< 0x00002000 */
7003 #define PWR_PUCRE_PE13 PWR_PUCRE_PE13_Msk /*!< Port PE13 Pull-Up set */
7004 #define PWR_PUCRE_PE12_Pos (12U)
7005 #define PWR_PUCRE_PE12_Msk (0x1UL << PWR_PUCRE_PE12_Pos) /*!< 0x00001000 */
7006 #define PWR_PUCRE_PE12 PWR_PUCRE_PE12_Msk /*!< Port PE12 Pull-Up set */
7007 #define PWR_PUCRE_PE11_Pos (11U)
7008 #define PWR_PUCRE_PE11_Msk (0x1UL << PWR_PUCRE_PE11_Pos) /*!< 0x00000800 */
7009 #define PWR_PUCRE_PE11 PWR_PUCRE_PE11_Msk /*!< Port PE11 Pull-Up set */
7010 #define PWR_PUCRE_PE10_Pos (10U)
7011 #define PWR_PUCRE_PE10_Msk (0x1UL << PWR_PUCRE_PE10_Pos) /*!< 0x00000400 */
7012 #define PWR_PUCRE_PE10 PWR_PUCRE_PE10_Msk /*!< Port PE10 Pull-Up set */
7013 #define PWR_PUCRE_PE9_Pos (9U)
7014 #define PWR_PUCRE_PE9_Msk (0x1UL << PWR_PUCRE_PE9_Pos) /*!< 0x00000200 */
7015 #define PWR_PUCRE_PE9 PWR_PUCRE_PE9_Msk /*!< Port PE9 Pull-Up set */
7016 #define PWR_PUCRE_PE8_Pos (8U)
7017 #define PWR_PUCRE_PE8_Msk (0x1UL << PWR_PUCRE_PE8_Pos) /*!< 0x00000100 */
7018 #define PWR_PUCRE_PE8 PWR_PUCRE_PE8_Msk /*!< Port PE8 Pull-Up set */
7019 #define PWR_PUCRE_PE7_Pos (7U)
7020 #define PWR_PUCRE_PE7_Msk (0x1UL << PWR_PUCRE_PE7_Pos) /*!< 0x00000080 */
7021 #define PWR_PUCRE_PE7 PWR_PUCRE_PE7_Msk /*!< Port PE7 Pull-Up set */
7022 #define PWR_PUCRE_PE6_Pos (6U)
7023 #define PWR_PUCRE_PE6_Msk (0x1UL << PWR_PUCRE_PE6_Pos) /*!< 0x00000040 */
7024 #define PWR_PUCRE_PE6 PWR_PUCRE_PE6_Msk /*!< Port PE6 Pull-Up set */
7025 #define PWR_PUCRE_PE5_Pos (5U)
7026 #define PWR_PUCRE_PE5_Msk (0x1UL << PWR_PUCRE_PE5_Pos) /*!< 0x00000020 */
7027 #define PWR_PUCRE_PE5 PWR_PUCRE_PE5_Msk /*!< Port PE5 Pull-Up set */
7028 #define PWR_PUCRE_PE4_Pos (4U)
7029 #define PWR_PUCRE_PE4_Msk (0x1UL << PWR_PUCRE_PE4_Pos) /*!< 0x00000010 */
7030 #define PWR_PUCRE_PE4 PWR_PUCRE_PE4_Msk /*!< Port PE4 Pull-Up set */
7031 #define PWR_PUCRE_PE3_Pos (3U)
7032 #define PWR_PUCRE_PE3_Msk (0x1UL << PWR_PUCRE_PE3_Pos) /*!< 0x00000008 */
7033 #define PWR_PUCRE_PE3 PWR_PUCRE_PE3_Msk /*!< Port PE3 Pull-Up set */
7034 #define PWR_PUCRE_PE2_Pos (2U)
7035 #define PWR_PUCRE_PE2_Msk (0x1UL << PWR_PUCRE_PE2_Pos) /*!< 0x00000004 */
7036 #define PWR_PUCRE_PE2 PWR_PUCRE_PE2_Msk /*!< Port PE2 Pull-Up set */
7037 #define PWR_PUCRE_PE1_Pos (1U)
7038 #define PWR_PUCRE_PE1_Msk (0x1UL << PWR_PUCRE_PE1_Pos) /*!< 0x00000002 */
7039 #define PWR_PUCRE_PE1 PWR_PUCRE_PE1_Msk /*!< Port PE1 Pull-Up set */
7040 #define PWR_PUCRE_PE0_Pos (0U)
7041 #define PWR_PUCRE_PE0_Msk (0x1UL << PWR_PUCRE_PE0_Pos) /*!< 0x00000001 */
7042 #define PWR_PUCRE_PE0 PWR_PUCRE_PE0_Msk /*!< Port PE0 Pull-Up set */
7043
7044 /******************** Bit definition for PWR_PDCRE register ********************/
7045 #define PWR_PDCRE_PE15_Pos (15U)
7046 #define PWR_PDCRE_PE15_Msk (0x1UL << PWR_PDCRE_PE15_Pos) /*!< 0x00008000 */
7047 #define PWR_PDCRE_PE15 PWR_PDCRE_PE15_Msk /*!< Port PE15 Pull-Down set */
7048 #define PWR_PDCRE_PE14_Pos (14U)
7049 #define PWR_PDCRE_PE14_Msk (0x1UL << PWR_PDCRE_PE14_Pos) /*!< 0x00004000 */
7050 #define PWR_PDCRE_PE14 PWR_PDCRE_PE14_Msk /*!< Port PE14 Pull-Down set */
7051 #define PWR_PDCRE_PE13_Pos (13U)
7052 #define PWR_PDCRE_PE13_Msk (0x1UL << PWR_PDCRE_PE13_Pos) /*!< 0x00002000 */
7053 #define PWR_PDCRE_PE13 PWR_PDCRE_PE13_Msk /*!< Port PE13 Pull-Down set */
7054 #define PWR_PDCRE_PE12_Pos (12U)
7055 #define PWR_PDCRE_PE12_Msk (0x1UL << PWR_PDCRE_PE12_Pos) /*!< 0x00001000 */
7056 #define PWR_PDCRE_PE12 PWR_PDCRE_PE12_Msk /*!< Port PE12 Pull-Down set */
7057 #define PWR_PDCRE_PE11_Pos (11U)
7058 #define PWR_PDCRE_PE11_Msk (0x1UL << PWR_PDCRE_PE11_Pos) /*!< 0x00000800 */
7059 #define PWR_PDCRE_PE11 PWR_PDCRE_PE11_Msk /*!< Port PE11 Pull-Down set */
7060 #define PWR_PDCRE_PE10_Pos (10U)
7061 #define PWR_PDCRE_PE10_Msk (0x1UL << PWR_PDCRE_PE10_Pos) /*!< 0x00000400 */
7062 #define PWR_PDCRE_PE10 PWR_PDCRE_PE10_Msk /*!< Port PE10 Pull-Down set */
7063 #define PWR_PDCRE_PE9_Pos (9U)
7064 #define PWR_PDCRE_PE9_Msk (0x1UL << PWR_PDCRE_PE9_Pos) /*!< 0x00000200 */
7065 #define PWR_PDCRE_PE9 PWR_PDCRE_PE9_Msk /*!< Port PE9 Pull-Down set */
7066 #define PWR_PDCRE_PE8_Pos (8U)
7067 #define PWR_PDCRE_PE8_Msk (0x1UL << PWR_PDCRE_PE8_Pos) /*!< 0x00000100 */
7068 #define PWR_PDCRE_PE8 PWR_PDCRE_PE8_Msk /*!< Port PE8 Pull-Down set */
7069 #define PWR_PDCRE_PE7_Pos (7U)
7070 #define PWR_PDCRE_PE7_Msk (0x1UL << PWR_PDCRE_PE7_Pos) /*!< 0x00000080 */
7071 #define PWR_PDCRE_PE7 PWR_PDCRE_PE7_Msk /*!< Port PE7 Pull-Down set */
7072 #define PWR_PDCRE_PE6_Pos (6U)
7073 #define PWR_PDCRE_PE6_Msk (0x1UL << PWR_PDCRE_PE6_Pos) /*!< 0x00000040 */
7074 #define PWR_PDCRE_PE6 PWR_PDCRE_PE6_Msk /*!< Port PE6 Pull-Down set */
7075 #define PWR_PDCRE_PE5_Pos (5U)
7076 #define PWR_PDCRE_PE5_Msk (0x1UL << PWR_PDCRE_PE5_Pos) /*!< 0x00000020 */
7077 #define PWR_PDCRE_PE5 PWR_PDCRE_PE5_Msk /*!< Port PE5 Pull-Down set */
7078 #define PWR_PDCRE_PE4_Pos (4U)
7079 #define PWR_PDCRE_PE4_Msk (0x1UL << PWR_PDCRE_PE4_Pos) /*!< 0x00000010 */
7080 #define PWR_PDCRE_PE4 PWR_PDCRE_PE4_Msk /*!< Port PE4 Pull-Down set */
7081 #define PWR_PDCRE_PE3_Pos (3U)
7082 #define PWR_PDCRE_PE3_Msk (0x1UL << PWR_PDCRE_PE3_Pos) /*!< 0x00000008 */
7083 #define PWR_PDCRE_PE3 PWR_PDCRE_PE3_Msk /*!< Port PE3 Pull-Down set */
7084 #define PWR_PDCRE_PE2_Pos (2U)
7085 #define PWR_PDCRE_PE2_Msk (0x1UL << PWR_PDCRE_PE2_Pos) /*!< 0x00000004 */
7086 #define PWR_PDCRE_PE2 PWR_PDCRE_PE2_Msk /*!< Port PE2 Pull-Down set */
7087 #define PWR_PDCRE_PE1_Pos (1U)
7088 #define PWR_PDCRE_PE1_Msk (0x1UL << PWR_PDCRE_PE1_Pos) /*!< 0x00000002 */
7089 #define PWR_PDCRE_PE1 PWR_PDCRE_PE1_Msk /*!< Port PE1 Pull-Down set */
7090 #define PWR_PDCRE_PE0_Pos (0U)
7091 #define PWR_PDCRE_PE0_Msk (0x1UL << PWR_PDCRE_PE0_Pos) /*!< 0x00000001 */
7092 #define PWR_PDCRE_PE0 PWR_PDCRE_PE0_Msk /*!< Port PE0 Pull-Down set */
7093
7094 /******************** Bit definition for PWR_PUCRF register ********************/
7095 #define PWR_PUCRF_PF15_Pos (15U)
7096 #define PWR_PUCRF_PF15_Msk (0x1UL << PWR_PUCRF_PF15_Pos) /*!< 0x00008000 */
7097 #define PWR_PUCRF_PF15 PWR_PUCRF_PF15_Msk /*!< Port PF15 Pull-Up set */
7098 #define PWR_PUCRF_PF14_Pos (14U)
7099 #define PWR_PUCRF_PF14_Msk (0x1UL << PWR_PUCRF_PF14_Pos) /*!< 0x00004000 */
7100 #define PWR_PUCRF_PF14 PWR_PUCRF_PF14_Msk /*!< Port PF14 Pull-Up set */
7101 #define PWR_PUCRF_PF13_Pos (13U)
7102 #define PWR_PUCRF_PF13_Msk (0x1UL << PWR_PUCRF_PF13_Pos) /*!< 0x00002000 */
7103 #define PWR_PUCRF_PF13 PWR_PUCRF_PF13_Msk /*!< Port PF13 Pull-Up set */
7104 #define PWR_PUCRF_PF12_Pos (12U)
7105 #define PWR_PUCRF_PF12_Msk (0x1UL << PWR_PUCRF_PF12_Pos) /*!< 0x00001000 */
7106 #define PWR_PUCRF_PF12 PWR_PUCRF_PF12_Msk /*!< Port PF12 Pull-Up set */
7107 #define PWR_PUCRF_PF11_Pos (11U)
7108 #define PWR_PUCRF_PF11_Msk (0x1UL << PWR_PUCRF_PF11_Pos) /*!< 0x00000800 */
7109 #define PWR_PUCRF_PF11 PWR_PUCRF_PF11_Msk /*!< Port PF11 Pull-Up set */
7110 #define PWR_PUCRF_PF10_Pos (10U)
7111 #define PWR_PUCRF_PF10_Msk (0x1UL << PWR_PUCRF_PF10_Pos) /*!< 0x00000400 */
7112 #define PWR_PUCRF_PF10 PWR_PUCRF_PF10_Msk /*!< Port PF10 Pull-Up set */
7113 #define PWR_PUCRF_PF9_Pos (9U)
7114 #define PWR_PUCRF_PF9_Msk (0x1UL << PWR_PUCRF_PF9_Pos) /*!< 0x00000200 */
7115 #define PWR_PUCRF_PF9 PWR_PUCRF_PF9_Msk /*!< Port PF9 Pull-Up set */
7116 #define PWR_PUCRF_PF8_Pos (8U)
7117 #define PWR_PUCRF_PF8_Msk (0x1UL << PWR_PUCRF_PF8_Pos) /*!< 0x00000100 */
7118 #define PWR_PUCRF_PF8 PWR_PUCRF_PF8_Msk /*!< Port PF8 Pull-Up set */
7119 #define PWR_PUCRF_PF7_Pos (7U)
7120 #define PWR_PUCRF_PF7_Msk (0x1UL << PWR_PUCRF_PF7_Pos) /*!< 0x00000080 */
7121 #define PWR_PUCRF_PF7 PWR_PUCRF_PF7_Msk /*!< Port PF7 Pull-Up set */
7122 #define PWR_PUCRF_PF6_Pos (6U)
7123 #define PWR_PUCRF_PF6_Msk (0x1UL << PWR_PUCRF_PF6_Pos) /*!< 0x00000040 */
7124 #define PWR_PUCRF_PF6 PWR_PUCRF_PF6_Msk /*!< Port PF6 Pull-Up set */
7125 #define PWR_PUCRF_PF5_Pos (5U)
7126 #define PWR_PUCRF_PF5_Msk (0x1UL << PWR_PUCRF_PF5_Pos) /*!< 0x00000020 */
7127 #define PWR_PUCRF_PF5 PWR_PUCRF_PF5_Msk /*!< Port PF5 Pull-Up set */
7128 #define PWR_PUCRF_PF4_Pos (4U)
7129 #define PWR_PUCRF_PF4_Msk (0x1UL << PWR_PUCRF_PF4_Pos) /*!< 0x00000010 */
7130 #define PWR_PUCRF_PF4 PWR_PUCRF_PF4_Msk /*!< Port PF4 Pull-Up set */
7131 #define PWR_PUCRF_PF3_Pos (3U)
7132 #define PWR_PUCRF_PF3_Msk (0x1UL << PWR_PUCRF_PF3_Pos) /*!< 0x00000008 */
7133 #define PWR_PUCRF_PF3 PWR_PUCRF_PF3_Msk /*!< Port PF3 Pull-Up set */
7134 #define PWR_PUCRF_PF2_Pos (2U)
7135 #define PWR_PUCRF_PF2_Msk (0x1UL << PWR_PUCRF_PF2_Pos) /*!< 0x00000004 */
7136 #define PWR_PUCRF_PF2 PWR_PUCRF_PF2_Msk /*!< Port PF2 Pull-Up set */
7137 #define PWR_PUCRF_PF1_Pos (1U)
7138 #define PWR_PUCRF_PF1_Msk (0x1UL << PWR_PUCRF_PF1_Pos) /*!< 0x00000002 */
7139 #define PWR_PUCRF_PF1 PWR_PUCRF_PF1_Msk /*!< Port PF1 Pull-Up set */
7140 #define PWR_PUCRF_PF0_Pos (0U)
7141 #define PWR_PUCRF_PF0_Msk (0x1UL << PWR_PUCRF_PF0_Pos) /*!< 0x00000001 */
7142 #define PWR_PUCRF_PF0 PWR_PUCRF_PF0_Msk /*!< Port PF0 Pull-Up set */
7143
7144 /******************** Bit definition for PWR_PDCRF register ********************/
7145 #define PWR_PDCRF_PF10_Pos (10U)
7146 #define PWR_PDCRF_PF10_Msk (0x1UL << PWR_PDCRF_PF10_Pos) /*!< 0x00000400 */
7147 #define PWR_PDCRF_PF10 PWR_PDCRF_PF10_Msk /*!< Port PF10 Pull-Down set */
7148 #define PWR_PDCRF_PF9_Pos (9U)
7149 #define PWR_PDCRF_PF9_Msk (0x1UL << PWR_PDCRF_PF9_Pos) /*!< 0x00000200 */
7150 #define PWR_PDCRF_PF9 PWR_PDCRF_PF9_Msk /*!< Port PF9 Pull-Down set */
7151 #define PWR_PDCRF_PF2_Pos (2U)
7152 #define PWR_PDCRF_PF2_Msk (0x1UL << PWR_PDCRF_PF2_Pos) /*!< 0x00000004 */
7153 #define PWR_PDCRF_PF2 PWR_PDCRF_PF2_Msk /*!< Port PF2 Pull-Down set */
7154 #define PWR_PDCRF_PF1_Pos (1U)
7155 #define PWR_PDCRF_PF1_Msk (0x1UL << PWR_PDCRF_PF1_Pos) /*!< 0x00000002 */
7156 #define PWR_PDCRF_PF1 PWR_PDCRF_PF1_Msk /*!< Port PF1 Pull-Down set */
7157 #define PWR_PDCRF_PF0_Pos (0U)
7158 #define PWR_PDCRF_PF0_Msk (0x1UL << PWR_PDCRF_PF0_Pos) /*!< 0x00000001 */
7159 #define PWR_PDCRF_PF0 PWR_PDCRF_PF0_Msk /*!< Port PF0 Pull-Down set */
7160
7161 /******************** Bit definition for PWR_PUCRG register ********************/
7162 #define PWR_PUCRG_PG10_Pos (10U)
7163 #define PWR_PUCRG_PG10_Msk (0x1UL << PWR_PUCRG_PG10_Pos) /*!< 0x00000400 */
7164 #define PWR_PUCRG_PG10 PWR_PUCRG_PG10_Msk /*!< Port PG10 Pull-Up set */
7165
7166 /******************** Bit definition for PWR_PDCRG register ********************/
7167 #define PWR_PDCRG_PG10_Pos (10U)
7168 #define PWR_PDCRG_PG10_Msk (0x1UL << PWR_PDCRG_PG10_Pos) /*!< 0x00000400 */
7169 #define PWR_PDCRG_PG10 PWR_PDCRG_PG10_Msk /*!< Port PG10 Pull-Down set */
7170 #define PWR_PDCRG_PG9_Pos (9U)
7171 #define PWR_PDCRG_PG9_Msk (0x1UL << PWR_PDCRG_PG9_Pos) /*!< 0x00000200 */
7172 #define PWR_PDCRG_PG9 PWR_PDCRG_PG9_Msk /*!< Port PG9 Pull-Down set */
7173 #define PWR_PDCRG_PG8_Pos (8U)
7174 #define PWR_PDCRG_PG8_Msk (0x1UL << PWR_PDCRG_PG8_Pos) /*!< 0x00000100 */
7175 #define PWR_PDCRG_PG8 PWR_PDCRG_PG8_Msk /*!< Port PG8 Pull-Down set */
7176 #define PWR_PDCRG_PG7_Pos (7U)
7177 #define PWR_PDCRG_PG7_Msk (0x1UL << PWR_PDCRG_PG7_Pos) /*!< 0x00000080 */
7178 #define PWR_PDCRG_PG7 PWR_PDCRG_PG7_Msk /*!< Port PG7 Pull-Down set */
7179 #define PWR_PDCRG_PG6_Pos (6U)
7180 #define PWR_PDCRG_PG6_Msk (0x1UL << PWR_PDCRG_PG6_Pos) /*!< 0x00000040 */
7181 #define PWR_PDCRG_PG6 PWR_PDCRG_PG6_Msk /*!< Port PG6 Pull-Down set */
7182 #define PWR_PDCRG_PG5_Pos (5U)
7183 #define PWR_PDCRG_PG5_Msk (0x1UL << PWR_PDCRG_PG5_Pos) /*!< 0x00000020 */
7184 #define PWR_PDCRG_PG5 PWR_PDCRG_PG5_Msk /*!< Port PG5 Pull-Down set */
7185 #define PWR_PDCRG_PG4_Pos (4U)
7186 #define PWR_PDCRG_PG4_Msk (0x1UL << PWR_PDCRG_PG4_Pos) /*!< 0x00000010 */
7187 #define PWR_PDCRG_PG4 PWR_PDCRG_PG4_Msk /*!< Port PG4 Pull-Down set */
7188 #define PWR_PDCRG_PG3_Pos (3U)
7189 #define PWR_PDCRG_PG3_Msk (0x1UL << PWR_PDCRG_PG3_Pos) /*!< 0x00000008 */
7190 #define PWR_PDCRG_PG3 PWR_PDCRG_PG3_Msk /*!< Port PG3 Pull-Down set */
7191 #define PWR_PDCRG_PG2_Pos (2U)
7192 #define PWR_PDCRG_PG2_Msk (0x1UL << PWR_PDCRG_PG2_Pos) /*!< 0x00000004 */
7193 #define PWR_PDCRG_PG2 PWR_PDCRG_PG2_Msk /*!< Port PG2 Pull-Down set */
7194 #define PWR_PDCRG_PG1_Pos (1U)
7195 #define PWR_PDCRG_PG1_Msk (0x1UL << PWR_PDCRG_PG1_Pos) /*!< 0x00000002 */
7196 #define PWR_PDCRG_PG1 PWR_PDCRG_PG1_Msk /*!< Port PG1 Pull-Down set */
7197 #define PWR_PDCRG_PG0_Pos (0U)
7198 #define PWR_PDCRG_PG0_Msk (0x1UL << PWR_PDCRG_PG0_Pos) /*!< 0x00000001 */
7199 #define PWR_PDCRG_PG0 PWR_PDCRG_PG0_Msk /*!< Port PG0 Pull-Down set */
7200
7201 /******************** Bit definition for PWR_CR5 register ********************/
7202 #define PWR_CR5_R1MODE_Pos (8U)
7203 #define PWR_CR5_R1MODE_Msk (0x1U << PWR_CR5_R1MODE_Pos) /*!< 0x00000100 */
7204 #define PWR_CR5_R1MODE PWR_CR5_R1MODE_Msk /*!< selection for Main Regulator in Range1 */
7205
7206
7207 /******************************************************************************/
7208 /* */
7209 /* Reset and Clock Control */
7210 /* */
7211 /******************************************************************************/
7212 /*
7213 * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
7214 */
7215
7216 #define RCC_HSI48_SUPPORT
7217 #define RCC_PLLP_DIV_2_31_SUPPORT
7218
7219 /******************** Bit definition for RCC_CR register ********************/
7220 #define RCC_CR_HSION_Pos (8U)
7221 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000100 */
7222 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */
7223 #define RCC_CR_HSIKERON_Pos (9U)
7224 #define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */
7225 #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
7226 #define RCC_CR_HSIRDY_Pos (10U)
7227 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */
7228 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */
7229
7230 #define RCC_CR_HSEON_Pos (16U)
7231 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
7232 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */
7233 #define RCC_CR_HSERDY_Pos (17U)
7234 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
7235 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */
7236 #define RCC_CR_HSEBYP_Pos (18U)
7237 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
7238 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */
7239 #define RCC_CR_CSSON_Pos (19U)
7240 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
7241 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */
7242
7243 #define RCC_CR_PLLON_Pos (24U)
7244 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
7245 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
7246 #define RCC_CR_PLLRDY_Pos (25U)
7247 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
7248 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
7249
7250 /******************** Bit definition for RCC_ICSCR register ***************/
7251 /*!< HSICAL configuration */
7252 #define RCC_ICSCR_HSICAL_Pos (16U)
7253 #define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00FF0000 */
7254 #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */
7255 #define RCC_ICSCR_HSICAL_0 (0x01UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00010000 */
7256 #define RCC_ICSCR_HSICAL_1 (0x02UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00020000 */
7257 #define RCC_ICSCR_HSICAL_2 (0x04UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00040000 */
7258 #define RCC_ICSCR_HSICAL_3 (0x08UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00080000 */
7259 #define RCC_ICSCR_HSICAL_4 (0x10UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00100000 */
7260 #define RCC_ICSCR_HSICAL_5 (0x20UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00200000 */
7261 #define RCC_ICSCR_HSICAL_6 (0x40UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00400000 */
7262 #define RCC_ICSCR_HSICAL_7 (0x80UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00800000 */
7263
7264 /*!< HSITRIM configuration */
7265 #define RCC_ICSCR_HSITRIM_Pos (24U)
7266 #define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
7267 #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
7268 #define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
7269 #define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
7270 #define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
7271 #define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
7272 #define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
7273 #define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
7274 #define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
7275
7276 /******************** Bit definition for RCC_CFGR register ******************/
7277 /*!< SW configuration */
7278 #define RCC_CFGR_SW_Pos (0U)
7279 #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
7280 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
7281 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
7282 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
7283
7284 #define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI16 oscillator selection as system clock */
7285 #define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE oscillator selection as system clock */
7286 #define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selection as system clock */
7287
7288 /*!< SWS configuration */
7289 #define RCC_CFGR_SWS_Pos (2U)
7290 #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
7291 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
7292 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
7293 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
7294
7295 #define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI16 oscillator used as system clock */
7296 #define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
7297 #define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
7298
7299 /*!< HPRE configuration */
7300 #define RCC_CFGR_HPRE_Pos (4U)
7301 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
7302 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
7303 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
7304 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
7305 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
7306 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
7307
7308 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
7309 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
7310 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
7311 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
7312 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
7313 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
7314 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
7315 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
7316 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
7317
7318 /*!< PPRE1 configuration */
7319 #define RCC_CFGR_PPRE1_Pos (8U)
7320 #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
7321 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB2 prescaler) */
7322 #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
7323 #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
7324 #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
7325
7326 #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
7327 #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
7328 #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
7329 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
7330 #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
7331
7332 /*!< PPRE2 configuration */
7333 #define RCC_CFGR_PPRE2_Pos (11U)
7334 #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
7335 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
7336 #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
7337 #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
7338 #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
7339
7340 #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
7341 #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
7342 #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
7343 #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
7344 #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
7345
7346 /*!< MCOSEL configuration */
7347 #define RCC_CFGR_MCOSEL_Pos (24U)
7348 #define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
7349 #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [3:0] bits (Clock output selection) */
7350 #define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
7351 #define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
7352 #define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
7353 #define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
7354
7355 #define RCC_CFGR_MCOPRE_Pos (28U)
7356 #define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
7357 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
7358 #define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
7359 #define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
7360 #define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
7361
7362 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
7363 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
7364 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
7365 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
7366 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
7367
7368 /* Legacy aliases */
7369 #define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE
7370 #define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1
7371 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2
7372 #define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4
7373 #define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8
7374 #define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16
7375
7376 /******************** Bit definition for RCC_PLLCFGR register ***************/
7377 #define RCC_PLLCFGR_PLLSRC_Pos (0U)
7378 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
7379 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
7380 #define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
7381 #define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
7382
7383 #define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)
7384 #define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos)/*!< 0x00000002 */
7385 #define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk /*!< HSI16 oscillator source clock selected */
7386 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)
7387 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)/*!< 0x00000003 */
7388 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk /*!< HSE oscillator source clock selected */
7389
7390 #define RCC_PLLCFGR_PLLM_Pos (4U)
7391 #define RCC_PLLCFGR_PLLM_Msk (0xFUL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x000000F0 */
7392 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
7393 #define RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
7394 #define RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
7395 #define RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */
7396 #define RCC_PLLCFGR_PLLM_3 (0x8UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000080 */
7397
7398 #define RCC_PLLCFGR_PLLN_Pos (8U)
7399 #define RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */
7400 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
7401 #define RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
7402 #define RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
7403 #define RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
7404 #define RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
7405 #define RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
7406 #define RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
7407 #define RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
7408
7409 #define RCC_PLLCFGR_PLLPEN_Pos (16U)
7410 #define RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
7411 #define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk
7412 #define RCC_PLLCFGR_PLLP_Pos (17U)
7413 #define RCC_PLLCFGR_PLLP_Msk (0x1UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
7414 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
7415 #define RCC_PLLCFGR_PLLQEN_Pos (20U)
7416 #define RCC_PLLCFGR_PLLQEN_Msk (0x1UL << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */
7417 #define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk
7418
7419 #define RCC_PLLCFGR_PLLQ_Pos (21U)
7420 #define RCC_PLLCFGR_PLLQ_Msk (0x3UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00600000 */
7421 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
7422 #define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00200000 */
7423 #define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00400000 */
7424
7425 #define RCC_PLLCFGR_PLLREN_Pos (24U)
7426 #define RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */
7427 #define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk
7428 #define RCC_PLLCFGR_PLLR_Pos (25U)
7429 #define RCC_PLLCFGR_PLLR_Msk (0x3UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x06000000 */
7430 #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
7431 #define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x02000000 */
7432 #define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x04000000 */
7433
7434 #define RCC_PLLCFGR_PLLPDIV_Pos (27U)
7435 #define RCC_PLLCFGR_PLLPDIV_Msk (0x1FUL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0xF8000000 */
7436 #define RCC_PLLCFGR_PLLPDIV RCC_PLLCFGR_PLLPDIV_Msk
7437 #define RCC_PLLCFGR_PLLPDIV_0 (0x01UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x08000000 */
7438 #define RCC_PLLCFGR_PLLPDIV_1 (0x02UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x10000000 */
7439 #define RCC_PLLCFGR_PLLPDIV_2 (0x04UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x20000000 */
7440 #define RCC_PLLCFGR_PLLPDIV_3 (0x08UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x40000000 */
7441 #define RCC_PLLCFGR_PLLPDIV_4 (0x10UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x80000000 */
7442
7443 /******************** Bit definition for RCC_CIER register ******************/
7444 #define RCC_CIER_LSIRDYIE_Pos (0U)
7445 #define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
7446 #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
7447 #define RCC_CIER_LSERDYIE_Pos (1U)
7448 #define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
7449 #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
7450 #define RCC_CIER_HSIRDYIE_Pos (3U)
7451 #define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */
7452 #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
7453 #define RCC_CIER_HSERDYIE_Pos (4U)
7454 #define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */
7455 #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
7456 #define RCC_CIER_PLLRDYIE_Pos (5U)
7457 #define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */
7458 #define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
7459 #define RCC_CIER_LSECSSIE_Pos (9U)
7460 #define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
7461 #define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
7462 #define RCC_CIER_HSI48RDYIE_Pos (10U)
7463 #define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos)/*!< 0x00000400 */
7464 #define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
7465
7466 /******************** Bit definition for RCC_CIFR register ******************/
7467 #define RCC_CIFR_LSIRDYF_Pos (0U)
7468 #define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
7469 #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
7470 #define RCC_CIFR_LSERDYF_Pos (1U)
7471 #define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
7472 #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
7473 #define RCC_CIFR_HSIRDYF_Pos (3U)
7474 #define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */
7475 #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
7476 #define RCC_CIFR_HSERDYF_Pos (4U)
7477 #define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */
7478 #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
7479 #define RCC_CIFR_PLLRDYF_Pos (5U)
7480 #define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */
7481 #define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
7482 #define RCC_CIFR_CSSF_Pos (8U)
7483 #define RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */
7484 #define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk
7485 #define RCC_CIFR_LSECSSF_Pos (9U)
7486 #define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
7487 #define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
7488 #define RCC_CIFR_HSI48RDYF_Pos (10U)
7489 #define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000400 */
7490 #define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
7491
7492 /******************** Bit definition for RCC_CICR register ******************/
7493 #define RCC_CICR_LSIRDYC_Pos (0U)
7494 #define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
7495 #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
7496 #define RCC_CICR_LSERDYC_Pos (1U)
7497 #define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
7498 #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
7499 #define RCC_CICR_HSIRDYC_Pos (3U)
7500 #define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */
7501 #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
7502 #define RCC_CICR_HSERDYC_Pos (4U)
7503 #define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */
7504 #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
7505 #define RCC_CICR_PLLRDYC_Pos (5U)
7506 #define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */
7507 #define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
7508 #define RCC_CICR_CSSC_Pos (8U)
7509 #define RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */
7510 #define RCC_CICR_CSSC RCC_CICR_CSSC_Msk
7511 #define RCC_CICR_LSECSSC_Pos (9U)
7512 #define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
7513 #define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
7514 #define RCC_CICR_HSI48RDYC_Pos (10U)
7515 #define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000400 */
7516 #define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
7517
7518 /******************** Bit definition for RCC_AHB1RSTR register **************/
7519 #define RCC_AHB1RSTR_DMA1RST_Pos (0U)
7520 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)/*!< 0x00000001 */
7521 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
7522 #define RCC_AHB1RSTR_DMA2RST_Pos (1U)
7523 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)/*!< 0x00000002 */
7524 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
7525 #define RCC_AHB1RSTR_DMAMUX1RST_Pos (2U)
7526 #define RCC_AHB1RSTR_DMAMUX1RST_Msk (0x1UL << RCC_AHB1RSTR_DMAMUX1RST_Pos)/*!< 0x00000004 */
7527 #define RCC_AHB1RSTR_DMAMUX1RST RCC_AHB1RSTR_DMAMUX1RST_Msk
7528 #define RCC_AHB1RSTR_CORDICRST_Pos (3U)
7529 #define RCC_AHB1RSTR_CORDICRST_Msk (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos)/*!< 0x00000008 */
7530 #define RCC_AHB1RSTR_CORDICRST RCC_AHB1RSTR_CORDICRST_Msk
7531 #define RCC_AHB1RSTR_FMACRST_Pos (4U)
7532 #define RCC_AHB1RSTR_FMACRST_Msk (0x1UL << RCC_AHB1RSTR_FMACRST_Pos) /*!< 0x00000010 */
7533 #define RCC_AHB1RSTR_FMACRST RCC_AHB1RSTR_FMACRST_Msk
7534 #define RCC_AHB1RSTR_FLASHRST_Pos (8U)
7535 #define RCC_AHB1RSTR_FLASHRST_Msk (0x1UL << RCC_AHB1RSTR_FLASHRST_Pos)/*!< 0x00000100 */
7536 #define RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk
7537 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
7538 #define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)/*!< 0x00001000 */
7539 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
7540
7541 /******************** Bit definition for RCC_AHB2RSTR register **************/
7542 #define RCC_AHB2RSTR_GPIOARST_Pos (0U)
7543 #define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)/*!< 0x00000001 */
7544 #define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk
7545 #define RCC_AHB2RSTR_GPIOBRST_Pos (1U)
7546 #define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)/*!< 0x00000002 */
7547 #define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk
7548 #define RCC_AHB2RSTR_GPIOCRST_Pos (2U)
7549 #define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)/*!< 0x00000004 */
7550 #define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk
7551 #define RCC_AHB2RSTR_GPIODRST_Pos (3U)
7552 #define RCC_AHB2RSTR_GPIODRST_Msk (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos)/*!< 0x00000008 */
7553 #define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk
7554 #define RCC_AHB2RSTR_GPIOERST_Pos (4U)
7555 #define RCC_AHB2RSTR_GPIOERST_Msk (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos)/*!< 0x00000010 */
7556 #define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk
7557 #define RCC_AHB2RSTR_GPIOFRST_Pos (5U)
7558 #define RCC_AHB2RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOFRST_Pos)/*!< 0x00000020 */
7559 #define RCC_AHB2RSTR_GPIOFRST RCC_AHB2RSTR_GPIOFRST_Msk
7560 #define RCC_AHB2RSTR_GPIOGRST_Pos (6U)
7561 #define RCC_AHB2RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOGRST_Pos)/*!< 0x00000040 */
7562 #define RCC_AHB2RSTR_GPIOGRST RCC_AHB2RSTR_GPIOGRST_Msk
7563 #define RCC_AHB2RSTR_ADC12RST_Pos (13U)
7564 #define RCC_AHB2RSTR_ADC12RST_Msk (0x1UL << RCC_AHB2RSTR_ADC12RST_Pos)/*!< 0x00002000 */
7565 #define RCC_AHB2RSTR_ADC12RST RCC_AHB2RSTR_ADC12RST_Msk
7566 #define RCC_AHB2RSTR_DAC1RST_Pos (16U)
7567 #define RCC_AHB2RSTR_DAC1RST_Msk (0x1UL << RCC_AHB2RSTR_DAC1RST_Pos)/*!< 0x00010000 */
7568 #define RCC_AHB2RSTR_DAC1RST RCC_AHB2RSTR_DAC1RST_Msk
7569 #define RCC_AHB2RSTR_DAC3RST_Pos (18U)
7570 #define RCC_AHB2RSTR_DAC3RST_Msk (0x1UL << RCC_AHB2RSTR_DAC3RST_Pos)/*!< 0x00040000 */
7571 #define RCC_AHB2RSTR_DAC3RST RCC_AHB2RSTR_DAC3RST_Msk
7572 #define RCC_AHB2RSTR_RNGRST_Pos (26U)
7573 #define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)/*!< 0x04000000 */
7574 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
7575
7576 /******************** Bit definition for RCC_AHB3RSTR register **************/
7577
7578 /******************** Bit definition for RCC_APB1RSTR1 register **************/
7579 #define RCC_APB1RSTR1_TIM2RST_Pos (0U)
7580 #define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)/*!< 0x00000001 */
7581 #define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk
7582 #define RCC_APB1RSTR1_TIM3RST_Pos (1U)
7583 #define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos)/*!< 0x00000002 */
7584 #define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk
7585 #define RCC_APB1RSTR1_TIM4RST_Pos (2U)
7586 #define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)/*!< 0x00000004 */
7587 #define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk
7588 #define RCC_APB1RSTR1_TIM6RST_Pos (4U)
7589 #define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)/*!< 0x00000010 */
7590 #define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk
7591 #define RCC_APB1RSTR1_TIM7RST_Pos (5U)
7592 #define RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)/*!< 0x00000020 */
7593 #define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk
7594 #define RCC_APB1RSTR1_CRSRST_Pos (8U)
7595 #define RCC_APB1RSTR1_CRSRST_Msk (0x1UL << RCC_APB1RSTR1_CRSRST_Pos)/*!< 0x00000100 */
7596 #define RCC_APB1RSTR1_CRSRST RCC_APB1RSTR1_CRSRST_Msk
7597 #define RCC_APB1RSTR1_SPI2RST_Pos (14U)
7598 #define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)/*!< 0x00004000 */
7599 #define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk
7600 #define RCC_APB1RSTR1_SPI3RST_Pos (15U)
7601 #define RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos)/*!< 0x00008000 */
7602 #define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk
7603 #define RCC_APB1RSTR1_USART2RST_Pos (17U)
7604 #define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */
7605 #define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk
7606 #define RCC_APB1RSTR1_USART3RST_Pos (18U)
7607 #define RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)/*!< 0x00040000 */
7608 #define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk
7609 #define RCC_APB1RSTR1_I2C1RST_Pos (21U)
7610 #define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)/*!< 0x00200000 */
7611 #define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk
7612 #define RCC_APB1RSTR1_I2C2RST_Pos (22U)
7613 #define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)/*!< 0x00400000 */
7614 #define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk
7615 #define RCC_APB1RSTR1_USBRST_Pos (23U)
7616 #define RCC_APB1RSTR1_USBRST_Msk (0x1UL << RCC_APB1RSTR1_USBRST_Pos)/*!< 0x00800000 */
7617 #define RCC_APB1RSTR1_USBRST RCC_APB1RSTR1_USBRST_Msk
7618 #define RCC_APB1RSTR1_FDCANRST_Pos (25U)
7619 #define RCC_APB1RSTR1_FDCANRST_Msk (0x1UL << RCC_APB1RSTR1_FDCANRST_Pos)/*!< 0x02000000 */
7620 #define RCC_APB1RSTR1_FDCANRST RCC_APB1RSTR1_FDCANRST_Msk
7621 #define RCC_APB1RSTR1_PWRRST_Pos (28U)
7622 #define RCC_APB1RSTR1_PWRRST_Msk (0x1UL << RCC_APB1RSTR1_PWRRST_Pos)/*!< 0x10000000 */
7623 #define RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk
7624 #define RCC_APB1RSTR1_I2C3RST_Pos (30U)
7625 #define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)/*!< 0x40000000 */
7626 #define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk
7627 #define RCC_APB1RSTR1_LPTIM1RST_Pos (31U)
7628 #define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x80000000 */
7629 #define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk
7630
7631 /******************** Bit definition for RCC_APB1RSTR2 register **************/
7632 #define RCC_APB1RSTR2_LPUART1RST_Pos (0U)
7633 #define RCC_APB1RSTR2_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)/*!< 0x00000001 */
7634 #define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk
7635 #define RCC_APB1RSTR2_UCPD1RST_Pos (8U)
7636 #define RCC_APB1RSTR2_UCPD1RST_Msk (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos)/*!< 0x00000100 */
7637 #define RCC_APB1RSTR2_UCPD1RST RCC_APB1RSTR2_UCPD1RST_Msk
7638
7639 /******************** Bit definition for RCC_APB2RSTR register **************/
7640 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
7641 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)/*!< 0x00000001 */
7642 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
7643 #define RCC_APB2RSTR_TIM1RST_Pos (11U)
7644 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)/*!< 0x00000800 */
7645 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
7646 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
7647 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)/*!< 0x00001000 */
7648 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
7649 #define RCC_APB2RSTR_TIM8RST_Pos (13U)
7650 #define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)/*!< 0x00002000 */
7651 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
7652 #define RCC_APB2RSTR_USART1RST_Pos (14U)
7653 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)/*!< 0x00004000 */
7654 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
7655 #define RCC_APB2RSTR_TIM15RST_Pos (16U)
7656 #define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)/*!< 0x00010000 */
7657 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
7658 #define RCC_APB2RSTR_TIM16RST_Pos (17U)
7659 #define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)/*!< 0x00020000 */
7660 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
7661 #define RCC_APB2RSTR_TIM17RST_Pos (18U)
7662 #define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)/*!< 0x00040000 */
7663 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
7664 #define RCC_APB2RSTR_SAI1RST_Pos (21U)
7665 #define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)/*!< 0x00200000 */
7666 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
7667
7668 /******************** Bit definition for RCC_AHB1ENR register ***************/
7669 #define RCC_AHB1ENR_DMA1EN_Pos (0U)
7670 #define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
7671 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
7672 #define RCC_AHB1ENR_DMA2EN_Pos (1U)
7673 #define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
7674 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
7675 #define RCC_AHB1ENR_DMAMUX1EN_Pos (2U)
7676 #define RCC_AHB1ENR_DMAMUX1EN_Msk (0x1UL << RCC_AHB1ENR_DMAMUX1EN_Pos)/*!< 0x00000004 */
7677 #define RCC_AHB1ENR_DMAMUX1EN RCC_AHB1ENR_DMAMUX1EN_Msk
7678 #define RCC_AHB1ENR_CORDICEN_Pos (3U)
7679 #define RCC_AHB1ENR_CORDICEN_Msk (0x1UL << RCC_AHB1ENR_CORDICEN_Pos)/*!< 0x00000008 */
7680 #define RCC_AHB1ENR_CORDICEN RCC_AHB1ENR_CORDICEN_Msk
7681 #define RCC_AHB1ENR_FMACEN_Pos (4U)
7682 #define RCC_AHB1ENR_FMACEN_Msk (0x1UL << RCC_AHB1ENR_FMACEN_Pos) /*!< 0x00000010 */
7683 #define RCC_AHB1ENR_FMACEN RCC_AHB1ENR_FMACEN_Msk
7684 #define RCC_AHB1ENR_FLASHEN_Pos (8U)
7685 #define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos)/*!< 0x00000100 */
7686 #define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk
7687 #define RCC_AHB1ENR_CRCEN_Pos (12U)
7688 #define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
7689 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
7690
7691 /******************** Bit definition for RCC_AHB2ENR register ***************/
7692 #define RCC_AHB2ENR_GPIOAEN_Pos (0U)
7693 #define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos)/*!< 0x00000001 */
7694 #define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk
7695 #define RCC_AHB2ENR_GPIOBEN_Pos (1U)
7696 #define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos)/*!< 0x00000002 */
7697 #define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk
7698 #define RCC_AHB2ENR_GPIOCEN_Pos (2U)
7699 #define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos)/*!< 0x00000004 */
7700 #define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk
7701 #define RCC_AHB2ENR_GPIODEN_Pos (3U)
7702 #define RCC_AHB2ENR_GPIODEN_Msk (0x1UL << RCC_AHB2ENR_GPIODEN_Pos)/*!< 0x00000008 */
7703 #define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk
7704 #define RCC_AHB2ENR_GPIOEEN_Pos (4U)
7705 #define RCC_AHB2ENR_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos)/*!< 0x00000010 */
7706 #define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk
7707 #define RCC_AHB2ENR_GPIOFEN_Pos (5U)
7708 #define RCC_AHB2ENR_GPIOFEN_Msk (0x1UL << RCC_AHB2ENR_GPIOFEN_Pos)/*!< 0x00000020 */
7709 #define RCC_AHB2ENR_GPIOFEN RCC_AHB2ENR_GPIOFEN_Msk
7710 #define RCC_AHB2ENR_GPIOGEN_Pos (6U)
7711 #define RCC_AHB2ENR_GPIOGEN_Msk (0x1UL << RCC_AHB2ENR_GPIOGEN_Pos)/*!< 0x00000040 */
7712 #define RCC_AHB2ENR_GPIOGEN RCC_AHB2ENR_GPIOGEN_Msk
7713 #define RCC_AHB2ENR_ADC12EN_Pos (13U)
7714 #define RCC_AHB2ENR_ADC12EN_Msk (0x1UL << RCC_AHB2ENR_ADC12EN_Pos) /*!< 0x00002000 */
7715 #define RCC_AHB2ENR_ADC12EN RCC_AHB2ENR_ADC12EN_Msk
7716 #define RCC_AHB2ENR_DAC1EN_Pos (16U)
7717 #define RCC_AHB2ENR_DAC1EN_Msk (0x1UL << RCC_AHB2ENR_DAC1EN_Pos) /*!< 0x00010000 */
7718 #define RCC_AHB2ENR_DAC1EN RCC_AHB2ENR_DAC1EN_Msk
7719 #define RCC_AHB2ENR_DAC3EN_Pos (18U)
7720 #define RCC_AHB2ENR_DAC3EN_Msk (0x1UL << RCC_AHB2ENR_DAC3EN_Pos) /*!< 0x00040000 */
7721 #define RCC_AHB2ENR_DAC3EN RCC_AHB2ENR_DAC3EN_Msk
7722 #define RCC_AHB2ENR_RNGEN_Pos (26U)
7723 #define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x04000000 */
7724 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
7725
7726 /******************** Bit definition for RCC_AHB3ENR register ***************/
7727
7728 /******************** Bit definition for RCC_APB1ENR1 register ***************/
7729 #define RCC_APB1ENR1_TIM2EN_Pos (0U)
7730 #define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)/*!< 0x00000001 */
7731 #define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk
7732 #define RCC_APB1ENR1_TIM3EN_Pos (1U)
7733 #define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos)/*!< 0x00000002 */
7734 #define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk
7735 #define RCC_APB1ENR1_TIM4EN_Pos (2U)
7736 #define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)/*!< 0x00000004 */
7737 #define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk
7738 #define RCC_APB1ENR1_TIM6EN_Pos (4U)
7739 #define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)/*!< 0x00000010 */
7740 #define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk
7741 #define RCC_APB1ENR1_TIM7EN_Pos (5U)
7742 #define RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)/*!< 0x00000020 */
7743 #define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk
7744 #define RCC_APB1ENR1_CRSEN_Pos (8U)
7745 #define RCC_APB1ENR1_CRSEN_Msk (0x1UL << RCC_APB1ENR1_CRSEN_Pos) /*!< 0x00000100 */
7746 #define RCC_APB1ENR1_CRSEN RCC_APB1ENR1_CRSEN_Msk
7747 #define RCC_APB1ENR1_RTCAPBEN_Pos (10U)
7748 #define RCC_APB1ENR1_RTCAPBEN_Msk (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos)/*!< 0x00000400 */
7749 #define RCC_APB1ENR1_RTCAPBEN RCC_APB1ENR1_RTCAPBEN_Msk
7750 #define RCC_APB1ENR1_WWDGEN_Pos (11U)
7751 #define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)/*!< 0x00000800 */
7752 #define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk
7753 #define RCC_APB1ENR1_SPI2EN_Pos (14U)
7754 #define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)/*!< 0x00004000 */
7755 #define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk
7756 #define RCC_APB1ENR1_SPI3EN_Pos (15U)
7757 #define RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos)/*!< 0x00008000 */
7758 #define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk
7759 #define RCC_APB1ENR1_USART2EN_Pos (17U)
7760 #define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos)/*!< 0x00020000 */
7761 #define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk
7762 #define RCC_APB1ENR1_USART3EN_Pos (18U)
7763 #define RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos)/*!< 0x00040000 */
7764 #define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk
7765 #define RCC_APB1ENR1_I2C1EN_Pos (21U)
7766 #define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)/*!< 0x00200000 */
7767 #define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk
7768 #define RCC_APB1ENR1_I2C2EN_Pos (22U)
7769 #define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)/*!< 0x00400000 */
7770 #define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk
7771 #define RCC_APB1ENR1_USBEN_Pos (23U)
7772 #define RCC_APB1ENR1_USBEN_Msk (0x1UL << RCC_APB1ENR1_USBEN_Pos)/*!< 0x00800000 */
7773 #define RCC_APB1ENR1_USBEN RCC_APB1ENR1_USBEN_Msk
7774 #define RCC_APB1ENR1_FDCANEN_Pos (25U)
7775 #define RCC_APB1ENR1_FDCANEN_Msk (0x1UL << RCC_APB1ENR1_FDCANEN_Pos)/*!< 0x02000000 */
7776 #define RCC_APB1ENR1_FDCANEN RCC_APB1ENR1_FDCANEN_Msk
7777 #define RCC_APB1ENR1_PWREN_Pos (28U)
7778 #define RCC_APB1ENR1_PWREN_Msk (0x1UL << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */
7779 #define RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk
7780 #define RCC_APB1ENR1_I2C3EN_Pos (30U)
7781 #define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos)/*!< 0x40000000 */
7782 #define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk
7783 #define RCC_APB1ENR1_LPTIM1EN_Pos (31U)
7784 #define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)/*!< 0x80000000 */
7785 #define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk
7786
7787 /******************** Bit definition for RCC_APB1RSTR2 register **************/
7788 #define RCC_APB1ENR2_LPUART1EN_Pos (0U)
7789 #define RCC_APB1ENR2_LPUART1EN_Msk (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)/*!< 0x00000001 */
7790 #define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk
7791 #define RCC_APB1ENR2_UCPD1EN_Pos (8U)
7792 #define RCC_APB1ENR2_UCPD1EN_Msk (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos)/*!< 0x00000100 */
7793 #define RCC_APB1ENR2_UCPD1EN RCC_APB1ENR2_UCPD1EN_Msk
7794
7795 /******************** Bit definition for RCC_APB2ENR register ***************/
7796 #define RCC_APB2ENR_SYSCFGEN_Pos (0U)
7797 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)/*!< 0x00000001 */
7798 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
7799 #define RCC_APB2ENR_TIM1EN_Pos (11U)
7800 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
7801 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
7802 #define RCC_APB2ENR_SPI1EN_Pos (12U)
7803 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
7804 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
7805 #define RCC_APB2ENR_TIM8EN_Pos (13U)
7806 #define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */
7807 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
7808 #define RCC_APB2ENR_USART1EN_Pos (14U)
7809 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)/*!< 0x00004000 */
7810 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
7811 #define RCC_APB2ENR_TIM15EN_Pos (16U)
7812 #define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos)/*!< 0x00010000 */
7813 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
7814 #define RCC_APB2ENR_TIM16EN_Pos (17U)
7815 #define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos)/*!< 0x00020000 */
7816 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
7817 #define RCC_APB2ENR_TIM17EN_Pos (18U)
7818 #define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)/*!< 0x00040000 */
7819 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
7820 #define RCC_APB2ENR_SAI1EN_Pos (21U)
7821 #define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)/*!< 0x00200000 */
7822 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
7823
7824 /******************** Bit definition for RCC_AHB1SMENR register ***************/
7825 #define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
7826 #define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)/*!< 0x00000001 */
7827 #define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk
7828 #define RCC_AHB1SMENR_DMA2SMEN_Pos (1U)
7829 #define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)/*!< 0x00000002 */
7830 #define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk
7831 #define RCC_AHB1SMENR_DMAMUX1SMEN_Pos (2U)
7832 #define RCC_AHB1SMENR_DMAMUX1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMAMUX1SMEN_Pos)/*!< 0x00000004 */
7833 #define RCC_AHB1SMENR_DMAMUX1SMEN RCC_AHB1SMENR_DMAMUX1SMEN_Msk
7834 #define RCC_AHB1SMENR_CORDICSMEN_Pos (3U)
7835 #define RCC_AHB1SMENR_CORDICSMEN_Msk (0x1UL << RCC_AHB1SMENR_CORDICSMEN_Pos)/*!< 0x00000008 */
7836 #define RCC_AHB1SMENR_CORDICSMEN RCC_AHB1SMENR_CORDICSMEN_Msk
7837 #define RCC_AHB1SMENR_FMACSMEN_Pos (4U)
7838 #define RCC_AHB1SMENR_FMACSMEN_Msk (0x1UL << RCC_AHB1SMENR_FMACSMEN_Pos) /*!< 0x00000010 */
7839 #define RCC_AHB1SMENR_FMACSMEN RCC_AHB1SMENR_FMACSMEN_Msk
7840 #define RCC_AHB1SMENR_FLASHSMEN_Pos (8U)
7841 #define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos)/*!< 0x00000100 */
7842 #define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk
7843 #define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U)
7844 #define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos)/*!< 0x00000200 */
7845 #define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk
7846 #define RCC_AHB1SMENR_CRCSMEN_Pos (12U)
7847 #define RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)/*!< 0x00001000 */
7848 #define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk
7849
7850 /******************** Bit definition for RCC_AHB2SMENR register *************/
7851 #define RCC_AHB2SMENR_GPIOASMEN_Pos (0U)
7852 #define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)/*!< 0x00000001 */
7853 #define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk
7854 #define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U)
7855 #define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)/*!< 0x00000002 */
7856 #define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk
7857 #define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U)
7858 #define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)/*!< 0x00000004 */
7859 #define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk
7860 #define RCC_AHB2SMENR_GPIODSMEN_Pos (3U)
7861 #define RCC_AHB2SMENR_GPIODSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIODSMEN_Pos)/*!< 0x00000008 */
7862 #define RCC_AHB2SMENR_GPIODSMEN RCC_AHB2SMENR_GPIODSMEN_Msk
7863 #define RCC_AHB2SMENR_GPIOESMEN_Pos (4U)
7864 #define RCC_AHB2SMENR_GPIOESMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOESMEN_Pos)/*!< 0x00000010 */
7865 #define RCC_AHB2SMENR_GPIOESMEN RCC_AHB2SMENR_GPIOESMEN_Msk
7866 #define RCC_AHB2SMENR_GPIOFSMEN_Pos (5U)
7867 #define RCC_AHB2SMENR_GPIOFSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOFSMEN_Pos)/*!< 0x00000020 */
7868 #define RCC_AHB2SMENR_GPIOFSMEN RCC_AHB2SMENR_GPIOFSMEN_Msk
7869 #define RCC_AHB2SMENR_GPIOGSMEN_Pos (6U)
7870 #define RCC_AHB2SMENR_GPIOGSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOGSMEN_Pos)/*!< 0x00000040 */
7871 #define RCC_AHB2SMENR_GPIOGSMEN RCC_AHB2SMENR_GPIOGSMEN_Msk
7872 #define RCC_AHB2SMENR_CCMSRAMSMEN_Pos (9U)
7873 #define RCC_AHB2SMENR_CCMSRAMSMEN_Msk (0x1UL << RCC_AHB2SMENR_CCMSRAMSMEN_Pos) /*!< 0x00000200 */
7874 #define RCC_AHB2SMENR_CCMSRAMSMEN RCC_AHB2SMENR_CCMSRAMSMEN_Msk
7875 #define RCC_AHB2SMENR_SRAM2SMEN_Pos (10U)
7876 #define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos)/*!< 0x00000400 */
7877 #define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk
7878 #define RCC_AHB2SMENR_ADC12SMEN_Pos (13U)
7879 #define RCC_AHB2SMENR_ADC12SMEN_Msk (0x1UL << RCC_AHB2SMENR_ADC12SMEN_Pos)/*!< 0x00002000 */
7880 #define RCC_AHB2SMENR_ADC12SMEN RCC_AHB2SMENR_ADC12SMEN_Msk
7881 #define RCC_AHB2SMENR_DAC1SMEN_Pos (16U)
7882 #define RCC_AHB2SMENR_DAC1SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC1SMEN_Pos)/*!< 0x00010000 */
7883 #define RCC_AHB2SMENR_DAC1SMEN RCC_AHB2SMENR_DAC1SMEN_Msk
7884 #define RCC_AHB2SMENR_DAC3SMEN_Pos (18U)
7885 #define RCC_AHB2SMENR_DAC3SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC3SMEN_Pos)/*!< 0x00040000 */
7886 #define RCC_AHB2SMENR_DAC3SMEN RCC_AHB2SMENR_DAC3SMEN_Msk
7887 #define RCC_AHB2SMENR_RNGSMEN_Pos (26U)
7888 #define RCC_AHB2SMENR_RNGSMEN_Msk (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos)/*!< 0x04000000 */
7889 #define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk
7890
7891 /******************** Bit definition for RCC_AHB3SMENR register *************/
7892
7893 /******************** Bit definition for RCC_APB1SMENR1 register *************/
7894 #define RCC_APB1SMENR1_TIM2SMEN_Pos (0U)
7895 #define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)/*!< 0x00000001 */
7896 #define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk
7897 #define RCC_APB1SMENR1_TIM3SMEN_Pos (1U)
7898 #define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos)/*!< 0x00000002 */
7899 #define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk
7900 #define RCC_APB1SMENR1_TIM4SMEN_Pos (2U)
7901 #define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos)/*!< 0x00000004 */
7902 #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk
7903 #define RCC_APB1SMENR1_TIM6SMEN_Pos (4U)
7904 #define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos)/*!< 0x00000010 */
7905 #define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk
7906 #define RCC_APB1SMENR1_TIM7SMEN_Pos (5U)
7907 #define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos)/*!< 0x00000020 */
7908 #define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk
7909 #define RCC_APB1SMENR1_CRSSMEN_Pos (8U)
7910 #define RCC_APB1SMENR1_CRSSMEN_Msk (0x1UL << RCC_APB1SMENR1_CRSSMEN_Pos)/*!< 0x00000100 */
7911 #define RCC_APB1SMENR1_CRSSMEN RCC_APB1SMENR1_CRSSMEN_Msk
7912 #define RCC_APB1SMENR1_RTCAPBSMEN_Pos (10U)
7913 #define RCC_APB1SMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos)/*!< 0x00000400 */
7914 #define RCC_APB1SMENR1_RTCAPBSMEN RCC_APB1SMENR1_RTCAPBSMEN_Msk
7915 #define RCC_APB1SMENR1_WWDGSMEN_Pos (11U)
7916 #define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)/*!< 0x00000800 */
7917 #define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk
7918 #define RCC_APB1SMENR1_SPI2SMEN_Pos (14U)
7919 #define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)/*!< 0x00004000 */
7920 #define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk
7921 #define RCC_APB1SMENR1_SPI3SMEN_Pos (15U)
7922 #define RCC_APB1SMENR1_SPI3SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI3SMEN_Pos)/*!< 0x00008000 */
7923 #define RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk
7924 #define RCC_APB1SMENR1_USART2SMEN_Pos (17U)
7925 #define RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)/*!< 0x00020000 */
7926 #define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk
7927 #define RCC_APB1SMENR1_USART3SMEN_Pos (18U)
7928 #define RCC_APB1SMENR1_USART3SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos)/*!< 0x00040000 */
7929 #define RCC_APB1SMENR1_USART3SMEN RCC_APB1SMENR1_USART3SMEN_Msk
7930 #define RCC_APB1SMENR1_I2C1SMEN_Pos (21U)
7931 #define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)/*!< 0x00200000 */
7932 #define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk
7933 #define RCC_APB1SMENR1_I2C2SMEN_Pos (22U)
7934 #define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)/*!< 0x00400000 */
7935 #define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk
7936 #define RCC_APB1SMENR1_USBSMEN_Pos (23U)
7937 #define RCC_APB1SMENR1_USBSMEN_Msk (0x1UL << RCC_APB1SMENR1_USBSMEN_Pos)/*!< 0x00800000 */
7938 #define RCC_APB1SMENR1_USBSMEN RCC_APB1SMENR1_USBSMEN_Msk
7939 #define RCC_APB1SMENR1_FDCANSMEN_Pos (25U)
7940 #define RCC_APB1SMENR1_FDCANSMEN_Msk (0x1UL << RCC_APB1SMENR1_FDCANSMEN_Pos)/*!< 0x02000000 */
7941 #define RCC_APB1SMENR1_FDCANSMEN RCC_APB1SMENR1_FDCANSMEN_Msk
7942 #define RCC_APB1SMENR1_PWRSMEN_Pos (28U)
7943 #define RCC_APB1SMENR1_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR1_PWRSMEN_Pos)/*!< 0x10000000 */
7944 #define RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk
7945 #define RCC_APB1SMENR1_I2C3SMEN_Pos (30U)
7946 #define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos)/*!< 0x40000000 */
7947 #define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk
7948 #define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U)
7949 #define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)/*!< 0x80000000 */
7950 #define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk
7951
7952 /******************** Bit definition for RCC_APB1SMENR2 register *************/
7953 #define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U)
7954 #define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)/*!< 0x00000001 */
7955 #define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk
7956 #define RCC_APB1SMENR2_UCPD1SMEN_Pos (8U)
7957 #define RCC_APB1SMENR2_UCPD1SMEN_Msk (0x1UL << RCC_APB1SMENR2_UCPD1SMEN_Pos)/*!< 0x00000100 */
7958 #define RCC_APB1SMENR2_UCPD1SMEN RCC_APB1SMENR2_UCPD1SMEN_Msk
7959
7960 /******************** Bit definition for RCC_APB2SMENR register *************/
7961 #define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
7962 #define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos)/*!< 0x00000001 */
7963 #define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk
7964 #define RCC_APB2SMENR_TIM1SMEN_Pos (11U)
7965 #define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)/*!< 0x00000800 */
7966 #define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk
7967 #define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
7968 #define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)/*!< 0x00001000 */
7969 #define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk
7970 #define RCC_APB2SMENR_TIM8SMEN_Pos (13U)
7971 #define RCC_APB2SMENR_TIM8SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM8SMEN_Pos)/*!< 0x00002000 */
7972 #define RCC_APB2SMENR_TIM8SMEN RCC_APB2SMENR_TIM8SMEN_Msk
7973 #define RCC_APB2SMENR_USART1SMEN_Pos (14U)
7974 #define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)/*!< 0x00004000 */
7975 #define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk
7976 #define RCC_APB2SMENR_TIM15SMEN_Pos (16U)
7977 #define RCC_APB2SMENR_TIM15SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos)/*!< 0x00010000 */
7978 #define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk
7979 #define RCC_APB2SMENR_TIM16SMEN_Pos (17U)
7980 #define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)/*!< 0x00020000 */
7981 #define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk
7982 #define RCC_APB2SMENR_TIM17SMEN_Pos (18U)
7983 #define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */
7984 #define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk
7985 #define RCC_APB2SMENR_SAI1SMEN_Pos (21U)
7986 #define RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos)/*!< 0x00200000 */
7987 #define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk
7988
7989 /******************** Bit definition for RCC_CCIPR register ******************/
7990 #define RCC_CCIPR_USART1SEL_Pos (0U)
7991 #define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000003 */
7992 #define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk
7993 #define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000001 */
7994 #define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000002 */
7995
7996 #define RCC_CCIPR_USART2SEL_Pos (2U)
7997 #define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x0000000C */
7998 #define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk
7999 #define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000004 */
8000 #define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000008 */
8001
8002 #define RCC_CCIPR_USART3SEL_Pos (4U)
8003 #define RCC_CCIPR_USART3SEL_Msk (0x3UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000030 */
8004 #define RCC_CCIPR_USART3SEL RCC_CCIPR_USART3SEL_Msk
8005 #define RCC_CCIPR_USART3SEL_0 (0x1UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000010 */
8006 #define RCC_CCIPR_USART3SEL_1 (0x2UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000020 */
8007
8008
8009
8010 #define RCC_CCIPR_LPUART1SEL_Pos (10U)
8011 #define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000C00 */
8012 #define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk
8013 #define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000400 */
8014 #define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000800 */
8015
8016 #define RCC_CCIPR_I2C1SEL_Pos (12U)
8017 #define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
8018 #define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk
8019 #define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
8020 #define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
8021
8022 #define RCC_CCIPR_I2C2SEL_Pos (14U)
8023 #define RCC_CCIPR_I2C2SEL_Msk (0x3UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x0000C000 */
8024 #define RCC_CCIPR_I2C2SEL RCC_CCIPR_I2C2SEL_Msk
8025 #define RCC_CCIPR_I2C2SEL_0 (0x1UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00004000 */
8026 #define RCC_CCIPR_I2C2SEL_1 (0x2UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00008000 */
8027
8028 #define RCC_CCIPR_I2C3SEL_Pos (16U)
8029 #define RCC_CCIPR_I2C3SEL_Msk (0x3UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */
8030 #define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk
8031 #define RCC_CCIPR_I2C3SEL_0 (0x1UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */
8032 #define RCC_CCIPR_I2C3SEL_1 (0x2UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */
8033
8034 #define RCC_CCIPR_LPTIM1SEL_Pos (18U)
8035 #define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x000C0000 */
8036 #define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk
8037 #define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00040000 */
8038 #define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00080000 */
8039
8040 #define RCC_CCIPR_SAI1SEL_Pos (20U)
8041 #define RCC_CCIPR_SAI1SEL_Msk (0x3UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00300000 */
8042 #define RCC_CCIPR_SAI1SEL RCC_CCIPR_SAI1SEL_Msk
8043 #define RCC_CCIPR_SAI1SEL_0 (0x1UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00100000 */
8044 #define RCC_CCIPR_SAI1SEL_1 (0x2UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00200000 */
8045
8046 #define RCC_CCIPR_I2S23SEL_Pos (22U)
8047 #define RCC_CCIPR_I2S23SEL_Msk (0x3UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00C00000 */
8048 #define RCC_CCIPR_I2S23SEL RCC_CCIPR_I2S23SEL_Msk
8049 #define RCC_CCIPR_I2S23SEL_0 (0x1UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00400000 */
8050 #define RCC_CCIPR_I2S23SEL_1 (0x2UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00800000 */
8051
8052 #define RCC_CCIPR_FDCANSEL_Pos (24U)
8053 #define RCC_CCIPR_FDCANSEL_Msk (0x3UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x03000000 */
8054 #define RCC_CCIPR_FDCANSEL RCC_CCIPR_FDCANSEL_Msk
8055 #define RCC_CCIPR_FDCANSEL_0 (0x1UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x01000000 */
8056 #define RCC_CCIPR_FDCANSEL_1 (0x2UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x02000000 */
8057
8058 #define RCC_CCIPR_CLK48SEL_Pos (26U)
8059 #define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */
8060 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
8061 #define RCC_CCIPR_CLK48SEL_0 (0x1UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */
8062 #define RCC_CCIPR_CLK48SEL_1 (0x2UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */
8063
8064 #define RCC_CCIPR_ADC12SEL_Pos (28U)
8065 #define RCC_CCIPR_ADC12SEL_Msk (0x3UL << RCC_CCIPR_ADC12SEL_Pos) /*!< 0x30000000 */
8066 #define RCC_CCIPR_ADC12SEL RCC_CCIPR_ADC12SEL_Msk
8067 #define RCC_CCIPR_ADC12SEL_0 (0x1UL << RCC_CCIPR_ADC12SEL_Pos) /*!< 0x10000000 */
8068 #define RCC_CCIPR_ADC12SEL_1 (0x2UL << RCC_CCIPR_ADC12SEL_Pos) /*!< 0x20000000 */
8069
8070
8071 /******************** Bit definition for RCC_BDCR register ******************/
8072 #define RCC_BDCR_LSEON_Pos (0U)
8073 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
8074 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
8075 #define RCC_BDCR_LSERDY_Pos (1U)
8076 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
8077 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
8078 #define RCC_BDCR_LSEBYP_Pos (2U)
8079 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
8080 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
8081
8082 #define RCC_BDCR_LSEDRV_Pos (3U)
8083 #define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
8084 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
8085 #define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
8086 #define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
8087
8088 #define RCC_BDCR_LSECSSON_Pos (5U)
8089 #define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
8090 #define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
8091 #define RCC_BDCR_LSECSSD_Pos (6U)
8092 #define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
8093 #define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
8094
8095 #define RCC_BDCR_RTCSEL_Pos (8U)
8096 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
8097 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
8098 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
8099 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
8100
8101 #define RCC_BDCR_RTCEN_Pos (15U)
8102 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
8103 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
8104 #define RCC_BDCR_BDRST_Pos (16U)
8105 #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
8106 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
8107 #define RCC_BDCR_LSCOEN_Pos (24U)
8108 #define RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */
8109 #define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk
8110 #define RCC_BDCR_LSCOSEL_Pos (25U)
8111 #define RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */
8112 #define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk
8113
8114 /******************** Bit definition for RCC_CSR register *******************/
8115 #define RCC_CSR_LSION_Pos (0U)
8116 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
8117 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
8118 #define RCC_CSR_LSIRDY_Pos (1U)
8119 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
8120 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
8121
8122 #define RCC_CSR_RMVF_Pos (23U)
8123 #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
8124 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
8125 #define RCC_CSR_OBLRSTF_Pos (25U)
8126 #define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
8127 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
8128 #define RCC_CSR_PINRSTF_Pos (26U)
8129 #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
8130 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
8131 #define RCC_CSR_BORRSTF_Pos (27U)
8132 #define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */
8133 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
8134 #define RCC_CSR_SFTRSTF_Pos (28U)
8135 #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
8136 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
8137 #define RCC_CSR_IWDGRSTF_Pos (29U)
8138 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
8139 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
8140 #define RCC_CSR_WWDGRSTF_Pos (30U)
8141 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
8142 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
8143 #define RCC_CSR_LPWRRSTF_Pos (31U)
8144 #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
8145 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
8146
8147 /******************** Bit definition for RCC_CRRCR register *****************/
8148 #define RCC_CRRCR_HSI48ON_Pos (0U)
8149 #define RCC_CRRCR_HSI48ON_Msk (0x1UL << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */
8150 #define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk
8151 #define RCC_CRRCR_HSI48RDY_Pos (1U)
8152 #define RCC_CRRCR_HSI48RDY_Msk (0x1UL << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
8153 #define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk
8154
8155 /*!< HSI48CAL configuration */
8156 #define RCC_CRRCR_HSI48CAL_Pos (7U)
8157 #define RCC_CRRCR_HSI48CAL_Msk (0x1FFUL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x0000FF80 */
8158 #define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[8:0] bits */
8159 #define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000080 */
8160 #define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000100 */
8161 #define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000200 */
8162 #define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000400 */
8163 #define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000800 */
8164 #define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00001000 */
8165 #define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00002000 */
8166 #define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00004000 */
8167 #define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00008000 */
8168
8169 /******************** Bit definition for RCC_CCIPR2 register ******************/
8170
8171
8172 /******************************************************************************/
8173 /* */
8174 /* RNG */
8175 /* */
8176 /******************************************************************************/
8177 /******************** Bits definition for RNG_CR register *******************/
8178 #define RNG_CR_RNGEN_Pos (2U)
8179 #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
8180 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
8181 #define RNG_CR_IE_Pos (3U)
8182 #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
8183 #define RNG_CR_IE RNG_CR_IE_Msk
8184 #define RNG_CR_CED_Pos (5U)
8185 #define RNG_CR_CED_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000020 */
8186 #define RNG_CR_CED RNG_CR_IE_Msk
8187
8188 /******************** Bits definition for RNG_SR register *******************/
8189 #define RNG_SR_DRDY_Pos (0U)
8190 #define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
8191 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
8192 #define RNG_SR_CECS_Pos (1U)
8193 #define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
8194 #define RNG_SR_CECS RNG_SR_CECS_Msk
8195 #define RNG_SR_SECS_Pos (2U)
8196 #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
8197 #define RNG_SR_SECS RNG_SR_SECS_Msk
8198 #define RNG_SR_CEIS_Pos (5U)
8199 #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
8200 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
8201 #define RNG_SR_SEIS_Pos (6U)
8202 #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
8203 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
8204
8205 /******************************************************************************/
8206 /* */
8207 /* Real-Time Clock (RTC) */
8208 /* */
8209 /******************************************************************************/
8210
8211 /******************** Bits definition for RTC_TR register *******************/
8212 #define RTC_TR_PM_Pos (22U)
8213 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
8214 #define RTC_TR_PM RTC_TR_PM_Msk
8215 #define RTC_TR_HT_Pos (20U)
8216 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
8217 #define RTC_TR_HT RTC_TR_HT_Msk
8218 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
8219 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
8220 #define RTC_TR_HU_Pos (16U)
8221 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
8222 #define RTC_TR_HU RTC_TR_HU_Msk
8223 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
8224 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
8225 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
8226 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
8227 #define RTC_TR_MNT_Pos (12U)
8228 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
8229 #define RTC_TR_MNT RTC_TR_MNT_Msk
8230 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
8231 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
8232 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
8233 #define RTC_TR_MNU_Pos (8U)
8234 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
8235 #define RTC_TR_MNU RTC_TR_MNU_Msk
8236 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
8237 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
8238 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
8239 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
8240 #define RTC_TR_ST_Pos (4U)
8241 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
8242 #define RTC_TR_ST RTC_TR_ST_Msk
8243 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
8244 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
8245 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
8246 #define RTC_TR_SU_Pos (0U)
8247 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
8248 #define RTC_TR_SU RTC_TR_SU_Msk
8249 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
8250 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
8251 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
8252 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
8253
8254 /******************** Bits definition for RTC_DR register *******************/
8255 #define RTC_DR_YT_Pos (20U)
8256 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
8257 #define RTC_DR_YT RTC_DR_YT_Msk
8258 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
8259 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
8260 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
8261 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
8262 #define RTC_DR_YU_Pos (16U)
8263 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
8264 #define RTC_DR_YU RTC_DR_YU_Msk
8265 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
8266 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
8267 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
8268 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
8269 #define RTC_DR_WDU_Pos (13U)
8270 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
8271 #define RTC_DR_WDU RTC_DR_WDU_Msk
8272 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
8273 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
8274 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
8275 #define RTC_DR_MT_Pos (12U)
8276 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
8277 #define RTC_DR_MT RTC_DR_MT_Msk
8278 #define RTC_DR_MU_Pos (8U)
8279 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
8280 #define RTC_DR_MU RTC_DR_MU_Msk
8281 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
8282 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
8283 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
8284 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
8285 #define RTC_DR_DT_Pos (4U)
8286 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
8287 #define RTC_DR_DT RTC_DR_DT_Msk
8288 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
8289 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
8290 #define RTC_DR_DU_Pos (0U)
8291 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
8292 #define RTC_DR_DU RTC_DR_DU_Msk
8293 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
8294 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
8295 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
8296 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
8297
8298 /******************** Bits definition for RTC_SSR register ******************/
8299 #define RTC_SSR_SS_Pos (0U)
8300 #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
8301 #define RTC_SSR_SS RTC_SSR_SS_Msk
8302
8303 /******************** Bits definition for RTC_ICSR register ******************/
8304 #define RTC_ICSR_RECALPF_Pos (16U)
8305 #define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */
8306 #define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk
8307 #define RTC_ICSR_INIT_Pos (7U)
8308 #define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */
8309 #define RTC_ICSR_INIT RTC_ICSR_INIT_Msk
8310 #define RTC_ICSR_INITF_Pos (6U)
8311 #define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */
8312 #define RTC_ICSR_INITF RTC_ICSR_INITF_Msk
8313 #define RTC_ICSR_RSF_Pos (5U)
8314 #define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */
8315 #define RTC_ICSR_RSF RTC_ICSR_RSF_Msk
8316 #define RTC_ICSR_INITS_Pos (4U)
8317 #define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */
8318 #define RTC_ICSR_INITS RTC_ICSR_INITS_Msk
8319 #define RTC_ICSR_SHPF_Pos (3U)
8320 #define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */
8321 #define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk
8322 #define RTC_ICSR_WUTWF_Pos (2U)
8323 #define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */
8324 #define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk
8325 #define RTC_ICSR_ALRBWF_Pos (1U)
8326 #define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */
8327 #define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk
8328 #define RTC_ICSR_ALRAWF_Pos (0U)
8329 #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */
8330 #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk
8331
8332 /******************** Bits definition for RTC_PRER register *****************/
8333 #define RTC_PRER_PREDIV_A_Pos (16U)
8334 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
8335 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
8336 #define RTC_PRER_PREDIV_S_Pos (0U)
8337 #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
8338 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
8339
8340 /******************** Bits definition for RTC_WUTR register *****************/
8341 #define RTC_WUTR_WUT_Pos (0U)
8342 #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
8343 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
8344
8345 /******************** Bits definition for RTC_CR register *******************/
8346 #define RTC_CR_OUT2EN_Pos (31U)
8347 #define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */
8348 #define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!<RTC_OUT2 output enable */
8349 #define RTC_CR_TAMPALRM_TYPE_Pos (30U)
8350 #define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */
8351 #define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!<TAMPALARM output type */
8352 #define RTC_CR_TAMPALRM_PU_Pos (29U)
8353 #define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */
8354 #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!<TAMPALARM output pull-up config */
8355 #define RTC_CR_TAMPOE_Pos (26U)
8356 #define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */
8357 #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk /*!<Tamper detection output enable on TAMPALARM */
8358 #define RTC_CR_TAMPTS_Pos (25U)
8359 #define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */
8360 #define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!<Activate timestamp on tamper detection event */
8361 #define RTC_CR_ITSE_Pos (24U)
8362 #define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
8363 #define RTC_CR_ITSE RTC_CR_ITSE_Msk /*!<Timestamp on internal event enable */
8364 #define RTC_CR_COE_Pos (23U)
8365 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
8366 #define RTC_CR_COE RTC_CR_COE_Msk
8367 #define RTC_CR_OSEL_Pos (21U)
8368 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
8369 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
8370 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
8371 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
8372 #define RTC_CR_POL_Pos (20U)
8373 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
8374 #define RTC_CR_POL RTC_CR_POL_Msk
8375 #define RTC_CR_COSEL_Pos (19U)
8376 #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
8377 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
8378 #define RTC_CR_BKP_Pos (18U)
8379 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
8380 #define RTC_CR_BKP RTC_CR_BKP_Msk
8381 #define RTC_CR_SUB1H_Pos (17U)
8382 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
8383 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
8384 #define RTC_CR_ADD1H_Pos (16U)
8385 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
8386 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
8387 #define RTC_CR_TSIE_Pos (15U)
8388 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
8389 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
8390 #define RTC_CR_WUTIE_Pos (14U)
8391 #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
8392 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
8393 #define RTC_CR_ALRBIE_Pos (13U)
8394 #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
8395 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
8396 #define RTC_CR_ALRAIE_Pos (12U)
8397 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
8398 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
8399 #define RTC_CR_TSE_Pos (11U)
8400 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
8401 #define RTC_CR_TSE RTC_CR_TSE_Msk
8402 #define RTC_CR_WUTE_Pos (10U)
8403 #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
8404 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
8405 #define RTC_CR_ALRBE_Pos (9U)
8406 #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
8407 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
8408 #define RTC_CR_ALRAE_Pos (8U)
8409 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
8410 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
8411 #define RTC_CR_FMT_Pos (6U)
8412 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
8413 #define RTC_CR_FMT RTC_CR_FMT_Msk
8414 #define RTC_CR_BYPSHAD_Pos (5U)
8415 #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
8416 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
8417 #define RTC_CR_REFCKON_Pos (4U)
8418 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
8419 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
8420 #define RTC_CR_TSEDGE_Pos (3U)
8421 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
8422 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
8423 #define RTC_CR_WUCKSEL_Pos (0U)
8424 #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
8425 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
8426 #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
8427 #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
8428 #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
8429
8430 /******************** Bits definition for RTC_WPR register ******************/
8431 #define RTC_WPR_KEY_Pos (0U)
8432 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
8433 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
8434
8435 /******************** Bits definition for RTC_CALR register *****************/
8436 #define RTC_CALR_CALP_Pos (15U)
8437 #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
8438 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
8439 #define RTC_CALR_CALW8_Pos (14U)
8440 #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
8441 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
8442 #define RTC_CALR_CALW16_Pos (13U)
8443 #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
8444 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
8445 #define RTC_CALR_CALM_Pos (0U)
8446 #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
8447 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
8448 #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
8449 #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
8450 #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
8451 #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
8452 #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
8453 #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
8454 #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
8455 #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
8456 #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
8457
8458 /******************** Bits definition for RTC_SHIFTR register ***************/
8459 #define RTC_SHIFTR_SUBFS_Pos (0U)
8460 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
8461 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
8462 #define RTC_SHIFTR_ADD1S_Pos (31U)
8463 #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
8464 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
8465
8466 /******************** Bits definition for RTC_TSTR register *****************/
8467 #define RTC_TSTR_PM_Pos (22U)
8468 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
8469 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
8470 #define RTC_TSTR_HT_Pos (20U)
8471 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
8472 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
8473 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
8474 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
8475 #define RTC_TSTR_HU_Pos (16U)
8476 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
8477 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
8478 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
8479 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
8480 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
8481 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
8482 #define RTC_TSTR_MNT_Pos (12U)
8483 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
8484 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
8485 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
8486 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
8487 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
8488 #define RTC_TSTR_MNU_Pos (8U)
8489 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
8490 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
8491 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
8492 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
8493 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
8494 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
8495 #define RTC_TSTR_ST_Pos (4U)
8496 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
8497 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
8498 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
8499 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
8500 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
8501 #define RTC_TSTR_SU_Pos (0U)
8502 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
8503 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
8504 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
8505 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
8506 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
8507 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
8508
8509 /******************** Bits definition for RTC_TSDR register *****************/
8510 #define RTC_TSDR_WDU_Pos (13U)
8511 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
8512 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
8513 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
8514 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
8515 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
8516 #define RTC_TSDR_MT_Pos (12U)
8517 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
8518 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
8519 #define RTC_TSDR_MU_Pos (8U)
8520 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
8521 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
8522 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
8523 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
8524 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
8525 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
8526 #define RTC_TSDR_DT_Pos (4U)
8527 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
8528 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
8529 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
8530 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
8531 #define RTC_TSDR_DU_Pos (0U)
8532 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
8533 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
8534 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
8535 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
8536 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
8537 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
8538
8539 /******************** Bits definition for RTC_TSSSR register ****************/
8540 #define RTC_TSSSR_SS_Pos (0U)
8541 #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
8542 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
8543
8544 /******************** Bits definition for RTC_ALRMAR register ***************/
8545 #define RTC_ALRMAR_MSK4_Pos (31U)
8546 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
8547 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
8548 #define RTC_ALRMAR_WDSEL_Pos (30U)
8549 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
8550 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
8551 #define RTC_ALRMAR_DT_Pos (28U)
8552 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
8553 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
8554 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
8555 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
8556 #define RTC_ALRMAR_DU_Pos (24U)
8557 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
8558 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
8559 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
8560 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
8561 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
8562 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
8563 #define RTC_ALRMAR_MSK3_Pos (23U)
8564 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
8565 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
8566 #define RTC_ALRMAR_PM_Pos (22U)
8567 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
8568 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
8569 #define RTC_ALRMAR_HT_Pos (20U)
8570 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
8571 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
8572 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
8573 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
8574 #define RTC_ALRMAR_HU_Pos (16U)
8575 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
8576 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
8577 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
8578 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
8579 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
8580 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
8581 #define RTC_ALRMAR_MSK2_Pos (15U)
8582 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
8583 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
8584 #define RTC_ALRMAR_MNT_Pos (12U)
8585 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
8586 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
8587 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
8588 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
8589 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
8590 #define RTC_ALRMAR_MNU_Pos (8U)
8591 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
8592 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
8593 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
8594 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
8595 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
8596 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
8597 #define RTC_ALRMAR_MSK1_Pos (7U)
8598 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
8599 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
8600 #define RTC_ALRMAR_ST_Pos (4U)
8601 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
8602 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
8603 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
8604 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
8605 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
8606 #define RTC_ALRMAR_SU_Pos (0U)
8607 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
8608 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
8609 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
8610 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
8611 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
8612 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
8613
8614 /******************** Bits definition for RTC_ALRMASSR register *************/
8615 #define RTC_ALRMASSR_MASKSS_Pos (24U)
8616 #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
8617 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
8618 #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
8619 #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
8620 #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
8621 #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
8622 #define RTC_ALRMASSR_SS_Pos (0U)
8623 #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
8624 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
8625
8626 /******************** Bits definition for RTC_ALRMBR register ***************/
8627 #define RTC_ALRMBR_MSK4_Pos (31U)
8628 #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
8629 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
8630 #define RTC_ALRMBR_WDSEL_Pos (30U)
8631 #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
8632 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
8633 #define RTC_ALRMBR_DT_Pos (28U)
8634 #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
8635 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
8636 #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
8637 #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
8638 #define RTC_ALRMBR_DU_Pos (24U)
8639 #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
8640 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
8641 #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
8642 #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
8643 #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
8644 #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
8645 #define RTC_ALRMBR_MSK3_Pos (23U)
8646 #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
8647 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
8648 #define RTC_ALRMBR_PM_Pos (22U)
8649 #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
8650 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
8651 #define RTC_ALRMBR_HT_Pos (20U)
8652 #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
8653 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
8654 #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
8655 #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
8656 #define RTC_ALRMBR_HU_Pos (16U)
8657 #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
8658 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
8659 #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
8660 #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
8661 #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
8662 #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
8663 #define RTC_ALRMBR_MSK2_Pos (15U)
8664 #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
8665 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
8666 #define RTC_ALRMBR_MNT_Pos (12U)
8667 #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
8668 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
8669 #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
8670 #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
8671 #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
8672 #define RTC_ALRMBR_MNU_Pos (8U)
8673 #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
8674 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
8675 #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
8676 #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
8677 #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
8678 #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
8679 #define RTC_ALRMBR_MSK1_Pos (7U)
8680 #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
8681 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
8682 #define RTC_ALRMBR_ST_Pos (4U)
8683 #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
8684 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
8685 #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
8686 #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
8687 #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
8688 #define RTC_ALRMBR_SU_Pos (0U)
8689 #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
8690 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
8691 #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
8692 #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
8693 #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
8694 #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
8695
8696 /******************** Bits definition for RTC_ALRMASSR register *************/
8697 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
8698 #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
8699 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
8700 #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
8701 #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
8702 #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
8703 #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
8704 #define RTC_ALRMBSSR_SS_Pos (0U)
8705 #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
8706 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
8707
8708 /******************** Bits definition for RTC_SR register *******************/
8709 #define RTC_SR_ITSF_Pos (5U)
8710 #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */
8711 #define RTC_SR_ITSF RTC_SR_ITSF_Msk
8712 #define RTC_SR_TSOVF_Pos (4U)
8713 #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */
8714 #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk
8715 #define RTC_SR_TSF_Pos (3U)
8716 #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */
8717 #define RTC_SR_TSF RTC_SR_TSF_Msk
8718 #define RTC_SR_WUTF_Pos (2U)
8719 #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */
8720 #define RTC_SR_WUTF RTC_SR_WUTF_Msk
8721 #define RTC_SR_ALRBF_Pos (1U)
8722 #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */
8723 #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk
8724 #define RTC_SR_ALRAF_Pos (0U)
8725 #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */
8726 #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk
8727
8728 /******************** Bits definition for RTC_MISR register *****************/
8729 #define RTC_MISR_ITSMF_Pos (5U)
8730 #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */
8731 #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk
8732 #define RTC_MISR_TSOVMF_Pos (4U)
8733 #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */
8734 #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk
8735 #define RTC_MISR_TSMF_Pos (3U)
8736 #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */
8737 #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk
8738 #define RTC_MISR_WUTMF_Pos (2U)
8739 #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */
8740 #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk
8741 #define RTC_MISR_ALRBMF_Pos (1U)
8742 #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */
8743 #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk
8744 #define RTC_MISR_ALRAMF_Pos (0U)
8745 #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */
8746 #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk
8747
8748 /******************** Bits definition for RTC_SCR register ******************/
8749 #define RTC_SCR_CITSF_Pos (5U)
8750 #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */
8751 #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk
8752 #define RTC_SCR_CTSOVF_Pos (4U)
8753 #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */
8754 #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk
8755 #define RTC_SCR_CTSF_Pos (3U)
8756 #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */
8757 #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk
8758 #define RTC_SCR_CWUTF_Pos (2U)
8759 #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */
8760 #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk
8761 #define RTC_SCR_CALRBF_Pos (1U)
8762 #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */
8763 #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk
8764 #define RTC_SCR_CALRAF_Pos (0U)
8765 #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
8766 #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
8767
8768 /******************************************************************************/
8769 /* */
8770 /* Tamper and backup register (TAMP) */
8771 /* */
8772 /******************************************************************************/
8773 /******************** Bits definition for TAMP_CR1 register *****************/
8774 #define TAMP_CR1_TAMP1E_Pos (0U)
8775 #define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */
8776 #define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk
8777 #define TAMP_CR1_TAMP2E_Pos (1U)
8778 #define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */
8779 #define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk
8780 #define TAMP_CR1_TAMP3E_Pos (2U)
8781 #define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */
8782 #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk
8783 #define TAMP_CR1_ITAMP3E_Pos (18U)
8784 #define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */
8785 #define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk
8786 #define TAMP_CR1_ITAMP4E_Pos (19U)
8787 #define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */
8788 #define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk
8789 #define TAMP_CR1_ITAMP5E_Pos (20U)
8790 #define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */
8791 #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk
8792 #define TAMP_CR1_ITAMP6E_Pos (21U)
8793 #define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */
8794 #define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk
8795
8796 /******************** Bits definition for TAMP_CR2 register *****************/
8797 #define TAMP_CR2_TAMP1NOERASE_Pos (0U)
8798 #define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */
8799 #define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk
8800 #define TAMP_CR2_TAMP2NOERASE_Pos (1U)
8801 #define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */
8802 #define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk
8803 #define TAMP_CR2_TAMP3NOERASE_Pos (2U)
8804 #define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */
8805 #define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk
8806 #define TAMP_CR2_TAMP1MF_Pos (16U)
8807 #define TAMP_CR2_TAMP1MF_Msk (0x1UL << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */
8808 #define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk
8809 #define TAMP_CR2_TAMP2MF_Pos (17U)
8810 #define TAMP_CR2_TAMP2MF_Msk (0x1UL << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */
8811 #define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk
8812 #define TAMP_CR2_TAMP3MF_Pos (18U)
8813 #define TAMP_CR2_TAMP3MF_Msk (0x1UL << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */
8814 #define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk
8815 #define TAMP_CR2_TAMP1TRG_Pos (24U)
8816 #define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */
8817 #define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk
8818 #define TAMP_CR2_TAMP2TRG_Pos (25U)
8819 #define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */
8820 #define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk
8821 #define TAMP_CR2_TAMP3TRG_Pos (26U)
8822 #define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */
8823 #define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
8824
8825 /******************** Bits definition for TAMP_FLTCR register ***************/
8826 #define TAMP_FLTCR_TAMPFREQ_0 ((uint32_t)0x00000001)
8827 #define TAMP_FLTCR_TAMPFREQ_1 ((uint32_t)0x00000002)
8828 #define TAMP_FLTCR_TAMPFREQ_2 ((uint32_t)0x00000004)
8829 #define TAMP_FLTCR_TAMPFREQ_Pos (0U)
8830 #define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
8831 #define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
8832 #define TAMP_FLTCR_TAMPFLT_0 ((uint32_t)0x00000008)
8833 #define TAMP_FLTCR_TAMPFLT_1 ((uint32_t)0x00000010)
8834 #define TAMP_FLTCR_TAMPFLT_Pos (3U)
8835 #define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
8836 #define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
8837 #define TAMP_FLTCR_TAMPPRCH_0 ((uint32_t)0x00000020)
8838 #define TAMP_FLTCR_TAMPPRCH_1 ((uint32_t)0x00000040)
8839 #define TAMP_FLTCR_TAMPPRCH_Pos (5U)
8840 #define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
8841 #define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
8842 #define TAMP_FLTCR_TAMPPUDIS_Pos (7U)
8843 #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */
8844 #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk
8845
8846 /******************** Bits definition for TAMP_IER register *****************/
8847 #define TAMP_IER_TAMP1IE_Pos (0U)
8848 #define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */
8849 #define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk
8850 #define TAMP_IER_TAMP2IE_Pos (1U)
8851 #define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */
8852 #define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk
8853 #define TAMP_IER_TAMP3IE_Pos (2U)
8854 #define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */
8855 #define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk
8856 #define TAMP_IER_ITAMP3IE_Pos (18U)
8857 #define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */
8858 #define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk
8859 #define TAMP_IER_ITAMP4IE_Pos (19U)
8860 #define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */
8861 #define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk
8862 #define TAMP_IER_ITAMP5IE_Pos (20U)
8863 #define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */
8864 #define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk
8865 #define TAMP_IER_ITAMP6IE_Pos (21U)
8866 #define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */
8867 #define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk
8868
8869 /******************** Bits definition for TAMP_SR register ******************/
8870 #define TAMP_SR_TAMP1F_Pos (0U)
8871 #define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */
8872 #define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk
8873 #define TAMP_SR_TAMP2F_Pos (1U)
8874 #define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */
8875 #define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk
8876 #define TAMP_SR_TAMP3F_Pos (2U)
8877 #define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */
8878 #define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk
8879 #define TAMP_SR_ITAMP3F_Pos (18U)
8880 #define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */
8881 #define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk
8882 #define TAMP_SR_ITAMP4F_Pos (19U)
8883 #define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */
8884 #define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk
8885 #define TAMP_SR_ITAMP5F_Pos (20U)
8886 #define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */
8887 #define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk
8888 #define TAMP_SR_ITAMP6F_Pos (21U)
8889 #define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */
8890 #define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk
8891
8892 /******************** Bits definition for TAMP_MISR register ****************/
8893 #define TAMP_MISR_TAMP1MF_Pos (0U)
8894 #define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */
8895 #define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk
8896 #define TAMP_MISR_TAMP2MF_Pos (1U)
8897 #define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */
8898 #define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk
8899 #define TAMP_MISR_TAMP3MF_Pos (2U)
8900 #define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */
8901 #define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk
8902 #define TAMP_MISR_ITAMP3MF_Pos (18U)
8903 #define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */
8904 #define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk
8905 #define TAMP_MISR_ITAMP4MF_Pos (19U)
8906 #define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */
8907 #define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk
8908 #define TAMP_MISR_ITAMP5MF_Pos (20U)
8909 #define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */
8910 #define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk
8911 #define TAMP_MISR_ITAMP6MF_Pos (21U)
8912 #define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */
8913 #define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk
8914
8915 /******************** Bits definition for TAMP_SCR register *****************/
8916 #define TAMP_SCR_CTAMP1F_Pos (0U)
8917 #define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */
8918 #define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk
8919 #define TAMP_SCR_CTAMP2F_Pos (1U)
8920 #define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */
8921 #define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk
8922 #define TAMP_SCR_CTAMP3F_Pos (2U)
8923 #define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */
8924 #define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk
8925 #define TAMP_SCR_CITAMP3F_Pos (18U)
8926 #define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */
8927 #define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk
8928 #define TAMP_SCR_CITAMP4F_Pos (19U)
8929 #define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */
8930 #define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk
8931 #define TAMP_SCR_CITAMP5F_Pos (20U)
8932 #define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */
8933 #define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk
8934 #define TAMP_SCR_CITAMP6F_Pos (21U)
8935 #define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */
8936 #define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk
8937
8938 /******************** Bits definition for TAMP_BKP0R register ***************/
8939 #define TAMP_BKP0R_Pos (0U)
8940 #define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */
8941 #define TAMP_BKP0R TAMP_BKP0R_Msk
8942
8943 /******************** Bits definition for TAMP_BKP1R register ***************/
8944 #define TAMP_BKP1R_Pos (0U)
8945 #define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */
8946 #define TAMP_BKP1R TAMP_BKP1R_Msk
8947
8948 /******************** Bits definition for TAMP_BKP2R register ***************/
8949 #define TAMP_BKP2R_Pos (0U)
8950 #define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */
8951 #define TAMP_BKP2R TAMP_BKP2R_Msk
8952
8953 /******************** Bits definition for TAMP_BKP3R register ***************/
8954 #define TAMP_BKP3R_Pos (0U)
8955 #define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */
8956 #define TAMP_BKP3R TAMP_BKP3R_Msk
8957
8958 /******************** Bits definition for TAMP_BKP4R register ***************/
8959 #define TAMP_BKP4R_Pos (0U)
8960 #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
8961 #define TAMP_BKP4R TAMP_BKP4R_Msk
8962
8963 /******************** Bits definition for TAMP_BKP5R register ***************/
8964 #define TAMP_BKP5R_Pos (0U)
8965 #define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */
8966 #define TAMP_BKP5R TAMP_BKP5R_Msk
8967
8968 /******************** Bits definition for TAMP_BKP6R register ***************/
8969 #define TAMP_BKP6R_Pos (0U)
8970 #define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */
8971 #define TAMP_BKP6R TAMP_BKP6R_Msk
8972
8973 /******************** Bits definition for TAMP_BKP7R register ***************/
8974 #define TAMP_BKP7R_Pos (0U)
8975 #define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */
8976 #define TAMP_BKP7R TAMP_BKP7R_Msk
8977
8978 /******************** Bits definition for TAMP_BKP8R register ***************/
8979 #define TAMP_BKP8R_Pos (0U)
8980 #define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */
8981 #define TAMP_BKP8R TAMP_BKP8R_Msk
8982
8983 /******************** Bits definition for TAMP_BKP9R register ***************/
8984 #define TAMP_BKP9R_Pos (0U)
8985 #define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */
8986 #define TAMP_BKP9R TAMP_BKP9R_Msk
8987
8988 /******************** Bits definition for TAMP_BKP10R register ***************/
8989 #define TAMP_BKP10R_Pos (0U)
8990 #define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */
8991 #define TAMP_BKP10R TAMP_BKP10R_Msk
8992
8993 /******************** Bits definition for TAMP_BKP11R register ***************/
8994 #define TAMP_BKP11R_Pos (0U)
8995 #define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */
8996 #define TAMP_BKP11R TAMP_BKP11R_Msk
8997
8998 /******************** Bits definition for TAMP_BKP12R register ***************/
8999 #define TAMP_BKP12R_Pos (0U)
9000 #define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */
9001 #define TAMP_BKP12R TAMP_BKP12R_Msk
9002
9003 /******************** Bits definition for TAMP_BKP13R register ***************/
9004 #define TAMP_BKP13R_Pos (0U)
9005 #define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */
9006 #define TAMP_BKP13R TAMP_BKP13R_Msk
9007
9008 /******************** Bits definition for TAMP_BKP14R register ***************/
9009 #define TAMP_BKP14R_Pos (0U)
9010 #define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */
9011 #define TAMP_BKP14R TAMP_BKP14R_Msk
9012
9013 /******************** Bits definition for TAMP_BKP15R register ***************/
9014 #define TAMP_BKP15R_Pos (0U)
9015 #define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */
9016 #define TAMP_BKP15R TAMP_BKP15R_Msk
9017
9018
9019 /******************************************************************************/
9020 /* */
9021 /* Serial Audio Interface */
9022 /* */
9023 /******************************************************************************/
9024 /******************** Bit definition for SAI_GCR register *******************/
9025 #define SAI_GCR_SYNCIN_Pos (0U)
9026 #define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
9027 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
9028 #define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
9029 #define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
9030
9031 #define SAI_GCR_SYNCOUT_Pos (4U)
9032 #define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
9033 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
9034 #define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
9035 #define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
9036
9037 /******************* Bit definition for SAI_xCR1 register *******************/
9038 #define SAI_xCR1_MODE_Pos (0U)
9039 #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
9040 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
9041 #define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
9042 #define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
9043
9044 #define SAI_xCR1_PRTCFG_Pos (2U)
9045 #define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
9046 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
9047 #define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
9048 #define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
9049
9050 #define SAI_xCR1_DS_Pos (5U)
9051 #define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
9052 #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
9053 #define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
9054 #define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
9055 #define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
9056
9057 #define SAI_xCR1_LSBFIRST_Pos (8U)
9058 #define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
9059 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
9060 #define SAI_xCR1_CKSTR_Pos (9U)
9061 #define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
9062 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
9063
9064 #define SAI_xCR1_SYNCEN_Pos (10U)
9065 #define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
9066 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
9067 #define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
9068 #define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
9069
9070 #define SAI_xCR1_MONO_Pos (12U)
9071 #define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
9072 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
9073 #define SAI_xCR1_OUTDRIV_Pos (13U)
9074 #define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
9075 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
9076 #define SAI_xCR1_SAIEN_Pos (16U)
9077 #define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
9078 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
9079 #define SAI_xCR1_DMAEN_Pos (17U)
9080 #define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
9081 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
9082 #define SAI_xCR1_NODIV_Pos (19U)
9083 #define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
9084 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
9085
9086 #define SAI_xCR1_MCKDIV_Pos (20U)
9087 #define SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos) /*!< 0x03F00000 */
9088 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[5:0] (Master ClocK Divider) */
9089 #define SAI_xCR1_MCKDIV_0 (0x00100000U) /*!<Bit 0 */
9090 #define SAI_xCR1_MCKDIV_1 (0x00200000U) /*!<Bit 1 */
9091 #define SAI_xCR1_MCKDIV_2 (0x00400000U) /*!<Bit 2 */
9092 #define SAI_xCR1_MCKDIV_3 (0x00800000U) /*!<Bit 3 */
9093 #define SAI_xCR1_MCKDIV_4 (0x01000000U) /*!<Bit 4 */
9094 #define SAI_xCR1_MCKDIV_5 (0x02000000U) /*!<Bit 5 */
9095
9096 #define SAI_xCR1_OSR_Pos (26U)
9097 #define SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos) /*!< 0x04000000 */
9098 #define SAI_xCR1_OSR SAI_xCR1_OSR_Msk /*!<Oversampling ratio for master clock */
9099
9100 #define SAI_xCR1_MCKEN_Pos (27U)
9101 #define SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos) /*!< 0x08000000 */
9102 #define SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk /*!<Master clock generation enable */
9103
9104 /******************* Bit definition for SAI_xCR2 register *******************/
9105 #define SAI_xCR2_FTH_Pos (0U)
9106 #define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
9107 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
9108 #define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
9109 #define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
9110 #define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
9111
9112 #define SAI_xCR2_FFLUSH_Pos (3U)
9113 #define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
9114 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
9115 #define SAI_xCR2_TRIS_Pos (4U)
9116 #define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
9117 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
9118 #define SAI_xCR2_MUTE_Pos (5U)
9119 #define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
9120 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
9121 #define SAI_xCR2_MUTEVAL_Pos (6U)
9122 #define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
9123 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
9124
9125
9126 #define SAI_xCR2_MUTECNT_Pos (7U)
9127 #define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
9128 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
9129 #define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
9130 #define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
9131 #define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
9132 #define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
9133 #define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
9134 #define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
9135
9136 #define SAI_xCR2_CPL_Pos (13U)
9137 #define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
9138 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!<CPL mode */
9139 #define SAI_xCR2_COMP_Pos (14U)
9140 #define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
9141 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
9142 #define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
9143 #define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
9144
9145
9146 /****************** Bit definition for SAI_xFRCR register *******************/
9147 #define SAI_xFRCR_FRL_Pos (0U)
9148 #define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
9149 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */
9150 #define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
9151 #define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
9152 #define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
9153 #define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
9154 #define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
9155 #define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
9156 #define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
9157 #define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
9158
9159 #define SAI_xFRCR_FSALL_Pos (8U)
9160 #define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
9161 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */
9162 #define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
9163 #define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
9164 #define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
9165 #define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
9166 #define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
9167 #define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
9168 #define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
9169
9170 #define SAI_xFRCR_FSDEF_Pos (16U)
9171 #define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
9172 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
9173 #define SAI_xFRCR_FSPOL_Pos (17U)
9174 #define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
9175 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
9176 #define SAI_xFRCR_FSOFF_Pos (18U)
9177 #define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
9178 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
9179
9180 /****************** Bit definition for SAI_xSLOTR register *******************/
9181 #define SAI_xSLOTR_FBOFF_Pos (0U)
9182 #define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
9183 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
9184 #define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
9185 #define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
9186 #define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
9187 #define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
9188 #define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
9189
9190 #define SAI_xSLOTR_SLOTSZ_Pos (6U)
9191 #define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
9192 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
9193 #define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
9194 #define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
9195
9196 #define SAI_xSLOTR_NBSLOT_Pos (8U)
9197 #define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
9198 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
9199 #define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
9200 #define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
9201 #define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
9202 #define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
9203
9204 #define SAI_xSLOTR_SLOTEN_Pos (16U)
9205 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
9206 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
9207
9208 /******************* Bit definition for SAI_xIMR register *******************/
9209 #define SAI_xIMR_OVRUDRIE_Pos (0U)
9210 #define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
9211 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
9212 #define SAI_xIMR_MUTEDETIE_Pos (1U)
9213 #define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
9214 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
9215 #define SAI_xIMR_WCKCFGIE_Pos (2U)
9216 #define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
9217 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
9218 #define SAI_xIMR_FREQIE_Pos (3U)
9219 #define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
9220 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
9221 #define SAI_xIMR_CNRDYIE_Pos (4U)
9222 #define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
9223 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
9224 #define SAI_xIMR_AFSDETIE_Pos (5U)
9225 #define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
9226 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
9227 #define SAI_xIMR_LFSDETIE_Pos (6U)
9228 #define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
9229 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
9230
9231 /******************** Bit definition for SAI_xSR register *******************/
9232 #define SAI_xSR_OVRUDR_Pos (0U)
9233 #define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
9234 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
9235 #define SAI_xSR_MUTEDET_Pos (1U)
9236 #define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
9237 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
9238 #define SAI_xSR_WCKCFG_Pos (2U)
9239 #define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
9240 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
9241 #define SAI_xSR_FREQ_Pos (3U)
9242 #define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
9243 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
9244 #define SAI_xSR_CNRDY_Pos (4U)
9245 #define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
9246 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
9247 #define SAI_xSR_AFSDET_Pos (5U)
9248 #define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
9249 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
9250 #define SAI_xSR_LFSDET_Pos (6U)
9251 #define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
9252 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
9253
9254 #define SAI_xSR_FLVL_Pos (16U)
9255 #define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
9256 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
9257 #define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
9258 #define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
9259 #define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
9260
9261 /****************** Bit definition for SAI_xCLRFR register ******************/
9262 #define SAI_xCLRFR_COVRUDR_Pos (0U)
9263 #define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
9264 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
9265 #define SAI_xCLRFR_CMUTEDET_Pos (1U)
9266 #define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
9267 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
9268 #define SAI_xCLRFR_CWCKCFG_Pos (2U)
9269 #define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
9270 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
9271 #define SAI_xCLRFR_CFREQ_Pos (3U)
9272 #define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
9273 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
9274 #define SAI_xCLRFR_CCNRDY_Pos (4U)
9275 #define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
9276 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
9277 #define SAI_xCLRFR_CAFSDET_Pos (5U)
9278 #define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
9279 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
9280 #define SAI_xCLRFR_CLFSDET_Pos (6U)
9281 #define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
9282 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
9283
9284 /****************** Bit definition for SAI_xDR register ******************/
9285 #define SAI_xDR_DATA_Pos (0U)
9286 #define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
9287 #define SAI_xDR_DATA SAI_xDR_DATA_Msk
9288
9289 /****************** Bit definition for SAI_PDMCR register *******************/
9290 #define SAI_PDMCR_PDMEN_Pos (0U)
9291 #define SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos) /*!< 0x00000001 */
9292 #define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk /*!<PDM enable */
9293
9294 #define SAI_PDMCR_MICNBR_Pos (4U)
9295 #define SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000030 */
9296 #define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk /*!<MICNBR[1:0] (Number of microphones) */
9297 #define SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000010 */
9298 #define SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000020 */
9299
9300 #define SAI_PDMCR_CKEN1_Pos (8U)
9301 #define SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos) /*!< 0x00000100 */
9302 #define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk /*!<Clock 1 enable */
9303 #define SAI_PDMCR_CKEN2_Pos (9U)
9304 #define SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos) /*!< 0x00000200 */
9305 #define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk /*!<Clock 2 enable */
9306 #define SAI_PDMCR_CKEN3_Pos (10U)
9307 #define SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos) /*!< 0x00000400 */
9308 #define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk /*!<Clock 3 enable */
9309 #define SAI_PDMCR_CKEN4_Pos (11U)
9310 #define SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos) /*!< 0x00000800 */
9311 #define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk /*!<Clock 4 enable */
9312
9313 /****************** Bit definition for SAI_PDMDLY register ******************/
9314 #define SAI_PDMDLY_DLYM1L_Pos (0U)
9315 #define SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000007 */
9316 #define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
9317 #define SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000001 */
9318 #define SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000002 */
9319 #define SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000004 */
9320
9321 #define SAI_PDMDLY_DLYM1R_Pos (4U)
9322 #define SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000070 */
9323 #define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
9324 #define SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000010 */
9325 #define SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000020 */
9326 #define SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000040 */
9327
9328 #define SAI_PDMDLY_DLYM2L_Pos (8U)
9329 #define SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000700 */
9330 #define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
9331 #define SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000100 */
9332 #define SAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000200 */
9333 #define SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000400 */
9334
9335 #define SAI_PDMDLY_DLYM2R_Pos (12U)
9336 #define SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00007000 */
9337 #define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2) */
9338 #define SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00001000 */
9339 #define SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00002000 */
9340 #define SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00004000 */
9341
9342 #define SAI_PDMDLY_DLYM3L_Pos (16U)
9343 #define SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00070000 */
9344 #define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3) */
9345 #define SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00010000 */
9346 #define SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00020000 */
9347 #define SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00040000 */
9348
9349 #define SAI_PDMDLY_DLYM3R_Pos (20U)
9350 #define SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00700000 */
9351 #define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3) */
9352 #define SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00100000 */
9353 #define SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00200000 */
9354 #define SAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00400000 */
9355
9356 #define SAI_PDMDLY_DLYM4L_Pos (24U)
9357 #define SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x07000000 */
9358 #define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4) */
9359 #define SAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x01000000 */
9360 #define SAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x02000000 */
9361 #define SAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x04000000 */
9362
9363 #define SAI_PDMDLY_DLYM4R_Pos (28U)
9364 #define SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x70000000 */
9365 #define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4) */
9366 #define SAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x10000000 */
9367 #define SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x20000000 */
9368 #define SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x40000000 */
9369
9370
9371 /******************************************************************************/
9372 /* */
9373 /* Serial Peripheral Interface (SPI) */
9374 /* */
9375 /******************************************************************************/
9376 /*
9377 * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
9378 */
9379 #define SPI_I2S_SUPPORT /*!< I2S support */
9380
9381 /******************* Bit definition for SPI_CR1 register ********************/
9382 #define SPI_CR1_CPHA_Pos (0U)
9383 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
9384 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
9385 #define SPI_CR1_CPOL_Pos (1U)
9386 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
9387 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
9388 #define SPI_CR1_MSTR_Pos (2U)
9389 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
9390 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
9391
9392 #define SPI_CR1_BR_Pos (3U)
9393 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
9394 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
9395 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
9396 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
9397 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
9398
9399 #define SPI_CR1_SPE_Pos (6U)
9400 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
9401 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
9402 #define SPI_CR1_LSBFIRST_Pos (7U)
9403 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
9404 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
9405 #define SPI_CR1_SSI_Pos (8U)
9406 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
9407 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
9408 #define SPI_CR1_SSM_Pos (9U)
9409 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
9410 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
9411 #define SPI_CR1_RXONLY_Pos (10U)
9412 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
9413 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
9414 #define SPI_CR1_CRCL_Pos (11U)
9415 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
9416 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
9417 #define SPI_CR1_CRCNEXT_Pos (12U)
9418 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
9419 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
9420 #define SPI_CR1_CRCEN_Pos (13U)
9421 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
9422 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
9423 #define SPI_CR1_BIDIOE_Pos (14U)
9424 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
9425 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
9426 #define SPI_CR1_BIDIMODE_Pos (15U)
9427 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
9428 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
9429
9430 /******************* Bit definition for SPI_CR2 register ********************/
9431 #define SPI_CR2_RXDMAEN_Pos (0U)
9432 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
9433 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
9434 #define SPI_CR2_TXDMAEN_Pos (1U)
9435 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
9436 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
9437 #define SPI_CR2_SSOE_Pos (2U)
9438 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
9439 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
9440 #define SPI_CR2_NSSP_Pos (3U)
9441 #define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
9442 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
9443 #define SPI_CR2_FRF_Pos (4U)
9444 #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
9445 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
9446 #define SPI_CR2_ERRIE_Pos (5U)
9447 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
9448 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
9449 #define SPI_CR2_RXNEIE_Pos (6U)
9450 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
9451 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
9452 #define SPI_CR2_TXEIE_Pos (7U)
9453 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
9454 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
9455 #define SPI_CR2_DS_Pos (8U)
9456 #define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
9457 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
9458 #define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */
9459 #define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */
9460 #define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */
9461 #define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */
9462 #define SPI_CR2_FRXTH_Pos (12U)
9463 #define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
9464 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
9465 #define SPI_CR2_LDMARX_Pos (13U)
9466 #define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
9467 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
9468 #define SPI_CR2_LDMATX_Pos (14U)
9469 #define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
9470 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
9471
9472 /******************** Bit definition for SPI_SR register ********************/
9473 #define SPI_SR_RXNE_Pos (0U)
9474 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
9475 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
9476 #define SPI_SR_TXE_Pos (1U)
9477 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
9478 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
9479 #define SPI_SR_CHSIDE_Pos (2U)
9480 #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
9481 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
9482 #define SPI_SR_UDR_Pos (3U)
9483 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
9484 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
9485 #define SPI_SR_CRCERR_Pos (4U)
9486 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
9487 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
9488 #define SPI_SR_MODF_Pos (5U)
9489 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
9490 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
9491 #define SPI_SR_OVR_Pos (6U)
9492 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
9493 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
9494 #define SPI_SR_BSY_Pos (7U)
9495 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
9496 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
9497 #define SPI_SR_FRE_Pos (8U)
9498 #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
9499 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
9500 #define SPI_SR_FRLVL_Pos (9U)
9501 #define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
9502 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
9503 #define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
9504 #define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
9505 #define SPI_SR_FTLVL_Pos (11U)
9506 #define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
9507 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
9508 #define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
9509 #define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
9510
9511 /******************** Bit definition for SPI_DR register ********************/
9512 #define SPI_DR_DR_Pos (0U)
9513 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
9514 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
9515
9516 /******************* Bit definition for SPI_CRCPR register ******************/
9517 #define SPI_CRCPR_CRCPOLY_Pos (0U)
9518 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
9519 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
9520
9521 /****************** Bit definition for SPI_RXCRCR register ******************/
9522 #define SPI_RXCRCR_RXCRC_Pos (0U)
9523 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
9524 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
9525
9526 /****************** Bit definition for SPI_TXCRCR register ******************/
9527 #define SPI_TXCRCR_TXCRC_Pos (0U)
9528 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
9529 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
9530
9531 /****************** Bit definition for SPI_I2SCFGR register *****************/
9532 #define SPI_I2SCFGR_CHLEN_Pos (0U)
9533 #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
9534 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
9535 #define SPI_I2SCFGR_DATLEN_Pos (1U)
9536 #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
9537 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
9538 #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
9539 #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
9540 #define SPI_I2SCFGR_CKPOL_Pos (3U)
9541 #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
9542 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
9543 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
9544 #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
9545 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
9546 #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
9547 #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
9548 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
9549 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
9550 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
9551 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
9552 #define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
9553 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
9554 #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
9555 #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
9556 #define SPI_I2SCFGR_I2SE_Pos (10U)
9557 #define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
9558 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
9559 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
9560 #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
9561 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
9562 #define SPI_I2SCFGR_ASTRTEN_Pos (12U)
9563 #define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
9564 #define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
9565
9566 /****************** Bit definition for SPI_I2SPR register *******************/
9567 #define SPI_I2SPR_I2SDIV_Pos (0U)
9568 #define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
9569 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
9570 #define SPI_I2SPR_ODD_Pos (8U)
9571 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
9572 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
9573 #define SPI_I2SPR_MCKOE_Pos (9U)
9574 #define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
9575 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
9576
9577 /******************************************************************************/
9578 /* */
9579 /* SYSCFG */
9580 /* */
9581 /******************************************************************************/
9582 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
9583 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
9584 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
9585 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
9586 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
9587 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
9588 #define SYSCFG_MEMRMP_MEM_MODE_2 (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
9589
9590 #define SYSCFG_MEMRMP_FB_MODE_Pos (8U)
9591 #define SYSCFG_MEMRMP_FB_MODE_Msk (0x1UL << SYSCFG_MEMRMP_FB_MODE_Pos) /*!< 0x00000100 */
9592 #define SYSCFG_MEMRMP_FB_MODE SYSCFG_MEMRMP_FB_MODE_Msk /*!< User Flash Bank mode selection */
9593
9594 /****************** Bit definition for SYSCFG_CFGR1 register ******************/
9595 #define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
9596 #define SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */
9597 #define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
9598 #define SYSCFG_CFGR1_ANASWVDD_Pos (9U)
9599 #define SYSCFG_CFGR1_ANASWVDD_Msk (0x1UL << SYSCFG_CFGR1_ANASWVDD_Pos) /*!< 0x00000200 */
9600 #define SYSCFG_CFGR1_ANASWVDD SYSCFG_CFGR1_ANASWVDD_Msk /*!< GPIO analog switch control voltage selection */
9601 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
9602 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)/*!< 0x00010000 */
9603 #define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
9604 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
9605 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)/*!< 0x00020000 */
9606 #define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
9607 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
9608 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)/*!< 0x00040000 */
9609 #define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
9610 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
9611 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)/*!< 0x00080000 */
9612 #define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
9613 #define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
9614 #define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
9615 #define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
9616 #define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)
9617 #define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */
9618 #define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
9619 #define SYSCFG_CFGR1_I2C3_FMP_Pos (22U)
9620 #define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos) /*!< 0x00400000 */
9621 #define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
9622 #define SYSCFG_CFGR1_FPU_IE_0 (0x04000000U) /*!< Invalid operation Interrupt enable */
9623 #define SYSCFG_CFGR1_FPU_IE_1 (0x08000000U) /*!< Divide-by-zero Interrupt enable */
9624 #define SYSCFG_CFGR1_FPU_IE_2 (0x10000000U) /*!< Underflow Interrupt enable */
9625 #define SYSCFG_CFGR1_FPU_IE_3 (0x20000000U) /*!< Overflow Interrupt enable */
9626 #define SYSCFG_CFGR1_FPU_IE_4 (0x40000000U) /*!< Input denormal Interrupt enable */
9627 #define SYSCFG_CFGR1_FPU_IE_5 (0x80000000U) /*!< Inexact Interrupt enable (interrupt disabled at reset) */
9628
9629 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
9630 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
9631 #define SYSCFG_EXTICR1_EXTI0_Msk (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
9632 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
9633 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
9634 #define SYSCFG_EXTICR1_EXTI1_Msk (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
9635 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
9636 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
9637 #define SYSCFG_EXTICR1_EXTI2_Msk (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
9638 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
9639 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
9640 #define SYSCFG_EXTICR1_EXTI3_Msk (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
9641 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
9642
9643 /**
9644 * @brief EXTI0 configuration
9645 */
9646 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!<PA[0] pin */
9647 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
9648 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
9649 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
9650 #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
9651 #define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
9652 #define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
9653
9654 /**
9655 * @brief EXTI1 configuration
9656 */
9657 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!<PA[1] pin */
9658 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
9659 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
9660 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
9661 #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
9662 #define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
9663 #define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
9664
9665 /**
9666 * @brief EXTI2 configuration
9667 */
9668 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!<PA[2] pin */
9669 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
9670 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
9671 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
9672 #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
9673 #define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
9674 #define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
9675
9676 /**
9677 * @brief EXTI3 configuration
9678 */
9679 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!<PA[3] pin */
9680 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
9681 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
9682 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
9683 #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
9684 #define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
9685 #define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
9686
9687 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
9688 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
9689 #define SYSCFG_EXTICR2_EXTI4_Msk (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
9690 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
9691 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
9692 #define SYSCFG_EXTICR2_EXTI5_Msk (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
9693 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
9694 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
9695 #define SYSCFG_EXTICR2_EXTI6_Msk (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
9696 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
9697 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
9698 #define SYSCFG_EXTICR2_EXTI7_Msk (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
9699 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
9700
9701 /**
9702 * @brief EXTI4 configuration
9703 */
9704 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!<PA[4] pin */
9705 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
9706 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
9707 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
9708 #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
9709 #define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
9710 #define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
9711
9712 /**
9713 * @brief EXTI5 configuration
9714 */
9715 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!<PA[5] pin */
9716 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
9717 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
9718 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
9719 #define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
9720 #define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
9721 #define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
9722
9723 /**
9724 * @brief EXTI6 configuration
9725 */
9726 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!<PA[6] pin */
9727 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
9728 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
9729 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
9730 #define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
9731 #define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
9732 #define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
9733
9734 /**
9735 * @brief EXTI7 configuration
9736 */
9737 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!<PA[7] pin */
9738 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
9739 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
9740 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
9741 #define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
9742 #define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
9743 #define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
9744
9745 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
9746 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
9747 #define SYSCFG_EXTICR3_EXTI8_Msk (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
9748 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
9749 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
9750 #define SYSCFG_EXTICR3_EXTI9_Msk (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
9751 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
9752 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
9753 #define SYSCFG_EXTICR3_EXTI10_Msk (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
9754 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
9755 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
9756 #define SYSCFG_EXTICR3_EXTI11_Msk (0x7UL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
9757 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
9758
9759 /**
9760 * @brief EXTI8 configuration
9761 */
9762 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!<PA[8] pin */
9763 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
9764 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
9765 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
9766 #define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
9767 #define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
9768 #define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
9769
9770 /**
9771 * @brief EXTI9 configuration
9772 */
9773 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!<PA[9] pin */
9774 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
9775 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
9776 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
9777 #define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
9778 #define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
9779 #define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
9780
9781 /**
9782 * @brief EXTI10 configuration
9783 */
9784 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!<PA[10] pin */
9785 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
9786 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
9787 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
9788 #define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
9789 #define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
9790
9791 /**
9792 * @brief EXTI11 configuration
9793 */
9794 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!<PA[11] pin */
9795 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
9796 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
9797 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
9798 #define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
9799 #define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
9800
9801 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
9802 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
9803 #define SYSCFG_EXTICR4_EXTI12_Msk (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */
9804 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
9805 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
9806 #define SYSCFG_EXTICR4_EXTI13_Msk (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x00000070 */
9807 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
9808 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
9809 #define SYSCFG_EXTICR4_EXTI14_Msk (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000700 */
9810 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
9811 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
9812 #define SYSCFG_EXTICR4_EXTI15_Msk (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x00007000 */
9813 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
9814
9815 /**
9816 * @brief EXTI12 configuration
9817 */
9818 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!<PA[12] pin */
9819 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
9820 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
9821 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
9822 #define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
9823 #define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
9824
9825 /**
9826 * @brief EXTI13 configuration
9827 */
9828 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!<PA[13] pin */
9829 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
9830 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
9831 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
9832 #define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
9833 #define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
9834
9835 /**
9836 * @brief EXTI14 configuration
9837 */
9838 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!<PA[14] pin */
9839 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
9840 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
9841 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
9842 #define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
9843 #define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
9844
9845 /**
9846 * @brief EXTI15 configuration
9847 */
9848 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!<PA[15] pin */
9849 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
9850 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
9851 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
9852 #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
9853 #define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
9854
9855 /****************** Bit definition for SYSCFG_SCSR register ****************/
9856 #define SYSCFG_SCSR_CCMER_Pos (0U)
9857 #define SYSCFG_SCSR_CCMER_Msk (0x1UL << SYSCFG_SCSR_CCMER_Pos) /*!< 0x00000001 */
9858 #define SYSCFG_SCSR_CCMER SYSCFG_SCSR_CCMER_Msk /*!< CCMSRAM Erase Request */
9859 #define SYSCFG_SCSR_CCMBSY_Pos (1U)
9860 #define SYSCFG_SCSR_CCMBSY_Msk (0x1UL << SYSCFG_SCSR_CCMBSY_Pos) /*!< 0x00000002 */
9861 #define SYSCFG_SCSR_CCMBSY SYSCFG_SCSR_CCMBSY_Msk /*!< CCMSRAM Erase Ongoing */
9862
9863 /****************** Bit definition for SYSCFG_CFGR2 register ****************/
9864 #define SYSCFG_CFGR2_CLL_Pos (0U)
9865 #define SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */
9866 #define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Core Lockup Lock */
9867 #define SYSCFG_CFGR2_SPL_Pos (1U)
9868 #define SYSCFG_CFGR2_SPL_Msk (0x1UL << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */
9869 #define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< SRAM Parity Lock*/
9870 #define SYSCFG_CFGR2_PVDL_Pos (2U)
9871 #define SYSCFG_CFGR2_PVDL_Msk (0x1UL << SYSCFG_CFGR2_PVDL_Pos) /*!< 0x00000004 */
9872 #define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk /*!< PVD Lock */
9873 #define SYSCFG_CFGR2_ECCL_Pos (3U)
9874 #define SYSCFG_CFGR2_ECCL_Msk (0x1UL << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */
9875 #define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECC Lock*/
9876 #define SYSCFG_CFGR2_SPF_Pos (8U)
9877 #define SYSCFG_CFGR2_SPF_Msk (0x1UL << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */
9878 #define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM Parity Flag */
9879
9880 /****************** Bit definition for SYSCFG_SWPR register ****************/
9881 #define SYSCFG_SWPR_PAGE0_Pos (0U)
9882 #define SYSCFG_SWPR_PAGE0_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
9883 #define SYSCFG_SWPR_PAGE0 (uint32_t)(SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
9884 #define SYSCFG_SWPR_PAGE1_Pos (1U)
9885 #define SYSCFG_SWPR_PAGE1_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
9886 #define SYSCFG_SWPR_PAGE1 (uint32_t)(SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
9887 #define SYSCFG_SWPR_PAGE2_Pos (2U)
9888 #define SYSCFG_SWPR_PAGE2_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
9889 #define SYSCFG_SWPR_PAGE2 (uint32_t)(SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
9890 #define SYSCFG_SWPR_PAGE3_Pos (3U)
9891 #define SYSCFG_SWPR_PAGE3_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
9892 #define SYSCFG_SWPR_PAGE3 (uint32_t)(SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
9893 #define SYSCFG_SWPR_PAGE4_Pos (4U)
9894 #define SYSCFG_SWPR_PAGE4_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
9895 #define SYSCFG_SWPR_PAGE4 (uint32_t)(SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
9896 #define SYSCFG_SWPR_PAGE5_Pos (5U)
9897 #define SYSCFG_SWPR_PAGE5_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
9898 #define SYSCFG_SWPR_PAGE5 (uint32_t)(SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
9899 #define SYSCFG_SWPR_PAGE6_Pos (6U)
9900 #define SYSCFG_SWPR_PAGE6_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
9901 #define SYSCFG_SWPR_PAGE6 (uint32_t)(SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
9902 #define SYSCFG_SWPR_PAGE7_Pos (7U)
9903 #define SYSCFG_SWPR_PAGE7_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
9904 #define SYSCFG_SWPR_PAGE7 (uint32_t)(SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
9905 #define SYSCFG_SWPR_PAGE8_Pos (8U)
9906 #define SYSCFG_SWPR_PAGE8_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
9907 #define SYSCFG_SWPR_PAGE8 (uint32_t)(SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
9908 #define SYSCFG_SWPR_PAGE9_Pos (9U)
9909 #define SYSCFG_SWPR_PAGE9_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
9910 #define SYSCFG_SWPR_PAGE9 (uint32_t)(SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
9911 /****************** Bit definition for SYSCFG_SKR register ****************/
9912 #define SYSCFG_SKR_KEY_Pos (0U)
9913 #define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
9914 #define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk /*!< CCMSRAM write protection key for software erase */
9915
9916 /******************************************************************************/
9917 /* */
9918 /* TIM */
9919 /* */
9920 /******************************************************************************/
9921 /******************* Bit definition for TIM_CR1 register ********************/
9922 #define TIM_CR1_CEN_Pos (0U)
9923 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
9924 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
9925 #define TIM_CR1_UDIS_Pos (1U)
9926 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
9927 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
9928 #define TIM_CR1_URS_Pos (2U)
9929 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
9930 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
9931 #define TIM_CR1_OPM_Pos (3U)
9932 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
9933 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
9934 #define TIM_CR1_DIR_Pos (4U)
9935 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
9936 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
9937
9938 #define TIM_CR1_CMS_Pos (5U)
9939 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
9940 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
9941 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
9942 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
9943
9944 #define TIM_CR1_ARPE_Pos (7U)
9945 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
9946 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
9947
9948 #define TIM_CR1_CKD_Pos (8U)
9949 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
9950 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
9951 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
9952 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
9953
9954 #define TIM_CR1_UIFREMAP_Pos (11U)
9955 #define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
9956 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
9957
9958 #define TIM_CR1_DITHEN_Pos (12U)
9959 #define TIM_CR1_DITHEN_Msk (0x1UL << TIM_CR1_DITHEN_Pos) /*!< 0x00001000 */
9960 #define TIM_CR1_DITHEN TIM_CR1_DITHEN_Msk /*!<Dithering enable */
9961
9962 /******************* Bit definition for TIM_CR2 register ********************/
9963 #define TIM_CR2_CCPC_Pos (0U)
9964 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
9965 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
9966 #define TIM_CR2_CCUS_Pos (2U)
9967 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
9968 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
9969 #define TIM_CR2_CCDS_Pos (3U)
9970 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
9971 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
9972
9973 #define TIM_CR2_MMS_Pos (4U)
9974 #define TIM_CR2_MMS_Msk (0x200007UL << TIM_CR2_MMS_Pos) /*!< 0x02000070 */
9975 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[3:0] bits (Master Mode Selection) */
9976 #define TIM_CR2_MMS_0 (0x000001UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
9977 #define TIM_CR2_MMS_1 (0x000002UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
9978 #define TIM_CR2_MMS_2 (0x000004UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
9979 #define TIM_CR2_MMS_3 (0x200000UL << TIM_CR2_MMS_Pos) /*!< 0x02000000 */
9980
9981 #define TIM_CR2_TI1S_Pos (7U)
9982 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
9983 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
9984 #define TIM_CR2_OIS1_Pos (8U)
9985 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
9986 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
9987 #define TIM_CR2_OIS1N_Pos (9U)
9988 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
9989 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
9990 #define TIM_CR2_OIS2_Pos (10U)
9991 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
9992 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
9993 #define TIM_CR2_OIS2N_Pos (11U)
9994 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
9995 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
9996 #define TIM_CR2_OIS3_Pos (12U)
9997 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
9998 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
9999 #define TIM_CR2_OIS3N_Pos (13U)
10000 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
10001 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
10002 #define TIM_CR2_OIS4_Pos (14U)
10003 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
10004 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
10005 #define TIM_CR2_OIS4N_Pos (15U)
10006 #define TIM_CR2_OIS4N_Msk (0x1UL << TIM_CR2_OIS4N_Pos) /*!< 0x00008000 */
10007 #define TIM_CR2_OIS4N TIM_CR2_OIS4N_Msk /*!<Output Idle state 4 (OC4N output) */
10008 #define TIM_CR2_OIS5_Pos (16U)
10009 #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
10010 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */
10011 #define TIM_CR2_OIS6_Pos (18U)
10012 #define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
10013 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */
10014
10015 #define TIM_CR2_MMS2_Pos (20U)
10016 #define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
10017 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
10018 #define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
10019 #define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
10020 #define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
10021 #define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
10022
10023 /******************* Bit definition for TIM_SMCR register *******************/
10024 #define TIM_SMCR_SMS_Pos (0U)
10025 #define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
10026 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
10027 #define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
10028 #define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
10029 #define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
10030 #define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
10031
10032 #define TIM_SMCR_OCCS_Pos (3U)
10033 #define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
10034 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
10035
10036 #define TIM_SMCR_TS_Pos (4U)
10037 #define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) /*!< 0x00300070 */
10038 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
10039 #define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
10040 #define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
10041 #define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
10042 #define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos) /*!< 0x00100000 */
10043 #define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos) /*!< 0x00200000 */
10044
10045 #define TIM_SMCR_MSM_Pos (7U)
10046 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
10047 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
10048
10049 #define TIM_SMCR_ETF_Pos (8U)
10050 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
10051 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
10052 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
10053 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
10054 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
10055 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
10056
10057 #define TIM_SMCR_ETPS_Pos (12U)
10058 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
10059 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
10060 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
10061 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
10062
10063 #define TIM_SMCR_ECE_Pos (14U)
10064 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
10065 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
10066 #define TIM_SMCR_ETP_Pos (15U)
10067 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
10068 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
10069
10070 #define TIM_SMCR_SMSPE_Pos (24U)
10071 #define TIM_SMCR_SMSPE_Msk (0x1UL << TIM_SMCR_SMSPE_Pos) /*!< 0x02000000 */
10072 #define TIM_SMCR_SMSPE TIM_SMCR_SMSPE_Msk /*!<SMS preload enable */
10073
10074 #define TIM_SMCR_SMSPS_Pos (25U)
10075 #define TIM_SMCR_SMSPS_Msk (0x1UL << TIM_SMCR_SMSPS_Pos) /*!< 0x04000000 */
10076 #define TIM_SMCR_SMSPS TIM_SMCR_SMSPS_Msk /*!<SMS preload source */
10077
10078 /******************* Bit definition for TIM_DIER register *******************/
10079 #define TIM_DIER_UIE_Pos (0U)
10080 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
10081 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
10082 #define TIM_DIER_CC1IE_Pos (1U)
10083 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
10084 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
10085 #define TIM_DIER_CC2IE_Pos (2U)
10086 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
10087 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
10088 #define TIM_DIER_CC3IE_Pos (3U)
10089 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
10090 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
10091 #define TIM_DIER_CC4IE_Pos (4U)
10092 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
10093 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
10094 #define TIM_DIER_COMIE_Pos (5U)
10095 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
10096 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
10097 #define TIM_DIER_TIE_Pos (6U)
10098 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
10099 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
10100 #define TIM_DIER_BIE_Pos (7U)
10101 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
10102 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
10103 #define TIM_DIER_UDE_Pos (8U)
10104 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
10105 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
10106 #define TIM_DIER_CC1DE_Pos (9U)
10107 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
10108 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
10109 #define TIM_DIER_CC2DE_Pos (10U)
10110 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
10111 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
10112 #define TIM_DIER_CC3DE_Pos (11U)
10113 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
10114 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
10115 #define TIM_DIER_CC4DE_Pos (12U)
10116 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
10117 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
10118 #define TIM_DIER_COMDE_Pos (13U)
10119 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
10120 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
10121 #define TIM_DIER_TDE_Pos (14U)
10122 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
10123 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
10124 #define TIM_DIER_IDXIE_Pos (20U)
10125 #define TIM_DIER_IDXIE_Msk (0x1UL << TIM_DIER_IDXIE_Pos) /*!< 0x00100000 */
10126 #define TIM_DIER_IDXIE TIM_DIER_IDXIE_Msk /*!<Encoder index interrupt enable */
10127 #define TIM_DIER_DIRIE_Pos (21U)
10128 #define TIM_DIER_DIRIE_Msk (0x1UL << TIM_DIER_DIRIE_Pos) /*!< 0x00200000 */
10129 #define TIM_DIER_DIRIE TIM_DIER_DIRIE_Msk /*!<Encoder direction change interrupt enable */
10130 #define TIM_DIER_IERRIE_Pos (22U)
10131 #define TIM_DIER_IERRIE_Msk (0x1UL << TIM_DIER_IERRIE_Pos) /*!< 0x00400000 */
10132 #define TIM_DIER_IERRIE TIM_DIER_IERRIE_Msk /*!<Encoder index error enable */
10133 #define TIM_DIER_TERRIE_Pos (23U)
10134 #define TIM_DIER_TERRIE_Msk (0x1UL << TIM_DIER_TERRIE_Pos) /*!< 0x00800000 */
10135 #define TIM_DIER_TERRIE TIM_DIER_TERRIE_Msk /*!<Encoder transition error enable */
10136
10137 /******************** Bit definition for TIM_SR register ********************/
10138 #define TIM_SR_UIF_Pos (0U)
10139 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
10140 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
10141 #define TIM_SR_CC1IF_Pos (1U)
10142 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
10143 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
10144 #define TIM_SR_CC2IF_Pos (2U)
10145 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
10146 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
10147 #define TIM_SR_CC3IF_Pos (3U)
10148 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
10149 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
10150 #define TIM_SR_CC4IF_Pos (4U)
10151 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
10152 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
10153 #define TIM_SR_COMIF_Pos (5U)
10154 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
10155 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
10156 #define TIM_SR_TIF_Pos (6U)
10157 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
10158 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
10159 #define TIM_SR_BIF_Pos (7U)
10160 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
10161 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
10162 #define TIM_SR_B2IF_Pos (8U)
10163 #define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
10164 #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */
10165 #define TIM_SR_CC1OF_Pos (9U)
10166 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
10167 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
10168 #define TIM_SR_CC2OF_Pos (10U)
10169 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
10170 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
10171 #define TIM_SR_CC3OF_Pos (11U)
10172 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
10173 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
10174 #define TIM_SR_CC4OF_Pos (12U)
10175 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
10176 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
10177 #define TIM_SR_SBIF_Pos (13U)
10178 #define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
10179 #define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
10180 #define TIM_SR_CC5IF_Pos (16U)
10181 #define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
10182 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
10183 #define TIM_SR_CC6IF_Pos (17U)
10184 #define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
10185 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
10186 #define TIM_SR_IDXF_Pos (20U)
10187 #define TIM_SR_IDXF_Msk (0x1UL << TIM_SR_IDXF_Pos) /*!< 0x00100000 */
10188 #define TIM_SR_IDXF TIM_SR_IDXF_Msk /*!<Encoder index interrupt flag */
10189 #define TIM_SR_DIRF_Pos (21U)
10190 #define TIM_SR_DIRF_Msk (0x1UL << TIM_SR_DIRF_Pos) /*!< 0x00200000 */
10191 #define TIM_SR_DIRF TIM_SR_DIRF_Msk /*!<Encoder direction change interrupt flag */
10192 #define TIM_SR_IERRF_Pos (22U)
10193 #define TIM_SR_IERRF_Msk (0x1UL << TIM_SR_IERRF_Pos) /*!< 0x00400000 */
10194 #define TIM_SR_IERRF TIM_SR_IERRF_Msk /*!<Encoder index error flag */
10195 #define TIM_SR_TERRF_Pos (23U)
10196 #define TIM_SR_TERRF_Msk (0x1UL << TIM_SR_TERRF_Pos) /*!< 0x00800000 */
10197 #define TIM_SR_TERRF TIM_SR_TERRF_Msk /*!<Encoder transition error flag */
10198
10199 /******************* Bit definition for TIM_EGR register ********************/
10200 #define TIM_EGR_UG_Pos (0U)
10201 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
10202 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
10203 #define TIM_EGR_CC1G_Pos (1U)
10204 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
10205 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
10206 #define TIM_EGR_CC2G_Pos (2U)
10207 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
10208 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
10209 #define TIM_EGR_CC3G_Pos (3U)
10210 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
10211 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
10212 #define TIM_EGR_CC4G_Pos (4U)
10213 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
10214 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
10215 #define TIM_EGR_COMG_Pos (5U)
10216 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
10217 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
10218 #define TIM_EGR_TG_Pos (6U)
10219 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
10220 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
10221 #define TIM_EGR_BG_Pos (7U)
10222 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */
10223 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
10224 #define TIM_EGR_B2G_Pos (8U)
10225 #define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
10226 #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */
10227
10228
10229 /****************** Bit definition for TIM_CCMR1 register *******************/
10230 #define TIM_CCMR1_CC1S_Pos (0U)
10231 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
10232 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
10233 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
10234 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
10235
10236 #define TIM_CCMR1_OC1FE_Pos (2U)
10237 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
10238 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
10239 #define TIM_CCMR1_OC1PE_Pos (3U)
10240 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
10241 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
10242
10243 #define TIM_CCMR1_OC1M_Pos (4U)
10244 #define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
10245 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
10246 #define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
10247 #define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
10248 #define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
10249 #define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
10250
10251 #define TIM_CCMR1_OC1CE_Pos (7U)
10252 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
10253 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */
10254
10255 #define TIM_CCMR1_CC2S_Pos (8U)
10256 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
10257 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
10258 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
10259 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
10260
10261 #define TIM_CCMR1_OC2FE_Pos (10U)
10262 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
10263 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
10264 #define TIM_CCMR1_OC2PE_Pos (11U)
10265 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
10266 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
10267
10268 #define TIM_CCMR1_OC2M_Pos (12U)
10269 #define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
10270 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
10271 #define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
10272 #define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
10273 #define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
10274 #define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
10275
10276 #define TIM_CCMR1_OC2CE_Pos (15U)
10277 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
10278 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
10279
10280 /*----------------------------------------------------------------------------*/
10281 #define TIM_CCMR1_IC1PSC_Pos (2U)
10282 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
10283 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
10284 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
10285 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
10286
10287 #define TIM_CCMR1_IC1F_Pos (4U)
10288 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
10289 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
10290 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
10291 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
10292 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
10293 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
10294
10295 #define TIM_CCMR1_IC2PSC_Pos (10U)
10296 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
10297 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
10298 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
10299 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
10300
10301 #define TIM_CCMR1_IC2F_Pos (12U)
10302 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
10303 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
10304 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
10305 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
10306 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
10307 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
10308
10309 /****************** Bit definition for TIM_CCMR2 register *******************/
10310 #define TIM_CCMR2_CC3S_Pos (0U)
10311 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
10312 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
10313 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
10314 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
10315
10316 #define TIM_CCMR2_OC3FE_Pos (2U)
10317 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
10318 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
10319 #define TIM_CCMR2_OC3PE_Pos (3U)
10320 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
10321 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
10322
10323 #define TIM_CCMR2_OC3M_Pos (4U)
10324 #define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
10325 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
10326 #define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
10327 #define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
10328 #define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
10329 #define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
10330
10331 #define TIM_CCMR2_OC3CE_Pos (7U)
10332 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
10333 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
10334
10335 #define TIM_CCMR2_CC4S_Pos (8U)
10336 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
10337 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
10338 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
10339 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
10340
10341 #define TIM_CCMR2_OC4FE_Pos (10U)
10342 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
10343 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
10344 #define TIM_CCMR2_OC4PE_Pos (11U)
10345 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
10346 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
10347
10348 #define TIM_CCMR2_OC4M_Pos (12U)
10349 #define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
10350 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
10351 #define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
10352 #define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
10353 #define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
10354 #define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
10355
10356 #define TIM_CCMR2_OC4CE_Pos (15U)
10357 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
10358 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
10359
10360 /*----------------------------------------------------------------------------*/
10361 #define TIM_CCMR2_IC3PSC_Pos (2U)
10362 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
10363 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
10364 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
10365 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
10366
10367 #define TIM_CCMR2_IC3F_Pos (4U)
10368 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
10369 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
10370 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
10371 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
10372 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
10373 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
10374
10375 #define TIM_CCMR2_IC4PSC_Pos (10U)
10376 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
10377 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
10378 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
10379 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
10380
10381 #define TIM_CCMR2_IC4F_Pos (12U)
10382 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
10383 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
10384 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
10385 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
10386 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
10387 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
10388
10389 /****************** Bit definition for TIM_CCMR3 register *******************/
10390 #define TIM_CCMR3_OC5FE_Pos (2U)
10391 #define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
10392 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
10393 #define TIM_CCMR3_OC5PE_Pos (3U)
10394 #define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
10395 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
10396
10397 #define TIM_CCMR3_OC5M_Pos (4U)
10398 #define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
10399 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
10400 #define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
10401 #define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
10402 #define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
10403 #define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
10404
10405 #define TIM_CCMR3_OC5CE_Pos (7U)
10406 #define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
10407 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
10408
10409 #define TIM_CCMR3_OC6FE_Pos (10U)
10410 #define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
10411 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
10412 #define TIM_CCMR3_OC6PE_Pos (11U)
10413 #define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
10414 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */
10415
10416 #define TIM_CCMR3_OC6M_Pos (12U)
10417 #define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
10418 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
10419 #define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
10420 #define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
10421 #define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
10422 #define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
10423
10424 #define TIM_CCMR3_OC6CE_Pos (15U)
10425 #define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
10426 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */
10427
10428 /******************* Bit definition for TIM_CCER register *******************/
10429 #define TIM_CCER_CC1E_Pos (0U)
10430 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
10431 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
10432 #define TIM_CCER_CC1P_Pos (1U)
10433 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
10434 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
10435 #define TIM_CCER_CC1NE_Pos (2U)
10436 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
10437 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
10438 #define TIM_CCER_CC1NP_Pos (3U)
10439 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
10440 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
10441 #define TIM_CCER_CC2E_Pos (4U)
10442 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
10443 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
10444 #define TIM_CCER_CC2P_Pos (5U)
10445 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
10446 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
10447 #define TIM_CCER_CC2NE_Pos (6U)
10448 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
10449 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
10450 #define TIM_CCER_CC2NP_Pos (7U)
10451 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
10452 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
10453 #define TIM_CCER_CC3E_Pos (8U)
10454 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
10455 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
10456 #define TIM_CCER_CC3P_Pos (9U)
10457 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
10458 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
10459 #define TIM_CCER_CC3NE_Pos (10U)
10460 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
10461 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
10462 #define TIM_CCER_CC3NP_Pos (11U)
10463 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
10464 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
10465 #define TIM_CCER_CC4E_Pos (12U)
10466 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
10467 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
10468 #define TIM_CCER_CC4P_Pos (13U)
10469 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
10470 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
10471 #define TIM_CCER_CC4NE_Pos (14U)
10472 #define TIM_CCER_CC4NE_Msk (0x1UL << TIM_CCER_CC4NE_Pos) /*!< 0x00004000 */
10473 #define TIM_CCER_CC4NE TIM_CCER_CC4NE_Msk /*!<Capture/Compare 4 Complementary output enable */
10474 #define TIM_CCER_CC4NP_Pos (15U)
10475 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
10476 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
10477 #define TIM_CCER_CC5E_Pos (16U)
10478 #define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
10479 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
10480 #define TIM_CCER_CC5P_Pos (17U)
10481 #define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
10482 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
10483 #define TIM_CCER_CC6E_Pos (20U)
10484 #define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
10485 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
10486 #define TIM_CCER_CC6P_Pos (21U)
10487 #define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
10488 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
10489
10490 /******************* Bit definition for TIM_CNT register ********************/
10491 #define TIM_CNT_CNT_Pos (0U)
10492 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
10493 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
10494 #define TIM_CNT_UIFCPY_Pos (31U)
10495 #define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
10496 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
10497
10498 /******************* Bit definition for TIM_PSC register ********************/
10499 #define TIM_PSC_PSC_Pos (0U)
10500 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
10501 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
10502
10503 /******************* Bit definition for TIM_ARR register ********************/
10504 #define TIM_ARR_ARR_Pos (0U)
10505 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
10506 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
10507
10508 /******************* Bit definition for TIM_RCR register ********************/
10509 #define TIM_RCR_REP_Pos (0U)
10510 #define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
10511 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
10512
10513 /******************* Bit definition for TIM_CCR1 register *******************/
10514 #define TIM_CCR1_CCR1_Pos (0U)
10515 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
10516 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
10517
10518 /******************* Bit definition for TIM_CCR2 register *******************/
10519 #define TIM_CCR2_CCR2_Pos (0U)
10520 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
10521 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
10522
10523 /******************* Bit definition for TIM_CCR3 register *******************/
10524 #define TIM_CCR3_CCR3_Pos (0U)
10525 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
10526 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
10527
10528 /******************* Bit definition for TIM_CCR4 register *******************/
10529 #define TIM_CCR4_CCR4_Pos (0U)
10530 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
10531 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
10532
10533 /******************* Bit definition for TIM_CCR5 register *******************/
10534 #define TIM_CCR5_CCR5_Pos (0U)
10535 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
10536 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
10537 #define TIM_CCR5_GC5C1_Pos (29U)
10538 #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
10539 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
10540 #define TIM_CCR5_GC5C2_Pos (30U)
10541 #define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
10542 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
10543 #define TIM_CCR5_GC5C3_Pos (31U)
10544 #define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
10545 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
10546
10547 /******************* Bit definition for TIM_CCR6 register *******************/
10548 #define TIM_CCR6_CCR6_Pos (0U)
10549 #define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
10550 #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
10551
10552 /******************* Bit definition for TIM_BDTR register *******************/
10553 #define TIM_BDTR_DTG_Pos (0U)
10554 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
10555 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
10556 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
10557 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
10558 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
10559 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
10560 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
10561 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
10562 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
10563 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
10564
10565 #define TIM_BDTR_LOCK_Pos (8U)
10566 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
10567 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
10568 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
10569 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
10570
10571 #define TIM_BDTR_OSSI_Pos (10U)
10572 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
10573 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
10574 #define TIM_BDTR_OSSR_Pos (11U)
10575 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
10576 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
10577 #define TIM_BDTR_BKE_Pos (12U)
10578 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
10579 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */
10580 #define TIM_BDTR_BKP_Pos (13U)
10581 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
10582 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */
10583 #define TIM_BDTR_AOE_Pos (14U)
10584 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
10585 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
10586 #define TIM_BDTR_MOE_Pos (15U)
10587 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
10588 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
10589
10590 #define TIM_BDTR_BKF_Pos (16U)
10591 #define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
10592 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */
10593 #define TIM_BDTR_BK2F_Pos (20U)
10594 #define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
10595 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */
10596
10597 #define TIM_BDTR_BK2E_Pos (24U)
10598 #define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
10599 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */
10600 #define TIM_BDTR_BK2P_Pos (25U)
10601 #define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
10602 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */
10603
10604 #define TIM_BDTR_BKDSRM_Pos (26U)
10605 #define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
10606 #define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */
10607 #define TIM_BDTR_BK2DSRM_Pos (27U)
10608 #define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
10609 #define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */
10610
10611 #define TIM_BDTR_BKBID_Pos (28U)
10612 #define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
10613 #define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break BIDirectional */
10614 #define TIM_BDTR_BK2BID_Pos (29U)
10615 #define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
10616 #define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 BIDirectional */
10617
10618 /******************* Bit definition for TIM_DCR register ********************/
10619 #define TIM_DCR_DBA_Pos (0U)
10620 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
10621 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
10622 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
10623 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
10624 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
10625 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
10626 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
10627
10628 #define TIM_DCR_DBL_Pos (8U)
10629 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
10630 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
10631 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
10632 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
10633 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
10634 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
10635 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
10636
10637 /******************* Bit definition for TIM1_AF1 register *******************/
10638 #define TIM1_AF1_BKINE_Pos (0U)
10639 #define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */
10640 #define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BRK BKIN input enable */
10641 #define TIM1_AF1_BKCMP1E_Pos (1U)
10642 #define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
10643 #define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */
10644 #define TIM1_AF1_BKCMP2E_Pos (2U)
10645 #define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
10646 #define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */
10647 #define TIM1_AF1_BKCMP3E_Pos (3U)
10648 #define TIM1_AF1_BKCMP3E_Msk (0x1UL << TIM1_AF1_BKCMP3E_Pos) /*!< 0x00000008 */
10649 #define TIM1_AF1_BKCMP3E TIM1_AF1_BKCMP3E_Msk /*!<BRK COMP3 enable */
10650 #define TIM1_AF1_BKCMP4E_Pos (4U)
10651 #define TIM1_AF1_BKCMP4E_Msk (0x1UL << TIM1_AF1_BKCMP4E_Pos) /*!< 0x00000010 */
10652 #define TIM1_AF1_BKCMP4E TIM1_AF1_BKCMP4E_Msk /*!<BRK COMP4 enable */
10653 #define TIM1_AF1_BKINP_Pos (9U)
10654 #define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */
10655 #define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
10656 #define TIM1_AF1_BKCMP1P_Pos (10U)
10657 #define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
10658 #define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
10659 #define TIM1_AF1_BKCMP2P_Pos (11U)
10660 #define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
10661 #define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
10662 #define TIM1_AF1_BKCMP3P_Pos (12U)
10663 #define TIM1_AF1_BKCMP3P_Msk (0x1UL << TIM1_AF1_BKCMP3P_Pos) /*!< 0x00001000 */
10664 #define TIM1_AF1_BKCMP3P TIM1_AF1_BKCMP3P_Msk /*!<BRK COMP3 input polarity */
10665 #define TIM1_AF1_BKCMP4P_Pos (13U)
10666 #define TIM1_AF1_BKCMP4P_Msk (0x1UL << TIM1_AF1_BKCMP4P_Pos) /*!< 0x00002000 */
10667 #define TIM1_AF1_BKCMP4P TIM1_AF1_BKCMP4P_Msk /*!<BRK COMP4 input polarity */
10668 #define TIM1_AF1_ETRSEL_Pos (14U)
10669 #define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
10670 #define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
10671 #define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00004000 */
10672 #define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */
10673 #define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00010000 */
10674 #define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */
10675
10676 /******************* Bit definition for TIM1_AF2 register *********************/
10677 #define TIM1_AF2_BK2INE_Pos (0U)
10678 #define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */
10679 #define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BRK2 BKIN input enable */
10680 #define TIM1_AF2_BK2CMP1E_Pos (1U)
10681 #define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */
10682 #define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
10683 #define TIM1_AF2_BK2CMP2E_Pos (2U)
10684 #define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */
10685 #define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
10686 #define TIM1_AF2_BK2CMP3E_Pos (3U)
10687 #define TIM1_AF2_BK2CMP3E_Msk (0x1UL << TIM1_AF2_BK2CMP3E_Pos) /*!< 0x00000008 */
10688 #define TIM1_AF2_BK2CMP3E TIM1_AF2_BK2CMP3E_Msk /*!<BRK2 COMP3 enable */
10689 #define TIM1_AF2_BK2CMP4E_Pos (4U)
10690 #define TIM1_AF2_BK2CMP4E_Msk (0x1UL << TIM1_AF2_BK2CMP4E_Pos) /*!< 0x00000010 */
10691 #define TIM1_AF2_BK2CMP4E TIM1_AF2_BK2CMP4E_Msk /*!<BRK2 COMP4 enable */
10692 #define TIM1_AF2_BK2INP_Pos (9U)
10693 #define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */
10694 #define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRK2 BKIN input polarity */
10695 #define TIM1_AF2_BK2CMP1P_Pos (10U)
10696 #define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */
10697 #define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
10698 #define TIM1_AF2_BK2CMP2P_Pos (11U)
10699 #define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */
10700 #define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
10701 #define TIM1_AF2_BK2CMP3P_Pos (12U)
10702 #define TIM1_AF2_BK2CMP3P_Msk (0x1UL << TIM1_AF2_BK2CMP3P_Pos) /*!< 0x00000400 */
10703 #define TIM1_AF2_BK2CMP3P TIM1_AF2_BK2CMP3P_Msk /*!<BRK2 COMP3 input polarity */
10704 #define TIM1_AF2_BK2CMP4P_Pos (13U)
10705 #define TIM1_AF2_BK2CMP4P_Msk (0x1UL << TIM1_AF2_BK2CMP4P_Pos) /*!< 0x00000800 */
10706 #define TIM1_AF2_BK2CMP4P TIM1_AF2_BK2CMP4P_Msk /*!<BRK2 COMP4 input polarity */
10707 #define TIM1_AF2_OCRSEL_Pos (16U)
10708 #define TIM1_AF2_OCRSEL_Msk (0x7UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00070000 */
10709 #define TIM1_AF2_OCRSEL TIM1_AF2_OCRSEL_Msk /*!<BRK2 COMP2 input polarity */
10710 #define TIM1_AF2_OCRSEL_0 (0x1UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00010000 */
10711 #define TIM1_AF2_OCRSEL_1 (0x2UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00020000 */
10712 #define TIM1_AF2_OCRSEL_2 (0x4UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00040000 */
10713
10714 /******************* Bit definition for TIM_OR register *********************/
10715 #define TIM_OR_HSE32EN_Pos (0U)
10716 #define TIM_OR_HSE32EN_Msk (0x1UL << TIM_OR_HSE32EN_Pos) /*!< 0x00000001 */
10717 #define TIM_OR_HSE32EN TIM_OR_HSE32EN_Msk /*!< HSE/32 clock enable */
10718
10719 /******************* Bit definition for TIM_TISEL register *********************/
10720 #define TIM_TISEL_TI1SEL_Pos (0U)
10721 #define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
10722 #define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
10723 #define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
10724 #define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
10725 #define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
10726 #define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
10727
10728 #define TIM_TISEL_TI2SEL_Pos (8U)
10729 #define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
10730 #define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
10731 #define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
10732 #define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
10733 #define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
10734 #define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
10735
10736 #define TIM_TISEL_TI3SEL_Pos (16U)
10737 #define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
10738 #define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/
10739 #define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
10740 #define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
10741 #define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
10742 #define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
10743
10744 #define TIM_TISEL_TI4SEL_Pos (24U)
10745 #define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
10746 #define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/
10747 #define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
10748 #define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
10749 #define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
10750 #define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
10751
10752 /******************* Bit definition for TIM_DTR2 register *********************/
10753 #define TIM_DTR2_DTGF_Pos (0U)
10754 #define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F */
10755 #define TIM_DTR2_DTGF TIM_DTR2_DTGF_Msk /*!<DTGF[7:0] bits (Deadtime falling edge generator setup)*/
10756 #define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001 */
10757 #define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002 */
10758 #define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004 */
10759 #define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008 */
10760 #define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010 */
10761 #define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020 */
10762 #define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040 */
10763 #define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080 */
10764
10765 #define TIM_DTR2_DTAE_Pos (16U)
10766 #define TIM_DTR2_DTAE_Msk (0x1UL << TIM_DTR2_DTAE_Pos) /*!< 0x00004000 */
10767 #define TIM_DTR2_DTAE TIM_DTR2_DTAE_Msk /*!<Deadtime asymmetric enable */
10768 #define TIM_DTR2_DTPE_Pos (17U)
10769 #define TIM_DTR2_DTPE_Msk (0x1UL << TIM_DTR2_DTPE_Pos) /*!< 0x00008000 */
10770 #define TIM_DTR2_DTPE TIM_DTR2_DTPE_Msk /*!<Deadtime prelaod enable */
10771
10772 /******************* Bit definition for TIM_ECR register *********************/
10773 #define TIM_ECR_IE_Pos (0U)
10774 #define TIM_ECR_IE_Msk (0x1UL << TIM_ECR_IE_Pos) /*!< 0x00000001 */
10775 #define TIM_ECR_IE TIM_ECR_IE_Msk /*!<Index enable */
10776
10777 #define TIM_ECR_IDIR_Pos (1U)
10778 #define TIM_ECR_IDIR_Msk (0x3UL << TIM_ECR_IDIR_Pos) /*!< 0x00000006 */
10779 #define TIM_ECR_IDIR TIM_ECR_IDIR_Msk /*!<IDIR[1:0] bits (Index direction)*/
10780 #define TIM_ECR_IDIR_0 (0x01UL << TIM_ECR_IDIR_Pos) /*!< 0x00000001 */
10781 #define TIM_ECR_IDIR_1 (0x02UL << TIM_ECR_IDIR_Pos) /*!< 0x00000002 */
10782
10783 #define TIM_ECR_FIDX_Pos (5U)
10784 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
10785 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index enable */
10786
10787 #define TIM_ECR_IPOS_Pos (6U)
10788 #define TIM_ECR_IPOS_Msk (0x3UL << TIM_ECR_IPOS_Pos) /*!< 0x0000000C0 */
10789 #define TIM_ECR_IPOS TIM_ECR_IPOS_Msk /*!<IPOS[1:0] bits (Index positioning)*/
10790 #define TIM_ECR_IPOS_0 (0x01UL << TIM_ECR_IPOS_Pos) /*!< 0x00000001 */
10791 #define TIM_ECR_IPOS_1 (0x02UL << TIM_ECR_IPOS_Pos) /*!< 0x00000002 */
10792
10793 #define TIM_ECR_PW_Pos (16U)
10794 #define TIM_ECR_PW_Msk (0xFFUL << TIM_ECR_PW_Pos) /*!< 0x00FF0000 */
10795 #define TIM_ECR_PW TIM_ECR_PW_Msk /*!<PW[7:0] bits (Pulse width)*/
10796 #define TIM_ECR_PW_0 (0x01UL << TIM_ECR_PW_Pos) /*!< 0x00010000 */
10797 #define TIM_ECR_PW_1 (0x02UL << TIM_ECR_PW_Pos) /*!< 0x00020000 */
10798 #define TIM_ECR_PW_2 (0x04UL << TIM_ECR_PW_Pos) /*!< 0x00040000 */
10799 #define TIM_ECR_PW_3 (0x08UL << TIM_ECR_PW_Pos) /*!< 0x00080000 */
10800 #define TIM_ECR_PW_4 (0x10UL << TIM_ECR_PW_Pos) /*!< 0x00100000 */
10801 #define TIM_ECR_PW_5 (0x20UL << TIM_ECR_PW_Pos) /*!< 0x00200000 */
10802 #define TIM_ECR_PW_6 (0x40UL << TIM_ECR_PW_Pos) /*!< 0x00400000 */
10803 #define TIM_ECR_PW_7 (0x80UL << TIM_ECR_PW_Pos) /*!< 0x00800000 */
10804
10805 #define TIM_ECR_PWPRSC_Pos (24U)
10806 #define TIM_ECR_PWPRSC_Msk (0x7UL << TIM_ECR_PWPRSC_Pos) /*!< 0x07000000 */
10807 #define TIM_ECR_PWPRSC TIM_ECR_PWPRSC_Msk /*!<PWPRSC[2:0] bits (Pulse width prescaler)*/
10808 #define TIM_ECR_PWPRSC_0 (0x01UL << TIM_ECR_PWPRSC_Pos) /*!< 0x01000000 */
10809 #define TIM_ECR_PWPRSC_1 (0x02UL << TIM_ECR_PWPRSC_Pos) /*!< 0x02000000 */
10810 #define TIM_ECR_PWPRSC_2 (0x04UL << TIM_ECR_PWPRSC_Pos) /*!< 0x04000000 */
10811
10812 /******************* Bit definition for TIM_DMAR register *******************/
10813 #define TIM_DMAR_DMAB_Pos (0U)
10814 #define TIM_DMAR_DMAB_Msk (0xFFFFFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0xFFFFFFFF */
10815 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
10816
10817 /******************************************************************************/
10818 /* */
10819 /* Low Power Timer (LPTIM) */
10820 /* */
10821 /******************************************************************************/
10822 /****************** Bit definition for LPTIM_ISR register *******************/
10823 #define LPTIM_ISR_CMPM_Pos (0U)
10824 #define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
10825 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
10826 #define LPTIM_ISR_ARRM_Pos (1U)
10827 #define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
10828 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
10829 #define LPTIM_ISR_EXTTRIG_Pos (2U)
10830 #define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
10831 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
10832 #define LPTIM_ISR_CMPOK_Pos (3U)
10833 #define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
10834 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
10835 #define LPTIM_ISR_ARROK_Pos (4U)
10836 #define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
10837 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
10838 #define LPTIM_ISR_UP_Pos (5U)
10839 #define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
10840 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
10841 #define LPTIM_ISR_DOWN_Pos (6U)
10842 #define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
10843 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
10844
10845 /****************** Bit definition for LPTIM_ICR register *******************/
10846 #define LPTIM_ICR_CMPMCF_Pos (0U)
10847 #define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
10848 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
10849 #define LPTIM_ICR_ARRMCF_Pos (1U)
10850 #define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
10851 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
10852 #define LPTIM_ICR_EXTTRIGCF_Pos (2U)
10853 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
10854 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
10855 #define LPTIM_ICR_CMPOKCF_Pos (3U)
10856 #define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
10857 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
10858 #define LPTIM_ICR_ARROKCF_Pos (4U)
10859 #define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
10860 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
10861 #define LPTIM_ICR_UPCF_Pos (5U)
10862 #define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
10863 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
10864 #define LPTIM_ICR_DOWNCF_Pos (6U)
10865 #define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
10866 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
10867
10868 /****************** Bit definition for LPTIM_IER register ********************/
10869 #define LPTIM_IER_CMPMIE_Pos (0U)
10870 #define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
10871 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
10872 #define LPTIM_IER_ARRMIE_Pos (1U)
10873 #define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
10874 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
10875 #define LPTIM_IER_EXTTRIGIE_Pos (2U)
10876 #define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
10877 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
10878 #define LPTIM_IER_CMPOKIE_Pos (3U)
10879 #define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
10880 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
10881 #define LPTIM_IER_ARROKIE_Pos (4U)
10882 #define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
10883 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
10884 #define LPTIM_IER_UPIE_Pos (5U)
10885 #define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
10886 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
10887 #define LPTIM_IER_DOWNIE_Pos (6U)
10888 #define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
10889 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
10890
10891 /****************** Bit definition for LPTIM_CFGR register *******************/
10892 #define LPTIM_CFGR_CKSEL_Pos (0U)
10893 #define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
10894 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
10895
10896 #define LPTIM_CFGR_CKPOL_Pos (1U)
10897 #define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
10898 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
10899 #define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
10900 #define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
10901
10902 #define LPTIM_CFGR_CKFLT_Pos (3U)
10903 #define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
10904 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
10905 #define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
10906 #define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
10907
10908 #define LPTIM_CFGR_TRGFLT_Pos (6U)
10909 #define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
10910 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
10911 #define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
10912 #define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
10913
10914 #define LPTIM_CFGR_PRESC_Pos (9U)
10915 #define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
10916 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
10917 #define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
10918 #define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
10919 #define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
10920
10921 #define LPTIM_CFGR_TRIGSEL_Pos (13U)
10922 #define LPTIM_CFGR_TRIGSEL_Msk (0x10007UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0200E000 */
10923 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
10924 #define LPTIM_CFGR_TRIGSEL_0 (0x00001UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
10925 #define LPTIM_CFGR_TRIGSEL_1 (0x00002UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
10926 #define LPTIM_CFGR_TRIGSEL_2 (0x00004UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
10927 #define LPTIM_CFGR_TRIGSEL_3 (0x10000UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x02000000 */
10928
10929 #define LPTIM_CFGR_TRIGEN_Pos (17U)
10930 #define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
10931 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
10932 #define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
10933 #define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
10934
10935 #define LPTIM_CFGR_TIMOUT_Pos (19U)
10936 #define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
10937 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
10938 #define LPTIM_CFGR_WAVE_Pos (20U)
10939 #define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
10940 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
10941 #define LPTIM_CFGR_WAVPOL_Pos (21U)
10942 #define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
10943 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
10944 #define LPTIM_CFGR_PRELOAD_Pos (22U)
10945 #define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
10946 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
10947 #define LPTIM_CFGR_COUNTMODE_Pos (23U)
10948 #define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
10949 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
10950 #define LPTIM_CFGR_ENC_Pos (24U)
10951 #define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
10952 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
10953
10954 /****************** Bit definition for LPTIM_CR register ********************/
10955 #define LPTIM_CR_ENABLE_Pos (0U)
10956 #define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
10957 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
10958 #define LPTIM_CR_SNGSTRT_Pos (1U)
10959 #define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
10960 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
10961 #define LPTIM_CR_CNTSTRT_Pos (2U)
10962 #define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
10963 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
10964 #define LPTIM_CR_COUNTRST_Pos (3U)
10965 #define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */
10966 #define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Counter reset */
10967 #define LPTIM_CR_RSTARE_Pos (4U)
10968 #define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */
10969 #define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Reset after read enable */
10970
10971 /****************** Bit definition for LPTIM_CMP register *******************/
10972 #define LPTIM_CMP_CMP_Pos (0U)
10973 #define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
10974 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
10975
10976 /****************** Bit definition for LPTIM_ARR register *******************/
10977 #define LPTIM_ARR_ARR_Pos (0U)
10978 #define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
10979 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
10980
10981 /****************** Bit definition for LPTIM_CNT register *******************/
10982 #define LPTIM_CNT_CNT_Pos (0U)
10983 #define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
10984 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
10985
10986 /****************** Bit definition for LPTIM_OR register *******************/
10987 #define LPTIM_OR_IN1_Pos (0U)
10988 #define LPTIM_OR_IN1_Msk (0xDUL << LPTIM_OR_IN1_Pos) /*!< 0x0000000D */
10989 #define LPTIM_OR_IN1 LPTIM_OR_IN1_Msk /*!< IN1[2:0] bits (Remap selection) */
10990 #define LPTIM_OR_IN1_0 (0x1UL << LPTIM_OR_IN1_Pos) /*!< 0x00000001 */
10991 #define LPTIM_OR_IN1_1 (0x4UL << LPTIM_OR_IN1_Pos) /*!< 0x00000004 */
10992 #define LPTIM_OR_IN1_2 (0x8UL << LPTIM_OR_IN1_Pos) /*!< 0x00000008 */
10993
10994 #define LPTIM_OR_IN2_Pos (1U)
10995 #define LPTIM_OR_IN2_Msk (0x19UL << LPTIM_OR_IN2_Pos) /*!< 0x00000032 */
10996 #define LPTIM_OR_IN2 LPTIM_OR_IN2_Msk /*!< IN2[2:0] bits (Remap selection) */
10997 #define LPTIM_OR_IN2_0 (0x1UL << LPTIM_OR_IN2_Pos) /*!< 0x00000002 */
10998 #define LPTIM_OR_IN2_1 (0x8UL << LPTIM_OR_IN2_Pos) /*!< 0x00000010 */
10999 #define LPTIM_OR_IN2_2 (0x10UL << LPTIM_OR_IN2_Pos) /*!< 0x00000020 */
11000 /******************************************************************************/
11001 /* */
11002 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
11003 /* */
11004 /******************************************************************************/
11005 /****************** Bit definition for USART_CR1 register *******************/
11006 #define USART_CR1_UE_Pos (0U)
11007 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
11008 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
11009 #define USART_CR1_UESM_Pos (1U)
11010 #define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
11011 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
11012 #define USART_CR1_RE_Pos (2U)
11013 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
11014 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
11015 #define USART_CR1_TE_Pos (3U)
11016 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
11017 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
11018 #define USART_CR1_IDLEIE_Pos (4U)
11019 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
11020 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
11021 #define USART_CR1_RXNEIE_Pos (5U)
11022 #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
11023 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
11024 #define USART_CR1_RXNEIE_RXFNEIE_Pos USART_CR1_RXNEIE_Pos
11025 #define USART_CR1_RXNEIE_RXFNEIE_Msk USART_CR1_RXNEIE_Msk /*!< 0x00000020 */
11026 #define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_Msk /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
11027 #define USART_CR1_TCIE_Pos (6U)
11028 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
11029 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
11030 #define USART_CR1_TXEIE_Pos (7U)
11031 #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
11032 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
11033 #define USART_CR1_TXEIE_TXFNFIE_Pos USART_CR1_TXEIE_Pos
11034 #define USART_CR1_TXEIE_TXFNFIE_Msk USART_CR1_TXEIE_Msk /*!< 0x00000080 */
11035 #define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_Msk /*!< TXE and TX FIFO Not Full Interrupt Enable */
11036 #define USART_CR1_PEIE_Pos (8U)
11037 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
11038 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
11039 #define USART_CR1_PS_Pos (9U)
11040 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
11041 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
11042 #define USART_CR1_PCE_Pos (10U)
11043 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
11044 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
11045 #define USART_CR1_WAKE_Pos (11U)
11046 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
11047 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
11048 #define USART_CR1_M_Pos (12U)
11049 #define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
11050 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
11051 #define USART_CR1_M0_Pos (12U)
11052 #define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
11053 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
11054 #define USART_CR1_MME_Pos (13U)
11055 #define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
11056 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
11057 #define USART_CR1_CMIE_Pos (14U)
11058 #define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
11059 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
11060 #define USART_CR1_OVER8_Pos (15U)
11061 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
11062 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
11063 #define USART_CR1_DEDT_Pos (16U)
11064 #define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
11065 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
11066 #define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
11067 #define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
11068 #define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
11069 #define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
11070 #define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
11071 #define USART_CR1_DEAT_Pos (21U)
11072 #define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
11073 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
11074 #define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
11075 #define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
11076 #define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
11077 #define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
11078 #define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
11079 #define USART_CR1_RTOIE_Pos (26U)
11080 #define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
11081 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
11082 #define USART_CR1_EOBIE_Pos (27U)
11083 #define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
11084 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
11085 #define USART_CR1_M1_Pos (28U)
11086 #define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
11087 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
11088 #define USART_CR1_FIFOEN_Pos (29U)
11089 #define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */
11090 #define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */
11091 #define USART_CR1_TXFEIE_Pos (30U)
11092 #define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */
11093 #define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */
11094 #define USART_CR1_RXFFIE_Pos (31U)
11095 #define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */
11096 #define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */
11097
11098 /****************** Bit definition for USART_CR2 register *******************/
11099 #define USART_CR2_SLVEN_Pos (0U)
11100 #define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */
11101 #define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode enable */
11102 #define USART_CR2_DIS_NSS_Pos (3U)
11103 #define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */
11104 #define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< Slave Select (NSS) pin management */
11105 #define USART_CR2_ADDM7_Pos (4U)
11106 #define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
11107 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
11108 #define USART_CR2_LBDL_Pos (5U)
11109 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
11110 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
11111 #define USART_CR2_LBDIE_Pos (6U)
11112 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
11113 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
11114 #define USART_CR2_LBCL_Pos (8U)
11115 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
11116 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
11117 #define USART_CR2_CPHA_Pos (9U)
11118 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
11119 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
11120 #define USART_CR2_CPOL_Pos (10U)
11121 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
11122 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
11123 #define USART_CR2_CLKEN_Pos (11U)
11124 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
11125 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
11126 #define USART_CR2_STOP_Pos (12U)
11127 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
11128 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
11129 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
11130 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
11131 #define USART_CR2_LINEN_Pos (14U)
11132 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
11133 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
11134 #define USART_CR2_SWAP_Pos (15U)
11135 #define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
11136 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
11137 #define USART_CR2_RXINV_Pos (16U)
11138 #define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
11139 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
11140 #define USART_CR2_TXINV_Pos (17U)
11141 #define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
11142 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
11143 #define USART_CR2_DATAINV_Pos (18U)
11144 #define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
11145 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
11146 #define USART_CR2_MSBFIRST_Pos (19U)
11147 #define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
11148 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
11149 #define USART_CR2_ABREN_Pos (20U)
11150 #define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
11151 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
11152 #define USART_CR2_ABRMODE_Pos (21U)
11153 #define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
11154 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
11155 #define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
11156 #define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
11157 #define USART_CR2_RTOEN_Pos (23U)
11158 #define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
11159 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
11160 #define USART_CR2_ADD_Pos (24U)
11161 #define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
11162 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
11163
11164 /****************** Bit definition for USART_CR3 register *******************/
11165 #define USART_CR3_EIE_Pos (0U)
11166 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
11167 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
11168 #define USART_CR3_IREN_Pos (1U)
11169 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
11170 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
11171 #define USART_CR3_IRLP_Pos (2U)
11172 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
11173 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
11174 #define USART_CR3_HDSEL_Pos (3U)
11175 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
11176 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
11177 #define USART_CR3_NACK_Pos (4U)
11178 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
11179 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
11180 #define USART_CR3_SCEN_Pos (5U)
11181 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
11182 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
11183 #define USART_CR3_DMAR_Pos (6U)
11184 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
11185 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
11186 #define USART_CR3_DMAT_Pos (7U)
11187 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
11188 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
11189 #define USART_CR3_RTSE_Pos (8U)
11190 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
11191 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
11192 #define USART_CR3_CTSE_Pos (9U)
11193 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
11194 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
11195 #define USART_CR3_CTSIE_Pos (10U)
11196 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
11197 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
11198 #define USART_CR3_ONEBIT_Pos (11U)
11199 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
11200 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
11201 #define USART_CR3_OVRDIS_Pos (12U)
11202 #define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
11203 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
11204 #define USART_CR3_DDRE_Pos (13U)
11205 #define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
11206 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
11207 #define USART_CR3_DEM_Pos (14U)
11208 #define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
11209 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
11210 #define USART_CR3_DEP_Pos (15U)
11211 #define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
11212 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
11213 #define USART_CR3_SCARCNT_Pos (17U)
11214 #define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
11215 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
11216 #define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
11217 #define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
11218 #define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
11219 #define USART_CR3_WUS_Pos (20U)
11220 #define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
11221 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
11222 #define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
11223 #define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
11224 #define USART_CR3_WUFIE_Pos (22U)
11225 #define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
11226 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
11227 #define USART_CR3_TXFTIE_Pos (23U)
11228 #define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */
11229 #define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */
11230 #define USART_CR3_TCBGTIE_Pos (24U)
11231 #define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
11232 #define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */
11233 #define USART_CR3_RXFTCFG_Pos (25U)
11234 #define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */
11235 #define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFIFO FIFO threshold configuration */
11236 #define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */
11237 #define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */
11238 #define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */
11239 #define USART_CR3_RXFTIE_Pos (28U)
11240 #define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */
11241 #define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */
11242 #define USART_CR3_TXFTCFG_Pos (29U)
11243 #define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */
11244 #define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFIFO threshold configuration */
11245 #define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */
11246 #define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */
11247 #define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */
11248
11249 /****************** Bit definition for USART_BRR register *******************/
11250 #define USART_BRR_LPUART_Pos (0U)
11251 #define USART_BRR_LPUART_Msk (0xFFFFFUL << USART_BRR_LPUART_Pos) /*!< 0x000FFFFF */
11252 #define USART_BRR_LPUART USART_BRR_LPUART_Msk /*!< LPUART Baud rate register [19:0] */
11253 #define USART_BRR_BRR_Pos (0U)
11254 #define USART_BRR_BRR_Msk (0xFFFFUL << USART_BRR_BRR_Pos) /*!< 0x0000FFFF */
11255 #define USART_BRR_BRR USART_BRR_BRR_Msk /*!< USART Baud rate register [15:0] */
11256
11257 /****************** Bit definition for USART_GTPR register ******************/
11258 #define USART_GTPR_PSC_Pos (0U)
11259 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
11260 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
11261 #define USART_GTPR_GT_Pos (8U)
11262 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
11263 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
11264
11265 /******************* Bit definition for USART_RTOR register *****************/
11266 #define USART_RTOR_RTO_Pos (0U)
11267 #define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
11268 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
11269 #define USART_RTOR_BLEN_Pos (24U)
11270 #define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
11271 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
11272
11273 /******************* Bit definition for USART_RQR register ******************/
11274 #define USART_RQR_ABRRQ_Pos (0U)
11275 #define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
11276 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
11277 #define USART_RQR_SBKRQ_Pos (1U)
11278 #define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
11279 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
11280 #define USART_RQR_MMRQ_Pos (2U)
11281 #define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
11282 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
11283 #define USART_RQR_RXFRQ_Pos (3U)
11284 #define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
11285 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
11286 #define USART_RQR_TXFRQ_Pos (4U)
11287 #define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
11288 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
11289
11290 /******************* Bit definition for USART_ISR register ******************/
11291 #define USART_ISR_PE_Pos (0U)
11292 #define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
11293 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
11294 #define USART_ISR_FE_Pos (1U)
11295 #define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
11296 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
11297 #define USART_ISR_NE_Pos (2U)
11298 #define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
11299 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
11300 #define USART_ISR_ORE_Pos (3U)
11301 #define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
11302 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
11303 #define USART_ISR_IDLE_Pos (4U)
11304 #define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
11305 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
11306 #define USART_ISR_RXNE_Pos (5U)
11307 #define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
11308 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
11309 #define USART_ISR_RXNE_RXFNE_Pos USART_ISR_RXNE_Pos
11310 #define USART_ISR_RXNE_RXFNE_Msk USART_ISR_RXNE_Msk /*!< 0x00000020 */
11311 #define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_Msk /*!< Read Data Register or RX FIFO Not Empty */
11312 #define USART_ISR_TC_Pos (6U)
11313 #define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
11314 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
11315 #define USART_ISR_TXE_Pos (7U)
11316 #define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */
11317 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
11318 #define USART_ISR_TXE_TXFNF_Pos USART_ISR_TXE_Pos
11319 #define USART_ISR_TXE_TXFNF_Msk USART_ISR_TXE_Msk /*!< 0x00000080 */
11320 #define USART_ISR_TXE_TXFNF USART_ISR_TXE_Msk /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
11321 #define USART_ISR_LBDF_Pos (8U)
11322 #define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
11323 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
11324 #define USART_ISR_CTSIF_Pos (9U)
11325 #define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
11326 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
11327 #define USART_ISR_CTS_Pos (10U)
11328 #define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
11329 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
11330 #define USART_ISR_RTOF_Pos (11U)
11331 #define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
11332 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
11333 #define USART_ISR_EOBF_Pos (12U)
11334 #define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
11335 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
11336 #define USART_ISR_UDR_Pos (13U)
11337 #define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) /*!< 0x00002000 */
11338 #define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI slave underrun error flag */
11339 #define USART_ISR_ABRE_Pos (14U)
11340 #define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
11341 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
11342 #define USART_ISR_ABRF_Pos (15U)
11343 #define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
11344 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
11345 #define USART_ISR_BUSY_Pos (16U)
11346 #define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
11347 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
11348 #define USART_ISR_CMF_Pos (17U)
11349 #define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
11350 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
11351 #define USART_ISR_SBKF_Pos (18U)
11352 #define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
11353 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
11354 #define USART_ISR_RWU_Pos (19U)
11355 #define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
11356 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
11357 #define USART_ISR_WUF_Pos (20U)
11358 #define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
11359 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
11360 #define USART_ISR_TEACK_Pos (21U)
11361 #define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
11362 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
11363 #define USART_ISR_REACK_Pos (22U)
11364 #define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
11365 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
11366 #define USART_ISR_TXFE_Pos (23U)
11367 #define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) /*!< 0x00800000 */
11368 #define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty */
11369 #define USART_ISR_RXFF_Pos (24U)
11370 #define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) /*!< 0x01000000 */
11371 #define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full */
11372 #define USART_ISR_TCBGT_Pos (25U)
11373 #define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
11374 #define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time completion */
11375 #define USART_ISR_RXFT_Pos (26U)
11376 #define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) /*!< 0x04000000 */
11377 #define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO threshold flag */
11378 #define USART_ISR_TXFT_Pos (27U)
11379 #define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) /*!< 0x08000000 */
11380 #define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO threshold flag */
11381
11382 /******************* Bit definition for USART_ICR register ******************/
11383 #define USART_ICR_PECF_Pos (0U)
11384 #define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
11385 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
11386 #define USART_ICR_FECF_Pos (1U)
11387 #define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
11388 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
11389 #define USART_ICR_NECF_Pos (2U)
11390 #define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */
11391 #define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise detected Clear Flag */
11392 #define USART_ICR_ORECF_Pos (3U)
11393 #define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
11394 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
11395 #define USART_ICR_IDLECF_Pos (4U)
11396 #define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
11397 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
11398 #define USART_ICR_TXFECF_Pos (5U)
11399 #define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */
11400 #define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO empty Clear flag */
11401 #define USART_ICR_TCCF_Pos (6U)
11402 #define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
11403 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
11404 #define USART_ICR_TCBGTCF_Pos (7U)
11405 #define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
11406 #define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */
11407 #define USART_ICR_LBDCF_Pos (8U)
11408 #define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
11409 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
11410 #define USART_ICR_CTSCF_Pos (9U)
11411 #define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
11412 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
11413 #define USART_ICR_RTOCF_Pos (11U)
11414 #define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
11415 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
11416 #define USART_ICR_EOBCF_Pos (12U)
11417 #define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
11418 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
11419 #define USART_ICR_UDRCF_Pos (13U)
11420 #define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */
11421 #define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI Slave Underrun Clear Flag */
11422 #define USART_ICR_CMCF_Pos (17U)
11423 #define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
11424 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
11425 #define USART_ICR_WUCF_Pos (20U)
11426 #define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
11427 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
11428
11429 /******************* Bit definition for USART_RDR register ******************/
11430 #define USART_RDR_RDR_Pos (0U)
11431 #define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
11432 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
11433
11434 /******************* Bit definition for USART_TDR register ******************/
11435 #define USART_TDR_TDR_Pos (0U)
11436 #define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
11437 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
11438
11439 /******************* Bit definition for USART_PRESC register ****************/
11440 #define USART_PRESC_PRESCALER_Pos (0U)
11441 #define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */
11442 #define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */
11443 #define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */
11444 #define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */
11445 #define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
11446 #define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
11447
11448
11449 /******************************************************************************/
11450 /* */
11451 /* USB Device FS Endpoint registers */
11452 /* */
11453 /******************************************************************************/
11454 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
11455 #define USB_EP1R (USB_BASE + 0x0x00000004) /*!< endpoint 1 register address */
11456 #define USB_EP2R (USB_BASE + 0x0x00000008) /*!< endpoint 2 register address */
11457 #define USB_EP3R (USB_BASE + 0x0x0000000C) /*!< endpoint 3 register address */
11458 #define USB_EP4R (USB_BASE + 0x0x00000010) /*!< endpoint 4 register address */
11459 #define USB_EP5R (USB_BASE + 0x0x00000014) /*!< endpoint 5 register address */
11460 #define USB_EP6R (USB_BASE + 0x0x00000018) /*!< endpoint 6 register address */
11461 #define USB_EP7R (USB_BASE + 0x0x0000001C) /*!< endpoint 7 register address */
11462
11463 /* bit positions */
11464 #define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
11465 #define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
11466 #define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
11467 #define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
11468 #define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
11469 #define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
11470 #define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
11471 #define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
11472 #define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
11473 #define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
11474
11475 /* EndPoint REGister MASK (no toggle fields) */
11476 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
11477 /*!< EP_TYPE[1:0] EndPoint TYPE */
11478 #define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
11479 #define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
11480 #define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
11481 #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
11482 #define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
11483 #define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
11484
11485 #define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
11486 /*!< STAT_TX[1:0] STATus for TX transfer */
11487 #define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
11488 #define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
11489 #define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
11490 #define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
11491 #define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
11492 #define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
11493 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
11494 /*!< STAT_RX[1:0] STATus for RX transfer */
11495 #define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
11496 #define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
11497 #define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
11498 #define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
11499 #define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
11500 #define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
11501 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
11502
11503 /******************************************************************************/
11504 /* */
11505 /* USB Device FS General registers */
11506 /* */
11507 /******************************************************************************/
11508 #define USB_CNTR (USB_BASE + 0x00000040U) /*!< Control register */
11509 #define USB_ISTR (USB_BASE + 0x00000044U) /*!< Interrupt status register */
11510 #define USB_FNR (USB_BASE + 0x00000048U) /*!< Frame number register */
11511 #define USB_DADDR (USB_BASE + 0x0000004CU) /*!< Device address register */
11512 #define USB_BTABLE (USB_BASE + 0x00000050U) /*!< Buffer Table address register */
11513 #define USB_LPMCSR (USB_BASE + 0x00000054U) /*!< LPM Control and Status register */
11514 #define USB_BCDR (USB_BASE + 0x00000058U) /*!< Battery Charging detector register*/
11515
11516 /****************** Bits definition for USB_CNTR register *******************/
11517 #define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
11518 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
11519 #define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
11520 #define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
11521 #define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
11522 #define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
11523 #define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
11524 #define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
11525 #define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */
11526 #define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */
11527 #define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
11528 #define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
11529 #define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
11530 #define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
11531 #define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
11532
11533 /****************** Bits definition for USB_ISTR register *******************/
11534 #define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
11535 #define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
11536 #define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */
11537 #define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
11538 #define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
11539 #define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
11540 #define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
11541 #define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
11542 #define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
11543 #define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
11544 #define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
11545
11546 #define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
11547 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
11548 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
11549 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
11550 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
11551 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
11552 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
11553 #define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
11554 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
11555
11556 /****************** Bits definition for USB_FNR register ********************/
11557 #define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
11558 #define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
11559 #define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
11560 #define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
11561 #define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
11562
11563 /****************** Bits definition for USB_DADDR register ****************/
11564 #define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< ADD[6:0] bits (Device Address) */
11565 #define USB_DADDR_ADD0 ((uint8_t)0x01U) /*!< Bit 0 */
11566 #define USB_DADDR_ADD1 ((uint8_t)0x02U) /*!< Bit 1 */
11567 #define USB_DADDR_ADD2 ((uint8_t)0x04U) /*!< Bit 2 */
11568 #define USB_DADDR_ADD3 ((uint8_t)0x08U) /*!< Bit 3 */
11569 #define USB_DADDR_ADD4 ((uint8_t)0x10U) /*!< Bit 4 */
11570 #define USB_DADDR_ADD5 ((uint8_t)0x20U) /*!< Bit 5 */
11571 #define USB_DADDR_ADD6 ((uint8_t)0x40U) /*!< Bit 6 */
11572
11573 #define USB_DADDR_EF ((uint8_t)0x80U) /*!< Enable Function */
11574
11575 /****************** Bit definition for USB_BTABLE register ******************/
11576 #define USB_BTABLE_BTABLE ((uint16_t)0xFFF8U) /*!< Buffer Table */
11577
11578 /****************** Bits definition for USB_BCDR register *******************/
11579 #define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */
11580 #define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */
11581 #define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */
11582 #define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */
11583 #define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */
11584 #define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */
11585 #define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */
11586 #define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */
11587 #define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */
11588
11589 /******************* Bit definition for LPMCSR register *********************/
11590 #define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */
11591 #define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/
11592 #define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */
11593 #define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */
11594
11595 /*!< Buffer descriptor table */
11596 /***************** Bit definition for USB_ADDR0_TX register *****************/
11597 #define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
11598 #define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos)/*!< 0x0000FFFE */
11599 #define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */
11600
11601 /***************** Bit definition for USB_ADDR1_TX register *****************/
11602 #define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
11603 #define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos)/*!< 0x0000FFFE */
11604 #define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */
11605
11606 /***************** Bit definition for USB_ADDR2_TX register *****************/
11607 #define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
11608 #define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos)/*!< 0x0000FFFE */
11609 #define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */
11610
11611 /***************** Bit definition for USB_ADDR3_TX register *****************/
11612 #define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
11613 #define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos)/*!< 0x0000FFFE */
11614 #define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */
11615
11616 /***************** Bit definition for USB_ADDR4_TX register *****************/
11617 #define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
11618 #define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos)/*!< 0x0000FFFE */
11619 #define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */
11620
11621 /***************** Bit definition for USB_ADDR5_TX register *****************/
11622 #define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
11623 #define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos)/*!< 0x0000FFFE */
11624 #define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */
11625
11626 /***************** Bit definition for USB_ADDR6_TX register *****************/
11627 #define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
11628 #define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos)/*!< 0x0000FFFE */
11629 #define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */
11630
11631 /***************** Bit definition for USB_ADDR7_TX register *****************/
11632 #define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
11633 #define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos)/*!< 0x0000FFFE */
11634 #define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */
11635
11636 /*----------------------------------------------------------------------------*/
11637
11638 /***************** Bit definition for USB_COUNT0_TX register ****************/
11639 #define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
11640 #define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos)/*!< 0x000003FF */
11641 #define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */
11642
11643 /***************** Bit definition for USB_COUNT1_TX register ****************/
11644 #define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
11645 #define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos)/*!< 0x000003FF */
11646 #define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */
11647
11648 /***************** Bit definition for USB_COUNT2_TX register ****************/
11649 #define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
11650 #define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos)/*!< 0x000003FF */
11651 #define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */
11652
11653 /***************** Bit definition for USB_COUNT3_TX register ****************/
11654 #define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
11655 #define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos)/*!< 0x000003FF */
11656 #define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */
11657
11658 /***************** Bit definition for USB_COUNT4_TX register ****************/
11659 #define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
11660 #define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos)/*!< 0x000003FF */
11661 #define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */
11662
11663 /***************** Bit definition for USB_COUNT5_TX register ****************/
11664 #define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
11665 #define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos)/*!< 0x000003FF */
11666 #define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */
11667
11668 /***************** Bit definition for USB_COUNT6_TX register ****************/
11669 #define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
11670 #define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos)/*!< 0x000003FF */
11671 #define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */
11672
11673 /***************** Bit definition for USB_COUNT7_TX register ****************/
11674 #define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
11675 #define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos)/*!< 0x000003FF */
11676 #define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */
11677
11678 /*----------------------------------------------------------------------------*/
11679
11680 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/
11681 #define USB_COUNT0_TX_0_COUNT0_TX_0 (0x000003FFU) /*!< Transmission Byte Count 0 (low) */
11682
11683 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/
11684 #define USB_COUNT0_TX_1_COUNT0_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 0 (high) */
11685
11686 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/
11687 #define USB_COUNT1_TX_0_COUNT1_TX_0 (0x000003FFU) /*!< Transmission Byte Count 1 (low) */
11688
11689 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/
11690 #define USB_COUNT1_TX_1_COUNT1_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 1 (high) */
11691
11692 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/
11693 #define USB_COUNT2_TX_0_COUNT2_TX_0 (0x000003FFU) /*!< Transmission Byte Count 2 (low) */
11694
11695 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/
11696 #define USB_COUNT2_TX_1_COUNT2_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 2 (high) */
11697
11698 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/
11699 #define USB_COUNT3_TX_0_COUNT3_TX_0 (0x000003FFU) /*!< Transmission Byte Count 3 (low) */
11700
11701 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/
11702 #define USB_COUNT3_TX_1_COUNT3_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 3 (high) */
11703
11704 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/
11705 #define USB_COUNT4_TX_0_COUNT4_TX_0 (0x000003FFU) /*!< Transmission Byte Count 4 (low) */
11706
11707 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/
11708 #define USB_COUNT4_TX_1_COUNT4_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 4 (high) */
11709
11710 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/
11711 #define USB_COUNT5_TX_0_COUNT5_TX_0 (0x000003FFU) /*!< Transmission Byte Count 5 (low) */
11712
11713 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/
11714 #define USB_COUNT5_TX_1_COUNT5_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 5 (high) */
11715
11716 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/
11717 #define USB_COUNT6_TX_0_COUNT6_TX_0 (0x000003FFU) /*!< Transmission Byte Count 6 (low) */
11718
11719 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/
11720 #define USB_COUNT6_TX_1_COUNT6_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 6 (high) */
11721
11722 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/
11723 #define USB_COUNT7_TX_0_COUNT7_TX_0 (0x000003FFU) /*!< Transmission Byte Count 7 (low) */
11724
11725 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/
11726 #define USB_COUNT7_TX_1_COUNT7_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 7 (high) */
11727
11728 /*----------------------------------------------------------------------------*/
11729
11730 /***************** Bit definition for USB_ADDR0_RX register *****************/
11731 #define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
11732 #define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos)/*!< 0x0000FFFE */
11733 #define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */
11734
11735 /***************** Bit definition for USB_ADDR1_RX register *****************/
11736 #define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
11737 #define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos)/*!< 0x0000FFFE */
11738 #define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */
11739
11740 /***************** Bit definition for USB_ADDR2_RX register *****************/
11741 #define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
11742 #define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos)/*!< 0x0000FFFE */
11743 #define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */
11744
11745 /***************** Bit definition for USB_ADDR3_RX register *****************/
11746 #define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
11747 #define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos)/*!< 0x0000FFFE */
11748 #define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */
11749
11750 /***************** Bit definition for USB_ADDR4_RX register *****************/
11751 #define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
11752 #define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos)/*!< 0x0000FFFE */
11753 #define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */
11754
11755 /***************** Bit definition for USB_ADDR5_RX register *****************/
11756 #define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
11757 #define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos)/*!< 0x0000FFFE */
11758 #define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */
11759
11760 /***************** Bit definition for USB_ADDR6_RX register *****************/
11761 #define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
11762 #define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos)/*!< 0x0000FFFE */
11763 #define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */
11764
11765 /***************** Bit definition for USB_ADDR7_RX register *****************/
11766 #define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
11767 #define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos)/*!< 0x0000FFFE */
11768 #define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */
11769
11770 /*----------------------------------------------------------------------------*/
11771
11772 /***************** Bit definition for USB_COUNT0_RX register ****************/
11773 #define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
11774 #define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos)/*!< 0x000003FF */
11775 #define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */
11776
11777 #define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
11778 #define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
11779 #define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
11780 #define USB_COUNT0_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
11781 #define USB_COUNT0_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
11782 #define USB_COUNT0_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
11783 #define USB_COUNT0_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
11784 #define USB_COUNT0_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
11785
11786 #define USB_COUNT0_RX_BLSIZE_Pos (15U)
11787 #define USB_COUNT0_RX_BLSIZE_Msk (0x1UL << USB_COUNT0_RX_BLSIZE_Pos)/*!< 0x00008000 */
11788 #define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */
11789
11790 /***************** Bit definition for USB_COUNT1_RX register ****************/
11791 #define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
11792 #define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos)/*!< 0x000003FF */
11793 #define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */
11794
11795 #define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
11796 #define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
11797 #define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
11798 #define USB_COUNT1_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
11799 #define USB_COUNT1_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
11800 #define USB_COUNT1_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
11801 #define USB_COUNT1_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
11802 #define USB_COUNT1_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
11803
11804 #define USB_COUNT1_RX_BLSIZE_Pos (15U)
11805 #define USB_COUNT1_RX_BLSIZE_Msk (0x1UL << USB_COUNT1_RX_BLSIZE_Pos)/*!< 0x00008000 */
11806 #define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */
11807
11808 /***************** Bit definition for USB_COUNT2_RX register ****************/
11809 #define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
11810 #define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos)/*!< 0x000003FF */
11811 #define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */
11812
11813 #define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
11814 #define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
11815 #define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
11816 #define USB_COUNT2_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
11817 #define USB_COUNT2_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
11818 #define USB_COUNT2_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
11819 #define USB_COUNT2_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
11820 #define USB_COUNT2_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
11821
11822 #define USB_COUNT2_RX_BLSIZE_Pos (15U)
11823 #define USB_COUNT2_RX_BLSIZE_Msk (0x1UL << USB_COUNT2_RX_BLSIZE_Pos)/*!< 0x00008000 */
11824 #define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */
11825
11826 /***************** Bit definition for USB_COUNT3_RX register ****************/
11827 #define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
11828 #define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos)/*!< 0x000003FF */
11829 #define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */
11830
11831 #define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
11832 #define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
11833 #define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
11834 #define USB_COUNT3_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
11835 #define USB_COUNT3_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
11836 #define USB_COUNT3_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
11837 #define USB_COUNT3_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
11838 #define USB_COUNT3_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
11839
11840 #define USB_COUNT3_RX_BLSIZE_Pos (15U)
11841 #define USB_COUNT3_RX_BLSIZE_Msk (0x1UL << USB_COUNT3_RX_BLSIZE_Pos)/*!< 0x00008000 */
11842 #define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */
11843
11844 /***************** Bit definition for USB_COUNT4_RX register ****************/
11845 #define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
11846 #define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos)/*!< 0x000003FF */
11847 #define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */
11848
11849 #define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
11850 #define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
11851 #define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
11852 #define USB_COUNT4_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
11853 #define USB_COUNT4_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
11854 #define USB_COUNT4_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
11855 #define USB_COUNT4_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
11856 #define USB_COUNT4_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
11857
11858 #define USB_COUNT4_RX_BLSIZE_Pos (15U)
11859 #define USB_COUNT4_RX_BLSIZE_Msk (0x1UL << USB_COUNT4_RX_BLSIZE_Pos)/*!< 0x00008000 */
11860 #define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */
11861
11862 /***************** Bit definition for USB_COUNT5_RX register ****************/
11863 #define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
11864 #define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos)/*!< 0x000003FF */
11865 #define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */
11866
11867 #define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
11868 #define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
11869 #define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
11870 #define USB_COUNT5_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
11871 #define USB_COUNT5_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
11872 #define USB_COUNT5_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
11873 #define USB_COUNT5_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
11874 #define USB_COUNT5_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
11875
11876 #define USB_COUNT5_RX_BLSIZE_Pos (15U)
11877 #define USB_COUNT5_RX_BLSIZE_Msk (0x1UL << USB_COUNT5_RX_BLSIZE_Pos)/*!< 0x00008000 */
11878 #define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */
11879
11880 /***************** Bit definition for USB_COUNT6_RX register ****************/
11881 #define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
11882 #define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos)/*!< 0x000003FF */
11883 #define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */
11884
11885 #define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
11886 #define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
11887 #define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
11888 #define USB_COUNT6_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
11889 #define USB_COUNT6_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
11890 #define USB_COUNT6_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
11891 #define USB_COUNT6_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
11892 #define USB_COUNT6_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
11893
11894 #define USB_COUNT6_RX_BLSIZE_Pos (15U)
11895 #define USB_COUNT6_RX_BLSIZE_Msk (0x1UL << USB_COUNT6_RX_BLSIZE_Pos)/*!< 0x00008000 */
11896 #define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */
11897
11898 /***************** Bit definition for USB_COUNT7_RX register ****************/
11899 #define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
11900 #define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos)/*!< 0x000003FF */
11901 #define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */
11902
11903 #define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
11904 #define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
11905 #define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
11906 #define USB_COUNT7_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
11907 #define USB_COUNT7_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
11908 #define USB_COUNT7_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
11909 #define USB_COUNT7_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
11910 #define USB_COUNT7_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
11911
11912 #define USB_COUNT7_RX_BLSIZE_Pos (15U)
11913 #define USB_COUNT7_RX_BLSIZE_Msk (0x1UL << USB_COUNT7_RX_BLSIZE_Pos)/*!< 0x00008000 */
11914 #define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */
11915
11916 /*----------------------------------------------------------------------------*/
11917
11918 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/
11919 #define USB_COUNT0_RX_0_COUNT0_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
11920
11921 #define USB_COUNT0_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
11922 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
11923 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
11924 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
11925 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
11926 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
11927
11928 #define USB_COUNT0_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
11929
11930 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/
11931 #define USB_COUNT0_RX_1_COUNT0_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
11932
11933 #define USB_COUNT0_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
11934 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 1 */
11935 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
11936 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
11937 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
11938 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
11939
11940 #define USB_COUNT0_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
11941
11942 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/
11943 #define USB_COUNT1_RX_0_COUNT1_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
11944
11945 #define USB_COUNT1_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
11946 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
11947 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
11948 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
11949 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
11950 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
11951
11952 #define USB_COUNT1_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
11953
11954 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/
11955 #define USB_COUNT1_RX_1_COUNT1_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
11956
11957 #define USB_COUNT1_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
11958 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
11959 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
11960 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
11961 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
11962 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
11963
11964 #define USB_COUNT1_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
11965
11966 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/
11967 #define USB_COUNT2_RX_0_COUNT2_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
11968
11969 #define USB_COUNT2_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
11970 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
11971 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
11972 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
11973 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
11974 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
11975
11976 #define USB_COUNT2_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
11977
11978 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/
11979 #define USB_COUNT2_RX_1_COUNT2_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
11980
11981 #define USB_COUNT2_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
11982 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
11983 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
11984 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
11985 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
11986 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
11987
11988 #define USB_COUNT2_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
11989
11990 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/
11991 #define USB_COUNT3_RX_0_COUNT3_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
11992
11993 #define USB_COUNT3_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
11994 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
11995 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
11996 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
11997 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
11998 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
11999
12000 #define USB_COUNT3_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
12001
12002 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/
12003 #define USB_COUNT3_RX_1_COUNT3_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
12004
12005 #define USB_COUNT3_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
12006 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
12007 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
12008 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
12009 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
12010 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
12011
12012 #define USB_COUNT3_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
12013
12014 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/
12015 #define USB_COUNT4_RX_0_COUNT4_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
12016
12017 #define USB_COUNT4_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
12018 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
12019 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
12020 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
12021 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
12022 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
12023
12024 #define USB_COUNT4_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
12025
12026 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/
12027 #define USB_COUNT4_RX_1_COUNT4_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
12028
12029 #define USB_COUNT4_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
12030 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
12031 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
12032 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
12033 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
12034 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
12035
12036 #define USB_COUNT4_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
12037
12038 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/
12039 #define USB_COUNT5_RX_0_COUNT5_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
12040
12041 #define USB_COUNT5_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
12042 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
12043 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
12044 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
12045 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
12046 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
12047
12048 #define USB_COUNT5_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
12049
12050 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/
12051 #define USB_COUNT5_RX_1_COUNT5_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
12052
12053 #define USB_COUNT5_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
12054 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
12055 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
12056 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
12057 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
12058 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
12059
12060 #define USB_COUNT5_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
12061
12062 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/
12063 #define USB_COUNT6_RX_0_COUNT6_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
12064
12065 #define USB_COUNT6_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
12066 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
12067 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
12068 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
12069 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
12070 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
12071
12072 #define USB_COUNT6_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
12073
12074 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/
12075 #define USB_COUNT6_RX_1_COUNT6_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
12076
12077 #define USB_COUNT6_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
12078 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
12079 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
12080 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
12081 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
12082 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
12083
12084 #define USB_COUNT6_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
12085
12086 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/
12087 #define USB_COUNT7_RX_0_COUNT7_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
12088
12089 #define USB_COUNT7_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
12090 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
12091 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
12092 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
12093 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
12094 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
12095
12096 #define USB_COUNT7_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
12097
12098 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/
12099 #define USB_COUNT7_RX_1_COUNT7_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
12100
12101 #define USB_COUNT7_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
12102 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
12103 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
12104 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
12105 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
12106 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
12107
12108 #define USB_COUNT7_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
12109
12110 /******************************************************************************/
12111 /* */
12112 /* UCPD */
12113 /* */
12114 /******************************************************************************/
12115 /******************** Bits definition for UCPD_CFG1 register *******************/
12116 #define UCPD_CFG1_HBITCLKDIV_Pos (0U)
12117 #define UCPD_CFG1_HBITCLKDIV_Msk (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x0000003F */
12118 #define UCPD_CFG1_HBITCLKDIV UCPD_CFG1_HBITCLKDIV_Msk /*!< Number of cycles (minus 1) for a half bit clock */
12119 #define UCPD_CFG1_HBITCLKDIV_0 (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000001 */
12120 #define UCPD_CFG1_HBITCLKDIV_1 (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000002 */
12121 #define UCPD_CFG1_HBITCLKDIV_2 (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000004 */
12122 #define UCPD_CFG1_HBITCLKDIV_3 (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000008 */
12123 #define UCPD_CFG1_HBITCLKDIV_4 (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000010 */
12124 #define UCPD_CFG1_HBITCLKDIV_5 (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000020 */
12125 #define UCPD_CFG1_IFRGAP_Pos (6U)
12126 #define UCPD_CFG1_IFRGAP_Msk (0x1FUL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x000007C0 */
12127 #define UCPD_CFG1_IFRGAP UCPD_CFG1_IFRGAP_Msk /*!< Clock divider value to generates Interframe gap */
12128 #define UCPD_CFG1_IFRGAP_0 (0x01UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000040 */
12129 #define UCPD_CFG1_IFRGAP_1 (0x02UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000080 */
12130 #define UCPD_CFG1_IFRGAP_2 (0x04UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000100 */
12131 #define UCPD_CFG1_IFRGAP_3 (0x08UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000200 */
12132 #define UCPD_CFG1_IFRGAP_4 (0x10UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000400 */
12133 #define UCPD_CFG1_TRANSWIN_Pos (11U)
12134 #define UCPD_CFG1_TRANSWIN_Msk (0x1FUL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x0000F800 */
12135 #define UCPD_CFG1_TRANSWIN UCPD_CFG1_TRANSWIN_Msk /*!< Number of cycles (minus 1) of the half bit clock */
12136 #define UCPD_CFG1_TRANSWIN_0 (0x01UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00000800 */
12137 #define UCPD_CFG1_TRANSWIN_1 (0x02UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00001000 */
12138 #define UCPD_CFG1_TRANSWIN_2 (0x04UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00002000 */
12139 #define UCPD_CFG1_TRANSWIN_3 (0x08UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00004000 */
12140 #define UCPD_CFG1_TRANSWIN_4 (0x10UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00008000 */
12141 #define UCPD_CFG1_PSC_UCPDCLK_Pos (17U)
12142 #define UCPD_CFG1_PSC_UCPDCLK_Msk (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x000E0000 */
12143 #define UCPD_CFG1_PSC_UCPDCLK UCPD_CFG1_PSC_UCPDCLK_Msk /*!< Prescaler for UCPDCLK */
12144 #define UCPD_CFG1_PSC_UCPDCLK_0 (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00020000 */
12145 #define UCPD_CFG1_PSC_UCPDCLK_1 (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00040000 */
12146 #define UCPD_CFG1_PSC_UCPDCLK_2 (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00080000 */
12147 #define UCPD_CFG1_RXORDSETEN_Pos (20U)
12148 #define UCPD_CFG1_RXORDSETEN_Msk (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x1FF00000 */
12149 #define UCPD_CFG1_RXORDSETEN UCPD_CFG1_RXORDSETEN_Msk /*!< Receiver ordered set detection enable */
12150 #define UCPD_CFG1_RXORDSETEN_0 (0x001UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00100000 */
12151 #define UCPD_CFG1_RXORDSETEN_1 (0x002UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00200000 */
12152 #define UCPD_CFG1_RXORDSETEN_2 (0x004UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00400000 */
12153 #define UCPD_CFG1_RXORDSETEN_3 (0x008UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00800000 */
12154 #define UCPD_CFG1_RXORDSETEN_4 (0x010UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x01000000 */
12155 #define UCPD_CFG1_RXORDSETEN_5 (0x020UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x02000000 */
12156 #define UCPD_CFG1_RXORDSETEN_6 (0x040UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x04000000 */
12157 #define UCPD_CFG1_RXORDSETEN_7 (0x080UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x08000000 */
12158 #define UCPD_CFG1_RXORDSETEN_8 (0x100UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x10000000 */
12159 #define UCPD_CFG1_TXDMAEN_Pos (29U)
12160 #define UCPD_CFG1_TXDMAEN_Msk (0x1UL << UCPD_CFG1_TXDMAEN_Pos) /*!< 0x20000000 */
12161 #define UCPD_CFG1_TXDMAEN UCPD_CFG1_TXDMAEN_Msk /*!< DMA transmission requests enable */
12162 #define UCPD_CFG1_RXDMAEN_Pos (30U)
12163 #define UCPD_CFG1_RXDMAEN_Msk (0x1UL << UCPD_CFG1_RXDMAEN_Pos) /*!< 0x40000000 */
12164 #define UCPD_CFG1_RXDMAEN UCPD_CFG1_RXDMAEN_Msk /*!< DMA reception requests enable */
12165 #define UCPD_CFG1_UCPDEN_Pos (31U)
12166 #define UCPD_CFG1_UCPDEN_Msk (0x1UL << UCPD_CFG1_UCPDEN_Pos) /*!< 0x80000000 */
12167 #define UCPD_CFG1_UCPDEN UCPD_CFG1_UCPDEN_Msk /*!< USB Power Delivery Block Enable */
12168
12169 /******************** Bits definition for UCPD_CFG2 register *******************/
12170 #define UCPD_CFG2_RXFILTDIS_Pos (0U)
12171 #define UCPD_CFG2_RXFILTDIS_Msk (0x1UL << UCPD_CFG2_RXFILTDIS_Pos) /*!< 0x00000001 */
12172 #define UCPD_CFG2_RXFILTDIS UCPD_CFG2_RXFILTDIS_Msk /*!< Enables an Rx pre-filter for the BMC decoder */
12173 #define UCPD_CFG2_RXFILT2N3_Pos (1U)
12174 #define UCPD_CFG2_RXFILT2N3_Msk (0x1UL << UCPD_CFG2_RXFILT2N3_Pos) /*!< 0x00000002 */
12175 #define UCPD_CFG2_RXFILT2N3 UCPD_CFG2_RXFILT2N3_Msk /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */
12176 #define UCPD_CFG2_FORCECLK_Pos (2U)
12177 #define UCPD_CFG2_FORCECLK_Msk (0x1UL << UCPD_CFG2_FORCECLK_Pos) /*!< 0x00000004 */
12178 #define UCPD_CFG2_FORCECLK UCPD_CFG2_FORCECLK_Msk /*!< Controls forcing of the clock request UCPDCLK_REQ */
12179 #define UCPD_CFG2_WUPEN_Pos (3U)
12180 #define UCPD_CFG2_WUPEN_Msk (0x1UL << UCPD_CFG2_WUPEN_Pos) /*!< 0x00000008 */
12181 #define UCPD_CFG2_WUPEN UCPD_CFG2_WUPEN_Msk /*!< Wakeup from STOP enable */
12182
12183 /******************** Bits definition for UCPD_CR register ********************/
12184 #define UCPD_CR_TXMODE_Pos (0U)
12185 #define UCPD_CR_TXMODE_Msk (0x3UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000003 */
12186 #define UCPD_CR_TXMODE UCPD_CR_TXMODE_Msk /*!< Type of Tx packet */
12187 #define UCPD_CR_TXMODE_0 (0x1UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000001 */
12188 #define UCPD_CR_TXMODE_1 (0x2UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000002 */
12189 #define UCPD_CR_TXSEND_Pos (2U)
12190 #define UCPD_CR_TXSEND_Msk (0x1UL << UCPD_CR_TXSEND_Pos) /*!< 0x00000004 */
12191 #define UCPD_CR_TXSEND UCPD_CR_TXSEND_Msk /*!< Type of Tx packet */
12192 #define UCPD_CR_TXHRST_Pos (3U)
12193 #define UCPD_CR_TXHRST_Msk (0x1UL << UCPD_CR_TXHRST_Pos) /*!< 0x00000008 */
12194 #define UCPD_CR_TXHRST UCPD_CR_TXHRST_Msk /*!< Command to send a Tx Hard Reset */
12195 #define UCPD_CR_RXMODE_Pos (4U)
12196 #define UCPD_CR_RXMODE_Msk (0x1UL << UCPD_CR_RXMODE_Pos) /*!< 0x00000010 */
12197 #define UCPD_CR_RXMODE UCPD_CR_RXMODE_Msk /*!< Receiver mode */
12198 #define UCPD_CR_PHYRXEN_Pos (5U)
12199 #define UCPD_CR_PHYRXEN_Msk (0x1UL << UCPD_CR_PHYRXEN_Pos) /*!< 0x00000020 */
12200 #define UCPD_CR_PHYRXEN UCPD_CR_PHYRXEN_Msk /*!< Controls enable of USB Power Delivery receiver */
12201 #define UCPD_CR_PHYCCSEL_Pos (6U)
12202 #define UCPD_CR_PHYCCSEL_Msk (0x1UL << UCPD_CR_PHYCCSEL_Pos) /*!< 0x00000040 */
12203 #define UCPD_CR_PHYCCSEL UCPD_CR_PHYCCSEL_Msk /*!< */
12204 #define UCPD_CR_ANASUBMODE_Pos (7U)
12205 #define UCPD_CR_ANASUBMODE_Msk (0x3UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000180 */
12206 #define UCPD_CR_ANASUBMODE UCPD_CR_ANASUBMODE_Msk /*!< Analog PHY sub-mode */
12207 #define UCPD_CR_ANASUBMODE_0 (0x1UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000080 */
12208 #define UCPD_CR_ANASUBMODE_1 (0x2UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000100 */
12209 #define UCPD_CR_ANAMODE_Pos (9U)
12210 #define UCPD_CR_ANAMODE_Msk (0x1UL << UCPD_CR_ANAMODE_Pos) /*!< 0x00000200 */
12211 #define UCPD_CR_ANAMODE UCPD_CR_ANAMODE_Msk /*!< Analog PHY working mode */
12212 #define UCPD_CR_CCENABLE_Pos (10U)
12213 #define UCPD_CR_CCENABLE_Msk (0x3UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000C00 */
12214 #define UCPD_CR_CCENABLE UCPD_CR_CCENABLE_Msk /*!< */
12215 #define UCPD_CR_CCENABLE_0 (0x1UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000400 */
12216 #define UCPD_CR_CCENABLE_1 (0x2UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000800 */
12217 #define UCPD_CR_FRSRXEN_Pos (16U)
12218 #define UCPD_CR_FRSRXEN_Msk (0x1UL << UCPD_CR_FRSRXEN_Pos) /*!< 0x00010000 */
12219 #define UCPD_CR_FRSRXEN UCPD_CR_FRSRXEN_Msk /*!< Enable FRS request detection function */
12220 #define UCPD_CR_FRSTX_Pos (17U)
12221 #define UCPD_CR_FRSTX_Msk (0x1UL << UCPD_CR_FRSTX_Pos) /*!< 0x00020000 */
12222 #define UCPD_CR_FRSTX UCPD_CR_FRSTX_Msk /*!< Signal Fast Role Swap request */
12223 #define UCPD_CR_RDCH_Pos (18U)
12224 #define UCPD_CR_RDCH_Msk (0x1UL << UCPD_CR_RDCH_Pos) /*!< 0x00040000 */
12225 #define UCPD_CR_RDCH UCPD_CR_RDCH_Msk /*!< */
12226 #define UCPD_CR_CC1TCDIS_Pos (20U)
12227 #define UCPD_CR_CC1TCDIS_Msk (0x1UL << UCPD_CR_CC1TCDIS_Pos) /*!< 0x00100000 */
12228 #define UCPD_CR_CC1TCDIS UCPD_CR_CC1TCDIS_Msk /*!< The bit allows the Type-C detector for CC0 to be disabled. */
12229 #define UCPD_CR_CC2TCDIS_Pos (21U)
12230 #define UCPD_CR_CC2TCDIS_Msk (0x1UL << UCPD_CR_CC2TCDIS_Pos) /*!< 0x00200000 */
12231 #define UCPD_CR_CC2TCDIS UCPD_CR_CC2TCDIS_Msk /*!< The bit allows the Type-C detector for CC2 to be disabled. */
12232
12233 /******************** Bits definition for UCPD_IMR register *******************/
12234 #define UCPD_IMR_TXISIE_Pos (0U)
12235 #define UCPD_IMR_TXISIE_Msk (0x1UL << UCPD_IMR_TXISIE_Pos) /*!< 0x00000001 */
12236 #define UCPD_IMR_TXISIE UCPD_IMR_TXISIE_Msk /*!< Enable TXIS interrupt */
12237 #define UCPD_IMR_TXMSGDISCIE_Pos (1U)
12238 #define UCPD_IMR_TXMSGDISCIE_Msk (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos) /*!< 0x00000002 */
12239 #define UCPD_IMR_TXMSGDISCIE UCPD_IMR_TXMSGDISCIE_Msk /*!< Enable TXMSGDISC interrupt */
12240 #define UCPD_IMR_TXMSGSENTIE_Pos (2U)
12241 #define UCPD_IMR_TXMSGSENTIE_Msk (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos) /*!< 0x00000004 */
12242 #define UCPD_IMR_TXMSGSENTIE UCPD_IMR_TXMSGSENTIE_Msk /*!< Enable TXMSGSENT interrupt */
12243 #define UCPD_IMR_TXMSGABTIE_Pos (3U)
12244 #define UCPD_IMR_TXMSGABTIE_Msk (0x1UL << UCPD_IMR_TXMSGABTIE_Pos) /*!< 0x00000008 */
12245 #define UCPD_IMR_TXMSGABTIE UCPD_IMR_TXMSGABTIE_Msk /*!< Enable TXMSGABT interrupt */
12246 #define UCPD_IMR_HRSTDISCIE_Pos (4U)
12247 #define UCPD_IMR_HRSTDISCIE_Msk (0x1UL << UCPD_IMR_HRSTDISCIE_Pos) /*!< 0x00000010 */
12248 #define UCPD_IMR_HRSTDISCIE UCPD_IMR_HRSTDISCIE_Msk /*!< Enable HRSTDISC interrupt */
12249 #define UCPD_IMR_HRSTSENTIE_Pos (5U)
12250 #define UCPD_IMR_HRSTSENTIE_Msk (0x1UL << UCPD_IMR_HRSTSENTIE_Pos) /*!< 0x00000020 */
12251 #define UCPD_IMR_HRSTSENTIE UCPD_IMR_HRSTSENTIE_Msk /*!< Enable HRSTSENT interrupt */
12252 #define UCPD_IMR_TXUNDIE_Pos (6U)
12253 #define UCPD_IMR_TXUNDIE_Msk (0x1UL << UCPD_IMR_TXUNDIE_Pos) /*!< 0x00000040 */
12254 #define UCPD_IMR_TXUNDIE UCPD_IMR_TXUNDIE_Msk /*!< Enable TXUND interrupt */
12255 #define UCPD_IMR_RXNEIE_Pos (8U)
12256 #define UCPD_IMR_RXNEIE_Msk (0x1UL << UCPD_IMR_RXNEIE_Pos) /*!< 0x00000100 */
12257 #define UCPD_IMR_RXNEIE UCPD_IMR_RXNEIE_Msk /*!< Enable RXNE interrupt */
12258 #define UCPD_IMR_RXORDDETIE_Pos (9U)
12259 #define UCPD_IMR_RXORDDETIE_Msk (0x1UL << UCPD_IMR_RXORDDETIE_Pos) /*!< 0x00000200 */
12260 #define UCPD_IMR_RXORDDETIE UCPD_IMR_RXORDDETIE_Msk /*!< Enable RXORDDET interrupt */
12261 #define UCPD_IMR_RXHRSTDETIE_Pos (10U)
12262 #define UCPD_IMR_RXHRSTDETIE_Msk (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos) /*!< 0x00000400 */
12263 #define UCPD_IMR_RXHRSTDETIE UCPD_IMR_RXHRSTDETIE_Msk /*!< Enable RXHRSTDET interrupt */
12264 #define UCPD_IMR_RXOVRIE_Pos (11U)
12265 #define UCPD_IMR_RXOVRIE_Msk (0x1UL << UCPD_IMR_RXOVRIE_Pos) /*!< 0x00000800 */
12266 #define UCPD_IMR_RXOVRIE UCPD_IMR_RXOVRIE_Msk /*!< Enable RXOVR interrupt */
12267 #define UCPD_IMR_RXMSGENDIE_Pos (12U)
12268 #define UCPD_IMR_RXMSGENDIE_Msk (0x1UL << UCPD_IMR_RXMSGENDIE_Pos) /*!< 0x00001000 */
12269 #define UCPD_IMR_RXMSGENDIE UCPD_IMR_RXMSGENDIE_Msk /*!< Enable RXMSGEND interrupt */
12270 #define UCPD_IMR_TYPECEVT1IE_Pos (14U)
12271 #define UCPD_IMR_TYPECEVT1IE_Msk (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos) /*!< 0x00004000 */
12272 #define UCPD_IMR_TYPECEVT1IE UCPD_IMR_TYPECEVT1IE_Msk /*!< Enable TYPECEVT1IE interrupt */
12273 #define UCPD_IMR_TYPECEVT2IE_Pos (15U)
12274 #define UCPD_IMR_TYPECEVT2IE_Msk (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos) /*!< 0x00008000 */
12275 #define UCPD_IMR_TYPECEVT2IE UCPD_IMR_TYPECEVT2IE_Msk /*!< Enable TYPECEVT2IE interrupt */
12276 #define UCPD_IMR_FRSEVTIE_Pos (20U)
12277 #define UCPD_IMR_FRSEVTIE_Msk (0x1UL << UCPD_IMR_FRSEVTIE_Pos) /*!< 0x00100000 */
12278 #define UCPD_IMR_FRSEVTIE UCPD_IMR_FRSEVTIE_Msk /*!< Fast Role Swap interrupt */
12279
12280 /******************** Bits definition for UCPD_SR register ********************/
12281 #define UCPD_SR_TXIS_Pos (0U)
12282 #define UCPD_SR_TXIS_Msk (0x1UL << UCPD_SR_TXIS_Pos) /*!< 0x00000001 */
12283 #define UCPD_SR_TXIS UCPD_SR_TXIS_Msk /*!< Transmit interrupt status */
12284 #define UCPD_SR_TXMSGDISC_Pos (1U)
12285 #define UCPD_SR_TXMSGDISC_Msk (0x1UL << UCPD_SR_TXMSGDISC_Pos) /*!< 0x00000002 */
12286 #define UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC_Msk /*!< Transmit message discarded interrupt */
12287 #define UCPD_SR_TXMSGSENT_Pos (2U)
12288 #define UCPD_SR_TXMSGSENT_Msk (0x1UL << UCPD_SR_TXMSGSENT_Pos) /*!< 0x00000004 */
12289 #define UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT_Msk /*!< Transmit message sent interrupt */
12290 #define UCPD_SR_TXMSGABT_Pos (3U)
12291 #define UCPD_SR_TXMSGABT_Msk (0x1UL << UCPD_SR_TXMSGABT_Pos) /*!< 0x00000008 */
12292 #define UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT_Msk /*!< Transmit message abort interrupt */
12293 #define UCPD_SR_HRSTDISC_Pos (4U)
12294 #define UCPD_SR_HRSTDISC_Msk (0x1UL << UCPD_SR_HRSTDISC_Pos) /*!< 0x00000010 */
12295 #define UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC_Msk /*!< HRST discarded interrupt */
12296 #define UCPD_SR_HRSTSENT_Pos (5U)
12297 #define UCPD_SR_HRSTSENT_Msk (0x1UL << UCPD_SR_HRSTSENT_Pos) /*!< 0x00000020 */
12298 #define UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT_Msk /*!< HRST sent interrupt */
12299 #define UCPD_SR_TXUND_Pos (6U)
12300 #define UCPD_SR_TXUND_Msk (0x1UL << UCPD_SR_TXUND_Pos) /*!< 0x00000040 */
12301 #define UCPD_SR_TXUND UCPD_SR_TXUND_Msk /*!< Tx data underrun condition interrupt */
12302 #define UCPD_SR_RXNE_Pos (8U)
12303 #define UCPD_SR_RXNE_Msk (0x1UL << UCPD_SR_RXNE_Pos) /*!< 0x00000100 */
12304 #define UCPD_SR_RXNE UCPD_SR_RXNE_Msk /*!< Receive data register not empty interrupt */
12305 #define UCPD_SR_RXORDDET_Pos (9U)
12306 #define UCPD_SR_RXORDDET_Msk (0x1UL << UCPD_SR_RXORDDET_Pos) /*!< 0x00000200 */
12307 #define UCPD_SR_RXORDDET UCPD_SR_RXORDDET_Msk /*!< Rx ordered set (4 K-codes) detected interrupt */
12308 #define UCPD_SR_RXHRSTDET_Pos (10U)
12309 #define UCPD_SR_RXHRSTDET_Msk (0x1UL << UCPD_SR_RXHRSTDET_Pos) /*!< 0x00000400 */
12310 #define UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET_Msk /*!< Rx Hard Reset detect interrupt */
12311 #define UCPD_SR_RXOVR_Pos (11U)
12312 #define UCPD_SR_RXOVR_Msk (0x1UL << UCPD_SR_RXOVR_Pos) /*!< 0x00000800 */
12313 #define UCPD_SR_RXOVR UCPD_SR_RXOVR_Msk /*!< Rx data overflow interrupt */
12314 #define UCPD_SR_RXMSGEND_Pos (12U)
12315 #define UCPD_SR_RXMSGEND_Msk (0x1UL << UCPD_SR_RXMSGEND_Pos) /*!< 0x00001000 */
12316 #define UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND_Msk /*!< Rx message received */
12317 #define UCPD_SR_RXERR_Pos (13U)
12318 #define UCPD_SR_RXERR_Msk (0x1UL << UCPD_SR_RXERR_Pos) /*!< 0x00002000 */
12319 #define UCPD_SR_RXERR UCPD_SR_RXERR_Msk /*!< RX Error */
12320 #define UCPD_SR_TYPECEVT1_Pos (14U)
12321 #define UCPD_SR_TYPECEVT1_Msk (0x1UL << UCPD_SR_TYPECEVT1_Pos) /*!< 0x00004000 */
12322 #define UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1_Msk /*!< Type C voltage level event on CC1 */
12323 #define UCPD_SR_TYPECEVT2_Pos (15U)
12324 #define UCPD_SR_TYPECEVT2_Msk (0x1UL << UCPD_SR_TYPECEVT2_Pos) /*!< 0x00008000 */
12325 #define UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2_Msk /*!< Type C voltage level event on CC2 */
12326 #define UCPD_SR_TYPEC_VSTATE_CC1_Pos (16U)
12327 #define UCPD_SR_TYPEC_VSTATE_CC1_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00030000 */
12328 #define UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1_Msk /*!< Status of DC level on CC1 pin */
12329 #define UCPD_SR_TYPEC_VSTATE_CC1_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00010000 */
12330 #define UCPD_SR_TYPEC_VSTATE_CC1_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00020000 */
12331 #define UCPD_SR_TYPEC_VSTATE_CC2_Pos (18U)
12332 #define UCPD_SR_TYPEC_VSTATE_CC2_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x000C0000 */
12333 #define UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2_Msk /*!<Status of DC level on CC2 pin */
12334 #define UCPD_SR_TYPEC_VSTATE_CC2_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00040000 */
12335 #define UCPD_SR_TYPEC_VSTATE_CC2_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00080000 */
12336 #define UCPD_SR_FRSEVT_Pos (20U)
12337 #define UCPD_SR_FRSEVT_Msk (0x1UL << UCPD_SR_FRSEVT_Pos) /*!< 0x00100000 */
12338 #define UCPD_SR_FRSEVT UCPD_SR_FRSEVT_Msk /*!< Fast Role Swap detection event */
12339
12340 /******************** Bits definition for UCPD_ICR register *******************/
12341 #define UCPD_ICR_TXMSGDISCCF_Pos (1U)
12342 #define UCPD_ICR_TXMSGDISCCF_Msk (0x1UL << UCPD_ICR_TXMSGDISCCF_Pos) /*!< 0x00000002 */
12343 #define UCPD_ICR_TXMSGDISCCF UCPD_ICR_TXMSGDISCCF_Msk /*!< Tx message discarded flag (TXMSGDISC) clear */
12344 #define UCPD_ICR_TXMSGSENTCF_Pos (2U)
12345 #define UCPD_ICR_TXMSGSENTCF_Msk (0x1UL << UCPD_ICR_TXMSGSENTCF_Pos) /*!< 0x00000004 */
12346 #define UCPD_ICR_TXMSGSENTCF UCPD_ICR_TXMSGSENTCF_Msk /*!< Tx message sent flag (TXMSGSENT) clear */
12347 #define UCPD_ICR_TXMSGABTCF_Pos (3U)
12348 #define UCPD_ICR_TXMSGABTCF_Msk (0x1UL << UCPD_ICR_TXMSGABTCF_Pos) /*!< 0x00000008 */
12349 #define UCPD_ICR_TXMSGABTCF UCPD_ICR_TXMSGABTCF_Msk /*!< Tx message abort flag (TXMSGABT) clear */
12350 #define UCPD_ICR_HRSTDISCCF_Pos (4U)
12351 #define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */
12352 #define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset discarded flag (HRSTDISC) clear */
12353 #define UCPD_ICR_HRSTSENTCF_Pos (5U)
12354 #define UCPD_ICR_HRSTSENTCF_Msk (0x1UL << UCPD_ICR_HRSTSENTCF_Pos) /*!< 0x00000020 */
12355 #define UCPD_ICR_HRSTSENTCF UCPD_ICR_HRSTSENTCF_Msk /*!< Hard reset sent flag (HRSTSENT) clear */
12356 #define UCPD_ICR_TXUNDCF_Pos (6U)
12357 #define UCPD_ICR_TXUNDCF_Msk (0x1UL << UCPD_ICR_TXUNDCF_Pos) /*!< 0x00000040 */
12358 #define UCPD_ICR_TXUNDCF UCPD_ICR_TXUNDCF_Msk /*!< Tx underflow flag (TXUND) clear */
12359 #define UCPD_ICR_RXORDDETCF_Pos (9U)
12360 #define UCPD_ICR_RXORDDETCF_Msk (0x1UL << UCPD_ICR_RXORDDETCF_Pos) /*!< 0x00000200 */
12361 #define UCPD_ICR_RXORDDETCF UCPD_ICR_RXORDDETCF_Msk /*!< Rx ordered set detect flag (RXORDDET) clear */
12362 #define UCPD_ICR_RXHRSTDETCF_Pos (10U)
12363 #define UCPD_ICR_RXHRSTDETCF_Msk (0x1UL << UCPD_ICR_RXHRSTDETCF_Pos) /*!< 0x00000400 */
12364 #define UCPD_ICR_RXHRSTDETCF UCPD_ICR_RXHRSTDETCF_Msk /*!< Rx Hard Reset detected flag (RXHRSTDET) clear */
12365 #define UCPD_ICR_RXOVRCF_Pos (11U)
12366 #define UCPD_ICR_RXOVRCF_Msk (0x1UL << UCPD_ICR_RXOVRCF_Pos) /*!< 0x00000800 */
12367 #define UCPD_ICR_RXOVRCF UCPD_ICR_RXOVRCF_Msk /*!< Rx overflow flag (RXOVR) clear */
12368 #define UCPD_ICR_RXMSGENDCF_Pos (12U)
12369 #define UCPD_ICR_RXMSGENDCF_Msk (0x1UL << UCPD_ICR_RXMSGENDCF_Pos) /*!< 0x00001000 */
12370 #define UCPD_ICR_RXMSGENDCF UCPD_ICR_RXMSGENDCF_Msk /*!< Rx message received flag (RXMSGEND) clear */
12371 #define UCPD_ICR_TYPECEVT1CF_Pos (14U)
12372 #define UCPD_ICR_TYPECEVT1CF_Msk (0x1UL << UCPD_ICR_TYPECEVT1CF_Pos) /*!< 0x00004000 */
12373 #define UCPD_ICR_TYPECEVT1CF UCPD_ICR_TYPECEVT1CF_Msk /*!< TypeC event (CC1) flag (TYPECEVT1) clear */
12374 #define UCPD_ICR_TYPECEVT2CF_Pos (15U)
12375 #define UCPD_ICR_TYPECEVT2CF_Msk (0x1UL << UCPD_ICR_TYPECEVT2CF_Pos) /*!< 0x00008000 */
12376 #define UCPD_ICR_TYPECEVT2CF UCPD_ICR_TYPECEVT2CF_Msk /*!< TypeC event (CC2) flag (TYPECEVT2) clear */
12377 #define UCPD_ICR_FRSEVTCF_Pos (20U)
12378 #define UCPD_ICR_FRSEVTCF_Msk (0x1UL << UCPD_ICR_FRSEVTCF_Pos) /*!< 0x00100000 */
12379 #define UCPD_ICR_FRSEVTCF UCPD_ICR_FRSEVTCF_Msk /*!< Fast Role Swap event flag clear */
12380
12381 /******************** Bits definition for UCPD_TXORDSET register **************/
12382 #define UCPD_TX_ORDSET_TXORDSET_Pos (0U)
12383 #define UCPD_TX_ORDSET_TXORDSET_Msk (0xFFFFFUL << UCPD_TX_ORDSET_TXORDSET_Pos)/*!< 0x000FFFFF */
12384 #define UCPD_TX_ORDSET_TXORDSET UCPD_TX_ORDSET_TXORDSET_Msk /*!< Tx Ordered Set */
12385
12386 /******************** Bits definition for UCPD_TXPAYSZ register ****************/
12387 #define UCPD_TX_PAYSZ_TXPAYSZ_Pos (0U)
12388 #define UCPD_TX_PAYSZ_TXPAYSZ_Msk (0x3FFUL << UCPD_TX_PAYSZ_TXPAYSZ_Pos)/*!< 0x000003FF */
12389 #define UCPD_TX_PAYSZ_TXPAYSZ UCPD_TX_PAYSZ_TXPAYSZ_Msk /*!< Tx payload size in bytes */
12390
12391 /******************** Bits definition for UCPD_TXDR register *******************/
12392 #define UCPD_TXDR_TXDATA_Pos (0U)
12393 #define UCPD_TXDR_TXDATA_Msk (0xFFUL << UCPD_TXDR_TXDATA_Pos) /*!< 0x000000FF */
12394 #define UCPD_TXDR_TXDATA UCPD_TXDR_TXDATA_Msk /*!< Tx Data Register */
12395
12396 /******************** Bits definition for UCPD_RXORDSET register **************/
12397 #define UCPD_RX_ORDSET_RXORDSET_Pos (0U)
12398 #define UCPD_RX_ORDSET_RXORDSET_Msk (0x7UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000007 */
12399 #define UCPD_RX_ORDSET_RXORDSET UCPD_RX_ORDSET_RXORDSET_Msk /*!< Rx Ordered Set Code detected */
12400 #define UCPD_RX_ORDSET_RXORDSET_0 (0x1UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000001 */
12401 #define UCPD_RX_ORDSET_RXORDSET_1 (0x2UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000002 */
12402 #define UCPD_RX_ORDSET_RXORDSET_2 (0x4UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000004 */
12403 #define UCPD_RX_ORDSET_RXSOP3OF4_Pos (3U)
12404 #define UCPD_RX_ORDSET_RXSOP3OF4_Msk (0x1UL << UCPD_RX_ORDSET_RXSOP3OF4_Pos)/*!< 0x00000008 */
12405 #define UCPD_RX_ORDSET_RXSOP3OF4 UCPD_RX_ORDSET_RXSOP3OF4_Msk /*!< Rx Ordered Set Debug indication */
12406 #define UCPD_RX_ORDSET_RXSOPKINVALID_Pos (4U)
12407 #define UCPD_RX_ORDSET_RXSOPKINVALID_Msk (0x7UL << UCPD_RX_ORDSET_RXSOPKINVALID_Pos)/*!< 0x00000070 */
12408 #define UCPD_RX_ORDSET_RXSOPKINVALID UCPD_RX_ORDSET_RXSOPKINVALID_Msk /*!< Rx Ordered Set corrupted K-Codes (Debug) */
12409
12410 /******************** Bits definition for UCPD_RXPAYSZ register ****************/
12411 #define UCPD_RX_PAYSZ_RXPAYSZ_Pos (0U)
12412 #define UCPD_RX_PAYSZ_RXPAYSZ_Msk (0x3FFUL << UCPD_RX_PAYSZ_RXPAYSZ_Pos)/*!< 0x000003FF */
12413 #define UCPD_RX_PAYSZ_RXPAYSZ UCPD_RX_PAYSZ_RXPAYSZ_Msk /*!< Rx payload size in bytes */
12414
12415 /******************** Bits definition for UCPD_RXDR register *******************/
12416 #define UCPD_RXDR_RXDATA_Pos (0U)
12417 #define UCPD_RXDR_RXDATA_Msk (0xFFUL << UCPD_RXDR_RXDATA_Pos) /*!< 0x000000FF */
12418 #define UCPD_RXDR_RXDATA UCPD_RXDR_RXDATA_Msk /*!< 8-bit receive data */
12419
12420 /******************** Bits definition for UCPD_RXORDEXT1 register **************/
12421 #define UCPD_RX_ORDEXT1_RXSOPX1_Pos (0U)
12422 #define UCPD_RX_ORDEXT1_RXSOPX1_Msk (0xFFFFFUL << UCPD_RX_ORDEXT1_RXSOPX1_Pos)/*!< 0x000FFFFF */
12423 #define UCPD_RX_ORDEXT1_RXSOPX1 UCPD_RX_ORDEXT1_RXSOPX1_Msk /*!< RX Ordered Set Extension Register 1 */
12424
12425 /******************** Bits definition for UCPD_RXORDEXT2 register **************/
12426 #define UCPD_RX_ORDEXT2_RXSOPX2_Pos (0U)
12427 #define UCPD_RX_ORDEXT2_RXSOPX2_Msk (0xFFFFFUL << UCPD_RX_ORDEXT2_RXSOPX2_Pos)/*!< 0x000FFFFF */
12428 #define UCPD_RX_ORDEXT2_RXSOPX2 UCPD_RX_ORDEXT2_RXSOPX2_Msk /*!< RX Ordered Set Extension Register 1 */
12429
12430 /******************************************************************************/
12431 /* */
12432 /* Window WATCHDOG */
12433 /* */
12434 /******************************************************************************/
12435 /******************* Bit definition for WWDG_CR register ********************/
12436 #define WWDG_CR_T_Pos (0U)
12437 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
12438 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
12439 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
12440 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
12441 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
12442 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
12443 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
12444 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
12445 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
12446
12447 #define WWDG_CR_WDGA_Pos (7U)
12448 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
12449 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
12450
12451 /******************* Bit definition for WWDG_CFR register *******************/
12452 #define WWDG_CFR_W_Pos (0U)
12453 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
12454 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
12455 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
12456 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
12457 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
12458 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
12459 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
12460 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
12461 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
12462
12463 #define WWDG_CFR_WDGTB_Pos (11U)
12464 #define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00003800 */
12465 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[2:0] bits (Timer Base) */
12466 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000800 */
12467 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00001000 */
12468 #define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00002000 */
12469
12470 #define WWDG_CFR_EWI_Pos (9U)
12471 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
12472 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
12473
12474 /******************* Bit definition for WWDG_SR register ********************/
12475 #define WWDG_SR_EWIF_Pos (0U)
12476 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
12477 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
12478
12479 /**
12480 * @}
12481 */
12482
12483 /**
12484 * @}
12485 */
12486
12487 /** @addtogroup Exported_macros
12488 * @{
12489 */
12490
12491 /******************************* ADC Instances ********************************/
12492
12493 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
12494 ((INSTANCE) == ADC2))
12495
12496 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
12497
12498 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
12499
12500
12501 /******************************** FDCAN Instances ******************************/
12502 #define IS_FDCAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN1)
12503
12504 #define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN_CONFIG)
12505 /******************************** COMP Instances ******************************/
12506 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
12507 ((INSTANCE) == COMP2) || \
12508 ((INSTANCE) == COMP3) || \
12509 ((INSTANCE) == COMP4))
12510
12511 /******************************* CORDIC Instances *****************************/
12512 #define IS_CORDIC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CORDIC)
12513
12514 /******************************* CRC Instances ********************************/
12515 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
12516
12517 /******************************* DAC Instances ********************************/
12518 #define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1) || \
12519 ((INSTANCE) == DAC3))
12520
12521
12522 /******************************** DMA Instances *******************************/
12523 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
12524 ((INSTANCE) == DMA1_Channel2) || \
12525 ((INSTANCE) == DMA1_Channel3) || \
12526 ((INSTANCE) == DMA1_Channel4) || \
12527 ((INSTANCE) == DMA1_Channel5) || \
12528 ((INSTANCE) == DMA1_Channel6) || \
12529 ((INSTANCE) == DMA2_Channel1) || \
12530 ((INSTANCE) == DMA2_Channel2) || \
12531 ((INSTANCE) == DMA2_Channel3) || \
12532 ((INSTANCE) == DMA2_Channel4) || \
12533 ((INSTANCE) == DMA2_Channel5) || \
12534 ((INSTANCE) == DMA2_Channel6))
12535
12536 #define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
12537 ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
12538 ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
12539 ((INSTANCE) == DMAMUX1_RequestGenerator3))
12540
12541 /******************************* FMAC Instances *******************************/
12542 #define IS_FMAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FMAC)
12543
12544 /******************************* GPIO Instances *******************************/
12545 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
12546 ((INSTANCE) == GPIOB) || \
12547 ((INSTANCE) == GPIOC) || \
12548 ((INSTANCE) == GPIOD) || \
12549 ((INSTANCE) == GPIOE) || \
12550 ((INSTANCE) == GPIOF) || \
12551 ((INSTANCE) == GPIOG))
12552
12553 /******************************* GPIO AF Instances ****************************/
12554 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
12555
12556 /**************************** GPIO Lock Instances *****************************/
12557 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
12558
12559 /******************************** I2C Instances *******************************/
12560 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
12561 ((INSTANCE) == I2C2) || \
12562 ((INSTANCE) == I2C3))
12563
12564 /****************** I2C Instances : wakeup capability from stop modes *********/
12565 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
12566
12567 /****************************** OPAMP Instances *******************************/
12568 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
12569 ((INSTANCE) == OPAMP2) || \
12570 ((INSTANCE) == OPAMP3))
12571
12572
12573 /******************************** PCD Instances *******************************/
12574 #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
12575
12576
12577 /******************************* RNG Instances ********************************/
12578 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
12579
12580 /****************************** RTC Instances *********************************/
12581 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
12582
12583 #define IS_TAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TAMP)
12584
12585 /****************************** SMBUS Instances *******************************/
12586 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
12587 ((INSTANCE) == I2C2) || \
12588 ((INSTANCE) == I2C3))
12589
12590 /******************************** SAI Instances *******************************/
12591 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || ((INSTANCE) == SAI1_Block_B))
12592
12593 /******************************** SPI Instances *******************************/
12594 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
12595 ((INSTANCE) == SPI2) || \
12596 ((INSTANCE) == SPI3))
12597
12598 /******************************** I2S Instances *******************************/
12599 #define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI2) || \
12600 ((__INSTANCE__) == SPI3))
12601
12602 /****************** LPTIM Instances : All supported instances *****************/
12603 #define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
12604
12605 /****************** LPTIM Instances : supporting encoder interface **************/
12606 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
12607
12608 /****************** LPTIM Instances : All supported instances *****************/
12609 #define IS_LPTIM_ENCODER_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
12610
12611 /****************** TIM Instances : All supported instances *******************/
12612 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12613 ((INSTANCE) == TIM2) || \
12614 ((INSTANCE) == TIM3) || \
12615 ((INSTANCE) == TIM4) || \
12616 ((INSTANCE) == TIM6) || \
12617 ((INSTANCE) == TIM7) || \
12618 ((INSTANCE) == TIM8) || \
12619 ((INSTANCE) == TIM15) || \
12620 ((INSTANCE) == TIM16) || \
12621 ((INSTANCE) == TIM17))
12622
12623 /****************** TIM Instances : supporting 32 bits counter ****************/
12624
12625 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
12626
12627 /****************** TIM Instances : supporting the break function *************/
12628 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12629 ((INSTANCE) == TIM8) || \
12630 ((INSTANCE) == TIM15) || \
12631 ((INSTANCE) == TIM16) || \
12632 ((INSTANCE) == TIM17))
12633
12634 /************** TIM Instances : supporting Break source selection *************/
12635 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12636 ((INSTANCE) == TIM8) || \
12637 ((INSTANCE) == TIM15) || \
12638 ((INSTANCE) == TIM16) || \
12639 ((INSTANCE) == TIM17))
12640
12641 /****************** TIM Instances : supporting 2 break inputs *****************/
12642 #define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12643 ((INSTANCE) == TIM8))
12644
12645 /************* TIM Instances : at least 1 capture/compare channel *************/
12646 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12647 ((INSTANCE) == TIM2) || \
12648 ((INSTANCE) == TIM3) || \
12649 ((INSTANCE) == TIM4) || \
12650 ((INSTANCE) == TIM8) || \
12651 ((INSTANCE) == TIM15) || \
12652 ((INSTANCE) == TIM16) || \
12653 ((INSTANCE) == TIM17))
12654
12655 /************ TIM Instances : at least 2 capture/compare channels *************/
12656 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12657 ((INSTANCE) == TIM2) || \
12658 ((INSTANCE) == TIM3) || \
12659 ((INSTANCE) == TIM4) || \
12660 ((INSTANCE) == TIM8) || \
12661 ((INSTANCE) == TIM15))
12662
12663 /************ TIM Instances : at least 3 capture/compare channels *************/
12664 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12665 ((INSTANCE) == TIM2) || \
12666 ((INSTANCE) == TIM3) || \
12667 ((INSTANCE) == TIM4) || \
12668 ((INSTANCE) == TIM8))
12669
12670 /************ TIM Instances : at least 4 capture/compare channels *************/
12671 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12672 ((INSTANCE) == TIM2) || \
12673 ((INSTANCE) == TIM3) || \
12674 ((INSTANCE) == TIM4) || \
12675 ((INSTANCE) == TIM8))
12676
12677 /****************** TIM Instances : at least 5 capture/compare channels *******/
12678 #define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12679 ((INSTANCE) == TIM8))
12680
12681 /****************** TIM Instances : at least 6 capture/compare channels *******/
12682 #define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12683 ((INSTANCE) == TIM8))
12684
12685 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
12686 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12687 ((INSTANCE) == TIM8) || \
12688 ((INSTANCE) == TIM15) || \
12689 ((INSTANCE) == TIM16) || \
12690 ((INSTANCE) == TIM17))
12691
12692 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
12693 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12694 ((INSTANCE) == TIM2) || \
12695 ((INSTANCE) == TIM3) || \
12696 ((INSTANCE) == TIM4) || \
12697 ((INSTANCE) == TIM6) || \
12698 ((INSTANCE) == TIM7) || \
12699 ((INSTANCE) == TIM8) || \
12700 ((INSTANCE) == TIM15) || \
12701 ((INSTANCE) == TIM16) || \
12702 ((INSTANCE) == TIM17))
12703
12704 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
12705 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12706 ((INSTANCE) == TIM2) || \
12707 ((INSTANCE) == TIM3) || \
12708 ((INSTANCE) == TIM4) || \
12709 ((INSTANCE) == TIM8) || \
12710 ((INSTANCE) == TIM15) || \
12711 ((INSTANCE) == TIM16) || \
12712 ((INSTANCE) == TIM17))
12713
12714 /******************** TIM Instances : DMA burst feature ***********************/
12715 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12716 ((INSTANCE) == TIM2) || \
12717 ((INSTANCE) == TIM3) || \
12718 ((INSTANCE) == TIM4) || \
12719 ((INSTANCE) == TIM8) || \
12720 ((INSTANCE) == TIM15) || \
12721 ((INSTANCE) == TIM16) || \
12722 ((INSTANCE) == TIM17))
12723
12724 /******************* TIM Instances : output(s) available **********************/
12725 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
12726 ((((INSTANCE) == TIM1) && \
12727 (((CHANNEL) == TIM_CHANNEL_1) || \
12728 ((CHANNEL) == TIM_CHANNEL_2) || \
12729 ((CHANNEL) == TIM_CHANNEL_3) || \
12730 ((CHANNEL) == TIM_CHANNEL_4) || \
12731 ((CHANNEL) == TIM_CHANNEL_5) || \
12732 ((CHANNEL) == TIM_CHANNEL_6))) \
12733 || \
12734 (((INSTANCE) == TIM2) && \
12735 (((CHANNEL) == TIM_CHANNEL_1) || \
12736 ((CHANNEL) == TIM_CHANNEL_2) || \
12737 ((CHANNEL) == TIM_CHANNEL_3) || \
12738 ((CHANNEL) == TIM_CHANNEL_4))) \
12739 || \
12740 (((INSTANCE) == TIM3) && \
12741 (((CHANNEL) == TIM_CHANNEL_1) || \
12742 ((CHANNEL) == TIM_CHANNEL_2) || \
12743 ((CHANNEL) == TIM_CHANNEL_3) || \
12744 ((CHANNEL) == TIM_CHANNEL_4))) \
12745 || \
12746 (((INSTANCE) == TIM4) && \
12747 (((CHANNEL) == TIM_CHANNEL_1) || \
12748 ((CHANNEL) == TIM_CHANNEL_2) || \
12749 ((CHANNEL) == TIM_CHANNEL_3) || \
12750 ((CHANNEL) == TIM_CHANNEL_4))) \
12751 || \
12752 (((INSTANCE) == TIM8) && \
12753 (((CHANNEL) == TIM_CHANNEL_1) || \
12754 ((CHANNEL) == TIM_CHANNEL_2) || \
12755 ((CHANNEL) == TIM_CHANNEL_3) || \
12756 ((CHANNEL) == TIM_CHANNEL_4) || \
12757 ((CHANNEL) == TIM_CHANNEL_5) || \
12758 ((CHANNEL) == TIM_CHANNEL_6))) \
12759 || \
12760 (((INSTANCE) == TIM15) && \
12761 (((CHANNEL) == TIM_CHANNEL_1) || \
12762 ((CHANNEL) == TIM_CHANNEL_2))) \
12763 || \
12764 (((INSTANCE) == TIM16) && \
12765 (((CHANNEL) == TIM_CHANNEL_1))) \
12766 || \
12767 (((INSTANCE) == TIM17) && \
12768 (((CHANNEL) == TIM_CHANNEL_1))))
12769
12770 /****************** TIM Instances : supporting complementary output(s) ********/
12771 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
12772 ((((INSTANCE) == TIM1) && \
12773 (((CHANNEL) == TIM_CHANNEL_1) || \
12774 ((CHANNEL) == TIM_CHANNEL_2) || \
12775 ((CHANNEL) == TIM_CHANNEL_3) || \
12776 ((CHANNEL) == TIM_CHANNEL_4))) \
12777 || \
12778 (((INSTANCE) == TIM8) && \
12779 (((CHANNEL) == TIM_CHANNEL_1) || \
12780 ((CHANNEL) == TIM_CHANNEL_2) || \
12781 ((CHANNEL) == TIM_CHANNEL_3) || \
12782 ((CHANNEL) == TIM_CHANNEL_4))) \
12783 || \
12784 (((INSTANCE) == TIM15) && \
12785 ((CHANNEL) == TIM_CHANNEL_1)) \
12786 || \
12787 (((INSTANCE) == TIM16) && \
12788 ((CHANNEL) == TIM_CHANNEL_1)) \
12789 || \
12790 (((INSTANCE) == TIM17) && \
12791 ((CHANNEL) == TIM_CHANNEL_1)))
12792
12793 /****************** TIM Instances : supporting clock division *****************/
12794 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12795 ((INSTANCE) == TIM2) || \
12796 ((INSTANCE) == TIM3) || \
12797 ((INSTANCE) == TIM4) || \
12798 ((INSTANCE) == TIM8) || \
12799 ((INSTANCE) == TIM15) || \
12800 ((INSTANCE) == TIM16) || \
12801 ((INSTANCE) == TIM17))
12802
12803 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
12804 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12805 ((INSTANCE) == TIM2) || \
12806 ((INSTANCE) == TIM3) || \
12807 ((INSTANCE) == TIM4) || \
12808 ((INSTANCE) == TIM8))
12809
12810 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
12811 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12812 ((INSTANCE) == TIM2) || \
12813 ((INSTANCE) == TIM3) || \
12814 ((INSTANCE) == TIM4) || \
12815 ((INSTANCE) == TIM8))
12816
12817 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
12818 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12819 ((INSTANCE) == TIM2) || \
12820 ((INSTANCE) == TIM3) || \
12821 ((INSTANCE) == TIM4) || \
12822 ((INSTANCE) == TIM8) || \
12823 ((INSTANCE) == TIM15))
12824
12825 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
12826 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12827 ((INSTANCE) == TIM2) || \
12828 ((INSTANCE) == TIM3) || \
12829 ((INSTANCE) == TIM4) || \
12830 ((INSTANCE) == TIM8) || \
12831 ((INSTANCE) == TIM15))
12832
12833 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
12834 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12835 ((INSTANCE) == TIM8))
12836
12837 /****************** TIM Instances : supporting commutation event generation ***/
12838 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12839 ((INSTANCE) == TIM8) || \
12840 ((INSTANCE) == TIM15) || \
12841 ((INSTANCE) == TIM16) || \
12842 ((INSTANCE) == TIM17))
12843
12844 /****************** TIM Instances : supporting counting mode selection ********/
12845 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12846 ((INSTANCE) == TIM2) || \
12847 ((INSTANCE) == TIM3) || \
12848 ((INSTANCE) == TIM4) || \
12849 ((INSTANCE) == TIM8))
12850
12851 /****************** TIM Instances : supporting encoder interface **************/
12852 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12853 ((INSTANCE) == TIM2) || \
12854 ((INSTANCE) == TIM3) || \
12855 ((INSTANCE) == TIM4) || \
12856 ((INSTANCE) == TIM8))
12857
12858 /****************** TIM Instances : supporting Hall sensor interface **********/
12859 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12860 ((INSTANCE) == TIM2) || \
12861 ((INSTANCE) == TIM3) || \
12862 ((INSTANCE) == TIM4) || \
12863 ((INSTANCE) == TIM8) || \
12864 ((INSTANCE) == TIM15))
12865
12866 /**************** TIM Instances : external trigger input available ************/
12867 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12868 ((INSTANCE) == TIM2) || \
12869 ((INSTANCE) == TIM3) || \
12870 ((INSTANCE) == TIM4) || \
12871 ((INSTANCE) == TIM8))
12872
12873 /************* TIM Instances : supporting ETR source selection ***************/
12874 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12875 ((INSTANCE) == TIM2) || \
12876 ((INSTANCE) == TIM3) || \
12877 ((INSTANCE) == TIM4) || \
12878 ((INSTANCE) == TIM8))
12879
12880 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
12881 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12882 ((INSTANCE) == TIM2) || \
12883 ((INSTANCE) == TIM3) || \
12884 ((INSTANCE) == TIM4) || \
12885 ((INSTANCE) == TIM6) || \
12886 ((INSTANCE) == TIM7) || \
12887 ((INSTANCE) == TIM8) || \
12888 ((INSTANCE) == TIM15))
12889
12890 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
12891 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12892 ((INSTANCE) == TIM2) || \
12893 ((INSTANCE) == TIM3) || \
12894 ((INSTANCE) == TIM4) || \
12895 ((INSTANCE) == TIM8) || \
12896 ((INSTANCE) == TIM15))
12897
12898 /****************** TIM Instances : supporting OCxREF clear *******************/
12899
12900 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12901 ((INSTANCE) == TIM2) || \
12902 ((INSTANCE) == TIM3) || \
12903 ((INSTANCE) == TIM4) || \
12904 ((INSTANCE) == TIM8) || \
12905 ((INSTANCE) == TIM15) || \
12906 ((INSTANCE) == TIM16) || \
12907 ((INSTANCE) == TIM17))
12908
12909 /****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
12910 #define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12911 ((INSTANCE) == TIM2) || \
12912 ((INSTANCE) == TIM3) || \
12913 ((INSTANCE) == TIM8) || \
12914 ((INSTANCE) == TIM15) || \
12915 ((INSTANCE) == TIM16) || \
12916 ((INSTANCE) == TIM17))
12917
12918 /****************** TIM Instances : remapping capability **********************/
12919 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12920 ((INSTANCE) == TIM2) || \
12921 ((INSTANCE) == TIM3) || \
12922 ((INSTANCE) == TIM4) || \
12923 ((INSTANCE) == TIM8))
12924
12925 /****************** TIM Instances : supporting repetition counter *************/
12926 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12927 ((INSTANCE) == TIM8) || \
12928 ((INSTANCE) == TIM15) || \
12929 ((INSTANCE) == TIM16) || \
12930 ((INSTANCE) == TIM17))
12931
12932 /****************** TIM Instances : supporting synchronization ****************/
12933 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
12934
12935 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
12936 #define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12937 ((INSTANCE) == TIM8))
12938
12939 /******************* TIM Instances : Timer input XOR function *****************/
12940 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12941 ((INSTANCE) == TIM2) || \
12942 ((INSTANCE) == TIM3) || \
12943 ((INSTANCE) == TIM4) || \
12944 ((INSTANCE) == TIM8) || \
12945 ((INSTANCE) == TIM15))
12946
12947 /******************* TIM Instances : Timer input selection ********************/
12948 #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12949 ((INSTANCE) == TIM2) || \
12950 ((INSTANCE) == TIM3) || \
12951 ((INSTANCE) == TIM4) || \
12952 ((INSTANCE) == TIM8) || \
12953 ((INSTANCE) == TIM15) || \
12954 ((INSTANCE) == TIM16) || \
12955 ((INSTANCE) == TIM17))
12956
12957
12958 /****************** TIM Instances : Advanced timer instances *******************/
12959 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
12960 ((INSTANCE) == TIM8))
12961
12962
12963 /****************** TIM Instances : supporting HSE/32 request instances *******************/
12964 #define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16) || \
12965 ((INSTANCE) == TIM17))
12966
12967
12968 /******************** USART Instances : Synchronous mode **********************/
12969 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
12970 ((INSTANCE) == USART2) || \
12971 ((INSTANCE) == USART3))
12972
12973 /******************** UART Instances : Asynchronous mode **********************/
12974 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
12975 ((INSTANCE) == USART2) || \
12976 ((INSTANCE) == USART3))
12977
12978 /*********************** UART Instances : FIFO mode ***************************/
12979 #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
12980 ((INSTANCE) == USART2) || \
12981 ((INSTANCE) == USART3) || \
12982 ((INSTANCE) == LPUART1))
12983
12984 /*********************** UART Instances : SPI Slave mode **********************/
12985 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
12986 ((INSTANCE) == USART2) || \
12987 ((INSTANCE) == USART3))
12988
12989 /****************** UART Instances : Auto Baud Rate detection ****************/
12990 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
12991 ((INSTANCE) == USART2) || \
12992 ((INSTANCE) == USART3))
12993
12994 /****************** UART Instances : Driver Enable *****************/
12995 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
12996 ((INSTANCE) == USART2) || \
12997 ((INSTANCE) == USART3) || \
12998 ((INSTANCE) == LPUART1))
12999
13000 /******************** UART Instances : Half-Duplex mode **********************/
13001 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
13002 ((INSTANCE) == USART2) || \
13003 ((INSTANCE) == USART3) || \
13004 ((INSTANCE) == LPUART1))
13005
13006 /****************** UART Instances : Hardware Flow control ********************/
13007 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
13008 ((INSTANCE) == USART2) || \
13009 ((INSTANCE) == USART3) || \
13010 ((INSTANCE) == LPUART1))
13011
13012 /******************** UART Instances : LIN mode **********************/
13013 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
13014 ((INSTANCE) == USART2) || \
13015 ((INSTANCE) == USART3))
13016
13017 /******************** UART Instances : Wake-up from Stop mode **********************/
13018 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
13019 ((INSTANCE) == USART2) || \
13020 ((INSTANCE) == USART3) || \
13021 ((INSTANCE) == LPUART1))
13022
13023 /*********************** UART Instances : IRDA mode ***************************/
13024 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
13025 ((INSTANCE) == USART2) || \
13026 ((INSTANCE) == USART3))
13027
13028 /********************* USART Instances : Smard card mode ***********************/
13029 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
13030 ((INSTANCE) == USART2) || \
13031 ((INSTANCE) == USART3))
13032
13033 /******************** LPUART Instance *****************************************/
13034 #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
13035
13036 /****************************** IWDG Instances ********************************/
13037 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
13038
13039 /****************************** WWDG Instances ********************************/
13040 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
13041
13042 /****************************** UCPD Instances ********************************/
13043 #define IS_UCPD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == UCPD1)
13044
13045 /******************************* USB Instances *******************************/
13046 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
13047
13048 /**
13049 * @}
13050 */
13051
13052
13053 /******************************************************************************/
13054 /* For a painless codes migration between the STM32G4xx device product */
13055 /* lines, the aliases defined below are put in place to overcome the */
13056 /* differences in the interrupt handlers and IRQn definitions. */
13057 /* No need to update developed interrupt code when moving across */
13058 /* product lines within the same STM32G4 Family */
13059 /******************************************************************************/
13060
13061 /* Aliases for __IRQn */
13062 #define TIM7_DAC_IRQn TIM7_IRQn
13063 #define COMP4_5_6_IRQn COMP4_IRQn
13064
13065 /* Aliases for __IRQHandler */
13066 #define TIM7_DAC_IRQHandler TIM7_IRQHandler
13067 #define COMP4_5_6_IRQHandler COMP4_IRQHandler
13068
13069 #ifdef __cplusplus
13070 }
13071 #endif /* __cplusplus */
13072
13073 #endif /* __STM32GBK1CB_H */
13074
13075 /**
13076 * @}
13077 */
13078
13079 /**
13080 * @}
13081 */
13082
13083 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/