lib/main/STM32H7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32h7xx_hal_dma.h
   4   * @author  MCD Application Team
   5   * @brief   Header file of DMA HAL module.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
  10   * All rights reserved.</center></h2>
  11   *
  12   * This software component is licensed by ST under BSD 3-Clause license,
  13   * the "License"; You may not use this file except in compliance with the
  14   * License. You may obtain a copy of the License at:
  15   *                        opensource.org/licenses/BSD-3-Clause
  16   *
  17   ******************************************************************************
  18   */
  19
  20 /* Define to prevent recursive inclusion -------------------------------------*/
  21 #ifndef STM32H7xx_HAL_DMA_H
  22 #define STM32H7xx_HAL_DMA_H
  23
  24 #ifdef __cplusplus
  25  extern "C" {
  26 #endif
  27
  28 /* Includes ------------------------------------------------------------------*/
  29 #include "stm32h7xx_hal_def.h"
  30
  31 /** @addtogroup STM32H7xx_HAL_Driver
  32   * @{
  33   */
  34
  35 /** @addtogroup DMA
  36   * @{
  37   */
  38
  39 /* Exported types ------------------------------------------------------------*/
  40
  41 /** @defgroup DMA_Exported_Types DMA Exported Types
  42   * @brief    DMA Exported Types
  43   * @{
  44   */
  45
  46 /**
  47   * @brief  DMA Configuration Structure definition
  48   */
  49 typedef struct
  50 {
  51   uint32_t Request;               /*!< Specifies the request selected for the specified stream.
  52                                            This parameter can be a value of @ref DMA_Request_selection              */
  53
  54   uint32_t Direction;            /*!< Specifies if the data will be transferred from memory to peripheral,
  55                                       from memory to memory or from peripheral to memory.
  56                                       This parameter can be a value of @ref DMA_Data_transfer_direction              */
  57
  58   uint32_t PeriphInc;            /*!< Specifies whether the Peripheral address register should be incremented or not.
  59                                       This parameter can be a value of @ref DMA_Peripheral_incremented_mode          */
  60
  61   uint32_t MemInc;               /*!< Specifies whether the memory address register should be incremented or not.
  62                                       This parameter can be a value of @ref DMA_Memory_incremented_mode              */
  63
  64   uint32_t PeriphDataAlignment;  /*!< Specifies the Peripheral data width.
  65                                       This parameter can be a value of @ref DMA_Peripheral_data_size                 */
  66
  67   uint32_t MemDataAlignment;     /*!< Specifies the Memory data width.
  68                                       This parameter can be a value of @ref DMA_Memory_data_size                     */
  69
  70   uint32_t Mode;                 /*!< Specifies the operation mode of the DMAy Streamx.
  71                                       This parameter can be a value of @ref DMA_mode
  72                                       @note The circular buffer mode cannot be used if the memory-to-memory
  73                                             data transfer is configured on the selected Stream                        */
  74
  75   uint32_t Priority;             /*!< Specifies the software priority for the DMAy Streamx.
  76                                       This parameter can be a value of @ref DMA_Priority_level                        */
  77
  78   uint32_t FIFOMode;             /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
  79                                       This parameter can be a value of @ref DMA_FIFO_direct_mode
  80                                       @note The Direct mode (FIFO mode disabled) cannot be used if the
  81                                             memory-to-memory data transfer is configured on the selected stream       */
  82
  83   uint32_t FIFOThreshold;        /*!< Specifies the FIFO threshold level.
  84                                       This parameter can be a value of @ref DMA_FIFO_threshold_level                  */
  85
  86   uint32_t MemBurst;             /*!< Specifies the Burst transfer configuration for the memory transfers.
  87                                       It specifies the amount of data to be transferred in a single non interruptible
  88                                       transaction.
  89                                       This parameter can be a value of @ref DMA_Memory_burst
  90                                       @note The burst mode is possible only if the address Increment mode is enabled. */
  91
  92   uint32_t PeriphBurst;          /*!< Specifies the Burst transfer configuration for the peripheral transfers.
  93                                       It specifies the amount of data to be transferred in a single non interruptible
  94                                       transaction.
  95                                       This parameter can be a value of @ref DMA_Peripheral_burst
  96                                       @note The burst mode is possible only if the address Increment mode is enabled. */
  97 }DMA_InitTypeDef;
  98
  99 /**
 100   * @brief  HAL DMA State structures definition
 101   */
 102 typedef enum
 103 {
 104   HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled */
 105   HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use   */
 106   HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing              */
 107   HAL_DMA_STATE_ERROR             = 0x03U,  /*!< DMA error state                     */
 108   HAL_DMA_STATE_ABORT             = 0x04U,  /*!< DMA Abort state                     */
 109 }HAL_DMA_StateTypeDef;
 110
 111 /**
 112   * @brief  HAL DMA Transfer complete level structure definition
 113   */
 114 typedef enum
 115 {
 116   HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */
 117   HAL_DMA_HALF_TRANSFER      = 0x01U,    /*!< Half Transfer     */
 118 }HAL_DMA_LevelCompleteTypeDef;
 119
 120 /**
 121   * @brief  HAL DMA Callbacks IDs structure definition
 122   */
 123 typedef enum
 124 {
 125   HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */
 126   HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half Transfer     */
 127   HAL_DMA_XFER_M1CPLT_CB_ID        = 0x02U,    /*!< M1 Full Transfer  */
 128   HAL_DMA_XFER_M1HALFCPLT_CB_ID    = 0x03U,    /*!< M1 Half Transfer  */
 129   HAL_DMA_XFER_ERROR_CB_ID         = 0x04U,    /*!< Error             */
 130   HAL_DMA_XFER_ABORT_CB_ID         = 0x05U,    /*!< Abort             */
 131   HAL_DMA_XFER_ALL_CB_ID           = 0x06U     /*!< All               */
 132 }HAL_DMA_CallbackIDTypeDef;
 133
 134 /**
 135   * @brief  DMA handle Structure definition
 136   */
 137 typedef struct __DMA_HandleTypeDef
 138 {
 139   void                            *Instance;                                                        /*!< Register base address                         */
 140
 141   DMA_InitTypeDef                 Init;                                                             /*!< DMA communication parameters                  */
 142
 143   HAL_LockTypeDef                 Lock;                                                             /*!< DMA locking object                            */
 144
 145   __IO HAL_DMA_StateTypeDef       State;                                                            /*!< DMA transfer state                            */
 146
 147   void                            *Parent;                                                          /*!< Parent object state                           */
 148
 149   void                            (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);         /*!< DMA transfer complete callback                */
 150
 151   void                            (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA Half transfer complete callback           */
 152
 153   void                            (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);       /*!< DMA transfer complete Memory1 callback        */
 154
 155   void                            (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer Half complete Memory1 callback   */
 156
 157   void                            (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);        /*!< DMA transfer error callback                   */
 158
 159   void                            (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);        /*!< DMA transfer Abort callback                   */
 160
 161  __IO uint32_t                    ErrorCode;                                                        /*!< DMA Error code                                */
 162
 163  uint32_t                         StreamBaseAddress;                                                /*!< DMA Stream Base Address                       */
 164
 165  uint32_t                         StreamIndex;                                                      /*!< DMA Stream Index                              */
 166
 167  DMAMUX_Channel_TypeDef           *DMAmuxChannel;                                                   /*!< DMAMUX Channel Base Address                   */
 168
 169  DMAMUX_ChannelStatus_TypeDef     *DMAmuxChannelStatus;                                             /*!< DMAMUX Channels Status Base Address           */
 170
 171  uint32_t                         DMAmuxChannelStatusMask;                                          /*!< DMAMUX Channel Status Mask                    */
 172
 173
 174  DMAMUX_RequestGen_TypeDef        *DMAmuxRequestGen;                                                /*!< DMAMUX request generator Base Address         */
 175
 176  DMAMUX_RequestGenStatus_TypeDef  *DMAmuxRequestGenStatus;                                          /*!< DMAMUX request generator Status Address       */
 177
 178  uint32_t                         DMAmuxRequestGenStatusMask;                                       /*!< DMAMUX request generator Status mask          */
 179
 180 }DMA_HandleTypeDef;
 181
 182 /**
 183   * @}
 184   */
 185
 186
 187 /* Exported constants --------------------------------------------------------*/
 188
 189 /** @defgroup DMA_Exported_Constants DMA Exported Constants
 190   * @brief    DMA Exported constants
 191   * @{
 192   */
 193
 194 /** @defgroup DMA_Error_Code DMA Error Code
 195   * @brief    DMA Error Code
 196   * @{
 197   */
 198 #define HAL_DMA_ERROR_NONE            (0x00000000U)    /*!< No error                                */
 199 #define HAL_DMA_ERROR_TE              (0x00000001U)    /*!< Transfer error                          */
 200 #define HAL_DMA_ERROR_FE              (0x00000002U)    /*!< FIFO error                              */
 201 #define HAL_DMA_ERROR_DME             (0x00000004U)    /*!< Direct Mode error                       */
 202 #define HAL_DMA_ERROR_TIMEOUT         (0x00000020U)    /*!< Timeout error                           */
 203 #define HAL_DMA_ERROR_PARAM           (0x00000040U)    /*!< Parameter error                         */
 204 #define HAL_DMA_ERROR_NO_XFER         (0x00000080U)    /*!< Abort requested with no Xfer ongoing    */
 205 #define HAL_DMA_ERROR_NOT_SUPPORTED   (0x00000100U)    /*!< Not supported mode                      */
 206 #define HAL_DMA_ERROR_SYNC            (0x00000200U)    /*!< DMAMUX sync overrun  error              */
 207 #define HAL_DMA_ERROR_REQGEN          (0x00000400U)    /*!< DMAMUX request generator overrun  error */
 208 #define HAL_DMA_ERROR_BUSY            (0x00000800U)    /*!< DMA Busy                          error */
 209
 210 /**
 211   * @}
 212   */
 213
 214 /** @defgroup DMA_Request_selection DMA Request selection
 215   * @brief    DMA Request selection
 216   * @{
 217   */
 218 /* DMAMUX1 requests */
 219 #define DMA_REQUEST_MEM2MEM          0U  /*!< memory to memory transfer   */
 220
 221 #define DMA_REQUEST_GENERATOR0       1U  /*!< DMAMUX1 request generator 0 */
 222 #define DMA_REQUEST_GENERATOR1       2U  /*!< DMAMUX1 request generator 1 */
 223 #define DMA_REQUEST_GENERATOR2       3U  /*!< DMAMUX1 request generator 2 */
 224 #define DMA_REQUEST_GENERATOR3       4U  /*!< DMAMUX1 request generator 3 */
 225 #define DMA_REQUEST_GENERATOR4       5U  /*!< DMAMUX1 request generator 4 */
 226 #define DMA_REQUEST_GENERATOR5       6U  /*!< DMAMUX1 request generator 5 */
 227 #define DMA_REQUEST_GENERATOR6       7U  /*!< DMAMUX1 request generator 6 */
 228 #define DMA_REQUEST_GENERATOR7       8U  /*!< DMAMUX1 request generator 7 */
 229
 230 #define DMA_REQUEST_ADC1             9U  /*!< DMAMUX1 ADC1 request */
 231 #define DMA_REQUEST_ADC2             10U /*!< DMAMUX1 ADC2 request */
 232
 233 #define DMA_REQUEST_TIM1_CH1         11U  /*!< DMAMUX1 TIM1 CH1 request  */
 234 #define DMA_REQUEST_TIM1_CH2         12U  /*!< DMAMUX1 TIM1 CH2 request  */
 235 #define DMA_REQUEST_TIM1_CH3         13U  /*!< DMAMUX1 TIM1 CH3 request  */
 236 #define DMA_REQUEST_TIM1_CH4         14U  /*!< DMAMUX1 TIM1 CH4 request  */
 237 #define DMA_REQUEST_TIM1_UP          15U  /*!< DMAMUX1 TIM1 UP request   */
 238 #define DMA_REQUEST_TIM1_TRIG        16U  /*!< DMAMUX1 TIM1 TRIG request */
 239 #define DMA_REQUEST_TIM1_COM         17U  /*!< DMAMUX1 TIM1 COM request  */
 240
 241 #define DMA_REQUEST_TIM2_CH1         18U  /*!< DMAMUX1 TIM2 CH1 request  */
 242 #define DMA_REQUEST_TIM2_CH2         19U  /*!< DMAMUX1 TIM2 CH2 request  */
 243 #define DMA_REQUEST_TIM2_CH3         20U  /*!< DMAMUX1 TIM2 CH3 request  */
 244 #define DMA_REQUEST_TIM2_CH4         21U  /*!< DMAMUX1 TIM2 CH4 request  */
 245 #define DMA_REQUEST_TIM2_UP          22U  /*!< DMAMUX1 TIM2 UP request   */
 246
 247 #define DMA_REQUEST_TIM3_CH1         23U  /*!< DMAMUX1 TIM3 CH1 request  */
 248 #define DMA_REQUEST_TIM3_CH2         24U  /*!< DMAMUX1 TIM3 CH2 request  */
 249 #define DMA_REQUEST_TIM3_CH3         25U  /*!< DMAMUX1 TIM3 CH3 request  */
 250 #define DMA_REQUEST_TIM3_CH4         26U  /*!< DMAMUX1 TIM3 CH4 request  */
 251 #define DMA_REQUEST_TIM3_UP          27U  /*!< DMAMUX1 TIM3 UP request   */
 252 #define DMA_REQUEST_TIM3_TRIG        28U  /*!< DMAMUX1 TIM3 TRIG request */
 253
 254 #define DMA_REQUEST_TIM4_CH1         29U  /*!< DMAMUX1 TIM4 CH1 request  */
 255 #define DMA_REQUEST_TIM4_CH2         30U  /*!< DMAMUX1 TIM4 CH2 request  */
 256 #define DMA_REQUEST_TIM4_CH3         31U  /*!< DMAMUX1 TIM4 CH3 request  */
 257 #define DMA_REQUEST_TIM4_UP          32U  /*!< DMAMUX1 TIM4 UP request   */
 258
 259 #define DMA_REQUEST_I2C1_RX          33U  /*!< DMAMUX1 I2C1 RX request   */
 260 #define DMA_REQUEST_I2C1_TX          34U  /*!< DMAMUX1 I2C1 TX request   */
 261 #define DMA_REQUEST_I2C2_RX          35U  /*!< DMAMUX1 I2C2 RX request   */
 262 #define DMA_REQUEST_I2C2_TX          36U  /*!< DMAMUX1 I2C2 TX request   */
 263
 264 #define DMA_REQUEST_SPI1_RX          37U  /*!< DMAMUX1 SPI1 RX request   */
 265 #define DMA_REQUEST_SPI1_TX          38U  /*!< DMAMUX1 SPI1 TX request   */
 266 #define DMA_REQUEST_SPI2_RX          39U  /*!< DMAMUX1 SPI2 RX request   */
 267 #define DMA_REQUEST_SPI2_TX          40U  /*!< DMAMUX1 SPI2 TX request   */
 268
 269 #define DMA_REQUEST_USART1_RX        41U  /*!< DMAMUX1 USART1 RX request */
 270 #define DMA_REQUEST_USART1_TX        42U  /*!< DMAMUX1 USART1 TX request */
 271 #define DMA_REQUEST_USART2_RX        43U  /*!< DMAMUX1 USART2 RX request */
 272 #define DMA_REQUEST_USART2_TX        44U  /*!< DMAMUX1 USART2 TX request */
 273 #define DMA_REQUEST_USART3_RX        45U  /*!< DMAMUX1 USART3 RX request */
 274 #define DMA_REQUEST_USART3_TX        46U  /*!< DMAMUX1 USART3 TX request */
 275
 276 #define DMA_REQUEST_TIM8_CH1         47U  /*!< DMAMUX1 TIM8 CH1 request  */
 277 #define DMA_REQUEST_TIM8_CH2         48U  /*!< DMAMUX1 TIM8 CH2 request  */
 278 #define DMA_REQUEST_TIM8_CH3         49U  /*!< DMAMUX1 TIM8 CH3 request  */
 279 #define DMA_REQUEST_TIM8_CH4         50U  /*!< DMAMUX1 TIM8 CH4 request  */
 280 #define DMA_REQUEST_TIM8_UP          51U  /*!< DMAMUX1 TIM8 UP request   */
 281 #define DMA_REQUEST_TIM8_TRIG        52U  /*!< DMAMUX1 TIM8 TRIG request */
 282 #define DMA_REQUEST_TIM8_COM         53U  /*!< DMAMUX1 TIM8 COM request  */
 283
 284 #define DMA_REQUEST_TIM5_CH1         55U  /*!< DMAMUX1 TIM5 CH1 request  */
 285 #define DMA_REQUEST_TIM5_CH2         56U  /*!< DMAMUX1 TIM5 CH2 request  */
 286 #define DMA_REQUEST_TIM5_CH3         57U  /*!< DMAMUX1 TIM5 CH3 request  */
 287 #define DMA_REQUEST_TIM5_CH4         58U  /*!< DMAMUX1 TIM5 CH4 request  */
 288 #define DMA_REQUEST_TIM5_UP          59U  /*!< DMAMUX1 TIM5 UP request   */
 289 #define DMA_REQUEST_TIM5_TRIG        60U  /*!< DMAMUX1 TIM5 TRIG request */
 290
 291 #define DMA_REQUEST_SPI3_RX          61U  /*!< DMAMUX1 SPI3 RX request   */
 292 #define DMA_REQUEST_SPI3_TX          62U  /*!< DMAMUX1 SPI3 TX request   */
 293
 294 #define DMA_REQUEST_UART4_RX         63U  /*!< DMAMUX1 UART4 RX request */
 295 #define DMA_REQUEST_UART4_TX         64U  /*!< DMAMUX1 UART4 TX request */
 296 #define DMA_REQUEST_UART5_RX         65U  /*!< DMAMUX1 UART5 RX request */
 297 #define DMA_REQUEST_UART5_TX         66U  /*!< DMAMUX1 UART5 TX request */
 298
 299 #define DMA_REQUEST_DAC1_CH1         67U  /*!< DMAMUX1 DAC1 Channel 1 request */
 300 #define DMA_REQUEST_DAC1_CH2         68U  /*!< DMAMUX1 DAC1 Channel 2 request */
 301
 302 #define DMA_REQUEST_TIM6_UP          69U  /*!< DMAMUX1 TIM6 UP request   */
 303 #define DMA_REQUEST_TIM7_UP          70U  /*!< DMAMUX1 TIM7 UP request   */
 304
 305 #define DMA_REQUEST_USART6_RX        71U  /*!< DMAMUX1 USART6 RX request */
 306 #define DMA_REQUEST_USART6_TX        72U  /*!< DMAMUX1 USART6 TX request */
 307
 308 #define DMA_REQUEST_I2C3_RX          73U  /*!< DMAMUX1 I2C3 RX request   */
 309 #define DMA_REQUEST_I2C3_TX          74U  /*!< DMAMUX1 I2C3 TX request   */
 310
 311 #if defined (PSSI)
 312 #define DMA_REQUEST_DCMI_PSSI        75U  /*!< DMAMUX1 DCMI/PSSI request    */
 313 #define DMA_REQUEST_DCMI             DMA_REQUEST_DCMI_PSSI /* Legacy define */
 314 #else
 315 #define DMA_REQUEST_DCMI             75U  /*!< DMAMUX1 DCMI request         */
 316 #endif /* PSSI */
 317
 318 #define DMA_REQUEST_CRYP_IN          76U  /*!< DMAMUX1 CRYP IN request   */
 319 #define DMA_REQUEST_CRYP_OUT         77U  /*!< DMAMUX1 CRYP OUT request  */
 320
 321 #define DMA_REQUEST_HASH_IN          78U  /*!< DMAMUX1 HASH IN request   */
 322
 323 #define DMA_REQUEST_UART7_RX         79U  /*!< DMAMUX1 UART7 RX request  */
 324 #define DMA_REQUEST_UART7_TX         80U  /*!< DMAMUX1 UART7 TX request  */
 325 #define DMA_REQUEST_UART8_RX         81U  /*!< DMAMUX1 UART8 RX request  */
 326 #define DMA_REQUEST_UART8_TX         82U  /*!< DMAMUX1 UART8 TX request  */
 327
 328 #define DMA_REQUEST_SPI4_RX          83U  /*!< DMAMUX1 SPI4 RX request   */
 329 #define DMA_REQUEST_SPI4_TX          84U  /*!< DMAMUX1 SPI4 TX request   */
 330 #define DMA_REQUEST_SPI5_RX          85U  /*!< DMAMUX1 SPI5 RX request   */
 331 #define DMA_REQUEST_SPI5_TX          86U  /*!< DMAMUX1 SPI5 TX request   */
 332
 333 #define DMA_REQUEST_SAI1_A           87U  /*!< DMAMUX1 SAI1 A request    */
 334 #define DMA_REQUEST_SAI1_B           88U  /*!< DMAMUX1 SAI1 B request    */
 335
 336 #if defined(SAI2)
 337 #define DMA_REQUEST_SAI2_A           89U  /*!< DMAMUX1 SAI2 A request    */
 338 #define DMA_REQUEST_SAI2_B           90U  /*!< DMAMUX1 SAI2 B request    */
 339 #endif /* SAI2 */
 340
 341 #define DMA_REQUEST_SWPMI_RX         91U  /*!< DMAMUX1 SWPMI RX request  */
 342 #define DMA_REQUEST_SWPMI_TX         92U  /*!< DMAMUX1 SWPMI TX request  */
 343
 344 #define DMA_REQUEST_SPDIF_RX_DT      93U  /*!< DMAMUX1 SPDIF RXDT request*/
 345 #define DMA_REQUEST_SPDIF_RX_CS      94U  /*!< DMAMUX1 SPDIF RXCS request*/
 346
 347 #if defined(HRTIM1)
 348 #define DMA_REQUEST_HRTIM_MASTER     95U  /*!< DMAMUX1 HRTIM1 Master request 1 */
 349 #define DMA_REQUEST_HRTIM_TIMER_A    96U  /*!< DMAMUX1 HRTIM1 TimerA request 2 */
 350 #define DMA_REQUEST_HRTIM_TIMER_B    97U  /*!< DMAMUX1 HRTIM1 TimerB request 3 */
 351 #define DMA_REQUEST_HRTIM_TIMER_C    98U  /*!< DMAMUX1 HRTIM1 TimerC request 4 */
 352 #define DMA_REQUEST_HRTIM_TIMER_D    99U  /*!< DMAMUX1 HRTIM1 TimerD request 5 */
 353 #define DMA_REQUEST_HRTIM_TIMER_E   100U  /*!< DMAMUX1 HRTIM1 TimerE request 6 */
 354 #endif /* HRTIM1 */
 355
 356 #define DMA_REQUEST_DFSDM1_FLT0     101U  /*!< DMAMUX1 DFSDM Filter0 request */
 357 #define DMA_REQUEST_DFSDM1_FLT1     102U  /*!< DMAMUX1 DFSDM Filter1 request */
 358 #define DMA_REQUEST_DFSDM1_FLT2     103U  /*!< DMAMUX1 DFSDM Filter2 request */
 359 #define DMA_REQUEST_DFSDM1_FLT3     104U  /*!< DMAMUX1 DFSDM Filter3 request */
 360
 361 #define DMA_REQUEST_TIM15_CH1       105U  /*!< DMAMUX1 TIM15 CH1 request  */
 362 #define DMA_REQUEST_TIM15_UP        106U  /*!< DMAMUX1 TIM15 UP request   */
 363 #define DMA_REQUEST_TIM15_TRIG      107U  /*!< DMAMUX1 TIM15 TRIG request */
 364 #define DMA_REQUEST_TIM15_COM       108U  /*!< DMAMUX1 TIM15 COM request  */
 365
 366 #define DMA_REQUEST_TIM16_CH1       109U  /*!< DMAMUX1 TIM16 CH1 request  */
 367 #define DMA_REQUEST_TIM16_UP        110U  /*!< DMAMUX1 TIM16 UP request   */
 368
 369 #define DMA_REQUEST_TIM17_CH1       111U  /*!< DMAMUX1 TIM17 CH1 request  */
 370 #define DMA_REQUEST_TIM17_UP        112U  /*!< DMAMUX1 TIM17 UP request   */
 371
 372 #if defined(SAI3)
 373 #define DMA_REQUEST_SAI3_A          113U  /*!< DMAMUX1 SAI3 A request  */
 374 #define DMA_REQUEST_SAI3_B          114U  /*!< DMAMUX1 SAI3 B request  */
 375 #endif /* SAI3 */
 376
 377 #if defined(ADC3)
 378 #define DMA_REQUEST_ADC3            115U  /*!< DMAMUX1 ADC3 request  */
 379 #endif /* ADC3 */
 380
 381 #if defined(UART9)
 382 #define DMA_REQUEST_UART9_RX        116U  /*!< DMAMUX1 UART9 request  */
 383 #define DMA_REQUEST_UART9_TX        117U  /*!< DMAMUX1 UART9 request  */
 384 #endif /* UART9 */
 385
 386 #if defined(USART10)
 387 #define DMA_REQUEST_USART10_RX      118U  /*!< DMAMUX1 USART10 request  */
 388 #define DMA_REQUEST_USART10_TX      119U  /*!< DMAMUX1 USART10 request  */
 389 #endif /* USART10 */
 390
 391 #if defined(FMAC)
 392 #define DMA_REQUEST_FMAC_READ       120U  /*!< DMAMUX1 FMAC Read request  */
 393 #define DMA_REQUEST_FMAC_WRITE      121U  /*!< DMAMUX1 FMAC Write request */
 394 #endif /* FMAC */
 395
 396 #if defined(CORDIC)
 397 #define DMA_REQUEST_CORDIC_READ     122U  /*!< DMAMUX1 CORDIC Read request  */
 398 #define DMA_REQUEST_CORDIC_WRITE    123U  /*!< DMAMUX1 CORDIC Write request */
 399 #endif /* CORDIC */
 400
 401 #if defined(I2C5)
 402 #define DMA_REQUEST_I2C5_RX         124U  /*!< DMAMUX1 I2C5 RX request   */
 403 #define DMA_REQUEST_I2C5_TX         125U  /*!< DMAMUX1 I2C5 TX request   */
 404 #endif /* I2C5 */
 405
 406 #if defined(TIM23)
 407 #define DMA_REQUEST_TIM23_CH1        126U  /*!< DMAMUX1 TIM23 CH1 request  */
 408 #define DMA_REQUEST_TIM23_CH2        127U  /*!< DMAMUX1 TIM23 CH2 request  */
 409 #define DMA_REQUEST_TIM23_CH3        128U  /*!< DMAMUX1 TIM23 CH3 request  */
 410 #define DMA_REQUEST_TIM23_CH4        129U  /*!< DMAMUX1 TIM23 CH4 request  */
 411 #define DMA_REQUEST_TIM23_UP         130U  /*!< DMAMUX1 TIM23 UP request   */
 412 #define DMA_REQUEST_TIM23_TRIG       131U  /*!< DMAMUX1 TIM23 TRIG request */
 413 #endif /* TIM23 */
 414
 415 #if defined(TIM24)
 416 #define DMA_REQUEST_TIM24_CH1        132U  /*!< DMAMUX1 TIM24 CH1 request  */
 417 #define DMA_REQUEST_TIM24_CH2        133U  /*!< DMAMUX1 TIM24 CH2 request  */
 418 #define DMA_REQUEST_TIM24_CH3        134U  /*!< DMAMUX1 TIM24 CH3 request  */
 419 #define DMA_REQUEST_TIM24_CH4        135U  /*!< DMAMUX1 TIM24 CH4 request  */
 420 #define DMA_REQUEST_TIM24_UP         136U  /*!< DMAMUX1 TIM24 UP request   */
 421 #define DMA_REQUEST_TIM24_TRIG       137U  /*!< DMAMUX1 TIM24 TRIG request */
 422 #endif /* TIM24 */
 423
 424 /* DMAMUX2 requests */
 425 #define BDMA_REQUEST_MEM2MEM          0U  /*!< memory to memory transfer   */
 426 #define BDMA_REQUEST_GENERATOR0       1U  /*!< DMAMUX2 request generator 0 */
 427 #define BDMA_REQUEST_GENERATOR1       2U  /*!< DMAMUX2 request generator 1 */
 428 #define BDMA_REQUEST_GENERATOR2       3U  /*!< DMAMUX2 request generator 2 */
 429 #define BDMA_REQUEST_GENERATOR3       4U  /*!< DMAMUX2 request generator 3 */
 430 #define BDMA_REQUEST_GENERATOR4       5U  /*!< DMAMUX2 request generator 4 */
 431 #define BDMA_REQUEST_GENERATOR5       6U  /*!< DMAMUX2 request generator 5 */
 432 #define BDMA_REQUEST_GENERATOR6       7U  /*!< DMAMUX2 request generator 6 */
 433 #define BDMA_REQUEST_GENERATOR7       8U  /*!< DMAMUX2 request generator 7 */
 434 #define BDMA_REQUEST_LPUART1_RX       9U  /*!< DMAMUX2 LP_UART1_RX request */
 435 #define BDMA_REQUEST_LPUART1_TX      10U  /*!< DMAMUX2 LP_UART1_TX request */
 436 #define BDMA_REQUEST_SPI6_RX         11U  /*!< DMAMUX2 SPI6 RX request     */
 437 #define BDMA_REQUEST_SPI6_TX         12U  /*!< DMAMUX2 SPI6 TX request     */
 438 #define BDMA_REQUEST_I2C4_RX         13U  /*!< DMAMUX2 I2C4 RX request     */
 439 #define BDMA_REQUEST_I2C4_TX         14U  /*!< DMAMUX2 I2C4 TX request     */
 440 #if defined(SAI4)
 441 #define BDMA_REQUEST_SAI4_A          15U  /*!< DMAMUX2 SAI4 A request      */
 442 #define BDMA_REQUEST_SAI4_B          16U  /*!< DMAMUX2 SAI4 B request      */
 443 #endif /* SAI4 */
 444 #if defined(ADC3)
 445 #define BDMA_REQUEST_ADC3            17U  /*!< DMAMUX2 ADC3 request        */
 446 #endif /* ADC3 */
 447 #if defined(DAC2)
 448 #define BDMA_REQUEST_DAC2_CH1        17U  /*!< DMAMUX2 DAC2 CH1 request    */
 449 #endif /* DAC2 */
 450 #if defined(DFSDM2_Channel0)
 451 #define BDMA_REQUEST_DFSDM2_FLT0     18U  /*!< DMAMUX2 DFSDM2 request      */
 452 #endif /* DFSDM1_Channel0 */
 453
 454 /**
 455   * @}
 456   */
 457
 458 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
 459   * @brief    DMA data transfer direction
 460   * @{
 461   */
 462 #define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000U)      /*!< Peripheral to memory direction */
 463 #define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_SxCR_DIR_0)  /*!< Memory to peripheral direction */
 464 #define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_SxCR_DIR_1)  /*!< Memory to memory direction     */
 465 /**
 466   * @}
 467   */
 468
 469 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
 470   * @brief    DMA peripheral incremented mode
 471   * @{
 472   */
 473 #define DMA_PINC_ENABLE        ((uint32_t)DMA_SxCR_PINC)  /*!< Peripheral increment mode enable  */
 474 #define DMA_PINC_DISABLE       ((uint32_t)0x00000000U)     /*!< Peripheral increment mode disable */
 475 /**
 476   * @}
 477   */
 478
 479 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
 480   * @brief    DMA memory incremented mode
 481   * @{
 482   */
 483 #define DMA_MINC_ENABLE         ((uint32_t)DMA_SxCR_MINC)  /*!< Memory increment mode enable  */
 484 #define DMA_MINC_DISABLE        ((uint32_t)0x00000000U)     /*!< Memory increment mode disable */
 485 /**
 486   * @}
 487   */
 488
 489 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
 490   * @brief    DMA peripheral data size
 491   * @{
 492   */
 493 #define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000U)       /*!< Peripheral data alignment: Byte      */
 494 #define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_PSIZE_0)  /*!< Peripheral data alignment: HalfWord  */
 495 #define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_SxCR_PSIZE_1)  /*!< Peripheral data alignment: Word      */
 496 /**
 497   * @}
 498   */
 499
 500 /** @defgroup DMA_Memory_data_size DMA Memory data size
 501   * @brief    DMA memory data size
 502   * @{
 503   */
 504 #define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000U)       /*!< Memory data alignment: Byte     */
 505 #define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_MSIZE_0)  /*!< Memory data alignment: HalfWord */
 506 #define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_SxCR_MSIZE_1)  /*!< Memory data alignment: Word     */
 507 /**
 508   * @}
 509   */
 510
 511 /** @defgroup DMA_mode DMA mode
 512   * @brief    DMA mode
 513   * @{
 514   */
 515 #define DMA_NORMAL              ((uint32_t)0x00000000U)                  /*!< Normal mode                                    */
 516 #define DMA_CIRCULAR            ((uint32_t)DMA_SxCR_CIRC)                /*!< Circular mode                                  */
 517 #define DMA_PFCTRL              ((uint32_t)DMA_SxCR_PFCTRL)              /*!< Peripheral flow control mode                   */
 518 #define DMA_DOUBLE_BUFFER_M0    ((uint32_t)DMA_SxCR_DBM)                 /*!< Double buffer mode with first target memory M0 */
 519 #define DMA_DOUBLE_BUFFER_M1    ((uint32_t)(DMA_SxCR_DBM | DMA_SxCR_CT)) /*!< Double buffer mode with first target memory M1 */
 520 /**
 521   * @}
 522   */
 523
 524 /** @defgroup DMA_Priority_level DMA Priority level
 525   * @brief    DMA priority levels
 526   * @{
 527   */
 528 #define DMA_PRIORITY_LOW             ((uint32_t)0x00000000U)    /*!< Priority level: Low       */
 529 #define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_SxCR_PL_0)  /*!< Priority level: Medium    */
 530 #define DMA_PRIORITY_HIGH            ((uint32_t)DMA_SxCR_PL_1)  /*!< Priority level: High      */
 531 #define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_SxCR_PL)    /*!< Priority level: Very High */
 532 /**
 533   * @}
 534   */
 535
 536 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
 537   * @brief    DMA FIFO direct mode
 538   * @{
 539   */
 540 #define DMA_FIFOMODE_DISABLE        ((uint32_t)0x00000000U)       /*!< FIFO mode disable */
 541 #define DMA_FIFOMODE_ENABLE         ((uint32_t)DMA_SxFCR_DMDIS)  /*!< FIFO mode enable  */
 542 /**
 543   * @}
 544   */
 545
 546 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
 547   * @brief    DMA FIFO level
 548   * @{
 549   */
 550 #define DMA_FIFO_THRESHOLD_1QUARTERFULL       ((uint32_t)0x00000000U)       /*!< FIFO threshold 1 quart full configuration  */
 551 #define DMA_FIFO_THRESHOLD_HALFFULL           ((uint32_t)DMA_SxFCR_FTH_0)  /*!< FIFO threshold half full configuration     */
 552 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL      ((uint32_t)DMA_SxFCR_FTH_1)  /*!< FIFO threshold 3 quarts full configuration */
 553 #define DMA_FIFO_THRESHOLD_FULL               ((uint32_t)DMA_SxFCR_FTH)    /*!< FIFO threshold full configuration          */
 554 /**
 555   * @}
 556   */
 557
 558 /** @defgroup DMA_Memory_burst DMA Memory burst
 559   * @brief    DMA memory burst
 560   * @{
 561   */
 562 #define DMA_MBURST_SINGLE       ((uint32_t)0x00000000U)
 563 #define DMA_MBURST_INC4         ((uint32_t)DMA_SxCR_MBURST_0)
 564 #define DMA_MBURST_INC8         ((uint32_t)DMA_SxCR_MBURST_1)
 565 #define DMA_MBURST_INC16        ((uint32_t)DMA_SxCR_MBURST)
 566 /**
 567   * @}
 568   */
 569
 570 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst
 571   * @brief    DMA peripheral burst
 572   * @{
 573   */
 574 #define DMA_PBURST_SINGLE       ((uint32_t)0x00000000U)
 575 #define DMA_PBURST_INC4         ((uint32_t)DMA_SxCR_PBURST_0)
 576 #define DMA_PBURST_INC8         ((uint32_t)DMA_SxCR_PBURST_1)
 577 #define DMA_PBURST_INC16        ((uint32_t)DMA_SxCR_PBURST)
 578 /**
 579   * @}
 580   */
 581
 582 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
 583   * @brief    DMA interrupts definition
 584   * @{
 585   */
 586 #define DMA_IT_TC                         ((uint32_t)DMA_SxCR_TCIE)
 587 #define DMA_IT_HT                         ((uint32_t)DMA_SxCR_HTIE)
 588 #define DMA_IT_TE                         ((uint32_t)DMA_SxCR_TEIE)
 589 #define DMA_IT_DME                        ((uint32_t)DMA_SxCR_DMEIE)
 590 #define DMA_IT_FE                         ((uint32_t)0x00000080U)
 591 /**
 592   * @}
 593   */
 594
 595 /** @defgroup DMA_flag_definitions DMA flag definitions
 596   * @brief    DMA flag definitions
 597   * @{
 598   */
 599 #define DMA_FLAG_FEIF0_4                    ((uint32_t)0x00000001U)
 600 #define DMA_FLAG_DMEIF0_4                   ((uint32_t)0x00000004U)
 601 #define DMA_FLAG_TEIF0_4                    ((uint32_t)0x00000008U)
 602 #define DMA_FLAG_HTIF0_4                    ((uint32_t)0x00000010U)
 603 #define DMA_FLAG_TCIF0_4                    ((uint32_t)0x00000020U)
 604 #define DMA_FLAG_FEIF1_5                    ((uint32_t)0x00000040U)
 605 #define DMA_FLAG_DMEIF1_5                   ((uint32_t)0x00000100U)
 606 #define DMA_FLAG_TEIF1_5                    ((uint32_t)0x00000200U)
 607 #define DMA_FLAG_HTIF1_5                    ((uint32_t)0x00000400U)
 608 #define DMA_FLAG_TCIF1_5                    ((uint32_t)0x00000800U)
 609 #define DMA_FLAG_FEIF2_6                    ((uint32_t)0x00010000U)
 610 #define DMA_FLAG_DMEIF2_6                   ((uint32_t)0x00040000U)
 611 #define DMA_FLAG_TEIF2_6                    ((uint32_t)0x00080000U)
 612 #define DMA_FLAG_HTIF2_6                    ((uint32_t)0x00100000U)
 613 #define DMA_FLAG_TCIF2_6                    ((uint32_t)0x00200000U)
 614 #define DMA_FLAG_FEIF3_7                    ((uint32_t)0x00400000U)
 615 #define DMA_FLAG_DMEIF3_7                   ((uint32_t)0x01000000U)
 616 #define DMA_FLAG_TEIF3_7                    ((uint32_t)0x02000000U)
 617 #define DMA_FLAG_HTIF3_7                    ((uint32_t)0x04000000U)
 618 #define DMA_FLAG_TCIF3_7                    ((uint32_t)0x08000000U)
 619 /**
 620   * @}
 621   */
 622
 623 /** @defgroup BDMA_flag_definitions BDMA flag definitions
 624   * @brief    BDMA flag definitions
 625   * @{
 626   */
 627 #define BDMA_FLAG_GL0                      ((uint32_t)0x00000001)
 628 #define BDMA_FLAG_TC0                      ((uint32_t)0x00000002)
 629 #define BDMA_FLAG_HT0                      ((uint32_t)0x00000004)
 630 #define BDMA_FLAG_TE0                      ((uint32_t)0x00000008)
 631 #define BDMA_FLAG_GL1                      ((uint32_t)0x00000010)
 632 #define BDMA_FLAG_TC1                      ((uint32_t)0x00000020)
 633 #define BDMA_FLAG_HT1                      ((uint32_t)0x00000040)
 634 #define BDMA_FLAG_TE1                      ((uint32_t)0x00000080)
 635 #define BDMA_FLAG_GL2                      ((uint32_t)0x00000100)
 636 #define BDMA_FLAG_TC2                      ((uint32_t)0x00000200)
 637 #define BDMA_FLAG_HT2                      ((uint32_t)0x00000400)
 638 #define BDMA_FLAG_TE2                      ((uint32_t)0x00000800)
 639 #define BDMA_FLAG_GL3                      ((uint32_t)0x00001000)
 640 #define BDMA_FLAG_TC3                      ((uint32_t)0x00002000)
 641 #define BDMA_FLAG_HT3                      ((uint32_t)0x00004000)
 642 #define BDMA_FLAG_TE3                      ((uint32_t)0x00008000)
 643 #define BDMA_FLAG_GL4                      ((uint32_t)0x00010000)
 644 #define BDMA_FLAG_TC4                      ((uint32_t)0x00020000)
 645 #define BDMA_FLAG_HT4                      ((uint32_t)0x00040000)
 646 #define BDMA_FLAG_TE4                      ((uint32_t)0x00080000)
 647 #define BDMA_FLAG_GL5                      ((uint32_t)0x00100000)
 648 #define BDMA_FLAG_TC5                      ((uint32_t)0x00200000)
 649 #define BDMA_FLAG_HT5                      ((uint32_t)0x00400000)
 650 #define BDMA_FLAG_TE5                      ((uint32_t)0x00800000)
 651 #define BDMA_FLAG_GL6                      ((uint32_t)0x01000000)
 652 #define BDMA_FLAG_TC6                      ((uint32_t)0x02000000)
 653 #define BDMA_FLAG_HT6                      ((uint32_t)0x04000000)
 654 #define BDMA_FLAG_TE6                      ((uint32_t)0x08000000)
 655 #define BDMA_FLAG_GL7                      ((uint32_t)0x10000000)
 656 #define BDMA_FLAG_TC7                      ((uint32_t)0x20000000)
 657 #define BDMA_FLAG_HT7                      ((uint32_t)0x40000000)
 658 #define BDMA_FLAG_TE7                      ((uint32_t)0x80000000)
 659
 660 /**
 661   * @}
 662   */
 663
 664 /**
 665   * @}
 666   */
 667
 668 /* Exported macro ------------------------------------------------------------*/
 669 /** @defgroup DMA_Exported_Macros DMA Exported Macros
 670   * @{
 671   */
 672
 673 /** @brief Reset DMA handle state
 674   * @param  __HANDLE__: specifies the DMA handle.
 675   * @retval None
 676   */
 677 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
 678
 679 /**
 680   * @brief  Return the current DMA Stream FIFO filled level.
 681   * @param  __HANDLE__: DMA handle
 682   * @retval The FIFO filling state.
 683   *           - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
 684   *                                              and not empty.
 685   *           - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
 686   *           - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
 687   *           - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
 688   *           - DMA_FIFOStatus_Empty: when FIFO is empty
 689   *           - DMA_FIFOStatus_Full: when FIFO is full
 690   */
 691 #define __HAL_DMA_GET_FS(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (DMA_SxFCR_FS)) : 0)
 692
 693 /**
 694   * @brief  Enable the specified DMA Stream.
 695   * @param  __HANDLE__: DMA handle
 696   * @retval None
 697   */
 698 #define __HAL_DMA_ENABLE(__HANDLE__) \
 699 ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |=  DMA_SxCR_EN) : \
 700 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |=  BDMA_CCR_EN))
 701
 702 /**
 703   * @brief  Disable the specified DMA Stream.
 704   * @param  __HANDLE__: DMA handle
 705   * @retval None
 706   */
 707 #define __HAL_DMA_DISABLE(__HANDLE__) \
 708 ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &=  ~DMA_SxCR_EN) : \
 709 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &=  ~BDMA_CCR_EN))
 710
 711 /* Interrupt & Flag management */
 712
 713 /**
 714   * @brief  Return the current DMA Stream transfer complete flag.
 715   * @param  __HANDLE__: DMA handle
 716   * @retval The specified transfer complete flag index.
 717   */
 718 #if defined(BDMA1)
 719 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
 720 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
 721  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
 722  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
 723  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
 724  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
 725  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
 726  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
 727  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
 728  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
 729  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
 730  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
 731  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
 732  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\
 733  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\
 734  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\
 735  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\
 736  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TC0  :\
 737  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TC0  :\
 738  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TC1  :\
 739  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TC1  :\
 740  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TC2  :\
 741  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TC2  :\
 742  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TC3  :\
 743  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TC3  :\
 744  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TC4  :\
 745  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TC4  :\
 746  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TC5  :\
 747  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TC5  :\
 748  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TC6  :\
 749  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TC6  :\
 750  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TC7  :\
 751  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TC7  :\
 752  (uint32_t)0x00000000)
 753 #else
 754 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
 755 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
 756  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
 757  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
 758  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
 759  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
 760  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
 761  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
 762  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
 763  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
 764  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
 765  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
 766  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
 767  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\
 768  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\
 769  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\
 770  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\
 771  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TC0   :\
 772  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TC1   :\
 773  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TC2   :\
 774  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TC3   :\
 775  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TC4   :\
 776  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TC5   :\
 777  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TC6   :\
 778  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TC7   :\
 779  (uint32_t)0x00000000)
 780 #endif /* BDMA1 */
 781
 782 /**
 783   * @brief  Return the current DMA Stream half transfer complete flag.
 784   * @param  __HANDLE__: DMA handle
 785   * @retval The specified half transfer complete flag index.
 786   */
 787 #if defined(BDMA1)
 788 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
 789 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
 790  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
 791  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
 792  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
 793  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
 794  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
 795  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
 796  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
 797  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
 798  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
 799  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
 800  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
 801  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\
 802  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\
 803  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\
 804  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\
 805  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_HT0  :\
 806  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_HT0  :\
 807  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_HT1  :\
 808  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_HT1  :\
 809  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_HT2  :\
 810  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_HT2  :\
 811  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_HT3  :\
 812  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_HT3  :\
 813  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_HT4  :\
 814  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_HT4  :\
 815  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_HT5  :\
 816  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_HT5  :\
 817  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_HT6  :\
 818  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_HT6  :\
 819  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_HT7  :\
 820  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_HT7  :\
 821  (uint32_t)0x00000000)
 822 #else
 823 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
 824 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
 825  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
 826  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
 827  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
 828  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
 829  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
 830  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
 831  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
 832  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
 833  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
 834  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
 835  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
 836  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\
 837  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\
 838  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\
 839  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\
 840  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_HT0   :\
 841  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_HT1   :\
 842  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_HT2   :\
 843  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_HT3   :\
 844  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_HT4   :\
 845  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_HT5   :\
 846  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_HT6   :\
 847  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_HT7   :\
 848  (uint32_t)0x00000000)
 849 #endif /* BDMA1 */
 850
 851 /**
 852   * @brief  Return the current DMA Stream transfer error flag.
 853   * @param  __HANDLE__: DMA handle
 854   * @retval The specified transfer error flag index.
 855   */
 856 #if defined(BDMA1)
 857 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
 858 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
 859  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
 860  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
 861  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
 862  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
 863  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
 864  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
 865  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
 866  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
 867  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
 868  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
 869  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
 870  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\
 871  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\
 872  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\
 873  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\
 874  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TE0  :\
 875  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TE0  :\
 876  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TE1  :\
 877  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TE1  :\
 878  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TE2  :\
 879  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TE2  :\
 880  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TE3  :\
 881  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TE3  :\
 882  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TE4  :\
 883  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TE4  :\
 884  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TE5  :\
 885  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TE5  :\
 886  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TE6  :\
 887  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TE6  :\
 888  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TE7  :\
 889  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TE7  :\
 890  (uint32_t)0x00000000)
 891 #else
 892 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
 893 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
 894  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
 895  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
 896  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
 897  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
 898  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
 899  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
 900  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
 901  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
 902  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
 903  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
 904  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
 905  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\
 906  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\
 907  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\
 908  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\
 909  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TE0   :\
 910  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TE1   :\
 911  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TE2   :\
 912  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TE3   :\
 913  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TE4   :\
 914  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TE5   :\
 915  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TE6   :\
 916  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TE7   :\
 917  (uint32_t)0x00000000)
 918 #endif /* BDMA1 */
 919
 920 /**
 921   * @brief  Return the current DMA Stream FIFO error flag.
 922   * @param  __HANDLE__: DMA handle
 923   * @retval The specified FIFO error flag index.
 924   */
 925 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
 926 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
 927  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
 928  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
 929  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
 930  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
 931  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
 932  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
 933  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
 934  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
 935  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
 936  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
 937  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
 938  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_FEIF3_7 :\
 939  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_FEIF3_7 :\
 940  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_FEIF3_7 :\
 941  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_FEIF3_7 :\
 942   (uint32_t)0x00000000)
 943
 944 /**
 945   * @brief  Return the current DMA Stream direct mode error flag.
 946   * @param  __HANDLE__: DMA handle
 947   * @retval The specified direct mode error flag index.
 948   */
 949 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
 950 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
 951  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
 952  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
 953  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
 954  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
 955  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
 956  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
 957  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
 958  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
 959  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
 960  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
 961  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
 962  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_DMEIF3_7 :\
 963  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_DMEIF3_7 :\
 964  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_DMEIF3_7 :\
 965  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_DMEIF3_7 :\
 966   (uint32_t)0x00000000)
 967
 968 /**
 969   * @brief  Returns the current BDMA Channel Global interrupt flag.
 970   * @param  __HANDLE__: DMA handle
 971   * @retval The specified transfer error flag index.
 972   */
 973 #if defined(BDMA1)
 974 #define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\
 975 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_ISR_GIF0 :\
 976  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_ISR_GIF0 :\
 977  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_ISR_GIF1 :\
 978  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_ISR_GIF1 :\
 979  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_ISR_GIF2 :\
 980  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_ISR_GIF2 :\
 981  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_ISR_GIF3 :\
 982  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_ISR_GIF3 :\
 983  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_ISR_GIF4 :\
 984  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_ISR_GIF4 :\
 985  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_ISR_GIF5 :\
 986  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_ISR_GIF5 :\
 987  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_ISR_GIF6 :\
 988  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_ISR_GIF6 :\
 989  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_ISR_GIF7 :\
 990  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_ISR_GIF7 :\
 991  (uint32_t)0x00000000)
 992 #else
 993 #define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\
 994 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_ISR_GIF0 :\
 995  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_ISR_GIF1 :\
 996  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_ISR_GIF2 :\
 997  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_ISR_GIF3 :\
 998  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_ISR_GIF4 :\
 999  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_ISR_GIF5 :\
1000  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_ISR_GIF6 :\
1001  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_ISR_GIF7 :\
1002   (uint32_t)0x00000000)
1003 #endif /* BDMA1 */
1004
1005 /**
1006   * @brief  Get the DMA Stream pending flags.
1007   * @param  __HANDLE__: DMA handle
1008   * @param  __FLAG__: Get the specified flag.
1009   *          This parameter can be any combination of the following values:
1010   *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
1011   *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
1012   *            @arg DMA_FLAG_TEIFx: Transfer error flag.
1013   *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
1014   *            @arg DMA_FLAG_FEIFx: FIFO error flag.
1015   *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
1016   * @retval The state of FLAG (SET or RESET).
1017   */
1018 #if defined(BDMA1)
1019 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
1020 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)?  (BDMA2->ISR & (__FLAG__)) :\
1021  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7  )?  (BDMA1->ISR & (__FLAG__)) :\
1022  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3  )?  (DMA2->HISR & (__FLAG__)) :\
1023  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7  )?  (DMA2->LISR & (__FLAG__)) :\
1024  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3  )?  (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
1025 #else
1026 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
1027 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->ISR & (__FLAG__))  :\
1028  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
1029  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
1030  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
1031 #endif /* BDMA1 */
1032
1033 /**
1034   * @brief  Clear the DMA Stream pending flags.
1035   * @param  __HANDLE__: DMA handle
1036   * @param  __FLAG__: specifies the flag to clear.
1037   *          This parameter can be any combination of the following values:
1038   *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
1039   *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
1040   *            @arg DMA_FLAG_TEIFx: Transfer error flag.
1041   *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
1042   *            @arg DMA_FLAG_FEIFx: FIFO error flag.
1043   *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
1044   * @retval None
1045   */
1046 #if defined(BDMA1)
1047 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
1048 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)? (BDMA2->IFCR = (__FLAG__)) :\
1049  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)?  (BDMA1->IFCR = (__FLAG__)) :\
1050  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)?  (DMA2->HIFCR = (__FLAG__)) :\
1051  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)?  (DMA2->LIFCR = (__FLAG__)) :\
1052  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)?  (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
1053 #else
1054 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
1055 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->IFCR = (__FLAG__))  :\
1056  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
1057  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
1058  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
1059 #endif /* BDMA1 */
1060
1061 #define DMA_TO_BDMA_IT(__DMA_IT__) \
1062 ((((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\
1063  (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT)) == (DMA_IT_TC | DMA_IT_HT)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE) :\
1064  (((__DMA_IT__) & (DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_HTIE |BDMA_CCR_TEIE)  :\
1065  (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_TE)) ? (BDMA_CCR_TCIE |BDMA_CCR_TEIE)  :\
1066  ((__DMA_IT__) == DMA_IT_TC) ? BDMA_CCR_TCIE :\
1067  ((__DMA_IT__) == DMA_IT_HT) ? BDMA_CCR_HTIE :\
1068  ((__DMA_IT__) == DMA_IT_TE) ? BDMA_CCR_TEIE :\
1069  (uint32_t)0x00000000)
1070
1071
1072 #define __HAL_BDMA_CHANNEL_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
1073 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= (DMA_TO_BDMA_IT(__INTERRUPT__)))
1074
1075 #define __HAL_DMA_STREAM_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((__INTERRUPT__) != DMA_IT_FE)? \
1076 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= (__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR |= (__INTERRUPT__)))
1077
1078 /**
1079   * @brief  Enable the specified DMA Stream interrupts.
1080   * @param  __HANDLE__: DMA handle
1081   * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
1082   *        This parameter can be one of the following values:
1083   *           @arg DMA_IT_TC: Transfer complete interrupt mask.
1084   *           @arg DMA_IT_HT: Half transfer complete interrupt mask.
1085   *           @arg DMA_IT_TE: Transfer error interrupt mask.
1086   *           @arg DMA_IT_FE: FIFO error interrupt mask.
1087   *           @arg DMA_IT_DME: Direct mode error interrupt.
1088   * @retval None
1089   */
1090 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\
1091                                                         (__HAL_DMA_STREAM_ENABLE_IT((__HANDLE__), (__INTERRUPT__))) :\
1092                                                         (__HAL_BDMA_CHANNEL_ENABLE_IT((__HANDLE__), (__INTERRUPT__))))
1093
1094
1095 #define __HAL_BDMA_CHANNEL_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~(DMA_TO_BDMA_IT(__INTERRUPT__)))
1096
1097 #define __HAL_DMA_STREAM_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
1098 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~(__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR &= ~(__INTERRUPT__)))
1099
1100 /**
1101   * @brief  Disable the specified DMA Stream interrupts.
1102   * @param  __HANDLE__: DMA handle
1103   * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
1104   *         This parameter can be one of the following values:
1105   *            @arg DMA_IT_TC: Transfer complete interrupt mask.
1106   *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
1107   *            @arg DMA_IT_TE: Transfer error interrupt mask.
1108   *            @arg DMA_IT_FE: FIFO error interrupt mask.
1109   *            @arg DMA_IT_DME: Direct mode error interrupt.
1110   * @retval None
1111   */
1112 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\
1113                                                          (__HAL_DMA_STREAM_DISABLE_IT((__HANDLE__), (__INTERRUPT__))) :\
1114                                                          (__HAL_BDMA_CHANNEL_DISABLE_IT((__HANDLE__), (__INTERRUPT__))))
1115
1116
1117 #define __HAL_BDMA_CHANNEL_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  ((((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR & (DMA_TO_BDMA_IT(__INTERRUPT__))))
1118
1119 #define __HAL_DMA_STREAM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
1120                                                         (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR & (__INTERRUPT__)) : \
1121                                                         (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (__INTERRUPT__)))
1122
1123 /**
1124   * @brief  Check whether the specified DMA Stream interrupt is enabled or not.
1125   * @param  __HANDLE__: DMA handle
1126   * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
1127   *         This parameter can be one of the following values:
1128   *            @arg DMA_IT_TC: Transfer complete interrupt mask.
1129   *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
1130   *            @arg DMA_IT_TE: Transfer error interrupt mask.
1131   *            @arg DMA_IT_FE: FIFO error interrupt mask.
1132   *            @arg DMA_IT_DME: Direct mode error interrupt.
1133   * @retval The state of DMA_IT.
1134   */
1135 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
1136                                                             (__HAL_DMA_STREAM_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))) :\
1137                                                             (__HAL_BDMA_CHANNEL_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))))
1138
1139 /**
1140   * @brief  Writes the number of data units to be transferred on the DMA Stream.
1141   * @param  __HANDLE__: DMA handle
1142   * @param  __COUNTER__: Number of data units to be transferred (from 0 to 65535)
1143   *          Number of data items depends only on the Peripheral data format.
1144   *
1145   * @note   If Peripheral data format is Bytes: number of data units is equal
1146   *         to total number of bytes to be transferred.
1147   *
1148   * @note   If Peripheral data format is Half-Word: number of data units is
1149   *         equal to total number of bytes to be transferred / 2.
1150   *
1151   * @note   If Peripheral data format is Word: number of data units is equal
1152   *         to total  number of bytes to be transferred / 4.
1153   *
1154   * @retval The number of remaining data units in the current DMAy Streamx transfer.
1155   */
1156 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
1157                                                         (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR = (uint16_t)(__COUNTER__)) :\
1158                                                         (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR = (uint16_t)(__COUNTER__)))
1159
1160 /**
1161   * @brief  Returns the number of remaining data units in the current DMAy Streamx transfer.
1162   * @param  __HANDLE__: DMA handle
1163   *
1164   * @retval The number of remaining data units in the current DMA Stream transfer.
1165   */
1166 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
1167                                            (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR) :\
1168                                            (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR))
1169
1170 /**
1171   * @}
1172   */
1173
1174 /* Include DMA HAL Extension module */
1175 #include "stm32h7xx_hal_dma_ex.h"
1176
1177 /* Exported functions --------------------------------------------------------*/
1178
1179 /** @defgroup DMA_Exported_Functions DMA Exported Functions
1180   * @brief    DMA Exported functions
1181   * @{
1182   */
1183
1184 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
1185   * @brief   Initialization and de-initialization functions
1186   * @{
1187   */
1188 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
1189 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
1190 /**
1191   * @}
1192   */
1193
1194 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
1195   * @brief   I/O operation functions
1196   * @{
1197   */
1198 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
1199 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
1200 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
1201 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
1202 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
1203 void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
1204 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
1205 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
1206
1207 /**
1208   * @}
1209   */
1210
1211 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
1212   * @brief    Peripheral State functions
1213   * @{
1214   */
1215 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
1216 uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
1217 /**
1218   * @}
1219   */
1220 /**
1221   * @}
1222   */
1223 /* Private Constants -------------------------------------------------------------*/
1224 /** @defgroup DMA_Private_Constants DMA Private Constants
1225   * @brief    DMA private defines and constants
1226   * @{
1227   */
1228 /**
1229   * @}
1230   */
1231
1232 /* Private macros ------------------------------------------------------------*/
1233 /** @defgroup DMA_Private_Macros DMA Private Macros
1234   * @brief    DMA private macros
1235   * @{
1236   */
1237
1238 #if defined(TIM24)
1239 #define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_TIM24_TRIG))
1240 #elif defined(ADC3)
1241 #define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_ADC3))
1242 #else
1243 #define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_USART10_TX))
1244 #endif /* TIM24 */
1245
1246 #if defined(ADC3)
1247 #define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_ADC3))
1248 #else
1249 #define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_DFSDM2_FLT0))
1250 #endif /* ADC3 */
1251
1252 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
1253                                      ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
1254                                      ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
1255
1256 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
1257
1258 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
1259                                             ((STATE) == DMA_PINC_DISABLE))
1260
1261 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
1262                                         ((STATE) == DMA_MINC_DISABLE))
1263
1264 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
1265                                            ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
1266                                            ((SIZE) == DMA_PDATAALIGN_WORD))
1267
1268 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
1269                                        ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
1270                                        ((SIZE) == DMA_MDATAALIGN_WORD ))
1271
1272 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )           || \
1273                            ((MODE) == DMA_CIRCULAR)          || \
1274                            ((MODE) == DMA_PFCTRL)            || \
1275                            ((MODE) == DMA_DOUBLE_BUFFER_M0)  || \
1276                            ((MODE) == DMA_DOUBLE_BUFFER_M1))
1277
1278 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
1279                                    ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
1280                                    ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
1281                                    ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
1282
1283 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
1284                                        ((STATE) == DMA_FIFOMODE_ENABLE))
1285
1286 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
1287                                           ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL)      || \
1288                                           ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
1289                                           ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
1290
1291 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
1292                                     ((BURST) == DMA_MBURST_INC4)   || \
1293                                     ((BURST) == DMA_MBURST_INC8)   || \
1294                                     ((BURST) == DMA_MBURST_INC16))
1295
1296 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
1297                                         ((BURST) == DMA_PBURST_INC4)   || \
1298                                         ((BURST) == DMA_PBURST_INC8)   || \
1299                                         ((BURST) == DMA_PBURST_INC16))
1300 /**
1301   * @}
1302   */
1303
1304 /* Private functions ---------------------------------------------------------*/
1305 /** @defgroup DMA_Private_Functions DMA Private Functions
1306   * @brief    DMA private  functions
1307   * @{
1308   */
1309 /**
1310   * @}
1311   */
1312
1313 /**
1314   * @}
1315   */
1316
1317 /**
1318   * @}
1319   */
1320
1321 #ifdef __cplusplus
1322 }
1323 #endif
1324
1325 #endif /* STM32H7xx_HAL_DMA_H */
1326
1327 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/