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Merge pull request #11270 from haslinghuis/rename_attr
[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_hal_dsi.h
bloba3894ec4e393aceb1006d4fcf30aad445795a88f
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal_dsi.h
4 * @author MCD Application Team
5 * @brief Header file of DSI HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_HAL_DSI_H
22 #define STM32H7xx_HAL_DSI_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 #if defined(DSI)
29 /* Includes ------------------------------------------------------------------*/
30 #include "stm32h7xx_hal_def.h"
31
32 /** @addtogroup STM32H7xx_HAL_Driver
33 * @{
34 */
35
36 /** @defgroup DSI DSI
37 * @brief DSI HAL module driver
38 * @{
39 */
40
41 /* Exported types ------------------------------------------------------------*/
42 /**
43 * @brief DSI Init Structure definition
44 */
45 typedef struct
46 {
47 uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control
48 This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */
49
50 uint32_t TXEscapeCkdiv; /*!< TX Escape clock division
51 The values 0 and 1 stop the TX_ESC clock generation */
52
53 uint32_t NumberOfLanes; /*!< Number of lanes
54 This parameter can be any value of @ref DSI_Number_Of_Lanes */
55
56 } DSI_InitTypeDef;
57
58 /**
59 * @brief DSI PLL Clock structure definition
60 */
61 typedef struct
62 {
63 uint32_t PLLNDIV; /*!< PLL Loop Division Factor
64 This parameter must be a value between 10 and 125 */
65
66 uint32_t PLLIDF; /*!< PLL Input Division Factor
67 This parameter can be any value of @ref DSI_PLL_IDF */
68
69 uint32_t PLLODF; /*!< PLL Output Division Factor
70 This parameter can be any value of @ref DSI_PLL_ODF */
71
72 } DSI_PLLInitTypeDef;
73
74 /**
75 * @brief DSI Video mode configuration
76 */
77 typedef struct
78 {
79 uint32_t VirtualChannelID; /*!< Virtual channel ID */
80
81 uint32_t ColorCoding; /*!< Color coding for LTDC interface
82 This parameter can be any value of @ref DSI_Color_Coding */
83
84 uint32_t LooselyPacked; /*!< Enable or disable loosely packed stream (needed only when using
85 18-bit configuration).
86 This parameter can be any value of @ref DSI_LooselyPacked */
87
88 uint32_t Mode; /*!< Video mode type
89 This parameter can be any value of @ref DSI_Video_Mode_Type */
90
91 uint32_t PacketSize; /*!< Video packet size */
92
93 uint32_t NumberOfChunks; /*!< Number of chunks */
94
95 uint32_t NullPacketSize; /*!< Null packet size */
96
97 uint32_t HSPolarity; /*!< HSYNC pin polarity
98 This parameter can be any value of @ref DSI_HSYNC_Polarity */
99
100 uint32_t VSPolarity; /*!< VSYNC pin polarity
101 This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */
102
103 uint32_t DEPolarity; /*!< Data Enable pin polarity
104 This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
105
106 uint32_t HorizontalSyncActive; /*!< Horizontal synchronism active duration (in lane byte clock cycles) */
107
108 uint32_t HorizontalBackPorch; /*!< Horizontal back-porch duration (in lane byte clock cycles) */
109
110 uint32_t HorizontalLine; /*!< Horizontal line duration (in lane byte clock cycles) */
111
112 uint32_t VerticalSyncActive; /*!< Vertical synchronism active duration */
113
114 uint32_t VerticalBackPorch; /*!< Vertical back-porch duration */
115
116 uint32_t VerticalFrontPorch; /*!< Vertical front-porch duration */
117
118 uint32_t VerticalActive; /*!< Vertical active duration */
119
120 uint32_t LPCommandEnable; /*!< Low-power command enable
121 This parameter can be any value of @ref DSI_LP_Command */
122
123 uint32_t LPLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that
124 can fit in a line during VSA, VBP and VFP regions */
125
126 uint32_t LPVACTLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that
127 can fit in a line during VACT region */
128
129 uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable
130 This parameter can be any value of @ref DSI_LP_HFP */
131
132 uint32_t LPHorizontalBackPorchEnable; /*!< Low-power horizontal back-porch enable
133 This parameter can be any value of @ref DSI_LP_HBP */
134
135 uint32_t LPVerticalActiveEnable; /*!< Low-power vertical active enable
136 This parameter can be any value of @ref DSI_LP_VACT */
137
138 uint32_t LPVerticalFrontPorchEnable; /*!< Low-power vertical front-porch enable
139 This parameter can be any value of @ref DSI_LP_VFP */
140
141 uint32_t LPVerticalBackPorchEnable; /*!< Low-power vertical back-porch enable
142 This parameter can be any value of @ref DSI_LP_VBP */
143
144 uint32_t LPVerticalSyncActiveEnable; /*!< Low-power vertical sync active enable
145 This parameter can be any value of @ref DSI_LP_VSYNC */
146
147 uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable
148 This parameter can be any value of @ref DSI_FBTA_acknowledge */
149
150 } DSI_VidCfgTypeDef;
151
152 /**
153 * @brief DSI Adapted command mode configuration
154 */
155 typedef struct
156 {
157 uint32_t VirtualChannelID; /*!< Virtual channel ID */
158
159 uint32_t ColorCoding; /*!< Color coding for LTDC interface
160 This parameter can be any value of @ref DSI_Color_Coding */
161
162 uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in
163 pixels. This parameter can be any value between 0x00 and 0xFFFFU */
164
165 uint32_t TearingEffectSource; /*!< Tearing effect source
166 This parameter can be any value of @ref DSI_TearingEffectSource */
167
168 uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity
169 This parameter can be any value of @ref DSI_TearingEffectPolarity */
170
171 uint32_t HSPolarity; /*!< HSYNC pin polarity
172 This parameter can be any value of @ref DSI_HSYNC_Polarity */
173
174 uint32_t VSPolarity; /*!< VSYNC pin polarity
175 This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */
176
177 uint32_t DEPolarity; /*!< Data Enable pin polarity
178 This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
179
180 uint32_t VSyncPol; /*!< VSync edge on which the LTDC is halted
181 This parameter can be any value of @ref DSI_Vsync_Polarity */
182
183 uint32_t AutomaticRefresh; /*!< Automatic refresh mode
184 This parameter can be any value of @ref DSI_AutomaticRefresh */
185
186 uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable
187 This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */
188
189 } DSI_CmdCfgTypeDef;
190
191 /**
192 * @brief DSI command transmission mode configuration
193 */
194 typedef struct
195 {
196 uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission
197 This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */
198
199 uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission
200 This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */
201
202 uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission
203 This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */
204
205 uint32_t LPGenShortReadNoP; /*!< Generic Short Read Zero parameters Transmission
206 This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP */
207
208 uint32_t LPGenShortReadOneP; /*!< Generic Short Read One parameter Transmission
209 This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP */
210
211 uint32_t LPGenShortReadTwoP; /*!< Generic Short Read Two parameters Transmission
212 This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP */
213
214 uint32_t LPGenLongWrite; /*!< Generic Long Write Transmission
215 This parameter can be any value of @ref DSI_LP_LPGenLongWrite */
216
217 uint32_t LPDcsShortWriteNoP; /*!< DCS Short Write Zero parameters Transmission
218 This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP */
219
220 uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission
221 This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */
222
223 uint32_t LPDcsShortReadNoP; /*!< DCS Short Read Zero parameters Transmission
224 This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP */
225
226 uint32_t LPDcsLongWrite; /*!< DCS Long Write Transmission
227 This parameter can be any value of @ref DSI_LP_LPDcsLongWrite */
228
229 uint32_t LPMaxReadPacket; /*!< Maximum Read Packet Size Transmission
230 This parameter can be any value of @ref DSI_LP_LPMaxReadPacket */
231
232 uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable
233 This parameter can be any value of @ref DSI_AcknowledgeRequest */
234
235 } DSI_LPCmdTypeDef;
236
237 /**
238 * @brief DSI PHY Timings definition
239 */
240 typedef struct
241 {
242 uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed
243 to low-power transmission */
244
245 uint32_t ClockLaneLP2HSTime; /*!< The maximum time that the D-PHY clock lane takes to go from low-power
246 to high-speed transmission */
247
248 uint32_t DataLaneHS2LPTime; /*!< The maximum time that the D-PHY data lanes takes to go from high-speed
249 to low-power transmission */
250
251 uint32_t DataLaneLP2HSTime; /*!< The maximum time that the D-PHY data lanes takes to go from low-power
252 to high-speed transmission */
253
254 uint32_t DataLaneMaxReadTime; /*!< The maximum time required to perform a read command */
255
256 uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the
257 Stop state */
258
259 } DSI_PHY_TimerTypeDef;
260
261 /**
262 * @brief DSI HOST Timeouts definition
263 */
264 typedef struct
265 {
266 uint32_t TimeoutCkdiv; /*!< Time-out clock division */
267
268 uint32_t HighSpeedTransmissionTimeout; /*!< High-speed transmission time-out */
269
270 uint32_t LowPowerReceptionTimeout; /*!< Low-power reception time-out */
271
272 uint32_t HighSpeedReadTimeout; /*!< High-speed read time-out */
273
274 uint32_t LowPowerReadTimeout; /*!< Low-power read time-out */
275
276 uint32_t HighSpeedWriteTimeout; /*!< High-speed write time-out */
277
278 uint32_t HighSpeedWritePrespMode; /*!< High-speed write presp mode
279 This parameter can be any value of @ref DSI_HS_PrespMode */
280
281 uint32_t LowPowerWriteTimeout; /*!< Low-speed write time-out */
282
283 uint32_t BTATimeout; /*!< BTA time-out */
284
285 } DSI_HOST_TimeoutTypeDef;
286
287 /**
288 * @brief DSI States Structure definition
289 */
290 typedef enum
291 {
292 HAL_DSI_STATE_RESET = 0x00U,
293 HAL_DSI_STATE_READY = 0x01U,
294 HAL_DSI_STATE_ERROR = 0x02U,
295 HAL_DSI_STATE_BUSY = 0x03U,
296 HAL_DSI_STATE_TIMEOUT = 0x04U
297 } HAL_DSI_StateTypeDef;
298
299 /**
300 * @brief DSI Handle Structure definition
301 */
302 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
303 typedef struct __DSI_HandleTypeDef
304 #else
305 typedef struct
306 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
307 {
308 DSI_TypeDef *Instance; /*!< Register base address */
309 DSI_InitTypeDef Init; /*!< DSI required parameters */
310 HAL_LockTypeDef Lock; /*!< DSI peripheral status */
311 __IO HAL_DSI_StateTypeDef State; /*!< DSI communication state */
312 __IO uint32_t ErrorCode; /*!< DSI Error code */
313 uint32_t ErrorMsk; /*!< DSI Error monitoring mask */
314
315 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
316 void (* TearingEffectCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Tearing Effect Callback */
317 void (* EndOfRefreshCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI End Of Refresh Callback */
318 void (* ErrorCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Error Callback */
319
320 void (* MspInitCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp Init callback */
321 void (* MspDeInitCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp DeInit callback */
322
323 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
324
325 } DSI_HandleTypeDef;
326
327 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
328 /**
329 * @brief HAL DSI Callback ID enumeration definition
330 */
331 typedef enum
332 {
333 HAL_DSI_MSPINIT_CB_ID = 0x00U, /*!< DSI MspInit callback ID */
334 HAL_DSI_MSPDEINIT_CB_ID = 0x01U, /*!< DSI MspDeInit callback ID */
335
336 HAL_DSI_TEARING_EFFECT_CB_ID = 0x02U, /*!< DSI Tearing Effect Callback ID */
337 HAL_DSI_ENDOF_REFRESH_CB_ID = 0x03U, /*!< DSI End Of Refresh Callback ID */
338 HAL_DSI_ERROR_CB_ID = 0x04U /*!< DSI Error Callback ID */
339
340 } HAL_DSI_CallbackIDTypeDef;
341
342 /**
343 * @brief HAL DSI Callback pointer definition
344 */
345 typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to an DSI callback function */
346
347 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
348
349 /* Exported constants --------------------------------------------------------*/
350 /** @defgroup DSI_Exported_Constants DSI Exported Constants
351 * @{
352 */
353 /** @defgroup DSI_DCS_Command DSI DCS Command
354 * @{
355 */
356 #define DSI_ENTER_IDLE_MODE 0x39U
357 #define DSI_ENTER_INVERT_MODE 0x21U
358 #define DSI_ENTER_NORMAL_MODE 0x13U
359 #define DSI_ENTER_PARTIAL_MODE 0x12U
360 #define DSI_ENTER_SLEEP_MODE 0x10U
361 #define DSI_EXIT_IDLE_MODE 0x38U
362 #define DSI_EXIT_INVERT_MODE 0x20U
363 #define DSI_EXIT_SLEEP_MODE 0x11U
364 #define DSI_GET_3D_CONTROL 0x3FU
365 #define DSI_GET_ADDRESS_MODE 0x0BU
366 #define DSI_GET_BLUE_CHANNEL 0x08U
367 #define DSI_GET_DIAGNOSTIC_RESULT 0x0FU
368 #define DSI_GET_DISPLAY_MODE 0x0DU
369 #define DSI_GET_GREEN_CHANNEL 0x07U
370 #define DSI_GET_PIXEL_FORMAT 0x0CU
371 #define DSI_GET_POWER_MODE 0x0AU
372 #define DSI_GET_RED_CHANNEL 0x06U
373 #define DSI_GET_SCANLINE 0x45U
374 #define DSI_GET_SIGNAL_MODE 0x0EU
375 #define DSI_NOP 0x00U
376 #define DSI_READ_DDB_CONTINUE 0xA8U
377 #define DSI_READ_DDB_START 0xA1U
378 #define DSI_READ_MEMORY_CONTINUE 0x3EU
379 #define DSI_READ_MEMORY_START 0x2EU
380 #define DSI_SET_3D_CONTROL 0x3DU
381 #define DSI_SET_ADDRESS_MODE 0x36U
382 #define DSI_SET_COLUMN_ADDRESS 0x2AU
383 #define DSI_SET_DISPLAY_OFF 0x28U
384 #define DSI_SET_DISPLAY_ON 0x29U
385 #define DSI_SET_GAMMA_CURVE 0x26U
386 #define DSI_SET_PAGE_ADDRESS 0x2BU
387 #define DSI_SET_PARTIAL_COLUMNS 0x31U
388 #define DSI_SET_PARTIAL_ROWS 0x30U
389 #define DSI_SET_PIXEL_FORMAT 0x3AU
390 #define DSI_SET_SCROLL_AREA 0x33U
391 #define DSI_SET_SCROLL_START 0x37U
392 #define DSI_SET_TEAR_OFF 0x34U
393 #define DSI_SET_TEAR_ON 0x35U
394 #define DSI_SET_TEAR_SCANLINE 0x44U
395 #define DSI_SET_VSYNC_TIMING 0x40U
396 #define DSI_SOFT_RESET 0x01U
397 #define DSI_WRITE_LUT 0x2DU
398 #define DSI_WRITE_MEMORY_CONTINUE 0x3CU
399 #define DSI_WRITE_MEMORY_START 0x2CU
400 /**
401 * @}
402 */
403
404 /** @defgroup DSI_Video_Mode_Type DSI Video Mode Type
405 * @{
406 */
407 #define DSI_VID_MODE_NB_PULSES 0U
408 #define DSI_VID_MODE_NB_EVENTS 1U
409 #define DSI_VID_MODE_BURST 2U
410 /**
411 * @}
412 */
413
414 /** @defgroup DSI_Color_Mode DSI Color Mode
415 * @{
416 */
417 #define DSI_COLOR_MODE_FULL 0x00000000U
418 #define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM
419 /**
420 * @}
421 */
422
423 /** @defgroup DSI_ShutDown DSI ShutDown
424 * @{
425 */
426 #define DSI_DISPLAY_ON 0x00000000U
427 #define DSI_DISPLAY_OFF DSI_WCR_SHTDN
428 /**
429 * @}
430 */
431
432 /** @defgroup DSI_LP_Command DSI LP Command
433 * @{
434 */
435 #define DSI_LP_COMMAND_DISABLE 0x00000000U
436 #define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE
437 /**
438 * @}
439 */
440
441 /** @defgroup DSI_LP_HFP DSI LP HFP
442 * @{
443 */
444 #define DSI_LP_HFP_DISABLE 0x00000000U
445 #define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE
446 /**
447 * @}
448 */
449
450 /** @defgroup DSI_LP_HBP DSI LP HBP
451 * @{
452 */
453 #define DSI_LP_HBP_DISABLE 0x00000000U
454 #define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE
455 /**
456 * @}
457 */
458
459 /** @defgroup DSI_LP_VACT DSI LP VACT
460 * @{
461 */
462 #define DSI_LP_VACT_DISABLE 0x00000000U
463 #define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE
464 /**
465 * @}
466 */
467
468 /** @defgroup DSI_LP_VFP DSI LP VFP
469 * @{
470 */
471 #define DSI_LP_VFP_DISABLE 0x00000000U
472 #define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE
473 /**
474 * @}
475 */
476
477 /** @defgroup DSI_LP_VBP DSI LP VBP
478 * @{
479 */
480 #define DSI_LP_VBP_DISABLE 0x00000000U
481 #define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE
482 /**
483 * @}
484 */
485
486 /** @defgroup DSI_LP_VSYNC DSI LP VSYNC
487 * @{
488 */
489 #define DSI_LP_VSYNC_DISABLE 0x00000000U
490 #define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE
491 /**
492 * @}
493 */
494
495 /** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge
496 * @{
497 */
498 #define DSI_FBTAA_DISABLE 0x00000000U
499 #define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE
500 /**
501 * @}
502 */
503
504 /** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source
505 * @{
506 */
507 #define DSI_TE_DSILINK 0x00000000U
508 #define DSI_TE_EXTERNAL DSI_WCFGR_TESRC
509 /**
510 * @}
511 */
512
513 /** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity
514 * @{
515 */
516 #define DSI_TE_RISING_EDGE 0x00000000U
517 #define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL
518 /**
519 * @}
520 */
521
522 /** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity
523 * @{
524 */
525 #define DSI_VSYNC_FALLING 0x00000000U
526 #define DSI_VSYNC_RISING DSI_WCFGR_VSPOL
527 /**
528 * @}
529 */
530
531 /** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh
532 * @{
533 */
534 #define DSI_AR_DISABLE 0x00000000U
535 #define DSI_AR_ENABLE DSI_WCFGR_AR
536 /**
537 * @}
538 */
539
540 /** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request
541 * @{
542 */
543 #define DSI_TE_ACKNOWLEDGE_DISABLE 0x00000000U
544 #define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE
545 /**
546 * @}
547 */
548
549 /** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request
550 * @{
551 */
552 #define DSI_ACKNOWLEDGE_DISABLE 0x00000000U
553 #define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE
554 /**
555 * @}
556 */
557
558 /** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP
559 * @{
560 */
561 #define DSI_LP_GSW0P_DISABLE 0x00000000U
562 #define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX
563 /**
564 * @}
565 */
566
567 /** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP
568 * @{
569 */
570 #define DSI_LP_GSW1P_DISABLE 0x00000000U
571 #define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX
572 /**
573 * @}
574 */
575
576 /** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP
577 * @{
578 */
579 #define DSI_LP_GSW2P_DISABLE 0x00000000U
580 #define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX
581 /**
582 * @}
583 */
584
585 /** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP
586 * @{
587 */
588 #define DSI_LP_GSR0P_DISABLE 0x00000000U
589 #define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX
590 /**
591 * @}
592 */
593
594 /** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP
595 * @{
596 */
597 #define DSI_LP_GSR1P_DISABLE 0x00000000U
598 #define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX
599 /**
600 * @}
601 */
602
603 /** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP
604 * @{
605 */
606 #define DSI_LP_GSR2P_DISABLE 0x00000000U
607 #define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX
608 /**
609 * @}
610 */
611
612 /** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite
613 * @{
614 */
615 #define DSI_LP_GLW_DISABLE 0x00000000U
616 #define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX
617 /**
618 * @}
619 */
620
621 /** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP
622 * @{
623 */
624 #define DSI_LP_DSW0P_DISABLE 0x00000000U
625 #define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX
626 /**
627 * @}
628 */
629
630 /** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP
631 * @{
632 */
633 #define DSI_LP_DSW1P_DISABLE 0x00000000U
634 #define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX
635 /**
636 * @}
637 */
638
639 /** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP
640 * @{
641 */
642 #define DSI_LP_DSR0P_DISABLE 0x00000000U
643 #define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX
644 /**
645 * @}
646 */
647
648 /** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write
649 * @{
650 */
651 #define DSI_LP_DLW_DISABLE 0x00000000U
652 #define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX
653 /**
654 * @}
655 */
656
657 /** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet
658 * @{
659 */
660 #define DSI_LP_MRDP_DISABLE 0x00000000U
661 #define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS
662 /**
663 * @}
664 */
665
666 /** @defgroup DSI_HS_PrespMode DSI HS Presp Mode
667 * @{
668 */
669 #define DSI_HS_PM_DISABLE 0x00000000U
670 #define DSI_HS_PM_ENABLE DSI_TCCR3_PM
671 /**
672 * @}
673 */
674
675
676 /** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control
677 * @{
678 */
679 #define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0x00000000U
680 #define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR
681 /**
682 * @}
683 */
684
685 /** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes
686 * @{
687 */
688 #define DSI_ONE_DATA_LANE 0U
689 #define DSI_TWO_DATA_LANES 1U
690 /**
691 * @}
692 */
693
694 /** @defgroup DSI_FlowControl DSI Flow Control
695 * @{
696 */
697 #define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE
698 #define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE
699 #define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE
700 #define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE
701 #define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE
702 #define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \
703 DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \
704 DSI_FLOW_CONTROL_EOTP_TX)
705 /**
706 * @}
707 */
708
709 /** @defgroup DSI_Color_Coding DSI Color Coding
710 * @{
711 */
712 #define DSI_RGB565 0x00000000U /*!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration */
713 #define DSI_RGB666 0x00000003U /*!< The value 0x00000004 can also be used for the RGB666 color mode configuration */
714 #define DSI_RGB888 0x00000005U
715 /**
716 * @}
717 */
718
719 /** @defgroup DSI_LooselyPacked DSI Loosely Packed
720 * @{
721 */
722 #define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE
723 #define DSI_LOOSELY_PACKED_DISABLE 0x00000000U
724 /**
725 * @}
726 */
727
728 /** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity
729 * @{
730 */
731 #define DSI_HSYNC_ACTIVE_HIGH 0x00000000U
732 #define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP
733 /**
734 * @}
735 */
736
737 /** @defgroup DSI_VSYNC_Active_Polarity DSI VSYNC Active Polarity
738 * @{
739 */
740 #define DSI_VSYNC_ACTIVE_HIGH 0x00000000U
741 #define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP
742 /**
743 * @}
744 */
745
746 /** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity
747 * @{
748 */
749 #define DSI_DATA_ENABLE_ACTIVE_HIGH 0x00000000U
750 #define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP
751 /**
752 * @}
753 */
754
755 /** @defgroup DSI_PLL_IDF DSI PLL IDF
756 * @{
757 */
758 #define DSI_PLL_IN_DIV1 0x00000001U
759 #define DSI_PLL_IN_DIV2 0x00000002U
760 #define DSI_PLL_IN_DIV3 0x00000003U
761 #define DSI_PLL_IN_DIV4 0x00000004U
762 #define DSI_PLL_IN_DIV5 0x00000005U
763 #define DSI_PLL_IN_DIV6 0x00000006U
764 #define DSI_PLL_IN_DIV7 0x00000007U
765 /**
766 * @}
767 */
768
769 /** @defgroup DSI_PLL_ODF DSI PLL ODF
770 * @{
771 */
772 #define DSI_PLL_OUT_DIV1 0x00000000U
773 #define DSI_PLL_OUT_DIV2 0x00000001U
774 #define DSI_PLL_OUT_DIV4 0x00000002U
775 #define DSI_PLL_OUT_DIV8 0x00000003U
776 /**
777 * @}
778 */
779
780 /** @defgroup DSI_Flags DSI Flags
781 * @{
782 */
783 #define DSI_FLAG_TE DSI_WISR_TEIF
784 #define DSI_FLAG_ER DSI_WISR_ERIF
785 #define DSI_FLAG_BUSY DSI_WISR_BUSY
786 #define DSI_FLAG_PLLLS DSI_WISR_PLLLS
787 #define DSI_FLAG_PLLL DSI_WISR_PLLLIF
788 #define DSI_FLAG_PLLU DSI_WISR_PLLUIF
789 #define DSI_FLAG_RRS DSI_WISR_RRS
790 #define DSI_FLAG_RR DSI_WISR_RRIF
791 /**
792 * @}
793 */
794
795 /** @defgroup DSI_Interrupts DSI Interrupts
796 * @{
797 */
798 #define DSI_IT_TE DSI_WIER_TEIE
799 #define DSI_IT_ER DSI_WIER_ERIE
800 #define DSI_IT_PLLL DSI_WIER_PLLLIE
801 #define DSI_IT_PLLU DSI_WIER_PLLUIE
802 #define DSI_IT_RR DSI_WIER_RRIE
803 /**
804 * @}
805 */
806
807 /** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type
808 * @{
809 */
810 #define DSI_DCS_SHORT_PKT_WRITE_P0 0x00000005U /*!< DCS short write, no parameters */
811 #define DSI_DCS_SHORT_PKT_WRITE_P1 0x00000015U /*!< DCS short write, one parameter */
812 #define DSI_GEN_SHORT_PKT_WRITE_P0 0x00000003U /*!< Generic short write, no parameters */
813 #define DSI_GEN_SHORT_PKT_WRITE_P1 0x00000013U /*!< Generic short write, one parameter */
814 #define DSI_GEN_SHORT_PKT_WRITE_P2 0x00000023U /*!< Generic short write, two parameters */
815 /**
816 * @}
817 */
818
819 /** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type
820 * @{
821 */
822 #define DSI_DCS_LONG_PKT_WRITE 0x00000039U /*!< DCS long write */
823 #define DSI_GEN_LONG_PKT_WRITE 0x00000029U /*!< Generic long write */
824 /**
825 * @}
826 */
827
828 /** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type
829 * @{
830 */
831 #define DSI_DCS_SHORT_PKT_READ 0x00000006U /*!< DCS short read */
832 #define DSI_GEN_SHORT_PKT_READ_P0 0x00000004U /*!< Generic short read, no parameters */
833 #define DSI_GEN_SHORT_PKT_READ_P1 0x00000014U /*!< Generic short read, one parameter */
834 #define DSI_GEN_SHORT_PKT_READ_P2 0x00000024U /*!< Generic short read, two parameters */
835 /**
836 * @}
837 */
838
839 /** @defgroup DSI_Error_Data_Type DSI Error Data Type
840 * @{
841 */
842 #define HAL_DSI_ERROR_NONE 0U
843 #define HAL_DSI_ERROR_ACK 0x00000001U /*!< acknowledge errors */
844 #define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */
845 #define HAL_DSI_ERROR_TX 0x00000004U /*!< transmission error */
846 #define HAL_DSI_ERROR_RX 0x00000008U /*!< reception error */
847 #define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */
848 #define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */
849 #define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */
850 #define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */
851 #define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */
852 #define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */
853 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
854 #define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U /*!< DSI Invalid Callback error */
855 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
856 /**
857 * @}
858 */
859
860 /** @defgroup DSI_Lane_Group DSI Lane Group
861 * @{
862 */
863 #define DSI_CLOCK_LANE 0x00000000U
864 #define DSI_DATA_LANES 0x00000001U
865 /**
866 * @}
867 */
868
869 /** @defgroup DSI_Communication_Delay DSI Communication Delay
870 * @{
871 */
872 #define DSI_SLEW_RATE_HSTX 0x00000000U
873 #define DSI_SLEW_RATE_LPTX 0x00000001U
874 #define DSI_HS_DELAY 0x00000002U
875 /**
876 * @}
877 */
878
879 /** @defgroup DSI_CustomLane DSI CustomLane
880 * @{
881 */
882 #define DSI_SWAP_LANE_PINS 0x00000000U
883 #define DSI_INVERT_HS_SIGNAL 0x00000001U
884 /**
885 * @}
886 */
887
888 /** @defgroup DSI_Lane_Select DSI Lane Select
889 * @{
890 */
891 #define DSI_CLK_LANE 0x00000000U
892 #define DSI_DATA_LANE0 0x00000001U
893 #define DSI_DATA_LANE1 0x00000002U
894 /**
895 * @}
896 */
897
898 /** @defgroup DSI_PHY_Timing DSI PHY Timing
899 * @{
900 */
901 #define DSI_TCLK_POST 0x00000000U
902 #define DSI_TLPX_CLK 0x00000001U
903 #define DSI_THS_EXIT 0x00000002U
904 #define DSI_TLPX_DATA 0x00000003U
905 #define DSI_THS_ZERO 0x00000004U
906 #define DSI_THS_TRAIL 0x00000005U
907 #define DSI_THS_PREPARE 0x00000006U
908 #define DSI_TCLK_ZERO 0x00000007U
909 #define DSI_TCLK_PREPARE 0x00000008U
910 /**
911 * @}
912 */
913
914 /**
915 * @}
916 */
917
918 /* Exported macros -----------------------------------------------------------*/
919 /** @defgroup DSI_Exported_Macros DSI Exported Macros
920 * @{
921 */
922
923 /**
924 * @brief Reset DSI handle state.
925 * @param __HANDLE__: DSI handle
926 * @retval None
927 */
928 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
929 #define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) do{ \
930 (__HANDLE__)->State = HAL_DSI_STATE_RESET; \
931 (__HANDLE__)->MspInitCallback = NULL; \
932 (__HANDLE__)->MspDeInitCallback = NULL; \
933 } while(0)
934 #else
935 #define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DSI_STATE_RESET)
936 #endif /*USE_HAL_DSI_REGISTER_CALLBACKS */
937
938 /**
939 * @brief Enables the DSI host.
940 * @param __HANDLE__ DSI handle
941 * @retval None.
942 */
943 #define __HAL_DSI_ENABLE(__HANDLE__) do { \
944 __IO uint32_t tmpreg = 0x00U; \
945 SET_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
946 /* Delay after an DSI Host enabling */ \
947 tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
948 UNUSED(tmpreg); \
949 } while(0U)
950
951 /**
952 * @brief Disables the DSI host.
953 * @param __HANDLE__ DSI handle
954 * @retval None.
955 */
956 #define __HAL_DSI_DISABLE(__HANDLE__) do { \
957 __IO uint32_t tmpreg = 0x00U; \
958 CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
959 /* Delay after an DSI Host disabling */ \
960 tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
961 UNUSED(tmpreg); \
962 } while(0U)
963
964 /**
965 * @brief Enables the DSI wrapper.
966 * @param __HANDLE__ DSI handle
967 * @retval None.
968 */
969 #define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \
970 __IO uint32_t tmpreg = 0x00U; \
971 SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
972 /* Delay after an DSI warpper enabling */ \
973 tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
974 UNUSED(tmpreg); \
975 } while(0U)
976
977 /**
978 * @brief Disable the DSI wrapper.
979 * @param __HANDLE__ DSI handle
980 * @retval None.
981 */
982 #define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \
983 __IO uint32_t tmpreg = 0x00U; \
984 CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
985 /* Delay after an DSI warpper disabling*/ \
986 tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
987 UNUSED(tmpreg); \
988 } while(0U)
989
990 /**
991 * @brief Enables the DSI PLL.
992 * @param __HANDLE__ DSI handle
993 * @retval None.
994 */
995 #define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \
996 __IO uint32_t tmpreg = 0x00U; \
997 SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
998 /* Delay after an DSI PLL enabling */ \
999 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
1000 UNUSED(tmpreg); \
1001 } while(0U)
1002
1003 /**
1004 * @brief Disables the DSI PLL.
1005 * @param __HANDLE__ DSI handle
1006 * @retval None.
1007 */
1008 #define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \
1009 __IO uint32_t tmpreg = 0x00U; \
1010 CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
1011 /* Delay after an DSI PLL disabling */ \
1012 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
1013 UNUSED(tmpreg); \
1014 } while(0U)
1015
1016 /**
1017 * @brief Enables the DSI regulator.
1018 * @param __HANDLE__ DSI handle
1019 * @retval None.
1020 */
1021 #define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \
1022 __IO uint32_t tmpreg = 0x00U; \
1023 SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
1024 /* Delay after an DSI regulator enabling */ \
1025 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
1026 UNUSED(tmpreg); \
1027 } while(0U)
1028
1029 /**
1030 * @brief Disables the DSI regulator.
1031 * @param __HANDLE__ DSI handle
1032 * @retval None.
1033 */
1034 #define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \
1035 __IO uint32_t tmpreg = 0x00U; \
1036 CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
1037 /* Delay after an DSI regulator disabling */ \
1038 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
1039 UNUSED(tmpreg); \
1040 } while(0U)
1041
1042 /**
1043 * @brief Get the DSI pending flags.
1044 * @param __HANDLE__ DSI handle.
1045 * @param __FLAG__ Get the specified flag.
1046 * This parameter can be any combination of the following values:
1047 * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
1048 * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
1049 * @arg DSI_FLAG_BUSY : Busy Flag
1050 * @arg DSI_FLAG_PLLLS: PLL Lock Status
1051 * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
1052 * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
1053 * @arg DSI_FLAG_RRS : Regulator Ready Flag
1054 * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag
1055 * @retval The state of FLAG (SET or RESET).
1056 */
1057 #define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__))
1058
1059 /**
1060 * @brief Clears the DSI pending flags.
1061 * @param __HANDLE__ DSI handle.
1062 * @param __FLAG__ specifies the flag to clear.
1063 * This parameter can be any combination of the following values:
1064 * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
1065 * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
1066 * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
1067 * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
1068 * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag
1069 * @retval None
1070 */
1071 #define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__))
1072
1073 /**
1074 * @brief Enables the specified DSI interrupts.
1075 * @param __HANDLE__ DSI handle.
1076 * @param __INTERRUPT__ specifies the DSI interrupt sources to be enabled.
1077 * This parameter can be any combination of the following values:
1078 * @arg DSI_IT_TE : Tearing Effect Interrupt
1079 * @arg DSI_IT_ER : End of Refresh Interrupt
1080 * @arg DSI_IT_PLLL: PLL Lock Interrupt
1081 * @arg DSI_IT_PLLU: PLL Unlock Interrupt
1082 * @arg DSI_IT_RR : Regulator Ready Interrupt
1083 * @retval None
1084 */
1085 #define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER |= (__INTERRUPT__))
1086
1087 /**
1088 * @brief Disables the specified DSI interrupts.
1089 * @param __HANDLE__ DSI handle
1090 * @param __INTERRUPT__ specifies the DSI interrupt sources to be disabled.
1091 * This parameter can be any combination of the following values:
1092 * @arg DSI_IT_TE : Tearing Effect Interrupt
1093 * @arg DSI_IT_ER : End of Refresh Interrupt
1094 * @arg DSI_IT_PLLL: PLL Lock Interrupt
1095 * @arg DSI_IT_PLLU: PLL Unlock Interrupt
1096 * @arg DSI_IT_RR : Regulator Ready Interrupt
1097 * @retval None
1098 */
1099 #define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__))
1100
1101 /**
1102 * @brief Checks whether the specified DSI interrupt source is enabled or not.
1103 * @param __HANDLE__ DSI handle
1104 * @param __INTERRUPT__ specifies the DSI interrupt source to check.
1105 * This parameter can be one of the following values:
1106 * @arg DSI_IT_TE : Tearing Effect Interrupt
1107 * @arg DSI_IT_ER : End of Refresh Interrupt
1108 * @arg DSI_IT_PLLL: PLL Lock Interrupt
1109 * @arg DSI_IT_PLLU: PLL Unlock Interrupt
1110 * @arg DSI_IT_RR : Regulator Ready Interrupt
1111 * @retval The state of INTERRUPT (SET or RESET).
1112 */
1113 #define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__))
1114
1115 /**
1116 * @}
1117 */
1118
1119 /* Exported functions --------------------------------------------------------*/
1120 /** @defgroup DSI_Exported_Functions DSI Exported Functions
1121 * @{
1122 */
1123 HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit);
1124 HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi);
1125 void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi);
1126 void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi);
1127
1128 void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);
1129 void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
1130 void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
1131 void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
1132
1133 /* Callbacks Register/UnRegister functions ***********************************/
1134 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
1135 HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID,
1136 pDSI_CallbackTypeDef pCallback);
1137 HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID);
1138 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
1139
1140 HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID);
1141 HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg);
1142 HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg);
1143 HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd);
1144 HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl);
1145 HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers);
1146 HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts);
1147 HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi);
1148 HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi);
1149 HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi);
1150 HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode);
1151 HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown);
1152 HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
1153 uint32_t ChannelID,
1154 uint32_t Mode,
1155 uint32_t Param1,
1156 uint32_t Param2);
1157 HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
1158 uint32_t ChannelID,
1159 uint32_t Mode,
1160 uint32_t NbParams,
1161 uint32_t Param1,
1162 uint8_t *ParametersTable);
1163 HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
1164 uint32_t ChannelNbr,
1165 uint8_t *Array,
1166 uint32_t Size,
1167 uint32_t Mode,
1168 uint32_t DCSCmd,
1169 uint8_t *ParametersTable);
1170 HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi);
1171 HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi);
1172 HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi);
1173 HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi);
1174
1175 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation);
1176 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi);
1177
1178 HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane,
1179 uint32_t Value);
1180 HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency);
1181 HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State);
1182 HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane,
1183 FunctionalState State);
1184 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State,
1185 uint32_t Value);
1186 HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State);
1187 HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State);
1188 HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State);
1189 HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State);
1190 HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State);
1191
1192 uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi);
1193 HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);
1194 HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
1195 /**
1196 * @}
1197 */
1198
1199 /* Private types -------------------------------------------------------------*/
1200 /** @defgroup DSI_Private_Types DSI Private Types
1201 * @{
1202 */
1203
1204 /**
1205 * @}
1206 */
1207
1208 /* Private defines -----------------------------------------------------------*/
1209 /** @defgroup DSI_Private_Defines DSI Private Defines
1210 * @{
1211 */
1212
1213 /**
1214 * @}
1215 */
1216
1217 /* Private variables ---------------------------------------------------------*/
1218 /** @defgroup DSI_Private_Variables DSI Private Variables
1219 * @{
1220 */
1221
1222 /**
1223 * @}
1224 */
1225
1226 /* Private constants ---------------------------------------------------------*/
1227 /** @defgroup DSI_Private_Constants DSI Private Constants
1228 * @{
1229 */
1230 #define DSI_MAX_RETURN_PKT_SIZE (0x00000037U) /*!< Maximum return packet configuration */
1231 /**
1232 * @}
1233 */
1234
1235 /* Private macros ------------------------------------------------------------*/
1236 /** @defgroup DSI_Private_Macros DSI Private Macros
1237 * @{
1238 */
1239 #define IS_DSI_PLL_NDIV(NDIV) ((10U <= (NDIV)) && ((NDIV) <= 125U))
1240 #define IS_DSI_PLL_IDF(IDF) (((IDF) == DSI_PLL_IN_DIV1) || \
1241 ((IDF) == DSI_PLL_IN_DIV2) || \
1242 ((IDF) == DSI_PLL_IN_DIV3) || \
1243 ((IDF) == DSI_PLL_IN_DIV4) || \
1244 ((IDF) == DSI_PLL_IN_DIV5) || \
1245 ((IDF) == DSI_PLL_IN_DIV6) || \
1246 ((IDF) == DSI_PLL_IN_DIV7))
1247 #define IS_DSI_PLL_ODF(ODF) (((ODF) == DSI_PLL_OUT_DIV1) || \
1248 ((ODF) == DSI_PLL_OUT_DIV2) || \
1249 ((ODF) == DSI_PLL_OUT_DIV4) || \
1250 ((ODF) == DSI_PLL_OUT_DIV8))
1251 #define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
1252 #define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES))
1253 #define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL)
1254 #define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U)
1255 #define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
1256 #define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
1257 #define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
1258 #define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
1259 #define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \
1260 ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \
1261 ((VideoModeType) == DSI_VID_MODE_BURST))
1262 #define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT))
1263 #define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF))
1264 #define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE))
1265 #define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE))
1266 #define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE))
1267 #define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE))
1268 #define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE))
1269 #define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE))
1270 #define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
1271 #define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
1272 #define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL))
1273 #define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE))
1274 #define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE))
1275 #define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING))
1276 #define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
1277 #define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
1278 #define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
1279 #define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
1280 #define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
1281 #define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
1282 #define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
1283 #define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
1284 #define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE))
1285 #define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
1286 #define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
1287 #define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
1288 #define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE))
1289 #define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
1290 #define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \
1291 ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \
1292 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \
1293 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \
1294 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2))
1295 #define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \
1296 ((MODE) == DSI_GEN_LONG_PKT_WRITE))
1297 #define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) || \
1298 ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \
1299 ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \
1300 ((MODE) == DSI_GEN_SHORT_PKT_READ_P2))
1301 #define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY))
1302 #define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES))
1303 #define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL))
1304 #define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1))
1305 #define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \
1306 ((Timing) == DSI_TLPX_CLK ) || \
1307 ((Timing) == DSI_THS_EXIT ) || \
1308 ((Timing) == DSI_TLPX_DATA ) || \
1309 ((Timing) == DSI_THS_ZERO ) || \
1310 ((Timing) == DSI_THS_TRAIL ) || \
1311 ((Timing) == DSI_THS_PREPARE ) || \
1312 ((Timing) == DSI_TCLK_ZERO ) || \
1313 ((Timing) == DSI_TCLK_PREPARE))
1314
1315 /**
1316 * @}
1317 */
1318
1319 /* Private functions prototypes ----------------------------------------------*/
1320 /** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes
1321 * @{
1322 */
1323
1324 /**
1325 * @}
1326 */
1327
1328 /* Private functions ---------------------------------------------------------*/
1329 /** @defgroup DSI_Private_Functions DSI Private Functions
1330 * @{
1331 */
1332
1333 /**
1334 * @}
1335 */
1336
1337 /**
1338 * @}
1339 */
1340
1341 /**
1342 * @}
1343 */
1344 #endif /* DSI */
1345
1346 #ifdef __cplusplus
1347 }
1348 #endif
1349
1350 #endif /* STM32H7xx_HAL_DSI_H */
1351
1352 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/