?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge pull request #11270 from haslinghuis/rename_attr
[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_hal_eth.h
blob039dc6641f4d25978c2a28f417600add359a34a9
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal_eth.h
4 * @author MCD Application Team
5 * @brief Header file of ETH HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_HAL_ETH_H
22 #define STM32H7xx_HAL_ETH_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28
29 /* Includes ------------------------------------------------------------------*/
30 #include "stm32h7xx_hal_def.h"
31
32 #if defined(ETH)
33
34 /** @addtogroup STM32H7xx_HAL_Driver
35 * @{
36 */
37
38 /** @addtogroup ETH
39 * @{
40 */
41
42 /* Exported types ------------------------------------------------------------*/
43 #ifndef ETH_TX_DESC_CNT
44 #define ETH_TX_DESC_CNT 4U
45 #endif
46
47 #ifndef ETH_RX_DESC_CNT
48 #define ETH_RX_DESC_CNT 4U
49 #endif
50
51 /*********************** Descriptors struct def section ************************/
52 /** @defgroup ETH_Exported_Types ETH Exported Types
53 * @{
54 */
55
56 /**
57 * @brief ETH DMA Descriptor structure definition
58 */
59 typedef struct
60 {
61 __IO uint32_t DESC0;
62 __IO uint32_t DESC1;
63 __IO uint32_t DESC2;
64 __IO uint32_t DESC3;
65 uint32_t BackupAddr0; /* used to store rx buffer 1 address */
66 uint32_t BackupAddr1; /* used to store rx buffer 2 address */
67 }ETH_DMADescTypeDef;
68 /**
69 *
70 */
71
72 /**
73 * @brief ETH Buffers List structure definition
74 */
75 typedef struct __ETH_BufferTypeDef
76 {
77 uint8_t *buffer; /*<! buffer address */
78
79 uint32_t len; /*<! buffer length */
80
81 struct __ETH_BufferTypeDef *next; /*<! Pointer to the next buffer in the list */
82 }ETH_BufferTypeDef;
83 /**
84 *
85 */
86
87 /**
88 * @brief DMA Transmit Descriptors Wrapper structure definition
89 */
90 typedef struct
91 {
92 uint32_t TxDesc[ETH_TX_DESC_CNT]; /*<! Tx DMA descriptors addresses */
93
94 uint32_t CurTxDesc; /*<! Current Tx descriptor index for packet transmission */
95
96 }ETH_TxDescListTypeDef;
97 /**
98 *
99 */
100
101 /**
102 * @brief Transmit Packet Configuration structure definition
103 */
104 typedef struct
105 {
106 uint32_t Attributes; /*!< Tx packet HW features capabilities.
107 This parameter can be a combination of @ref ETH_Tx_Packet_Attributes*/
108
109 uint32_t Length; /*!< Total packet length */
110
111 ETH_BufferTypeDef *TxBuffer; /*!< Tx buffers pointers */
112
113 uint32_t SrcAddrCtrl; /*!< Specifies the source address insertion control.
114 This parameter can be a value of @ref ETH_Tx_Packet_Source_Addr_Control */
115
116 uint32_t CRCPadCtrl; /*!< Specifies the CRC and Pad insertion and replacement control.
117 This parameter can be a value of @ref ETH_Tx_Packet_CRC_Pad_Control */
118
119 uint32_t ChecksumCtrl; /*!< Specifies the checksum insertion control.
120 This parameter can be a value of @ref ETH_Tx_Packet_Checksum_Control */
121
122 uint32_t MaxSegmentSize; /*!< Sets TCP maximum segment size only when TCP segmentation is enabled.
123 This parameter can be a value from 0x0 to 0x3FFF */
124
125 uint32_t PayloadLen; /*!< Sets Total payload length only when TCP segmentation is enabled.
126 This parameter can be a value from 0x0 to 0x3FFFF */
127
128 uint32_t TCPHeaderLen; /*!< Sets TCP header length only when TCP segmentation is enabled.
129 This parameter can be a value from 0x5 to 0xF */
130
131 uint32_t VlanTag; /*!< Sets VLAN Tag only when VLAN is enabled.
132 This parameter can be a value from 0x0 to 0xFFFF*/
133
134 uint32_t VlanCtrl; /*!< Specifies VLAN Tag insertion control only when VLAN is enabled.
135 This parameter can be a value of @ref ETH_Tx_Packet_VLAN_Control */
136
137 uint32_t InnerVlanTag; /*!< Sets Inner VLAN Tag only when Inner VLAN is enabled.
138 This parameter can be a value from 0x0 to 0x3FFFF */
139
140 uint32_t InnerVlanCtrl; /*!< Specifies Inner VLAN Tag insertion control only when Inner VLAN is enabled.
141 This parameter can be a value of @ref ETH_Tx_Packet_Inner_VLAN_Control */
142
143 }ETH_TxPacketConfig;
144 /**
145 *
146 */
147
148 /**
149 * @brief DMA Receive Descriptors Wrapper structure definition
150 */
151 typedef struct
152 {
153 uint32_t RxDesc[ETH_RX_DESC_CNT]; /*<! Rx DMA descriptors addresses. */
154
155 uint32_t CurRxDesc; /*<! Current Rx descriptor, ready for next reception. */
156
157 uint32_t FirstAppDesc; /*<! First descriptor of last received packet. */
158
159 uint32_t AppDescNbr; /*<! Number of descriptors of last received packet. */
160
161 uint32_t AppContextDesc; /*<! If 1 a context descriptor is present in last received packet.
162 If 0 no context descriptor is present in last received packet. */
163
164 uint32_t ItMode; /*<! If 1, DMA will generate the Rx complete interrupt.
165 If 0, DMA will not generate the Rx complete interrupt. */
166 }ETH_RxDescListTypeDef;
167 /**
168 *
169 */
170
171 /**
172 * @brief Received Packet Information structure definition
173 */
174 typedef struct
175 {
176 uint32_t SegmentCnt; /*<! Number of Rx Descriptors */
177
178 uint32_t VlanTag; /*<! Vlan Tag value */
179
180 uint32_t InnerVlanTag; /*<! Inner Vlan Tag value */
181
182 uint32_t Checksum; /*<! Rx Checksum status.
183 This parameter can be a value of @ref ETH_Rx_Checksum_Status */
184
185 uint32_t HeaderType; /*<! IP header type.
186 This parameter can be a value of @ref ETH_Rx_IP_Header_Type */
187
188 uint32_t PayloadType; /*<! Payload type.
189 This parameter can be a value of @ref ETH_Rx_Payload_Type */
190
191 uint32_t MacFilterStatus; /*<! MAC filter status.
192 This parameter can be a value of @ref ETH_Rx_MAC_Filter_Status */
193
194 uint32_t L3FilterStatus; /*<! L3 filter status
195 This parameter can be a value of @ref ETH_Rx_L3_Filter_Status */
196
197 uint32_t L4FilterStatus; /*<! L4 filter status
198 This parameter can be a value of @ref ETH_Rx_L4_Filter_Status */
199
200 uint32_t ErrorCode; /*<! Rx error code
201 This parameter can be a combination of @ref ETH_Rx_Error_Code */
202
203 } ETH_RxPacketInfo;
204 /**
205 *
206 */
207
208 /**
209 * @brief ETH MAC Configuration Structure definition
210 */
211 typedef struct
212 {
213 uint32_t SourceAddrControl; /*!< Selects the Source Address Insertion or Replacement Control.
214 This parameter can be a value of @ref ETH_Source_Addr_Control */
215
216 FunctionalState ChecksumOffload; /*!< Enables or Disable the checksum checking for received packet payloads TCP, UDP or ICMP headers */
217
218 uint32_t InterPacketGapVal; /*!< Sets the minimum IPG between Packet during transmission.
219 This parameter can be a value of @ref ETH_Inter_Packet_Gap */
220
221 FunctionalState GiantPacketSizeLimitControl; /*!< Enables or disables the Giant Packet Size Limit Control. */
222
223 FunctionalState Support2KPacket; /*!< Enables or disables the IEEE 802.3as Support for 2K length Packets */
224
225 FunctionalState CRCStripTypePacket; /*!< Enables or disables the CRC stripping for Type packets.*/
226
227 FunctionalState AutomaticPadCRCStrip; /*!< Enables or disables the Automatic MAC Pad/CRC Stripping.*/
228
229 FunctionalState Watchdog; /*!< Enables or disables the Watchdog timer on Rx path
230 When enabled, the MAC allows no more then 2048 bytes to be received.
231 When disabled, the MAC can receive up to 16384 bytes. */
232
233 FunctionalState Jabber; /*!< Enables or disables Jabber timer on Tx path
234 When enabled, the MAC allows no more then 2048 bytes to be sent.
235 When disabled, the MAC can send up to 16384 bytes. */
236
237 FunctionalState JumboPacket; /*!< Enables or disables receiving Jumbo Packet
238 When enabled, the MAC allows jumbo packets of 9,018 bytes
239 without reporting a giant packet error */
240
241 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
242 This parameter can be a value of @ref ETH_Speed */
243
244 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
245 This parameter can be a value of @ref ETH_Duplex_Mode */
246
247 FunctionalState LoopbackMode; /*!< Enables or disables the loopback mode */
248
249 FunctionalState CarrierSenseBeforeTransmit; /*!< Enables or disables the Carrier Sense Before Transmission in Full Duplex Mode. */
250
251 FunctionalState ReceiveOwn; /*!< Enables or disables the Receive Own in Half Duplex mode. */
252
253 FunctionalState CarrierSenseDuringTransmit; /*!< Enables or disables the Carrier Sense During Transmission in the Half Duplex mode */
254
255 FunctionalState RetryTransmission; /*!< Enables or disables the MAC retry transmission, when a collision occurs in Half Duplex mode.*/
256
257 uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
258 This parameter can be a value of @ref ETH_Back_Off_Limit */
259
260 FunctionalState DeferralCheck; /*!< Enables or disables the deferral check function in Half Duplex mode. */
261
262 uint32_t PreambleLength; /*!< Selects or not the Preamble Length for Transmit packets (Full Duplex mode).
263 This parameter can be a value of @ref ETH_Preamble_Length */
264
265 FunctionalState UnicastSlowProtocolPacketDetect; /*!< Enable or disables the Detection of Slow Protocol Packets with unicast address. */
266
267 FunctionalState SlowProtocolDetect; /*!< Enable or disables the Slow Protocol Detection. */
268
269 FunctionalState CRCCheckingRxPackets; /*!< Enable or disables the CRC Checking for Received Packets. */
270
271 uint32_t GiantPacketSizeLimit; /*!< Specifies the packet size that the MAC will declare it as Giant, If it's size is
272 greater than the value programmed in this field in units of bytes
273 This parameter must be a number between Min_Data = 0x618 (1518 byte) and Max_Data = 0x3FFF (32 Kbyte)*/
274
275 FunctionalState ExtendedInterPacketGap; /*!< Enable or disables the extended inter packet gap. */
276
277 uint32_t ExtendedInterPacketGapVal; /*!< Sets the Extended IPG between Packet during transmission.
278 This parameter can be a value from 0x0 to 0xFF */
279
280 FunctionalState ProgrammableWatchdog; /*!< Enable or disables the Programmable Watchdog.*/
281
282 uint32_t WatchdogTimeout; /*!< This field is used as watchdog timeout for a received packet
283 This parameter can be a value of @ref ETH_Watchdog_Timeout */
284
285 uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control packet.
286 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
287
288 FunctionalState ZeroQuantaPause; /*!< Enable or disables the automatic generation of Zero Quanta Pause Control packets.*/
289
290 uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Packet.
291 This parameter can be a value of @ref ETH_Pause_Low_Threshold */
292
293 FunctionalState TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause packets in Full Duplex mode
294 or the MAC back pressure operation in Half Duplex mode */
295
296 FunctionalState UnicastPausePacketDetect; /*!< Enables or disables the MAC to detect Pause packets with unicast address of the station */
297
298 FunctionalState ReceiveFlowControl; /*!< Enables or disables the MAC to decodes the received Pause packet
299 and disables its transmitter for a specified (Pause) time */
300
301 uint32_t TransmitQueueMode; /*!< Specifies the Transmit Queue operating mode.
302 This parameter can be a value of @ref ETH_Transmit_Mode */
303
304 uint32_t ReceiveQueueMode; /*!< Specifies the Receive Queue operating mode.
305 This parameter can be a value of @ref ETH_Receive_Mode */
306
307 FunctionalState DropTCPIPChecksumErrorPacket; /*!< Enables or disables Dropping of TCPIP Checksum Error Packets. */
308
309 FunctionalState ForwardRxErrorPacket; /*!< Enables or disables forwarding Error Packets. */
310
311 FunctionalState ForwardRxUndersizedGoodPacket; /*!< Enables or disables forwarding Undersized Good Packets.*/
312 } ETH_MACConfigTypeDef;
313 /**
314 *
315 */
316
317 /**
318 * @brief ETH DMA Configuration Structure definition
319 */
320 typedef struct
321 {
322 uint32_t DMAArbitration; /*!< Sets the arbitration scheme between DMA Tx and Rx
323 This parameter can be a value of @ref ETH_DMA_Arbitration */
324
325 FunctionalState AddressAlignedBeats; /*!< Enables or disables the AHB Master interface address aligned
326 burst transfers on Read and Write channels */
327
328 uint32_t BurstMode; /*!< Sets the AHB Master interface burst transfers.
329 This parameter can be a value of @ref ETH_Burst_Mode */
330
331 FunctionalState RebuildINCRxBurst; /*!< Enables or disables the AHB Master to rebuild the pending beats
332 of any initiated burst transfer with INCRx and SINGLE transfers. */
333
334 FunctionalState PBLx8Mode; /*!< Enables or disables the PBL multiplication by eight. */
335
336 uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
337 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
338
339 FunctionalState SecondPacketOperate; /*!< Enables or disables the Operate on second Packet mode, which allows the DMA to process a second
340 Packet of Transmit data even before obtaining the status for the first one. */
341
342 uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
343 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
344
345 FunctionalState FlushRxPacket; /*!< Enables or disables the Rx Packet Flush */
346
347 FunctionalState TCPSegmentation; /*!< Enables or disables the TCP Segmentation */
348
349 uint32_t MaximumSegmentSize; /*!< Sets the maximum segment size that should be used while segmenting the packet
350 This parameter can be a value from 0x40 to 0x3FFF */
351 } ETH_DMAConfigTypeDef;
352 /**
353 *
354 */
355
356 /**
357 * @brief HAL ETH Media Interfaces enum definition
358 */
359 typedef enum
360 {
361 HAL_ETH_MII_MODE = 0x00U, /*!< Media Independent Interface */
362 HAL_ETH_RMII_MODE = 0x01U /*!< Reduced Media Independent Interface */
363 }ETH_MediaInterfaceTypeDef;
364 /**
365 *
366 */
367
368 /**
369 * @brief ETH Init Structure definition
370 */
371 typedef struct
372 {
373
374 uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
375
376 ETH_MediaInterfaceTypeDef MediaInterface; /*!< Selects the MII interface or the RMII interface. */
377
378 ETH_DMADescTypeDef *TxDesc; /*!< Provides the address of the first DMA Tx descriptor in the list */
379
380 ETH_DMADescTypeDef *RxDesc; /*!< Provides the address of the first DMA Rx descriptor in the list */
381
382 uint32_t RxBuffLen; /*!< Provides the length of Rx buffers size */
383
384 }ETH_InitTypeDef;
385 /**
386 *
387 */
388
389 /**
390 * @brief HAL State structures definition
391 */
392 typedef uint32_t HAL_ETH_StateTypeDef;
393 /**
394 *
395 */
396
397 /**
398 * @brief ETH Handle Structure definition
399 */
400 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
401 typedef struct __ETH_HandleTypeDef
402 #else
403 typedef struct
404 #endif
405 {
406 ETH_TypeDef *Instance; /*!< Register base address */
407
408 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
409
410 ETH_TxDescListTypeDef TxDescList; /*!< Tx descriptor wrapper: holds all Tx descriptors list
411 addresses and current descriptor index */
412
413 ETH_RxDescListTypeDef RxDescList; /*!< Rx descriptor wrapper: holds all Rx descriptors list
414 addresses and current descriptor index */
415
416 HAL_LockTypeDef Lock; /*!< Locking object */
417
418 __IO HAL_ETH_StateTypeDef gState; /*!< ETH state information related to global Handle management
419 and also related to Tx operations.
420 This parameter can be a value of @ref HAL_ETH_StateTypeDef */
421
422 __IO HAL_ETH_StateTypeDef RxState; /*!< ETH state information related to Rx operations.
423 This parameter can be a value of @ref HAL_ETH_StateTypeDef */
424
425 __IO uint32_t ErrorCode; /*!< Holds the global Error code of the ETH HAL status machine
426 This parameter can be a value of of @ref ETH_Error_Code */
427
428 __IO uint32_t DMAErrorCode; /*!< Holds the DMA Rx Tx Error code when a DMA AIS interrupt occurs
429 This parameter can be a combination of @ref ETH_DMA_Status_Flags */
430
431 __IO uint32_t MACErrorCode; /*!< Holds the MAC Rx Tx Error code when a MAC Rx or Tx status interrupt occurs
432 This parameter can be a combination of @ref ETH_MAC_Rx_Tx_Status */
433
434 __IO uint32_t MACWakeUpEvent; /*!< Holds the Wake Up event when the MAC exit the power down mode
435 This parameter can be a value of @ref ETH_MAC_Wake_Up_Event */
436
437 __IO uint32_t MACLPIEvent; /*!< Holds the LPI event when the an LPI status interrupt occurs.
438 This parameter can be a value of @ref ETHEx_LPI_Event */
439
440 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
441
442 void (* TxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Tx Complete Callback */
443 void (* RxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Rx Complete Callback */
444 void (* DMAErrorCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH DMA Error Callback */
445 void (* MACErrorCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH MAC Error Callback */
446 void (* PMTCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Power Management Callback */
447 void (* EEECallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH EEE Callback */
448 void (* WakeUpCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Wake UP Callback */
449
450 void (* MspInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp Init callback */
451 void (* MspDeInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp DeInit callback */
452
453 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
454
455 } ETH_HandleTypeDef;
456 /**
457 *
458 */
459
460 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
461 /**
462 * @brief HAL ETH Callback ID enumeration definition
463 */
464 typedef enum
465 {
466 HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */
467 HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */
468
469 HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */
470 HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */
471 HAL_ETH_DMA_ERROR_CB_ID = 0x04U, /*!< ETH DMA Error Callback ID */
472 HAL_ETH_MAC_ERROR_CB_ID = 0x05U, /*!< ETH MAC Error Callback ID */
473 HAL_ETH_PMT_CB_ID = 0x06U, /*!< ETH Power Management Callback ID */
474 HAL_ETH_EEE_CB_ID = 0x07U, /*!< ETH EEE Callback ID */
475 HAL_ETH_WAKEUP_CB_ID = 0x08U /*!< ETH Wake UP Callback ID */
476
477
478 }HAL_ETH_CallbackIDTypeDef;
479
480 /**
481 * @brief HAL ETH Callback pointer definition
482 */
483 typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef * heth); /*!< pointer to an ETH callback function */
484
485 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
486
487 /**
488 * @brief ETH MAC filter structure definition
489 */
490 typedef struct{
491 FunctionalState PromiscuousMode; /*!< Enable or Disable Promiscuous Mode */
492
493 FunctionalState ReceiveAllMode; /*!< Enable or Disable Receive All Mode */
494
495 FunctionalState HachOrPerfectFilter; /*!< Enable or Disable Perfect filtering in addition to Hash filtering */
496
497 FunctionalState HashUnicast; /*!< Enable or Disable Hash filtering on unicast packets */
498
499 FunctionalState HashMulticast; /*!< Enable or Disable Hash filtering on multicast packets */
500
501 FunctionalState PassAllMulticast; /*!< Enable or Disable passing all multicast packets */
502
503 FunctionalState SrcAddrFiltering; /*!< Enable or Disable source address filtering module */
504
505 FunctionalState SrcAddrInverseFiltering; /*!< Enable or Disable source address inverse filtering */
506
507 FunctionalState DestAddrInverseFiltering; /*!< Enable or Disable destination address inverse filtering */
508
509 FunctionalState BroadcastFilter; /*!< Enable or Disable broadcast filter */
510
511 uint32_t ControlPacketsFilter; /*!< Set the control packets filter
512 This parameter can be a value of @ref ETH_Control_Packets_Filter */
513 }ETH_MACFilterConfigTypeDef;
514 /**
515 *
516 */
517
518 /**
519 * @brief ETH Power Down structure definition
520 */
521 typedef struct{
522 FunctionalState WakeUpPacket; /*!< Enable or Disable Wake up packet detection in power down mode */
523
524 FunctionalState MagicPacket; /*!< Enable or Disable Magic packet detection in power down mode */
525
526 FunctionalState GlobalUnicast; /*!< Enable or Disable Global unicast packet detection in power down mode */
527
528 FunctionalState WakeUpForward; /*!< Enable or Disable Forwarding Wake up packets */
529
530 }ETH_PowerDownConfigTypeDef;
531 /**
532 *
533 */
534
535 /**
536 * @}
537 */
538
539 /* Exported constants --------------------------------------------------------*/
540 /** @defgroup ETH_Exported_Constants ETH Exported Constants
541 * @{
542 */
543
544 /** @defgroup ETH_DMA_Tx_Descriptor_Bit_Definition ETH DMA Tx Descriptor Bit Definition
545 * @{
546 */
547
548 /*
549 DMA Tx Normal Desciptor Read Format
550 -----------------------------------------------------------------------------------------------
551 TDES0 | Buffer1 or Header Address [31:0] |
552 -----------------------------------------------------------------------------------------------
553 TDES1 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
554 -----------------------------------------------------------------------------------------------
555 TDES2 | IOC(31) | TTSE(30) | Buff2 Length[29:16] | VTIR[15:14] | Header or Buff1 Length[13:0] |
556 -----------------------------------------------------------------------------------------------
557 TDES3 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
558 -----------------------------------------------------------------------------------------------
559 */
560
561 /**
562 * @brief Bit definition of TDES0 RF register
563 */
564 #define ETH_DMATXNDESCRF_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Transmit Packet Timestamp Low */
565
566 /**
567 * @brief Bit definition of TDES1 RF register
568 */
569 #define ETH_DMATXNDESCRF_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Transmit Packet Timestamp High */
570
571 /**
572 * @brief Bit definition of TDES2 RF register
573 */
574 #define ETH_DMATXNDESCRF_IOC ((uint32_t)0x80000000U) /*!< Interrupt on Completion */
575 #define ETH_DMATXNDESCRF_TTSE ((uint32_t)0x40000000U) /*!< Transmit Timestamp Enable */
576 #define ETH_DMATXNDESCRF_B2L ((uint32_t)0x3FFF0000U) /*!< Buffer 2 Length */
577 #define ETH_DMATXNDESCRF_VTIR ((uint32_t)0x0000C000U) /*!< VLAN Tag Insertion or Replacement mask */
578 #define ETH_DMATXNDESCRF_VTIR_DISABLE ((uint32_t)0x00000000U) /*!< Do not add a VLAN tag. */
579 #define ETH_DMATXNDESCRF_VTIR_REMOVE ((uint32_t)0x00004000U) /*!< Remove the VLAN tag from the packets before transmission. */
580 #define ETH_DMATXNDESCRF_VTIR_INSERT ((uint32_t)0x00008000U) /*!< Insert a VLAN tag. */
581 #define ETH_DMATXNDESCRF_VTIR_REPLACE ((uint32_t)0x0000C000U) /*!< Replace the VLAN tag. */
582 #define ETH_DMATXNDESCRF_B1L ((uint32_t)0x00003FFFU) /*!< Buffer 1 Length */
583 #define ETH_DMATXNDESCRF_HL ((uint32_t)0x000003FFU) /*!< Header Length */
584
585 /**
586 * @brief Bit definition of TDES3 RF register
587 */
588 #define ETH_DMATXNDESCRF_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */
589 #define ETH_DMATXNDESCRF_CTXT ((uint32_t)0x40000000U) /*!< Context Type */
590 #define ETH_DMATXNDESCRF_FD ((uint32_t)0x20000000U) /*!< First Descriptor */
591 #define ETH_DMATXNDESCRF_LD ((uint32_t)0x10000000U) /*!< Last Descriptor */
592 #define ETH_DMATXNDESCRF_CPC ((uint32_t)0x0C000000U) /*!< CRC Pad Control mask */
593 #define ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT ((uint32_t)0x00000000U) /*!< CRC Pad Control: CRC and Pad Insertion */
594 #define ETH_DMATXNDESCRF_CPC_CRC_INSERT ((uint32_t)0x04000000U) /*!< CRC Pad Control: CRC Insertion (Disable Pad Insertion) */
595 #define ETH_DMATXNDESCRF_CPC_DISABLE ((uint32_t)0x08000000U) /*!< CRC Pad Control: Disable CRC Insertion */
596 #define ETH_DMATXNDESCRF_CPC_CRC_REPLACE ((uint32_t)0x0C000000U) /*!< CRC Pad Control: CRC Replacement */
597 #define ETH_DMATXNDESCRF_SAIC ((uint32_t)0x03800000U) /*!< SA Insertion Control mask*/
598 #define ETH_DMATXNDESCRF_SAIC_DISABLE ((uint32_t)0x00000000U) /*!< SA Insertion Control: Do not include the source address */
599 #define ETH_DMATXNDESCRF_SAIC_INSERT ((uint32_t)0x00800000U) /*!< SA Insertion Control: Include or insert the source address */
600 #define ETH_DMATXNDESCRF_SAIC_REPLACE ((uint32_t)0x01000000U) /*!< SA Insertion Control: Replace the source address */
601 #define ETH_DMATXNDESCRF_THL ((uint32_t)0x00780000U) /*!< TCP Header Length */
602 #define ETH_DMATXNDESCRF_TSE ((uint32_t)0x00040000U) /*!< TCP segmentation enable */
603 #define ETH_DMATXNDESCRF_CIC ((uint32_t)0x00030000U) /*!< Checksum Insertion Control: 4 cases */
604 #define ETH_DMATXNDESCRF_CIC_DISABLE ((uint32_t)0x00000000U) /*!< Do Nothing: Checksum Engine is disabled */
605 #define ETH_DMATXNDESCRF_CIC_IPHDR_INSERT ((uint32_t)0x00010000U) /*!< Only IP header checksum calculation and insertion are enabled. */
606 #define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT ((uint32_t)0x00020000U) /*!< IP header checksum and payload checksum calculation and insertion are
607 enabled, but pseudo header checksum is not calculated in hardware */
608 #define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC ((uint32_t)0x00030000U) /*!< IP Header checksum and payload checksum calculation and insertion are
609 enabled, and pseudo header checksum is calculated in hardware. */
610 #define ETH_DMATXNDESCRF_TPL ((uint32_t)0x0003FFFFU) /*!< TCP Payload Length */
611 #define ETH_DMATXNDESCRF_FL ((uint32_t)0x00007FFFU) /*!< Transmit End of Ring */
612
613 /*
614 DMA Tx Normal Descriptor Write Back Format
615 -----------------------------------------------------------------------------------------------
616 TDES0 | Timestamp Low |
617 -----------------------------------------------------------------------------------------------
618 TDES1 | Timestamp High |
619 -----------------------------------------------------------------------------------------------
620 TDES2 | Reserved[31:0] |
621 -----------------------------------------------------------------------------------------------
622 TDES3 | OWN(31) | Status[30:0] |
623 -----------------------------------------------------------------------------------------------
624 */
625
626 /**
627 * @brief Bit definition of TDES0 WBF register
628 */
629 #define ETH_DMATXNDESCWBF_TTSL ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer or TSO Header Address Pointer */
630
631 /**
632 * @brief Bit definition of TDES1 WBF register
633 */
634 #define ETH_DMATXNDESCWBF_TTSH ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */
635
636 /**
637 * @brief Bit definition of TDES3 WBF register
638 */
639 #define ETH_DMATXNDESCWBF_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */
640 #define ETH_DMATXNDESCWBF_CTXT ((uint32_t)0x40000000U) /*!< Context Type */
641 #define ETH_DMATXNDESCWBF_FD ((uint32_t)0x20000000U) /*!< First Descriptor */
642 #define ETH_DMATXNDESCWBF_LD ((uint32_t)0x10000000U) /*!< Last Descriptor */
643 #define ETH_DMATXNDESCWBF_TTSS ((uint32_t)0x00020000U) /*!< Tx Timestamp Status */
644 #define ETH_DMATXNDESCWBF_DP ((uint32_t)0x04000000U) /*!< Disable Padding */
645 #define ETH_DMATXNDESCWBF_TTSE ((uint32_t)0x02000000U) /*!< Transmit Timestamp Enable */
646 #define ETH_DMATXNDESCWBF_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: IHE || UF || ED || EC || LCO || PCE || NC || LCA || FF || JT */
647 #define ETH_DMATXNDESCWBF_JT ((uint32_t)0x00004000U) /*!< Jabber Timeout */
648 #define ETH_DMATXNDESCWBF_FF ((uint32_t)0x00002000U) /*!< Packet Flushed: DMA/MTL flushed the packet due to SW flush */
649 #define ETH_DMATXNDESCWBF_PCE ((uint32_t)0x00001000U) /*!< Payload Checksum Error */
650 #define ETH_DMATXNDESCWBF_LCA ((uint32_t)0x00000800U) /*!< Loss of Carrier: carrier lost during transmission */
651 #define ETH_DMATXNDESCWBF_NC ((uint32_t)0x00000400U) /*!< No Carrier: no carrier signal from the transceiver */
652 #define ETH_DMATXNDESCWBF_LCO ((uint32_t)0x00000200U) /*!< Late Collision: transmission aborted due to collision */
653 #define ETH_DMATXNDESCWBF_EC ((uint32_t)0x00000100U) /*!< Excessive Collision: transmission aborted after 16 collisions */
654 #define ETH_DMATXNDESCWBF_CC ((uint32_t)0x000000F0U) /*!< Collision Count */
655 #define ETH_DMATXNDESCWBF_ED ((uint32_t)0x00000008U) /*!< Excessive Deferral */
656 #define ETH_DMATXNDESCWBF_UF ((uint32_t)0x00000004U) /*!< Underflow Error: late data arrival from the memory */
657 #define ETH_DMATXNDESCWBF_DB ((uint32_t)0x00000002U) /*!< Deferred Bit */
658 #define ETH_DMATXNDESCWBF_IHE ((uint32_t)0x00000004U) /*!< IP Header Error */
659
660
661 /*
662 DMA Tx Context Desciptor
663 -----------------------------------------------------------------------------------------------
664 TDES0 | Timestamp Low |
665 -----------------------------------------------------------------------------------------------
666 TDES1 | Timestamp High |
667 -----------------------------------------------------------------------------------------------
668 TDES2 | Inner VLAN Tag[31:16] | Reserved(15) | Maximum Segment Size [14:0] |
669 -----------------------------------------------------------------------------------------------
670 TDES3 | OWN(31) | Status[30:0] |
671 -----------------------------------------------------------------------------------------------
672 */
673
674 /**
675 * @brief Bit definition of Tx context descriptor register 0
676 */
677 #define ETH_DMATXCDESC_TTSL ((uint32_t)0xFFFFFFFFU) /*!< Transmit Packet Timestamp Low */
678
679 /**
680 * @brief Bit definition of Tx context descriptor register 1
681 */
682 #define ETH_DMATXCDESC_TTSH ((uint32_t)0xFFFFFFFFU) /*!< Transmit Packet Timestamp High */
683
684 /**
685 * @brief Bit definition of Tx context descriptor register 2
686 */
687 #define ETH_DMATXCDESC_IVT ((uint32_t)0xFFFF0000U) /*!< Inner VLAN Tag */
688 #define ETH_DMATXCDESC_MSS ((uint32_t)0x00003FFFU) /*!< Maximum Segment Size */
689
690 /**
691 * @brief Bit definition of Tx context descriptor register 3
692 */
693 #define ETH_DMATXCDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */
694 #define ETH_DMATXCDESC_CTXT ((uint32_t)0x40000000U) /*!< Context Type */
695 #define ETH_DMATXCDESC_OSTC ((uint32_t)0x08000000U) /*!< One-Step Timestamp Correction Enable */
696 #define ETH_DMATXCDESC_TCMSSV ((uint32_t)0x04000000U) /*!< One-Step Timestamp Correction Input or MSS Valid */
697 #define ETH_DMATXCDESC_CDE ((uint32_t)0x00800000U) /*!< Context Descriptor Error */
698 #define ETH_DMATXCDESC_IVTIR ((uint32_t)0x000C0000U) /*!< Inner VLAN Tag Insert or Replace Mask */
699 #define ETH_DMATXCDESC_IVTIR_DISABLE ((uint32_t)0x00000000U) /*!< Do not add the inner VLAN tag. */
700 #define ETH_DMATXCDESC_IVTIR_REMOVE ((uint32_t)0x00040000U) /*!< Remove the inner VLAN tag from the packets before transmission. */
701 #define ETH_DMATXCDESC_IVTIR_INSERT ((uint32_t)0x00080000U) /*!< Insert the inner VLAN tag. */
702 #define ETH_DMATXCDESC_IVTIR_REPLACE ((uint32_t)0x000C0000U) /*!< Replace the inner VLAN tag. */
703 #define ETH_DMATXCDESC_IVLTV ((uint32_t)0x00020000U) /*!< Inner VLAN Tag Valid */
704 #define ETH_DMATXCDESC_VLTV ((uint32_t)0x00010000U) /*!< VLAN Tag Valid */
705 #define ETH_DMATXCDESC_VT ((uint32_t)0x0000FFFFU) /*!< VLAN Tag */
706
707 /**
708 * @}
709 */
710
711
712 /** @defgroup ETH_DMA_Rx_Descriptor_Bit_Definition ETH DMA Rx Descriptor Bit Definition
713 * @{
714 */
715
716 /*
717 DMA Rx Normal Descriptor read format
718 -----------------------------------------------------------------------------------------------------------
719 RDES0 | Buffer1 or Header Address [31:0] |
720 -----------------------------------------------------------------------------------------------------------
721 RDES1 | Reserved |
722 -----------------------------------------------------------------------------------------------------------
723 RDES2 | Payload or Buffer2 Address[31:0] |
724 -----------------------------------------------------------------------------------------------------------
725 RDES3 | OWN(31) | IOC(30) | Reserved [29:26] | BUF2V(25) | BUF1V(24) | Reserved [23:0] |
726 -----------------------------------------------------------------------------------------------------------
727 */
728
729 /**
730 * @brief Bit definition of Rx normal descriptor register 0 read format
731 */
732 #define ETH_DMARXNDESCRF_BUF1AP ((uint32_t)0xFFFFFFFFU) /*!< Header or Buffer 1 Address Pointer */
733
734 /**
735 * @brief Bit definition of Rx normal descriptor register 2 read format
736 */
737 #define ETH_DMARXNDESCRF_BUF2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer 2 Address Pointer */
738
739 /**
740 * @brief Bit definition of Rx normal descriptor register 3 read format
741 */
742 #define ETH_DMARXNDESCRF_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */
743 #define ETH_DMARXNDESCRF_IOC ((uint32_t)0x40000000U) /*!< Interrupt Enabled on Completion */
744 #define ETH_DMARXNDESCRF_BUF2V ((uint32_t)0x02000000U) /*!< Buffer 2 Address Valid */
745 #define ETH_DMARXNDESCRF_BUF1V ((uint32_t)0x01000000U) /*!< Buffer 1 Address Valid */
746
747 /*
748 DMA Rx Normal Descriptor write back format
749 ---------------------------------------------------------------------------------------------------------------------
750 RDES0 | Inner VLAN Tag[31:16] | Outer VLAN Tag[15:0] |
751 ---------------------------------------------------------------------------------------------------------------------
752 RDES1 | OAM code, or MAC Control Opcode [31:16] | Extended Status |
753 ---------------------------------------------------------------------------------------------------------------------
754 RDES2 | MAC Filter Status[31:16] | VF(15) | Reserved [14:12] | ARP Status [11:10] | Header Length [9:0] |
755 ---------------------------------------------------------------------------------------------------------------------
756 RDES3 | OWN(31) | CTXT(30) | FD(29) | LD(28) | Status[27:16] | ES(15) | Packet Length[14:0] |
757 ---------------------------------------------------------------------------------------------------------------------
758 */
759
760 /**
761 * @brief Bit definition of Rx normal descriptor register 0 write back format
762 */
763 #define ETH_DMARXNDESCWBF_IVT ((uint32_t)0xFFFF0000U) /*!< Inner VLAN Tag */
764 #define ETH_DMARXNDESCWBF_OVT ((uint32_t)0x0000FFFFU) /*!< Outer VLAN Tag */
765
766 /**
767 * @brief Bit definition of Rx normal descriptor register 1 write back format
768 */
769 #define ETH_DMARXNDESCWBF_OPC ((uint32_t)0xFFFF0000U) /*!< OAM Sub-Type Code, or MAC Control Packet opcode */
770 #define ETH_DMARXNDESCWBF_TD ((uint32_t)0x00008000U) /*!< Timestamp Dropped */
771 #define ETH_DMARXNDESCWBF_TSA ((uint32_t)0x00004000U) /*!< Timestamp Available */
772 #define ETH_DMARXNDESCWBF_PV ((uint32_t)0x00002000U) /*!< PTP Version */
773 #define ETH_DMARXNDESCWBF_PFT ((uint32_t)0x00001000U) /*!< PTP Packet Type */
774 #define ETH_DMARXNDESCWBF_PMT_NO ((uint32_t)0x00000000U) /*!< PTP Message Type: No PTP message received */
775 #define ETH_DMARXNDESCWBF_PMT_SYNC ((uint32_t)0x00000100U) /*!< PTP Message Type: SYNC (all clock types) */
776 #define ETH_DMARXNDESCWBF_PMT_FUP ((uint32_t)0x00000200U) /*!< PTP Message Type: Follow_Up (all clock types) */
777 #define ETH_DMARXNDESCWBF_PMT_DREQ ((uint32_t)0x00000300U) /*!< PTP Message Type: Delay_Req (all clock types) */
778 #define ETH_DMARXNDESCWBF_PMT_DRESP ((uint32_t)0x00000400U) /*!< PTP Message Type: Delay_Resp (all clock types) */
779 #define ETH_DMARXNDESCWBF_PMT_PDREQ ((uint32_t)0x00000500U) /*!< PTP Message Type: Pdelay_Req (in peer-to-peer transparent clock) */
780 #define ETH_DMARXNDESCWBF_PMT_PDRESP ((uint32_t)0x00000600U) /*!< PTP Message Type: Pdelay_Resp (in peer-to-peer transparent clock) */
781 #define ETH_DMARXNDESCWBF_PMT_PDRESPFUP ((uint32_t)0x00000700U) /*!< PTP Message Type: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock) */
782 #define ETH_DMARXNDESCWBF_PMT_ANNOUNCE ((uint32_t)0x00000800U) /*!< PTP Message Type: Announce */
783 #define ETH_DMARXNDESCWBF_PMT_MANAG ((uint32_t)0x00000900U) /*!< PTP Message Type: Management */
784 #define ETH_DMARXNDESCWBF_PMT_SIGN ((uint32_t)0x00000A00U) /*!< PTP Message Type: Signaling */
785 #define ETH_DMARXNDESCWBF_PMT_RESERVED ((uint32_t)0x00000F00U) /*!< PTP Message Type: PTP packet with Reserved message type */
786 #define ETH_DMARXNDESCWBF_IPCE ((uint32_t)0x00000080U) /*!< IP Payload Error */
787 #define ETH_DMARXNDESCWBF_IPCB ((uint32_t)0x00000040U) /*!< IP Checksum Bypassed */
788 #define ETH_DMARXNDESCWBF_IPV6 ((uint32_t)0x00000020U) /*!< IPv6 header Present */
789 #define ETH_DMARXNDESCWBF_IPV4 ((uint32_t)0x00000010U) /*!< IPv4 header Present */
790 #define ETH_DMARXNDESCWBF_IPHE ((uint32_t)0x00000008U) /*!< IP Header Error */
791 #define ETH_DMARXNDESCWBF_PT ((uint32_t)0x00000003U) /*!< Payload Type mask */
792 #define ETH_DMARXNDESCWBF_PT_UNKNOWN ((uint32_t)0x00000000U) /*!< Payload Type: Unknown type or IP/AV payload not processed */
793 #define ETH_DMARXNDESCWBF_PT_UDP ((uint32_t)0x00000001U) /*!< Payload Type: UDP */
794 #define ETH_DMARXNDESCWBF_PT_TCP ((uint32_t)0x00000002U) /*!< Payload Type: TCP */
795 #define ETH_DMARXNDESCWBF_PT_ICMP ((uint32_t)0x00000003U) /*!< Payload Type: ICMP */
796
797 /**
798 * @brief Bit definition of Rx normal descriptor register 2 write back format
799 */
800 #define ETH_DMARXNDESCWBF_L3L4FM ((uint32_t)0x20000000U) /*!< L3 and L4 Filter Number Matched: if reset filter 0 is matched , if set filter 1 is matched */
801 #define ETH_DMARXNDESCWBF_L4FM ((uint32_t)0x10000000U) /*!< Layer 4 Filter Match */
802 #define ETH_DMARXNDESCWBF_L3FM ((uint32_t)0x08000000U) /*!< Layer 3 Filter Match */
803 #define ETH_DMARXNDESCWBF_MADRM ((uint32_t)0x07F80000U) /*!< MAC Address Match or Hash Value */
804 #define ETH_DMARXNDESCWBF_HF ((uint32_t)0x00040000U) /*!< Hash Filter Status */
805 #define ETH_DMARXNDESCWBF_DAF ((uint32_t)0x00020000U) /*!< Destination Address Filter Fail */
806 #define ETH_DMARXNDESCWBF_SAF ((uint32_t)0x00010000U) /*!< SA Address Filter Fail */
807 #define ETH_DMARXNDESCWBF_VF ((uint32_t)0x00008000U) /*!< VLAN Filter Status */
808 #define ETH_DMARXNDESCWBF_ARPNR ((uint32_t)0x00000400U) /*!< ARP Reply Not Generated */
809
810
811 /**
812 * @brief Bit definition of Rx normal descriptor register 3 write back format
813 */
814 #define ETH_DMARXNDESCWBF_OWN ((uint32_t)0x80000000U) /*!< Own Bit */
815 #define ETH_DMARXNDESCWBF_CTXT ((uint32_t)0x40000000U) /*!< Receive Context Descriptor */
816 #define ETH_DMARXNDESCWBF_FD ((uint32_t)0x20000000U) /*!< First Descriptor */
817 #define ETH_DMARXNDESCWBF_LD ((uint32_t)0x10000000U) /*!< Last Descriptor */
818 #define ETH_DMARXNDESCWBF_RS2V ((uint32_t)0x08000000U) /*!< Receive Status RDES2 Valid */
819 #define ETH_DMARXNDESCWBF_RS1V ((uint32_t)0x04000000U) /*!< Receive Status RDES1 Valid */
820 #define ETH_DMARXNDESCWBF_RS0V ((uint32_t)0x02000000U) /*!< Receive Status RDES0 Valid */
821 #define ETH_DMARXNDESCWBF_CE ((uint32_t)0x01000000U) /*!< CRC Error */
822 #define ETH_DMARXNDESCWBF_GP ((uint32_t)0x00800000U) /*!< Giant Packet */
823 #define ETH_DMARXNDESCWBF_RWT ((uint32_t)0x00400000U) /*!< Receive Watchdog Timeout */
824 #define ETH_DMARXNDESCWBF_OE ((uint32_t)0x00200000U) /*!< Overflow Error */
825 #define ETH_DMARXNDESCWBF_RE ((uint32_t)0x00100000U) /*!< Receive Error */
826 #define ETH_DMARXNDESCWBF_DE ((uint32_t)0x00080000U) /*!< Dribble Bit Error */
827 #define ETH_DMARXNDESCWBF_LT ((uint32_t)0x00070000U) /*!< Length/Type Field */
828 #define ETH_DMARXNDESCWBF_LT_LP ((uint32_t)0x00000000U) /*!< The packet is a length packet */
829 #define ETH_DMARXNDESCWBF_LT_TP ((uint32_t)0x00010000U) /*!< The packet is a type packet */
830 #define ETH_DMARXNDESCWBF_LT_ARP ((uint32_t)0x00030000U) /*!< The packet is a ARP Request packet type */
831 #define ETH_DMARXNDESCWBF_LT_VLAN ((uint32_t)0x00040000U) /*!< The packet is a type packet with VLAN Tag */
832 #define ETH_DMARXNDESCWBF_LT_DVLAN ((uint32_t)0x00050000U) /*!< The packet is a type packet with Double VLAN Tag */
833 #define ETH_DMARXNDESCWBF_LT_MAC ((uint32_t)0x00060000U) /*!< The packet is a MAC Control packet type */
834 #define ETH_DMARXNDESCWBF_LT_OAM ((uint32_t)0x00070000U) /*!< The packet is a OAM packet type */
835 #define ETH_DMARXNDESCWBF_ES ((uint32_t)0x00008000U) /*!< Error Summary */
836 #define ETH_DMARXNDESCWBF_PL ((uint32_t)0x00007FFFU) /*!< Packet Length */
837
838 /*
839 DMA Rx context Descriptor
840 ---------------------------------------------------------------------------------------------------------------------
841 RDES0 | Timestamp Low[31:0] |
842 ---------------------------------------------------------------------------------------------------------------------
843 RDES1 | Timestamp High[31:0] |
844 ---------------------------------------------------------------------------------------------------------------------
845 RDES2 | Reserved |
846 ---------------------------------------------------------------------------------------------------------------------
847 RDES3 | OWN(31) | CTXT(30) | Reserved[29:0] |
848 ---------------------------------------------------------------------------------------------------------------------
849 */
850
851 /**
852 * @brief Bit definition of Rx context descriptor register 0
853 */
854 #define ETH_DMARXCDESC_RTSL ((uint32_t)0xFFFFFFFFU) /*!< Receive Packet Timestamp Low */
855
856 /**
857 * @brief Bit definition of Rx context descriptor register 1
858 */
859 #define ETH_DMARXCDESC_RTSH ((uint32_t)0xFFFFFFFFU) /*!< Receive Packet Timestamp High */
860
861 /**
862 * @brief Bit definition of Rx context descriptor register 3
863 */
864 #define ETH_DMARXCDESC_OWN ((uint32_t)0x80000000U) /*!< Own Bit */
865 #define ETH_DMARXCDESC_CTXT ((uint32_t)0x40000000U) /*!< Receive Context Descriptor */
866
867 /**
868 * @}
869 */
870
871 /** @defgroup ETH_Frame_settings ETH frame settings
872 * @{
873 */
874 #define ETH_MAX_PACKET_SIZE ((uint32_t)1528U) /*!< ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */
875 #define ETH_HEADER ((uint32_t)14U) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
876 #define ETH_CRC ((uint32_t)4U) /*!< Ethernet CRC */
877 #define ETH_VLAN_TAG ((uint32_t)4U) /*!< optional 802.1q VLAN Tag */
878 #define ETH_MIN_PAYLOAD ((uint32_t)46U) /*!< Minimum Ethernet payload size */
879 #define ETH_MAX_PAYLOAD ((uint32_t)1500U) /*!< Maximum Ethernet payload size */
880 #define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000U) /*!< Jumbo frame payload size */
881 /**
882 * @}
883 */
884
885 /** @defgroup ETH_Error_Code ETH Error Code
886 * @{
887 */
888 #define HAL_ETH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
889 #define HAL_ETH_ERROR_PARAM ((uint32_t)0x00000001U) /*!< Busy error */
890 #define HAL_ETH_ERROR_BUSY ((uint32_t)0x00000002U) /*!< Parameter error */
891 #define HAL_ETH_ERROR_TIMEOUT ((uint32_t)0x00000004U) /*!< Timeout error */
892 #define HAL_ETH_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA transfer error */
893 #define HAL_ETH_ERROR_MAC ((uint32_t)0x00000010U) /*!< MAC transfer error */
894 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
895 #define HAL_ETH_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */
896 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
897 /**
898 * @}
899 */
900
901 /** @defgroup ETH_Tx_Packet_Attributes ETH Tx Packet Attributes
902 * @{
903 */
904 #define ETH_TX_PACKETS_FEATURES_CSUM ((uint32_t)0x00000001U)
905 #define ETH_TX_PACKETS_FEATURES_SAIC ((uint32_t)0x00000002U)
906 #define ETH_TX_PACKETS_FEATURES_VLANTAG ((uint32_t)0x00000004U)
907 #define ETH_TX_PACKETS_FEATURES_INNERVLANTAG ((uint32_t)0x00000008U)
908 #define ETH_TX_PACKETS_FEATURES_TSO ((uint32_t)0x00000010U)
909 #define ETH_TX_PACKETS_FEATURES_CRCPAD ((uint32_t)0x00000020U)
910 /**
911 * @}
912 */
913
914 /** @defgroup ETH_Tx_Packet_Source_Addr_Control ETH Tx Packet Source Addr Control
915 * @{
916 */
917 #define ETH_SRC_ADDR_CONTROL_DISABLE ETH_DMATXNDESCRF_SAIC_DISABLE
918 #define ETH_SRC_ADDR_INSERT ETH_DMATXNDESCRF_SAIC_INSERT
919 #define ETH_SRC_ADDR_REPLACE ETH_DMATXNDESCRF_SAIC_REPLACE
920 /**
921 * @}
922 */
923
924 /** @defgroup ETH_Tx_Packet_CRC_Pad_Control ETH Tx Packet CRC Pad Control
925 * @{
926 */
927 #define ETH_CRC_PAD_DISABLE ETH_DMATXNDESCRF_CPC_DISABLE
928 #define ETH_CRC_PAD_INSERT ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT
929 #define ETH_CRC_INSERT ETH_DMATXNDESCRF_CPC_CRC_INSERT
930 #define ETH_CRC_REPLACE ETH_DMATXNDESCRF_CPC_CRC_REPLACE
931 /**
932 * @}
933 */
934
935 /** @defgroup ETH_Tx_Packet_Checksum_Control ETH Tx Packet Checksum Control
936 * @{
937 */
938 #define ETH_CHECKSUM_DISABLE ETH_DMATXNDESCRF_CIC_DISABLE
939 #define ETH_CHECKSUM_IPHDR_INSERT ETH_DMATXNDESCRF_CIC_IPHDR_INSERT
940 #define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT
941 #define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC
942 /**
943 * @}
944 */
945
946 /** @defgroup ETH_Tx_Packet_VLAN_Control ETH Tx Packet VLAN Control
947 * @{
948 */
949 #define ETH_VLAN_DISABLE ETH_DMATXNDESCRF_VTIR_DISABLE
950 #define ETH_VLAN_REMOVE ETH_DMATXNDESCRF_VTIR_REMOVE
951 #define ETH_VLAN_INSERT ETH_DMATXNDESCRF_VTIR_INSERT
952 #define ETH_VLAN_REPLACE ETH_DMATXNDESCRF_VTIR_REPLACE
953 /**
954 * @}
955 */
956
957 /** @defgroup ETH_Tx_Packet_Inner_VLAN_Control ETH Tx Packet Inner VLAN Control
958 * @{
959 */
960 #define ETH_INNER_VLAN_DISABLE ETH_DMATXCDESC_IVTIR_DISABLE
961 #define ETH_INNER_VLAN_REMOVE ETH_DMATXCDESC_IVTIR_REMOVE
962 #define ETH_INNER_VLAN_INSERT ETH_DMATXCDESC_IVTIR_INSERT
963 #define ETH_INNER_VLAN_REPLACE ETH_DMATXCDESC_IVTIR_REPLACE
964 /**
965 * @}
966 */
967
968 /** @defgroup ETH_Rx_Checksum_Status ETH Rx Checksum Status
969 * @{
970 */
971 #define ETH_CHECKSUM_BYPASSED ETH_DMARXNDESCWBF_IPCB
972 #define ETH_CHECKSUM_IP_HEADER_ERROR ETH_DMARXNDESCWBF_IPHE
973 #define ETH_CHECKSUM_IP_PAYLOAD_ERROR ETH_DMARXNDESCWBF_IPCE
974 /**
975 * @}
976 */
977
978 /** @defgroup ETH_Rx_IP_Header_Type ETH Rx IP Header Type
979 * @{
980 */
981 #define ETH_IP_HEADER_IPV4 ETH_DMARXNDESCWBF_IPV4
982 #define ETH_IP_HEADER_IPV6 ETH_DMARXNDESCWBF_IPV6
983 /**
984 * @}
985 */
986
987 /** @defgroup ETH_Rx_Payload_Type ETH Rx Payload Type
988 * @{
989 */
990 #define ETH_IP_PAYLOAD_UNKNOWN ETH_DMARXNDESCWBF_PT_UNKNOWN
991 #define ETH_IP_PAYLOAD_UDP ETH_DMARXNDESCWBF_PT_UDP
992 #define ETH_IP_PAYLOAD_TCP ETH_DMARXNDESCWBF_PT_TCP
993 #define ETH_IP_PAYLOAD_ICMPN ETH_DMARXNDESCWBF_PT_ICMP
994 /**
995 * @}
996 */
997
998 /** @defgroup ETH_Rx_MAC_Filter_Status ETH Rx MAC Filter Status
999 * @{
1000 */
1001 #define ETH_HASH_FILTER_PASS ETH_DMARXNDESCWBF_HF
1002 #define ETH_VLAN_FILTER_PASS ETH_DMARXNDESCWBF_VF
1003 #define ETH_DEST_ADDRESS_FAIL ETH_DMARXNDESCWBF_DAF
1004 #define ETH_SOURCE_ADDRESS_FAIL ETH_DMARXNDESCWBF_SAF
1005 /**
1006 * @}
1007 */
1008
1009 /** @defgroup ETH_Rx_L3_Filter_Status ETH Rx L3 Filter Status
1010 * @{
1011 */
1012 #define ETH_L3_FILTER0_MATCH ETH_DMARXNDESCWBF_L3FM
1013 #define ETH_L3_FILTER1_MATCH (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM)
1014 /**
1015 * @}
1016 */
1017
1018 /** @defgroup ETH_Rx_L4_Filter_Status ETH Rx L4 Filter Status
1019 * @{
1020 */
1021 #define ETH_L4_FILTER0_MATCH ETH_DMARXNDESCWBF_L4FM
1022 #define ETH_L4_FILTER1_MATCH (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM)
1023 /**
1024 * @}
1025 */
1026
1027 /** @defgroup ETH_Rx_Error_Code ETH Rx Error Code
1028 * @{
1029 */
1030 #define ETH_DRIBBLE_BIT_ERROR ETH_DMARXNDESCWBF_DE
1031 #define ETH_RECEIVE_ERROR ETH_DMARXNDESCWBF_RE
1032 #define ETH_RECEIVE_OVERFLOW ETH_DMARXNDESCWBF_OE
1033 #define ETH_WATCHDOG_TIMEOUT ETH_DMARXNDESCWBF_RWT
1034 #define ETH_GIANT_PACKET ETH_DMARXNDESCWBF_GP
1035 #define ETH_CRC_ERROR ETH_DMARXNDESCWBF_CE
1036 /**
1037 * @}
1038 */
1039
1040 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
1041 * @{
1042 */
1043 #define ETH_DMAARBITRATION_RX ETH_DMAMR_DA
1044 #define ETH_DMAARBITRATION_RX1_TX1 ((uint32_t)0x00000000U)
1045 #define ETH_DMAARBITRATION_RX2_TX1 ETH_DMAMR_PR_2_1
1046 #define ETH_DMAARBITRATION_RX3_TX1 ETH_DMAMR_PR_3_1
1047 #define ETH_DMAARBITRATION_RX4_TX1 ETH_DMAMR_PR_4_1
1048 #define ETH_DMAARBITRATION_RX5_TX1 ETH_DMAMR_PR_5_1
1049 #define ETH_DMAARBITRATION_RX6_TX1 ETH_DMAMR_PR_6_1
1050 #define ETH_DMAARBITRATION_RX7_TX1 ETH_DMAMR_PR_7_1
1051 #define ETH_DMAARBITRATION_RX8_TX1 ETH_DMAMR_PR_8_1
1052 #define ETH_DMAARBITRATION_TX (ETH_DMAMR_TXPR | ETH_DMAMR_DA)
1053 #define ETH_DMAARBITRATION_TX1_RX1 ((uint32_t)0x00000000U)
1054 #define ETH_DMAARBITRATION_TX2_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_2_1)
1055 #define ETH_DMAARBITRATION_TX3_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_3_1)
1056 #define ETH_DMAARBITRATION_TX4_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_4_1)
1057 #define ETH_DMAARBITRATION_TX5_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_5_1)
1058 #define ETH_DMAARBITRATION_TX6_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_6_1)
1059 #define ETH_DMAARBITRATION_TX7_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_7_1)
1060 #define ETH_DMAARBITRATION_TX8_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_8_1)
1061 /**
1062 * @}
1063 */
1064
1065 /** @defgroup ETH_Burst_Mode ETH Burst Mode
1066 * @{
1067 */
1068 #define ETH_BURSTLENGTH_FIXED ETH_DMASBMR_FB
1069 #define ETH_BURSTLENGTH_MIXED ETH_DMASBMR_MB
1070 #define ETH_BURSTLENGTH_UNSPECIFIED ((uint32_t)0x00000000U)
1071 /**
1072 * @}
1073 */
1074
1075 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
1076 * @{
1077 */
1078 #define ETH_TXDMABURSTLENGTH_1BEAT ETH_DMACTCR_TPBL_1PBL
1079 #define ETH_TXDMABURSTLENGTH_2BEAT ETH_DMACTCR_TPBL_2PBL
1080 #define ETH_TXDMABURSTLENGTH_4BEAT ETH_DMACTCR_TPBL_4PBL
1081 #define ETH_TXDMABURSTLENGTH_8BEAT ETH_DMACTCR_TPBL_8PBL
1082 #define ETH_TXDMABURSTLENGTH_16BEAT ETH_DMACTCR_TPBL_16PBL
1083 #define ETH_TXDMABURSTLENGTH_32BEAT ETH_DMACTCR_TPBL_32PBL
1084 /**
1085 * @}
1086 */
1087
1088 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
1089 * @{
1090 */
1091 #define ETH_RXDMABURSTLENGTH_1BEAT ETH_DMACRCR_RPBL_1PBL
1092 #define ETH_RXDMABURSTLENGTH_2BEAT ETH_DMACRCR_RPBL_2PBL
1093 #define ETH_RXDMABURSTLENGTH_4BEAT ETH_DMACRCR_RPBL_4PBL
1094 #define ETH_RXDMABURSTLENGTH_8BEAT ETH_DMACRCR_RPBL_8PBL
1095 #define ETH_RXDMABURSTLENGTH_16BEAT ETH_DMACRCR_RPBL_16PBL
1096 #define ETH_RXDMABURSTLENGTH_32BEAT ETH_DMACRCR_RPBL_32PBL
1097 /**
1098 * @}
1099 */
1100
1101 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
1102 * @{
1103 */
1104 #define ETH_DMA_NORMAL_IT ETH_DMACIER_NIE
1105 #define ETH_DMA_ABNORMAL_IT ETH_DMACIER_AIE
1106 #define ETH_DMA_CONTEXT_DESC_ERROR_IT ETH_DMACIER_CDEE
1107 #define ETH_DMA_FATAL_BUS_ERROR_IT ETH_DMACIER_FBEE
1108 #define ETH_DMA_EARLY_RX_IT ETH_DMACIER_ERIE
1109 #define ETH_DMA_EARLY_TX_IT ETH_DMACIER_ETIE
1110 #define ETH_DMA_RX_WATCHDOG_TIMEOUT_IT ETH_DMACIER_RWTE
1111 #define ETH_DMA_RX_PROCESS_STOPPED_IT ETH_DMACIER_RSE
1112 #define ETH_DMA_RX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_RBUE
1113 #define ETH_DMA_RX_IT ETH_DMACIER_RIE
1114 #define ETH_DMA_TX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_TBUE
1115 #define ETH_DMA_TX_PROCESS_STOPPED_IT ETH_DMACIER_TXSE
1116 #define ETH_DMA_TX_IT ETH_DMACIER_TIE
1117 /**
1118 * @}
1119 */
1120
1121 /** @defgroup ETH_DMA_Status_Flags ETH DMA Status Flags
1122 * @{
1123 */
1124 #define ETH_DMA_RX_NO_ERROR_FLAG ((uint32_t)0x00000000U)
1125 #define ETH_DMA_RX_DESC_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1 | ETH_DMACSR_REB_BIT_0)
1126 #define ETH_DMA_RX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1)
1127 #define ETH_DMA_RX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_0)
1128 #define ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_REB_BIT_2
1129 #define ETH_DMA_TX_NO_ERROR_FLAG ((uint32_t)0x00000000U)
1130 #define ETH_DMA_TX_DESC_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1 | ETH_DMACSR_TEB_BIT_0)
1131 #define ETH_DMA_TX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1)
1132 #define ETH_DMA_TX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_0)
1133 #define ETH_DMA_TX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_TEB_BIT_2
1134 #define ETH_DMA_CONTEXT_DESC_ERROR_FLAG ETH_DMACSR_CDE
1135 #define ETH_DMA_FATAL_BUS_ERROR_FLAG ETH_DMACSR_FBE
1136 #define ETH_DMA_EARLY_TX_IT_FLAG ETH_DMACSR_ERI
1137 #define ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG ETH_DMACSR_RWT
1138 #define ETH_DMA_RX_PROCESS_STOPPED_FLAG ETH_DMACSR_RPS
1139 #define ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG ETH_DMACSR_RBU
1140 #define ETH_DMA_TX_PROCESS_STOPPED_FLAG ETH_DMACSR_TPS
1141 /**
1142 * @}
1143 */
1144
1145 /** @defgroup ETH_Transmit_Mode ETH Transmit Mode
1146 * @{
1147 */
1148 #define ETH_TRANSMITSTOREFORWARD ETH_MTLTQOMR_TSF
1149 #define ETH_TRANSMITTHRESHOLD_32 ETH_MTLTQOMR_TTC_32BITS
1150 #define ETH_TRANSMITTHRESHOLD_64 ETH_MTLTQOMR_TTC_64BITS
1151 #define ETH_TRANSMITTHRESHOLD_96 ETH_MTLTQOMR_TTC_96BITS
1152 #define ETH_TRANSMITTHRESHOLD_128 ETH_MTLTQOMR_TTC_128BITS
1153 #define ETH_TRANSMITTHRESHOLD_192 ETH_MTLTQOMR_TTC_192BITS
1154 #define ETH_TRANSMITTHRESHOLD_256 ETH_MTLTQOMR_TTC_256BITS
1155 #define ETH_TRANSMITTHRESHOLD_384 ETH_MTLTQOMR_TTC_384BITS
1156 #define ETH_TRANSMITTHRESHOLD_512 ETH_MTLTQOMR_TTC_512BITS
1157 /**
1158 * @}
1159 */
1160
1161 /** @defgroup ETH_Receive_Mode ETH Receive Mode
1162 * @{
1163 */
1164 #define ETH_RECEIVESTOREFORWARD ETH_MTLRQOMR_RSF
1165 #define ETH_RECEIVETHRESHOLD8_64 ETH_MTLRQOMR_RTC_64BITS
1166 #define ETH_RECEIVETHRESHOLD8_32 ETH_MTLRQOMR_RTC_32BITS
1167 #define ETH_RECEIVETHRESHOLD8_96 ETH_MTLRQOMR_RTC_96BITS
1168 #define ETH_RECEIVETHRESHOLD8_128 ETH_MTLRQOMR_RTC_128BITS
1169 /**
1170 * @}
1171 */
1172
1173 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
1174 * @{
1175 */
1176 #define ETH_PAUSELOWTHRESHOLD_MINUS_4 ETH_MACTFCR_PLT_MINUS4
1177 #define ETH_PAUSELOWTHRESHOLD_MINUS_28 ETH_MACTFCR_PLT_MINUS28
1178 #define ETH_PAUSELOWTHRESHOLD_MINUS_36 ETH_MACTFCR_PLT_MINUS36
1179 #define ETH_PAUSELOWTHRESHOLD_MINUS_144 ETH_MACTFCR_PLT_MINUS144
1180 #define ETH_PAUSELOWTHRESHOLD_MINUS_256 ETH_MACTFCR_PLT_MINUS256
1181 #define ETH_PAUSELOWTHRESHOLD_MINUS_512 ETH_MACTFCR_PLT_MINUS512
1182 /**
1183 * @}
1184 */
1185
1186 /** @defgroup ETH_Watchdog_Timeout ETH Watchdog Timeout
1187 * @{
1188 */
1189 #define ETH_WATCHDOGTIMEOUT_2KB ETH_MACWTR_WTO_2KB
1190 #define ETH_WATCHDOGTIMEOUT_3KB ETH_MACWTR_WTO_3KB
1191 #define ETH_WATCHDOGTIMEOUT_4KB ETH_MACWTR_WTO_4KB
1192 #define ETH_WATCHDOGTIMEOUT_5KB ETH_MACWTR_WTO_5KB
1193 #define ETH_WATCHDOGTIMEOUT_6KB ETH_MACWTR_WTO_6KB
1194 #define ETH_WATCHDOGTIMEOUT_7KB ETH_MACWTR_WTO_7KB
1195 #define ETH_WATCHDOGTIMEOUT_8KB ETH_MACWTR_WTO_8KB
1196 #define ETH_WATCHDOGTIMEOUT_9KB ETH_MACWTR_WTO_9KB
1197 #define ETH_WATCHDOGTIMEOUT_10KB ETH_MACWTR_WTO_10KB
1198 #define ETH_WATCHDOGTIMEOUT_11KB ETH_MACWTR_WTO_12KB
1199 #define ETH_WATCHDOGTIMEOUT_12KB ETH_MACWTR_WTO_12KB
1200 #define ETH_WATCHDOGTIMEOUT_13KB ETH_MACWTR_WTO_13KB
1201 #define ETH_WATCHDOGTIMEOUT_14KB ETH_MACWTR_WTO_14KB
1202 #define ETH_WATCHDOGTIMEOUT_15KB ETH_MACWTR_WTO_15KB
1203 #define ETH_WATCHDOGTIMEOUT_16KB ETH_MACWTR_WTO_16KB
1204 /**
1205 * @}
1206 */
1207
1208 /** @defgroup ETH_Inter_Packet_Gap ETH Inter Packet Gap
1209 * @{
1210 */
1211 #define ETH_INTERPACKETGAP_96BIT ETH_MACCR_IPG_96BIT
1212 #define ETH_INTERPACKETGAP_88BIT ETH_MACCR_IPG_88BIT
1213 #define ETH_INTERPACKETGAP_80BIT ETH_MACCR_IPG_80BIT
1214 #define ETH_INTERPACKETGAP_72BIT ETH_MACCR_IPG_72BIT
1215 #define ETH_INTERPACKETGAP_64BIT ETH_MACCR_IPG_64BIT
1216 #define ETH_INTERPACKETGAP_56BIT ETH_MACCR_IPG_56BIT
1217 #define ETH_INTERPACKETGAP_48BIT ETH_MACCR_IPG_48BIT
1218 #define ETH_INTERPACKETGAP_40BIT ETH_MACCR_IPG_40BIT
1219 /**
1220 * @}
1221 */
1222
1223 /** @defgroup ETH_Speed ETH Speed
1224 * @{
1225 */
1226 #define ETH_SPEED_10M ((uint32_t)0x00000000U)
1227 #define ETH_SPEED_100M ETH_MACCR_FES
1228 /**
1229 * @}
1230 */
1231
1232 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode
1233 * @{
1234 */
1235 #define ETH_FULLDUPLEX_MODE ETH_MACCR_DM
1236 #define ETH_HALFDUPLEX_MODE ((uint32_t)0x00000000U)
1237 /**
1238 * @}
1239 */
1240
1241 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
1242 * @{
1243 */
1244 #define ETH_BACKOFFLIMIT_10 ETH_MACCR_BL_10
1245 #define ETH_BACKOFFLIMIT_8 ETH_MACCR_BL_8
1246 #define ETH_BACKOFFLIMIT_4 ETH_MACCR_BL_4
1247 #define ETH_BACKOFFLIMIT_1 ETH_MACCR_BL_1
1248 /**
1249 * @}
1250 */
1251
1252 /** @defgroup ETH_Preamble_Length ETH Preamble Length
1253 * @{
1254 */
1255 #define ETH_PREAMBLELENGTH_7 ETH_MACCR_PRELEN_7
1256 #define ETH_PREAMBLELENGTH_5 ETH_MACCR_PRELEN_5
1257 #define ETH_PREAMBLELENGTH_3 ETH_MACCR_PRELEN_3
1258 /**
1259 * @}
1260 */
1261
1262 /** @defgroup ETH_Source_Addr_Control ETH Source Addr Control
1263 * @{
1264 */
1265 #define ETH_SOURCEADDRESS_DISABLE ((uint32_t)0x00000000U)
1266 #define ETH_SOURCEADDRESS_INSERT_ADDR0 ETH_MACCR_SARC_INSADDR0
1267 #define ETH_SOURCEADDRESS_INSERT_ADDR1 ETH_MACCR_SARC_INSADDR1
1268 #define ETH_SOURCEADDRESS_REPLACE_ADDR0 ETH_MACCR_SARC_REPADDR0
1269 #define ETH_SOURCEADDRESS_REPLACE_ADDR1 ETH_MACCR_SARC_REPADDR1
1270 /**
1271 * @}
1272 */
1273
1274 /** @defgroup ETH_Control_Packets_Filter ETH Control Packets Filter
1275 * @{
1276 */
1277 #define ETH_CTRLPACKETS_BLOCK_ALL ETH_MACPFR_PCF_BLOCKALL
1278 #define ETH_CTRLPACKETS_FORWARD_ALL_EXCEPT_PA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA
1279 #define ETH_CTRLPACKETS_FORWARD_ALL ETH_MACPFR_PCF_FORWARDALL
1280 #define ETH_CTRLPACKETS_FORWARD_PASSED_ADDR_FILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER
1281 /**
1282 * @}
1283 */
1284
1285 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
1286 * @{
1287 */
1288 #define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U)
1289 #define ETH_VLANTAGCOMPARISON_12BIT ETH_MACVTR_ETV
1290 /**
1291 * @}
1292 */
1293
1294 /** @defgroup ETH_MAC_addresses ETH MAC addresses
1295 * @{
1296 */
1297 #define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000U)
1298 #define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008U)
1299 #define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010U)
1300 #define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018U)
1301 /**
1302 * @}
1303 */
1304
1305 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
1306 * @{
1307 */
1308 #define ETH_MAC_RX_STATUS_IT ETH_MACIER_RXSTSIE
1309 #define ETH_MAC_TX_STATUS_IT ETH_MACIER_TXSTSIE
1310 #define ETH_MAC_TIMESTAMP_IT ETH_MACIER_TSIE
1311 #define ETH_MAC_LPI_IT ETH_MACIER_LPIIE
1312 #define ETH_MAC_PMT_IT ETH_MACIER_PMTIE
1313 #define ETH_MAC_PHY_IT ETH_MACIER_PHYIE
1314 /**
1315 * @}
1316 */
1317
1318 /** @defgroup ETH_MAC_Wake_Up_Event ETH MAC Wake Up Event
1319 * @{
1320 */
1321 #define ETH_WAKEUP_PACKET_RECIEVED ETH_MACPCSR_RWKPRCVD
1322 #define ETH_MAGIC_PACKET_RECIEVED ETH_MACPCSR_MGKPRCVD
1323 /**
1324 * @}
1325 */
1326
1327 /** @defgroup ETH_MAC_Rx_Tx_Status ETH MAC Rx Tx Status
1328 * @{
1329 */
1330 #define ETH_RECEIVE_WATCHDOG_TIMEOUT ETH_MACRXTXSR_RWT
1331 #define ETH_EXECESSIVE_COLLISIONS ETH_MACRXTXSR_EXCOL
1332 #define ETH_LATE_COLLISIONS ETH_MACRXTXSR_LCOL
1333 #define ETH_EXECESSIVE_DEFERRAL ETH_MACRXTXSR_EXDEF
1334 #define ETH_LOSS_OF_CARRIER ETH_MACRXTXSR_LCARR
1335 #define ETH_NO_CARRIER ETH_MACRXTXSR_NCARR
1336 #define ETH_TRANSMIT_JABBR_TIMEOUT ETH_MACRXTXSR_TJT
1337 /**
1338 * @}
1339 */
1340
1341 /** @defgroup HAL_ETH_StateTypeDef ETH States
1342 * @{
1343 */
1344 #define HAL_ETH_STATE_RESET ((uint32_t)0x00000000U) /*!< Peripheral not yet Initialized or disabled */
1345 #define HAL_ETH_STATE_READY ((uint32_t)0x00000010U) /*!< Peripheral Communication started */
1346 #define HAL_ETH_STATE_BUSY ((uint32_t)0x00000023U) /*!< an internal process is ongoing */
1347 #define HAL_ETH_STATE_BUSY_TX ((uint32_t)0x00000021U) /*!< Transmission process is ongoing */
1348 #define HAL_ETH_STATE_BUSY_RX ((uint32_t)0x00000022U) /*!< Reception process is ongoing */
1349 #define HAL_ETH_STATE_ERROR ((uint32_t)0x000000E0U) /*!< Error State */
1350 /**
1351 * @}
1352 */
1353 /**
1354 * @}
1355 */
1356
1357 /* Exported macro ------------------------------------------------------------*/
1358 /** @defgroup ETH_Exported_Macros ETH Exported Macros
1359 * @{
1360 */
1361
1362 /** @brief Reset ETH handle state
1363 * @param __HANDLE__: specifies the ETH handle.
1364 * @retval None
1365 */
1366 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1367 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \
1368 (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \
1369 (__HANDLE__)->RxState = HAL_ETH_STATE_RESET; \
1370 (__HANDLE__)->MspInitCallback = NULL; \
1371 (__HANDLE__)->MspDeInitCallback = NULL; \
1372 } while(0)
1373 #else
1374 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \
1375 (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \
1376 (__HANDLE__)->RxState = HAL_ETH_STATE_RESET; \
1377 } while(0)
1378 #endif /*USE_HAL_ETH_REGISTER_CALLBACKS */
1379
1380 /**
1381 * @brief Enables the specified ETHERNET DMA interrupts.
1382 * @param __HANDLE__ : ETH Handle
1383 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
1384 * enabled @ref ETH_DMA_Interrupts
1385 * @retval None
1386 */
1387 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER |= (__INTERRUPT__))
1388
1389 /**
1390 * @brief Disables the specified ETHERNET DMA interrupts.
1391 * @param __HANDLE__ : ETH Handle
1392 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
1393 * disabled. @ref ETH_DMA_Interrupts
1394 * @retval None
1395 */
1396 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER &= ~(__INTERRUPT__))
1397
1398 /**
1399 * @brief Gets the ETHERNET DMA IT source enabled or disabled.
1400 * @param __HANDLE__ : ETH Handle
1401 * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
1402 * @retval The ETH DMA IT Source enabled or disabled
1403 */
1404 #define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMACIER & (__INTERRUPT__)) == (__INTERRUPT__))
1405
1406 /**
1407 * @brief Gets the ETHERNET DMA IT pending bit.
1408 * @param __HANDLE__ : ETH Handle
1409 * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
1410 * @retval The state of ETH DMA IT (SET or RESET)
1411 */
1412 #define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMACSR & (__INTERRUPT__)) == (__INTERRUPT__))
1413
1414 /**
1415 * @brief Clears the ETHERNET DMA IT pending bit.
1416 * @param __HANDLE__ : ETH Handle
1417 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
1418 * @retval None
1419 */
1420 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACSR = (__INTERRUPT__))
1421
1422 /**
1423 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
1424 * @param __HANDLE__: ETH Handle
1425 * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
1426 * @retval The state of ETH DMA FLAG (SET or RESET).
1427 */
1428 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMACSR &( __FLAG__)) == ( __FLAG__))
1429
1430 /**
1431 * @brief Clears the specified ETHERNET DMA flag.
1432 * @param __HANDLE__: ETH Handle
1433 * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
1434 * @retval The state of ETH DMA FLAG (SET or RESET).
1435 */
1436 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMACSR = ( __FLAG__))
1437
1438 /**
1439 * @brief Enables the specified ETHERNET MAC interrupts.
1440 * @param __HANDLE__ : ETH Handle
1441 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
1442 * enabled @ref ETH_MAC_Interrupts
1443 * @retval None
1444 */
1445 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__))
1446
1447 /**
1448 * @brief Disables the specified ETHERNET MAC interrupts.
1449 * @param __HANDLE__ : ETH Handle
1450 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
1451 * enabled @ref ETH_MAC_Interrupts
1452 * @retval None
1453 */
1454 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__))
1455
1456 /**
1457 * @brief Checks whether the specified ETHERNET MAC flag is set or not.
1458 * @param __HANDLE__: ETH Handle
1459 * @param __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts
1460 * @retval The state of ETH MAC IT (SET or RESET).
1461 */
1462 #define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MACISR &( __INTERRUPT__)) == ( __INTERRUPT__))
1463
1464 /*!< External interrupt line 86 Connected to the ETH wakeup EXTI Line */
1465 #define ETH_WAKEUP_EXTI_LINE ((uint32_t)0x00400000U) /* !< 86 - 64 = 22 */
1466
1467 /**
1468 * @brief Enable the ETH WAKEUP Exti Line.
1469 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled.
1470 * @arg ETH_WAKEUP_EXTI_LINE
1471 * @retval None.
1472 */
1473 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI_D1->IMR3 |= (__EXTI_LINE__))
1474
1475 /**
1476 * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not.
1477 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
1478 * @arg ETH_WAKEUP_EXTI_LINE
1479 * @retval EXTI ETH WAKEUP Line Status.
1480 */
1481 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 & (__EXTI_LINE__))
1482
1483 /**
1484 * @brief Clear the ETH WAKEUP Exti flag.
1485 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
1486 * @arg ETH_WAKEUP_EXTI_LINE
1487 * @retval None.
1488 */
1489 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 = (__EXTI_LINE__))
1490
1491 #if defined(DUAL_CORE)
1492 /**
1493 * @brief Enable the ETH WAKEUP Exti Line by Core2.
1494 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled.
1495 * @arg ETH_WAKEUP_EXTI_LINE
1496 * @retval None.
1497 */
1498 #define __HAL_ETH_WAKEUP_EXTID2_ENABLE_IT(__EXTI_LINE__) (EXTI_D2->IMR3 |= (__EXTI_LINE__))
1499
1500 /**
1501 * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not.
1502 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
1503 * @arg ETH_WAKEUP_EXTI_LINE
1504 * @retval EXTI ETH WAKEUP Line Status.
1505 */
1506 #define __HAL_ETH_WAKEUP_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI_D2->PR3 & (__EXTI_LINE__))
1507
1508 /**
1509 * @brief Clear the ETH WAKEUP Exti flag.
1510 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
1511 * @arg ETH_WAKEUP_EXTI_LINE
1512 * @retval None.
1513 */
1514 #define __HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D2->PR3 = (__EXTI_LINE__))
1515 #endif
1516
1517 /**
1518 * @brief enable rising edge interrupt on selected EXTI line.
1519 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
1520 * @arg ETH_WAKEUP_EXTI_LINE
1521 * @retval None
1522 */
1523 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR3 &= ~(__EXTI_LINE__)); \
1524 (EXTI->RTSR3 |= (__EXTI_LINE__))
1525
1526 /**
1527 * @brief enable falling edge interrupt on selected EXTI line.
1528 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
1529 * @arg ETH_WAKEUP_EXTI_LINE
1530 * @retval None
1531 */
1532 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 &= ~(__EXTI_LINE__));\
1533 (EXTI->FTSR3 |= (__EXTI_LINE__))
1534
1535 /**
1536 * @brief enable falling edge interrupt on selected EXTI line.
1537 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
1538 * @arg ETH_WAKEUP_EXTI_LINE
1539 * @retval None
1540 */
1541 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 |= (__EXTI_LINE__));\
1542 (EXTI->FTSR3 |= (__EXTI_LINE__))
1543
1544 /**
1545 * @brief Generates a Software interrupt on selected EXTI line.
1546 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
1547 * @arg ETH_WAKEUP_EXTI_LINE
1548 * @retval None
1549 */
1550 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER3 |= (__EXTI_LINE__))
1551
1552 /**
1553 * @}
1554 */
1555
1556 /* Include ETH HAL Extension module */
1557 #include "stm32h7xx_hal_eth_ex.h"
1558
1559 /* Exported functions --------------------------------------------------------*/
1560
1561 /** @addtogroup ETH_Exported_Functions
1562 * @{
1563 */
1564
1565 /** @addtogroup ETH_Exported_Functions_Group1
1566 * @{
1567 */
1568 /* Initialization and de initialization functions **********************************/
1569 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
1570 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
1571 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
1572 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
1573 HAL_StatusTypeDef HAL_ETH_DescAssignMemory(ETH_HandleTypeDef *heth, uint32_t Index, uint8_t *pBuffer1,uint8_t *pBuffer2);
1574
1575 /* Callbacks Register/UnRegister functions ***********************************/
1576 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1577 HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback);
1578 HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID);
1579 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1580
1581 /**
1582 * @}
1583 */
1584
1585 /** @addtogroup ETH_Exported_Functions_Group2
1586 * @{
1587 */
1588 /* IO operation functions *******************************************************/
1589 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
1590 HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth);
1591 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
1592 HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth);
1593
1594 uint8_t HAL_ETH_IsRxDataAvailable(ETH_HandleTypeDef *heth);
1595 HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer(ETH_HandleTypeDef *heth, ETH_BufferTypeDef *RxBuffer);
1596 HAL_StatusTypeDef HAL_ETH_GetRxDataLength(ETH_HandleTypeDef *heth, uint32_t *Length);
1597 HAL_StatusTypeDef HAL_ETH_GetRxDataInfo(ETH_HandleTypeDef *heth, ETH_RxPacketInfo *RxPacketInfo);
1598 HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth);
1599
1600 HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout);
1601 HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig);
1602
1603 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue);
1604 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue);
1605
1606 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
1607 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
1608 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
1609 void HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth);
1610 void HAL_ETH_MACErrorCallback(ETH_HandleTypeDef *heth);
1611 void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth);
1612 void HAL_ETH_EEECallback(ETH_HandleTypeDef *heth);
1613 void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth);
1614 /**
1615 * @}
1616 */
1617
1618 /** @addtogroup ETH_Exported_Functions_Group3
1619 * @{
1620 */
1621 /* Peripheral Control functions **********************************************/
1622 /* MAC & DMA Configuration APIs **********************************************/
1623 HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
1624 HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
1625 HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
1626 HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
1627 void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth);
1628
1629 /* MAC VLAN Processing APIs ************************************************/
1630 void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier);
1631
1632 /* MAC L2 Packet Filtering APIs **********************************************/
1633 HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
1634 HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
1635 HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable);
1636 HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr);
1637
1638 /* MAC Power Down APIs *****************************************************/
1639 void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig);
1640 void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth);
1641 HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count);
1642
1643 /**
1644 * @}
1645 */
1646
1647 /** @addtogroup ETH_Exported_Functions_Group4
1648 * @{
1649 */
1650 /* Peripheral State functions **************************************************/
1651 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
1652 uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth);
1653 uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth);
1654 uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth);
1655 uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth);
1656 /**
1657 * @}
1658 */
1659
1660 /**
1661 * @}
1662 */
1663
1664 /**
1665 * @}
1666 */
1667
1668 /**
1669 * @}
1670 */
1671
1672 #endif /* ETH */
1673
1674 #ifdef __cplusplus
1675 }
1676 #endif
1677
1678 #endif /* STM32H7xx_HAL_ETH_H */
1679
1680
1681
1682 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/