Merge pull request #11270 from haslinghuis/rename_attr
[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_hal_i2s.h
blob66762f450aa1383fe5f0c595d7d129e7aeb4f304
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal_i2s.h
4 * @author MCD Application Team
5 * @brief Header file of I2S HAL module.
6 ******************************************************************************
7 * @attention
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
17 ******************************************************************************
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_HAL_I2S_H
22 #define STM32H7xx_HAL_I2S_H
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx_hal_def.h"
31 /** @addtogroup STM32H7xx_HAL_Driver
32 * @{
35 /** @addtogroup I2S
36 * @{
39 /* Exported types ------------------------------------------------------------*/
40 /** @defgroup I2S_Exported_Types I2S Exported Types
41 * @{
44 /**
45 * @brief I2S Init structure definition
47 typedef struct
49 uint32_t Mode; /*!< Specifies the I2S operating mode.
50 This parameter can be a value of @ref I2S_Mode */
52 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
53 This parameter can be a value of @ref I2S_Standard */
55 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
56 This parameter can be a value of @ref I2S_Data_Format */
58 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
59 This parameter can be a value of @ref I2S_MCLK_Output */
61 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
62 This parameter can be a value of @ref I2S_Audio_Frequency */
64 uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
65 This parameter can be a value of @ref I2S_Clock_Polarity */
67 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
68 This parameter can be a value of @ref I2S_MSB_LSB_Transmission */
70 uint32_t WSInversion; /*!< Control the Word Select Inversion.
71 This parameter can be a value of @ref I2S_WSInversion */
73 uint32_t Data24BitAlignment; /*!< Specifies the Data Padding for 24 bits data length
74 This parameter can be a value of @ref I2S_Data_24Bit_Alignment */
76 uint32_t MasterKeepIOState; /*!< Control of Alternate function GPIOs state
77 This parameter can be a value of @ref I2S_Master_Keep_IO_State */
79 } I2S_InitTypeDef;
81 /**
82 * @brief HAL State structures definition
84 typedef enum
86 HAL_I2S_STATE_RESET = 0x00UL, /*!< I2S not yet initialized or disabled */
87 HAL_I2S_STATE_READY = 0x01UL, /*!< I2S initialized and ready for use */
88 HAL_I2S_STATE_BUSY = 0x02UL, /*!< I2S internal process is ongoing */
89 HAL_I2S_STATE_BUSY_TX = 0x03UL, /*!< Data Transmission process is ongoing */
90 HAL_I2S_STATE_BUSY_RX = 0x04UL, /*!< Data Reception process is ongoing */
91 HAL_I2S_STATE_BUSY_TX_RX = 0x05UL, /*!< Data Transmission and Reception process is ongoing */
92 HAL_I2S_STATE_TIMEOUT = 0x06UL, /*!< I2S timeout state */
93 HAL_I2S_STATE_ERROR = 0x07UL /*!< I2S error state */
94 } HAL_I2S_StateTypeDef;
96 /**
97 * @brief I2S handle Structure definition
99 typedef struct __I2S_HandleTypeDef
101 SPI_TypeDef *Instance; /*!< I2S registers base address */
103 I2S_InitTypeDef Init; /*!< I2S communication parameters */
105 uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
107 __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
109 __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
111 uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
113 __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
115 __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
116 (This field is initialized at the
117 same value as transfer size at the
118 beginning of the transfer and
119 decremented when a sample is received
120 NbSamplesReceived = RxBufferSize-RxBufferCount) */
122 void (*RxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Rx ISR */
124 void (*TxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Tx ISR */
126 DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
128 DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
130 __IO HAL_LockTypeDef Lock; /*!< I2S locking object */
132 __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
134 __IO uint32_t ErrorCode; /*!< I2S Error code
135 This parameter can be a value of @ref I2S_Error */
137 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
138 void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */
139 void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */
140 void (* TxRxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S TxRx Completed callback */
141 void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */
142 void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */
143 void (* TxRxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S TxRx Half Completed callback */
144 void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */
145 void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */
146 void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */
148 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
149 } I2S_HandleTypeDef;
151 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
154 * @brief HAL I2S Callback ID enumeration definition
156 typedef enum
158 HAL_I2S_TX_COMPLETE_CB_ID = 0x00UL, /*!< I2S Tx Completed callback ID */
159 HAL_I2S_RX_COMPLETE_CB_ID = 0x01UL, /*!< I2S Rx Completed callback ID */
160 HAL_I2S_TX_RX_COMPLETE_CB_ID = 0x02UL, /*!< I2S TxRx Completed callback ID */
161 HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03UL, /*!< I2S Tx Half Completed callback ID */
162 HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04UL, /*!< I2S Rx Half Completed callback ID */
163 HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID = 0x05UL, /*!< I2S TxRx Half Completed callback ID */
164 HAL_I2S_ERROR_CB_ID = 0x06UL, /*!< I2S Error callback ID */
165 HAL_I2S_MSPINIT_CB_ID = 0x07UL, /*!< I2S Msp Init callback ID */
166 HAL_I2S_MSPDEINIT_CB_ID = 0x08UL /*!< I2S Msp DeInit callback ID */
168 } HAL_I2S_CallbackIDTypeDef;
171 * @brief HAL I2S Callback pointer definition
173 typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */
175 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
177 * @}
180 /* Exported constants --------------------------------------------------------*/
181 /** @defgroup I2S_Exported_Constants I2S Exported Constants
182 * @{
184 /** @defgroup I2S_Error I2S Error
185 * @{
187 #define HAL_I2S_ERROR_NONE (0x00000000UL) /*!< No error */
188 #define HAL_I2S_ERROR_TIMEOUT (0x00000001UL) /*!< Timeout error */
189 #define HAL_I2S_ERROR_OVR (0x00000002UL) /*!< OVR error */
190 #define HAL_I2S_ERROR_UDR (0x00000004UL) /*!< UDR error */
191 #define HAL_I2S_ERROR_DMA (0x00000008UL) /*!< DMA transfer error */
192 #define HAL_I2S_ERROR_PRESCALER (0x00000010UL) /*!< Prescaler Calculation error */
193 #define HAL_I2S_ERROR_FRE (0x00000020UL) /*!< FRE error */
194 #define HAL_I2S_ERROR_NO_OGT (0x00000040UL) /*!< No On Going Transfer error */
195 #define HAL_I2S_ERROR_NOT_SUPPORTED (0x00000080UL) /*!< Requested operation not supported */
196 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
197 #define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000100UL) /*!< Invalid Callback error */
198 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
200 * @}
203 /** @defgroup I2S_Mode I2S Mode
204 * @{
206 #define I2S_MODE_SLAVE_TX (0x00000000UL)
207 #define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
208 #define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
209 #define I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)
210 #define I2S_MODE_SLAVE_FULLDUPLEX (SPI_I2SCFGR_I2SCFG_2)
211 #define I2S_MODE_MASTER_FULLDUPLEX (SPI_I2SCFGR_I2SCFG_2 | SPI_I2SCFGR_I2SCFG_0)
213 * @}
216 /** @defgroup I2S_Standard I2S Standard
217 * @{
219 #define I2S_STANDARD_PHILIPS (0x00000000UL)
220 #define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
221 #define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
222 #define I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)
223 #define I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)
225 * @}
228 /** @defgroup I2S_Data_Format I2S Data Format
229 * @{
231 #define I2S_DATAFORMAT_16B (0x00000000UL)
232 #define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
233 #define I2S_DATAFORMAT_24B (SPI_I2SCFGR_DATLEN_0)
234 #define I2S_DATAFORMAT_32B (SPI_I2SCFGR_DATLEN_1)
236 * @}
239 /** @defgroup I2S_MCLK_Output I2S MCLK Output
240 * @{
242 #define I2S_MCLKOUTPUT_ENABLE (SPI_I2SCFGR_MCKOE)
243 #define I2S_MCLKOUTPUT_DISABLE (0x00000000UL)
245 * @}
248 /** @defgroup I2S_Audio_Frequency I2S Audio Frequency
249 * @{
251 #define I2S_AUDIOFREQ_192K (192000UL)
252 #define I2S_AUDIOFREQ_96K (96000UL)
253 #define I2S_AUDIOFREQ_48K (48000UL)
254 #define I2S_AUDIOFREQ_44K (44100UL)
255 #define I2S_AUDIOFREQ_32K (32000UL)
256 #define I2S_AUDIOFREQ_22K (22050UL)
257 #define I2S_AUDIOFREQ_16K (16000UL)
258 #define I2S_AUDIOFREQ_11K (11025UL)
259 #define I2S_AUDIOFREQ_8K (8000UL)
260 #define I2S_AUDIOFREQ_DEFAULT (2UL)
262 * @}
265 /** @defgroup I2S_Clock_Polarity I2S FullDuplex Mode
266 * @{
268 #define I2S_CPOL_LOW (0x00000000UL)
269 #define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)
271 * @}
274 /** @defgroup I2S_MSB_LSB_Transmission I2S MSB LSB Transmission
275 * @{
277 #define I2S_FIRSTBIT_MSB (0x00000000UL)
278 #define I2S_FIRSTBIT_LSB SPI_CFG2_LSBFRST
280 * @}
283 /** @defgroup I2S_WSInversion I2S Word Select Inversion
284 * @{
286 #define I2S_WS_INVERSION_DISABLE (0x00000000UL)
287 #define I2S_WS_INVERSION_ENABLE SPI_I2SCFGR_WSINV
289 * @}
292 /** @defgroup I2S_Data_24Bit_Alignment Data Padding 24Bit
293 * @{
295 #define I2S_DATA_24BIT_ALIGNMENT_RIGHT (0x00000000UL)
296 #define I2S_DATA_24BIT_ALIGNMENT_LEFT SPI_I2SCFGR_DATFMT
298 * @}
301 /** @defgroup I2S_Master_Keep_IO_State Keep IO State
302 * @{
304 #define I2S_MASTER_KEEP_IO_STATE_DISABLE (0x00000000U)
305 #define I2S_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR
307 * @}
310 /** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
311 * @{
313 #define I2S_IT_RXP SPI_IER_RXPIE
314 #define I2S_IT_TXP SPI_IER_TXPIE
315 #define I2S_IT_DXP SPI_IER_DXPIE
316 #define I2S_IT_UDR SPI_IER_UDRIE
317 #define I2S_IT_OVR SPI_IER_OVRIE
318 #define I2S_IT_FRE SPI_IER_TIFREIE
319 #define I2S_IT_ERR (SPI_IER_UDRIE | SPI_IER_OVRIE | SPI_IER_TIFREIE)
321 * @}
324 /** @defgroup I2S_Flags_Definition I2S Flags Definition
325 * @{
327 #define I2S_FLAG_RXP SPI_SR_RXP /* I2S status flag : Rx-Packet available flag */
328 #define I2S_FLAG_TXP SPI_SR_TXP /* I2S status flag : Tx-Packet space available flag */
329 #define I2S_FLAG_DXP SPI_SR_DXP /* I2S status flag : Dx-Packet space available flag */
330 #define I2S_FLAG_UDR SPI_SR_UDR /* I2S Error flag : Underrun flag */
331 #define I2S_FLAG_OVR SPI_SR_OVR /* I2S Error flag : Overrun flag */
332 #define I2S_FLAG_FRE SPI_SR_TIFRE /* I2S Error flag : TI mode frame format error flag */
334 #define I2S_FLAG_MASK (SPI_SR_RXP | SPI_SR_TXP | SPI_SR_DXP |SPI_SR_UDR | SPI_SR_OVR | SPI_SR_TIFRE)
336 * @}
340 * @}
343 /* Exported macros -----------------------------------------------------------*/
344 /** @defgroup I2S_Exported_macros I2S Exported Macros
345 * @{
348 /** @brief Reset I2S handle state
349 * @param __HANDLE__ specifies the I2S Handle.
350 * @retval None
352 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
353 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \
354 (__HANDLE__)->State = HAL_I2S_STATE_RESET; \
355 (__HANDLE__)->MspInitCallback = NULL; \
356 (__HANDLE__)->MspDeInitCallback = NULL; \
357 } while(0)
358 #else
359 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
360 #endif
362 /** @brief Enable the specified SPI peripheral (in I2S mode).
363 * @param __HANDLE__ specifies the I2S Handle.
364 * @retval None
366 #define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE))
368 /** @brief Disable the specified SPI peripheral (in I2S mode).
369 * @param __HANDLE__ specifies the I2S Handle.
370 * @retval None
372 #define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE))
374 /** @brief Enable the specified I2S interrupts.
375 * @param __HANDLE__ specifies the I2S Handle.
376 * This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
377 * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
378 * This parameter can be one of the following values:
379 * @arg I2S_IT_RXP : Rx-Packet available interrupt
380 * @arg I2S_IT_TXP : Tx-Packet space available interrupt
381 * @arg I2S_IT_UDR : Underrun interrupt
382 * @arg I2S_IT_OVR : Overrun interrupt
383 * @arg I2S_IT_FRE : TI mode frame format error interrupt
384 * @arg I2S_IT_ERR : Error interrupt enable
385 * @retval None
387 #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
389 /** @brief Disable the specified I2S interrupts.
390 * @param __HANDLE__ specifies the I2S Handle.
391 * This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
392 * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
393 * This parameter can be one of the following values:
394 * @arg I2S_IT_RXP : Rx-Packet available interrupt
395 * @arg I2S_IT_TXP : Tx-Packet space available interrupt
396 * @arg I2S_IT_UDR : Underrun interrupt
397 * @arg I2S_IT_OVR : Overrun interrupt
398 * @arg I2S_IT_FRE : TI mode frame format error interrupt
399 * @arg I2S_IT_ERR : Error interrupt enable
400 * @retval None
402 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
404 /** @brief Check if the specified I2S interrupt source is enabled or disabled.
405 * @param __HANDLE__ specifies the I2S Handle.
406 * This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
407 * @param __INTERRUPT__ specifies the I2S interrupt source to check.
408 * This parameter can be one of the following values:
409 * @arg I2S_IT_RXP : Rx-Packet available interrupt
410 * @arg I2S_IT_TXP : Tx-Packet space available interrupt
411 * @arg I2S_IT_DXP : Tx-Packet space available interrupt
412 * @arg I2S_IT_UDR : Underrun interrupt
413 * @arg I2S_IT_OVR : Overrun interrupt
414 * @arg I2S_IT_FRE : TI mode frame format error interrupt
415 * @arg I2S_IT_ERR : Error interrupt enable
416 * @retval The new state of __IT__ (TRUE or FALSE).
418 #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
420 /** @brief Check whether the specified I2S flag is set or not.
421 * @param __HANDLE__ specifies the I2S Handle.
422 * This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
423 * @param __FLAG__ specifies the flag to check.
424 * This parameter can be one of the following values:
425 * @arg I2S_FLAG_RXP : Rx-Packet available flag
426 * @arg I2S_FLAG_TXP : Tx-Packet space available flag
427 * @arg I2S_FLAG_UDR : Underrun flag
428 * @arg I2S_FLAG_OVR : Overrun flag
429 * @arg I2S_FLAG_FRE : TI mode frame format error flag
430 * @retval The new state of __FLAG__ (TRUE or FALSE).
432 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
434 /** @brief Clear the I2S OVR pending flag.
435 * @param __HANDLE__ specifies the I2S Handle.
436 * @retval None
438 #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
440 /** @brief Clear the I2S UDR pending flag.
441 * @param __HANDLE__ specifies the I2S Handle.
442 * @retval None
444 #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
446 /** @brief Clear the I2S FRE pending flag.
447 * @param __HANDLE__: specifies the I2S Handle.
448 * @retval None
450 #define __HAL_I2S_CLEAR_TIFREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
452 * @}
456 /* Exported functions --------------------------------------------------------*/
457 /** @addtogroup I2S_Exported_Functions
458 * @{
461 /** @addtogroup I2S_Exported_Functions_Group1
462 * @{
464 /* Initialization/de-initialization functions ********************************/
465 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
466 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s);
467 void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
468 void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
470 /* Callbacks Register/UnRegister functions ***********************************/
471 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
472 HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback);
473 HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
474 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
476 * @}
479 /** @addtogroup I2S_Exported_Functions_Group2
480 * @{
482 /* I/O operation functions ***************************************************/
483 /* Blocking mode: Polling */
484 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
485 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
486 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
487 uint16_t Size, uint32_t Timeout);
489 /* Non-Blocking mode: Interrupt */
490 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
491 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
492 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
493 uint16_t Size);
495 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
497 /* Non-Blocking mode: DMA */
498 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
499 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
500 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
501 uint16_t Size);
503 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
504 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
505 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
507 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
508 void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
509 void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
510 void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
511 void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
512 void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
513 void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s);
514 void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
516 * @}
519 /** @addtogroup I2S_Exported_Functions_Group3
520 * @{
522 /* Peripheral Control and State functions ************************************/
523 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
524 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
526 * @}
530 * @}
533 /* Private types -------------------------------------------------------------*/
534 /* Private variables ---------------------------------------------------------*/
535 /* Private constants ---------------------------------------------------------*/
536 /** @defgroup I2S_Private_Constants I2S Private Constants
537 * @{
541 * @}
544 /* Private macros ------------------------------------------------------------*/
545 /** @defgroup I2S_Private_Macros I2S Private Macros
546 * @{
549 /** @brief Check whether the specified SPI flag is set or not.
550 * @param __SR__ copy of I2S SR register.
551 * @param __FLAG__ specifies the flag to check.
552 * This parameter can be one of the following values:
553 * @arg I2S_FLAG_RXP : Rx-Packet available flag
554 * @arg I2S_FLAG_TXP : Tx-Packet space available flag
555 * @arg I2S_FLAG_UDR : Underrun flag
556 * @arg I2S_FLAG_OVR : Overrun flag
557 * @arg I2S_FLAG_FRE : TI mode frame format error flag
558 * @retval SET or RESET.
560 #define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
562 /** @brief Check whether the specified SPI Interrupt is set or not.
563 * @param __IER__ copy of I2S IER register.
564 * @param __INTERRUPT__ specifies the SPI interrupt source to check.
565 * This parameter can be one of the following values:
566 * @arg I2S_IT_RXP : Rx-Packet available interrupt
567 * @arg I2S_IT_TXP : Tx-Packet space available interrupt
568 * @arg I2S_IT_UDR : Underrun interrupt
569 * @arg I2S_IT_OVR : Overrun interrupt
570 * @arg I2S_IT_FRE : TI mode frame format error interrupt
571 * @arg I2S_IT_ERR : Error interrupt enable
572 * @retval SET or RESET.
574 #define I2S_CHECK_IT_SOURCE(__IER__, __INTERRUPT__) ((((__IER__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
576 /** @brief Checks if I2S Mode parameter is in allowed range.
577 * @param __MODE__ specifies the I2S Mode.
578 * This parameter can be a value of @ref I2S_Mode
579 * @retval None
581 #define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
582 ((__MODE__) == I2S_MODE_SLAVE_RX) || \
583 ((__MODE__) == I2S_MODE_MASTER_TX) || \
584 ((__MODE__) == I2S_MODE_MASTER_RX) || \
585 ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX) || \
586 ((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX))
588 #define IS_I2S_MASTER(__MODE__) (((__MODE__) == I2S_MODE_MASTER_TX) || \
589 ((__MODE__) == I2S_MODE_MASTER_RX) || \
590 ((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX))
592 #define IS_I2S_SLAVE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
593 ((__MODE__) == I2S_MODE_SLAVE_RX) || \
594 ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX))
596 #define IS_I2S_FULLDUPLEX(__MODE__) (((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX) || \
597 ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX))
599 #define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \
600 ((__STANDARD__) == I2S_STANDARD_MSB) || \
601 ((__STANDARD__) == I2S_STANDARD_LSB) || \
602 ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
603 ((__STANDARD__) == I2S_STANDARD_PCM_LONG))
605 #define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \
606 ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
607 ((__FORMAT__) == I2S_DATAFORMAT_24B) || \
608 ((__FORMAT__) == I2S_DATAFORMAT_32B))
610 #define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
611 ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
613 #define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \
614 ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
615 ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
617 #define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
618 ((__CPOL__) == I2S_CPOL_HIGH))
620 #define IS_I2S_FIRST_BIT(__BIT__) (((__BIT__) == I2S_FIRSTBIT_MSB) || \
621 ((__BIT__) == I2S_FIRSTBIT_LSB))
623 #define IS_I2S_WS_INVERSION(__WSINV__) (((__WSINV__) == I2S_WS_INVERSION_DISABLE) || \
624 ((__WSINV__) == I2S_WS_INVERSION_ENABLE))
626 #define IS_I2S_DATA_24BIT_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == I2S_DATA_24BIT_ALIGNMENT_RIGHT) || \
627 ((__ALIGNMENT__) == I2S_DATA_24BIT_ALIGNMENT_LEFT))
629 #define IS_I2S_MASTER_KEEP_IO_STATE(__AFCNTR__) (((__AFCNTR__) == I2S_MASTER_KEEP_IO_STATE_DISABLE) || \
630 ((__AFCNTR__) == I2S_MASTER_KEEP_IO_STATE_ENABLE))
634 * @}
638 * @}
642 * @}
645 #ifdef __cplusplus
647 #endif
649 #endif /* STM32H7xx_HAL_I2S_H */
651 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/