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Merge pull request #11270 from haslinghuis/rename_attr
[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_hal_mdma.h
blobafd2aeb4e32b5f134f9cb4df5a0cd7ea67da0418
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal_mdma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_HAL_MDMA_H
22 #define STM32H7xx_HAL_MDMA_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx_hal_def.h"
30
31 /** @addtogroup STM32H7xx_HAL_Driver
32 * @{
33 */
34
35 /** @addtogroup MDMA
36 * @{
37 */
38
39 /* Exported types ------------------------------------------------------------*/
40
41 /** @defgroup MDMA_Exported_Types MDMA Exported Types
42 * @brief MDMA Exported Types
43 * @{
44 */
45
46 /**
47 * @brief MDMA Configuration Structure definition
48 */
49 typedef struct
50 {
51
52 uint32_t Request; /*!< Specifies the MDMA request.
53 This parameter can be a value of @ref MDMA_Request_selection*/
54
55 uint32_t TransferTriggerMode; /*!< Specifies the Trigger Transfer mode : each request triggers a :
56 a buffer transfer, a block transfer, a repeated block transfer or a linked list transfer
57 This parameter can be a value of @ref MDMA_Transfer_TriggerMode */
58
59 uint32_t Priority; /*!< Specifies the software priority for the MDMAy channelx.
60 This parameter can be a value of @ref MDMA_Priority_level */
61
62 uint32_t Endianness; /*!< Specifies if the MDMA transactions preserve the Little endianness.
63 This parameter can be a value of @ref MDMA_Endianness */
64
65 uint32_t SourceInc; /*!< Specifies if the Source increment mode .
66 This parameter can be a value of @ref MDMA_Source_increment_mode */
67
68 uint32_t DestinationInc; /*!< Specifies if the Destination increment mode .
69 This parameter can be a value of @ref MDMA_Destination_increment_mode */
70
71 uint32_t SourceDataSize; /*!< Specifies the source data size.
72 This parameter can be a value of @ref MDMA_Source_data_size */
73
74 uint32_t DestDataSize; /*!< Specifies the destination data size.
75 This parameter can be a value of @ref MDMA_Destination_data_size */
76
77
78 uint32_t DataAlignment; /*!< Specifies the source to destination Memory data packing/padding mode.
79 This parameter can be a value of @ref MDMA_data_Alignment */
80
81 uint32_t BufferTransferLength; /*!< Specifies the buffer Transfer Length (number of bytes),
82 this is the number of bytes to be transferred in a single transfer (1 byte to 128 bytes)*/
83
84 uint32_t SourceBurst; /*!< Specifies the Burst transfer configuration for the source memory transfers.
85 It specifies the amount of data to be transferred in a single non interruptable
86 transaction.
87 This parameter can be a value of @ref MDMA_Source_burst
88 @note : the burst may be FIXED/INCR based on SourceInc value ,
89 the BURST must be programmed as to ensure that the burst size will be lower than than
90 BufferTransferLength */
91
92 uint32_t DestBurst; /*!< Specifies the Burst transfer configuration for the destination memory transfers.
93 It specifies the amount of data to be transferred in a single non interruptable
94 transaction.
95 This parameter can be a value of @ref MDMA_Destination_burst
96 @note : the burst may be FIXED/INCR based on DestinationInc value ,
97 the BURST must be programmed as to ensure that the burst size will be lower than than
98 BufferTransferLength */
99
100 int32_t SourceBlockAddressOffset; /*!< this field specifies the Next block source address offset
101 signed value : if > 0 then increment the next block source Address by offset from where the last block ends
102 if < 0 then decrement the next block source Address by offset from where the last block ends
103 if == 0, the next block source address starts from where the last block ends
104 */
105
106
107 int32_t DestBlockAddressOffset; /*!< this field specifies the Next block destination address offset
108 signed value : if > 0 then increment the next block destination Address by offset from where the last block ends
109 if < 0 then decrement the next block destination Address by offset from where the last block ends
110 if == 0, the next block destination address starts from where the last block ends
111 */
112
113 }MDMA_InitTypeDef;
114
115 /**
116 * @brief HAL MDMA linked list node structure definition
117 * @note The Linked list node allows to define a new MDMA configuration
118 * (CTCR ,CBNDTR ,CSAR ,CDAR ,CBRUR, CLAR, CTBR, CMAR and CMDR registers).
119 * When CLAR register is configured to a non NULL value , each time a transfer ends,
120 * a new configuration (linked list node) is automatically loaded from the address given in CLAR register.
121 */
122 typedef struct
123 {
124 __IO uint32_t CTCR; /*!< New CTCR register configuration for the given MDMA linked list node */
125 __IO uint32_t CBNDTR; /*!< New CBNDTR register configuration for the given MDMA linked list node */
126 __IO uint32_t CSAR; /*!< New CSAR register configuration for the given MDMA linked list node */
127 __IO uint32_t CDAR; /*!< New CDAR register configuration for the given MDMA linked list node */
128 __IO uint32_t CBRUR; /*!< New CBRUR register configuration for the given MDMA linked list node */
129 __IO uint32_t CLAR; /*!< New CLAR register configuration for the given MDMA linked list node */
130 __IO uint32_t CTBR; /*!< New CTBR register configuration for the given MDMA linked list node */
131 __IO uint32_t Reserved; /*!< Reserved register */
132 __IO uint32_t CMAR; /*!< New CMAR register configuration for the given MDMA linked list node */
133 __IO uint32_t CMDR; /*!< New CMDR register configuration for the given MDMA linked list node */
134
135 }MDMA_LinkNodeTypeDef;
136
137 /**
138 * @brief HAL MDMA linked list node configuration structure definition
139 * @note used with HAL_MDMA_LinkedList_CreateNode function
140 */
141 typedef struct
142 {
143 MDMA_InitTypeDef Init; /*!< configuration of the specified MDMA Linked List Node */
144 uint32_t SrcAddress; /*!< The source memory address for the Linked list Node */
145 uint32_t DstAddress; /*!< The destination memory address for the Linked list Node */
146 uint32_t BlockDataLength; /*!< The data length of a block in bytes */
147 uint32_t BlockCount; /*!< The number of blocks to be transferred */
148
149 uint32_t PostRequestMaskAddress; /*!< specifies the address to be updated (written) with PostRequestMaskData after a request is served.
150 PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served */
151
152 uint32_t PostRequestMaskData; /*!< specifies the value to be written to PostRequestMaskAddress after a request is served.
153 PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served */
154
155
156 }MDMA_LinkNodeConfTypeDef;
157
158
159 /**
160 * @brief HAL MDMA State structure definition
161 */
162 typedef enum
163 {
164 HAL_MDMA_STATE_RESET = 0x00U, /*!< MDMA not yet initialized or disabled */
165 HAL_MDMA_STATE_READY = 0x01U, /*!< MDMA initialized and ready for use */
166 HAL_MDMA_STATE_BUSY = 0x02U, /*!< MDMA process is ongoing */
167 HAL_MDMA_STATE_ERROR = 0x03U, /*!< MDMA error state */
168 HAL_MDMA_STATE_ABORT = 0x04U, /*!< MDMA Abort state */
169
170 }HAL_MDMA_StateTypeDef;
171
172 /**
173 * @brief HAL MDMA Level Complete structure definition
174 */
175 typedef enum
176 {
177 HAL_MDMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
178 HAL_MDMA_BUFFER_TRANSFER = 0x01U, /*!< Buffer Transfer */
179 HAL_MDMA_BLOCK_TRANSFER = 0x02U, /*!< Block Transfer */
180 HAL_MDMA_REPEAT_BLOCK_TRANSFER = 0x03U /*!< repeat block Transfer */
181
182 }HAL_MDMA_LevelCompleteTypeDef;
183
184 /**
185 * @brief HAL MDMA Callbacks IDs structure definition
186 */
187 typedef enum
188 {
189 HAL_MDMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
190 HAL_MDMA_XFER_BUFFERCPLT_CB_ID = 0x01U, /*!< Buffer Transfer */
191 HAL_MDMA_XFER_BLOCKCPLT_CB_ID = 0x02U, /*!< Block Transfer */
192 HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID = 0x03U, /*!< Repeated Block Transfer */
193 HAL_MDMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */
194 HAL_MDMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */
195 HAL_MDMA_XFER_ALL_CB_ID = 0x06U /*!< All */
196
197 }HAL_MDMA_CallbackIDTypeDef;
198
199
200 /**
201 * @brief MDMA handle Structure definition
202 */
203 typedef struct __MDMA_HandleTypeDef
204 {
205 MDMA_Channel_TypeDef *Instance; /*!< Register base address */
206
207 MDMA_InitTypeDef Init; /*!< MDMA communication parameters */
208
209 HAL_LockTypeDef Lock; /*!< MDMA locking object */
210
211 __IO HAL_MDMA_StateTypeDef State; /*!< MDMA transfer state */
212
213 void *Parent; /*!< Parent object state */
214
215 void (* XferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer complete callback */
216
217 void (* XferBufferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA buffer transfer complete callback */
218
219 void (* XferBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA block transfer complete callback */
220
221 void (* XferRepeatBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA block transfer repeat callback */
222
223 void (* XferErrorCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer error callback */
224
225 void (* XferAbortCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer Abort callback */
226
227
228 MDMA_LinkNodeTypeDef *FirstLinkedListNodeAddress; /*!< specifies the first node address of the transfer list
229 (after the initial node defined by the Init struct)
230 this parameter is used internally by the MDMA driver
231 to construct the linked list node
232 */
233
234 MDMA_LinkNodeTypeDef *LastLinkedListNodeAddress; /*!< specifies the last node address of the transfer list
235 this parameter is used internally by the MDMA driver
236 to construct the linked list node
237 */
238 uint32_t LinkedListNodeCounter; /*!< Number of nodes in the MDMA linked list */
239
240 __IO uint32_t ErrorCode; /*!< MDMA Error code */
241
242 } MDMA_HandleTypeDef;
243
244 /**
245 * @}
246 */
247
248 /* Exported constants --------------------------------------------------------*/
249
250 /** @defgroup MDMA_Exported_Constants MDMA Exported Constants
251 * @brief MDMA Exported constants
252 * @{
253 */
254
255 /** @defgroup MDMA_Error_Codes MDMA Error Codes
256 * @brief MDMA Error Codes
257 * @{
258 */
259 #define HAL_MDMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
260 #define HAL_MDMA_ERROR_READ_XFER ((uint32_t)0x00000001U) /*!< Read Transfer error */
261 #define HAL_MDMA_ERROR_WRITE_XFER ((uint32_t)0x00000002U) /*!< Write Transfer error */
262 #define HAL_MDMA_ERROR_MASK_DATA ((uint32_t)0x00000004U) /*!< Error Mask Data error */
263 #define HAL_MDMA_ERROR_LINKED_LIST ((uint32_t)0x00000008U) /*!< Linked list Data error */
264 #define HAL_MDMA_ERROR_ALIGNMENT ((uint32_t)0x00000010U) /*!< Address/Size alignment error */
265 #define HAL_MDMA_ERROR_BLOCK_SIZE ((uint32_t)0x00000020U) /*!< Block Size error */
266 #define HAL_MDMA_ERROR_TIMEOUT ((uint32_t)0x00000040U) /*!< Timeout error */
267 #define HAL_MDMA_ERROR_NO_XFER ((uint32_t)0x00000080U) /*!< Abort or SW trigger requested with no Xfer ongoing */
268 #define HAL_MDMA_ERROR_BUSY ((uint32_t)0x00000100U) /*!< DeInit or SW trigger requested with Xfer ongoing */
269
270 /**
271 * @}
272 */
273
274 /** @defgroup MDMA_Request_selection MDMA Request selection
275 * @brief MDMA_Request_selection
276 * @{
277 */
278
279 #define MDMA_REQUEST_DMA1_Stream0_TC ((uint32_t)0x00000000U) /*!< MDMA HW request is DMA1 Stream 0 Transfer Complete Flag */
280 #define MDMA_REQUEST_DMA1_Stream1_TC ((uint32_t)0x00000001U) /*!< MDMA HW request is DMA1 Stream 1 Transfer Complete Flag */
281 #define MDMA_REQUEST_DMA1_Stream2_TC ((uint32_t)0x00000002U) /*!< MDMA HW request is DMA1 Stream 2 Transfer Complete Flag */
282 #define MDMA_REQUEST_DMA1_Stream3_TC ((uint32_t)0x00000003U) /*!< MDMA HW request is DMA1 Stream 3 Transfer Complete Flag */
283 #define MDMA_REQUEST_DMA1_Stream4_TC ((uint32_t)0x00000004U) /*!< MDMA HW request is DMA1 Stream 4 Transfer Complete Flag */
284 #define MDMA_REQUEST_DMA1_Stream5_TC ((uint32_t)0x00000005U) /*!< MDMA HW request is DMA1 Stream 5 Transfer Complete Flag */
285 #define MDMA_REQUEST_DMA1_Stream6_TC ((uint32_t)0x00000006U) /*!< MDMA HW request is DMA1 Stream 6 Transfer Complete Flag */
286 #define MDMA_REQUEST_DMA1_Stream7_TC ((uint32_t)0x00000007U) /*!< MDMA HW request is DMA1 Stream 7 Transfer Complete Flag */
287 #define MDMA_REQUEST_DMA2_Stream0_TC ((uint32_t)0x00000008U) /*!< MDMA HW request is DMA2 Stream 0 Transfer Complete Flag */
288 #define MDMA_REQUEST_DMA2_Stream1_TC ((uint32_t)0x00000009U) /*!< MDMA HW request is DMA2 Stream 1 Transfer Complete Flag */
289 #define MDMA_REQUEST_DMA2_Stream2_TC ((uint32_t)0x0000000AU) /*!< MDMA HW request is DMA2 Stream 2 Transfer Complete Flag */
290 #define MDMA_REQUEST_DMA2_Stream3_TC ((uint32_t)0x0000000BU) /*!< MDMA HW request is DMA2 Stream 3 Transfer Complete Flag */
291 #define MDMA_REQUEST_DMA2_Stream4_TC ((uint32_t)0x0000000CU) /*!< MDMA HW request is DMA2 Stream 4 Transfer Complete Flag */
292 #define MDMA_REQUEST_DMA2_Stream5_TC ((uint32_t)0x0000000DU) /*!< MDMA HW request is DMA2 Stream 5 Transfer Complete Flag */
293 #define MDMA_REQUEST_DMA2_Stream6_TC ((uint32_t)0x0000000EU) /*!< MDMA HW request is DMA2 Stream 6 Transfer Complete Flag */
294 #define MDMA_REQUEST_DMA2_Stream7_TC ((uint32_t)0x0000000FU) /*!< MDMA HW request is DMA2 Stream 7 Transfer Complete Flag */
295 #if defined (LTDC)
296 #define MDMA_REQUEST_LTDC_LINE_IT ((uint32_t)0x00000010U) /*!< MDMA HW request is LTDC Line interrupt Flag */
297 #endif /* LTDC */
298 #if defined (JPEG)
299 #define MDMA_REQUEST_JPEG_INFIFO_TH ((uint32_t)0x00000011U) /*!< MDMA HW request is JPEG Input FIFO threshold Flag */
300 #define MDMA_REQUEST_JPEG_INFIFO_NF ((uint32_t)0x00000012U) /*!< MDMA HW request is JPEG Input FIFO not full Flag */
301 #define MDMA_REQUEST_JPEG_OUTFIFO_TH ((uint32_t)0x00000013U) /*!< MDMA HW request is JPEG Output FIFO threshold Flag */
302 #define MDMA_REQUEST_JPEG_OUTFIFO_NE ((uint32_t)0x00000014U) /*!< MDMA HW request is JPEG Output FIFO not empty Flag */
303 #define MDMA_REQUEST_JPEG_END_CONVERSION ((uint32_t)0x00000015U) /*!< MDMA HW request is JPEG End of conversion Flag */
304 #endif /* JPEG */
305 #if defined (OCTOSPI1)
306 #define MDMA_REQUEST_OCTOSPI1_FIFO_TH ((uint32_t)0x00000016U) /*!< MDMA HW request is OCTOSPI1 FIFO threshold Flag */
307 #define MDMA_REQUEST_OCTOSPI1_TC ((uint32_t)0x00000017U) /*!< MDMA HW request is OCTOSPI1 Transfer complete Flag */
308 #endif /* OCTOSPI1 */
309 #if defined (QUADSPI)
310 #define MDMA_REQUEST_QUADSPI_FIFO_TH ((uint32_t)0x00000016U) /*!< MDMA HW request is QSPI FIFO threshold Flag */
311 #define MDMA_REQUEST_QUADSPI_TC ((uint32_t)0x00000017U) /*!< MDMA HW request is QSPI Transfer complete Flag */
312 #endif /* QUADSPI */
313 #define MDMA_REQUEST_DMA2D_CLUT_TC ((uint32_t)0x00000018U) /*!< MDMA HW request is DMA2D CLUT Transfer Complete Flag */
314 #define MDMA_REQUEST_DMA2D_TC ((uint32_t)0x00000019U) /*!< MDMA HW request is DMA2D Transfer Complete Flag */
315 #define MDMA_REQUEST_DMA2D_TW ((uint32_t)0x0000001AU) /*!< MDMA HW request is DMA2D Transfer Watermark Flag */
316
317 #if defined (DSI)
318 #define MDMA_REQUEST_DSI_TEARING_EFFECT ((uint32_t)0x0000001BU) /*!< MDMA HW request is DSI Tearing Effect Flag */
319 #define MDMA_REQUEST_DSI_END_REFRESH ((uint32_t)0x0000001CU) /*!< MDMA HW request is DSI End of refresh Flag */
320 #endif /* DSI */
321
322 #define MDMA_REQUEST_SDMMC1_END_DATA ((uint32_t)0x0000001DU) /*!< MDMA HW request is SDMMC1 End of Data Flag */
323
324 #define MDMA_REQUEST_SDMMC1_DMA_ENDBUFFER ((uint32_t)0x0000001EU) /*!< MDMA HW request is SDMMC1 Internal DMA buffer End Flag */
325 #define MDMA_REQUEST_SDMMC1_COMMAND_END ((uint32_t)0x0000001FU) /*!< MDMA HW request is SDMMC1 Command End Flag */
326
327 #if defined (OCTOSPI2)
328 #define MDMA_REQUEST_OCTOSPI2_FIFO_TH ((uint32_t)0x00000020U) /*!< MDMA HW request is OCTOSPI2 FIFO threshold Flag */
329 #define MDMA_REQUEST_OCTOSPI2_TC ((uint32_t)0x00000021U) /*!< MDMA HW request is OCTOSPI2 Transfer complete Flag */
330 #endif /* OCTOSPI2 */
331
332 #define MDMA_REQUEST_SW ((uint32_t)0x40000000U) /*!< MDMA SW request */
333
334 /**
335 * @}
336 */
337
338 /** @defgroup MDMA_Transfer_TriggerMode MDMA Transfer Trigger Mode
339 * @brief MDMA Transfer Trigger Mode
340 * @{
341 */
342 #define MDMA_BUFFER_TRANSFER ((uint32_t)0x00000000U) /*!< Each MDMA request (SW or HW) triggers a buffer transfer */
343 #define MDMA_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_0) /*!< Each MDMA request (SW or HW) triggers a block transfer */
344 #define MDMA_REPEAT_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_1) /*!< Each MDMA request (SW or HW) triggers a repeated block transfer */
345 #define MDMA_FULL_TRANSFER ((uint32_t)MDMA_CTCR_TRGM) /*!< Each MDMA request (SW or HW) triggers a Full transfer or a linked list transfer if any */
346
347 /**
348 * @}
349 */
350
351 /** @defgroup MDMA_Priority_level MDMA Priority level
352 * @brief MDMA Priority level
353 * @{
354 */
355 #define MDMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */
356 #define MDMA_PRIORITY_MEDIUM ((uint32_t)MDMA_CCR_PL_0) /*!< Priority level: Medium */
357 #define MDMA_PRIORITY_HIGH ((uint32_t)MDMA_CCR_PL_1) /*!< Priority level: High */
358 #define MDMA_PRIORITY_VERY_HIGH ((uint32_t)MDMA_CCR_PL) /*!< Priority level: Very High */
359
360 /**
361 * @}
362 */
363
364
365 /** @defgroup MDMA_Endianness MDMA Endianness
366 * @brief MDMA Endianness
367 * @{
368 */
369 #define MDMA_LITTLE_ENDIANNESS_PRESERVE ((uint32_t)0x00000000U) /*!< little endianness preserve */
370 #define MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_BEX) /*!< BYTEs endianness exchange when destination data size is > Byte */
371 #define MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX) /*!< HALF WORDs endianness exchange when destination data size is > HALF WORD */
372 #define MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_WEX) /*!< WORDs endianness exchange when destination data size is > DOUBLE WORD */
373
374 /**
375 * @}
376 */
377
378 /** @defgroup MDMA_Source_increment_mode MDMA Source increment mode
379 * @brief MDMA Source increment mode
380 * @{
381 */
382 #define MDMA_SRC_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */
383 #define MDMA_SRC_INC_BYTE ((uint32_t)MDMA_CTCR_SINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits) */
384 #define MDMA_SRC_INC_HALFWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */
385 #define MDMA_SRC_INC_WORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits) */
386 #define MDMA_SRC_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS) /*!< Source address pointer is incremented by a double Word (64 bits)) */
387 #define MDMA_SRC_DEC_BYTE ((uint32_t)MDMA_CTCR_SINC) /*!< Source address pointer is decremented by a BYTE (8 bits) */
388 #define MDMA_SRC_DEC_HALFWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */
389 #define MDMA_SRC_DEC_WORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits) */
390 #define MDMA_SRC_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS) /*!< Source address pointer is decremented by a double Word (64 bits)) */
391
392 /**
393 * @}
394 */
395
396 /** @defgroup MDMA_Destination_increment_mode MDMA Destination increment mode
397 * @brief MDMA Destination increment mode
398 * @{
399 */
400 #define MDMA_DEST_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */
401 #define MDMA_DEST_INC_BYTE ((uint32_t)MDMA_CTCR_DINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits) */
402 #define MDMA_DEST_INC_HALFWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */
403 #define MDMA_DEST_INC_WORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits) */
404 #define MDMA_DEST_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS) /*!< Source address pointer is incremented by a double Word (64 bits)) */
405 #define MDMA_DEST_DEC_BYTE ((uint32_t)MDMA_CTCR_DINC) /*!< Source address pointer is decremented by a BYTE (8 bits) */
406 #define MDMA_DEST_DEC_HALFWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */
407 #define MDMA_DEST_DEC_WORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits) */
408 #define MDMA_DEST_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS) /*!< Source address pointer is decremented by a double Word (64 bits)) */
409
410 /**
411 * @}
412 */
413
414 /** @defgroup MDMA_Source_data_size MDMA Source data size
415 * @brief MDMA Source data size
416 * @{
417 */
418 #define MDMA_SRC_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Source data size is Byte */
419 #define MDMA_SRC_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_SSIZE_0) /*!< Source data size is half word */
420 #define MDMA_SRC_DATASIZE_WORD ((uint32_t)MDMA_CTCR_SSIZE_1) /*!< Source data size is word */
421 #define MDMA_SRC_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_SSIZE) /*!< Source data size is double word */
422
423 /**
424 * @}
425 */
426
427 /** @defgroup MDMA_Destination_data_size MDMA Destination data size
428 * @brief MDMA Destination data size
429 * @{
430 */
431 #define MDMA_DEST_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Destination data size is Byte */
432 #define MDMA_DEST_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_DSIZE_0) /*!< Destination data size is half word */
433 #define MDMA_DEST_DATASIZE_WORD ((uint32_t)MDMA_CTCR_DSIZE_1) /*!< Destination data size is word */
434 #define MDMA_DEST_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_DSIZE) /*!< Destination data size is double word */
435
436 /**
437 * @}
438 */
439
440 /** @defgroup MDMA_data_Alignment MDMA data alignment
441 * @brief MDMA data alignment
442 * @{
443 */
444 #define MDMA_DATAALIGN_PACKENABLE ((uint32_t)MDMA_CTCR_PKE) /*!< The source data is packed/un-packed into the destination data size
445 All data are right aligned, in Little Endien mode. */
446 #define MDMA_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< Right Aligned, padded w/ 0s (default) */
447 #define MDMA_DATAALIGN_RIGHT_SIGNED ((uint32_t)MDMA_CTCR_PAM_0) /*!< Right Aligned, Sign extended ,
448 Note : this mode is allowed only if the Source data size is smaller than Destination data size */
449 #define MDMA_DATAALIGN_LEFT ((uint32_t)MDMA_CTCR_PAM_1) /*!< Left Aligned (padded with 0s) */
450
451 /**
452 * @}
453 */
454
455 /** @defgroup MDMA_Source_burst MDMA Source burst
456 * @brief MDMA Source burst
457 * @{
458 */
459 #define MDMA_SOURCE_BURST_SINGLE ((uint32_t)0x00000000U) /*!< single transfer */
460 #define MDMA_SOURCE_BURST_2BEATS ((uint32_t)MDMA_CTCR_SBURST_0) /*!< Burst 2 beats */
461 #define MDMA_SOURCE_BURST_4BEATS ((uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 4 beats */
462 #define MDMA_SOURCE_BURST_8BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 8 beats */
463 #define MDMA_SOURCE_BURST_16BEATS ((uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 16 beats */
464 #define MDMA_SOURCE_BURST_32BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 32 beats */
465 #define MDMA_SOURCE_BURST_64BEATS ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 64 beats */
466 #define MDMA_SOURCE_BURST_128BEATS ((uint32_t)MDMA_CTCR_SBURST) /*!< Burst 128 beats */
467
468 /**
469 * @}
470 */
471
472 /** @defgroup MDMA_Destination_burst MDMA Destination burst
473 * @brief MDMA Destination burst
474 * @{
475 */
476 #define MDMA_DEST_BURST_SINGLE ((uint32_t)0x00000000U) /*!< single transfer */
477 #define MDMA_DEST_BURST_2BEATS ((uint32_t)MDMA_CTCR_DBURST_0) /*!< Burst 2 beats */
478 #define MDMA_DEST_BURST_4BEATS ((uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 4 beats */
479 #define MDMA_DEST_BURST_8BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 8 beats */
480 #define MDMA_DEST_BURST_16BEATS ((uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 16 beats */
481 #define MDMA_DEST_BURST_32BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 32 beats */
482 #define MDMA_DEST_BURST_64BEATS ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 64 beats */
483 #define MDMA_DEST_BURST_128BEATS ((uint32_t)MDMA_CTCR_DBURST) /*!< Burst 128 beats */
484
485 /**
486 * @}
487 */
488
489 /** @defgroup MDMA_interrupt_enable_definitions MDMA interrupt enable definitions
490 * @brief MDMA interrupt enable definitions
491 * @{
492 */
493 #define MDMA_IT_TE ((uint32_t)MDMA_CCR_TEIE) /*!< Transfer Error interrupt */
494 #define MDMA_IT_CTC ((uint32_t)MDMA_CCR_CTCIE) /*!< Channel Transfer Complete interrupt */
495 #define MDMA_IT_BRT ((uint32_t)MDMA_CCR_BRTIE) /*!< Block Repeat Transfer interrupt */
496 #define MDMA_IT_BT ((uint32_t)MDMA_CCR_BTIE) /*!< Block Transfer interrupt */
497 #define MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE) /*!< Buffer Transfer Complete interrupt */
498
499 /**
500 * @}
501 */
502
503 /** @defgroup MDMA_flag_definitions MDMA flag definitions
504 * @brief MDMA flag definitions
505 * @{
506 */
507 #define MDMA_FLAG_TE ((uint32_t)MDMA_CISR_TEIF) /*!< Transfer Error flag */
508 #define MDMA_FLAG_CTC ((uint32_t)MDMA_CISR_CTCIF) /*!< Channel Transfer Complete flag */
509 #define MDMA_FLAG_BRT ((uint32_t)MDMA_CISR_BRTIF) /*!< Block Repeat Transfer complete flag */
510 #define MDMA_FLAG_BT ((uint32_t)MDMA_CISR_BTIF) /*!< Block Transfer complete flag */
511 #define MDMA_FLAG_BFTC ((uint32_t)MDMA_CISR_TCIF) /*!< BuFfer Transfer complete flag */
512 #define MDMA_FLAG_CRQA ((uint32_t)MDMA_CISR_CRQA) /*!< Channel ReQest Active flag */
513
514 /**
515 * @}
516 */
517
518 /**
519 * @}
520 */
521
522 /* Exported macro ------------------------------------------------------------*/
523
524 /** @defgroup MDMA_Exported_Macros MDMA Exported Macros
525 * @{
526 */
527
528 /**
529 * @brief Enable the specified MDMA Channel.
530 * @param __HANDLE__: MDMA handle
531 * @retval None
532 */
533 #define __HAL_MDMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= MDMA_CCR_EN)
534
535 /**
536 * @brief Disable the specified MDMA Channel.
537 * @param __HANDLE__: MDMA handle
538 * @retval None
539 */
540 #define __HAL_MDMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~MDMA_CCR_EN)
541
542 /**
543 * @brief Get the MDMA Channel pending flags.
544 * @param __HANDLE__: MDMA handle
545 * @param __FLAG__: Get the specified flag.
546 * This parameter can be any combination of the following values:
547 * @arg MDMA_FLAG_TE : Transfer Error flag.
548 * @arg MDMA_FLAG_CTC : Channel Transfer Complete flag.
549 * @arg MDMA_FLAG_BRT : Block Repeat Transfer flag.
550 * @arg MDMA_FLAG_BT : Block Transfer complete flag.
551 * @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.
552 * @arg MDMA_FLAG_CRQA : Channel ReQest Active flag.
553 * @retval The state of FLAG (SET or RESET).
554 */
555 #define __HAL_MDMA_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CISR & (__FLAG__))
556
557 /**
558 * @brief Clear the MDMA Stream pending flags.
559 * @param __HANDLE__: MDMA handle
560 * @param __FLAG__: specifies the flag to clear.
561 * This parameter can be any combination of the following values:
562 * @arg MDMA_FLAG_TE : Transfer Error flag.
563 * @arg MDMA_FLAG_CTC : Channel Transfer Complete flag.
564 * @arg MDMA_FLAG_BRT : Block Repeat Transfer flag.
565 * @arg MDMA_FLAG_BT : Block Transfer complete flag.
566 * @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.
567 * @retval None
568 */
569 #define __HAL_MDMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CIFCR = (__FLAG__))
570
571 /**
572 * @brief Enables the specified MDMA Channel interrupts.
573 * @param __HANDLE__: MDMA handle
574 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
575 * This parameter can be any combination of the following values:
576 * @arg MDMA_IT_TE : Transfer Error interrupt mask
577 * @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask
578 * @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask
579 * @arg MDMA_IT_BT : Block Transfer interrupt mask
580 * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask
581 * @retval None
582 */
583 #define __HAL_MDMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
584
585 /**
586 * @brief Disables the specified MDMA Channel interrupts.
587 * @param __HANDLE__: MDMA handle
588 * @param __INTERRUPT__: specifies the MDMA interrupt sources to be enabled or disabled.
589 * This parameter can be any combination of the following values:
590 * @arg MDMA_IT_TE : Transfer Error interrupt mask
591 * @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask
592 * @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask
593 * @arg MDMA_IT_BT : Block Transfer interrupt mask
594 * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask
595 * @retval None
596 */
597 #define __HAL_MDMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
598
599 /**
600 * @brief Checks whether the specified MDMA Channel interrupt is enabled or not.
601 * @param __HANDLE__: MDMA handle
602 * @param __INTERRUPT__: specifies the MDMA interrupt source to check.
603 * @arg MDMA_IT_TE : Transfer Error interrupt mask
604 * @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask
605 * @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask
606 * @arg MDMA_IT_BT : Block Transfer interrupt mask
607 * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask
608 * @retval The state of MDMA_IT (SET or RESET).
609 */
610 #define __HAL_MDMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
611
612 /**
613 * @brief Writes the number of data in bytes to be transferred on the MDMA Channelx.
614 * @param __HANDLE__ : MDMA handle
615 * @param __COUNTER__: Number of data in bytes to be transferred.
616 * @retval None
617 */
618 #define __HAL_MDMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CBNDTR |= ((__COUNTER__) & MDMA_CBNDTR_BNDT))
619
620 /**
621 * @brief Returns the number of remaining data in bytes in the current MDMA Channelx transfer.
622 * @param __HANDLE__ : MDMA handle
623 * @retval The number of remaining data in bytes in the current MDMA Channelx transfer.
624 */
625 #define __HAL_MDMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CBNDTR & MDMA_CBNDTR_BNDT)
626
627 /**
628 * @}
629 */
630
631 /* Exported functions --------------------------------------------------------*/
632 /** @defgroup MDMA_Exported_Functions MDMA Exported Functions
633 * @{
634 */
635
636 /* Initialization and de-initialization functions *****************************/
637 /** @defgroup MDMA_Exported_Functions_Group1 Initialization and de-initialization functions
638 * @brief Initialization and de-initialization functions
639 * @{
640 */
641 HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma);
642 HAL_StatusTypeDef HAL_MDMA_DeInit (MDMA_HandleTypeDef *hmdma);
643 HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData);
644
645 HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void (* pCallback)(MDMA_HandleTypeDef *_hmdma));
646 HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID);
647
648 /**
649 * @}
650 */
651
652 /* Linked list operation functions ********************************************/
653 /** @defgroup MDMA_Exported_Functions_Group2 Linked List operation functions
654 * @brief Linked list operation functions
655 * @{
656 */
657
658 HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig);
659 HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode);
660 HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode);
661 HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma);
662 HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma);
663
664
665 /**
666 * @}
667 */
668
669 /* IO operation functions *****************************************************/
670 /** @defgroup MDMA_Exported_Functions_Group3 I/O operation functions
671 * @brief I/O operation functions
672 * @{
673 */
674 HAL_StatusTypeDef HAL_MDMA_Start (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
675 HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
676 HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma);
677 HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma);
678 HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, HAL_MDMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
679 HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma);
680 void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma);
681
682 /**
683 * @}
684 */
685
686 /* Peripheral State and Error functions ***************************************/
687 /** @defgroup MDMA_Exported_Functions_Group4 Peripheral State functions
688 * @brief Peripheral State functions
689 * @{
690 */
691 HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma);
692 uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma);
693
694 /**
695 * @}
696 */
697
698 /**
699 * @}
700 */
701
702 /* Private types -------------------------------------------------------------*/
703 /** @defgroup MDMA_Private_Types MDMA Private Types
704 * @{
705 */
706
707 /**
708 * @}
709 */
710
711 /* Private defines -----------------------------------------------------------*/
712 /** @defgroup MDMA_Private_Defines MDMA Private Defines
713 * @{
714 */
715
716 /**
717 * @}
718 */
719
720 /* Private variables ---------------------------------------------------------*/
721 /** @defgroup MDMA_Private_Variables MDMA Private Variables
722 * @{
723 */
724
725 /**
726 * @}
727 */
728
729 /* Private constants ---------------------------------------------------------*/
730 /** @defgroup MDMA_Private_Constants MDMA Private Constants
731 * @{
732 */
733
734 /**
735 * @}
736 */
737
738 /* Private macros ------------------------------------------------------------*/
739 /** @defgroup MDMA_Private_Macros MDMA Private Macros
740 * @{
741 */
742
743 #define IS_MDMA_LEVEL_COMPLETE(__LEVEL__) (((__LEVEL__) == HAL_MDMA_FULL_TRANSFER ) || \
744 ((__LEVEL__) == HAL_MDMA_BUFFER_TRANSFER )|| \
745 ((__LEVEL__) == HAL_MDMA_BLOCK_TRANSFER ) || \
746 ((__LEVEL__) == HAL_MDMA_REPEAT_BLOCK_TRANSFER ))
747
748
749 #define IS_MDMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == MDMA_PRIORITY_LOW ) || \
750 ((__PRIORITY__) == MDMA_PRIORITY_MEDIUM) || \
751 ((__PRIORITY__) == MDMA_PRIORITY_HIGH) || \
752 ((__PRIORITY__) == MDMA_PRIORITY_VERY_HIGH))
753
754 #define IS_MDMA_ENDIANNESS_MODE(__ENDIANNESS__) (((__ENDIANNESS__) == MDMA_LITTLE_ENDIANNESS_PRESERVE ) || \
755 ((__ENDIANNESS__) == MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE) || \
756 ((__ENDIANNESS__) == MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE) || \
757 ((__ENDIANNESS__) == MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE))
758
759
760 #if defined (OCTOSPI2)
761 #define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_OCTOSPI2_TC))
762 #else
763 #define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_SDMMC1_COMMAND_END))
764 #endif /* OCTOSPI2 */
765
766 #define IS_MDMA_SOURCE_INC(__INC__) (((__INC__) == MDMA_SRC_INC_DISABLE ) || \
767 ((__INC__) == MDMA_SRC_INC_BYTE ) || \
768 ((__INC__) == MDMA_SRC_INC_HALFWORD ) || \
769 ((__INC__) == MDMA_SRC_INC_WORD ) || \
770 ((__INC__) == MDMA_SRC_INC_DOUBLEWORD) || \
771 ((__INC__) == MDMA_SRC_DEC_BYTE) || \
772 ((__INC__) == MDMA_SRC_DEC_HALFWORD) || \
773 ((__INC__) == MDMA_SRC_DEC_WORD) || \
774 ((__INC__) == MDMA_SRC_DEC_DOUBLEWORD))
775
776 #define IS_MDMA_DESTINATION_INC(__INC__) (((__INC__) == MDMA_DEST_INC_DISABLE ) || \
777 ((__INC__) == MDMA_DEST_INC_BYTE ) || \
778 ((__INC__) == MDMA_DEST_INC_HALFWORD ) || \
779 ((__INC__) == MDMA_DEST_INC_WORD ) || \
780 ((__INC__) == MDMA_DEST_INC_DOUBLEWORD) || \
781 ((__INC__) == MDMA_DEST_DEC_BYTE) || \
782 ((__INC__) == MDMA_DEST_DEC_HALFWORD) || \
783 ((__INC__) == MDMA_DEST_DEC_WORD) || \
784 ((__INC__) == MDMA_DEST_DEC_DOUBLEWORD))
785
786 #define IS_MDMA_SOURCE_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_SRC_DATASIZE_BYTE ) || \
787 ((__SIZE__) == MDMA_SRC_DATASIZE_HALFWORD ) || \
788 ((__SIZE__) == MDMA_SRC_DATASIZE_WORD ) || \
789 ((__SIZE__) == MDMA_SRC_DATASIZE_DOUBLEWORD))
790
791 #define IS_MDMA_DESTINATION_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_DEST_DATASIZE_BYTE ) || \
792 ((__SIZE__) == MDMA_DEST_DATASIZE_HALFWORD ) || \
793 ((__SIZE__) == MDMA_DEST_DATASIZE_WORD ) || \
794 ((__SIZE__) == MDMA_DEST_DATASIZE_DOUBLEWORD))
795
796 #define IS_MDMA_DATA_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == MDMA_DATAALIGN_PACKENABLE ) || \
797 ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT ) || \
798 ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT_SIGNED ) || \
799 ((__ALIGNMENT__) == MDMA_DATAALIGN_LEFT))
800
801
802 #define IS_MDMA_SOURCE_BURST(__BURST__) (((__BURST__) == MDMA_SOURCE_BURST_SINGLE ) || \
803 ((__BURST__) == MDMA_SOURCE_BURST_2BEATS ) || \
804 ((__BURST__) == MDMA_SOURCE_BURST_4BEATS ) || \
805 ((__BURST__) == MDMA_SOURCE_BURST_8BEATS) || \
806 ((__BURST__) == MDMA_SOURCE_BURST_16BEATS) || \
807 ((__BURST__) == MDMA_SOURCE_BURST_32BEATS) || \
808 ((__BURST__) == MDMA_SOURCE_BURST_64BEATS) || \
809 ((__BURST__) == MDMA_SOURCE_BURST_128BEATS))
810
811
812 #define IS_MDMA_DESTINATION_BURST(__BURST__) (((__BURST__) == MDMA_DEST_BURST_SINGLE ) || \
813 ((__BURST__) == MDMA_DEST_BURST_2BEATS ) || \
814 ((__BURST__) == MDMA_DEST_BURST_4BEATS ) || \
815 ((__BURST__) == MDMA_DEST_BURST_8BEATS) || \
816 ((__BURST__) == MDMA_DEST_BURST_16BEATS) || \
817 ((__BURST__) == MDMA_DEST_BURST_32BEATS) || \
818 ((__BURST__) == MDMA_DEST_BURST_64BEATS) || \
819 ((__BURST__) == MDMA_DEST_BURST_128BEATS))
820
821 #define IS_MDMA_TRANSFER_TRIGGER_MODE(__MODE__) (((__MODE__) == MDMA_BUFFER_TRANSFER ) || \
822 ((__MODE__) == MDMA_BLOCK_TRANSFER ) || \
823 ((__MODE__) == MDMA_REPEAT_BLOCK_TRANSFER ) || \
824 ((__MODE__) == MDMA_FULL_TRANSFER))
825
826 #define IS_MDMA_BUFFER_TRANSFER_LENGTH(__LENGTH__) (((__LENGTH__) >= 0x00000001U) && ((__LENGTH__) < 0x000000FFU))
827
828 #define IS_MDMA_BLOCK_COUNT(__COUNT__) (((__COUNT__) > 0U ) && ((__COUNT__) <= 4096U))
829
830 #define IS_MDMA_TRANSFER_LENGTH(SIZE) (((SIZE) > 0U) && ((SIZE) <= 65536U))
831
832 #define IS_MDMA_BLOCK_ADDR_OFFSET(__BLOCK_ADD_OFFSET__) (((__BLOCK_ADD_OFFSET__) > (-65536)) && ((__BLOCK_ADD_OFFSET__) < 65536))
833
834 /**
835 * @}
836 */
837
838 /* Private functions prototypes ----------------------------------------------*/
839 /** @defgroup MDMA_Private_Functions_Prototypes MDMA Private Functions Prototypes
840 * @{
841 */
842
843 /**
844 * @}
845 */
846
847 /* Private functions ---------------------------------------------------------*/
848 /** @defgroup MDMA_Private_Functions MDMA Private Functions
849 * @{
850 */
851
852 /**
853 * @}
854 */
855
856 /**
857 * @}
858 */
859
860 /**
861 * @}
862 */
863
864 #ifdef __cplusplus
865 }
866 #endif
867
868 #endif /* STM32H7xx_HAL_MDMA_H */
869
870 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/