lib/main/STM32H7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nand.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32h7xx_hal_nand.h
   4   * @author  MCD Application Team
   5   * @brief   Header file of NAND HAL module.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  10   * All rights reserved.</center></h2>
  11   *
  12   * This software component is licensed by ST under BSD 3-Clause license,
  13   * the "License"; You may not use this file except in compliance with the
  14   * License. You may obtain a copy of the License at:
  15   *                       opensource.org/licenses/BSD-3-Clause
  16   *
  17   ******************************************************************************
  18   */
  19
  20 /* Define to prevent recursive inclusion -------------------------------------*/
  21 #ifndef STM32H7xx_HAL_NAND_H
  22 #define STM32H7xx_HAL_NAND_H
  23
  24 #ifdef __cplusplus
  25 extern "C" {
  26 #endif
  27
  28
  29 /* Includes ------------------------------------------------------------------*/
  30 #include "stm32h7xx_ll_fmc.h"
  31
  32 /** @addtogroup STM32H7xx_HAL_Driver
  33   * @{
  34   */
  35
  36 /** @addtogroup NAND
  37   * @{
  38   */
  39
  40 /* Exported typedef ----------------------------------------------------------*/
  41 /* Exported types ------------------------------------------------------------*/
  42 /** @defgroup NAND_Exported_Types NAND Exported Types
  43   * @{
  44   */
  45
  46 /**
  47   * @brief  HAL NAND State structures definition
  48   */
  49 typedef enum
  50 {
  51   HAL_NAND_STATE_RESET     = 0x00U,  /*!< NAND not yet initialized or disabled */
  52   HAL_NAND_STATE_READY     = 0x01U,  /*!< NAND initialized and ready for use   */
  53   HAL_NAND_STATE_BUSY      = 0x02U,  /*!< NAND internal process is ongoing     */
  54   HAL_NAND_STATE_ERROR     = 0x03U   /*!< NAND error state                     */
  55 } HAL_NAND_StateTypeDef;
  56
  57 /**
  58   * @brief  NAND Memory electronic signature Structure definition
  59   */
  60 typedef struct
  61 {
  62   /*<! NAND memory electronic signature maker and device IDs */
  63
  64   uint8_t Maker_Id;
  65
  66   uint8_t Device_Id;
  67
  68   uint8_t Third_Id;
  69
  70   uint8_t Fourth_Id;
  71 } NAND_IDTypeDef;
  72
  73 /**
  74   * @brief  NAND Memory address Structure definition
  75   */
  76 typedef struct
  77 {
  78   uint16_t Page;   /*!< NAND memory Page address  */
  79
  80   uint16_t Plane;   /*!< NAND memory Zone address  */
  81
  82   uint16_t Block;  /*!< NAND memory Block address */
  83
  84 } NAND_AddressTypeDef;
  85
  86 /**
  87   * @brief  NAND Memory info Structure definition
  88   */
  89 typedef struct
  90 {
  91   uint32_t        PageSize;              /*!< NAND memory page (without spare area) size measured in bytes
  92                                               for 8 bits adressing or words for 16 bits addressing             */
  93
  94   uint32_t        SpareAreaSize;         /*!< NAND memory spare area size measured in bytes
  95                                               for 8 bits adressing or words for 16 bits addressing             */
  96
  97   uint32_t        BlockSize;             /*!< NAND memory block size measured in number of pages               */
  98
  99   uint32_t        BlockNbr;              /*!< NAND memory number of total blocks                               */
 100
 101   uint32_t        PlaneNbr;              /*!< NAND memory number of planes                                     */
 102
 103   uint32_t        PlaneSize;             /*!< NAND memory zone size measured in number of blocks               */
 104
 105   FunctionalState ExtraCommandEnable;    /*!< NAND extra command needed for Page reading mode. This
 106                                               parameter is mandatory for some NAND parts after the read
 107                                               command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
 108                                               Example: Toshiba THTH58BYG3S0HBAI6.
 109                                               This parameter could be ENABLE or DISABLE
 110                                               Please check the Read Mode sequnece in the NAND device datasheet */
 111 } NAND_DeviceConfigTypeDef;
 112
 113 /**
 114   * @brief  NAND handle Structure definition
 115   */
 116 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
 117 typedef struct __NAND_HandleTypeDef
 118 #else
 119 typedef struct
 120 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS  */
 121 {
 122   FMC_NAND_TypeDef               *Instance;  /*!< Register base address                                 */
 123
 124   FMC_NAND_InitTypeDef           Init;       /*!< NAND device control configuration parameters          */
 125
 126   HAL_LockTypeDef                Lock;       /*!< NAND locking object                                   */
 127
 128   __IO HAL_NAND_StateTypeDef     State;      /*!< NAND device access state                              */
 129
 130   NAND_DeviceConfigTypeDef       Config;     /*!< NAND phusical characteristic information structure    */
 131
 132 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
 133   void  (* MspInitCallback)        ( struct __NAND_HandleTypeDef * hnand);    /*!< NAND Msp Init callback              */
 134   void  (* MspDeInitCallback)      ( struct __NAND_HandleTypeDef * hnand);    /*!< NAND Msp DeInit callback            */
 135   void  (* ItCallback)             ( struct __NAND_HandleTypeDef * hnand);    /*!< NAND IT callback                    */
 136 #endif
 137 } NAND_HandleTypeDef;
 138
 139 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
 140 /**
 141   * @brief  HAL NAND Callback ID enumeration definition
 142   */
 143 typedef enum
 144 {
 145   HAL_NAND_MSP_INIT_CB_ID       = 0x00U,  /*!< NAND MspInit Callback ID          */
 146   HAL_NAND_MSP_DEINIT_CB_ID     = 0x01U,  /*!< NAND MspDeInit Callback ID        */
 147   HAL_NAND_IT_CB_ID             = 0x02U   /*!< NAND IT Callback ID               */
 148 }HAL_NAND_CallbackIDTypeDef;
 149
 150 /**
 151   * @brief  HAL NAND Callback pointer definition
 152   */
 153 typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand);
 154 #endif
 155
 156 /**
 157   * @}
 158   */
 159
 160 /* Exported constants --------------------------------------------------------*/
 161 /* Exported macro ------------------------------------------------------------*/
 162 /** @defgroup NAND_Exported_Macros NAND Exported Macros
 163  * @{
 164  */
 165
 166 /** @brief Reset NAND handle state
 167   * @param  __HANDLE__ specifies the NAND handle.
 168   * @retval None
 169   */
 170 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
 171 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__)         do {                                             \
 172                                                                (__HANDLE__)->State = HAL_NAND_STATE_RESET; \
 173                                                                (__HANDLE__)->MspInitCallback = NULL;       \
 174                                                                (__HANDLE__)->MspDeInitCallback = NULL;     \
 175                                                              } while(0)
 176 #else
 177 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
 178 #endif
 179
 180 /**
 181   * @}
 182   */
 183
 184 /* Exported functions --------------------------------------------------------*/
 185 /** @addtogroup NAND_Exported_Functions NAND Exported Functions
 186   * @{
 187   */
 188
 189 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
 190   * @{
 191   */
 192
 193 /* Initialization/de-initialization functions  ********************************/
 194 HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
 195 HAL_StatusTypeDef  HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
 196
 197 HAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
 198
 199 HAL_StatusTypeDef  HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
 200
 201 void               HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
 202 void               HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
 203 void               HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
 204 void               HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
 205
 206 /**
 207   * @}
 208   */
 209
 210 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
 211   * @{
 212   */
 213
 214 /* IO operation functions  ****************************************************/
 215 HAL_StatusTypeDef  HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
 216
 217 HAL_StatusTypeDef  HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
 218 HAL_StatusTypeDef  HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
 219 HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
 220 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
 221
 222 HAL_StatusTypeDef  HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
 223 HAL_StatusTypeDef  HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
 224 HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
 225 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
 226
 227 HAL_StatusTypeDef  HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
 228
 229 uint32_t           HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
 230
 231 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
 232 /* NAND callback registering/unregistering */
 233 HAL_StatusTypeDef  HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback);
 234 HAL_StatusTypeDef  HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);
 235 #endif
 236
 237 /**
 238   * @}
 239   */
 240
 241 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
 242   * @{
 243   */
 244
 245 /* NAND Control functions  ****************************************************/
 246 HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
 247 HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
 248 HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
 249
 250 /**
 251   * @}
 252   */
 253
 254 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
 255   * @{
 256   */
 257 /* NAND State functions *******************************************************/
 258 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
 259 uint32_t              HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
 260 /**
 261   * @}
 262   */
 263
 264 /**
 265   * @}
 266   */
 267
 268 /* Private types -------------------------------------------------------------*/
 269 /* Private variables ---------------------------------------------------------*/
 270 /* Private constants ---------------------------------------------------------*/
 271 /** @defgroup NAND_Private_Constants NAND Private Constants
 272   * @{
 273   */
 274 #define NAND_DEVICE                0x80000000UL
 275 #define NAND_WRITE_TIMEOUT         0x01000000UL
 276
 277 #define CMD_AREA                   (1UL<<16U)  /* A16 = CLE high */
 278 #define ADDR_AREA                  (1UL<<17U)  /* A17 = ALE high */
 279
 280 #define NAND_CMD_AREA_A            0x00U
 281 #define NAND_CMD_AREA_B            0x01U
 282 #define NAND_CMD_AREA_C            0x50U
 283 #define NAND_CMD_AREA_TRUE1        0x30U
 284
 285 #define NAND_CMD_WRITE0            0x80U
 286 #define NAND_CMD_WRITE_TRUE1       0x10U
 287 #define NAND_CMD_ERASE0            0x60U
 288 #define NAND_CMD_ERASE1            0xD0U
 289 #define NAND_CMD_READID            0x90U
 290 #define NAND_CMD_STATUS            0x70U
 291 #define NAND_CMD_LOCK_STATUS       0x7AU
 292 #define NAND_CMD_RESET             0xFFU
 293
 294 /* NAND memory status */
 295 #define NAND_VALID_ADDRESS         0x00000100UL
 296 #define NAND_INVALID_ADDRESS       0x00000200UL
 297 #define NAND_TIMEOUT_ERROR         0x00000400UL
 298 #define NAND_BUSY                  0x00000000UL
 299 #define NAND_ERROR                 0x00000001UL
 300 #define NAND_READY                 0x00000040UL
 301 /**
 302   * @}
 303   */
 304
 305 /* Private macros ------------------------------------------------------------*/
 306 /** @defgroup NAND_Private_Macros NAND Private Macros
 307   * @{
 308   */
 309
 310 /**
 311   * @brief  NAND memory address computation.
 312   * @param  __ADDRESS__ NAND memory address.
 313   * @param  __HANDLE__  NAND handle.
 314   * @retval NAND Raw address value
 315   */
 316 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
 317                          (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
 318
 319 /**
 320   * @brief  NAND memory Column address computation.
 321   * @param  __HANDLE__ NAND handle.
 322   * @retval NAND Raw address value
 323   */
 324 #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
 325
 326 /**
 327   * @brief  NAND memory address cycling.
 328   * @param  __ADDRESS__ NAND memory address.
 329   * @retval NAND address cycling value.
 330   */
 331 #define ADDR_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st addressing cycle */
 332 #define ADDR_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd addressing cycle */
 333 #define ADDR_3RD_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 16)      /* 3rd addressing cycle */
 334 #define ADDR_4TH_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 24)      /* 4th addressing cycle */
 335
 336 /**
 337   * @brief  NAND memory Columns cycling.
 338   * @param  __ADDRESS__ NAND memory address.
 339   * @retval NAND Column address cycling value.
 340   */
 341 #define COLUMN_1ST_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) & 0xFFU)    /* 1st Column addressing cycle */
 342 #define COLUMN_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd Column addressing cycle */
 343
 344 /**
 345   * @}
 346   */
 347
 348 /**
 349   * @}
 350   */
 351
 352 /**
 353   * @}
 354   */
 355
 356 /**
 357   * @}
 358   */
 359
 360
 361 #ifdef __cplusplus
 362 }
 363 #endif
 364
 365 #endif /* STM32H7xx_HAL_NAND_H */
 366
 367 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/