lib/main/STM32H7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32h7xx_hal_pwr.h
   4   * @author  MCD Application Team
   5   * @brief   Header file of PWR HAL module.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
  10   * All rights reserved.</center></h2>
  11   *
  12   * This software component is licensed by ST under BSD 3-Clause license,
  13   * the "License"; You may not use this file except in compliance with the
  14   * License. You may obtain a copy of the License at:
  15   *                        opensource.org/licenses/BSD-3-Clause
  16   *
  17   ******************************************************************************
  18   */
  19
  20 /* Define to prevent recursive inclusion -------------------------------------*/
  21 #ifndef STM32H7xx_HAL_PWR_H
  22 #define STM32H7xx_HAL_PWR_H
  23
  24 #ifdef __cplusplus
  25  extern "C" {
  26 #endif /* __cplusplus */
  27
  28 /* Includes ------------------------------------------------------------------*/
  29 #include "stm32h7xx_hal_def.h"
  30
  31 /** @addtogroup STM32H7xx_HAL_Driver
  32   * @{
  33   */
  34
  35 /** @addtogroup PWR
  36   * @{
  37   */
  38
  39 /* Exported types ------------------------------------------------------------*/
  40
  41 /** @defgroup PWR_Exported_Types PWR Exported Types
  42   * @{
  43   */
  44
  45 /**
  46   * @brief  PWR PVD configuration structure definition
  47   */
  48 typedef struct
  49 {
  50   uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. This
  51                                     parameter can be a value of @ref
  52                                     PWR_PVD_detection_level.
  53                      */
  54
  55   uint32_t Mode;     /*!< Mode: Specifies the EXTI operating mode for the PVD
  56                                 event. This parameter can be a value of @ref
  57                                 PWR_PVD_Mode.
  58                      */
  59 }PWR_PVDTypeDef;
  60
  61 /**
  62   * @}
  63   */
  64
  65 /* Exported constants --------------------------------------------------------*/
  66 /** @defgroup PWR_Exported_Constants PWR Exported Constants
  67   * @{
  68   */
  69
  70 /** @defgroup PWR_PVD_detection_level PWR PVD detection level
  71   * @{
  72   */
  73 #define PWR_PVDLEVEL_0  PWR_CR1_PLS_LEV0  /*!< Programmable voltage detector
  74                                                level 0 selection : 1V95       */
  75 #define PWR_PVDLEVEL_1  PWR_CR1_PLS_LEV1  /*!< Programmable voltage detector
  76                                                level 1 selection : 2V1        */
  77 #define PWR_PVDLEVEL_2  PWR_CR1_PLS_LEV2  /*!< Programmable voltage detector
  78                                                level 2 selection : 2V25       */
  79 #define PWR_PVDLEVEL_3  PWR_CR1_PLS_LEV3  /*!< Programmable voltage detector
  80                                                level 3 selection : 2V4        */
  81 #define PWR_PVDLEVEL_4  PWR_CR1_PLS_LEV4  /*!< Programmable voltage detector
  82                                                level 4 selection : 2V55       */
  83 #define PWR_PVDLEVEL_5  PWR_CR1_PLS_LEV5  /*!< Programmable voltage detector
  84                                                level 5 selection : 2V7        */
  85 #define PWR_PVDLEVEL_6  PWR_CR1_PLS_LEV6  /*!< Programmable voltage detector
  86                                                level 6 selection : 2V85       */
  87 #define PWR_PVDLEVEL_7  PWR_CR1_PLS_LEV7  /*!< External input analog voltage
  88                                                (Compare internally to VREF)   */
  89 /**
  90   * @}
  91   */
  92
  93 /** @defgroup PWR_PVD_Mode PWR PVD Mode
  94   * @{
  95   */
  96 #define PWR_PVD_MODE_NORMAL               (0x00000000U) /*!< Basic mode is used                                        */
  97 #define PWR_PVD_MODE_IT_RISING            (0x00010001U) /*!< Interrupt Mode with Rising edge trigger detection         */
  98 #define PWR_PVD_MODE_IT_FALLING           (0x00010002U) /*!< Interrupt Mode with Falling edge trigger detection        */
  99 #define PWR_PVD_MODE_IT_RISING_FALLING    (0x00010003U) /*!< Interrupt Mode with Rising/Falling edge trigger detection */
 100 #define PWR_PVD_MODE_EVENT_RISING         (0x00020001U) /*!< Event Mode with Rising edge trigger detection             */
 101 #define PWR_PVD_MODE_EVENT_FALLING        (0x00020002U) /*!< Event Mode with Falling edge trigger detection            */
 102 #define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection     */
 103 /**
 104   * @}
 105   */
 106
 107 /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
 108   * @{
 109   */
 110 #define PWR_MAINREGULATOR_ON      (0U)
 111 #define PWR_LOWPOWERREGULATOR_ON  PWR_CR1_LPDS
 112 /**
 113   * @}
 114   */
 115
 116 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
 117   * @{
 118   */
 119 #define PWR_SLEEPENTRY_WFI  (0x01U)
 120 #define PWR_SLEEPENTRY_WFE  (0x02U)
 121 /**
 122   * @}
 123   */
 124
 125 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
 126   * @{
 127   */
 128 #define PWR_STOPENTRY_WFI  (0x01U)
 129 #define PWR_STOPENTRY_WFE  (0x02U)
 130 /**
 131   * @}
 132   */
 133
 134 /** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
 135   * @{
 136   */
 137 #if defined(PWR_SRDCR_VOS)
 138 #define PWR_REGULATOR_VOLTAGE_SCALE0  (PWR_SRDCR_VOS_1 | PWR_SRDCR_VOS_0)
 139 #define PWR_REGULATOR_VOLTAGE_SCALE1  (PWR_SRDCR_VOS_1)
 140 #define PWR_REGULATOR_VOLTAGE_SCALE2  (PWR_SRDCR_VOS_0)
 141 #define PWR_REGULATOR_VOLTAGE_SCALE3  (0U)
 142 #else
 143 #define PWR_REGULATOR_VOLTAGE_SCALE0  (0U)
 144 #define PWR_REGULATOR_VOLTAGE_SCALE1  (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0)
 145 #define PWR_REGULATOR_VOLTAGE_SCALE2  (PWR_D3CR_VOS_1)
 146 #define PWR_REGULATOR_VOLTAGE_SCALE3  (PWR_D3CR_VOS_0)
 147 #endif /* PWR_SRDCR_VOS */
 148 /**
 149   * @}
 150   */
 151
 152 /** @defgroup PWR_Flag PWR Flag
 153   * @{
 154   */
 155 /* PWR CPU flag */
 156 #define PWR_FLAG_STOP       (0x01U)
 157 #if defined (PWR_CPUCR_SBF_D2)
 158 #define PWR_FLAG_SB_D1      (0x02U)
 159 #define PWR_FLAG_SB_D2      (0x03U)
 160 #endif /* defined (PWR_CPUCR_SBF_D2) */
 161 #define PWR_FLAG_SB         (0x04U)
 162 #if defined (DUAL_CORE)
 163 #define PWR_FLAG_CPU_HOLD   (0x05U)
 164 #define PWR_FLAG_CPU2_HOLD  (0x06U)
 165 #define PWR_FLAG2_STOP      (0x07U)
 166 #define PWR_FLAG2_SB_D1     (0x08U)
 167 #define PWR_FLAG2_SB_D2     (0x09U)
 168 #define PWR_FLAG2_SB        (0x0AU)
 169 #endif /* defined (DUAL_CORE) */
 170 #define PWR_FLAG_PVDO       (0x0BU)
 171 #define PWR_FLAG_AVDO       (0x0CU)
 172 #define PWR_FLAG_ACTVOSRDY  (0x0DU)
 173 #define PWR_FLAG_ACTVOS     (0x0EU)
 174 #define PWR_FLAG_BRR        (0x0FU)
 175 #define PWR_FLAG_VOSRDY     (0x10U)
 176 #if defined (SMPS)
 177 #define PWR_FLAG_SMPSEXTRDY (0x11U)
 178 #else
 179 #define PWR_FLAG_SCUEN      (0x11U)
 180 #endif /* defined (SMPS) */
 181 #if defined (PWR_CSR1_MMCVDO)
 182 #define PWR_FLAG_MMCVDO     (0x12U)
 183 #endif /* defined (PWR_CSR1_MMCVDO) */
 184 #define PWR_FLAG_USB33RDY   (0x13U)
 185 #define PWR_FLAG_TEMPH      (0x14U)
 186 #define PWR_FLAG_TEMPL      (0x15U)
 187 #define PWR_FLAG_VBATH      (0x16U)
 188 #define PWR_FLAG_VBATL      (0x17U)
 189
 190 /* PWR Wake up flag */
 191 #define PWR_FLAG_WKUP1 PWR_WKUPCR_WKUPC1
 192 #define PWR_FLAG_WKUP2 PWR_WKUPCR_WKUPC2
 193 #define PWR_FLAG_WKUP3 PWR_WKUPCR_WKUPC3
 194 #define PWR_FLAG_WKUP4 PWR_WKUPCR_WKUPC4
 195 #define PWR_FLAG_WKUP5 PWR_WKUPCR_WKUPC5
 196 #define PWR_FLAG_WKUP6 PWR_WKUPCR_WKUPC6
 197 /**
 198   * @}
 199   */
 200
 201 /** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask
 202   * @{
 203   */
 204 #define  PWR_EWUP_MASK  (0x0FFF3F3FU)
 205 /**
 206   * @}
 207   */
 208
 209 /**
 210   * @}
 211   */
 212 /* Exported macro ------------------------------------------------------------*/
 213 /** @defgroup PWR_Exported_Macro PWR Exported Macro
 214   * @{
 215   */
 216
 217 /** @brief  Configure the main internal regulator output voltage.
 218   * @param  __REGULATOR__ : Specifies the regulator output voltage to achieve a
 219   *                         trade-off between performance and power consumption
 220   *                         when the device does not operate at the maximum
 221   *                         frequency (refer to the datasheet for more details).
 222   *          This parameter can be one of the following values:
 223   *            @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output
 224   *                                                Scale 0 mode.
 225   *            @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output
 226   *                                                Scale 1 mode.
 227   *            @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output
 228   *                                                Scale 2 mode.
 229   *            @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output
 230   *                                                Scale 3 mode.
 231   * @note   For STM32H74x and STM32H75x lines, configuring Voltage Scale 0 is
 232   *         only possible when Vcore is supplied from LDO (Low DropOut). The
 233   *         SYSCFG Clock must be enabled through __HAL_RCC_SYSCFG_CLK_ENABLE()
 234   *         macro before configuring Voltage Scale 0 using
 235   *         __HAL_PWR_VOLTAGESCALING_CONFIG().
 236   *         Transition to Voltage Scale 0 is only possible when the system is
 237   *         already in Voltage Scale 1.
 238   *         Transition from Voltage Scale 0 is only possible to Voltage Scale 1
 239   *         then once in Voltage Scale 1 it is possible to switch to another
 240   *         voltage scale.
 241   *         After each regulator voltage setting, wait on VOSRDY flag to be set
 242   *         using macro __HAL_PWR_GET_FLAG().
 243   *         To enter low power mode , and if current regulator voltage is
 244   *         Voltage Scale 0 then first switch to Voltage Scale 1 before entering
 245   *         low power mode.
 246   * @retval None.
 247   */
 248 #if defined (PWR_SRDCR_VOS) /* STM32H7Axxx and STM32H7Bxxx lines */
 249 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)                         \
 250 do {                                                                           \
 251       __IO uint32_t tmpreg = 0x00;                                             \
 252       /* Configure the Voltage Scaling */                                      \
 253       MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, (__REGULATOR__));                  \
 254       /* Delay after setting the voltage scaling */                            \
 255       tmpreg = READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS);                            \
 256       UNUSED(tmpreg);                                                          \
 257 } while(0)
 258 #else /* 3 power domains devices */
 259 #if defined(SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */
 260 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)                         \
 261 do {                                                                           \
 262       __IO uint32_t tmpreg = 0x00;                                             \
 263       /* Check the voltage scaling to be configured */                         \
 264       if((__REGULATOR__) == PWR_REGULATOR_VOLTAGE_SCALE0)                      \
 265       {                                                                        \
 266         /* Configure the Voltage Scaling 1 */                                  \
 267         MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);     \
 268         /* Delay after setting the voltage scaling */                          \
 269         tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS);                            \
 270         /* Enable the PWR overdrive */                                         \
 271         SET_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                             \
 272         /* Delay after setting the syscfg boost setting */                     \
 273         tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                   \
 274       }                                                                        \
 275       else                                                                     \
 276       {                                                                        \
 277         /* Disable the PWR overdrive */                                        \
 278         CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                           \
 279         /* Delay after setting the syscfg boost setting */                     \
 280         tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                   \
 281         /* Configure the Voltage Scaling x */                                  \
 282         MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__));                  \
 283         /* Delay after setting the voltage scaling */                          \
 284         tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS);                            \
 285       }                                                                        \
 286       UNUSED(tmpreg);                                                          \
 287 } while(0)
 288 #else /* STM32H72xxx and STM32H73xxx lines */
 289 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)                         \
 290 do {                                                                           \
 291       __IO uint32_t tmpreg = 0x00;                                             \
 292       /* Configure the Voltage Scaling */                                      \
 293       MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__));                   \
 294       /* Delay after setting the voltage scaling */                            \
 295       tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS);                              \
 296       UNUSED(tmpreg);                                                          \
 297 } while(0)
 298 #endif /* defined(SYSCFG_PWRCR_ODEN) */
 299 #endif /* defined (PWR_SRDCR_VOS) */
 300
 301 /** @brief  Check PWR flags are set or not.
 302   * @param  __FLAG__ : Specifies the flag to check.
 303   *           This parameter can be one of the following values:
 304   *            @arg PWR_FLAG_PVDO : PVD Output. This flag is valid only if PVD
 305   *                                 is enabled by the HAL_PWR_EnablePVD()
 306   *                                 function.
 307   *                                 The PVD is stopped by STANDBY mode. For this
 308   *                                 reason, this bit is equal to 0 after STANDBY
 309   *                                 or reset until the PVDE bit is set.
 310   *            @arg PWR_FLAG_AVDO : AVD Output. This flag is valid only if AVD
 311   *                                 is enabled by the HAL_PWREx_EnableAVD()
 312   *                                 function. The AVD is stopped by STANDBY mode.
 313   *                                 For this reason, this bit is equal to 0
 314   *                                 after STANDBY or reset until the AVDE bit
 315   *                                 is set.
 316   *            @arg PWR_FLAG_ACTVOSRDY : This flag indicates that the Regulator
 317   *                                      voltage scaling output selection is
 318   *                                      ready.
 319   *            @arg PWR_FLAG_BRR : Backup regulator ready flag. This bit is not
 320   *                                reset when the device wakes up from STANDBY
 321   *                                mode or by a system reset or power-on reset.
 322   *            @arg PWR_FLAG_VOSRDY : This flag indicates that the Regulator
 323   *                                   voltage scaling output selection is ready.
 324   *                                mode or by a system reset or power-on reset.
 325   *            @arg PWR_FLAG_USB33RDY : This flag indicates that the USB supply
 326   *                                     from regulator is ready.
 327   *            @arg PWR_FLAG_TEMPH : This flag indicates that the temperature
 328   *                                  equal or above high threshold level.
 329   *            @arg PWR_FLAG_TEMPL : This flag indicates that the temperature
 330   *                                  equal or below low threshold level.
 331   *            @arg PWR_FLAG_VBATH : This flag indicates that VBAT level equal
 332   *                                  or above high threshold level.
 333   *            @arg PWR_FLAG_VBATL : This flag indicates that VBAT level equal
 334   *                                  or below low threshold level.
 335   *            @arg PWR_FLAG_STOP : This flag indicates that the system entered
 336   *                                 in STOP mode.
 337   *            @arg PWR_FLAG_SB : This flag indicates that the system entered in
 338   *                               STANDBY mode.
 339   *            @arg PWR_FLAG_SB_D1 : This flag indicates that the D1 domain
 340   *                                  entered in STANDBY mode.
 341   *            @arg PWR_FLAG_SB_D2 : This flag indicates that the D2 domain
 342   *                                  entered in STANDBY mode.
 343   *            @arg PWR_FLAG2_STOP : This flag indicates that the system entered
 344   *                                 in STOP mode.
 345   *            @arg PWR_FLAG2_SB : This flag indicates that the system entered
 346   *                                in STANDBY mode.
 347   *            @arg PWR_FLAG2_SB_D1 : This flag indicates that the D1 domain
 348   *                                   entered in STANDBY mode.
 349   *            @arg PWR_FLAG2_SB_D2 : This flag indicates that the D2 domain
 350   *                                   entered in STANDBY mode.
 351   *            @arg PWR_FLAG_CPU_HOLD : This flag indicates that the CPU1 wakes
 352   *                                     up with hold.
 353   *            @arg PWR_FLAG_CPU2_HOLD : This flag indicates that the CPU2 wakes
 354   *                                      up with hold.
 355   *            @arg PWR_FLAG_SMPSEXTRDY : This flag indicates that the SMPS
 356   *                                       External supply is sready.
 357   *            @arg PWR_FLAG_SCUEN : This flag indicates that the supply
 358   *                                  configuration update is enabled.
 359   *            @arg PWR_FLAG_MMCVDO : This flag indicates that the VDDMMC is
 360   *                                   above or equal to 1.2 V.
 361   * @note   The PWR_FLAG_PVDO, PWR_FLAG_AVDO, PWR_FLAG_ACTVOSRDY, PWR_FLAG_BRR,
 362   *         PWR_FLAG_VOSRDY, PWR_FLAG_USB33RDY, PWR_FLAG_TEMPH, PWR_FLAG_TEMPL,
 363   *         PWR_FLAG_VBATH, PWR_FLAG_VBATL, PWR_FLAG_STOP and PWR_FLAG_SB flags
 364   *         are used for all H7 family lines.
 365   *         The PWR_FLAG2_STOP, PWR_FLAG2_SB, PWR_FLAG2_SB_D1, PWR_FLAG2_SB_D2,
 366   *         PWR_FLAG_CPU_HOLD and PWR_FLAG_CPU2_HOLD flags are used only for H7
 367   *         dual core lines.
 368   *         The PWR_FLAG_SB_D1 and PWR_FLAG_SB_D2 flags are used for all H7
 369   *         family except STM32H7Axxx and STM32H7Bxxx lines.
 370   *         The PWR_FLAG_MMCVDO flag is used only for STM32H7Axxx and
 371   *         STM32H7Bxxx lines.
 372   *         The PWR_FLAG_SCUEN flag is used for devices that support only LDO
 373   *         regulator.
 374   *         The PWR_FLAG_SMPSEXTRDY flag is used for devices that support LDO
 375   *         and SMPS regulators.
 376   * @retval The (__FLAG__) state (TRUE or FALSE).
 377   */
 378 #if defined (DUAL_CORE) /* Dual core lines */
 379 #define __HAL_PWR_GET_FLAG(__FLAG__)                                                              \
 380 (((__FLAG__) == PWR_FLAG_PVDO)       ? ((PWR->CSR1 & PWR_CSR1_PVDO)       == PWR_CSR1_PVDO)      :\
 381  ((__FLAG__) == PWR_FLAG_AVDO)       ? ((PWR->CSR1 & PWR_CSR1_AVDO)       == PWR_CSR1_AVDO)      :\
 382  ((__FLAG__) == PWR_FLAG_ACTVOSRDY)  ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY)  == PWR_CSR1_ACTVOSRDY) :\
 383  ((__FLAG__) == PWR_FLAG_VOSRDY)     ? ((PWR->D3CR & PWR_D3CR_VOSRDY)     == PWR_D3CR_VOSRDY)    :\
 384  ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY)   == PWR_CR3_SMPSEXTRDY) :\
 385  ((__FLAG__) == PWR_FLAG_BRR)        ? ((PWR->CR2 & PWR_CR2_BRRDY)        == PWR_CR2_BRRDY)      :\
 386  ((__FLAG__) == PWR_FLAG_CPU_HOLD)   ? ((PWR->CPU2CR & PWR_CPU2CR_HOLD1F) == PWR_CPU2CR_HOLD1F)  :\
 387  ((__FLAG__) == PWR_FLAG_CPU2_HOLD)  ? ((PWR->CPUCR & PWR_CPUCR_HOLD2F)   == PWR_CPUCR_HOLD2F)   :\
 388  ((__FLAG__) == PWR_FLAG_SB)         ? ((PWR->CPUCR & PWR_CPUCR_SBF)      == PWR_CPUCR_SBF)      :\
 389  ((__FLAG__) == PWR_FLAG2_SB)        ? ((PWR->CPU2CR & PWR_CPU2CR_SBF)    == PWR_CPU2CR_SBF)     :\
 390  ((__FLAG__) == PWR_FLAG_STOP)       ? ((PWR->CPUCR & PWR_CPUCR_STOPF)    == PWR_CPUCR_STOPF)    :\
 391  ((__FLAG__) == PWR_FLAG2_STOP)      ? ((PWR->CPU2CR & PWR_CPU2CR_STOPF)  == PWR_CPU2CR_STOPF)   :\
 392  ((__FLAG__) == PWR_FLAG_SB_D1)      ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1)   == PWR_CPUCR_SBF_D1)   :\
 393  ((__FLAG__) == PWR_FLAG2_SB_D1)     ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D1) == PWR_CPU2CR_SBF_D1)  :\
 394  ((__FLAG__) == PWR_FLAG_SB_D2)      ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2)   == PWR_CPUCR_SBF_D2)   :\
 395  ((__FLAG__) == PWR_FLAG2_SB_D2)     ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D2) == PWR_CPU2CR_SBF_D2)  :\
 396  ((__FLAG__) == PWR_FLAG_USB33RDY)   ? ((PWR->CR3 & PWR_CR3_USB33RDY)     == PWR_CR3_USB33RDY)   :\
 397  ((__FLAG__) == PWR_FLAG_TEMPH)      ? ((PWR->CR2 & PWR_CR2_TEMPH)        == PWR_CR2_TEMPH)      :\
 398  ((__FLAG__) == PWR_FLAG_TEMPL)      ? ((PWR->CR2 & PWR_CR2_TEMPL)        == PWR_CR2_TEMPL)      :\
 399  ((__FLAG__) == PWR_FLAG_VBATH)      ? ((PWR->CR2 & PWR_CR2_VBATH)        == PWR_CR2_VBATH)      :\
 400  ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
 401 #else /* Single core lines */
 402 #if defined (PWR_CPUCR_SBF_D2) /* STM32H72x, STM32H73x, STM32H74x and STM32H75x lines */
 403 #if defined (SMPS) /* STM32H725 and STM32H735 lines */
 404 #define __HAL_PWR_GET_FLAG(__FLAG__)                                                              \
 405 (((__FLAG__) == PWR_FLAG_PVDO)       ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)       :\
 406  ((__FLAG__) == PWR_FLAG_AVDO)       ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)       :\
 407  ((__FLAG__) == PWR_FLAG_ACTVOSRDY)  ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY)  :\
 408  ((__FLAG__) == PWR_FLAG_VOSRDY)     ? ((PWR->D3CR & PWR_D3CR_VOSRDY)    == PWR_D3CR_VOSRDY)     :\
 409  ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_FLAG_SMPSEXTRDY) == PWR_FLAG_SMPSEXTRDY) :\
 410  ((__FLAG__) == PWR_FLAG_BRR)        ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)       :\
 411  ((__FLAG__) == PWR_FLAG_SB)         ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)       :\
 412  ((__FLAG__) == PWR_FLAG_STOP)       ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)     :\
 413  ((__FLAG__) == PWR_FLAG_SB_D1)      ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1)  == PWR_CPUCR_SBF_D1)    :\
 414  ((__FLAG__) == PWR_FLAG_SB_D2)      ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2)  == PWR_CPUCR_SBF_D2)    :\
 415  ((__FLAG__) == PWR_FLAG_USB33RDY)   ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)    :\
 416  ((__FLAG__) == PWR_FLAG_TEMPH)      ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)       :\
 417  ((__FLAG__) == PWR_FLAG_TEMPL)      ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)       :\
 418  ((__FLAG__) == PWR_FLAG_VBATH)      ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)       :\
 419  ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
 420 #else /* STM32H723, STM32H733, STM32H742, STM32H743, STM32H750 and STM32H753 lines */
 421 #define __HAL_PWR_GET_FLAG(__FLAG__)                                                            \
 422 (((__FLAG__) == PWR_FLAG_PVDO)      ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\
 423  ((__FLAG__) == PWR_FLAG_AVDO)      ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\
 424  ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
 425  ((__FLAG__) == PWR_FLAG_VOSRDY)    ? ((PWR->D3CR & PWR_D3CR_VOSRDY)    == PWR_D3CR_VOSRDY)    :\
 426  ((__FLAG__) == PWR_FLAG_SCUEN)     ? ((PWR->CR3 & PWR_CR3_SCUEN)       == PWR_CR3_SCUEN)      :\
 427  ((__FLAG__) == PWR_FLAG_BRR)       ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\
 428  ((__FLAG__) == PWR_FLAG_SB)        ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\
 429  ((__FLAG__) == PWR_FLAG_STOP)      ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\
 430  ((__FLAG__) == PWR_FLAG_SB_D1)     ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1)  == PWR_CPUCR_SBF_D1)   :\
 431  ((__FLAG__) == PWR_FLAG_SB_D2)     ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2)  == PWR_CPUCR_SBF_D2)   :\
 432  ((__FLAG__) == PWR_FLAG_USB33RDY)  ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\
 433  ((__FLAG__) == PWR_FLAG_TEMPH)     ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\
 434  ((__FLAG__) == PWR_FLAG_TEMPL)     ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\
 435  ((__FLAG__) == PWR_FLAG_VBATH)     ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\
 436  ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
 437 #endif /* defined (SMPS) */
 438 #else /* STM32H7Axxx and STM32H7Bxxx lines */
 439 #if defined (SMPS) /* STM32H7AxxQ and STM32H7BxxQ lines */
 440 #define __HAL_PWR_GET_FLAG(__FLAG__)                                                             \
 441 (((__FLAG__) == PWR_FLAG_PVDO)       ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\
 442  ((__FLAG__) == PWR_FLAG_AVDO)       ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\
 443  ((__FLAG__) == PWR_FLAG_ACTVOSRDY)  ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
 444  ((__FLAG__) == PWR_FLAG_BRR)        ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\
 445  ((__FLAG__) == PWR_FLAG_VOSRDY)     ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY)  == PWR_SRDCR_VOSRDY)   :\
 446  ((__FLAG__) == PWR_FLAG_STOP)       ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\
 447  ((__FLAG__) == PWR_FLAG_SB)         ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\
 448  ((__FLAG__) == PWR_FLAG_MMCVDO)     ? ((PWR->CSR1 & PWR_CSR1_MMCVDO)    == PWR_CSR1_MMCVDO)    :\
 449  ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY)  == PWR_CR3_SMPSEXTRDY) :\
 450  ((__FLAG__) == PWR_FLAG_USB33RDY)   ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\
 451  ((__FLAG__) == PWR_FLAG_TEMPH)      ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\
 452  ((__FLAG__) == PWR_FLAG_TEMPL)      ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\
 453  ((__FLAG__) == PWR_FLAG_VBATH)      ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\
 454  ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
 455 #else /* STM32H7Axx and STM32H7Bxx lines */
 456 #define __HAL_PWR_GET_FLAG(__FLAG__)                                                            \
 457 (((__FLAG__) == PWR_FLAG_PVDO)      ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\
 458  ((__FLAG__) == PWR_FLAG_AVDO)      ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\
 459  ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
 460  ((__FLAG__) == PWR_FLAG_BRR)       ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\
 461  ((__FLAG__) == PWR_FLAG_VOSRDY)    ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY)  == PWR_SRDCR_VOSRDY)   :\
 462  ((__FLAG__) == PWR_FLAG_SCUEN)     ? ((PWR->CR3 & PWR_CR3_SCUEN)       == PWR_CR3_SCUEN)      :\
 463  ((__FLAG__) == PWR_FLAG_STOP)      ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\
 464  ((__FLAG__) == PWR_FLAG_SB)        ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\
 465  ((__FLAG__) == PWR_FLAG_MMCVDO)    ? ((PWR->CSR1 & PWR_CSR1_MMCVDO)    == PWR_CSR1_MMCVDO)    :\
 466  ((__FLAG__) == PWR_FLAG_USB33RDY)  ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\
 467  ((__FLAG__) == PWR_FLAG_TEMPH)     ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\
 468  ((__FLAG__) == PWR_FLAG_TEMPL)     ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\
 469  ((__FLAG__) == PWR_FLAG_VBATH)     ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\
 470  ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
 471 #endif /* SMPS */
 472 #endif /* PWR_CPUCR_SBF_D2 */
 473 #endif /* DUAL_CORE */
 474
 475 /** @brief  Check PWR wake up flags are set or not.
 476   * @param  __FLAG__: specifies the wake up flag to check.
 477   *           This parameter can be one of the following values:
 478   *            @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag.
 479   *            @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag.
 480   *            @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag.
 481   *            @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag.
 482   *            @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag.
 483   *            @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag.
 484   * @note   The PWR_FLAG_WKUP3 and PWR_FLAG_WKUP5 are available only for devices
 485   *         that support GPIOI port.
 486   * @retval The (__FLAG__) state (TRUE or FALSE).
 487   */
 488 #define __HAL_PWR_GET_WAKEUPFLAG(__FLAG__) ((PWR->WKUPFR & (__FLAG__)) ? 0 : 1)
 489
 490 #if defined (DUAL_CORE)
 491 /** @brief  Clear CPU PWR flags.
 492   * @param  __FLAG__ : Specifies the flag to clear.
 493   * @note   This parameter is not used for the STM32H7 family and is kept as
 494   *         parameter just to maintain compatibility with other families.
 495   * @note   This macro clear all CPU flags STOPF, SBF, SBF_D1, and SBF_D2.
 496   *           This parameter can be one of the following values :
 497   *            @arg PWR_CPU_FLAGS : Clear HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2
 498   *                                 CPU flags.
 499   * @retval None.
 500   */
 501 #define __HAL_PWR_CLEAR_FLAG(__FLAG__)      \
 502 do {                                        \
 503      SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF);   \
 504      SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); \
 505 } while(0)
 506 #else
 507 /** @brief  Clear CPU PWR flags.
 508   * @param  __FLAG__ : Specifies the flag to clear.
 509   * @note   This parameter is not used for the STM32H7 family and is kept as
 510   *         parameter just to maintain compatibility with other families.
 511   * @note   This macro clear all CPU flags.
 512   *         For single core devices except STM32H7Axxx and STM32H7Bxxx, CPU
 513   *         flags are STOPF, SBF, SBF_D1 and SBF_D2.
 514   *         For STM32H7Axxx and STM32H7Bxxx lines, CPU flags are STOPF and SBF.
 515   * @retval None.
 516   */
 517 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)
 518 #endif /* defined (DUAL_CORE) */
 519
 520 /** @brief  Clear PWR wake up flags.
 521   * @param  __FLAG__ : Specifies the wake up flag to be cleared.
 522   *           This parameter can be one of the following values :
 523   *            @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag.
 524   *            @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag.
 525   *            @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag.
 526   *            @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag.
 527   *            @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag.
 528   *            @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag.
 529   * @note   The PWR_FLAG_WKUP3 and PWR_FLAG_WKUP5 are available only for devices
 530   *         that support GPIOI port.
 531   * @retval None.
 532   */
 533 #define __HAL_PWR_CLEAR_WAKEUPFLAG(__FLAG__) SET_BIT(PWR->WKUPCR, (__FLAG__))
 534
 535 /**
 536   * @brief Enable the PVD EXTI Line 16.
 537   * @retval None.
 538   */
 539 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
 540
 541 #if defined (DUAL_CORE)
 542 /**
 543   * @brief Enable the PVD EXTI D2 Line 16.
 544   * @retval None.
 545   */
 546 #define __HAL_PWR_PVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
 547 #endif /* defined (DUAL_CORE) */
 548
 549 /**
 550   * @brief Disable the PVD EXTI Line 16.
 551   * @retval None.
 552   */
 553 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
 554
 555 #if defined (DUAL_CORE)
 556 /**
 557   * @brief Disable the PVD EXTI D2 Line 16.
 558   * @retval None.
 559   */
 560 #define __HAL_PWR_PVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
 561 #endif /* defined (DUAL_CORE) */
 562
 563 /**
 564   * @brief   Enable event on PVD EXTI Line 16.
 565   * @retval None.
 566   */
 567 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
 568
 569 #if defined (DUAL_CORE)
 570 /**
 571   * @brief Enable event on PVD EXTI D2 Line.
 572   * @retval None.
 573   */
 574 #define __HAL_PWR_PVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
 575 #endif /* defined (DUAL_CORE) */
 576
 577 /**
 578   * @brief   Disable event on PVD EXTI Line 16.
 579   * @retval None.
 580   */
 581 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
 582
 583 #if defined (DUAL_CORE)
 584 /**
 585   * @brief Disable event on PVD EXTI D2 Line.
 586   * @retval None.
 587   */
 588 #define __HAL_PWR_PVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
 589 #endif /* defined (DUAL_CORE) */
 590
 591 /**
 592   * @brief Enable the PVD Rising Interrupt Trigger.
 593   * @retval None.
 594   */
 595 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
 596
 597 /**
 598   * @brief Disable the PVD Rising Interrupt Trigger.
 599   * @retval None.
 600   */
 601 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
 602
 603 /**
 604   * @brief Enable the PVD Falling Interrupt Trigger.
 605   * @retval None.
 606   */
 607 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
 608
 609 /**
 610   * @brief Disable the PVD Falling Interrupt Trigger.
 611   * @retval None.
 612   */
 613 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
 614
 615 /**
 616   * @brief Enable the PVD Rising & Falling Interrupt Trigger.
 617   * @retval None.
 618   */
 619 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
 620 do {                                                    \
 621       __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();          \
 622       __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();         \
 623 } while(0);
 624
 625 /**
 626   * @brief Disable the PVD Rising & Falling Interrupt Trigger.
 627   * @retval None.
 628   */
 629 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
 630 do {                                                     \
 631       __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();          \
 632       __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();         \
 633 } while(0);
 634
 635 /**
 636   * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
 637   * @retval EXTI PVD Line Status.
 638   */
 639 #define __HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
 640
 641 #if defined (DUAL_CORE)
 642 /**
 643   * @brief Checks whether the specified PVD EXTI interrupt flag is set or not.
 644   * @retval EXTI D2 PVD Line Status.
 645   */
 646 #define __HAL_PWR_PVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
 647 #endif /* defined (DUAL_CORE) */
 648
 649 /**
 650   * @brief Clear the PVD EXTI flag.
 651   * @retval None.
 652   */
 653 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD)
 654
 655 #if defined (DUAL_CORE)
 656 /**
 657   * @brief Clear the PVD EXTI D2 flag.
 658   * @retval None.
 659   */
 660 #define __HAL_PWR_PVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD)
 661 #endif /* defined (DUAL_CORE) */
 662
 663 /**
 664   * @brief  Generates a Software interrupt on PVD EXTI line.
 665   * @retval None.
 666   */
 667 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
 668 /**
 669   * @}
 670   */
 671
 672 /* Include PWR HAL Extension module */
 673 #include "stm32h7xx_hal_pwr_ex.h"
 674
 675 /* Exported functions --------------------------------------------------------*/
 676 /** @addtogroup PWR_Exported_Functions PWR Exported Functions
 677   * @{
 678   */
 679
 680 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions
 681   * @{
 682   */
 683 /* Initialization and de-initialization functions *****************************/
 684 void HAL_PWR_DeInit            (void);
 685 void HAL_PWR_EnableBkUpAccess  (void);
 686 void HAL_PWR_DisableBkUpAccess (void);
 687 /**
 688   * @}
 689   */
 690
 691 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control Functions
 692   * @{
 693   */
 694 /* Peripheral Control functions  **********************************************/
 695 /* PVD configuration */
 696 void HAL_PWR_ConfigPVD  (PWR_PVDTypeDef *sConfigPVD);
 697 void HAL_PWR_EnablePVD  (void);
 698 void HAL_PWR_DisablePVD (void);
 699
 700 /* WakeUp pins configuration */
 701 void HAL_PWR_EnableWakeUpPin  (uint32_t WakeUpPinPolarity);
 702 void HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx);
 703
 704 /* Low Power modes entry */
 705 void HAL_PWR_EnterSTOPMode    (uint32_t Regulator, uint8_t STOPEntry);
 706 void HAL_PWR_EnterSLEEPMode   (uint32_t Regulator, uint8_t SLEEPEntry);
 707 void HAL_PWR_EnterSTANDBYMode (void);
 708
 709 /* Power PVD IRQ Handler */
 710 void HAL_PWR_PVD_IRQHandler (void);
 711 void HAL_PWR_PVDCallback    (void);
 712
 713 /* Cortex System Control functions  *******************************************/
 714 void HAL_PWR_EnableSleepOnExit  (void);
 715 void HAL_PWR_DisableSleepOnExit (void);
 716 void HAL_PWR_EnableSEVOnPend    (void);
 717 void HAL_PWR_DisableSEVOnPend   (void);
 718 /**
 719   * @}
 720   */
 721
 722 /**
 723   * @}
 724   */
 725
 726 /* Private types -------------------------------------------------------------*/
 727 /* Private variables ---------------------------------------------------------*/
 728 /* Private constants ---------------------------------------------------------*/
 729 /** @defgroup PWR_Private_Constants PWR Private Constants
 730   * @{
 731   */
 732
 733 /** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
 734   * @{
 735   */
 736 #define PWR_EXTI_LINE_PVD  EXTI_IMR1_IM16 /*!< External interrupt line 16
 737                                                Connected to the PVD EXTI Line */
 738 /**
 739   * @}
 740   */
 741
 742 /**
 743   * @}
 744   */
 745 /* Private macros ------------------------------------------------------------*/
 746 /** @defgroup PWR_Private_Macros PWR Private Macros
 747   * @{
 748   */
 749
 750 /** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
 751   * @{
 752   */
 753 /* Check PVD level parameter */
 754 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) ||\
 755                                  ((LEVEL) == PWR_PVDLEVEL_1) ||\
 756                                  ((LEVEL) == PWR_PVDLEVEL_2) ||\
 757                                  ((LEVEL) == PWR_PVDLEVEL_3) ||\
 758                                  ((LEVEL) == PWR_PVDLEVEL_4) ||\
 759                                  ((LEVEL) == PWR_PVDLEVEL_5) ||\
 760                                  ((LEVEL) == PWR_PVDLEVEL_6) ||\
 761                                  ((LEVEL) == PWR_PVDLEVEL_7))
 762
 763 /* Check PVD mode parameter */
 764 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)            ||\
 765                                ((MODE) == PWR_PVD_MODE_IT_FALLING)           ||\
 766                                ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING)    ||\
 767                                ((MODE) == PWR_PVD_MODE_EVENT_RISING)         ||\
 768                                ((MODE) == PWR_PVD_MODE_EVENT_FALLING)        ||\
 769                                ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) ||\
 770                                ((MODE) == PWR_PVD_MODE_NORMAL))
 771
 772 /* Check low power regulator parameter */
 773 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON)   ||\
 774                                      ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
 775
 776 /* Check low power mode entry parameter */
 777 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) ||\
 778                                    ((ENTRY) == PWR_SLEEPENTRY_WFE))
 779
 780 /* Check low power mode entry parameter */
 781 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) ||\
 782                                   ((ENTRY) == PWR_STOPENTRY_WFE))
 783
 784 /* Check voltage scale level parameter */
 785 #define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE0) || \
 786                                            ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
 787                                            ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
 788                                            ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
 789 /**
 790   * @}
 791   */
 792
 793 /**
 794   * @}
 795   */
 796
 797 /**
 798   * @}
 799   */
 800
 801 /**
 802   * @}
 803   */
 804
 805 #ifdef __cplusplus
 806 }
 807 #endif /* __cplusplus */
 808
 809 #endif /* STM32H7xx_HAL_PWR_H */
 810
 811 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/