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Merge pull request #11270 from haslinghuis/rename_attr
[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_hal_spi.h
blob47f26a17365830dd3c49aae2aed71593cfd71cbd
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal_spi.h
4 * @author MCD Application Team
5 * @brief Header file of SPI HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_HAL_SPI_H
22 #define STM32H7xx_HAL_SPI_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx_hal_def.h"
30
31 /** @addtogroup STM32H7xx_HAL_Driver
32 * @{
33 */
34
35 /** @addtogroup SPI
36 * @{
37 */
38
39 /* Exported types ------------------------------------------------------------*/
40 /** @defgroup SPI_Exported_Types SPI Exported Types
41 * @{
42 */
43
44 /**
45 * @brief SPI Configuration Structure definition
46 */
47 typedef struct
48 {
49 uint32_t Mode; /*!< Specifies the SPI operating mode.
50 This parameter can be a value of @ref SPI_Mode */
51
52 uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
53 This parameter can be a value of @ref SPI_Direction */
54
55 uint32_t DataSize; /*!< Specifies the SPI data size.
56 This parameter can be a value of @ref SPI_Data_Size */
57
58 uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
59 This parameter can be a value of @ref SPI_Clock_Polarity */
60
61 uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
62 This parameter can be a value of @ref SPI_Clock_Phase */
63
64 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
65 hardware (NSS pin) or by software using the SSI bit.
66 This parameter can be a value of @ref SPI_Slave_Select_Management */
67
68 uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
69 used to configure the transmit and receive SCK clock.
70 This parameter can be a value of @ref SPI_BaudRate_Prescaler
71 @note The communication clock is derived from the master
72 clock. The slave clock does not need to be set. */
73
74 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
75 This parameter can be a value of @ref SPI_MSB_LSB_Transmission */
76
77 uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
78 This parameter can be a value of @ref SPI_TI_Mode */
79
80 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
81 This parameter can be a value of @ref SPI_CRC_Calculation */
82
83 uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
84 This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535 */
85
86 uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
87 This parameter can be a value of @ref SPI_CRC_length */
88
89 uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
90 This parameter can be a value of @ref SPI_NSSP_Mode
91 This mode is activated by the SSOM bit in the SPIx_CR2 register and
92 it takes effect only if the SPI interface is configured as Motorola SPI
93 master (FRF=0). */
94
95 uint32_t NSSPolarity; /*!< Specifies which level of SS input/output external signal (present on SS pin) is
96 considered as active one.
97 This parameter can be a value of @ref SPI_NSS_Polarity */
98
99 uint32_t FifoThreshold; /*!< Specifies the FIFO threshold level.
100 This parameter can be a value of @ref SPI_Fifo_Threshold */
101
102 uint32_t TxCRCInitializationPattern; /*!< Specifies the transmitter CRC initialization Pattern used for the CRC calculation.
103 This parameter can be a value of @ref SPI_CRC_Calculation_Initialization_Pattern */
104
105 uint32_t RxCRCInitializationPattern; /*!< Specifies the receiver CRC initialization Pattern used for the CRC calculation.
106 This parameter can be a value of @ref SPI_CRC_Calculation_Initialization_Pattern */
107
108 uint32_t MasterSSIdleness; /*!< Specifies an extra delay, expressed in number of SPI clock cycle periods, inserted
109 additionally between active edge of SS and first data transaction start in master mode.
110 This parameter can be a value of @ref SPI_Master_SS_Idleness */
111
112 uint32_t MasterInterDataIdleness; /*!< Specifies minimum time delay (expressed in SPI clock cycles periods) inserted between
113 two consecutive data frames in master mode
114 This parameter can be a value of @ref SPI_Master_InterData_Idleness */
115
116 uint32_t MasterReceiverAutoSusp; /*!< Control continuous SPI transfer in master receiver mode and automatic management
117 in order to avoid overrun condition.
118 This parameter can be a value of @ref SPI_Master_RX_AutoSuspend*/
119
120 uint32_t MasterKeepIOState; /*!< Control of Alternate function GPIOs state
121 This parameter can be a value of @ref SPI_Master_Keep_IO_State */
122
123 uint32_t IOSwap; /*!< Invert MISO/MOSI alternate functions
124 This parameter can be a value of @ref SPI_IO_Swap */
125
126 } SPI_InitTypeDef;
127
128 /**
129 * @brief HAL SPI State structure definition
130 */
131 typedef enum
132 {
133 HAL_SPI_STATE_RESET = 0x00UL, /*!< Peripheral not Initialized */
134 HAL_SPI_STATE_READY = 0x01UL, /*!< Peripheral Initialized and ready for use */
135 HAL_SPI_STATE_BUSY = 0x02UL, /*!< an internal process is ongoing */
136 HAL_SPI_STATE_BUSY_TX = 0x03UL, /*!< Data Transmission process is ongoing */
137 HAL_SPI_STATE_BUSY_RX = 0x04UL, /*!< Data Reception process is ongoing */
138 HAL_SPI_STATE_BUSY_TX_RX = 0x05UL, /*!< Data Transmission and Reception process is ongoing */
139 HAL_SPI_STATE_ERROR = 0x06UL, /*!< SPI error state */
140 HAL_SPI_STATE_ABORT = 0x07UL /*!< SPI abort is ongoing */
141 } HAL_SPI_StateTypeDef;
142
143 #if defined(USE_SPI_RELOAD_TRANSFER)
144 /**
145 * @brief SPI Reload Structure definition
146 */
147 typedef struct
148 {
149 uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
150
151 uint16_t TxXferSize; /*!< SPI Tx Transfer size to reload */
152
153 uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
154
155 uint16_t RxXferSize; /*!< SPI Rx Transfer size to reload */
156
157 uint32_t Requested; /*!< SPI reload request */
158
159 } SPI_ReloadTypeDef;
160 #endif /* USE_HSPI_RELOAD_TRANSFER */
161
162 /**
163 * @brief SPI handle Structure definition
164 */
165 typedef struct __SPI_HandleTypeDef
166 {
167 SPI_TypeDef *Instance; /*!< SPI registers base address */
168
169 SPI_InitTypeDef Init; /*!< SPI communication parameters */
170
171 uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
172
173 uint16_t TxXferSize; /*!< SPI Tx Transfer size */
174
175 __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
176
177 uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
178
179 uint16_t RxXferSize; /*!< SPI Rx Transfer size */
180
181 __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
182
183 uint32_t CRCSize; /*!< SPI CRC size used for the transfer */
184
185 void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */
186
187 void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */
188
189 DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
190
191 DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
192
193 HAL_LockTypeDef Lock; /*!< Locking object */
194
195 __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
196
197 __IO uint32_t ErrorCode; /*!< SPI Error code */
198
199 #if defined(USE_SPI_RELOAD_TRANSFER)
200
201 SPI_ReloadTypeDef Reload; /*!< SPI reload parameters */
202
203 #endif /* USE_HSPI_RELOAD_TRANSFER */
204
205 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
206 void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */
207 void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */
208 void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */
209 void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */
210 void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */
211 void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */
212 void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */
213 void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */
214 void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */
215 void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */
216
217 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
218 } SPI_HandleTypeDef;
219
220 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
221 /**
222 * @brief HAL SPI Callback ID enumeration definition
223 */
224 typedef enum
225 {
226 HAL_SPI_TX_COMPLETE_CB_ID = 0x00UL, /*!< SPI Tx Completed callback ID */
227 HAL_SPI_RX_COMPLETE_CB_ID = 0x01UL, /*!< SPI Rx Completed callback ID */
228 HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02UL, /*!< SPI TxRx Completed callback ID */
229 HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03UL, /*!< SPI Tx Half Completed callback ID */
230 HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04UL, /*!< SPI Rx Half Completed callback ID */
231 HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05UL, /*!< SPI TxRx Half Completed callback ID */
232 HAL_SPI_ERROR_CB_ID = 0x06UL, /*!< SPI Error callback ID */
233 HAL_SPI_ABORT_CB_ID = 0x07UL, /*!< SPI Abort callback ID */
234 HAL_SPI_MSPINIT_CB_ID = 0x08UL, /*!< SPI Msp Init callback ID */
235 HAL_SPI_MSPDEINIT_CB_ID = 0x09UL /*!< SPI Msp DeInit callback ID */
236
237 } HAL_SPI_CallbackIDTypeDef;
238
239 /**
240 * @brief HAL SPI Callback pointer definition
241 */
242 typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */
243
244 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
245 /**
246 * @}
247 */
248
249 /* Exported constants --------------------------------------------------------*/
250
251 /** @defgroup SPI_Exported_Constants SPI Exported Constants
252 * @{
253 */
254
255 /** @defgroup SPI_FIFO_Type SPI FIFO Type
256 * @{
257 */
258 #define SPI_LOWEND_FIFO_SIZE 8UL
259 #define SPI_HIGHEND_FIFO_SIZE 16UL
260 /**
261 * @}
262 */
263
264 /** @defgroup SPI_Error_Code SPI Error Codes
265 * @{
266 */
267 #define HAL_SPI_ERROR_NONE (0x00000000UL) /*!< No error */
268 #define HAL_SPI_ERROR_MODF (0x00000001UL) /*!< MODF error */
269 #define HAL_SPI_ERROR_CRC (0x00000002UL) /*!< CRC error */
270 #define HAL_SPI_ERROR_OVR (0x00000004UL) /*!< OVR error */
271 #define HAL_SPI_ERROR_FRE (0x00000008UL) /*!< FRE error */
272 #define HAL_SPI_ERROR_DMA (0x00000010UL) /*!< DMA transfer error */
273 #define HAL_SPI_ERROR_FLAG (0x00000020UL) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
274 #define HAL_SPI_ERROR_ABORT (0x00000040UL) /*!< Error during SPI Abort procedure */
275 #define HAL_SPI_ERROR_UDR (0x00000080UL) /*!< Underrun error */
276 #define HAL_SPI_ERROR_TIMEOUT (0x00000100UL) /*!< Timeout error */
277 #define HAL_SPI_ERROR_UNKNOW (0x00000200UL) /*!< Unknow error */
278 #define HAL_SPI_ERROR_NOT_SUPPORTED (0x00000400UL) /*!< Requested operation not supported */
279 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
280 #define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000800UL) /*!< Invalid Callback error */
281 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
282 /**
283 * @}
284 */
285
286 /** @defgroup SPI_Mode SPI Mode
287 * @{
288 */
289 #define SPI_MODE_SLAVE (0x00000000UL)
290 #define SPI_MODE_MASTER SPI_CFG2_MASTER
291 /**
292 * @}
293 */
294
295 /** @defgroup SPI_Direction SPI Direction Mode
296 * @{
297 */
298 #define SPI_DIRECTION_2LINES (0x00000000UL)
299 #define SPI_DIRECTION_2LINES_TXONLY SPI_CFG2_COMM_0
300 #define SPI_DIRECTION_2LINES_RXONLY SPI_CFG2_COMM_1
301 #define SPI_DIRECTION_1LINE SPI_CFG2_COMM
302 /**
303 * @}
304 */
305
306 /** @defgroup SPI_Data_Size SPI Data Size
307 * @{
308 */
309 #define SPI_DATASIZE_4BIT (0x00000003UL)
310 #define SPI_DATASIZE_5BIT (0x00000004UL)
311 #define SPI_DATASIZE_6BIT (0x00000005UL)
312 #define SPI_DATASIZE_7BIT (0x00000006UL)
313 #define SPI_DATASIZE_8BIT (0x00000007UL)
314 #define SPI_DATASIZE_9BIT (0x00000008UL)
315 #define SPI_DATASIZE_10BIT (0x00000009UL)
316 #define SPI_DATASIZE_11BIT (0x0000000AUL)
317 #define SPI_DATASIZE_12BIT (0x0000000BUL)
318 #define SPI_DATASIZE_13BIT (0x0000000CUL)
319 #define SPI_DATASIZE_14BIT (0x0000000DUL)
320 #define SPI_DATASIZE_15BIT (0x0000000EUL)
321 #define SPI_DATASIZE_16BIT (0x0000000FUL)
322 #define SPI_DATASIZE_17BIT (0x00000010UL)
323 #define SPI_DATASIZE_18BIT (0x00000011UL)
324 #define SPI_DATASIZE_19BIT (0x00000012UL)
325 #define SPI_DATASIZE_20BIT (0x00000013UL)
326 #define SPI_DATASIZE_21BIT (0x00000014UL)
327 #define SPI_DATASIZE_22BIT (0x00000015UL)
328 #define SPI_DATASIZE_23BIT (0x00000016UL)
329 #define SPI_DATASIZE_24BIT (0x00000017UL)
330 #define SPI_DATASIZE_25BIT (0x00000018UL)
331 #define SPI_DATASIZE_26BIT (0x00000019UL)
332 #define SPI_DATASIZE_27BIT (0x0000001AUL)
333 #define SPI_DATASIZE_28BIT (0x0000001BUL)
334 #define SPI_DATASIZE_29BIT (0x0000001CUL)
335 #define SPI_DATASIZE_30BIT (0x0000001DUL)
336 #define SPI_DATASIZE_31BIT (0x0000001EUL)
337 #define SPI_DATASIZE_32BIT (0x0000001FUL)
338 /**
339 * @}
340 */
341
342 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
343 * @{
344 */
345 #define SPI_POLARITY_LOW (0x00000000UL)
346 #define SPI_POLARITY_HIGH SPI_CFG2_CPOL
347 /**
348 * @}
349 */
350
351 /** @defgroup SPI_Clock_Phase SPI Clock Phase
352 * @{
353 */
354 #define SPI_PHASE_1EDGE (0x00000000UL)
355 #define SPI_PHASE_2EDGE SPI_CFG2_CPHA
356 /**
357 * @}
358 */
359
360 /** @defgroup SPI_Slave_Select_Management SPI Slave Select Management
361 * @{
362 */
363 #define SPI_NSS_SOFT SPI_CFG2_SSM
364 #define SPI_NSS_HARD_INPUT (0x00000000UL)
365 #define SPI_NSS_HARD_OUTPUT SPI_CFG2_SSOE
366 /**
367 * @}
368 */
369
370 /** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
371 * @{
372 */
373 #define SPI_NSS_PULSE_DISABLE (0x00000000UL)
374 #define SPI_NSS_PULSE_ENABLE SPI_CFG2_SSOM
375 /**
376 * @}
377 */
378
379 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
380 * @{
381 */
382 #define SPI_BAUDRATEPRESCALER_2 (0x00000000UL)
383 #define SPI_BAUDRATEPRESCALER_4 (0x10000000UL)
384 #define SPI_BAUDRATEPRESCALER_8 (0x20000000UL)
385 #define SPI_BAUDRATEPRESCALER_16 (0x30000000UL)
386 #define SPI_BAUDRATEPRESCALER_32 (0x40000000UL)
387 #define SPI_BAUDRATEPRESCALER_64 (0x50000000UL)
388 #define SPI_BAUDRATEPRESCALER_128 (0x60000000UL)
389 #define SPI_BAUDRATEPRESCALER_256 (0x70000000UL)
390 /**
391 * @}
392 */
393
394 /** @defgroup SPI_MSB_LSB_Transmission SPI MSB LSB Transmission
395 * @{
396 */
397 #define SPI_FIRSTBIT_MSB (0x00000000UL)
398 #define SPI_FIRSTBIT_LSB SPI_CFG2_LSBFRST
399 /**
400 * @}
401 */
402
403 /** @defgroup SPI_TI_Mode SPI TI Mode
404 * @{
405 */
406 #define SPI_TIMODE_DISABLE (0x00000000UL)
407 #define SPI_TIMODE_ENABLE SPI_CFG2_SP_0
408 /**
409 * @}
410 */
411
412 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
413 * @{
414 */
415 #define SPI_CRCCALCULATION_DISABLE (0x00000000UL)
416 #define SPI_CRCCALCULATION_ENABLE SPI_CFG1_CRCEN
417 /**
418 * @}
419 */
420
421 /** @defgroup SPI_CRC_length SPI CRC Length
422 * @{
423 */
424 #define SPI_CRC_LENGTH_DATASIZE (0x00000000UL)
425 #define SPI_CRC_LENGTH_4BIT (0x00030000UL)
426 #define SPI_CRC_LENGTH_5BIT (0x00040000UL)
427 #define SPI_CRC_LENGTH_6BIT (0x00050000UL)
428 #define SPI_CRC_LENGTH_7BIT (0x00060000UL)
429 #define SPI_CRC_LENGTH_8BIT (0x00070000UL)
430 #define SPI_CRC_LENGTH_9BIT (0x00080000UL)
431 #define SPI_CRC_LENGTH_10BIT (0x00090000UL)
432 #define SPI_CRC_LENGTH_11BIT (0x000A0000UL)
433 #define SPI_CRC_LENGTH_12BIT (0x000B0000UL)
434 #define SPI_CRC_LENGTH_13BIT (0x000C0000UL)
435 #define SPI_CRC_LENGTH_14BIT (0x000D0000UL)
436 #define SPI_CRC_LENGTH_15BIT (0x000E0000UL)
437 #define SPI_CRC_LENGTH_16BIT (0x000F0000UL)
438 #define SPI_CRC_LENGTH_17BIT (0x00100000UL)
439 #define SPI_CRC_LENGTH_18BIT (0x00110000UL)
440 #define SPI_CRC_LENGTH_19BIT (0x00120000UL)
441 #define SPI_CRC_LENGTH_20BIT (0x00130000UL)
442 #define SPI_CRC_LENGTH_21BIT (0x00140000UL)
443 #define SPI_CRC_LENGTH_22BIT (0x00150000UL)
444 #define SPI_CRC_LENGTH_23BIT (0x00160000UL)
445 #define SPI_CRC_LENGTH_24BIT (0x00170000UL)
446 #define SPI_CRC_LENGTH_25BIT (0x00180000UL)
447 #define SPI_CRC_LENGTH_26BIT (0x00190000UL)
448 #define SPI_CRC_LENGTH_27BIT (0x001A0000UL)
449 #define SPI_CRC_LENGTH_28BIT (0x001B0000UL)
450 #define SPI_CRC_LENGTH_29BIT (0x001C0000UL)
451 #define SPI_CRC_LENGTH_30BIT (0x001D0000UL)
452 #define SPI_CRC_LENGTH_31BIT (0x001E0000UL)
453 #define SPI_CRC_LENGTH_32BIT (0x001F0000UL)
454 /**
455 * @}
456 */
457
458 /** @defgroup SPI_Fifo_Threshold SPI Fifo Threshold
459 * @{
460 */
461 #define SPI_FIFO_THRESHOLD_01DATA (0x00000000UL)
462 #define SPI_FIFO_THRESHOLD_02DATA (0x00000020UL)
463 #define SPI_FIFO_THRESHOLD_03DATA (0x00000040UL)
464 #define SPI_FIFO_THRESHOLD_04DATA (0x00000060UL)
465 #define SPI_FIFO_THRESHOLD_05DATA (0x00000080UL)
466 #define SPI_FIFO_THRESHOLD_06DATA (0x000000A0UL)
467 #define SPI_FIFO_THRESHOLD_07DATA (0x000000C0UL)
468 #define SPI_FIFO_THRESHOLD_08DATA (0x000000E0UL)
469 #define SPI_FIFO_THRESHOLD_09DATA (0x00000100UL)
470 #define SPI_FIFO_THRESHOLD_10DATA (0x00000120UL)
471 #define SPI_FIFO_THRESHOLD_11DATA (0x00000140UL)
472 #define SPI_FIFO_THRESHOLD_12DATA (0x00000160UL)
473 #define SPI_FIFO_THRESHOLD_13DATA (0x00000180UL)
474 #define SPI_FIFO_THRESHOLD_14DATA (0x000001A0UL)
475 #define SPI_FIFO_THRESHOLD_15DATA (0x000001C0UL)
476 #define SPI_FIFO_THRESHOLD_16DATA (0x000001E0UL)
477 /**
478 * @}
479 */
480
481 /** @defgroup SPI_CRC_Calculation_Initialization_Pattern SPI CRC Calculation Initialization Pattern
482 * @{
483 */
484 #define SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN (0x00000000UL)
485 #define SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN (0x00000001UL)
486 /**
487 * @}
488 */
489
490 /** @defgroup SPI_NSS_Polarity SPI NSS Polarity
491 * @{
492 */
493 #define SPI_NSS_POLARITY_LOW (0x00000000UL)
494 #define SPI_NSS_POLARITY_HIGH SPI_CFG2_SSIOP
495 /**
496 * @}
497 */
498
499 /** @defgroup SPI_Master_Keep_IO_State Keep IO State
500 * @{
501 */
502 #define SPI_MASTER_KEEP_IO_STATE_DISABLE (0x00000000UL)
503 #define SPI_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR
504 /**
505 * @}
506 */
507
508 /** @defgroup SPI_IO_Swap Control SPI IO Swap
509 * @{
510 */
511 #define SPI_IO_SWAP_DISABLE (0x00000000UL)
512 #define SPI_IO_SWAP_ENABLE SPI_CFG2_IOSWP
513 /**
514 * @}
515 */
516
517 /** @defgroup SPI_Master_SS_Idleness SPI Master SS Idleness
518 * @{
519 */
520 #define SPI_MASTER_SS_IDLENESS_00CYCLE (0x00000000UL)
521 #define SPI_MASTER_SS_IDLENESS_01CYCLE (0x00000001UL)
522 #define SPI_MASTER_SS_IDLENESS_02CYCLE (0x00000002UL)
523 #define SPI_MASTER_SS_IDLENESS_03CYCLE (0x00000003UL)
524 #define SPI_MASTER_SS_IDLENESS_04CYCLE (0x00000004UL)
525 #define SPI_MASTER_SS_IDLENESS_05CYCLE (0x00000005UL)
526 #define SPI_MASTER_SS_IDLENESS_06CYCLE (0x00000006UL)
527 #define SPI_MASTER_SS_IDLENESS_07CYCLE (0x00000007UL)
528 #define SPI_MASTER_SS_IDLENESS_08CYCLE (0x00000008UL)
529 #define SPI_MASTER_SS_IDLENESS_09CYCLE (0x00000009UL)
530 #define SPI_MASTER_SS_IDLENESS_10CYCLE (0x0000000AUL)
531 #define SPI_MASTER_SS_IDLENESS_11CYCLE (0x0000000BUL)
532 #define SPI_MASTER_SS_IDLENESS_12CYCLE (0x0000000CUL)
533 #define SPI_MASTER_SS_IDLENESS_13CYCLE (0x0000000DUL)
534 #define SPI_MASTER_SS_IDLENESS_14CYCLE (0x0000000EUL)
535 #define SPI_MASTER_SS_IDLENESS_15CYCLE (0x0000000FUL)
536 /**
537 * @}
538 */
539
540 /** @defgroup SPI_Master_InterData_Idleness SPI Master Inter-Data Idleness
541 * @{
542 */
543 #define SPI_MASTER_INTERDATA_IDLENESS_00CYCLE (0x00000000UL)
544 #define SPI_MASTER_INTERDATA_IDLENESS_01CYCLE (0x00000010UL)
545 #define SPI_MASTER_INTERDATA_IDLENESS_02CYCLE (0x00000020UL)
546 #define SPI_MASTER_INTERDATA_IDLENESS_03CYCLE (0x00000030UL)
547 #define SPI_MASTER_INTERDATA_IDLENESS_04CYCLE (0x00000040UL)
548 #define SPI_MASTER_INTERDATA_IDLENESS_05CYCLE (0x00000050UL)
549 #define SPI_MASTER_INTERDATA_IDLENESS_06CYCLE (0x00000060UL)
550 #define SPI_MASTER_INTERDATA_IDLENESS_07CYCLE (0x00000070UL)
551 #define SPI_MASTER_INTERDATA_IDLENESS_08CYCLE (0x00000080UL)
552 #define SPI_MASTER_INTERDATA_IDLENESS_09CYCLE (0x00000090UL)
553 #define SPI_MASTER_INTERDATA_IDLENESS_10CYCLE (0x000000A0UL)
554 #define SPI_MASTER_INTERDATA_IDLENESS_11CYCLE (0x000000B0UL)
555 #define SPI_MASTER_INTERDATA_IDLENESS_12CYCLE (0x000000C0UL)
556 #define SPI_MASTER_INTERDATA_IDLENESS_13CYCLE (0x000000D0UL)
557 #define SPI_MASTER_INTERDATA_IDLENESS_14CYCLE (0x000000E0UL)
558 #define SPI_MASTER_INTERDATA_IDLENESS_15CYCLE (0x000000F0UL)
559 /**
560 * @}
561 */
562
563 /** @defgroup SPI_Master_RX_AutoSuspend SPI Master Receiver AutoSuspend
564 * @{
565 */
566 #define SPI_MASTER_RX_AUTOSUSP_DISABLE (0x00000000UL)
567 #define SPI_MASTER_RX_AUTOSUSP_ENABLE SPI_CR1_MASRX
568 /**
569 * @}
570 */
571
572 /** @defgroup SPI_Underrun_Detection SPI Underrun Detection
573 * @{
574 */
575 #define SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME (0x00000000UL)
576 #define SPI_UNDERRUN_DETECT_END_DATA_FRAME SPI_CFG1_UDRDET_0
577 #define SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS SPI_CFG1_UDRDET_1
578 /**
579 * @}
580 */
581
582 /** @defgroup SPI_Underrun_Behaviour SPI Underrun Behavior
583 * @{
584 */
585 #define SPI_UNDERRUN_BEHAV_REGISTER_PATTERN (0x00000000UL)
586 #define SPI_UNDERRUN_BEHAV_LAST_RECEIVED SPI_CFG1_UDRCFG_0
587 #define SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED SPI_CFG1_UDRCFG_1
588 /**
589 * @}
590 */
591
592 /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
593 * @{
594 */
595 #define SPI_IT_RXP SPI_IER_RXPIE
596 #define SPI_IT_TXP SPI_IER_TXPIE
597 #define SPI_IT_DXP SPI_IER_DXPIE
598 #define SPI_IT_EOT SPI_IER_EOTIE
599 #define SPI_IT_TXTF SPI_IER_TXTFIE
600 #define SPI_IT_UDR SPI_IER_UDRIE
601 #define SPI_IT_OVR SPI_IER_OVRIE
602 #define SPI_IT_CRCERR SPI_IER_CRCEIE
603 #define SPI_IT_FRE SPI_IER_TIFREIE
604 #define SPI_IT_MODF SPI_IER_MODFIE
605 #define SPI_IT_TSERF SPI_IER_TSERFIE
606 #define SPI_IT_ERR (SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_CRCERR)
607 /**
608 * @}
609 */
610
611 /** @defgroup SPI_Flags_definition SPI Flags Definition
612 * @{
613 */
614 #define SPI_FLAG_RXP SPI_SR_RXP /* SPI status flag : Rx-Packet available flag */
615 #define SPI_FLAG_TXP SPI_SR_TXP /* SPI status flag : Tx-Packet space available flag */
616 #define SPI_FLAG_DXP SPI_SR_DXP /* SPI status flag : Duplex Packet flag */
617 #define SPI_FLAG_EOT SPI_SR_EOT /* SPI status flag : End of transfer flag */
618 #define SPI_FLAG_TXTF SPI_SR_TXTF /* SPI status flag : Transmission Transfer Filled flag */
619 #define SPI_FLAG_UDR SPI_SR_UDR /* SPI Error flag : Underrun flag */
620 #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag : Overrun flag */
621 #define SPI_FLAG_CRCERR SPI_SR_CRCE /* SPI Error flag : CRC error flag */
622 #define SPI_FLAG_FRE SPI_SR_TIFRE /* SPI Error flag : TI mode frame format error flag */
623 #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag : Mode fault flag */
624 #define SPI_FLAG_TSERF SPI_SR_TSERF /* SPI status flag : Additional number of data reloaded flag */
625 #define SPI_FLAG_SUSP SPI_SR_SUSP /* SPI status flag : Transfer suspend complete flag */
626 #define SPI_FLAG_TXC SPI_SR_TXC /* SPI status flag : TxFIFO transmission complete flag */
627 #define SPI_FLAG_FRLVL SPI_SR_RXPLVL /* SPI status flag : Fifo reception level flag */
628 #define SPI_FLAG_RXWNE SPI_SR_RXWNE /* SPI status flag : RxFIFO word not empty flag */
629 /**
630 * @}
631 */
632
633 /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
634 * @{
635 */
636 #define SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packets available in the RxFIFO */
637 #define SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0)
638 #define SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1)
639 #define SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)
640 /**
641 * @}
642 */
643
644 /**
645 * @}
646 */
647
648 /* Exported macros -----------------------------------------------------------*/
649 /** @defgroup SPI_Exported_Macros SPI Exported Macros
650 * @{
651 */
652
653 /** @brief Reset SPI handle state.
654 * @param __HANDLE__: specifies the SPI Handle.
655 * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
656 * @retval None
657 */
658 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
659 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \
660 (__HANDLE__)->State = HAL_SPI_STATE_RESET; \
661 (__HANDLE__)->MspInitCallback = NULL; \
662 (__HANDLE__)->MspDeInitCallback = NULL; \
663 } while(0)
664 #else
665 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
666 #endif
667
668 /** @brief Enable the specified SPI interrupts.
669 * @param __HANDLE__: specifies the SPI Handle.
670 * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
671 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
672 * This parameter can be one of the following values:
673 * @arg SPI_IT_RXP : Rx-Packet available interrupt
674 * @arg SPI_IT_TXP : Tx-Packet space available interrupt
675 * @arg SPI_IT_DXP : Duplex Packet interrupt
676 * @arg SPI_IT_EOT : End of transfer interrupt
677 * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt
678 * @arg SPI_IT_UDR : Underrun interrupt
679 * @arg SPI_IT_OVR : Overrun interrupt
680 * @arg SPI_IT_CRCERR : CRC error interrupt
681 * @arg SPI_IT_FRE : TI mode frame format error interrupt
682 * @arg SPI_IT_MODF : Mode fault interrupt
683 * @arg SPI_IT_TSERF : Additional number of data reloaded interrupt
684 * @arg SPI_IT_ERR : Error interrupt
685 * @retval None
686 */
687 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
688
689 /** @brief Disable the specified SPI interrupts.
690 * @param __HANDLE__: specifies the SPI Handle.
691 * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
692 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
693 * This parameter can be one of the following values:
694 * @arg SPI_IT_RXP : Rx-Packet available interrupt
695 * @arg SPI_IT_TXP : Tx-Packet space available interrupt
696 * @arg SPI_IT_DXP : Duplex Packet interrupt
697 * @arg SPI_IT_EOT : End of transfer interrupt
698 * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt
699 * @arg SPI_IT_UDR : Underrun interrupt
700 * @arg SPI_IT_OVR : Overrun interrupt
701 * @arg SPI_IT_CRCERR : CRC error interrupt
702 * @arg SPI_IT_FRE : TI mode frame format error interrupt
703 * @arg SPI_IT_MODF : Mode fault interrupt
704 * @arg SPI_IT_TSERF : Additional number of data reloaded interrupt
705 * @arg SPI_IT_ERR : Error interrupt
706 * @retval None
707 */
708 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
709
710 /** @brief Check whether the specified SPI interrupt source is enabled or not.
711 * @param __HANDLE__: specifies the SPI Handle.
712 * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
713 * @param __INTERRUPT__: specifies the SPI interrupt source to check.
714 * This parameter can be one of the following values:
715 * @arg SPI_IT_RXP : Rx-Packet available interrupt
716 * @arg SPI_IT_TXP : Tx-Packet space available interrupt
717 * @arg SPI_IT_DXP : Duplex Packet interrupt
718 * @arg SPI_IT_EOT : End of transfer interrupt
719 * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt
720 * @arg SPI_IT_UDR : Underrun interrupt
721 * @arg SPI_IT_OVR : Overrun interrupt
722 * @arg SPI_IT_CRCERR : CRC error interrupt
723 * @arg SPI_IT_FRE : TI mode frame format error interrupt
724 * @arg SPI_IT_MODF : Mode fault interrupt
725 * @arg SPI_IT_TSERF : Additional number of data reloaded interrupt
726 * @arg SPI_IT_ERR : Error interrupt
727 * @retval The new state of __IT__ (TRUE or FALSE).
728 */
729 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
730
731 /** @brief Check whether the specified SPI flag is set or not.
732 * @param __HANDLE__: specifies the SPI Handle.
733 * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
734 * @param __FLAG__: specifies the flag to check.
735 * This parameter can be one of the following values:
736 * @arg SPI_FLAG_RXP : Rx-Packet available flag
737 * @arg SPI_FLAG_TXP : Tx-Packet space available flag
738 * @arg SPI_FLAG_DXP : Duplex Packet flag
739 * @arg SPI_FLAG_EOT : End of transfer flag
740 * @arg SPI_FLAG_TXTF : Transmission Transfer Filled flag
741 * @arg SPI_FLAG_UDR : Underrun flag
742 * @arg SPI_FLAG_OVR : Overrun flag
743 * @arg SPI_FLAG_CRCERR : CRC error flag
744 * @arg SPI_FLAG_FRE : TI mode frame format error flag
745 * @arg SPI_FLAG_MODF : Mode fault flag
746 * @arg SPI_FLAG_TSERF : Additional number of data reloaded flag
747 * @arg SPI_FLAG_SUSP : Transfer suspend complete flag
748 * @arg SPI_FLAG_TXC : TxFIFO transmission complete flag
749 * @arg SPI_FLAG_FRLVL : Fifo reception level flag
750 * @arg SPI_FLAG_RXWNE : RxFIFO word not empty flag
751 * @retval The new state of __FLAG__ (TRUE or FALSE).
752 */
753 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
754
755 /** @brief Clear the SPI CRCERR pending flag.
756 * @param __HANDLE__: specifies the SPI Handle.
757 * @retval None
758 */
759 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_CRCEC)
760
761 /** @brief Clear the SPI MODF pending flag.
762 * @param __HANDLE__: specifies the SPI Handle.
763 * @retval None
764 */
765 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , (uint32_t)(SPI_IFCR_MODFC));
766
767 /** @brief Clear the SPI OVR pending flag.
768 * @param __HANDLE__: specifies the SPI Handle.
769 * @retval None
770 */
771 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
772
773 /** @brief Clear the SPI FRE pending flag.
774 * @param __HANDLE__: specifies the SPI Handle.
775 * @retval None
776 */
777 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
778
779 /** @brief Clear the SPI UDR pending flag.
780 * @param __HANDLE__: specifies the SPI Handle.
781 * @retval None
782 */
783 #define __HAL_SPI_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
784
785 /** @brief Clear the SPI EOT pending flag.
786 * @param __HANDLE__: specifies the SPI Handle.
787 * @retval None
788 */
789 #define __HAL_SPI_CLEAR_EOTFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_EOTC)
790
791 /** @brief Clear the SPI UDR pending flag.
792 * @param __HANDLE__: specifies the SPI Handle.
793 * @retval None
794 */
795 #define __HAL_SPI_CLEAR_TXTFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TXTFC)
796
797 /** @brief Clear the SPI SUSP pending flag.
798 * @param __HANDLE__: specifies the SPI Handle.
799 * @retval None
800 */
801 #define __HAL_SPI_CLEAR_SUSPFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_SUSPC)
802
803 /** @brief Clear the SPI TSERF pending flag.
804 * @param __HANDLE__: specifies the SPI Handle.
805 * @retval None
806 */
807 #define __HAL_SPI_CLEAR_TSERFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TSERFC)
808
809 /** @brief Enable the SPI peripheral.
810 * @param __HANDLE__: specifies the SPI Handle.
811 * @retval None
812 */
813 #define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
814
815 /** @brief Disable the SPI peripheral.
816 * @param __HANDLE__: specifies the SPI Handle.
817 * @retval None
818 */
819 #define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
820 /**
821 * @}
822 */
823
824
825 /* Include SPI HAL Extension module */
826 #include "stm32h7xx_hal_spi_ex.h"
827
828
829 /* Exported functions --------------------------------------------------------*/
830 /** @addtogroup SPI_Exported_Functions
831 * @{
832 */
833
834 /** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
835 * @{
836 */
837 /* Initialization/de-initialization functions ********************************/
838 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
839 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
840 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
841 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
842
843 /* Callbacks Register/UnRegister functions ***********************************/
844 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
845 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback);
846 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
847 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
848 /**
849 * @}
850 */
851
852 /** @addtogroup SPI_Exported_Functions_Group2 IO operation functions
853 * @{
854 */
855 /* I/O operation functions ***************************************************/
856 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
857 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
858 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
859 uint32_t Timeout);
860 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
861 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
862 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
863
864 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
865 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
866 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
867
868 #if defined(USE_SPI_RELOAD_TRANSFER)
869 HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
870 HAL_StatusTypeDef HAL_SPI_Reload_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
871 HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
872 #endif /* USE_HSPI_RELOAD_TRANSFER */
873
874 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
875 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
876 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
877
878 /* Transfer Abort functions */
879 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
880 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
881
882 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
883 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
884 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
885 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
886 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
887 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
888 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
889 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
890 void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
891 /**
892 * @}
893 */
894
895 /** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
896 * @{
897 */
898
899 /* Peripheral State and Error functions ***************************************/
900 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
901 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
902 /**
903 * @}
904 */
905
906 /**
907 * @}
908 */
909
910 /* Private macros ------------------------------------------------------------*/
911 /** @defgroup SPI_Private_Macros SPI Private Macros
912 * @{
913 */
914
915 /** @brief Set the SPI transmit-only mode.
916 * @param __HANDLE__: specifies the SPI Handle.
917 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
918 * @retval None
919 */
920 #define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_HDDIR)
921
922 /** @brief Set the SPI receive-only mode.
923 * @param __HANDLE__: specifies the SPI Handle.
924 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
925 * @retval None
926 */
927 #define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 ,SPI_CR1_HDDIR)
928
929 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
930 ((MODE) == SPI_MODE_MASTER))
931
932 #define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
933 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
934 ((MODE) == SPI_DIRECTION_1LINE) || \
935 ((MODE) == SPI_DIRECTION_2LINES_TXONLY))
936
937 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
938
939 #define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE) ( \
940 ((MODE) == SPI_DIRECTION_2LINES)|| \
941 ((MODE) == SPI_DIRECTION_1LINE) || \
942 ((MODE) == SPI_DIRECTION_2LINES_TXONLY))
943
944 #define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE) ( \
945 ((MODE) == SPI_DIRECTION_2LINES)|| \
946 ((MODE) == SPI_DIRECTION_1LINE) || \
947 ((MODE) == SPI_DIRECTION_2LINES_RXONLY))
948
949 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_32BIT) || \
950 ((DATASIZE) == SPI_DATASIZE_31BIT) || \
951 ((DATASIZE) == SPI_DATASIZE_30BIT) || \
952 ((DATASIZE) == SPI_DATASIZE_29BIT) || \
953 ((DATASIZE) == SPI_DATASIZE_28BIT) || \
954 ((DATASIZE) == SPI_DATASIZE_27BIT) || \
955 ((DATASIZE) == SPI_DATASIZE_26BIT) || \
956 ((DATASIZE) == SPI_DATASIZE_25BIT) || \
957 ((DATASIZE) == SPI_DATASIZE_24BIT) || \
958 ((DATASIZE) == SPI_DATASIZE_23BIT) || \
959 ((DATASIZE) == SPI_DATASIZE_22BIT) || \
960 ((DATASIZE) == SPI_DATASIZE_21BIT) || \
961 ((DATASIZE) == SPI_DATASIZE_20BIT) || \
962 ((DATASIZE) == SPI_DATASIZE_22BIT) || \
963 ((DATASIZE) == SPI_DATASIZE_19BIT) || \
964 ((DATASIZE) == SPI_DATASIZE_18BIT) || \
965 ((DATASIZE) == SPI_DATASIZE_17BIT) || \
966 ((DATASIZE) == SPI_DATASIZE_16BIT) || \
967 ((DATASIZE) == SPI_DATASIZE_15BIT) || \
968 ((DATASIZE) == SPI_DATASIZE_14BIT) || \
969 ((DATASIZE) == SPI_DATASIZE_13BIT) || \
970 ((DATASIZE) == SPI_DATASIZE_12BIT) || \
971 ((DATASIZE) == SPI_DATASIZE_11BIT) || \
972 ((DATASIZE) == SPI_DATASIZE_10BIT) || \
973 ((DATASIZE) == SPI_DATASIZE_9BIT) || \
974 ((DATASIZE) == SPI_DATASIZE_8BIT) || \
975 ((DATASIZE) == SPI_DATASIZE_7BIT) || \
976 ((DATASIZE) == SPI_DATASIZE_6BIT) || \
977 ((DATASIZE) == SPI_DATASIZE_5BIT) || \
978 ((DATASIZE) == SPI_DATASIZE_4BIT))
979
980 #define IS_SPI_FIFOTHRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \
981 ((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \
982 ((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \
983 ((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \
984 ((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \
985 ((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \
986 ((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \
987 ((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA) || \
988 ((THRESHOLD) == SPI_FIFO_THRESHOLD_09DATA) || \
989 ((THRESHOLD) == SPI_FIFO_THRESHOLD_10DATA) || \
990 ((THRESHOLD) == SPI_FIFO_THRESHOLD_11DATA) || \
991 ((THRESHOLD) == SPI_FIFO_THRESHOLD_12DATA) || \
992 ((THRESHOLD) == SPI_FIFO_THRESHOLD_13DATA) || \
993 ((THRESHOLD) == SPI_FIFO_THRESHOLD_14DATA) || \
994 ((THRESHOLD) == SPI_FIFO_THRESHOLD_15DATA) || \
995 ((THRESHOLD) == SPI_FIFO_THRESHOLD_16DATA))
996
997 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
998 ((CPOL) == SPI_POLARITY_HIGH))
999
1000 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
1001 ((CPHA) == SPI_PHASE_2EDGE))
1002
1003 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
1004 ((NSS) == SPI_NSS_HARD_INPUT) || \
1005 ((NSS) == SPI_NSS_HARD_OUTPUT))
1006
1007 #define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
1008 ((NSSP) == SPI_NSS_PULSE_DISABLE))
1009
1010 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
1011 ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
1012 ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
1013 ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
1014 ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
1015 ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
1016 ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
1017 ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
1018
1019 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
1020 ((BIT) == SPI_FIRSTBIT_LSB))
1021
1022 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
1023 ((MODE) == SPI_TIMODE_ENABLE))
1024
1025 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
1026 ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
1027
1028 #define IS_SPI_CRC_INITIALIZATION_PATTERN(PATTERN) (((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN) || \
1029 ((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN))
1030
1031 #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) || \
1032 ((LENGTH) == SPI_CRC_LENGTH_32BIT) || \
1033 ((LENGTH) == SPI_CRC_LENGTH_31BIT) || \
1034 ((LENGTH) == SPI_CRC_LENGTH_30BIT) || \
1035 ((LENGTH) == SPI_CRC_LENGTH_29BIT) || \
1036 ((LENGTH) == SPI_CRC_LENGTH_28BIT) || \
1037 ((LENGTH) == SPI_CRC_LENGTH_27BIT) || \
1038 ((LENGTH) == SPI_CRC_LENGTH_26BIT) || \
1039 ((LENGTH) == SPI_CRC_LENGTH_25BIT) || \
1040 ((LENGTH) == SPI_CRC_LENGTH_24BIT) || \
1041 ((LENGTH) == SPI_CRC_LENGTH_23BIT) || \
1042 ((LENGTH) == SPI_CRC_LENGTH_22BIT) || \
1043 ((LENGTH) == SPI_CRC_LENGTH_21BIT) || \
1044 ((LENGTH) == SPI_CRC_LENGTH_20BIT) || \
1045 ((LENGTH) == SPI_CRC_LENGTH_19BIT) || \
1046 ((LENGTH) == SPI_CRC_LENGTH_18BIT) || \
1047 ((LENGTH) == SPI_CRC_LENGTH_17BIT) || \
1048 ((LENGTH) == SPI_CRC_LENGTH_16BIT) || \
1049 ((LENGTH) == SPI_CRC_LENGTH_15BIT) || \
1050 ((LENGTH) == SPI_CRC_LENGTH_14BIT) || \
1051 ((LENGTH) == SPI_CRC_LENGTH_13BIT) || \
1052 ((LENGTH) == SPI_CRC_LENGTH_12BIT) || \
1053 ((LENGTH) == SPI_CRC_LENGTH_11BIT) || \
1054 ((LENGTH) == SPI_CRC_LENGTH_10BIT) || \
1055 ((LENGTH) == SPI_CRC_LENGTH_9BIT) || \
1056 ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \
1057 ((LENGTH) == SPI_CRC_LENGTH_7BIT) || \
1058 ((LENGTH) == SPI_CRC_LENGTH_6BIT) || \
1059 ((LENGTH) == SPI_CRC_LENGTH_5BIT) || \
1060 ((LENGTH) == SPI_CRC_LENGTH_4BIT))
1061
1062 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1UL)
1063
1064 #define IS_SPI_UNDERRUN_DETECTION(MODE) (((MODE) == SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME) || \
1065 ((MODE) == SPI_UNDERRUN_DETECT_END_DATA_FRAME) || \
1066 ((MODE) == SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS))
1067
1068 #define IS_SPI_UNDERRUN_BEHAVIOUR(MODE) (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \
1069 ((MODE) == SPI_UNDERRUN_BEHAV_LAST_RECEIVED) || \
1070 ((MODE) == SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED))
1071 /**
1072 * @}
1073 */
1074
1075 /**
1076 * @}
1077 */
1078
1079 /**
1080 * @}
1081 */
1082
1083 #ifdef __cplusplus
1084 }
1085 #endif
1086
1087 #endif /* STM32H7xx_HAL_SPI_H */
1088
1089 /**
1090 * @}
1091 */
1092 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/