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Merge pull request #11270 from haslinghuis/rename_attr
[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_hal_tim.h
blob22d5f9cc0c67ad7517d98db20e53b0d814ba17a5
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_HAL_TIM_H
22 #define STM32H7xx_HAL_TIM_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx_hal_def.h"
30
31 /** @addtogroup STM32H7xx_HAL_Driver
32 * @{
33 */
34
35 /** @addtogroup TIM
36 * @{
37 */
38
39 /* Exported types ------------------------------------------------------------*/
40 /** @defgroup TIM_Exported_Types TIM Exported Types
41 * @{
42 */
43
44 /**
45 * @brief TIM Time base Configuration Structure definition
46 */
47 typedef struct
48 {
49 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
50 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
51
52 uint32_t CounterMode; /*!< Specifies the counter mode.
53 This parameter can be a value of @ref TIM_Counter_Mode */
54
55 uint32_t Period; /*!< Specifies the period value to be loaded into the active
56 Auto-Reload Register at the next update event.
57 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
58
59 uint32_t ClockDivision; /*!< Specifies the clock division.
60 This parameter can be a value of @ref TIM_ClockDivision */
61
62 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
63 reaches zero, an update event is generated and counting restarts
64 from the RCR value (N).
65 This means in PWM mode that (N+1) corresponds to:
66 - the number of PWM periods in edge-aligned mode
67 - the number of half PWM period in center-aligned mode
68 GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
69 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
70
71 uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
72 This parameter can be a value of @ref TIM_AutoReloadPreload */
73 } TIM_Base_InitTypeDef;
74
75 /**
76 * @brief TIM Output Compare Configuration Structure definition
77 */
78 typedef struct
79 {
80 uint32_t OCMode; /*!< Specifies the TIM mode.
81 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
82
83 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
84 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
85
86 uint32_t OCPolarity; /*!< Specifies the output polarity.
87 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
88
89 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
90 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
91 @note This parameter is valid only for timer instances supporting break feature. */
92
93 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
94 This parameter can be a value of @ref TIM_Output_Fast_State
95 @note This parameter is valid only in PWM1 and PWM2 mode. */
96
97
98 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
99 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
100 @note This parameter is valid only for timer instances supporting break feature. */
101
102 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
103 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
104 @note This parameter is valid only for timer instances supporting break feature. */
105 } TIM_OC_InitTypeDef;
106
107 /**
108 * @brief TIM One Pulse Mode Configuration Structure definition
109 */
110 typedef struct
111 {
112 uint32_t OCMode; /*!< Specifies the TIM mode.
113 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
114
115 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
116 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
117
118 uint32_t OCPolarity; /*!< Specifies the output polarity.
119 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
120
121 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
122 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
123 @note This parameter is valid only for timer instances supporting break feature. */
124
125 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
126 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
127 @note This parameter is valid only for timer instances supporting break feature. */
128
129 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
130 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
131 @note This parameter is valid only for timer instances supporting break feature. */
132
133 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
134 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
135
136 uint32_t ICSelection; /*!< Specifies the input.
137 This parameter can be a value of @ref TIM_Input_Capture_Selection */
138
139 uint32_t ICFilter; /*!< Specifies the input capture filter.
140 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
141 } TIM_OnePulse_InitTypeDef;
142
143 /**
144 * @brief TIM Input Capture Configuration Structure definition
145 */
146 typedef struct
147 {
148 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
149 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
150
151 uint32_t ICSelection; /*!< Specifies the input.
152 This parameter can be a value of @ref TIM_Input_Capture_Selection */
153
154 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
155 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
156
157 uint32_t ICFilter; /*!< Specifies the input capture filter.
158 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
159 } TIM_IC_InitTypeDef;
160
161 /**
162 * @brief TIM Encoder Configuration Structure definition
163 */
164 typedef struct
165 {
166 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
167 This parameter can be a value of @ref TIM_Encoder_Mode */
168
169 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
170 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
171
172 uint32_t IC1Selection; /*!< Specifies the input.
173 This parameter can be a value of @ref TIM_Input_Capture_Selection */
174
175 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
176 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
177
178 uint32_t IC1Filter; /*!< Specifies the input capture filter.
179 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
180
181 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
182 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
183
184 uint32_t IC2Selection; /*!< Specifies the input.
185 This parameter can be a value of @ref TIM_Input_Capture_Selection */
186
187 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
188 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
189
190 uint32_t IC2Filter; /*!< Specifies the input capture filter.
191 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
192 } TIM_Encoder_InitTypeDef;
193
194 /**
195 * @brief Clock Configuration Handle Structure definition
196 */
197 typedef struct
198 {
199 uint32_t ClockSource; /*!< TIM clock sources
200 This parameter can be a value of @ref TIM_Clock_Source */
201 uint32_t ClockPolarity; /*!< TIM clock polarity
202 This parameter can be a value of @ref TIM_Clock_Polarity */
203 uint32_t ClockPrescaler; /*!< TIM clock prescaler
204 This parameter can be a value of @ref TIM_Clock_Prescaler */
205 uint32_t ClockFilter; /*!< TIM clock filter
206 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
207 } TIM_ClockConfigTypeDef;
208
209 /**
210 * @brief TIM Clear Input Configuration Handle Structure definition
211 */
212 typedef struct
213 {
214 uint32_t ClearInputState; /*!< TIM clear Input state
215 This parameter can be ENABLE or DISABLE */
216 uint32_t ClearInputSource; /*!< TIM clear Input sources
217 This parameter can be a value of @ref TIM_ClearInput_Source */
218 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
219 This parameter can be a value of @ref TIM_ClearInput_Polarity */
220 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
221 This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
222 uint32_t ClearInputFilter; /*!< TIM Clear Input filter
223 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
224 } TIM_ClearInputConfigTypeDef;
225
226 /**
227 * @brief TIM Master configuration Structure definition
228 * @note Advanced timers provide TRGO2 internal line which is redirected
229 * to the ADC
230 */
231 typedef struct
232 {
233 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
234 This parameter can be a value of @ref TIM_Master_Mode_Selection */
235 uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
236 This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
237 uint32_t MasterSlaveMode; /*!< Master/slave mode selection
238 This parameter can be a value of @ref TIM_Master_Slave_Mode
239 @note When the Master/slave mode is enabled, the effect of
240 an event on the trigger input (TRGI) is delayed to allow a
241 perfect synchronization between the current timer and its
242 slaves (through TRGO). It is not mandatory in case of timer
243 synchronization mode. */
244 } TIM_MasterConfigTypeDef;
245
246 /**
247 * @brief TIM Slave configuration Structure definition
248 */
249 typedef struct
250 {
251 uint32_t SlaveMode; /*!< Slave mode selection
252 This parameter can be a value of @ref TIM_Slave_Mode */
253 uint32_t InputTrigger; /*!< Input Trigger source
254 This parameter can be a value of @ref TIM_Trigger_Selection */
255 uint32_t TriggerPolarity; /*!< Input Trigger polarity
256 This parameter can be a value of @ref TIM_Trigger_Polarity */
257 uint32_t TriggerPrescaler; /*!< Input trigger prescaler
258 This parameter can be a value of @ref TIM_Trigger_Prescaler */
259 uint32_t TriggerFilter; /*!< Input trigger filter
260 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
261
262 } TIM_SlaveConfigTypeDef;
263
264 /**
265 * @brief TIM Break input(s) and Dead time configuration Structure definition
266 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
267 * filter and polarity.
268 */
269 typedef struct
270 {
271 uint32_t OffStateRunMode; /*!< TIM off state in run mode
272 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
273 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
274 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
275 uint32_t LockLevel; /*!< TIM Lock level
276 This parameter can be a value of @ref TIM_Lock_level */
277 uint32_t DeadTime; /*!< TIM dead Time
278 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
279 uint32_t BreakState; /*!< TIM Break State
280 This parameter can be a value of @ref TIM_Break_Input_enable_disable */
281 uint32_t BreakPolarity; /*!< TIM Break input polarity
282 This parameter can be a value of @ref TIM_Break_Polarity */
283 uint32_t BreakFilter; /*!< Specifies the break input filter.
284 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
285 uint32_t Break2State; /*!< TIM Break2 State
286 This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
287 uint32_t Break2Polarity; /*!< TIM Break2 input polarity
288 This parameter can be a value of @ref TIM_Break2_Polarity */
289 uint32_t Break2Filter; /*!< TIM break2 input filter.
290 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
291 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
292 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
293 } TIM_BreakDeadTimeConfigTypeDef;
294
295 /**
296 * @brief HAL State structures definition
297 */
298 typedef enum
299 {
300 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
301 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
302 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
303 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
304 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
305 } HAL_TIM_StateTypeDef;
306
307 /**
308 * @brief TIM Channel States definition
309 */
310 typedef enum
311 {
312 HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */
313 HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */
314 HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */
315 } HAL_TIM_ChannelStateTypeDef;
316
317 /**
318 * @brief DMA Burst States definition
319 */
320 typedef enum
321 {
322 HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */
323 HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */
324 HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */
325 } HAL_TIM_DMABurstStateTypeDef;
326
327 /**
328 * @brief HAL Active channel structures definition
329 */
330 typedef enum
331 {
332 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
333 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
334 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
335 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
336 HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */
337 HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */
338 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
339 } HAL_TIM_ActiveChannel;
340
341 /**
342 * @brief TIM Time Base Handle Structure definition
343 */
344 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
345 typedef struct __TIM_HandleTypeDef
346 #else
347 typedef struct
348 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
349 {
350 TIM_TypeDef *Instance; /*!< Register base address */
351 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
352 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
353 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
354 This array is accessed by a @ref DMA_Handle_index */
355 HAL_LockTypeDef Lock; /*!< Locking object */
356 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
357 __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */
358 __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */
359 __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */
360
361 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
362 void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
363 void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */
364 void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */
365 void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */
366 void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */
367 void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */
368 void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */
369 void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */
370 void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */
371 void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */
372 void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */
373 void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */
374 void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */
375 void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */
376 void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */
377 void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */
378 void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */
379 void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */
380 void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */
381 void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */
382 void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */
383 void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */
384 void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */
385 void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */
386 void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */
387 void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */
388 void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */
389 void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */
390 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
391 } TIM_HandleTypeDef;
392
393 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
394 /**
395 * @brief HAL TIM Callback ID enumeration definition
396 */
397 typedef enum
398 {
399 HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
400 ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
401 ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
402 ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
403 ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
404 ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
405 ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
406 ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
407 ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
408 ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
409 ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
410 ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
411 ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
412 ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
413 ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
414 ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
415 ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
416 ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
417
418 ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
419 ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
420 ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
421 ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
422 ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
423 ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
424 ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
425 ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
426 ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
427 ,HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */
428 } HAL_TIM_CallbackIDTypeDef;
429
430 /**
431 * @brief HAL TIM Callback pointer definition
432 */
433 typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */
434
435 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
436
437 /**
438 * @}
439 */
440 /* End of exported types -----------------------------------------------------*/
441
442 /* Exported constants --------------------------------------------------------*/
443 /** @defgroup TIM_Exported_Constants TIM Exported Constants
444 * @{
445 */
446
447 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source
448 * @{
449 */
450 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */
451 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */
452 /**
453 * @}
454 */
455
456 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address
457 * @{
458 */
459 #define TIM_DMABASE_CR1 0x00000000U
460 #define TIM_DMABASE_CR2 0x00000001U
461 #define TIM_DMABASE_SMCR 0x00000002U
462 #define TIM_DMABASE_DIER 0x00000003U
463 #define TIM_DMABASE_SR 0x00000004U
464 #define TIM_DMABASE_EGR 0x00000005U
465 #define TIM_DMABASE_CCMR1 0x00000006U
466 #define TIM_DMABASE_CCMR2 0x00000007U
467 #define TIM_DMABASE_CCER 0x00000008U
468 #define TIM_DMABASE_CNT 0x00000009U
469 #define TIM_DMABASE_PSC 0x0000000AU
470 #define TIM_DMABASE_ARR 0x0000000BU
471 #define TIM_DMABASE_RCR 0x0000000CU
472 #define TIM_DMABASE_CCR1 0x0000000DU
473 #define TIM_DMABASE_CCR2 0x0000000EU
474 #define TIM_DMABASE_CCR3 0x0000000FU
475 #define TIM_DMABASE_CCR4 0x00000010U
476 #define TIM_DMABASE_BDTR 0x00000011U
477 #define TIM_DMABASE_DCR 0x00000012U
478 #define TIM_DMABASE_DMAR 0x00000013U
479 #define TIM_DMABASE_CCMR3 0x00000015U
480 #define TIM_DMABASE_CCR5 0x00000016U
481 #define TIM_DMABASE_CCR6 0x00000017U
482 #if defined(TIM_BREAK_INPUT_SUPPORT)
483 #define TIM_DMABASE_AF1 0x00000018U
484 #define TIM_DMABASE_AF2 0x00000019U
485 #endif /* TIM_BREAK_INPUT_SUPPORT */
486 #define TIM_DMABASE_TISEL 0x0000001AU
487 /**
488 * @}
489 */
490
491 /** @defgroup TIM_Event_Source TIM Event Source
492 * @{
493 */
494 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
495 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
496 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
497 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
498 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
499 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
500 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
501 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
502 #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */
503 /**
504 * @}
505 */
506
507 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
508 * @{
509 */
510 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */
511 #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */
512 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
513 /**
514 * @}
515 */
516
517 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
518 * @{
519 */
520 #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */
521 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */
522 /**
523 * @}
524 */
525
526 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
527 * @{
528 */
529 #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */
530 #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */
531 #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */
532 #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */
533 /**
534 * @}
535 */
536
537 /** @defgroup TIM_Counter_Mode TIM Counter Mode
538 * @{
539 */
540 #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */
541 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */
542 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */
543 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */
544 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */
545 /**
546 * @}
547 */
548
549 /** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap
550 * @{
551 */
552 #define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */
553 #define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */
554 /**
555 * @}
556 */
557
558 /** @defgroup TIM_ClockDivision TIM Clock Division
559 * @{
560 */
561 #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */
562 #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */
563 #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */
564 /**
565 * @}
566 */
567
568 /** @defgroup TIM_Output_Compare_State TIM Output Compare State
569 * @{
570 */
571 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */
572 #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */
573 /**
574 * @}
575 */
576
577 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
578 * @{
579 */
580 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */
581 #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */
582
583 /**
584 * @}
585 */
586
587 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
588 * @{
589 */
590 #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */
591 #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */
592 /**
593 * @}
594 */
595
596 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
597 * @{
598 */
599 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */
600 #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */
601 /**
602 * @}
603 */
604
605 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
606 * @{
607 */
608 #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */
609 #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */
610 /**
611 * @}
612 */
613
614 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
615 * @{
616 */
617 #define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */
618 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */
619 /**
620 * @}
621 */
622
623 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
624 * @{
625 */
626 #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */
627 #define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */
628 /**
629 * @}
630 */
631
632 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
633 * @{
634 */
635 #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
636 #define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
637 /**
638 * @}
639 */
640
641 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
642 * @{
643 */
644 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */
645 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */
646 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/
647 /**
648 * @}
649 */
650
651 /** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
652 * @{
653 */
654 #define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */
655 #define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */
656 /**
657 * @}
658 */
659
660 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
661 * @{
662 */
663 #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be
664 connected to IC1, IC2, IC3 or IC4, respectively */
665 #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be
666 connected to IC2, IC1, IC4 or IC3, respectively */
667 #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
668 /**
669 * @}
670 */
671
672 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
673 * @{
674 */
675 #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */
676 #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
677 #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
678 #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */
679 /**
680 * @}
681 */
682
683 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
684 * @{
685 */
686 #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
687 #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
688 /**
689 * @}
690 */
691
692 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
693 * @{
694 */
695 #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */
696 #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
697 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
698 /**
699 * @}
700 */
701
702 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition
703 * @{
704 */
705 #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */
706 #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */
707 #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */
708 #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */
709 #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */
710 #define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */
711 #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */
712 #define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */
713 /**
714 * @}
715 */
716
717 /** @defgroup TIM_Commutation_Source TIM Commutation Source
718 * @{
719 */
720 #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
721 #define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
722 /**
723 * @}
724 */
725
726 /** @defgroup TIM_DMA_sources TIM DMA Sources
727 * @{
728 */
729 #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */
730 #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */
731 #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */
732 #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */
733 #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */
734 #define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */
735 #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */
736 /**
737 * @}
738 */
739
740 /** @defgroup TIM_Flag_definition TIM Flag Definition
741 * @{
742 */
743 #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */
744 #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */
745 #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */
746 #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */
747 #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */
748 #define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */
749 #define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */
750 #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */
751 #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */
752 #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */
753 #define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */
754 #define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */
755 #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */
756 #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */
757 #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */
758 #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */
759 /**
760 * @}
761 */
762
763 /** @defgroup TIM_Channel TIM Channel
764 * @{
765 */
766 #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */
767 #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */
768 #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */
769 #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */
770 #define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */
771 #define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */
772 #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */
773 /**
774 * @}
775 */
776
777 /** @defgroup TIM_Clock_Source TIM Clock Source
778 * @{
779 */
780 #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
781 #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */
782 #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */
783 #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */
784 #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */
785 #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */
786 #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
787 #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
788 #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
789 #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
790 #define TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4 /*!< External clock source mode 1 (ITR4) */
791 #define TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5 /*!< External clock source mode 1 (ITR5) */
792 #define TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6 /*!< External clock source mode 1 (ITR6) */
793 #define TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7 /*!< External clock source mode 1 (ITR7) */
794 #define TIM_CLOCKSOURCE_ITR8 TIM_TS_ITR8 /*!< External clock source mode 1 (ITR8) */
795 /**
796 * @}
797 */
798
799 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
800 * @{
801 */
802 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
803 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
804 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
805 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
806 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
807 /**
808 * @}
809 */
810
811 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
812 * @{
813 */
814 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
815 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
816 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
817 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
818 /**
819 * @}
820 */
821
822 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
823 * @{
824 */
825 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
826 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
827 /**
828 * @}
829 */
830
831 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
832 * @{
833 */
834 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
835 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
836 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
837 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
838 /**
839 * @}
840 */
841
842 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
843 * @{
844 */
845 #define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
846 #define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
847 /**
848 * @}
849 */
850
851 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
852 * @{
853 */
854 #define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
855 #define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
856 /**
857 * @}
858 */
859 /** @defgroup TIM_Lock_level TIM Lock level
860 * @{
861 */
862 #define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */
863 #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
864 #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
865 #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
866 /**
867 * @}
868 */
869
870 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
871 * @{
872 */
873 #define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */
874 #define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */
875 /**
876 * @}
877 */
878
879 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity
880 * @{
881 */
882 #define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
883 #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
884 /**
885 * @}
886 */
887
888 /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
889 * @{
890 */
891 #define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */
892 #define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */
893 /**
894 * @}
895 */
896
897 /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
898 * @{
899 */
900 #define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
901 #define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
902 /**
903 * @}
904 */
905
906 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
907 * @{
908 */
909 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
910 #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event
911 (if none of the break inputs BRK and BRK2 is active) */
912 /**
913 * @}
914 */
915
916 /** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
917 * @{
918 */
919 #define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
920 #define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
921 #define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
922 #define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
923 /**
924 * @}
925 */
926
927 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
928 * @{
929 */
930 #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */
931 #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */
932 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */
933 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
934 #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */
935 #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */
936 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */
937 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */
938 /**
939 * @}
940 */
941
942 /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
943 * @{
944 */
945 #define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */
946 #define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */
947 #define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */
948 #define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */
949 #define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */
950 #define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */
951 #define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */
952 #define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */
953 #define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */
954 #define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */
955 #define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */
956 #define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */
957 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */
958 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */
959 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */
960 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */
961 /**
962 * @}
963 */
964
965 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
966 * @{
967 */
968 #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */
969 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */
970 /**
971 * @}
972 */
973
974 /** @defgroup TIM_Slave_Mode TIM Slave mode
975 * @{
976 */
977 #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */
978 #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */
979 #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */
980 #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */
981 #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */
982 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */
983 /**
984 * @}
985 */
986
987 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
988 * @{
989 */
990 #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */
991 #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */
992 #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */
993 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */
994 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */
995 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */
996 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */
997 #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */
998 #define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */
999 #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */
1000 #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */
1001 #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */
1002 #define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */
1003 #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */
1004 /**
1005 * @}
1006 */
1007
1008 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
1009 * @{
1010 */
1011 #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */
1012 #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */
1013 #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */
1014 #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */
1015 #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */
1016 #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */
1017 #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */
1018 #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */
1019 #define TIM_TS_ITR4 (TIM_SMCR_TS_3) /*!< Internal Trigger 4 (ITR4) */
1020 #define TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) */
1021 #define TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) */
1022 #define TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) */
1023 #define TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) */
1024 #define TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 9 (ITR9) */
1025 #define TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 10 (ITR10) */
1026 #define TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) */
1027 #define TIM_TS_ITR12 (TIM_SMCR_TS_4) /*!< Internal Trigger 12 (ITR12) */
1028 #define TIM_TS_ITR13 (TIM_SMCR_TS_0 | TIM_SMCR_TS_4) /*!< Internal Trigger 13 (ITR13) */
1029 #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */
1030 /**
1031 * @}
1032 */
1033
1034 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
1035 * @{
1036 */
1037 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
1038 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
1039 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
1040 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
1041 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
1042 /**
1043 * @}
1044 */
1045
1046 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
1047 * @{
1048 */
1049 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
1050 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
1051 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
1052 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
1053 /**
1054 * @}
1055 */
1056
1057 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
1058 * @{
1059 */
1060 #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */
1061 #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
1062 /**
1063 * @}
1064 */
1065
1066 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
1067 * @{
1068 */
1069 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */
1070 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1071 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1072 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1073 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1074 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1075 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1076 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1077 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1078 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1079 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1080 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1081 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1082 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1083 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1084 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1085 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1086 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1087 /**
1088 * @}
1089 */
1090
1091 /** @defgroup DMA_Handle_index TIM DMA Handle Index
1092 * @{
1093 */
1094 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */
1095 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
1096 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
1097 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
1098 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
1099 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */
1100 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */
1101 /**
1102 * @}
1103 */
1104
1105 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State
1106 * @{
1107 */
1108 #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */
1109 #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */
1110 #define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */
1111 #define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */
1112 /**
1113 * @}
1114 */
1115
1116 /** @defgroup TIM_Break_System TIM Break System
1117 * @{
1118 */
1119 #define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */
1120 #define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */
1121 #define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */
1122 #define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */
1123 /**
1124 * @}
1125 */
1126
1127 /**
1128 * @}
1129 */
1130 /* End of exported constants -------------------------------------------------*/
1131
1132 /* Exported macros -----------------------------------------------------------*/
1133 /** @defgroup TIM_Exported_Macros TIM Exported Macros
1134 * @{
1135 */
1136
1137 /** @brief Reset TIM handle state.
1138 * @param __HANDLE__ TIM handle.
1139 * @retval None
1140 */
1141 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1142 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
1143 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
1144 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
1145 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
1146 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
1147 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
1148 (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \
1149 (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \
1150 (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
1151 (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
1152 (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
1153 (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
1154 (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
1155 (__HANDLE__)->Base_MspInitCallback = NULL; \
1156 (__HANDLE__)->Base_MspDeInitCallback = NULL; \
1157 (__HANDLE__)->IC_MspInitCallback = NULL; \
1158 (__HANDLE__)->IC_MspDeInitCallback = NULL; \
1159 (__HANDLE__)->OC_MspInitCallback = NULL; \
1160 (__HANDLE__)->OC_MspDeInitCallback = NULL; \
1161 (__HANDLE__)->PWM_MspInitCallback = NULL; \
1162 (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
1163 (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
1164 (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
1165 (__HANDLE__)->Encoder_MspInitCallback = NULL; \
1166 (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
1167 (__HANDLE__)->HallSensor_MspInitCallback = NULL; \
1168 (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
1169 } while(0)
1170 #else
1171 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
1172 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
1173 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
1174 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
1175 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
1176 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
1177 (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \
1178 (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \
1179 (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
1180 (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
1181 (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
1182 (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
1183 (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
1184 } while(0)
1185 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1186
1187 /**
1188 * @brief Enable the TIM peripheral.
1189 * @param __HANDLE__ TIM handle
1190 * @retval None
1191 */
1192 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
1193
1194 /**
1195 * @brief Enable the TIM main Output.
1196 * @param __HANDLE__ TIM handle
1197 * @retval None
1198 */
1199 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
1200
1201 /**
1202 * @brief Disable the TIM peripheral.
1203 * @param __HANDLE__ TIM handle
1204 * @retval None
1205 */
1206 #define __HAL_TIM_DISABLE(__HANDLE__) \
1207 do { \
1208 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
1209 { \
1210 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
1211 { \
1212 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
1213 } \
1214 } \
1215 } while(0)
1216
1217 /**
1218 * @brief Disable the TIM main Output.
1219 * @param __HANDLE__ TIM handle
1220 * @retval None
1221 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
1222 */
1223 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
1224 do { \
1225 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
1226 { \
1227 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
1228 { \
1229 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
1230 } \
1231 } \
1232 } while(0)
1233
1234 /**
1235 * @brief Disable the TIM main Output.
1236 * @param __HANDLE__ TIM handle
1237 * @retval None
1238 * @note The Main Output Enable of a timer instance is disabled unconditionally
1239 */
1240 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
1241
1242 /** @brief Enable the specified TIM interrupt.
1243 * @param __HANDLE__ specifies the TIM Handle.
1244 * @param __INTERRUPT__ specifies the TIM interrupt source to enable.
1245 * This parameter can be one of the following values:
1246 * @arg TIM_IT_UPDATE: Update interrupt
1247 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
1248 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
1249 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
1250 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
1251 * @arg TIM_IT_COM: Commutation interrupt
1252 * @arg TIM_IT_TRIGGER: Trigger interrupt
1253 * @arg TIM_IT_BREAK: Break interrupt
1254 * @retval None
1255 */
1256 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
1257
1258 /** @brief Disable the specified TIM interrupt.
1259 * @param __HANDLE__ specifies the TIM Handle.
1260 * @param __INTERRUPT__ specifies the TIM interrupt source to disable.
1261 * This parameter can be one of the following values:
1262 * @arg TIM_IT_UPDATE: Update interrupt
1263 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
1264 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
1265 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
1266 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
1267 * @arg TIM_IT_COM: Commutation interrupt
1268 * @arg TIM_IT_TRIGGER: Trigger interrupt
1269 * @arg TIM_IT_BREAK: Break interrupt
1270 * @retval None
1271 */
1272 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
1273
1274 /** @brief Enable the specified DMA request.
1275 * @param __HANDLE__ specifies the TIM Handle.
1276 * @param __DMA__ specifies the TIM DMA request to enable.
1277 * This parameter can be one of the following values:
1278 * @arg TIM_DMA_UPDATE: Update DMA request
1279 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
1280 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
1281 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
1282 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
1283 * @arg TIM_DMA_COM: Commutation DMA request
1284 * @arg TIM_DMA_TRIGGER: Trigger DMA request
1285 * @retval None
1286 */
1287 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
1288
1289 /** @brief Disable the specified DMA request.
1290 * @param __HANDLE__ specifies the TIM Handle.
1291 * @param __DMA__ specifies the TIM DMA request to disable.
1292 * This parameter can be one of the following values:
1293 * @arg TIM_DMA_UPDATE: Update DMA request
1294 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
1295 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
1296 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
1297 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
1298 * @arg TIM_DMA_COM: Commutation DMA request
1299 * @arg TIM_DMA_TRIGGER: Trigger DMA request
1300 * @retval None
1301 */
1302 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
1303
1304 /** @brief Check whether the specified TIM interrupt flag is set or not.
1305 * @param __HANDLE__ specifies the TIM Handle.
1306 * @param __FLAG__ specifies the TIM interrupt flag to check.
1307 * This parameter can be one of the following values:
1308 * @arg TIM_FLAG_UPDATE: Update interrupt flag
1309 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
1310 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
1311 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
1312 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
1313 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
1314 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
1315 * @arg TIM_FLAG_COM: Commutation interrupt flag
1316 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
1317 * @arg TIM_FLAG_BREAK: Break interrupt flag
1318 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
1319 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
1320 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
1321 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
1322 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
1323 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
1324 * @retval The new state of __FLAG__ (TRUE or FALSE).
1325 */
1326 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
1327
1328 /** @brief Clear the specified TIM interrupt flag.
1329 * @param __HANDLE__ specifies the TIM Handle.
1330 * @param __FLAG__ specifies the TIM interrupt flag to clear.
1331 * This parameter can be one of the following values:
1332 * @arg TIM_FLAG_UPDATE: Update interrupt flag
1333 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
1334 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
1335 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
1336 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
1337 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
1338 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
1339 * @arg TIM_FLAG_COM: Commutation interrupt flag
1340 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
1341 * @arg TIM_FLAG_BREAK: Break interrupt flag
1342 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
1343 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
1344 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
1345 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
1346 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
1347 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
1348 * @retval The new state of __FLAG__ (TRUE or FALSE).
1349 */
1350 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
1351
1352 /**
1353 * @brief Check whether the specified TIM interrupt source is enabled or not.
1354 * @param __HANDLE__ TIM handle
1355 * @param __INTERRUPT__ specifies the TIM interrupt source to check.
1356 * This parameter can be one of the following values:
1357 * @arg TIM_IT_UPDATE: Update interrupt
1358 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
1359 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
1360 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
1361 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
1362 * @arg TIM_IT_COM: Commutation interrupt
1363 * @arg TIM_IT_TRIGGER: Trigger interrupt
1364 * @arg TIM_IT_BREAK: Break interrupt
1365 * @retval The state of TIM_IT (SET or RESET).
1366 */
1367 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
1368 == (__INTERRUPT__)) ? SET : RESET)
1369
1370 /** @brief Clear the TIM interrupt pending bits.
1371 * @param __HANDLE__ TIM handle
1372 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
1373 * This parameter can be one of the following values:
1374 * @arg TIM_IT_UPDATE: Update interrupt
1375 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
1376 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
1377 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
1378 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
1379 * @arg TIM_IT_COM: Commutation interrupt
1380 * @arg TIM_IT_TRIGGER: Trigger interrupt
1381 * @arg TIM_IT_BREAK: Break interrupt
1382 * @retval None
1383 */
1384 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
1385
1386 /**
1387 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
1388 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
1389 * @param __HANDLE__ TIM handle.
1390 * @retval None
1391 mode.
1392 */
1393 #define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
1394
1395 /**
1396 * @brief Disable update interrupt flag (UIF) remapping.
1397 * @param __HANDLE__ TIM handle.
1398 * @retval None
1399 mode.
1400 */
1401 #define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
1402
1403 /**
1404 * @brief Get update interrupt flag (UIF) copy status.
1405 * @param __COUNTER__ Counter value.
1406 * @retval The state of UIFCPY (TRUE or FALSE).
1407 mode.
1408 */
1409 #define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
1410
1411 /**
1412 * @brief Indicates whether or not the TIM Counter is used as downcounter.
1413 * @param __HANDLE__ TIM handle.
1414 * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
1415 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
1416 mode.
1417 */
1418 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
1419
1420 /**
1421 * @brief Set the TIM Prescaler on runtime.
1422 * @param __HANDLE__ TIM handle.
1423 * @param __PRESC__ specifies the Prescaler new value.
1424 * @retval None
1425 */
1426 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
1427
1428 /**
1429 * @brief Set the TIM Counter Register value on runtime.
1430 * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance.
1431 * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.
1432 * @param __HANDLE__ TIM handle.
1433 * @param __COUNTER__ specifies the Counter register new value.
1434 * @retval None
1435 */
1436 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
1437
1438 /**
1439 * @brief Get the TIM Counter Register value on runtime.
1440 * @param __HANDLE__ TIM handle.
1441 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
1442 */
1443 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
1444
1445 /**
1446 * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
1447 * @param __HANDLE__ TIM handle.
1448 * @param __AUTORELOAD__ specifies the Counter register new value.
1449 * @retval None
1450 */
1451 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
1452 do{ \
1453 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
1454 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
1455 } while(0)
1456
1457 /**
1458 * @brief Get the TIM Autoreload Register value on runtime.
1459 * @param __HANDLE__ TIM handle.
1460 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
1461 */
1462 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
1463
1464 /**
1465 * @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
1466 * @param __HANDLE__ TIM handle.
1467 * @param __CKD__ specifies the clock division value.
1468 * This parameter can be one of the following value:
1469 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
1470 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
1471 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
1472 * @retval None
1473 */
1474 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
1475 do{ \
1476 (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
1477 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
1478 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
1479 } while(0)
1480
1481 /**
1482 * @brief Get the TIM Clock Division value on runtime.
1483 * @param __HANDLE__ TIM handle.
1484 * @retval The clock division can be one of the following values:
1485 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
1486 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
1487 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
1488 */
1489 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
1490
1491 /**
1492 * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
1493 * @param __HANDLE__ TIM handle.
1494 * @param __CHANNEL__ TIM Channels to be configured.
1495 * This parameter can be one of the following values:
1496 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1497 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1498 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1499 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1500 * @param __ICPSC__ specifies the Input Capture4 prescaler new value.
1501 * This parameter can be one of the following values:
1502 * @arg TIM_ICPSC_DIV1: no prescaler
1503 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1504 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1505 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1506 * @retval None
1507 */
1508 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
1509 do{ \
1510 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
1511 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
1512 } while(0)
1513
1514 /**
1515 * @brief Get the TIM Input Capture prescaler on runtime.
1516 * @param __HANDLE__ TIM handle.
1517 * @param __CHANNEL__ TIM Channels to be configured.
1518 * This parameter can be one of the following values:
1519 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
1520 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
1521 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
1522 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
1523 * @retval The input capture prescaler can be one of the following values:
1524 * @arg TIM_ICPSC_DIV1: no prescaler
1525 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1526 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1527 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1528 */
1529 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
1530 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
1531 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
1532 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
1533 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
1534
1535 /**
1536 * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
1537 * @param __HANDLE__ TIM handle.
1538 * @param __CHANNEL__ TIM Channels to be configured.
1539 * This parameter can be one of the following values:
1540 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1541 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1542 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1543 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1544 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1545 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1546 * @param __COMPARE__ specifies the Capture Compare register new value.
1547 * @retval None
1548 */
1549 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
1550 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
1551 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
1552 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
1553 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
1554 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
1555 ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
1556
1557 /**
1558 * @brief Get the TIM Capture Compare Register value on runtime.
1559 * @param __HANDLE__ TIM handle.
1560 * @param __CHANNEL__ TIM Channel associated with the capture compare register
1561 * This parameter can be one of the following values:
1562 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
1563 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
1564 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
1565 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
1566 * @arg TIM_CHANNEL_5: get capture/compare 5 register value
1567 * @arg TIM_CHANNEL_6: get capture/compare 6 register value
1568 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
1569 */
1570 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
1571 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
1572 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
1573 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
1574 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
1575 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
1576 ((__HANDLE__)->Instance->CCR6))
1577
1578 /**
1579 * @brief Set the TIM Output compare preload.
1580 * @param __HANDLE__ TIM handle.
1581 * @param __CHANNEL__ TIM Channels to be configured.
1582 * This parameter can be one of the following values:
1583 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1584 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1585 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1586 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1587 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1588 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1589 * @retval None
1590 */
1591 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
1592 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
1593 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
1594 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
1595 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
1596 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
1597 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
1598
1599 /**
1600 * @brief Reset the TIM Output compare preload.
1601 * @param __HANDLE__ TIM handle.
1602 * @param __CHANNEL__ TIM Channels to be configured.
1603 * This parameter can be one of the following values:
1604 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1605 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1606 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1607 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1608 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1609 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1610 * @retval None
1611 */
1612 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
1613 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
1614 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
1615 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
1616 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
1617 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
1618 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))
1619
1620 /**
1621 * @brief Enable fast mode for a given channel.
1622 * @param __HANDLE__ TIM handle.
1623 * @param __CHANNEL__ TIM Channels to be configured.
1624 * This parameter can be one of the following values:
1625 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1626 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1627 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1628 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1629 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1630 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1631 * @note When fast mode is enabled an active edge on the trigger input acts
1632 * like a compare match on CCx output. Delay to sample the trigger
1633 * input and to activate CCx output is reduced to 3 clock cycles.
1634 * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
1635 * @retval None
1636 */
1637 #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
1638 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
1639 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
1640 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
1641 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\
1642 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\
1643 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))
1644
1645 /**
1646 * @brief Disable fast mode for a given channel.
1647 * @param __HANDLE__ TIM handle.
1648 * @param __CHANNEL__ TIM Channels to be configured.
1649 * This parameter can be one of the following values:
1650 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1651 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1652 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1653 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1654 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1655 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1656 * @note When fast mode is disabled CCx output behaves normally depending
1657 * on counter and CCRx values even when the trigger is ON. The minimum
1658 * delay to activate CCx output when an active edge occurs on the
1659 * trigger input is 5 clock cycles.
1660 * @retval None
1661 */
1662 #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
1663 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
1664 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
1665 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
1666 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
1667 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
1668 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))
1669
1670 /**
1671 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
1672 * @param __HANDLE__ TIM handle.
1673 * @note When the URS bit of the TIMx_CR1 register is set, only counter
1674 * overflow/underflow generates an update interrupt or DMA request (if
1675 * enabled)
1676 * @retval None
1677 */
1678 #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
1679
1680 /**
1681 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
1682 * @param __HANDLE__ TIM handle.
1683 * @note When the URS bit of the TIMx_CR1 register is reset, any of the
1684 * following events generate an update interrupt or DMA request (if
1685 * enabled):
1686 * _ Counter overflow underflow
1687 * _ Setting the UG bit
1688 * _ Update generation through the slave mode controller
1689 * @retval None
1690 */
1691 #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
1692
1693 /**
1694 * @brief Set the TIM Capture x input polarity on runtime.
1695 * @param __HANDLE__ TIM handle.
1696 * @param __CHANNEL__ TIM Channels to be configured.
1697 * This parameter can be one of the following values:
1698 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1699 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1700 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1701 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1702 * @param __POLARITY__ Polarity for TIx source
1703 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
1704 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
1705 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
1706 * @retval None
1707 */
1708 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1709 do{ \
1710 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
1711 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
1712 }while(0)
1713
1714 /**
1715 * @}
1716 */
1717 /* End of exported macros ----------------------------------------------------*/
1718
1719 /* Private constants ---------------------------------------------------------*/
1720 /** @defgroup TIM_Private_Constants TIM Private Constants
1721 * @{
1722 */
1723 /* The counter of a timer instance is disabled only if all the CCx and CCxN
1724 channels have been disabled */
1725 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
1726 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
1727 /**
1728 * @}
1729 */
1730 /* End of private constants --------------------------------------------------*/
1731
1732 /* Private macros ------------------------------------------------------------*/
1733 /** @defgroup TIM_Private_Macros TIM Private Macros
1734 * @{
1735 */
1736 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \
1737 ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
1738
1739 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
1740 ((__BASE__) == TIM_DMABASE_CR2) || \
1741 ((__BASE__) == TIM_DMABASE_SMCR) || \
1742 ((__BASE__) == TIM_DMABASE_DIER) || \
1743 ((__BASE__) == TIM_DMABASE_SR) || \
1744 ((__BASE__) == TIM_DMABASE_EGR) || \
1745 ((__BASE__) == TIM_DMABASE_CCMR1) || \
1746 ((__BASE__) == TIM_DMABASE_CCMR2) || \
1747 ((__BASE__) == TIM_DMABASE_CCER) || \
1748 ((__BASE__) == TIM_DMABASE_CNT) || \
1749 ((__BASE__) == TIM_DMABASE_PSC) || \
1750 ((__BASE__) == TIM_DMABASE_ARR) || \
1751 ((__BASE__) == TIM_DMABASE_RCR) || \
1752 ((__BASE__) == TIM_DMABASE_CCR1) || \
1753 ((__BASE__) == TIM_DMABASE_CCR2) || \
1754 ((__BASE__) == TIM_DMABASE_CCR3) || \
1755 ((__BASE__) == TIM_DMABASE_CCR4) || \
1756 ((__BASE__) == TIM_DMABASE_BDTR) || \
1757 ((__BASE__) == TIM_DMABASE_CCMR3) || \
1758 ((__BASE__) == TIM_DMABASE_CCR5) || \
1759 ((__BASE__) == TIM_DMABASE_CCR6) || \
1760 ((__BASE__) == TIM_DMABASE_AF1) || \
1761 ((__BASE__) == TIM_DMABASE_AF2) || \
1762 ((__BASE__) == TIM_DMABASE_TISEL))
1763
1764
1765 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
1766
1767 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
1768 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
1769 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
1770 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
1771 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
1772
1773 #define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \
1774 ((__MODE__) == TIM_UIFREMAP_ENALE))
1775
1776 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
1777 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
1778 ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
1779
1780 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
1781 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
1782
1783 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
1784 ((__STATE__) == TIM_OCFAST_ENABLE))
1785
1786 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
1787 ((__POLARITY__) == TIM_OCPOLARITY_LOW))
1788
1789 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
1790 ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
1791
1792 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
1793 ((__STATE__) == TIM_OCIDLESTATE_RESET))
1794
1795 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
1796 ((__STATE__) == TIM_OCNIDLESTATE_RESET))
1797
1798 #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
1799 ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
1800
1801 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
1802 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
1803 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
1804
1805 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
1806 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
1807 ((__SELECTION__) == TIM_ICSELECTION_TRC))
1808
1809 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
1810 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
1811 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
1812 ((__PRESCALER__) == TIM_ICPSC_DIV8))
1813
1814 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
1815 ((__MODE__) == TIM_OPMODE_REPETITIVE))
1816
1817 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
1818 ((__MODE__) == TIM_ENCODERMODE_TI2) || \
1819 ((__MODE__) == TIM_ENCODERMODE_TI12))
1820
1821 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
1822
1823 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1824 ((__CHANNEL__) == TIM_CHANNEL_2) || \
1825 ((__CHANNEL__) == TIM_CHANNEL_3) || \
1826 ((__CHANNEL__) == TIM_CHANNEL_4) || \
1827 ((__CHANNEL__) == TIM_CHANNEL_5) || \
1828 ((__CHANNEL__) == TIM_CHANNEL_6) || \
1829 ((__CHANNEL__) == TIM_CHANNEL_ALL))
1830
1831 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1832 ((__CHANNEL__) == TIM_CHANNEL_2))
1833
1834 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1835 ((__CHANNEL__) == TIM_CHANNEL_2) || \
1836 ((__CHANNEL__) == TIM_CHANNEL_3))
1837
1838 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
1839 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
1840 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
1841 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
1842 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
1843 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
1844 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
1845 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
1846 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
1847 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
1848
1849 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
1850 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
1851 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
1852 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
1853 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
1854
1855 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
1856 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
1857 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
1858 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
1859
1860 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1861
1862 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
1863 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
1864
1865 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
1866 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
1867 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
1868 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
1869
1870 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1871
1872 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
1873 ((__STATE__) == TIM_OSSR_DISABLE))
1874
1875 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
1876 ((__STATE__) == TIM_OSSI_DISABLE))
1877
1878 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
1879 ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
1880 ((__LEVEL__) == TIM_LOCKLEVEL_2) || \
1881 ((__LEVEL__) == TIM_LOCKLEVEL_3))
1882
1883 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
1884
1885
1886 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
1887 ((__STATE__) == TIM_BREAK_DISABLE))
1888
1889 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
1890 ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
1891
1892 #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \
1893 ((__STATE__) == TIM_BREAK2_DISABLE))
1894
1895 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
1896 ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
1897
1898 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
1899 ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
1900
1901 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
1902
1903 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
1904 ((__SOURCE__) == TIM_TRGO_ENABLE) || \
1905 ((__SOURCE__) == TIM_TRGO_UPDATE) || \
1906 ((__SOURCE__) == TIM_TRGO_OC1) || \
1907 ((__SOURCE__) == TIM_TRGO_OC1REF) || \
1908 ((__SOURCE__) == TIM_TRGO_OC2REF) || \
1909 ((__SOURCE__) == TIM_TRGO_OC3REF) || \
1910 ((__SOURCE__) == TIM_TRGO_OC4REF))
1911
1912 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \
1913 ((__SOURCE__) == TIM_TRGO2_ENABLE) || \
1914 ((__SOURCE__) == TIM_TRGO2_UPDATE) || \
1915 ((__SOURCE__) == TIM_TRGO2_OC1) || \
1916 ((__SOURCE__) == TIM_TRGO2_OC1REF) || \
1917 ((__SOURCE__) == TIM_TRGO2_OC2REF) || \
1918 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
1919 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
1920 ((__SOURCE__) == TIM_TRGO2_OC4REF) || \
1921 ((__SOURCE__) == TIM_TRGO2_OC5REF) || \
1922 ((__SOURCE__) == TIM_TRGO2_OC6REF) || \
1923 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
1924 ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
1925 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
1926 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
1927 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
1928 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
1929
1930 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
1931 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
1932
1933 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
1934 ((__MODE__) == TIM_SLAVEMODE_RESET) || \
1935 ((__MODE__) == TIM_SLAVEMODE_GATED) || \
1936 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
1937 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
1938 ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
1939
1940 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
1941 ((__MODE__) == TIM_OCMODE_PWM2) || \
1942 ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \
1943 ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \
1944 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
1945 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
1946
1947 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
1948 ((__MODE__) == TIM_OCMODE_ACTIVE) || \
1949 ((__MODE__) == TIM_OCMODE_INACTIVE) || \
1950 ((__MODE__) == TIM_OCMODE_TOGGLE) || \
1951 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
1952 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \
1953 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
1954 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
1955
1956 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
1957 ((__SELECTION__) == TIM_TS_ITR1) || \
1958 ((__SELECTION__) == TIM_TS_ITR2) || \
1959 ((__SELECTION__) == TIM_TS_ITR3) || \
1960 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
1961 ((__SELECTION__) == TIM_TS_TI1FP1) || \
1962 ((__SELECTION__) == TIM_TS_TI2FP2) || \
1963 ((__SELECTION__) == TIM_TS_ETRF) || \
1964 ((__SELECTION__) == TIM_TS_ITR4) || \
1965 ((__SELECTION__) == TIM_TS_ITR5) || \
1966 ((__SELECTION__) == TIM_TS_ITR6) || \
1967 ((__SELECTION__) == TIM_TS_ITR7) || \
1968 ((__SELECTION__) == TIM_TS_ITR8) || \
1969 ((__SELECTION__) == TIM_TS_ITR12) || \
1970 ((__SELECTION__) == TIM_TS_ITR13))
1971
1972 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
1973 ((__SELECTION__) == TIM_TS_ITR1) || \
1974 ((__SELECTION__) == TIM_TS_ITR2) || \
1975 ((__SELECTION__) == TIM_TS_ITR3) || \
1976 ((__SELECTION__) == TIM_TS_ITR4) || \
1977 ((__SELECTION__) == TIM_TS_ITR5) || \
1978 ((__SELECTION__) == TIM_TS_ITR6) || \
1979 ((__SELECTION__) == TIM_TS_ITR7) || \
1980 ((__SELECTION__) == TIM_TS_ITR8) || \
1981 ((__SELECTION__) == TIM_TS_ITR12) || \
1982 ((__SELECTION__) == TIM_TS_ITR13) || \
1983 ((__SELECTION__) == TIM_TS_NONE))
1984
1985 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
1986 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
1987 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
1988 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
1989 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
1990
1991 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
1992 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
1993 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
1994 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
1995
1996 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1997
1998 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
1999 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
2000
2001 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
2002 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
2003 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
2004 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
2005 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
2006 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
2007 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
2008 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
2009 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
2010 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
2011 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
2012 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
2013 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
2014 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
2015 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
2016 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
2017 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
2018 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
2019
2020 #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
2021
2022 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
2023
2024 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
2025
2026 #define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \
2027 ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \
2028 ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \
2029 ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
2030
2031 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
2032 ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
2033
2034 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
2035 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
2036 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
2037 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
2038 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
2039
2040 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
2041 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
2042 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
2043 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
2044 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
2045
2046 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
2047 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
2048 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
2049 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
2050 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
2051
2052 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
2053 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
2054 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
2055 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
2056 ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
2057
2058 #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
2059 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
2060 ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
2061 ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
2062 ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\
2063 ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\
2064 (__HANDLE__)->ChannelState[5])
2065
2066 #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
2067 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
2068 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
2069 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
2070 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\
2071 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\
2072 ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__)))
2073
2074 #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
2075 (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \
2076 (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \
2077 (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \
2078 (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
2079 (__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \
2080 (__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \
2081 } while(0)
2082
2083 #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
2084 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
2085 ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
2086 ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
2087 (__HANDLE__)->ChannelNState[3])
2088
2089 #define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
2090 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
2091 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
2092 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
2093 ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
2094
2095 #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
2096 (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \
2097 (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \
2098 (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \
2099 (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \
2100 } while(0)
2101
2102 /**
2103 * @}
2104 */
2105 /* End of private macros -----------------------------------------------------*/
2106
2107 /* Include TIM HAL Extended module */
2108 #include "stm32h7xx_hal_tim_ex.h"
2109
2110 /* Exported functions --------------------------------------------------------*/
2111 /** @addtogroup TIM_Exported_Functions TIM Exported Functions
2112 * @{
2113 */
2114
2115 /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
2116 * @brief Time Base functions
2117 * @{
2118 */
2119 /* Time Base functions ********************************************************/
2120 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
2121 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
2122 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
2123 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
2124 /* Blocking mode: Polling */
2125 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
2126 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
2127 /* Non-Blocking mode: Interrupt */
2128 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
2129 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
2130 /* Non-Blocking mode: DMA */
2131 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
2132 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
2133 /**
2134 * @}
2135 */
2136
2137 /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
2138 * @brief TIM Output Compare functions
2139 * @{
2140 */
2141 /* Timer Output Compare functions *********************************************/
2142 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
2143 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
2144 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
2145 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
2146 /* Blocking mode: Polling */
2147 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
2148 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
2149 /* Non-Blocking mode: Interrupt */
2150 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2151 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2152 /* Non-Blocking mode: DMA */
2153 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
2154 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
2155 /**
2156 * @}
2157 */
2158
2159 /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
2160 * @brief TIM PWM functions
2161 * @{
2162 */
2163 /* Timer PWM functions ********************************************************/
2164 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
2165 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
2166 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
2167 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
2168 /* Blocking mode: Polling */
2169 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
2170 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
2171 /* Non-Blocking mode: Interrupt */
2172 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2173 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2174 /* Non-Blocking mode: DMA */
2175 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
2176 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
2177 /**
2178 * @}
2179 */
2180
2181 /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
2182 * @brief TIM Input Capture functions
2183 * @{
2184 */
2185 /* Timer Input Capture functions **********************************************/
2186 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
2187 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
2188 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
2189 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
2190 /* Blocking mode: Polling */
2191 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
2192 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
2193 /* Non-Blocking mode: Interrupt */
2194 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2195 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2196 /* Non-Blocking mode: DMA */
2197 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
2198 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
2199 /**
2200 * @}
2201 */
2202
2203 /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
2204 * @brief TIM One Pulse functions
2205 * @{
2206 */
2207 /* Timer One Pulse functions **************************************************/
2208 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
2209 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
2210 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
2211 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
2212 /* Blocking mode: Polling */
2213 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2214 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2215 /* Non-Blocking mode: Interrupt */
2216 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2217 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2218 /**
2219 * @}
2220 */
2221
2222 /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
2223 * @brief TIM Encoder functions
2224 * @{
2225 */
2226 /* Timer Encoder functions ****************************************************/
2227 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
2228 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
2229 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
2230 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
2231 /* Blocking mode: Polling */
2232 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
2233 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
2234 /* Non-Blocking mode: Interrupt */
2235 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2236 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2237 /* Non-Blocking mode: DMA */
2238 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
2239 uint32_t *pData2, uint16_t Length);
2240 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
2241 /**
2242 * @}
2243 */
2244
2245 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
2246 * @brief IRQ handler management
2247 * @{
2248 */
2249 /* Interrupt Handler functions ***********************************************/
2250 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
2251 /**
2252 * @}
2253 */
2254
2255 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
2256 * @brief Peripheral Control functions
2257 * @{
2258 */
2259 /* Control functions *********************************************************/
2260 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
2261 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
2262 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
2263 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
2264 uint32_t OutputChannel, uint32_t InputChannel);
2265 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
2266 uint32_t Channel);
2267 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
2268 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
2269 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
2270 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
2271 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2272 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
2273 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2274 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
2275 uint32_t DataLength);
2276 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
2277 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2278 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
2279 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2280 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
2281 uint32_t DataLength);
2282 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
2283 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
2284 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
2285 /**
2286 * @}
2287 */
2288
2289 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
2290 * @brief TIM Callbacks functions
2291 * @{
2292 */
2293 /* Callback in non blocking modes (Interrupt and DMA) *************************/
2294 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
2295 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
2296 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
2297 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
2298 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
2299 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
2300 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
2301 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
2302 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
2303 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
2304
2305 /* Callbacks Register/UnRegister functions ***********************************/
2306 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2307 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
2308 pTIM_CallbackTypeDef pCallback);
2309 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
2310 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2311
2312 /**
2313 * @}
2314 */
2315
2316 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
2317 * @brief Peripheral State functions
2318 * @{
2319 */
2320 /* Peripheral State functions ************************************************/
2321 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
2322 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
2323 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
2324 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
2325 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
2326 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
2327
2328 /* Peripheral Channel state functions ************************************************/
2329 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
2330 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel);
2331 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
2332 /**
2333 * @}
2334 */
2335
2336 /**
2337 * @}
2338 */
2339 /* End of exported functions -------------------------------------------------*/
2340
2341 /* Private functions----------------------------------------------------------*/
2342 /** @defgroup TIM_Private_Functions TIM Private Functions
2343 * @{
2344 */
2345 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
2346 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
2347 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
2348 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
2349 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
2350
2351 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
2352 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
2353 void TIM_DMAError(DMA_HandleTypeDef *hdma);
2354 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
2355 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
2356 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
2357
2358 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2359 void TIM_ResetCallback(TIM_HandleTypeDef *htim);
2360 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2361
2362 /**
2363 * @}
2364 */
2365 /* End of private functions --------------------------------------------------*/
2366
2367 /**
2368 * @}
2369 */
2370
2371 /**
2372 * @}
2373 */
2374
2375 #ifdef __cplusplus
2376 }
2377 #endif
2378
2379 #endif /* STM32H7xx_HAL_TIM_H */
2380
2381 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/