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Merge pull request #11270 from haslinghuis/rename_attr
[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_ll_adc.h
blobf7e8c9c1de81baa814c3b5c263f09dfb2a165978
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_LL_ADC_H
22 #define STM32H7xx_LL_ADC_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx.h"
30
31 /** @addtogroup STM32H7xx_LL_Driver
32 * @{
33 */
34
35 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
36
37 /** @defgroup ADC_LL ADC
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
46 * @{
47 */
48
49 /* Internal mask for ADC calibration: */
50 /* Internal register offset for ADC calibration factors configuration */
51
52 /* To select into literals LL_ADC_CALIB_OFFSET, LL_ADC_CALIB_LINEARITY, ... */
53 /* the relevant bits for: */
54 /* (concatenation of multiple bits used in different registers) */
55 /* - ADC calibration configuration: configuration before calibration start */
56 /* - ADC calibration factors: register offset */
57 #define ADC_CALIB_FACTOR_OFFSET_REGOFFSET (0x00000000UL) /* Register CALFACT defined as reference register */
58 #define ADC_CALIB_FACTOR_LINEARITY_REGOFFSET (0x00000001UL) /* Register CALFACT2 offset vs register CALFACT */
59 #define ADC_CALIB_FACTOR_REGOFFSET_MASK (ADC_CALIB_FACTOR_OFFSET_REGOFFSET | ADC_CALIB_FACTOR_LINEARITY_REGOFFSET)
60 #define ADC_CALIB_MODE_MASK (ADC_CR_ADCALLIN)
61 #define ADC_CALIB_MODE_BINARY_MASK (ADC_CALIB_FACTOR_REGOFFSET_MASK) /* Mask to get binary value of calibration mode: 0 for offset, 1 for linearity */
62
63
64 /* Internal mask for ADC group regular sequencer: */
65 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
66 /* - sequencer register offset */
67 /* - sequencer rank bits position into the selected register */
68
69 /* Internal register offset for ADC group regular sequencer configuration */
70 /* (offset placed into a spare area of literal definition) */
71 #define ADC_SQR1_REGOFFSET (0x00000000UL)
72 #define ADC_SQR2_REGOFFSET (0x00000100UL)
73 #define ADC_SQR3_REGOFFSET (0x00000200UL)
74 #define ADC_SQR4_REGOFFSET (0x00000300UL)
75
76 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
77 #define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
78 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
79
80 /* Definition of ADC group regular sequencer bits information to be inserted */
81 /* into ADC group regular sequencer ranks literals definition. */
82 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR1_SQ1" position in register */
83 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR1_SQ2" position in register */
84 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR1_SQ3" position in register */
85 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR1_SQ4" position in register */
86 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR2_SQ5" position in register */
87 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR2_SQ6" position in register */
88 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR2_SQ7" position in register */
89 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR2_SQ8" position in register */
90 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR2_SQ9" position in register */
91 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR3_SQ10" position in register */
92 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR3_SQ11" position in register */
93 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR3_SQ12" position in register */
94 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR3_SQ13" position in register */
95 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR3_SQ14" position in register */
96 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR4_SQ15" position in register */
97 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR4_SQ16" position in register */
98
99
100
101 /* Internal mask for ADC group injected sequencer: */
102 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
103 /* - data register offset */
104 /* - sequencer rank bits position into the selected register */
105
106 /* Internal register offset for ADC group injected data register */
107 /* (offset placed into a spare area of literal definition) */
108 #define ADC_JDR1_REGOFFSET (0x00000000UL)
109 #define ADC_JDR2_REGOFFSET (0x00000100UL)
110 #define ADC_JDR3_REGOFFSET (0x00000200UL)
111 #define ADC_JDR4_REGOFFSET (0x00000300UL)
112
113 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
114 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
115 #define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */
116
117 /* Definition of ADC group injected sequencer bits information to be inserted */
118 /* into ADC group injected sequencer ranks literals definition. */
119 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos)
120 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos)
121 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos)
122 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos)
123
124
125
126 /* Internal mask for ADC group regular trigger: */
127 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
128 /* - regular trigger source */
129 /* - regular trigger edge */
130 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
131
132 /* Mask containing trigger source masks for each of possible */
133 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
134 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
135 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
136 ((ADC_CFGR_EXTSEL) << (4U * 1UL)) | \
137 ((ADC_CFGR_EXTSEL) << (4U * 2UL)) | \
138 ((ADC_CFGR_EXTSEL) << (4U * 3UL)) )
139
140 /* Mask containing trigger edge masks for each of possible */
141 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
142 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
143 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
144 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
145 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
146 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
147
148 /* Definition of ADC group regular trigger bits information. */
149 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CFGR_EXTSEL" position in register */
150 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CFGR_EXTEN" position in register */
151
152
153
154 /* Internal mask for ADC group injected trigger: */
155 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
156 /* - injected trigger source */
157 /* - injected trigger edge */
158 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
159
160 /* Mask containing trigger source masks for each of possible */
161 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
162 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
163 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \
164 ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \
165 ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \
166 ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) )
167
168 /* Mask containing trigger edge masks for each of possible */
169 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
170 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
171 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
172 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
173 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
174 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
175
176 /* Definition of ADC group injected trigger bits information. */
177 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTSEL" position in register */
178 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTEN" position in register */
179
180
181
182
183
184
185 /* Internal mask for ADC channel: */
186 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
187 /* - channel identifier defined by number */
188 /* - channel identifier defined by bitfield */
189 /* - channel differentiation between external channels (connected to */
190 /* GPIO pins) and internal channels (connected to internal paths) */
191 /* - channel sampling time defined by SMPRx register offset */
192 /* and SMPx bits positions into SMPRx register */
193 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
194 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
195 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */
196 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
197 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
198 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
199
200 /* Channel differentiation between external and internal channels */
201 #define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
202 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)
203
204 /* Internal register offset for ADC channel sampling time configuration */
205 /* (offset placed into a spare area of literal definition) */
206 #define ADC_SMPR1_REGOFFSET (0x00000000UL)
207 #define ADC_SMPR2_REGOFFSET (0x02000000UL)
208 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
209 #define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
210
211 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)
212 #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */
213
214 /* Definition of channels ID number information to be inserted into */
215 /* channels literals definition. */
216 #define ADC_CHANNEL_0_NUMBER (0x00000000UL)
217 #define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)
218 #define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )
219 #define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
220 #define ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )
221 #define ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
222 #define ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
223 #define ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
224 #define ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )
225 #define ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
226 #define ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 )
227 #define ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
228 #define ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 )
229 #define ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
230 #define ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
231 #define ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
232 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )
233 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
234 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 )
235 #define ADC_CHANNEL_19_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
236
237 /* Definition of channels ID bitfield information to be inserted into */
238 /* channels literals definition. */
239 #define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
240 #define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
241 #define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
242 #define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
243 #define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
244 #define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
245 #define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
246 #define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
247 #define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
248 #define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
249 #define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
250 #define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
251 #define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
252 #define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
253 #define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
254 #define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
255 #define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
256 #define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
257 #define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
258 #define ADC_CHANNEL_19_BITFIELD (ADC_AWD2CR_AWD2CH_19)
259
260 /* Definition of channels sampling time information to be inserted into */
261 /* channels literals definition. */
262 #define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */
263 #define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */
264 #define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */
265 #define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */
266 #define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */
267 #define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */
268 #define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */
269 #define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */
270 #define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */
271 #define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */
272 #define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */
273 #define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */
274 #define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */
275 #define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */
276 #define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */
277 #define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */
278 #define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */
279 #define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */
280 #define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */
281 #define ADC_CHANNEL_19_SMP (ADC_SMPR2_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP19" position in register */
282
283
284 /* Internal mask for ADC mode single or differential ended: */
285 /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
286 /* the relevant bits for: */
287 /* (concatenation of multiple bits used in different registers) */
288 /* - ADC calibration: calibration start, calibration factor get or set */
289 /* - ADC channels: set each ADC channel ending mode */
290 #define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
291 #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
292 #define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
293 #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
294 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: mask of bit */
295 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode: position of bit */
296 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */
297
298 /* Internal mask for ADC analog watchdog: */
299 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
300 /* (concatenation of multiple bits used in different analog watchdogs, */
301 /* (feature of several watchdogs not available on all STM32 families)). */
302 /* - analog watchdog 1: monitored channel defined by number, */
303 /* selection of ADC group (ADC groups regular and-or injected). */
304 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
305 /* selection on groups. */
306
307 /* Internal register offset for ADC analog watchdog channel configuration */
308 #define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
309 #define ADC_AWD_CR2_REGOFFSET (0x00100000UL)
310 #define ADC_AWD_CR3_REGOFFSET (0x00200000UL)
311
312 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
313 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
314 #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
315 #define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
316
317 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
318
319 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
320 #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
321 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
322
323 #define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
324
325 /* Internal register offset for ADC analog watchdog threshold configuration */
326 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
327 #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
328 #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
329 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
330 #define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_TRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
331 #if defined(ADC_VER_V5_V90)
332 #define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */
333 #define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */
334 #define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */
335 #endif /* ADC_VER_V5_V90 */
336
337 /* Register offset gap between AWD1 and AWD2-AWD3 thresholds registers */
338 /* (Set separately as ADC_AWD_TRX_REGOFFSET to spare 32 bits space */
339 #define ADC_AWD_TR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
340 #define ADC_AWD_TR12_REGOFFSETGAP_VAL (0x00000022UL)
341
342 /* Legacy literals */
343 #define LL_ADC_AWD1_TR LL_ADC_AWD1
344 #define LL_ADC_AWD2_TR LL_ADC_AWD2
345 #define LL_ADC_AWD3_TR LL_ADC_AWD3
346
347 /* Internal mask for ADC offset: */
348 /* Internal register offset for ADC offset number configuration */
349 #define ADC_OFR1_REGOFFSET (0x00000000UL)
350 #define ADC_OFR2_REGOFFSET (0x00000001UL)
351 #define ADC_OFR3_REGOFFSET (0x00000002UL)
352 #define ADC_OFR4_REGOFFSET (0x00000003UL)
353 #define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
354
355
356 /* ADC registers bits positions */
357 #define ADC_CFGR_RES_BITOFFSET_POS (ADC_CFGR_RES_Pos)
358 #define ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR_AWD1SGL_Pos)
359 #define ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR_AWD1EN_Pos)
360 #define ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR_JAWD1EN_Pos)
361 #if defined(ADC_VER_V5_V90)
362 #define ADC_CFGR_RES_BITOFFSET_POS_ADC3 (ADC3_CFGR_RES_Pos)
363 #endif /* ADC_VER_V5_V90 */
364
365
366 /* ADC registers bits groups */
367 #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
368
369
370 /* ADC internal channels related definitions */
371 /* Internal voltage reference VrefInt */
372 #if defined(ADC_VER_V5_3)
373 #define VREFINT_CAL_ADDR ((uint16_t*) (0x8fff810UL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
374 /* Adress related to STM32H7A3 */
375 #else /* ADC_VER_V5_90 || ADC_VER_V5_X */
376 #define VREFINT_CAL_ADDR ((uint16_t*) (0x1FF1E860UL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
377 #endif /* ADC_VER_V5_3 */
378 #define VREFINT_CAL_VREF (3300UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
379 /* Temperature sensor */
380 #if defined(ADC_VER_V5_3)
381 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x8fff814UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32H7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
382 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x8fff818UL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32H7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
383 /* Adresses related to STM32H7A3 */
384 #else /* ADC_VER_V5_90 || ADC_VER_V5_X */
385 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FF1E820UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32H7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
386 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FF1E840UL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32H7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
387 #endif /* ADC_VER_V5_3 */
388
389 #define TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
390 #define TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
391 #define TEMPSENSOR_CAL_VREFANALOG (3300UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
392
393 /* Registers addresses with ADC linearity calibration content (programmed during device production, specific to each device) */
394 #define ADC_LINEAR_CALIB_REG_1_ADDR ((uint32_t*) (0x1FF1EC00UL))
395 #define ADC_LINEAR_CALIB_REG_2_ADDR ((uint32_t*) (0x1FF1EC04UL))
396 #define ADC_LINEAR_CALIB_REG_3_ADDR ((uint32_t*) (0x1FF1EC08UL))
397 #define ADC_LINEAR_CALIB_REG_4_ADDR ((uint32_t*) (0x1FF1EC0CUL))
398 #define ADC_LINEAR_CALIB_REG_5_ADDR ((uint32_t*) (0x1FF1EC10UL))
399 #define ADC_LINEAR_CALIB_REG_6_ADDR ((uint32_t*) (0x1FF1EC14UL))
400 #define ADC_LINEAR_CALIB_REG_COUNT (6UL)
401 /**
402 * @}
403 */
404
405
406 /* Private macros ------------------------------------------------------------*/
407 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
408 * @{
409 */
410
411 /**
412 * @brief Driver macro reserved for internal use: set a pointer to
413 * a register from a register basis from which an offset
414 * is applied.
415 * @param __REG__ Register basis from which the offset is applied.
416 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
417 * @retval Pointer to register address
418 */
419 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
420 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
421
422 /**
423 * @}
424 */
425
426
427 /* Exported types ------------------------------------------------------------*/
428 #if defined(USE_FULL_LL_DRIVER)
429 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
430 * @{
431 */
432
433 /**
434 * @brief Structure definition of some features of ADC common parameters
435 * and multimode
436 * (all ADC instances belonging to the same ADC common instance).
437 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
438 * is conditioned to ADC instances state (all ADC instances
439 * sharing the same ADC common instance):
440 * All ADC instances sharing the same ADC common instance must be
441 * disabled.
442 */
443 typedef struct
444 {
445 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
446 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
447 @note On this STM32 serie, if ADC group injected is used, some
448 clock ratio constraints between ADC clock and AHB clock
449 must be respected. Refer to reference manual.
450
451 This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
452
453 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
454 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
455
456 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
457
458 uint32_t MultiDMATransfer; /*!< Set ADC dual ADC mode DMA transfer data format: Each DMA, 32 down to 10-bits or 8-bits resolution.
459 This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
460
461 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
462
463 uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
464 This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
465
466 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
467
468 } LL_ADC_CommonInitTypeDef;
469
470 /**
471 * @brief Structure definition of some features of ADC instance.
472 * @note These parameters have an impact on ADC scope: ADC instance.
473 * Affects both group regular and group injected (availability
474 * of ADC group injected depends on STM32 families).
475 * Refer to corresponding unitary functions into
476 * @ref ADC_LL_EF_Configuration_ADC_Instance .
477 * @note The setting of these parameters by function @ref LL_ADC_Init()
478 * is conditioned to ADC state:
479 * ADC instance must be disabled.
480 * This condition is applied to all ADC features, for efficiency
481 * and compatibility over all STM32 families. However, the different
482 * features can be set under different ADC state conditions
483 * (setting possible with ADC enabled without conversion on going,
484 * ADC enabled with conversion on going, ...)
485 * Each feature can be updated afterwards with a unitary function
486 * and potentially with ADC in a different state than disabled,
487 * refer to description of each function for setting
488 * conditioned to ADC state.
489 */
490 typedef struct
491 {
492 uint32_t Resolution; /*!< Set ADC resolution.
493 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
494
495 This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
496
497 uint32_t LeftBitShift; /*!< Configures the left shifting applied to the final result with or without oversampling.
498 This parameter can be a value of @ref ADC_LL_EC_LEFT_BIT_SHIFT. */
499
500 uint32_t LowPowerMode; /*!< Set ADC low power mode.
501 This parameter can be a value of @ref ADC_LL_EC_LP_MODE
502
503 This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
504
505 } LL_ADC_InitTypeDef;
506
507 /**
508 * @brief Structure definition of some features of ADC group regular.
509 * @note These parameters have an impact on ADC scope: ADC group regular.
510 * Refer to corresponding unitary functions into
511 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
512 * (functions with prefix "REG").
513 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
514 * is conditioned to ADC state:
515 * ADC instance must be disabled.
516 * This condition is applied to all ADC features, for efficiency
517 * and compatibility over all STM32 families. However, the different
518 * features can be set under different ADC state conditions
519 * (setting possible with ADC enabled without conversion on going,
520 * ADC enabled with conversion on going, ...)
521 * Each feature can be updated afterwards with a unitary function
522 * and potentially with ADC in a different state than disabled,
523 * refer to description of each function for setting
524 * conditioned to ADC state.
525 */
526 typedef struct
527 {
528 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
529 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
530 @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
531 (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
532 In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
533
534 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
535
536 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
537 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
538
539 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
540
541 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
542 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
543 @note This parameter has an effect only if group regular sequencer is enabled
544 (scan length of 2 ranks or more).
545
546 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
547
548 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
549 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
550 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
551
552 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
553
554 uint32_t DataTransferMode; /*!< Set ADC group regular conversion data transfer mode: no transfer, transfer by DMA (Limited/Unlimited) or DFSDM.
555 This parameter can be a value of @ref ADC_LL_EC_REG_DATA_TRANSFER_MODE
556
557 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDataTransferMode(). */
558
559 uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
560 data preserved or overwritten.
561 This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
562
563 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
564
565 } LL_ADC_REG_InitTypeDef;
566
567 /**
568 * @brief Structure definition of some features of ADC group injected.
569 * @note These parameters have an impact on ADC scope: ADC group injected.
570 * Refer to corresponding unitary functions into
571 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
572 * (functions with prefix "INJ").
573 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
574 * is conditioned to ADC state:
575 * ADC instance must be disabled.
576 * This condition is applied to all ADC features, for efficiency
577 * and compatibility over all STM32 families. However, the different
578 * features can be set under different ADC state conditions
579 * (setting possible with ADC enabled without conversion on going,
580 * ADC enabled with conversion on going, ...)
581 * Each feature can be updated afterwards with a unitary function
582 * and potentially with ADC in a different state than disabled,
583 * refer to description of each function for setting
584 * conditioned to ADC state.
585 */
586 typedef struct
587 {
588 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
589 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
590 @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
591 (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
592 In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().
593
594 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
595
596 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
597 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
598
599 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
600
601 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
602 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
603 @note This parameter has an effect only if group injected sequencer is enabled
604 (scan length of 2 ranks or more).
605
606 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
607
608 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
609 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
610 Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
611
612 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
613
614 } LL_ADC_INJ_InitTypeDef;
615
616 /**
617 * @}
618 */
619 #endif /* USE_FULL_LL_DRIVER */
620
621 /* Exported constants --------------------------------------------------------*/
622 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
623 * @{
624 */
625
626 /** @defgroup ADC_LL_EC_FLAG ADC flags
627 * @brief Flags defines which can be used with LL_ADC_ReadReg function
628 * @{
629 */
630 #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
631 #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */
632 #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */
633 #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
634 #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
635 #define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary conversion */
636 #define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence conversions */
637 #define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue overflow */
638 #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
639 #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
640 #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
641 #define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */
642 #define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */
643 #define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of unitary conversion */
644 #define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of unitary conversion */
645 #define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of sequence conversions */
646 #define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of sequence conversions */
647 #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular overrun */
648 #define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular overrun */
649 #define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of sampling phase */
650 #define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of sampling phase */
651 #define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of unitary conversion */
652 #define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of unitary conversion */
653 #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of sequence conversions */
654 #define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of sequence conversions */
655 #define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected contexts queue overflow */
656 #define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected contexts queue overflow */
657 #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
658 #define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave */
659 #define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2 of the ADC master */
660 #define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */
661 #define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */
662 #define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */
663 /**
664 * @}
665 */
666
667 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
668 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
669 * @{
670 */
671 #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
672 #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */
673 #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */
674 #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
675 #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */
676 #define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary conversion */
677 #define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence conversions */
678 #define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue overflow */
679 #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
680 #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
681 #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
682 /**
683 * @}
684 */
685
686 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
687 * @{
688 */
689 /* List of ADC registers intended to be used (most commonly) with */
690 /* DMA transfer. */
691 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
692 #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
693 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
694 /**
695 * @}
696 */
697
698 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
699 * @{
700 */
701 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */
702 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
703 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
704 #define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without prescaler */
705 #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2 */
706 #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 4 */
707 #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 6 */
708 #define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 ) /*!< ADC asynchronous clock with prescaler division by 8 */
709 #define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10 */
710 #define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 12 */
711 #define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16 */
712 #define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with prescaler division by 32 */
713 #define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 64 */
714 #define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division by 128 */
715 #define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256 */
716 /**
717 * @}
718 */
719
720 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
721 * @{
722 */
723 /* Note: Other measurement paths to internal channels may be available */
724 /* (connections to other peripherals). */
725 /* If they are not listed below, they do not require any specific */
726 /* path enable. In this case, Access to measurement path is done */
727 /* only by selecting the corresponding ADC internal channel. */
728 #define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement pathes all disabled */
729 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
730 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */
731 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
732 /**
733 * @}
734 */
735
736 /** @defgroup ADC_LL_EC_BOOST_MODE ADC instance - Boost mode
737 * @{
738 */
739 #define LL_ADC_BOOST_MODE_6MHZ25 (0x00000000UL) /*!< Boost mode is configured for frequency <= 6.25Mhz */
740 #define LL_ADC_BOOST_MODE_12MHZ5 ( ADC_CR_BOOST_0) /*!< Boost mode is configured for 6.25Mhz < frequency <= 12.5Mhz */
741 #define LL_ADC_BOOST_MODE_20MHZ ( ADC_CR_BOOST_1 ) /*!< Boost mode is configured for 12.5Mhz < frequency <= 20Mhz */
742 #define LL_ADC_BOOST_MODE_25MHZ ((ADC_CR_BOOST_0 <<2) | ADC_CR_BOOST_1 ) /*!< Boost mode is configured for 20Mhz < frequency <= 25Mhz */
743 #define LL_ADC_BOOST_MODE_50MHZ ((ADC_CR_BOOST_0 <<2) | ADC_CR_BOOST_1 | ADC_CR_BOOST_0) /*!< Boost mode is configured for frequency > 25Mhz */
744 /**
745 * @}
746 */
747
748 /** @defgroup ADC_LL_EC_CALIBRATION_OFFSET_LINEARITY ADC instance - Calibration mode for offset and linearity
749 * @{
750 */
751 #define LL_ADC_CALIB_OFFSET (ADC_CALIB_FACTOR_OFFSET_REGOFFSET) /*!< Calibration of ADC offset. Duration of calibration of offset duration: 1280 ADC clock cycles. For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes. */
752 #define LL_ADC_CALIB_LINEARITY (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET) /*!< Calibration of ADC linearity. Duration of calibration of linearity: 15104 ADC clock cycles. For devices with differential mode available: Calibration of linearity is common to both single-ended and differential modes. */
753 #define LL_ADC_CALIB_OFFSET_LINEARITY (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET | ADC_CR_ADCALLIN) /*!< Calibration of ADC offset and linearity. Duration of calibration of offset and linearity: 16384 ADC clock cycles. For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes, calibration of linearity is common to both single-ended and differential modes. */
754 /**
755 * @}
756 */
757
758 /** @defgroup ADC_LL_EC_CALIBRATION_LINEARITY_WORD ADC instance - Calibration linearity words
759 * @{
760 */
761 #define LL_ADC_CALIB_LINEARITY_WORD1 (ADC_CR_LINCALRDYW1) /*!< ADC calibration linearity word 1 */
762 #define LL_ADC_CALIB_LINEARITY_WORD2 (ADC_CR_LINCALRDYW2) /*!< ADC calibration linearity word 2 */
763 #define LL_ADC_CALIB_LINEARITY_WORD3 (ADC_CR_LINCALRDYW3) /*!< ADC calibration linearity word 3 */
764 #define LL_ADC_CALIB_LINEARITY_WORD4 (ADC_CR_LINCALRDYW4) /*!< ADC calibration linearity word 4 */
765 #define LL_ADC_CALIB_LINEARITY_WORD5 (ADC_CR_LINCALRDYW5) /*!< ADC calibration linearity word 5 */
766 #define LL_ADC_CALIB_LINEARITY_WORD6 (ADC_CR_LINCALRDYW6) /*!< ADC calibration linearity word 6 */
767 /**
768 * @}
769 */
770
771 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
772 * @{
773 */
774 #define LL_ADC_RESOLUTION_16B (0x00000000UL) /*!< ADC resolution 16 bits */
775 #define LL_ADC_RESOLUTION_14B ( ADC_CFGR_RES_0) /*!< ADC resolution 12 bits */
776 #define LL_ADC_RESOLUTION_12B ( ADC_CFGR_RES_1 ) /*!< ADC resolution 12 bits */
777 #define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */
778
779 #if defined (ADC_VER_V5_X)
780 #define LL_ADC_RESOLUTION_14B_OPT (ADC_CFGR_RES_2 | ADC_CFGR_RES_0) /*!< ADC resolution 14 bits optimized for power consumption, available on for devices revision V only */
781 #define LL_ADC_RESOLUTION_12B_OPT (ADC_CFGR_RES_2 | ADC_CFGR_RES_1 ) /*!< ADC resolution 12 bits optimized for power consumption, available on for devices revision V only */
782 #endif
783
784 #if defined (ADC_VER_V5_3) || defined(ADC_VER_V5_V90)
785 #define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_2|ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 8 bits */
786 #else
787 #define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_2 ) /*!< ADC resolution 8 bits */
788 /*!< The resolution setting is managed internaly in the driver:
789 "LL_ADC_RESOLUTION_8B" definition: keep using the "100b" value (corresponding to STM32H74x/5x rev Y).
790 Rev.V value "111b" is handled through functions "LL_ADC_SetResolution/LL_ADC_GetResolution" with a dedicated check on DBGMCU IDCODE register */
791 #endif
792 #if defined(ADC_VER_V5_V90)
793 #define LL_ADC_RESOLUTION_6B (ADC3_CFGR_RES_1 | ADC3_CFGR_RES_0) /*!< ADC resolution 6 bits. Value available for ADC3 on STM32H72xx/3xx devices only*/
794 #endif /* ADC_VER_V5_V90 */
795 /**
796 * @}
797 */
798
799 #if defined(ADC_VER_V5_V90)
800 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
801 * @{
802 */
803 #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
804 #define LL_ADC_DATA_ALIGN_LEFT (ADC3_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
805 /**
806 * @}
807 */
808
809 #endif /* ADC_VER_V5_V90 */
810
811 /** @defgroup ADC_LL_EC_LEFT_BIT_SHIFT ADC left Shift
812 * @{
813 */
814 #define LL_ADC_LEFT_BIT_SHIFT_NONE (0x00000000UL) /*!< ADC no bit shift left applied on the final ADC convesion data */
815 #define LL_ADC_LEFT_BIT_SHIFT_1 (ADC_CFGR2_LSHIFT_0) /*!< ADC 1 bit shift left applied on the final ADC convesion data */
816 #define LL_ADC_LEFT_BIT_SHIFT_2 (ADC_CFGR2_LSHIFT_1) /*!< ADC 2 bits shift left applied on the final ADC convesion data */
817 #define LL_ADC_LEFT_BIT_SHIFT_3 (ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 3 bits shift left applied on the final ADC convesion data */
818 #define LL_ADC_LEFT_BIT_SHIFT_4 (ADC_CFGR2_LSHIFT_2) /*!< ADC 4 bits shift left applied on the final ADC convesion data */
819 #define LL_ADC_LEFT_BIT_SHIFT_5 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 5 bits shift left applied on the final ADC convesion data */
820 #define LL_ADC_LEFT_BIT_SHIFT_6 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 6 bits shift left applied on the final ADC convesion data */
821 #define LL_ADC_LEFT_BIT_SHIFT_7 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 7 bits shift left applied on the final ADC convesion data */
822 #define LL_ADC_LEFT_BIT_SHIFT_8 (ADC_CFGR2_LSHIFT_3) /*!< ADC 8 bits shift left applied on the final ADC convesion data */
823 #define LL_ADC_LEFT_BIT_SHIFT_9 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0) /*!< ADC 9 bits shift left applied on the final ADC convesion data */
824 #define LL_ADC_LEFT_BIT_SHIFT_10 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1) /*!< ADC 10 bits shift left applied on the final ADC convesion data */
825 #define LL_ADC_LEFT_BIT_SHIFT_11 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 11 bits shift left applied on the final ADC convesion data */
826 #define LL_ADC_LEFT_BIT_SHIFT_12 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2) /*!< ADC 12 bits shift left applied on the final ADC convesion data */
827 #define LL_ADC_LEFT_BIT_SHIFT_13 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 13 bits shift left applied on the final ADC convesion data */
828 #define LL_ADC_LEFT_BIT_SHIFT_14 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 14 bits shift left applied on the final ADC convesion data */
829 #define LL_ADC_LEFT_BIT_SHIFT_15 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 15 bits shift left applied on the final ADC convesion data */
830 /**
831 * @}
832 */
833
834 /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
835 * @{
836 */
837 #define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */
838 #define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
839 /**
840 * @}
841 */
842
843 /** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number
844 * @{
845 */
846 #define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
847 #define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
848 #define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
849 #define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
850 /**
851 * @}
852 */
853
854 /** @defgroup ADC_LL_EC_OFFSET_SIGNED_SATURATION ADC instance - Offset signed saturation mode
855 * @{
856 */
857 #define LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset signed saturation is disabled (among ADC selected offset number 1, 2, 3 or 4) */
858 #define LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE (ADC_OFR1_SSATE) /*!< ADC offset signed saturation is enabled (among ADC selected offset number 1, 2, 3 or 4) */
859 /**
860 * @}
861 */
862
863 /** @defgroup ADC_LL_EC_OFFSET_RSHIFT ADC instance - Offset right shift
864 * @{
865 */
866 #define LL_ADC_OFFSET_RSHIFT_DISABLE (0x00000000UL) /*!< ADC offset right shift is disabled (among ADC selected offset number 1, 2, 3 or 4) */
867 #define LL_ADC_OFFSET_RSHIFT_ENABLE (ADC_CFGR2_RSHIFT1) /*!< ADC offset right shif is enabled (among ADC selected offset number 1, 2, 3 or 4) */
868 /**
869 * @}
870 */
871 #if defined(ADC_VER_V5_V90)
872 /** @defgroup ADC_LL_EC_OFFSET_SATURATION ADC instance - Offset saturation mode
873 * @{
874 */
875 #define LL_ADC_OFFSET_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset saturation is disabled (among ADC selected offset number 1, 2, 3 or 4). On devices STM32H72xx and STM32H73xx */
876 #define LL_ADC_OFFSET_SATURATION_ENABLE (ADC3_OFR1_SATEN) /*!< ADC offset saturation is enabled (among ADC selected offset number 1, 2, 3 or 4). On devices STM32H72xx and STM32H73xx */
877 /**
878 * @}
879 */
880
881 /** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
882 * @{
883 */
884 #define LL_ADC_OFFSET_DISABLE (0x00000000UL) /*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */
885 #define LL_ADC_OFFSET_ENABLE (ADC3_OFR1_OFFSET1_EN) /*!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) */
886 /**
887 * @}
888 */
889 #if defined(ADC_VER_V5_V90)
890 /** @defgroup ADC_LL_EC_OFFSET_SIGN ADC instance - Offset sign
891 * @{
892 */
893 #define LL_ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< ADC offset is negative (among ADC selected offset number 1, 2, 3 or 4). On devices STM32H72xx and STM32H73xx */
894 #define LL_ADC_OFFSET_SIGN_POSITIVE (ADC3_OFR1_OFFSETPOS) /*!< ADC offset is positive (among ADC selected offset number 1, 2, 3 or 4). On devices STM32H72xx and STM32H73xx */
895 /**
896 * @}
897 */
898 #endif
899
900 #endif /* ADC_VER_V5_V90 */
901
902 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
903 * @{
904 */
905 #define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
906 #define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/
907 #define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */
908 /**
909 * @}
910 */
911
912 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
913 * @{
914 */
915 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
916 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
917 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
918 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
919 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
920 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
921 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
922 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
923 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
924 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
925 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
926 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
927 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
928 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
929 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
930 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
931 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
932 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
933 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
934 #define LL_ADC_CHANNEL_19 (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_SMP | ADC_CHANNEL_19_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */
935 #if defined(ADC3)
936 #if defined(ADC_VER_V5_V90)
937 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32H7, ADC channel available only on ADC instance: ADC3. */
938 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32H7, ADC channel available only on ADC instance: ADC3. */
939 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. On STM32H7, ADC channel available only on ADC instance: ADC3. */
940 #else
941 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32H7, ADC channel available only on ADC instance: ADC3. */
942 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32H7, ADC channel available only on ADC instance: ADC3. */
943 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. On STM32H7, ADC channel available only on ADC instance: ADC3. */
944 #endif
945 #else
946 /*!< Specific define for STM32H7A3xx and STM32HB3xx varieties of STM32H7XXX */
947 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32H7, ADC channel available only on ADC instance: ADC2. */
948 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32H7, ADC channel available only on ADC instance: ADC2. */
949 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. On STM32H7, ADC channel available only on ADC instance: ADC2. */
950 #endif
951 #define LL_ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */
952 #define LL_ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */
953 #if defined(DAC2)
954 /*!< Specific define for STM32H7A3xx and STM32HB3xx varieties of STM32H7XXX */
955 #define LL_ADC_CHANNEL_DAC2CH1_ADC2 (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC2 channel 1, channel specific to ADC2 */
956 #endif
957 /**
958 * @}
959 */
960
961 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
962 * @{
963 */
964 #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start. */
965 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
966 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
967 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
968 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
969 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */
970 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
971 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11 event. Trigger edge set to rising edge (default setting). */
972 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */
973 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */
974 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */
975 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */
976 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */
977 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */
978 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
979 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
980 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
981 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG1 event. Trigger edge set to rising edge (default setting). */
982 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG2 event. Trigger edge set to rising edge (default setting). */
983 #define LL_ADC_REG_TRIG_EXT_LPTIM1_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
984 #define LL_ADC_REG_TRIG_EXT_LPTIM2_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
985 #define LL_ADC_REG_TRIG_EXT_LPTIM3_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 event OUT. Trigger edge set to rising edge (default setting). */
986 #if defined (TIM23)
987 #define LL_ADC_REG_TRIG_EXT_TIM23_TRGO (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM23 TRGO event. Trigger edge set to rising edge (default setting). */
988 #endif /* TIM23 */
989 #if defined (TIM24)
990 #define LL_ADC_REG_TRIG_EXT_TIM24_TRGO (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM24 TRGO event. Trigger edge set to rising edge (default setting). */
991 #endif /* TIM24 */
992 /**
993 * @}
994 */
995
996 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
997 * @{
998 */
999 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
1000 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
1001 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
1002 /**
1003 * @}
1004 */
1005 #if defined(ADC_VER_V5_V90)
1006 /** @defgroup ADC_LL_EC_REG_SAMPLING_MODE ADC group regular - Sampling mode
1007 * @{
1008 */
1009 #define LL_ADC_REG_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is defined using @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME. On devices STM32H72xx and STM32H73xx */
1010 #define LL_ADC_REG_SAMPLING_MODE_BULB (ADC3_CFGR2_BULB) /*!< ADC conversions sampling phase starts immediately after end of conversion, and stops upon trigger event.
1011 Note: First conversion is using minimal sampling time (see @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME). On devices STM32H72xx and STM32H73xx */
1012 #define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED (ADC3_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled by trigger events:
1013 Trigger rising edge = start sampling
1014 Trigger falling edge = stop sampling and start conversion. On devices STM32H72xx and STM32H73xx */
1015 /**
1016 * @}
1017 */
1018 #endif /* ADC_VER_V5_V90 */
1019
1020 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
1021 * @{
1022 */
1023 #define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions are performed in single mode: one conversion per trigger */
1024 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
1025 /**
1026 * @}
1027 */
1028
1029 /** @defgroup ADC_LL_EC_REG_DATA_TRANSFER_MODE ADC group regular - Data transfer mode of ADC conversion data
1030 * @{
1031 */
1032 #define LL_ADC_REG_DR_TRANSFER (0x00000000UL) /*!< ADC conversions are transferred to DR rigister */
1033 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMNGT_0) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
1034 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMNGT_1 | ADC_CFGR_DMNGT_0) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
1035 #define LL_ADC_REG_DFSDM_TRANSFER (ADC_CFGR_DMNGT_1 ) /*!< ADC conversion data are transferred to DFSDM */
1036 /**
1037 * @}
1038 */
1039
1040 #if defined(ADC_VER_V5_V90)
1041 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
1042 * @{
1043 */
1044
1045 #define LL_ADC3_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA. On ADC3 of devices STM32H72xx and STM32H73xx */
1046 #define LL_ADC3_REG_DMA_TRANSFER_LIMITED ( ADC3_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. On ADC3 of devices STM32H72xx and STM32H73xx */
1047 #define LL_ADC3_REG_DMA_TRANSFER_UNLIMITED (ADC3_CFGR_DMACFG | ADC3_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. On ADC3 of devices STM32H72xx and STM32H73xx*/
1048 /**
1049 * @}
1050 */
1051 #endif
1052
1053 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
1054 * @{
1055 */
1056 #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data preserved */
1057 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */
1058 /**
1059 * @}
1060 */
1061
1062 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
1063 * @{
1064 */
1065 #define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1066 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
1067 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
1068 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
1069 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
1070 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
1071 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
1072 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
1073 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
1074 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
1075 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
1076 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
1077 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
1078 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
1079 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
1080 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
1081 /**
1082 * @}
1083 */
1084
1085 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
1086 * @{
1087 */
1088 #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable */
1089 #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
1090 #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
1091 #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
1092 #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
1093 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
1094 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
1095 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
1096 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
1097 /**
1098 * @}
1099 */
1100
1101 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
1102 * @{
1103 */
1104 #define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
1105 #define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
1106 #define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
1107 #define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
1108 #define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
1109 #define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
1110 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
1111 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
1112 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
1113 #define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
1114 #define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
1115 #define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
1116 #define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
1117 #define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
1118 #define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
1119 #define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
1120 /**
1121 * @}
1122 */
1123
1124 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
1125 * @{
1126 */
1127 #define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group injected conversion trigger internal: SW start. */
1128 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */
1129 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1130 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */
1131 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1132 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1133 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */
1134 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */
1135 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1136 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */
1137 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */
1138 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */
1139 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1140 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */
1141 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1142 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
1143 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
1144 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG2 event. Trigger edge set to rising edge (default setting). */
1145 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG4 event. Trigger edge set to rising edge (default setting). */
1146 #define LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
1147 #define LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
1148 #define LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1149 #define LL_ADC_INJ_TRIG_EXT_TIM23_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM23 TRGO event. Trigger edge set to rising edge (default setting). */
1150 #define LL_ADC_INJ_TRIG_EXT_TIM24_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM24 TRGO event. Trigger edge set to rising edge (default setting). */
1151 /**
1152 * @}
1153 */
1154
1155 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
1156 * @{
1157 */
1158 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
1159 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */
1160 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
1161 /**
1162 * @}
1163 */
1164
1165 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
1166 * @{
1167 */
1168 #define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
1169 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
1170 /**
1171 * @}
1172 */
1173
1174 /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode
1175 * @{
1176 */
1177 #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
1178 #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
1179 #define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */
1180 /**
1181 * @}
1182 */
1183
1184 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
1185 * @{
1186 */
1187 #define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1188 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
1189 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
1190 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
1191 /**
1192 * @}
1193 */
1194
1195 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
1196 * @{
1197 */
1198 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode disable */
1199 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
1200 /**
1201 * @}
1202 */
1203
1204 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
1205 * @{
1206 */
1207 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
1208 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
1209 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
1210 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
1211 /**
1212 * @}
1213 */
1214
1215 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
1216 * @{
1217 */
1218 #define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL) /*!< Sampling time 1.5 ADC clock cycles */
1219 #define LL_ADC_SAMPLINGTIME_2CYCLES_5 ( ADC_SMPR2_SMP10_0) /*!< Sampling time 2.5 ADC clock cycles */
1220 #define LL_ADC_SAMPLINGTIME_8CYCLES_5 ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 8.5 ADC clock cycles */
1221 #define LL_ADC_SAMPLINGTIME_16CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 16.5 ADC clock cycles */
1222 #define LL_ADC_SAMPLINGTIME_32CYCLES_5 (ADC_SMPR2_SMP10_2 ) /*!< Sampling time 32.5 ADC clock cycles */
1223 #define LL_ADC_SAMPLINGTIME_64CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 64.5 ADC clock cycles */
1224 #define LL_ADC_SAMPLINGTIME_387CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 387.5 ADC clock cycles */
1225 #define LL_ADC_SAMPLINGTIME_810CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 810.5 ADC clock cycles */
1226 /**
1227 * @}
1228 */
1229 #if defined(ADC_VER_V5_V90)
1230 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
1231 * @{
1232 */
1233 #define LL_ADC_SAMPLINGTIME_ADC3_2CYCLES_5 (0x00000000UL) /*!< Sampling time 2.5 ADC clock cycles. On ADC3 of devices STM32H72xx and STM32H73xx */
1234 #define LL_ADC_SAMPLINGTIME_ADC3_6CYCLES_5 ( ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles. On ADC3 of devices STM32H72xx and STM32H73xx */
1235 #define LL_ADC_SAMPLINGTIME_ADC3_12CYCLES_5 ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 12.5 ADC clock cycles. On ADC3 of devices STM32H72xx and STM32H73xx */
1236 #define LL_ADC_SAMPLINGTIME_ADC3_24CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles. On ADC3 of devices STM32H72xx and STM32H73xx */
1237 #define LL_ADC_SAMPLINGTIME_ADC3_47CYCLES_5 (ADC_SMPR2_SMP10_2 ) /*!< Sampling time 47.5 ADC clock cycles. On ADC3 of devices STM32H72xx and STM32H73xx */
1238 #define LL_ADC_SAMPLINGTIME_ADC3_92CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles. On ADC3 of devices STM32H72xx and STM32H73xx */
1239 #define LL_ADC_SAMPLINGTIME_ADC3_247CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 247.5 ADC clock cycles. On ADC3 of devices STM32H72xx and STM32H73xx */
1240 #define LL_ADC_SAMPLINGTIME_ADC3_640CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles. On ADC3 of devices STM32H72xx and STM32H73xx */
1241 /**
1242 * @}
1243 */
1244 #endif /* ADC_VER_V5_V90 */
1245
1246 /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
1247 * @{
1248 */
1249 #define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
1250 #define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
1251 #define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */
1252 /**
1253 * @}
1254 */
1255
1256 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
1257 * @{
1258 */
1259 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
1260 #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
1261 #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
1262 /**
1263 * @}
1264 */
1265
1266 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
1267 * @{
1268 */
1269 #define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */
1270 #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
1271 #define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
1272 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
1273 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
1274 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
1275 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
1276 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
1277 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
1278 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
1279 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
1280 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
1281 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
1282 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
1283 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
1284 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
1285 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
1286 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
1287 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
1288 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
1289 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
1290 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
1291 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
1292 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
1293 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
1294 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
1295 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
1296 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
1297 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
1298 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
1299 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
1300 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
1301 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
1302 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
1303 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
1304 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
1305 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
1306 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
1307 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
1308 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
1309 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
1310 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
1311 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
1312 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
1313 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
1314 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
1315 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
1316 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
1317 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
1318 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
1319 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
1320 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
1321 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
1322 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
1323 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
1324 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
1325 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
1326 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
1327 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
1328 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
1329 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
1330 #define LL_ADC_AWD_CHANNEL_19_REG ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */
1331 #define LL_ADC_AWD_CHANNEL_19_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */
1332 #define LL_ADC_AWD_CHANNEL_19_REG_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */
1333 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
1334 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
1335 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
1336 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
1337 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
1338 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
1339 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, converted by group regular only */
1340 #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, converted by group injected only */
1341 #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda */
1342 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
1343 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
1344 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
1345 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
1346 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
1347 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
1348 /**
1349 * @}
1350 */
1351
1352 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
1353 * @{
1354 */
1355 #define LL_ADC_AWD_THRESHOLD_HIGH (0x1UL) /*!< ADC analog watchdog threshold high */
1356 #define LL_ADC_AWD_THRESHOLD_LOW (0x0UL) /*!< ADC analog watchdog threshold low */
1357 /**
1358 * @}
1359 */
1360 #if defined(ADC_VER_V5_V90)
1361 /** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG Analog watchdog - filtering config
1362 * @{
1363 */
1364 #define LL_ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog wathdog no filtering, one out-of-window sample is needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
1365 #define LL_ADC_AWD_FILTERING_2SAMPLES ( ADC3_TR1_AWDFILT_0) /*!< ADC analog wathdog 2 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
1366 #define LL_ADC_AWD_FILTERING_3SAMPLES ( ADC3_TR1_AWDFILT_1 ) /*!< ADC analog wathdog 3 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
1367 #define LL_ADC_AWD_FILTERING_4SAMPLES ( ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0) /*!< ADC analog wathdog 4 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
1368 #define LL_ADC_AWD_FILTERING_5SAMPLES (ADC3_TR1_AWDFILT_2 ) /*!< ADC analog wathdog 5 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
1369 #define LL_ADC_AWD_FILTERING_6SAMPLES (ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_0) /*!< ADC analog wathdog 6 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
1370 #define LL_ADC_AWD_FILTERING_7SAMPLES (ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1 ) /*!< ADC analog wathdog 7 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
1371 #define LL_ADC_AWD_FILTERING_8SAMPLES (ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0) /*!< ADC analog wathdog 8 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
1372 /**
1373 * @}
1374 */
1375 #endif /* ADC_VER_V5_V90 */
1376
1377 /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
1378 * @{
1379 */
1380 #define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
1381 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */
1382 #define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
1383 #define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE ) /*!< ADC oversampling on conversions of ADC group injected. */
1384 #define LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
1385 /**
1386 * @}
1387 */
1388
1389 /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
1390 * @{
1391 */
1392 #define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
1393 #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
1394 /**
1395 * @}
1396 */
1397 #if defined(ADC_VER_V5_V90)
1398 /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
1399 * @{
1400 */
1401 #define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1402 #define LL_ADC_OVS_RATIO_4 ( ADC3_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1403 #define LL_ADC_OVS_RATIO_8 ( ADC3_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1404 #define LL_ADC_OVS_RATIO_16 ( ADC3_CFGR2_OVSR_1 | ADC3_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1405 #define LL_ADC_OVS_RATIO_32 (ADC3_CFGR2_OVSR_2 ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1406 #define LL_ADC_OVS_RATIO_64 (ADC3_CFGR2_OVSR_2 | ADC3_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1407 #define LL_ADC_OVS_RATIO_128 (ADC3_CFGR2_OVSR_2 | ADC3_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1408 #define LL_ADC_OVS_RATIO_256 (ADC3_CFGR2_OVSR_2 | ADC3_CFGR2_OVSR_1 | ADC3_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1409 /**
1410 * @}
1411 */
1412 #endif /* ADC_VER_V5_V90 */
1413
1414 /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift
1415 * @{
1416 */
1417 #define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
1418 #define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
1419 #define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
1420 #define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
1421 #define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
1422 #define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
1423 #define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
1424 #define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
1425 #define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
1426 #define LL_ADC_OVS_SHIFT_RIGHT_9 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 9 (sum of the ADC conversions data is divided by 512 to result as the ADC oversampling conversion data) */
1427 #define LL_ADC_OVS_SHIFT_RIGHT_10 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 10 (sum of the ADC conversions data is divided by 1024 to result as the ADC oversampling conversion data) */
1428 #define LL_ADC_OVS_SHIFT_RIGHT_11 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 11 (sum of the ADC conversions data is divided by 2048 to result as the ADC oversampling conversion data) */
1429 /**
1430 * @}
1431 */
1432
1433 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
1434 * @{
1435 */
1436 #define LL_ADC_MULTI_INDEPENDENT (0x00000000UL) /*!< ADC dual mode disabled (ADC independent mode) */
1437 #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
1438 #define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
1439 #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */
1440 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
1441 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
1442 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
1443 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
1444 /**
1445 * @}
1446 */
1447
1448 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
1449 * @{
1450 */
1451 #define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
1452 #define LL_ADC_MULTI_REG_DMA_RES_32_10B (ADC_CCR_DAMDF_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master). Setting for ADC resolution of 32 (16x2) down to 10 bits */
1453 #define LL_ADC_MULTI_REG_DMA_RES_8B (ADC_CCR_DAMDF_1 | ADC_CCR_DAMDF_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master). Setting for ADC resolution of 8 bits */
1454 /**
1455 * @}
1456 */
1457
1458 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
1459 * @{
1460 */
1461 #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5 (0x00000000UL) /*!< ADC multimode delay between two sampling phases: 1.5 ADC clock cycle for all resolution */
1462 #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5 ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2.5 ADC clock cycles for all resolution */
1463 #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5 ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 3.5 ADC clock cycles for all resolution */
1464 #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4.5 ADC clock cycles for 16, 14, 12 or 10 bits resolution */
1465 #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4.5 ADC clock cycles for 8 bits resolution */
1466 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 5.5 ADC clock cycles for 16, 14, 12 bits resolution */
1467 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 5.5 ADC clock cycles for 10 bits resolution */
1468 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles for 10 or 8 bits resolution */
1469 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6.5 ADC clock cycles for 16 or 14 bits resolution */
1470 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6.5 ADC clock cycles for 12 bits resolution */
1471 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 7.5 ADC clock cycles for 16 bits resolution */
1472 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles for 12 bits resolution */
1473 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles for 16 or 14 bits resolution */
1474 /**
1475 * @}
1476 */
1477
1478 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
1479 * @{
1480 */
1481 #define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
1482 #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */
1483 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
1484 /**
1485 * @}
1486 */
1487
1488
1489
1490 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
1491 * @note Only ADC peripheral HW delays are defined in ADC LL driver driver,
1492 * not timeout values.
1493 * For details on delays values, refer to descriptions in source code
1494 * above each literal definition.
1495 * @{
1496 */
1497
1498 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
1499 /* not timeout values. */
1500 /* Timeout values for ADC operations are dependent to device clock */
1501 /* configuration (system clock versus ADC clock), */
1502 /* and therefore must be defined in user application. */
1503 /* Indications for estimation of ADC timeout delays, for this */
1504 /* STM32 serie: */
1505 /* - ADC calibration time: maximum delay is 16384/fADC. */
1506 /* (refer to device datasheet, parameter "tCAL") */
1507 /* - ADC enable time: maximum delay is 1 conversion cycle. */
1508 /* (refer to device datasheet, parameter "tSTAB") */
1509 /* - ADC disable time: maximum delay should be a few ADC clock cycles */
1510 /* - ADC stop conversion time: maximum delay should be a few ADC clock */
1511 /* cycles */
1512 /* - ADC conversion time: duration depending on ADC clock and ADC */
1513 /* configuration. */
1514 /* (refer to device reference manual, section "Timing") */
1515
1516 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1517 /* Delay set to maximum value (refer to device datasheet, */
1518 /* parameter "tADCVREG_STUP"). */
1519 /* Unit: us */
1520 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1521
1522 /* Delay for internal voltage reference stabilization time. */
1523 /* Delay set to maximum value (refer to device datasheet, */
1524 /* parameter "ts_vrefint"). */
1525 /* Unit: us */
1526 #define LL_ADC_DELAY_VREFINT_STAB_US (5UL) /*!< Delay for internal voltage reference stabilization time */
1527
1528 /* Delay for temperature sensor stabilization time. */
1529 /* Literal set to maximum value (refer to device datasheet, */
1530 /* parameter "tSTART_RUN"). */
1531 /* Unit: us */
1532 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 26UL) /*!< Delay for temperature sensor stabilization time */
1533
1534 /* Delay required between ADC end of calibration and ADC enable. */
1535 /* Note: On this STM32 serie, a minimum number of ADC clock cycles */
1536 /* are required between ADC end of calibration and ADC enable. */
1537 /* Wait time can be computed in user application by waiting for the */
1538 /* equivalent number of CPU cycles, by taking into account */
1539 /* ratio of CPU clock versus ADC clock prescalers. */
1540 /* Unit: ADC clock cycles. */
1541 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */
1542
1543 /* Fixed timeout value for ADC linearity word bit set/clear delay. */
1544 /* Values defined to be higher than worst cases: low clock frequency, */
1545 /* maximum prescalers. */
1546 /* Ex of profile low frequency : f_ADC at 4,577 Khz (minimum value */
1547 /* according to Data sheet), linearity set/clear bit delay MAX = 6 / f_ADC + 3 cycles AHB */
1548 /* 6 / 4577 = 1,311ms */
1549 /* At maximum CPU speed (400 MHz), this means */
1550 /* 3.58 * 400 MHz = 524400 CPU cycles */
1551 #define ADC_LINEARITY_BIT_TOGGLE_TIMEOUT (524400UL) /*!< ADC linearity set/clear bit delay */
1552
1553 /**
1554 * @}
1555 */
1556
1557 /**
1558 * @}
1559 */
1560
1561
1562 /* Exported macro ------------------------------------------------------------*/
1563 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
1564 * @{
1565 */
1566
1567 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
1568 * @{
1569 */
1570
1571 /**
1572 * @brief Write a value in ADC register
1573 * @param __INSTANCE__ ADC Instance
1574 * @param __REG__ Register to be written
1575 * @param __VALUE__ Value to be written in the register
1576 * @retval None
1577 */
1578 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1579
1580 /**
1581 * @brief Read a value in ADC register
1582 * @param __INSTANCE__ ADC Instance
1583 * @param __REG__ Register to be read
1584 * @retval Register value
1585 */
1586 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1587 /**
1588 * @}
1589 */
1590
1591 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
1592 * @{
1593 */
1594
1595 #if defined(ADC_VER_V5_V90)
1596 /**
1597 * @brief Helper macro to convert the resolution defines to STM32H73x/2x ADC3 registers values
1598 * value corresponding to the ADC3 resolution according to the STM32H73x/2x RefMan.
1599 * @note The input can be a value from ADC3 resolution (12b, 10b, 8b,6b)
1600 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1601 * @arg @ref LL_ADC_RESOLUTION_12B
1602 * @arg @ref LL_ADC_RESOLUTION_10B
1603 * @arg @ref LL_ADC_RESOLUTION_8B
1604 * @arg @ref LL_ADC_RESOLUTION_6B
1605 * @retval Returned value can be one of the following values:
1606 * @arg 0x00000000UL (value correspodning to ADC3 12 bits)
1607 * @arg ADC_CFGR_RES_0 = 0x00000004 (value corresponding to ADC3 10 bits)
1608 * @arg ADC_CFGR_RES_1 = 0x00000008 (value corresponding to ADC3 8 bits)
1609 * @arg 0x0000001C (value corresponding to ADC3 6 bits)
1610 * @note This helper macro is applicable for STM32H73x/2x devices only
1611 */
1612 #define __LL_ADC12_RESOLUTION_TO_ADC3(__ADC_RESOLUTION__) \
1613 ( \
1614 ((__ADC_RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
1615 ?(0x00000000UL) \
1616 : \
1617 ((__ADC_RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
1618 ?(ADC_CFGR_RES_0) \
1619 : \
1620 ((__ADC_RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
1621 ?(ADC_CFGR_RES_1) \
1622 : \
1623 ((__ADC_RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
1624 ?((ADC_CFGR_RES_2|ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) \
1625 :(0x00000000UL) \
1626 )
1627
1628 #endif /* ADC_VER_V5_V90 */
1629
1630 /**
1631 * @brief Helper macro to get ADC channel number in decimal format
1632 * from literals LL_ADC_CHANNEL_x.
1633 * @note Example:
1634 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
1635 * will return decimal number "4".
1636 * @note The input can be a value from functions where a channel
1637 * number is returned, either defined with number
1638 * or with bitfield (only one bit must be set).
1639 * @param __CHANNEL__ This parameter can be one of the following values:
1640 * @arg @ref LL_ADC_CHANNEL_0 (3)
1641 * @arg @ref LL_ADC_CHANNEL_1 (3)
1642 * @arg @ref LL_ADC_CHANNEL_2 (3)
1643 * @arg @ref LL_ADC_CHANNEL_3 (3)
1644 * @arg @ref LL_ADC_CHANNEL_4 (3)
1645 * @arg @ref LL_ADC_CHANNEL_5 (3)
1646 * @arg @ref LL_ADC_CHANNEL_6
1647 * @arg @ref LL_ADC_CHANNEL_7
1648 * @arg @ref LL_ADC_CHANNEL_8
1649 * @arg @ref LL_ADC_CHANNEL_9
1650 * @arg @ref LL_ADC_CHANNEL_10
1651 * @arg @ref LL_ADC_CHANNEL_11
1652 * @arg @ref LL_ADC_CHANNEL_12
1653 * @arg @ref LL_ADC_CHANNEL_13
1654 * @arg @ref LL_ADC_CHANNEL_14
1655 * @arg @ref LL_ADC_CHANNEL_15
1656 * @arg @ref LL_ADC_CHANNEL_16
1657 * @arg @ref LL_ADC_CHANNEL_17
1658 * @arg @ref LL_ADC_CHANNEL_18
1659 * @arg @ref LL_ADC_CHANNEL_19
1660 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1661 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1662 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1663 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
1664 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
1665 *
1666 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
1667 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
1668 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
1669 * Other channels are slow channels (conversion rate: refer to reference manual).
1670 * @retval Value between Min_Data=0 and Max_Data=18
1671 */
1672 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1673 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) \
1674 ? ( \
1675 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
1676 ) \
1677 : \
1678 ( \
1679 (uint32_t)POSITION_VAL((__CHANNEL__)) \
1680 ) \
1681 )
1682
1683 /**
1684 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
1685 * from number in decimal format.
1686 * @note Example:
1687 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1688 * will return a data equivalent to "LL_ADC_CHANNEL_4".
1689 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
1690 * @retval Returned value can be one of the following values:
1691 * @arg @ref LL_ADC_CHANNEL_0 (3)
1692 * @arg @ref LL_ADC_CHANNEL_1 (3)
1693 * @arg @ref LL_ADC_CHANNEL_2 (3)
1694 * @arg @ref LL_ADC_CHANNEL_3 (3)
1695 * @arg @ref LL_ADC_CHANNEL_4 (3)
1696 * @arg @ref LL_ADC_CHANNEL_5 (3)
1697 * @arg @ref LL_ADC_CHANNEL_6
1698 * @arg @ref LL_ADC_CHANNEL_7
1699 * @arg @ref LL_ADC_CHANNEL_8
1700 * @arg @ref LL_ADC_CHANNEL_9
1701 * @arg @ref LL_ADC_CHANNEL_10
1702 * @arg @ref LL_ADC_CHANNEL_11
1703 * @arg @ref LL_ADC_CHANNEL_12
1704 * @arg @ref LL_ADC_CHANNEL_13
1705 * @arg @ref LL_ADC_CHANNEL_14
1706 * @arg @ref LL_ADC_CHANNEL_15
1707 * @arg @ref LL_ADC_CHANNEL_16
1708 * @arg @ref LL_ADC_CHANNEL_17
1709 * @arg @ref LL_ADC_CHANNEL_18
1710 * @arg @ref LL_ADC_CHANNEL_19
1711 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1712 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1713 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1714 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
1715 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
1716 *
1717 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
1718 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
1719 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
1720 * Other channels are slow channels (conversion rate: refer to reference manual).\n
1721 * (1, 2) For ADC channel read back from ADC register,
1722 * comparison with internal channel parameter to be done
1723 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1724 */
1725 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1726 (((__DECIMAL_NB__) <= 9UL) \
1727 ? ( \
1728 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1729 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
1730 (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1731 ) \
1732 : \
1733 ( \
1734 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1735 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
1736 (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1737 ) \
1738 )
1739
1740 /**
1741 * @brief Helper macro to determine whether the selected channel
1742 * corresponds to literal definitions of driver.
1743 * @note The different literal definitions of ADC channels are:
1744 * - ADC internal channel:
1745 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
1746 * - ADC external channel (channel connected to a GPIO pin):
1747 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
1748 * @note The channel parameter must be a value defined from literal
1749 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1750 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1751 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
1752 * must not be a value from functions where a channel number is
1753 * returned from ADC registers,
1754 * because internal and external channels share the same channel
1755 * number in ADC registers. The differentiation is made only with
1756 * parameters definitions of driver.
1757 * @param __CHANNEL__ This parameter can be one of the following values:
1758 * @arg @ref LL_ADC_CHANNEL_0 (3)
1759 * @arg @ref LL_ADC_CHANNEL_1 (3)
1760 * @arg @ref LL_ADC_CHANNEL_2 (3)
1761 * @arg @ref LL_ADC_CHANNEL_3 (3)
1762 * @arg @ref LL_ADC_CHANNEL_4 (3)
1763 * @arg @ref LL_ADC_CHANNEL_5 (3)
1764 * @arg @ref LL_ADC_CHANNEL_6
1765 * @arg @ref LL_ADC_CHANNEL_7
1766 * @arg @ref LL_ADC_CHANNEL_8
1767 * @arg @ref LL_ADC_CHANNEL_9
1768 * @arg @ref LL_ADC_CHANNEL_10
1769 * @arg @ref LL_ADC_CHANNEL_11
1770 * @arg @ref LL_ADC_CHANNEL_12
1771 * @arg @ref LL_ADC_CHANNEL_13
1772 * @arg @ref LL_ADC_CHANNEL_14
1773 * @arg @ref LL_ADC_CHANNEL_15
1774 * @arg @ref LL_ADC_CHANNEL_16
1775 * @arg @ref LL_ADC_CHANNEL_17
1776 * @arg @ref LL_ADC_CHANNEL_18
1777 * @arg @ref LL_ADC_CHANNEL_19
1778 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1779 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1780 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1781 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
1782 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
1783 *
1784 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
1785 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
1786 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
1787 * Other channels are slow channels (conversion rate: refer to reference manual).
1788 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
1789 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1790 */
1791 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1792 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
1793
1794 /**
1795 * @brief Helper macro to convert a channel defined from parameter
1796 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1797 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1798 * to its equivalent parameter definition of a ADC external channel
1799 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
1800 * @note The channel parameter can be, additionally to a value
1801 * defined from parameter definition of a ADC internal channel
1802 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
1803 * a value defined from parameter definition of
1804 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1805 * or a value from functions where a channel number is returned
1806 * from ADC registers.
1807 * @param __CHANNEL__ This parameter can be one of the following values:
1808 * @arg @ref LL_ADC_CHANNEL_0 (3)
1809 * @arg @ref LL_ADC_CHANNEL_1 (3)
1810 * @arg @ref LL_ADC_CHANNEL_2 (3)
1811 * @arg @ref LL_ADC_CHANNEL_3 (3)
1812 * @arg @ref LL_ADC_CHANNEL_4 (3)
1813 * @arg @ref LL_ADC_CHANNEL_5 (3)
1814 * @arg @ref LL_ADC_CHANNEL_6
1815 * @arg @ref LL_ADC_CHANNEL_7
1816 * @arg @ref LL_ADC_CHANNEL_8
1817 * @arg @ref LL_ADC_CHANNEL_9
1818 * @arg @ref LL_ADC_CHANNEL_10
1819 * @arg @ref LL_ADC_CHANNEL_11
1820 * @arg @ref LL_ADC_CHANNEL_12
1821 * @arg @ref LL_ADC_CHANNEL_13
1822 * @arg @ref LL_ADC_CHANNEL_14
1823 * @arg @ref LL_ADC_CHANNEL_15
1824 * @arg @ref LL_ADC_CHANNEL_16
1825 * @arg @ref LL_ADC_CHANNEL_17
1826 * @arg @ref LL_ADC_CHANNEL_18
1827 * @arg @ref LL_ADC_CHANNEL_19
1828 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1829 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1830 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1831 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
1832 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
1833 *
1834 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
1835 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
1836 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
1837 * Other channels are slow channels (conversion rate: refer to reference manual).
1838 * @retval Returned value can be one of the following values:
1839 * @arg @ref LL_ADC_CHANNEL_0
1840 * @arg @ref LL_ADC_CHANNEL_1
1841 * @arg @ref LL_ADC_CHANNEL_2
1842 * @arg @ref LL_ADC_CHANNEL_3
1843 * @arg @ref LL_ADC_CHANNEL_4
1844 * @arg @ref LL_ADC_CHANNEL_5
1845 * @arg @ref LL_ADC_CHANNEL_6
1846 * @arg @ref LL_ADC_CHANNEL_7
1847 * @arg @ref LL_ADC_CHANNEL_8
1848 * @arg @ref LL_ADC_CHANNEL_9
1849 * @arg @ref LL_ADC_CHANNEL_10
1850 * @arg @ref LL_ADC_CHANNEL_11
1851 * @arg @ref LL_ADC_CHANNEL_12
1852 * @arg @ref LL_ADC_CHANNEL_13
1853 * @arg @ref LL_ADC_CHANNEL_14
1854 * @arg @ref LL_ADC_CHANNEL_15
1855 * @arg @ref LL_ADC_CHANNEL_16
1856 * @arg @ref LL_ADC_CHANNEL_17
1857 * @arg @ref LL_ADC_CHANNEL_18
1858 * @arg @ref LL_ADC_CHANNEL_19
1859 */
1860 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1861 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1862
1863 /**
1864 * @brief Helper macro to determine whether the internal channel
1865 * selected is available on the ADC instance selected.
1866 * @note The channel parameter must be a value defined from parameter
1867 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1868 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1869 * must not be a value defined from parameter definition of
1870 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1871 * or a value from functions where a channel number is
1872 * returned from ADC registers,
1873 * because internal and external channels share the same channel
1874 * number in ADC registers. The differentiation is made only with
1875 * parameters definitions of driver.
1876 * @param __ADC_INSTANCE__ ADC instance
1877 * @param __CHANNEL__ This parameter can be one of the following values:
1878 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1879 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1880 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1881 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
1882 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
1883 *
1884 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
1885 * (2) On STM32H7, parameter available only on ADC instance: ADC2.
1886 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1887 * Value "1" if the internal channel selected is available on the ADC instance selected.
1888 */
1889 #if defined(ADC3)
1890 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1891 ((((__ADC_INSTANCE__) == ADC2) \
1892 &&( \
1893 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) || \
1894 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) \
1895 ) \
1896 ) \
1897 || \
1898 (((__ADC_INSTANCE__) == ADC3) \
1899 &&( \
1900 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1901 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1902 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
1903 ) \
1904 ) \
1905 )
1906 #else
1907 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1908 ((((__ADC_INSTANCE__) == ADC2) \
1909 &&( \
1910 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) || \
1911 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) || \
1912 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1913 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1914 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
1915 ) \
1916 ) \
1917 )
1918 #endif
1919
1920 /**
1921 * @brief Helper macro to define ADC analog watchdog parameter:
1922 * define a single channel to monitor with analog watchdog
1923 * from sequencer channel and groups definition.
1924 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1925 * Example:
1926 * LL_ADC_SetAnalogWDMonitChannels(
1927 * ADC1, LL_ADC_AWD1,
1928 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
1929 * @param __CHANNEL__ This parameter can be one of the following values:
1930 * @arg @ref LL_ADC_CHANNEL_0 (3)
1931 * @arg @ref LL_ADC_CHANNEL_1 (3)
1932 * @arg @ref LL_ADC_CHANNEL_2 (3)
1933 * @arg @ref LL_ADC_CHANNEL_3 (3)
1934 * @arg @ref LL_ADC_CHANNEL_4 (3)
1935 * @arg @ref LL_ADC_CHANNEL_5 (3)
1936 * @arg @ref LL_ADC_CHANNEL_6
1937 * @arg @ref LL_ADC_CHANNEL_7
1938 * @arg @ref LL_ADC_CHANNEL_8
1939 * @arg @ref LL_ADC_CHANNEL_9
1940 * @arg @ref LL_ADC_CHANNEL_10
1941 * @arg @ref LL_ADC_CHANNEL_11
1942 * @arg @ref LL_ADC_CHANNEL_12
1943 * @arg @ref LL_ADC_CHANNEL_13
1944 * @arg @ref LL_ADC_CHANNEL_14
1945 * @arg @ref LL_ADC_CHANNEL_15
1946 * @arg @ref LL_ADC_CHANNEL_16
1947 * @arg @ref LL_ADC_CHANNEL_17
1948 * @arg @ref LL_ADC_CHANNEL_18
1949 * @arg @ref LL_ADC_CHANNEL_19
1950 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1951 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1952 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1953 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
1954 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
1955 *
1956 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
1957 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
1958 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
1959 * Other channels are slow channels (conversion rate: refer to reference manual).\n
1960 * (1, 2) For ADC channel read back from ADC register,
1961 * comparison with internal channel parameter to be done
1962 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1963 * @param __GROUP__ This parameter can be one of the following values:
1964 * @arg @ref LL_ADC_GROUP_REGULAR
1965 * @arg @ref LL_ADC_GROUP_INJECTED
1966 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
1967 * @retval Returned value can be one of the following values:
1968 * @arg @ref LL_ADC_AWD_DISABLE
1969 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
1970 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
1971 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
1972 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
1973 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
1974 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
1975 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
1976 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
1977 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
1978 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
1979 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
1980 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
1981 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
1982 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
1983 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
1984 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
1985 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
1986 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
1987 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
1988 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
1989 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
1990 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
1991 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
1992 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
1993 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
1994 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
1995 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
1996 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
1997 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
1998 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
1999 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
2000 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
2001 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
2002 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
2003 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
2004 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
2005 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
2006 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
2007 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
2008 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
2009 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
2010 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
2011 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
2012 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
2013 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
2014 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
2015 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
2016 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
2017 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
2018 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
2019 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
2020 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
2021 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
2022 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
2023 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
2024 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
2025 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
2026 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
2027 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
2028 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
2029 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)
2030 * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)
2031 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
2032 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
2033 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
2034 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
2035 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)
2036 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
2037 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
2038 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1)
2039 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
2040 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
2041 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(2)
2042 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(2)
2043 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (2)
2044 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(2)
2045 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(2)
2046 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (2)
2047 *
2048 * (0) On STM32H7, parameter available only on analog watchdog number: AWD1.\n
2049 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
2050 * (2) On STM32H7, parameter available only on ADC instance: ADC2.
2051 */
2052 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
2053 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
2054 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
2055 : \
2056 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
2057 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \
2058 : \
2059 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
2060 )
2061
2062 /**
2063 * @brief Helper macro to set the value of ADC analog watchdog threshold high
2064 * or low in function of ADC resolution, when ADC resolution is
2065 * different of 16 bits.
2066 * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
2067 * Example, with a ADC resolution of 8 bits, to set the value of
2068 * analog watchdog threshold high (on 18 bits):
2069 * LL_ADC_SetAnalogWDThresholds
2070 * (< ADCx param >,
2071 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_18_bits>)
2072 * );
2073 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2074 * @arg @ref LL_ADC_RESOLUTION_16B
2075 * @arg @ref LL_ADC_RESOLUTION_14B
2076 * @arg @ref LL_ADC_RESOLUTION_12B
2077 * @arg @ref LL_ADC_RESOLUTION_10B
2078 * @arg @ref LL_ADC_RESOLUTION_8B
2079 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000000 and Max_Data=0xFFFFFF
2080 * @retval Value between Min_Data=0x000000 and Max_Data=0xFFFFFF
2081 */
2082 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
2083 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
2084
2085 /**
2086 * @brief Helper macro to get the value of ADC analog watchdog threshold high
2087 * or low in function of ADC resolution, when ADC resolution is
2088 * different of 16 bits.
2089 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
2090 * Example, with a ADC resolution of 8 bits, to get the value of
2091 * analog watchdog threshold high (on 18 bits):
2092 * < threshold_value_18_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
2093 * (LL_ADC_RESOLUTION_8B,
2094 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
2095 * );
2096 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2097 * @arg @ref LL_ADC_RESOLUTION_16B
2098 * @arg @ref LL_ADC_RESOLUTION_14B
2099 * @arg @ref LL_ADC_RESOLUTION_12B
2100 * @arg @ref LL_ADC_RESOLUTION_10B
2101 * @arg @ref LL_ADC_RESOLUTION_8B
2102 * @param __AWD_THRESHOLD_16_BITS__ Value between Min_Data=0x000000 and Max_Data=0xFFFFFF
2103 * @retval Value between Min_Data=0x000000 and Max_Data=0xFFFFFF
2104 */
2105 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_16_BITS__) \
2106 ((__AWD_THRESHOLD_16_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
2107
2108 /**
2109 * @brief Helper macro to set the ADC calibration value with both single ended
2110 * and differential modes calibration factors concatenated.
2111 * @note To be used with function @ref LL_ADC_SetCalibrationOffsetFactor().
2112 * Example, to set calibration factors single ended to 0x55
2113 * and differential ended to 0x2A:
2114 * LL_ADC_SetCalibrationOffsetFactor(
2115 * ADC1,
2116 * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
2117 * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
2118 * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
2119 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2120 */
2121 #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \
2122 (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
2123
2124 /**
2125 * @brief Helper macro to get the ADC multimode conversion data of ADC master
2126 * or ADC slave from raw value with both ADC conversion data concatenated.
2127 * @note This macro is intended to be used when multimode transfer by DMA
2128 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
2129 * In this case the transferred data need to processed with this macro
2130 * to separate the conversion data of ADC master and ADC slave.
2131 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
2132 * @arg @ref LL_ADC_MULTI_MASTER
2133 * @arg @ref LL_ADC_MULTI_SLAVE
2134 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
2135 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2136 */
2137 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
2138 (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
2139
2140 /**
2141 * @brief Helper macro to select, from a ADC instance, to which ADC instance
2142 * it has a dependence in multimode (ADC master of the corresponding
2143 * ADC common instance).
2144 * @note In case of device with multimode available and a mix of
2145 * ADC instances compliant and not compliant with multimode feature,
2146 * ADC instances not compliant with multimode feature are
2147 * considered as master instances (do not depend to
2148 * any other ADC instance).
2149 * @param __ADCx__ ADC instance
2150 * @retval __ADCx__ ADC instance master of the corresponding ADC common instance
2151 */
2152 #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
2153 ( ( ((__ADCx__) == ADC2) \
2154 )? \
2155 (ADC1) \
2156 : \
2157 (__ADCx__) \
2158 )
2159
2160 /**
2161 * @brief Helper macro to select the ADC common instance
2162 * to which is belonging the selected ADC instance.
2163 * @note ADC common register instance can be used for:
2164 * - Set parameters common to several ADC instances
2165 * - Multimode (for devices with several ADC instances)
2166 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2167 * @param __ADCx__ ADC instance
2168 * @retval ADC common register instance
2169 */
2170 #if defined(ADC3_COMMON)
2171 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2172 ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) \
2173 ? ( \
2174 (ADC12_COMMON) \
2175 ) \
2176 : \
2177 ( \
2178 (ADC3_COMMON) \
2179 ) \
2180 )
2181 #else
2182 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC12_COMMON)
2183 #endif
2184
2185 /**
2186 * @brief Helper macro to check if all ADC instances sharing the same
2187 * ADC common instance are disabled.
2188 * @note This check is required by functions with setting conditioned to
2189 * ADC state:
2190 * All ADC instances of the ADC common group must be disabled.
2191 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2192 * @note On devices with only 1 ADC common instance, parameter of this macro
2193 * is useless and can be ignored (parameter kept for compatibility
2194 * with devices featuring several ADC common instances).
2195 * @param __ADCXY_COMMON__ ADC common instance
2196 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2197 * @retval Value "0" if all ADC instances sharing the same ADC common instance
2198 * are disabled.
2199 * Value "1" if at least one ADC instance sharing the same ADC common instance
2200 * is enabled.
2201 */
2202 #if defined(ADC3_COMMON)
2203 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2204 (((__ADCXY_COMMON__) == ADC12_COMMON) \
2205 ? ( \
2206 (LL_ADC_IsEnabled(ADC1) | \
2207 LL_ADC_IsEnabled(ADC2) ) \
2208 ) \
2209 : \
2210 ( \
2211 (LL_ADC_IsEnabled(ADC3)) \
2212 ) \
2213 )
2214 #else
2215 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2216 (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))
2217 #endif
2218
2219 /**
2220 * @brief Helper macro to define the ADC conversion data full-scale digital
2221 * value corresponding to the selected ADC resolution.
2222 * @note ADC conversion data full-scale corresponds to voltage range
2223 * determined by analog voltage references Vref+ and Vref-
2224 * (refer to reference manual).
2225 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2226 * @arg @ref LL_ADC_RESOLUTION_16B
2227 * @arg @ref LL_ADC_RESOLUTION_14B
2228 * @arg @ref LL_ADC_RESOLUTION_12B
2229 * @arg @ref LL_ADC_RESOLUTION_10B
2230 * @arg @ref LL_ADC_RESOLUTION_8B
2231 * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
2232 */
2233 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2234 (0xFFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
2235
2236 #if defined(ADC_VER_V5_V90)
2237 /**
2238 * @brief Helper macro to define the ADC conversion data full-scale digital
2239 * value corresponding to the selected ADC resolution.
2240 * @note ADC conversion data full-scale corresponds to voltage range
2241 * determined by analog voltage references Vref+ and Vref-
2242 * (refer to reference manual).
2243 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2244 * @arg @ref LL_ADC_RESOLUTION_12B
2245 * @arg @ref LL_ADC_RESOLUTION_10B
2246 * @arg @ref LL_ADC_RESOLUTION_8B
2247 * @arg @ref LL_ADC_RESOLUTION_6B
2248 * @retval ADC conversion data equivalent voltage value (unit: digital value of ADC conversion bitfield)
2249 */
2250 #define __LL_ADC3_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2251 (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS_ADC3 - 1UL)))
2252 #endif /* ADC_VER_V5_V90 */
2253 /**
2254 * @brief Helper macro to convert the ADC conversion data from
2255 * a resolution to another resolution.
2256 * @param __DATA__ ADC conversion data to be converted
2257 * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
2258 * This parameter can be one of the following values:
2259 * @arg @ref LL_ADC_RESOLUTION_16B
2260 * @arg @ref LL_ADC_RESOLUTION_14B
2261 * @arg @ref LL_ADC_RESOLUTION_12B
2262 * @arg @ref LL_ADC_RESOLUTION_10B
2263 * @arg @ref LL_ADC_RESOLUTION_8B
2264 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
2265 * This parameter can be one of the following values:
2266 * @arg @ref LL_ADC_RESOLUTION_16B
2267 * @arg @ref LL_ADC_RESOLUTION_14B
2268 * @arg @ref LL_ADC_RESOLUTION_12B
2269 * @arg @ref LL_ADC_RESOLUTION_10B
2270 * @arg @ref LL_ADC_RESOLUTION_8B
2271 * @retval ADC conversion data to the requested resolution
2272 */
2273 #if defined(ADC_VER_V5_X) || defined(ADC_VER_V5_V90)
2274 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
2275 __ADC_RESOLUTION_CURRENT__,\
2276 __ADC_RESOLUTION_TARGET__) \
2277 ( (__ADC_RESOLUTION_CURRENT__ == LL_ADC_RESOLUTION_8B) \
2278 ?( \
2279 ((__DATA__) \
2280 << (((__ADC_RESOLUTION_CURRENT__) & ~(ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2281 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2282 ) \
2283 : \
2284 ( \
2285 (__ADC_RESOLUTION_TARGET__ == LL_ADC_RESOLUTION_8B) \
2286 ? ( \
2287 ((__DATA__) \
2288 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2289 >> (((__ADC_RESOLUTION_TARGET__) & ~(ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2290 ) \
2291 :\
2292 (\
2293 ((__DATA__) \
2294 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2295 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2296 ) \
2297 )\
2298 )
2299
2300
2301 #else /* defined(ADC_VER_V5_3) */
2302 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
2303 __ADC_RESOLUTION_CURRENT__,\
2304 __ADC_RESOLUTION_TARGET__) \
2305 ( (__ADC_RESOLUTION_CURRENT__ == LL_ADC_RESOLUTION_8B) \
2306 ?( \
2307 ((__DATA__) \
2308 << (((__ADC_RESOLUTION_CURRENT__) & ~(ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2309 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2310 ) \
2311 : \
2312 ( \
2313 (__ADC_RESOLUTION_TARGET__ == LL_ADC_RESOLUTION_8B) \
2314 ? ( \
2315 ((__DATA__) \
2316 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2317 >> (((__ADC_RESOLUTION_TARGET__) & ~(ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2318 ) \
2319 :\
2320 (\
2321 ((__DATA__) \
2322 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2323 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2324 ) \
2325 )\
2326 )
2327
2328 #endif
2329
2330 #if defined(ADC_VER_V5_V90)
2331 /**
2332 * @brief Helper macro to convert the ADC conversion data from
2333 * a resolution to another resolution.
2334 * @param __DATA__ ADC conversion data to be converted
2335 * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
2336 * This parameter can be one of the following values:
2337 * @arg @ref LL_ADC_RESOLUTION_12B
2338 * @arg @ref LL_ADC_RESOLUTION_10B
2339 * @arg @ref LL_ADC_RESOLUTION_8B
2340 * @arg @ref LL_ADC_RESOLUTION_6B
2341 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
2342 * This parameter can be one of the following values:
2343 * @arg @ref LL_ADC_RESOLUTION_12B
2344 * @arg @ref LL_ADC_RESOLUTION_10B
2345 * @arg @ref LL_ADC_RESOLUTION_8B
2346 * @arg @ref LL_ADC_RESOLUTION_6B
2347 * @retval ADC conversion data to the requested resolution
2348 */
2349 #define __LL_ADC_CONVERT_DATA_RESOLUTION_ADC3(__DATA__,\
2350 __ADC_RESOLUTION_CURRENT__,\
2351 __ADC_RESOLUTION_TARGET__) \
2352 (((__DATA__) \
2353 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS_ADC3 - 1UL))) \
2354 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS_ADC3 - 1UL)) \
2355 )
2356 #endif /* ADC_VER_V5_V90 */
2357 /**
2358 * @brief Helper macro to calculate the voltage (unit: mVolt)
2359 * corresponding to a ADC conversion data (unit: digital value).
2360 * @note Analog reference voltage (Vref+) must be either known from
2361 * user board environment or can be calculated using ADC measurement
2362 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2363 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2364 * @param __ADC_DATA__ ADC conversion data (resolution 16 bits)
2365 * (unit: digital value).
2366 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2367 * @arg @ref LL_ADC_RESOLUTION_16B
2368 * @arg @ref LL_ADC_RESOLUTION_14B
2369 * @arg @ref LL_ADC_RESOLUTION_12B
2370 * @arg @ref LL_ADC_RESOLUTION_10B
2371 * @arg @ref LL_ADC_RESOLUTION_8B
2372 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
2373 */
2374 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
2375 __ADC_DATA__,\
2376 __ADC_RESOLUTION__) \
2377 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
2378 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2379 )
2380
2381 /**
2382 * @brief Helper macro to calculate analog reference voltage (Vref+)
2383 * (unit: mVolt) from ADC conversion data of internal voltage
2384 * reference VrefInt.
2385 * @note Computation is using VrefInt calibration value
2386 * stored in system memory for each device during production.
2387 * @note This voltage depends on user board environment: voltage level
2388 * connected to pin Vref+.
2389 * On devices with small package, the pin Vref+ is not present
2390 * and internally bonded to pin Vdda.
2391 * @note On this STM32 serie, calibration data of internal voltage reference
2392 * VrefInt corresponds to a resolution of 16 bits,
2393 * this is the recommended ADC resolution to convert voltage of
2394 * internal voltage reference VrefInt.
2395 * Otherwise, this macro performs the processing to scale
2396 * ADC conversion data to 16 bits.
2397 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 16 bits)
2398 * of internal voltage reference VrefInt (unit: digital value).
2399 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2400 * @arg @ref LL_ADC_RESOLUTION_16B
2401 * @arg @ref LL_ADC_RESOLUTION_14B
2402 * @arg @ref LL_ADC_RESOLUTION_12B
2403 * @arg @ref LL_ADC_RESOLUTION_10B
2404 * @arg @ref LL_ADC_RESOLUTION_8B
2405 * @retval Analog reference voltage (unit: mV)
2406 */
2407 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
2408 __ADC_RESOLUTION__) \
2409 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
2410 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
2411 (__ADC_RESOLUTION__), \
2412 LL_ADC_RESOLUTION_16B) \
2413 )
2414
2415 /**
2416 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2417 * from ADC conversion data of internal temperature sensor.
2418 * @note Computation is using temperature sensor calibration values
2419 * stored in system memory for each device during production.
2420 * @note Calculation formula:
2421 * Temperature = ((TS_ADC_DATA - TS_CAL1)
2422 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
2423 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
2424 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2425 * Avg_Slope = (TS_CAL2 - TS_CAL1)
2426 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
2427 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
2428 * TEMP_DEGC_CAL1 (calibrated in factory)
2429 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
2430 * TEMP_DEGC_CAL2 (calibrated in factory)
2431 * Caution: Calculation relevancy under reserve that calibration
2432 * parameters are correct (address and data).
2433 * To calculate temperature using temperature sensor
2434 * datasheet typical values (generic values less, therefore
2435 * less accurate than calibrated values),
2436 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
2437 * @note As calculation input, the analog reference voltage (Vref+) must be
2438 * defined as it impacts the ADC LSB equivalent voltage.
2439 * @note Analog reference voltage (Vref+) must be either known from
2440 * user board environment or can be calculated using ADC measurement
2441 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2442 * @note On this STM32 serie, calibration data of temperature sensor
2443 * corresponds to a resolution of 16 bits,
2444 * this is the recommended ADC resolution to convert voltage of
2445 * temperature sensor.
2446 * Otherwise, this macro performs the processing to scale
2447 * ADC conversion data to 16 bits.
2448 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2449 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
2450 * temperature sensor (unit: digital value).
2451 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
2452 * sensor voltage has been measured.
2453 * This parameter can be one of the following values:
2454 * @arg @ref LL_ADC_RESOLUTION_16B
2455 * @arg @ref LL_ADC_RESOLUTION_14B
2456 * @arg @ref LL_ADC_RESOLUTION_12B
2457 * @arg @ref LL_ADC_RESOLUTION_10B
2458 * @arg @ref LL_ADC_RESOLUTION_8B
2459 * @retval Temperature (unit: degree Celsius)
2460 */
2461 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
2462 __TEMPSENSOR_ADC_DATA__,\
2463 __ADC_RESOLUTION__) \
2464 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
2465 (__ADC_RESOLUTION__), \
2466 LL_ADC_RESOLUTION_16B) \
2467 * (__VREFANALOG_VOLTAGE__)) \
2468 / TEMPSENSOR_CAL_VREFANALOG) \
2469 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
2470 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
2471 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
2472 ) + TEMPSENSOR_CAL1_TEMP \
2473 )
2474
2475 /**
2476 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2477 * from ADC conversion data of internal temperature sensor.
2478 * @note Computation is using temperature sensor typical values
2479 * (refer to device datasheet).
2480 * @note Calculation formula:
2481 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
2482 * / Avg_Slope + CALx_TEMP
2483 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2484 * (unit: digital value)
2485 * Avg_Slope = temperature sensor slope
2486 * (unit: uV/Degree Celsius)
2487 * TS_TYP_CALx_VOLT = temperature sensor digital value at
2488 * temperature CALx_TEMP (unit: mV)
2489 * Caution: Calculation relevancy under reserve the temperature sensor
2490 * of the current device has characteristics in line with
2491 * datasheet typical values.
2492 * If temperature sensor calibration values are available on
2493 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
2494 * temperature calculation will be more accurate using
2495 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
2496 * @note As calculation input, the analog reference voltage (Vref+) must be
2497 * defined as it impacts the ADC LSB equivalent voltage.
2498 * @note Analog reference voltage (Vref+) must be either known from
2499 * user board environment or can be calculated using ADC measurement
2500 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2501 * @note ADC measurement data must correspond to a resolution of 16 bits
2502 * (full scale digital value 4095). If not the case, the data must be
2503 * preliminarily rescaled to an equivalent resolution of 16 bits.
2504 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
2505 * On STM32H7, refer to device datasheet parameter "Avg_Slope".
2506 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
2507 * On STM32H7, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
2508 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
2509 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
2510 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
2511 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
2512 * This parameter can be one of the following values:
2513 * @arg @ref LL_ADC_RESOLUTION_16B
2514 * @arg @ref LL_ADC_RESOLUTION_14B
2515 * @arg @ref LL_ADC_RESOLUTION_12B
2516 * @arg @ref LL_ADC_RESOLUTION_10B
2517 * @arg @ref LL_ADC_RESOLUTION_8B
2518 * @retval Temperature (unit: degree Celsius)
2519 */
2520 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
2521 __TEMPSENSOR_TYP_CALX_V__,\
2522 __TEMPSENSOR_CALX_TEMP__,\
2523 __VREFANALOG_VOLTAGE__,\
2524 __TEMPSENSOR_ADC_DATA__,\
2525 __ADC_RESOLUTION__) \
2526 ((( ( \
2527 (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
2528 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
2529 * 1000UL) \
2530 - \
2531 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
2532 * 1000UL) \
2533 ) \
2534 ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
2535 ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
2536 )
2537
2538 /**
2539 * @}
2540 */
2541
2542 /**
2543 * @}
2544 */
2545
2546
2547 /* Exported functions --------------------------------------------------------*/
2548 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
2549 * @{
2550 */
2551
2552 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
2553 * @{
2554 */
2555
2556 /**
2557 * @brief Function to help to configure DMA transfer from ADC: retrieve the
2558 * ADC register address from ADC instance and a list of ADC registers
2559 * intended to be used (most commonly) with DMA transfer.
2560 * @note These ADC registers are data registers:
2561 * when ADC conversion data is available in ADC data registers,
2562 * ADC generates a DMA transfer request.
2563 * @note This macro is intended to be used with LL DMA driver, refer to
2564 * function "LL_DMA_ConfigAddresses()".
2565 * Example:
2566 * LL_DMA_ConfigAddresses(DMA1,
2567 * LL_DMA_CHANNEL_1,
2568 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
2569 * (uint32_t)&< array or variable >,
2570 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
2571 * @note For devices with several ADC: in multimode, some devices
2572 * use a different data register outside of ADC instance scope
2573 * (common data register). This macro manages this register difference,
2574 * only ADC instance has to be set as parameter.
2575 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
2576 * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
2577 * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
2578 * @param ADCx ADC instance
2579 * @param Register This parameter can be one of the following values:
2580 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
2581 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
2582 *
2583 * (1) Available on devices with several ADC instances.
2584 * @retval ADC register address
2585 */
2586 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
2587 {
2588 uint32_t data_reg_addr;
2589
2590 if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
2591 {
2592 /* Retrieve address of register DR */
2593 data_reg_addr = (uint32_t) & (ADCx->DR);
2594 }
2595 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
2596 {
2597 /* Retrieve address of register CDR */
2598 data_reg_addr = (uint32_t) & ((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
2599 }
2600
2601 return data_reg_addr;
2602 }
2603
2604 /**
2605 * @}
2606 */
2607
2608 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
2609 * @{
2610 */
2611
2612 /**
2613 * @brief Set parameter common to several ADC: Clock source and prescaler.
2614 * @note On this STM32 serie, if ADC group injected is used, some
2615 * clock ratio constraints between ADC clock and AHB clock
2616 * must be respected.
2617 * Refer to reference manual.
2618 * @note On this STM32 serie, setting of this feature is conditioned to
2619 * ADC state:
2620 * All ADC instances of the ADC common group must be disabled.
2621 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2622 * ADC instance or by using helper macro helper macro
2623 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2624 * @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n
2625 * CCR PRESC LL_ADC_SetCommonClock
2626 * @param ADCxy_COMMON ADC common instance
2627 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2628 * @param CommonClock This parameter can be one of the following values:
2629 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
2630 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
2631 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
2632 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
2633 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
2634 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
2635 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
2636 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
2637 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
2638 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
2639 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
2640 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
2641 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
2642 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
2643 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
2644 * @retval None
2645 */
2646 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
2647 {
2648 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
2649 }
2650
2651 /**
2652 * @brief Get parameter common to several ADC: Clock source and prescaler.
2653 * @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n
2654 * CCR PRESC LL_ADC_GetCommonClock
2655 * @param ADCxy_COMMON ADC common instance
2656 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2657 * @retval Returned value can be one of the following values:
2658 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
2659 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
2660 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
2661 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
2662 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
2663 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
2664 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
2665 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
2666 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
2667 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
2668 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
2669 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
2670 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
2671 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
2672 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
2673 */
2674 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
2675 {
2676 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
2677 }
2678
2679 /**
2680 * @brief Set parameter common to several ADC: measurement path to internal
2681 * channels (VrefInt, temperature sensor, ...).
2682 * @note One or several values can be selected.
2683 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2684 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2685 * @note Stabilization time of measurement path to internal channel:
2686 * After enabling internal paths, before starting ADC conversion,
2687 * a delay is required for internal voltage reference and
2688 * temperature sensor stabilization time.
2689 * Refer to device datasheet.
2690 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
2691 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
2692 * @note ADC internal channel sampling time constraint:
2693 * For ADC conversion of internal channels,
2694 * a sampling time minimum value is required.
2695 * Refer to device datasheet.
2696 * @note On this STM32 serie, setting of this feature is conditioned to
2697 * ADC state:
2698 * All ADC instances of the ADC common group must be disabled.
2699 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2700 * ADC instance or by using helper macro helper macro
2701 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2702 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
2703 * CCR TSEN LL_ADC_SetCommonPathInternalCh\n
2704 * CCR VBATEN LL_ADC_SetCommonPathInternalCh
2705 * @param ADCxy_COMMON ADC common instance
2706 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2707 * @param PathInternal This parameter can be a combination of the following values:
2708 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2709 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2710 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2711 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2712 * @retval None
2713 */
2714 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2715 {
2716 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
2717 }
2718
2719 /**
2720 * @brief Get parameter common to several ADC: measurement path to internal
2721 * channels (VrefInt, temperature sensor, ...).
2722 * @note One or several values can be selected.
2723 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2724 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2725 * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
2726 * CCR TSEN LL_ADC_GetCommonPathInternalCh\n
2727 * CCR VBATEN LL_ADC_GetCommonPathInternalCh
2728 * @param ADCxy_COMMON ADC common instance
2729 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2730 * @retval Returned value can be a combination of the following values:
2731 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2732 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2733 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2734 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2735 */
2736 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
2737 {
2738 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
2739 }
2740
2741 /**
2742 * @}
2743 */
2744
2745 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
2746 * @{
2747 */
2748
2749 /**
2750 * @brief Set ADC calibration factor in the mode single-ended
2751 * or differential (for devices with differential mode available).
2752 * @note This function is intended to set calibration parameters
2753 * without having to perform a new calibration using
2754 * @ref LL_ADC_StartCalibration().
2755 * @note For devices with differential mode available:
2756 * Calibration of offset is specific to each of
2757 * single-ended and differential modes
2758 * (calibration factor must be specified for each of these
2759 * differential modes, if used afterwards and if the application
2760 * requires their calibration).
2761 * Calibration of linearity is common to both
2762 * single-ended and differential modes
2763 * (calibration factor can be specified only once).
2764 * @note In case of setting calibration factors of both modes single ended
2765 * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
2766 * both calibration factors must be concatenated.
2767 * To perform this processing, use helper macro
2768 * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
2769 * @note On this STM32 serie, setting of this feature is conditioned to
2770 * ADC state:
2771 * ADC must be enabled, without calibration on going, without conversion
2772 * on going on group regular.
2773 * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationOffsetFactor\n
2774 * CALFACT CALFACT_D LL_ADC_SetCalibrationOffsetFactor
2775 * @param ADCx ADC instance
2776 * @param SingleDiff This parameter can be one of the following values:
2777 * @arg @ref LL_ADC_SINGLE_ENDED
2778 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
2779 * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
2780 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
2781 * @retval None
2782 */
2783 __STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
2784 {
2785 #if defined(ADC_VER_V5_V90)
2786 MODIFY_REG(ADCx->CALFACT_RES13,
2787 SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
2788 CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
2789 #else
2790 MODIFY_REG(ADCx->CALFACT,
2791 SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
2792 CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
2793 #endif
2794 }
2795
2796 /**
2797 * @brief Get ADC calibration factor in the mode single-ended
2798 * or differential (for devices with differential mode available).
2799 * @note Calibration factors are set by hardware after performing
2800 * a calibration run using function @ref LL_ADC_StartCalibration().
2801 * @note For devices with differential mode available:
2802 * Calibration of offset is specific to each of
2803 * single-ended and differential modes
2804 * Calibration of linearity is common to both
2805 * single-ended and differential modes
2806 * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationOffsetFactor\n
2807 * CALFACT CALFACT_D LL_ADC_GetCalibrationOffsetFactor
2808 * @param ADCx ADC instance
2809 * @param SingleDiff This parameter can be one of the following values:
2810 * @arg @ref LL_ADC_SINGLE_ENDED
2811 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
2812 * @retval Value between Min_Data=0x00 and Max_Data=0x7F
2813 */
2814 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
2815 {
2816 /* Retrieve bits with position in register depending on parameter */
2817 /* "SingleDiff". */
2818 /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
2819 /* containing other bits reserved for other purpose. */
2820 #if defined(ADC_VER_V5_V90)
2821 return (uint32_t)(READ_BIT(ADCx->CALFACT_RES13, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
2822 #else
2823 return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
2824 #endif
2825 }
2826
2827 /**
2828 * @brief Set ADC Linear calibration factor in the mode single-ended.
2829 * @note This function is intended to set linear calibration parameters
2830 * without having to perform a new calibration using
2831 * @ref LL_ADC_StartCalibration().
2832 * @note On this STM32 serie, setting of this feature is conditioned to
2833 * ADC state:
2834 * ADC must be enabled, without calibration on going, without conversion
2835 * on going on group regular.
2836 * @rmtoll CALFACT2 LINCALFACT LL_ADC_SetCalibrationLinearFactor\n
2837 * CALFACT2 LINCALFACT LL_ADC_SetCalibrationLinearFactor
2838 * @param ADCx ADC instance
2839 * @param LinearityWord This parameter can be one of the following values:
2840 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD1
2841 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD2
2842 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD3
2843 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD4
2844 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD5
2845 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD6
2846 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x3FFFFFFF
2847 * @retval None
2848 */
2849 __STATIC_INLINE void LL_ADC_SetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord, uint32_t CalibrationFactor)
2850 {
2851 #if defined(ADC_VER_V5_V90)
2852 if (ADCx != ADC3)
2853 {
2854 uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;
2855 MODIFY_REG(ADCx->CALFACT2_RES14, ADC_CALFACT2_LINCALFACT, CalibrationFactor);
2856 MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, LinearityWord);
2857 while ((READ_BIT(ADCx->CR, LinearityWord) == 0UL) && (timeout_cpu_cycles > 0UL))
2858 {
2859 timeout_cpu_cycles--;
2860 }
2861 }
2862 #else /* ADC_VER_V5_V90 */
2863 uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;
2864 MODIFY_REG(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT, CalibrationFactor);
2865 MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, LinearityWord);
2866 while ((READ_BIT(ADCx->CR, LinearityWord) == 0UL) && (timeout_cpu_cycles > 0UL))
2867 {
2868 timeout_cpu_cycles--;
2869 }
2870 #endif
2871 }
2872
2873 /**
2874 * @brief Get ADC Linear calibration factor in the mode single-ended.
2875 * @note Calibration factors are set by hardware after performing
2876 * a calibration run using function @ref LL_ADC_StartCalibration().
2877 * @rmtoll CALFACT2 LINCALFACT LL_ADC_GetCalibrationLinearFactor\n
2878 * CALFACT2 LINCALFACT LL_ADC_GetCalibrationLinearFactor
2879 * @param ADCx ADC instance
2880 * @param LinearityWord This parameter can be one of the following values:
2881 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD1
2882 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD2
2883 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD3
2884 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD4
2885 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD5
2886 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD6
2887 * @retval Value between Min_Data=0x00 and Max_Data=0x3FFFFFFF
2888 */
2889 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord)
2890 {
2891 uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;
2892 CLEAR_BIT(ADCx->CR, LinearityWord);
2893 while ((READ_BIT(ADCx->CR, LinearityWord) != 0UL) && (timeout_cpu_cycles > 0UL))
2894 {
2895 timeout_cpu_cycles--;
2896 }
2897 #if defined(ADC_VER_V5_V90)
2898 return (uint32_t)(READ_BIT(ADCx->CALFACT2_RES14, ADC_CALFACT2_LINCALFACT));
2899 #else
2900 return (uint32_t)(READ_BIT(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT));
2901 #endif
2902 }
2903 /**
2904 * @brief Set ADC resolution.
2905 * Refer to reference manual for alignments formats
2906 * dependencies to ADC resolutions.
2907 * @note On this STM32 serie, setting of this feature is conditioned to
2908 * ADC state:
2909 * ADC must be disabled or enabled without conversion on going
2910 * on either groups regular or injected.
2911 * @rmtoll CFGR RES LL_ADC_SetResolution
2912 * @param ADCx ADC instance
2913 * @param Resolution This parameter can be one of the following values:
2914 * @arg @ref LL_ADC_RESOLUTION_16B
2915 * @arg @ref LL_ADC_RESOLUTION_14B
2916 * @arg @ref LL_ADC_RESOLUTION_12B
2917 * @arg @ref LL_ADC_RESOLUTION_10B
2918 * @arg @ref LL_ADC_RESOLUTION_8B
2919 * @retval None
2920 */
2921 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
2922 {
2923 #if defined(ADC_VER_V5_3)
2924
2925 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
2926
2927 #elif defined(ADC_VER_V5_V90)
2928 if (ADCx == ADC3)
2929 {
2930 MODIFY_REG(ADCx->CFGR, ADC3_CFGR_RES, (((Resolution & 0x10UL) | 0x08UL | (Resolution & 0x04UL)) & 0x00000018UL));
2931 }
2932 else
2933 {
2934 if ((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Rev.Y */
2935 {
2936 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
2937 }
2938 else /* Rev.V */
2939 {
2940 if (LL_ADC_RESOLUTION_8B == Resolution)
2941 {
2942 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution | 0x0000000CUL);
2943 }
2944 else
2945 {
2946 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
2947 }
2948 }
2949 }
2950 #else /* ADC_VER_V5_V90 */
2951 if ((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Rev.Y */
2952 {
2953 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
2954 }
2955 else /* Rev.V */
2956 {
2957 if (LL_ADC_RESOLUTION_8B == Resolution)
2958 {
2959 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution | 0x0000000CUL);
2960 }
2961 else
2962 {
2963 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
2964 }
2965 }
2966
2967 #endif /* ADC_VER_V5_X*/
2968 }
2969
2970 /**
2971 * @brief Get ADC resolution.
2972 * Refer to reference manual for alignments formats
2973 * dependencies to ADC resolutions.
2974 * @rmtoll CFGR RES LL_ADC_GetResolution
2975 * @param ADCx ADC instance
2976 * @retval Returned value can be one of the following values:
2977 * @arg @ref LL_ADC_RESOLUTION_16B
2978 * @arg @ref LL_ADC_RESOLUTION_14B
2979 * @arg @ref LL_ADC_RESOLUTION_12B
2980 * @arg @ref LL_ADC_RESOLUTION_10B
2981 * @arg @ref LL_ADC_RESOLUTION_8B
2982 * @arg @ref LL_ADC_RESOLUTION_6B **Value available for ADC3 on STM32H72x/3x devices only **
2983 */
2984 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
2985 {
2986 #if defined (ADC_VER_V5_3)
2987
2988 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
2989
2990 #elif defined(ADC_VER_V5_V90)
2991 if (ADCx == ADC3)
2992 {
2993 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC3_CFGR_RES));
2994 }
2995 else
2996 {
2997 if ((uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES)) == 0x0000001CUL)
2998 {
2999 return (LL_ADC_RESOLUTION_8B);
3000 }
3001 else
3002 {
3003 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
3004 }
3005 }
3006
3007 #else /* ADC_VER_V5_V90 */
3008 if ((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Rev.Y */
3009 {
3010 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
3011 }
3012 else /* Rev.V */
3013 {
3014 if ((uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES)) == 0x0000001CUL)
3015 {
3016 return (LL_ADC_RESOLUTION_8B);
3017 }
3018 else
3019 {
3020 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
3021 }
3022 }
3023
3024 #endif /* ADC_VER_V5_X */
3025 }
3026
3027 /**
3028 * @brief Set ADC low power mode.
3029 * @note Description of ADC low power modes:
3030 * - ADC low power mode "auto wait": Dynamic low power mode,
3031 * ADC conversions occurrences are limited to the minimum necessary
3032 * in order to reduce power consumption.
3033 * New ADC conversion starts only when the previous
3034 * unitary conversion data (for ADC group regular)
3035 * or previous sequence conversions data (for ADC group injected)
3036 * has been retrieved by user software.
3037 * In the meantime, ADC remains idle: does not performs any
3038 * other conversion.
3039 * This mode allows to automatically adapt the ADC conversions
3040 * triggers to the speed of the software that reads the data.
3041 * Moreover, this avoids risk of overrun for low frequency
3042 * applications.
3043 * How to use this low power mode:
3044 * - Do not use with interruption or DMA since these modes
3045 * have to clear immediately the EOC flag to free the
3046 * IRQ vector sequencer.
3047 * - Do use with polling: 1. Start conversion,
3048 * 2. Later on, when conversion data is needed: poll for end of
3049 * conversion to ensure that conversion is completed and
3050 * retrieve ADC conversion data. This will trig another
3051 * ADC conversion start.
3052 * - ADC low power mode "auto power-off" (feature available on
3053 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
3054 * the ADC automatically powers-off after a conversion and
3055 * automatically wakes up when a new conversion is triggered
3056 * (with startup time between trigger and start of sampling).
3057 * This feature can be combined with low power mode "auto wait".
3058 * @note With ADC low power mode "auto wait", the ADC conversion data read
3059 * is corresponding to previous ADC conversion start, independently
3060 * of delay during which ADC was idle.
3061 * Therefore, the ADC conversion data may be outdated: does not
3062 * correspond to the current voltage level on the selected
3063 * ADC channel.
3064 * @note On this STM32 serie, setting of this feature is conditioned to
3065 * ADC state:
3066 * ADC must be disabled or enabled without conversion on going
3067 * on either groups regular or injected.
3068 * @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode
3069 * @param ADCx ADC instance
3070 * @param LowPowerMode This parameter can be one of the following values:
3071 * @arg @ref LL_ADC_LP_MODE_NONE
3072 * @arg @ref LL_ADC_LP_AUTOWAIT
3073 * @retval None
3074 */
3075 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
3076 {
3077 MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
3078 }
3079
3080 /**
3081 * @brief Get ADC low power mode:
3082 * @note Description of ADC low power modes:
3083 * - ADC low power mode "auto wait": Dynamic low power mode,
3084 * ADC conversions occurrences are limited to the minimum necessary
3085 * in order to reduce power consumption.
3086 * New ADC conversion starts only when the previous
3087 * unitary conversion data (for ADC group regular)
3088 * or previous sequence conversions data (for ADC group injected)
3089 * has been retrieved by user software.
3090 * In the meantime, ADC remains idle: does not performs any
3091 * other conversion.
3092 * This mode allows to automatically adapt the ADC conversions
3093 * triggers to the speed of the software that reads the data.
3094 * Moreover, this avoids risk of overrun for low frequency
3095 * applications.
3096 * How to use this low power mode:
3097 * - Do not use with interruption or DMA since these modes
3098 * have to clear immediately the EOC flag to free the
3099 * IRQ vector sequencer.
3100 * - Do use with polling: 1. Start conversion,
3101 * 2. Later on, when conversion data is needed: poll for end of
3102 * conversion to ensure that conversion is completed and
3103 * retrieve ADC conversion data. This will trig another
3104 * ADC conversion start.
3105 * - ADC low power mode "auto power-off" (feature available on
3106 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
3107 * the ADC automatically powers-off after a conversion and
3108 * automatically wakes up when a new conversion is triggered
3109 * (with startup time between trigger and start of sampling).
3110 * This feature can be combined with low power mode "auto wait".
3111 * @note With ADC low power mode "auto wait", the ADC conversion data read
3112 * is corresponding to previous ADC conversion start, independently
3113 * of delay during which ADC was idle.
3114 * Therefore, the ADC conversion data may be outdated: does not
3115 * correspond to the current voltage level on the selected
3116 * ADC channel.
3117 * @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode
3118 * @param ADCx ADC instance
3119 * @retval Returned value can be one of the following values:
3120 * @arg @ref LL_ADC_LP_MODE_NONE
3121 * @arg @ref LL_ADC_LP_AUTOWAIT
3122 */
3123 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
3124 {
3125 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
3126 }
3127
3128 /**
3129 * @brief Set ADC selected Channel.
3130 * @note This function set the pre-selection of channel configuration.
3131 * @note Caution: Channel selections is dependent to ADC instance and IP version:
3132 * For STM32H72x/3x This is applicable only for ADC1/ADC2
3133 * For Rest of STM32H7xxx This is applicable only all the ADCs instances.
3134 *
3135 * @param ADCx ADC instance
3136 * @param Channel This parameter can be one of the following values:
3137 * @arg @ref LL_ADC_CHANNEL_0
3138 * @arg @ref LL_ADC_CHANNEL_1
3139 * @arg @ref LL_ADC_CHANNEL_2
3140 * @arg @ref LL_ADC_CHANNEL_3
3141 * @arg @ref LL_ADC_CHANNEL_4
3142 * @arg @ref LL_ADC_CHANNEL_5
3143 * @arg @ref LL_ADC_CHANNEL_6
3144 * @arg @ref LL_ADC_CHANNEL_7
3145 * @arg @ref LL_ADC_CHANNEL_8
3146 * @arg @ref LL_ADC_CHANNEL_9
3147 * @arg @ref LL_ADC_CHANNEL_10
3148 * @arg @ref LL_ADC_CHANNEL_11
3149 * @arg @ref LL_ADC_CHANNEL_12
3150 * @arg @ref LL_ADC_CHANNEL_13
3151 * @arg @ref LL_ADC_CHANNEL_14
3152 * @arg @ref LL_ADC_CHANNEL_15
3153 * @arg @ref LL_ADC_CHANNEL_16
3154 * @arg @ref LL_ADC_CHANNEL_17
3155 * @arg @ref LL_ADC_CHANNEL_18
3156 * @arg @ref LL_ADC_CHANNEL_19
3157 * @retval None
3158 */
3159 __STATIC_INLINE void LL_ADC_SetChannelPreSelection(ADC_TypeDef *ADCx, uint32_t Channel)
3160 {
3161 #if defined(ADC_VER_V5_V90)
3162 if (ADCx != ADC3)
3163 {
3164 /* ADC channels preselection */
3165 ADCx->PCSEL_RES0 |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) & 0x1FUL));
3166 }
3167 #else
3168 /* ADC channels preselection */
3169 ADCx->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) & 0x1FUL));
3170 #endif /* ADC_VER_V5_V90 */
3171 }
3172
3173 /**
3174 * @brief Set ADC selected offset number 1, 2, 3 or 4.
3175 * @note This function set the 2 items of offset configuration:
3176 * - ADC channel to which the offset programmed will be applied
3177 * (independently of channel mapped on ADC group regular
3178 * or group injected)
3179 * - Offset level (offset to be subtracted from the raw
3180 * converted data).
3181 * @note Caution: Offset format is dependent to ADC resolution:
3182 * offset has to be left-aligned on bit 11, the LSB (right bits)
3183 * are set to 0.
3184 * @note This function enables the offset, by default. It can be forced
3185 * to disable state using function LL_ADC_SetOffsetState().
3186 * @note If a channel is mapped on several offsets numbers, only the offset
3187 * with the lowest value is considered for the subtraction.
3188 * @note On this STM32 serie, setting of this feature is conditioned to
3189 * ADC state:
3190 * ADC must be disabled or enabled without conversion on going
3191 * on either groups regular or injected.
3192 * @note On STM32H7, some fast channels are available: fast analog inputs
3193 * coming from GPIO pads (ADC_IN0..5).
3194 * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n
3195 * OFR1 OFFSET1 LL_ADC_SetOffset\n
3196 * OFR1 OFFSET1_EN LL_ADC_SetOffset\n
3197 * OFR2 OFFSET2_CH LL_ADC_SetOffset\n
3198 * OFR2 OFFSET2 LL_ADC_SetOffset\n
3199 * OFR2 OFFSET2_EN LL_ADC_SetOffset\n
3200 * OFR3 OFFSET3_CH LL_ADC_SetOffset\n
3201 * OFR3 OFFSET3 LL_ADC_SetOffset\n
3202 * OFR3 OFFSET3_EN LL_ADC_SetOffset\n
3203 * OFR4 OFFSET4_CH LL_ADC_SetOffset\n
3204 * OFR4 OFFSET4 LL_ADC_SetOffset\n
3205 * OFR4 OFFSET4_EN LL_ADC_SetOffset
3206 * @param ADCx ADC instance
3207 * @param Offsety This parameter can be one of the following values:
3208 * @arg @ref LL_ADC_OFFSET_1
3209 * @arg @ref LL_ADC_OFFSET_2
3210 * @arg @ref LL_ADC_OFFSET_3
3211 * @arg @ref LL_ADC_OFFSET_4
3212 * @param Channel This parameter can be one of the following values:
3213 * @arg @ref LL_ADC_CHANNEL_0 (3)
3214 * @arg @ref LL_ADC_CHANNEL_1 (3)
3215 * @arg @ref LL_ADC_CHANNEL_2 (3)
3216 * @arg @ref LL_ADC_CHANNEL_3 (3)
3217 * @arg @ref LL_ADC_CHANNEL_4 (3)
3218 * @arg @ref LL_ADC_CHANNEL_5 (3)
3219 * @arg @ref LL_ADC_CHANNEL_6
3220 * @arg @ref LL_ADC_CHANNEL_7
3221 * @arg @ref LL_ADC_CHANNEL_8
3222 * @arg @ref LL_ADC_CHANNEL_9
3223 * @arg @ref LL_ADC_CHANNEL_10
3224 * @arg @ref LL_ADC_CHANNEL_11
3225 * @arg @ref LL_ADC_CHANNEL_12
3226 * @arg @ref LL_ADC_CHANNEL_13
3227 * @arg @ref LL_ADC_CHANNEL_14
3228 * @arg @ref LL_ADC_CHANNEL_15
3229 * @arg @ref LL_ADC_CHANNEL_16
3230 * @arg @ref LL_ADC_CHANNEL_17
3231 * @arg @ref LL_ADC_CHANNEL_18
3232 * @arg @ref LL_ADC_CHANNEL_19
3233 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3234 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
3235 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3236 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
3237 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
3238 *
3239 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
3240 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
3241 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
3242 * Other channels are slow channels (conversion rate: refer to reference manual).
3243 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0x1FFFFFF
3244 * @retval None
3245 */
3246 __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
3247 {
3248 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3249 #if defined(ADC_VER_V5_V90)
3250 if (ADCx == ADC3)
3251 {
3252 MODIFY_REG(*preg,
3253 ADC3_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
3254 ADC3_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
3255 }
3256 else
3257 #endif /* ADC_VER_V5_V90 */
3258 {
3259 MODIFY_REG(*preg,
3260 ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
3261 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
3262 }
3263 }
3264
3265 /**
3266 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3267 * Channel to which the offset programmed will be applied
3268 * (independently of channel mapped on ADC group regular
3269 * or group injected)
3270 * @note Usage of the returned channel number:
3271 * - To reinject this channel into another function LL_ADC_xxx:
3272 * the returned channel number is only partly formatted on definition
3273 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3274 * with parts of literals LL_ADC_CHANNEL_x or using
3275 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3276 * Then the selected literal LL_ADC_CHANNEL_x can be used
3277 * as parameter for another function.
3278 * - To get the channel number in decimal format:
3279 * process the returned value with the helper macro
3280 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3281 * @note On STM32H7, some fast channels are available: fast analog inputs
3282 * coming from GPIO pads (ADC_IN0..5).
3283 * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n
3284 * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n
3285 * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n
3286 * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
3287 * @param ADCx ADC instance
3288 * @param Offsety This parameter can be one of the following values:
3289 * @arg @ref LL_ADC_OFFSET_1
3290 * @arg @ref LL_ADC_OFFSET_2
3291 * @arg @ref LL_ADC_OFFSET_3
3292 * @arg @ref LL_ADC_OFFSET_4
3293 * @retval Returned value can be one of the following values:
3294 * @arg @ref LL_ADC_CHANNEL_0 (3)
3295 * @arg @ref LL_ADC_CHANNEL_1 (3)
3296 * @arg @ref LL_ADC_CHANNEL_2 (3)
3297 * @arg @ref LL_ADC_CHANNEL_3 (3)
3298 * @arg @ref LL_ADC_CHANNEL_4 (3)
3299 * @arg @ref LL_ADC_CHANNEL_5 (3)
3300 * @arg @ref LL_ADC_CHANNEL_6
3301 * @arg @ref LL_ADC_CHANNEL_7
3302 * @arg @ref LL_ADC_CHANNEL_8
3303 * @arg @ref LL_ADC_CHANNEL_9
3304 * @arg @ref LL_ADC_CHANNEL_10
3305 * @arg @ref LL_ADC_CHANNEL_11
3306 * @arg @ref LL_ADC_CHANNEL_12
3307 * @arg @ref LL_ADC_CHANNEL_13
3308 * @arg @ref LL_ADC_CHANNEL_14
3309 * @arg @ref LL_ADC_CHANNEL_15
3310 * @arg @ref LL_ADC_CHANNEL_16
3311 * @arg @ref LL_ADC_CHANNEL_17
3312 * @arg @ref LL_ADC_CHANNEL_18
3313 * @arg @ref LL_ADC_CHANNEL_19
3314 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3315 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
3316 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3317 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
3318 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
3319 *
3320 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
3321 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
3322 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
3323 * Other channels are slow channels (conversion rate: refer to reference manual).\n
3324 * (1, 2) For ADC channel read back from ADC register,
3325 * comparison with internal channel parameter to be done
3326 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3327 */
3328 __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
3329 {
3330 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3331
3332 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
3333 }
3334
3335 /**
3336 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3337 * Offset level (offset to be subtracted from the raw
3338 * converted data).
3339 * @note Caution: Offset format is dependent to ADC resolution:
3340 * offset has to be left-aligned on bit 11, the LSB (right bits)
3341 * are set to 0.
3342 * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n
3343 * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n
3344 * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n
3345 * OFR4 OFFSET4 LL_ADC_GetOffsetLevel
3346 * @param ADCx ADC instance
3347 * @param Offsety This parameter can be one of the following values:
3348 * @arg @ref LL_ADC_OFFSET_1
3349 * @arg @ref LL_ADC_OFFSET_2
3350 * @arg @ref LL_ADC_OFFSET_3
3351 * @arg @ref LL_ADC_OFFSET_4
3352 * @retval Value between Min_Data=0x000 and Max_Data=0x1FFFFFF
3353 */
3354 __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
3355 {
3356 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3357
3358 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
3359 }
3360
3361
3362 /**
3363 * @brief Set data right shift for the ADC selected offset number 1, 2, 3 or 4:
3364 * signed offset saturation if enabled or disabled.
3365 * @rmtoll CFGR2 RSHIFT LL_ADC_SetDataRightShift\n
3366 * @param ADCx ADC instance
3367 * @param Offsety This parameter can be one of the following values:
3368 * @arg @ref LL_ADC_OFFSET_1
3369 * @arg @ref LL_ADC_OFFSET_2
3370 * @arg @ref LL_ADC_OFFSET_3
3371 * @arg @ref LL_ADC_OFFSET_4
3372 * @param RigthShift This parameter can be one of the following values:
3373 * @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE
3374 * @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE
3375 * @retval Returned None
3376 */
3377 __STATIC_INLINE void LL_ADC_SetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t RigthShift)
3378 {
3379 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 | ADC_CFGR2_RSHIFT2 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT4), RigthShift << (Offsety & 0x1FUL));
3380 }
3381
3382 /**
3383 * @brief Get data right shift for the ADC selected offset number 1, 2, 3 or 4:
3384 * signed offset saturation if enabled or disabled.
3385 * @rmtoll CFGR2 RSHIFT LL_ADC_GetDataRightShift\n
3386 * @param ADCx ADC instance
3387 * @param Offsety This parameter can be one of the following values:
3388 * @arg @ref LL_ADC_OFFSET_1
3389 * @arg @ref LL_ADC_OFFSET_2
3390 * @arg @ref LL_ADC_OFFSET_3
3391 * @arg @ref LL_ADC_OFFSET_4
3392 * @retval Returned value can be one of the following values:
3393 * @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE
3394 * @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE
3395 */
3396 __STATIC_INLINE uint32_t LL_ADC_GetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety)
3397 {
3398 return (uint32_t)((READ_BIT(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 << (Offsety & 0x1FUL)))) >> (Offsety & 0x1FUL));
3399 }
3400
3401 /**
3402 * @brief Set signed saturation for the ADC selected offset number 1, 2, 3 or 4:
3403 * signed offset saturation if enabled or disabled.
3404 * @rmtoll OFR1 SSATE LL_ADC_SetOffsetSignedSaturation\n
3405 * OFR2 SSATE LL_ADC_SetOffsetSignedSaturation\n
3406 * OFR3 SSATE LL_ADC_SetOffsetSignedSaturation\n
3407 * OFR4 SSATE LL_ADC_SetOffsetSignedSaturation
3408 * @param ADCx ADC instance
3409 * @param Offsety This parameter can be one of the following values:
3410 * @arg @ref LL_ADC_OFFSET_1
3411 * @arg @ref LL_ADC_OFFSET_2
3412 * @arg @ref LL_ADC_OFFSET_3
3413 * @arg @ref LL_ADC_OFFSET_4
3414 * @param OffsetSignedSaturation This parameter can be one of the following values:
3415 * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE
3416 * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE
3417 * @retval Returned None
3418 */
3419 __STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSignedSaturation)
3420 {
3421 #if defined(ADC_VER_V5_V90)
3422 if (ADCx == ADC3)
3423 {
3424 /* Function not available on this instance */
3425 }
3426 else
3427 #endif /* ADC_VER_V5_V90 */
3428 {
3429 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3430 MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation);
3431 }
3432 }
3433
3434 /**
3435 * @brief Get signed saturation for the ADC selected offset number 1, 2, 3 or 4:
3436 * signed offset saturation if enabled or disabled.
3437 * @rmtoll OFR1 SSATE LL_ADC_GetOffsetSignedSaturation\n
3438 * OFR2 SSATE LL_ADC_GetOffsetSignedSaturation\n
3439 * OFR3 SSATE LL_ADC_GetOffsetSignedSaturation\n
3440 * OFR4 SSATE LL_ADC_GetOffsetSignedSaturation
3441 * @param ADCx ADC instance
3442 * @param Offsety This parameter can be one of the following values:
3443 * @arg @ref LL_ADC_OFFSET_1
3444 * @arg @ref LL_ADC_OFFSET_2
3445 * @arg @ref LL_ADC_OFFSET_3
3446 * @arg @ref LL_ADC_OFFSET_4
3447 * @retval Returned value can be one of the following values:
3448 * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE
3449 * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE
3450 */
3451 __STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety)
3452 {
3453 #if defined(ADC_VER_V5_V90)
3454 if (ADCx == ADC3)
3455 {
3456 /* Function not available on this instance */
3457 return 0UL;
3458 }
3459 else
3460 #endif /* ADC_VER_V5_V90 */
3461 {
3462 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3463 return (uint32_t) READ_BIT(*preg, ADC_OFR1_SSATE);
3464 }
3465 }
3466
3467 #if defined(ADC_VER_V5_V90)
3468 /**
3469 * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
3470 * choose offset saturation mode.
3471 * @note On this STM32 serie, setting of this feature is conditioned to
3472 * ADC state:
3473 * ADC must be disabled or enabled without conversion on going
3474 * on either groups regular or injected.
3475 * @rmtoll OFR1 SATEN LL_ADC_SetOffsetSaturation\n
3476 * OFR2 SATEN LL_ADC_SetOffsetSaturation\n
3477 * OFR3 SATEN LL_ADC_SetOffsetSaturation\n
3478 * OFR4 SATEN LL_ADC_SetOffsetSaturation
3479 * @param ADCx ADC instance
3480 * @param Offsety This parameter can be one of the following values:
3481 * @arg @ref LL_ADC_OFFSET_1
3482 * @arg @ref LL_ADC_OFFSET_2
3483 * @arg @ref LL_ADC_OFFSET_3
3484 * @arg @ref LL_ADC_OFFSET_4
3485 * @param OffsetSaturation This parameter can be one of the following values:
3486 * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
3487 * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
3488 * @retval None
3489 */
3490 __STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation)
3491 {
3492 if (ADCx == ADC3)
3493 {
3494 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3495
3496 MODIFY_REG(*preg,
3497 ADC3_OFR1_SATEN,
3498 OffsetSaturation);
3499 }
3500 }
3501
3502 /**
3503 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3504 * offset saturation if enabled or disabled.
3505 * @rmtoll OFR1 SATEN LL_ADC_GetOffsetSaturation\n
3506 * OFR2 SATEN LL_ADC_GetOffsetSaturation\n
3507 * OFR3 SATEN LL_ADC_GetOffsetSaturation\n
3508 * OFR4 SATEN LL_ADC_GetOffsetSaturation
3509 * @param ADCx ADC instance
3510 * @param Offsety This parameter can be one of the following values:
3511 * @arg @ref LL_ADC_OFFSET_1
3512 * @arg @ref LL_ADC_OFFSET_2
3513 * @arg @ref LL_ADC_OFFSET_3
3514 * @arg @ref LL_ADC_OFFSET_4
3515 * @retval Returned value can be one of the following values:
3516 * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
3517 * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
3518 */
3519 __STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety)
3520 {
3521 if (ADCx == ADC3)
3522 {
3523 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3524
3525 return (uint32_t) READ_BIT(*preg, ADC3_OFR1_SATEN);
3526 }else
3527 {
3528 return 0UL;
3529 }
3530 }
3531
3532 /**
3533 * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
3534 * choose offset sign.
3535 * @note On this STM32 serie, setting of this feature is conditioned to
3536 * ADC state:
3537 * ADC must be disabled or enabled without conversion on going
3538 * on either groups regular or injected.
3539 * @rmtoll OFR1 OFFSETPOS LL_ADC_SetOffsetSign\n
3540 * OFR2 OFFSETPOS LL_ADC_SetOffsetSign\n
3541 * OFR3 OFFSETPOS LL_ADC_SetOffsetSign\n
3542 * OFR4 OFFSETPOS LL_ADC_SetOffsetSign
3543 * @param ADCx ADC instance
3544 * @param Offsety This parameter can be one of the following values:
3545 * @arg @ref LL_ADC_OFFSET_1
3546 * @arg @ref LL_ADC_OFFSET_2
3547 * @arg @ref LL_ADC_OFFSET_3
3548 * @arg @ref LL_ADC_OFFSET_4
3549 * @param OffsetSign This parameter can be one of the following values:
3550 * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
3551 * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
3552 * @retval None
3553 */
3554 __STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
3555 {
3556 if (ADCx == ADC3)
3557 {
3558 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3559
3560 MODIFY_REG(*preg,
3561 ADC3_OFR1_OFFSETPOS,
3562 OffsetSign);
3563 }
3564 }
3565
3566 /**
3567 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3568 * offset sign if positive or negative.
3569 * @rmtoll OFR1 OFFSETPOS LL_ADC_GetOffsetSign\n
3570 * OFR2 OFFSETPOS LL_ADC_GetOffsetSign\n
3571 * OFR3 OFFSETPOS LL_ADC_GetOffsetSign\n
3572 * OFR4 OFFSETPOS LL_ADC_GetOffsetSign
3573 * @param ADCx ADC instance
3574 * @param Offsety This parameter can be one of the following values:
3575 * @arg @ref LL_ADC_OFFSET_1
3576 * @arg @ref LL_ADC_OFFSET_2
3577 * @arg @ref LL_ADC_OFFSET_3
3578 * @arg @ref LL_ADC_OFFSET_4
3579 * @retval Returned value can be one of the following values:
3580 * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
3581 * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
3582 */
3583 __STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety)
3584 {
3585 if (ADCx == ADC3)
3586 {
3587 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3588
3589 return (uint32_t) READ_BIT(*preg, ADC3_OFR1_OFFSETPOS);
3590 }
3591 else
3592 {
3593 return 0UL;
3594 }
3595 }
3596
3597 /**
3598 * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
3599 * force offset state disable or enable
3600 * without modifying offset channel or offset value.
3601 * @note This function should be needed only in case of offset to be
3602 * enabled-disabled dynamically, and should not be needed in other cases:
3603 * function LL_ADC_SetOffset() automatically enables the offset.
3604 * @note On this STM32 serie, setting of this feature is conditioned to
3605 * ADC state:
3606 * ADC must be disabled or enabled without conversion on going
3607 * on either groups regular or injected.
3608 * @rmtoll OFR1 OFFSET1_EN LL_ADC_SetOffsetState\n
3609 * OFR2 OFFSET2_EN LL_ADC_SetOffsetState\n
3610 * OFR3 OFFSET3_EN LL_ADC_SetOffsetState\n
3611 * OFR4 OFFSET4_EN LL_ADC_SetOffsetState
3612 * @param ADCx ADC instance
3613 * @param Offsety This parameter can be one of the following values:
3614 * @arg @ref LL_ADC_OFFSET_1
3615 * @arg @ref LL_ADC_OFFSET_2
3616 * @arg @ref LL_ADC_OFFSET_3
3617 * @arg @ref LL_ADC_OFFSET_4
3618 * @param OffsetState This parameter can be one of the following values:
3619 * @arg @ref LL_ADC_OFFSET_DISABLE
3620 * @arg @ref LL_ADC_OFFSET_ENABLE
3621 * @retval None
3622 */
3623 __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
3624 {
3625 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3626 if (ADCx == ADC3)
3627 {
3628 MODIFY_REG(*preg,
3629 ADC3_OFR1_OFFSET1_EN,
3630 OffsetState);
3631 }
3632 else
3633 {
3634 MODIFY_REG(*preg,
3635 ADC_OFR1_SSATE,
3636 OffsetState);
3637 }
3638 }
3639
3640 /**
3641 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3642 * offset state disabled or enabled.
3643 * @rmtoll OFR1 OFFSET1_EN LL_ADC_GetOffsetState\n
3644 * OFR2 OFFSET2_EN LL_ADC_GetOffsetState\n
3645 * OFR3 OFFSET3_EN LL_ADC_GetOffsetState\n
3646 * OFR4 OFFSET4_EN LL_ADC_GetOffsetState
3647 * @param ADCx ADC instance
3648 * @param Offsety This parameter can be one of the following values:
3649 * @arg @ref LL_ADC_OFFSET_1
3650 * @arg @ref LL_ADC_OFFSET_2
3651 * @arg @ref LL_ADC_OFFSET_3
3652 * @arg @ref LL_ADC_OFFSET_4
3653 * @retval Returned value can be one of the following values:
3654 * @arg @ref LL_ADC_OFFSET_DISABLE
3655 * @arg @ref LL_ADC_OFFSET_ENABLE
3656 */
3657 __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety)
3658 {
3659 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3660 if (ADCx == ADC3)
3661 {
3662 return (uint32_t) READ_BIT(*preg, ADC3_OFR1_OFFSET1_EN);
3663 }
3664 else
3665 {
3666 return (uint32_t) READ_BIT(*preg, ADC_OFR1_SSATE);
3667 }
3668 }
3669
3670 #endif /* ADC_VER_V5_V90 */
3671
3672 /**
3673 * @}
3674 */
3675
3676 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
3677 * @{
3678 */
3679
3680 /**
3681 * @brief Set ADC group regular conversion trigger source:
3682 * internal (SW start) or from external peripheral (timer event,
3683 * external interrupt line).
3684 * @note On this STM32 serie, setting trigger source to external trigger
3685 * also set trigger polarity to rising edge
3686 * (default setting for compatibility with some ADC on other
3687 * STM32 families having this setting set by HW default value).
3688 * In case of need to modify trigger edge, use
3689 * function @ref LL_ADC_REG_SetTriggerEdge().
3690 * @note Availability of parameters of trigger sources from timer
3691 * depends on timers availability on the selected device.
3692 * @note On this STM32 serie, setting of this feature is conditioned to
3693 * ADC state:
3694 * ADC must be disabled or enabled without conversion on going
3695 * on group regular.
3696 * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n
3697 * CFGR EXTEN LL_ADC_REG_SetTriggerSource
3698 * @param ADCx ADC instance
3699 * @param TriggerSource This parameter can be one of the following values:
3700 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
3701 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
3702 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
3703 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
3704 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
3705 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
3706 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
3707 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
3708 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
3709 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
3710 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
3711 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
3712 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
3713 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
3714 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
3715 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
3716 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
3717 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
3718 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
3719 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_OUT
3720 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_OUT
3721 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_OUT
3722 * @retval None
3723 */
3724 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
3725 {
3726 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
3727 }
3728
3729 /**
3730 * @brief Get ADC group regular conversion trigger source:
3731 * internal (SW start) or from external peripheral (timer event,
3732 * external interrupt line).
3733 * @note To determine whether group regular trigger source is
3734 * internal (SW start) or external, without detail
3735 * of which peripheral is selected as external trigger,
3736 * (equivalent to
3737 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
3738 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
3739 * @note Availability of parameters of trigger sources from timer
3740 * depends on timers availability on the selected device.
3741 * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n
3742 * CFGR EXTEN LL_ADC_REG_GetTriggerSource
3743 * @param ADCx ADC instance
3744 * @retval Returned value can be one of the following values:
3745 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
3746 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
3747 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
3748 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
3749 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
3750 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
3751 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
3752 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
3753 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
3754 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
3755 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
3756 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
3757 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
3758 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
3759 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
3760 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
3761 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
3762 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
3763 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
3764 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_OUT
3765 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_OUT
3766 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_OUT
3767 */
3768 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
3769 {
3770 __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
3771
3772 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
3773 /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
3774 uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
3775
3776 /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
3777 /* to match with triggers literals definition. */
3778 return ((TriggerSource
3779 & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)
3780 | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)
3781 );
3782 }
3783
3784 /**
3785 * @brief Get ADC group regular conversion trigger source internal (SW start)
3786 * or external.
3787 * @note In case of group regular trigger source set to external trigger,
3788 * to determine which peripheral is selected as external trigger,
3789 * use function @ref LL_ADC_REG_GetTriggerSource().
3790 * @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart
3791 * @param ADCx ADC instance
3792 * @retval Value "0" if trigger source external trigger
3793 * Value "1" if trigger source SW start.
3794 */
3795 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
3796 {
3797 return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
3798 }
3799
3800 /**
3801 * @brief Set ADC group regular conversion trigger polarity.
3802 * @note Applicable only for trigger source set to external trigger.
3803 * @note On this STM32 serie, setting of this feature is conditioned to
3804 * ADC state:
3805 * ADC must be disabled or enabled without conversion on going
3806 * on group regular.
3807 * @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge
3808 * @param ADCx ADC instance
3809 * @param ExternalTriggerEdge This parameter can be one of the following values:
3810 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3811 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3812 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3813 * @retval None
3814 */
3815 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
3816 {
3817 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
3818 }
3819
3820 /**
3821 * @brief Get ADC group regular conversion trigger polarity.
3822 * @note Applicable only for trigger source set to external trigger.
3823 * @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge
3824 * @param ADCx ADC instance
3825 * @retval Returned value can be one of the following values:
3826 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3827 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3828 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3829 */
3830 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
3831 {
3832 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
3833 }
3834
3835 #if defined(ADC_VER_V5_V90)
3836 /**
3837 * @brief Set ADC sampling mode.
3838 * @note This function set the ADC conversion sampling mode
3839 * @note This mode applies to regular group only.
3840 * @note Set sampling mode is appied to all conversion of regular group.
3841 * @note On this STM32 serie, setting of this feature is conditioned to
3842 * ADC state:
3843 * ADC must be disabled or enabled without conversion on going
3844 * on group regular.
3845 * @rmtoll CFGR2 BULB LL_ADC_REG_SetSamplingMode\n
3846 * CFGR2 SMPTRIG LL_ADC_REG_SetSamplingMode
3847 * @param ADCx ADC instance
3848 * @param SamplingMode This parameter can be one of the following values:
3849 * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
3850 * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
3851 * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
3852 * @retval None
3853 */
3854 __STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t SamplingMode)
3855 {
3856 if (ADCx != ADC3)
3857 {
3858 /* Function not available on this instance */
3859 }
3860 else
3861 {
3862 MODIFY_REG(ADCx->CFGR2, ADC3_CFGR2_BULB | ADC3_CFGR2_SMPTRIG, SamplingMode);
3863 }
3864 }
3865 #endif /* ADC_VER_V5_V90 */
3866
3867 /**
3868 * @brief Set ADC group regular sequencer length and scan direction.
3869 * @note Description of ADC group regular sequencer features:
3870 * - For devices with sequencer fully configurable
3871 * (function "LL_ADC_REG_SetSequencerRanks()" available):
3872 * sequencer length and each rank affectation to a channel
3873 * are configurable.
3874 * This function performs configuration of:
3875 * - Sequence length: Number of ranks in the scan sequence.
3876 * - Sequence direction: Unless specified in parameters, sequencer
3877 * scan direction is forward (from rank 1 to rank n).
3878 * Sequencer ranks are selected using
3879 * function "LL_ADC_REG_SetSequencerRanks()".
3880 * - For devices with sequencer not fully configurable
3881 * (function "LL_ADC_REG_SetSequencerChannels()" available):
3882 * sequencer length and each rank affectation to a channel
3883 * are defined by channel number.
3884 * This function performs configuration of:
3885 * - Sequence length: Number of ranks in the scan sequence is
3886 * defined by number of channels set in the sequence,
3887 * rank of each channel is fixed by channel HW number.
3888 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3889 * - Sequence direction: Unless specified in parameters, sequencer
3890 * scan direction is forward (from lowest channel number to
3891 * highest channel number).
3892 * Sequencer ranks are selected using
3893 * function "LL_ADC_REG_SetSequencerChannels()".
3894 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
3895 * ADC conversion on only 1 channel.
3896 * @note On this STM32 serie, setting of this feature is conditioned to
3897 * ADC state:
3898 * ADC must be disabled or enabled without conversion on going
3899 * on group regular.
3900 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
3901 * @param ADCx ADC instance
3902 * @param SequencerNbRanks This parameter can be one of the following values:
3903 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
3904 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
3905 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
3906 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
3907 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
3908 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
3909 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
3910 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
3911 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
3912 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
3913 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
3914 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
3915 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
3916 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
3917 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
3918 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
3919 * @retval None
3920 */
3921 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
3922 {
3923 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
3924 }
3925
3926 /**
3927 * @brief Get ADC group regular sequencer length and scan direction.
3928 * @note Description of ADC group regular sequencer features:
3929 * - For devices with sequencer fully configurable
3930 * (function "LL_ADC_REG_SetSequencerRanks()" available):
3931 * sequencer length and each rank affectation to a channel
3932 * are configurable.
3933 * This function retrieves:
3934 * - Sequence length: Number of ranks in the scan sequence.
3935 * - Sequence direction: Unless specified in parameters, sequencer
3936 * scan direction is forward (from rank 1 to rank n).
3937 * Sequencer ranks are selected using
3938 * function "LL_ADC_REG_SetSequencerRanks()".
3939 * - For devices with sequencer not fully configurable
3940 * (function "LL_ADC_REG_SetSequencerChannels()" available):
3941 * sequencer length and each rank affectation to a channel
3942 * are defined by channel number.
3943 * This function retrieves:
3944 * - Sequence length: Number of ranks in the scan sequence is
3945 * defined by number of channels set in the sequence,
3946 * rank of each channel is fixed by channel HW number.
3947 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3948 * - Sequence direction: Unless specified in parameters, sequencer
3949 * scan direction is forward (from lowest channel number to
3950 * highest channel number).
3951 * Sequencer ranks are selected using
3952 * function "LL_ADC_REG_SetSequencerChannels()".
3953 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
3954 * ADC conversion on only 1 channel.
3955 * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength
3956 * @param ADCx ADC instance
3957 * @retval Returned value can be one of the following values:
3958 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
3959 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
3960 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
3961 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
3962 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
3963 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
3964 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
3965 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
3966 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
3967 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
3968 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
3969 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
3970 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
3971 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
3972 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
3973 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
3974 */
3975 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
3976 {
3977 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
3978 }
3979
3980 /**
3981 * @brief Set ADC group regular sequencer discontinuous mode:
3982 * sequence subdivided and scan conversions interrupted every selected
3983 * number of ranks.
3984 * @note It is not possible to enable both ADC group regular
3985 * continuous mode and sequencer discontinuous mode.
3986 * @note It is not possible to enable both ADC auto-injected mode
3987 * and ADC group regular sequencer discontinuous mode.
3988 * @note On this STM32 serie, setting of this feature is conditioned to
3989 * ADC state:
3990 * ADC must be disabled or enabled without conversion on going
3991 * on group regular.
3992 * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n
3993 * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
3994 * @param ADCx ADC instance
3995 * @param SeqDiscont This parameter can be one of the following values:
3996 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
3997 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
3998 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
3999 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
4000 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
4001 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
4002 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
4003 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
4004 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
4005 * @retval None
4006 */
4007 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
4008 {
4009 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
4010 }
4011
4012 /**
4013 * @brief Get ADC group regular sequencer discontinuous mode:
4014 * sequence subdivided and scan conversions interrupted every selected
4015 * number of ranks.
4016 * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n
4017 * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
4018 * @param ADCx ADC instance
4019 * @retval Returned value can be one of the following values:
4020 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
4021 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
4022 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
4023 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
4024 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
4025 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
4026 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
4027 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
4028 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
4029 */
4030 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
4031 {
4032 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
4033 }
4034
4035 /**
4036 * @brief Set ADC group regular sequence: channel on the selected
4037 * scan sequence rank.
4038 * @note This function performs configuration of:
4039 * - Channels ordering into each rank of scan sequence:
4040 * whatever channel can be placed into whatever rank.
4041 * @note On this STM32 serie, ADC group regular sequencer is
4042 * fully configurable: sequencer length and each rank
4043 * affectation to a channel are configurable.
4044 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
4045 * @note Depending on devices and packages, some channels may not be available.
4046 * Refer to device datasheet for channels availability.
4047 * @note On this STM32 serie, to measure internal channels (VrefInt,
4048 * TempSensor, ...), measurement paths to internal channels must be
4049 * enabled separately.
4050 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4051 * @note On this STM32 serie, setting of this feature is conditioned to
4052 * ADC state:
4053 * ADC must be disabled or enabled without conversion on going
4054 * on group regular.
4055 * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n
4056 * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n
4057 * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n
4058 * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n
4059 * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n
4060 * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n
4061 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
4062 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
4063 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
4064 * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n
4065 * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n
4066 * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n
4067 * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n
4068 * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n
4069 * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n
4070 * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
4071 * @param ADCx ADC instance
4072 * @param Rank This parameter can be one of the following values:
4073 * @arg @ref LL_ADC_REG_RANK_1
4074 * @arg @ref LL_ADC_REG_RANK_2
4075 * @arg @ref LL_ADC_REG_RANK_3
4076 * @arg @ref LL_ADC_REG_RANK_4
4077 * @arg @ref LL_ADC_REG_RANK_5
4078 * @arg @ref LL_ADC_REG_RANK_6
4079 * @arg @ref LL_ADC_REG_RANK_7
4080 * @arg @ref LL_ADC_REG_RANK_8
4081 * @arg @ref LL_ADC_REG_RANK_9
4082 * @arg @ref LL_ADC_REG_RANK_10
4083 * @arg @ref LL_ADC_REG_RANK_11
4084 * @arg @ref LL_ADC_REG_RANK_12
4085 * @arg @ref LL_ADC_REG_RANK_13
4086 * @arg @ref LL_ADC_REG_RANK_14
4087 * @arg @ref LL_ADC_REG_RANK_15
4088 * @arg @ref LL_ADC_REG_RANK_16
4089 * @param Channel This parameter can be one of the following values:
4090 * @arg @ref LL_ADC_CHANNEL_0 (3)
4091 * @arg @ref LL_ADC_CHANNEL_1 (3)
4092 * @arg @ref LL_ADC_CHANNEL_2 (3)
4093 * @arg @ref LL_ADC_CHANNEL_3 (3)
4094 * @arg @ref LL_ADC_CHANNEL_4 (3)
4095 * @arg @ref LL_ADC_CHANNEL_5 (3)
4096 * @arg @ref LL_ADC_CHANNEL_6
4097 * @arg @ref LL_ADC_CHANNEL_7
4098 * @arg @ref LL_ADC_CHANNEL_8
4099 * @arg @ref LL_ADC_CHANNEL_9
4100 * @arg @ref LL_ADC_CHANNEL_10
4101 * @arg @ref LL_ADC_CHANNEL_11
4102 * @arg @ref LL_ADC_CHANNEL_12
4103 * @arg @ref LL_ADC_CHANNEL_13
4104 * @arg @ref LL_ADC_CHANNEL_14
4105 * @arg @ref LL_ADC_CHANNEL_15
4106 * @arg @ref LL_ADC_CHANNEL_16
4107 * @arg @ref LL_ADC_CHANNEL_17
4108 * @arg @ref LL_ADC_CHANNEL_18
4109 * @arg @ref LL_ADC_CHANNEL_19
4110 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4111 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4112 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4113 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
4114 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
4115 *
4116 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
4117 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
4118 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
4119 * Other channels are slow channels (conversion rate: refer to reference manual).
4120 * @retval None
4121 */
4122 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
4123 {
4124 /* Set bits with content of parameter "Channel" with bits position */
4125 /* in register and register position depending on parameter "Rank". */
4126 /* Parameters "Rank" and "Channel" are used with masks because containing */
4127 /* other bits reserved for other purpose. */
4128 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
4129
4130 MODIFY_REG(*preg,
4131 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
4132 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
4133 }
4134
4135 /**
4136 * @brief Get ADC group regular sequence: channel on the selected
4137 * scan sequence rank.
4138 * @note On this STM32 serie, ADC group regular sequencer is
4139 * fully configurable: sequencer length and each rank
4140 * affectation to a channel are configurable.
4141 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
4142 * @note Depending on devices and packages, some channels may not be available.
4143 * Refer to device datasheet for channels availability.
4144 * @note Usage of the returned channel number:
4145 * - To reinject this channel into another function LL_ADC_xxx:
4146 * the returned channel number is only partly formatted on definition
4147 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
4148 * with parts of literals LL_ADC_CHANNEL_x or using
4149 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4150 * Then the selected literal LL_ADC_CHANNEL_x can be used
4151 * as parameter for another function.
4152 * - To get the channel number in decimal format:
4153 * process the returned value with the helper macro
4154 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4155 * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n
4156 * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n
4157 * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n
4158 * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n
4159 * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n
4160 * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n
4161 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
4162 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
4163 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
4164 * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n
4165 * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n
4166 * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n
4167 * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n
4168 * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n
4169 * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n
4170 * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
4171 * @param ADCx ADC instance
4172 * @param Rank This parameter can be one of the following values:
4173 * @arg @ref LL_ADC_REG_RANK_1
4174 * @arg @ref LL_ADC_REG_RANK_2
4175 * @arg @ref LL_ADC_REG_RANK_3
4176 * @arg @ref LL_ADC_REG_RANK_4
4177 * @arg @ref LL_ADC_REG_RANK_5
4178 * @arg @ref LL_ADC_REG_RANK_6
4179 * @arg @ref LL_ADC_REG_RANK_7
4180 * @arg @ref LL_ADC_REG_RANK_8
4181 * @arg @ref LL_ADC_REG_RANK_9
4182 * @arg @ref LL_ADC_REG_RANK_10
4183 * @arg @ref LL_ADC_REG_RANK_11
4184 * @arg @ref LL_ADC_REG_RANK_12
4185 * @arg @ref LL_ADC_REG_RANK_13
4186 * @arg @ref LL_ADC_REG_RANK_14
4187 * @arg @ref LL_ADC_REG_RANK_15
4188 * @arg @ref LL_ADC_REG_RANK_16
4189 * @retval Returned value can be one of the following values:
4190 * @arg @ref LL_ADC_CHANNEL_0 (3)
4191 * @arg @ref LL_ADC_CHANNEL_1 (3)
4192 * @arg @ref LL_ADC_CHANNEL_2 (3)
4193 * @arg @ref LL_ADC_CHANNEL_3 (3)
4194 * @arg @ref LL_ADC_CHANNEL_4 (3)
4195 * @arg @ref LL_ADC_CHANNEL_5 (3)
4196 * @arg @ref LL_ADC_CHANNEL_6
4197 * @arg @ref LL_ADC_CHANNEL_7
4198 * @arg @ref LL_ADC_CHANNEL_8
4199 * @arg @ref LL_ADC_CHANNEL_9
4200 * @arg @ref LL_ADC_CHANNEL_10
4201 * @arg @ref LL_ADC_CHANNEL_11
4202 * @arg @ref LL_ADC_CHANNEL_12
4203 * @arg @ref LL_ADC_CHANNEL_13
4204 * @arg @ref LL_ADC_CHANNEL_14
4205 * @arg @ref LL_ADC_CHANNEL_15
4206 * @arg @ref LL_ADC_CHANNEL_16
4207 * @arg @ref LL_ADC_CHANNEL_17
4208 * @arg @ref LL_ADC_CHANNEL_18
4209 * @arg @ref LL_ADC_CHANNEL_19
4210 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4211 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4212 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4213 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
4214 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
4215 *
4216 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
4217 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
4218 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
4219 * Other channels are slow channels (conversion rate: refer to reference manual).\n
4220 * (1, 2) For ADC channel read back from ADC register,
4221 * comparison with internal channel parameter to be done
4222 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
4223 */
4224 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
4225 {
4226 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
4227
4228 return (uint32_t)((READ_BIT(*preg,
4229 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
4230 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
4231 );
4232 }
4233
4234 /**
4235 * @brief Set ADC continuous conversion mode on ADC group regular.
4236 * @note Description of ADC continuous conversion mode:
4237 * - single mode: one conversion per trigger
4238 * - continuous mode: after the first trigger, following
4239 * conversions launched successively automatically.
4240 * @note It is not possible to enable both ADC group regular
4241 * continuous mode and sequencer discontinuous mode.
4242 * @note On this STM32 serie, setting of this feature is conditioned to
4243 * ADC state:
4244 * ADC must be disabled or enabled without conversion on going
4245 * on group regular.
4246 * @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode
4247 * @param ADCx ADC instance
4248 * @param Continuous This parameter can be one of the following values:
4249 * @arg @ref LL_ADC_REG_CONV_SINGLE
4250 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
4251 * @retval None
4252 */
4253 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
4254 {
4255 MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
4256 }
4257
4258 /**
4259 * @brief Get ADC continuous conversion mode on ADC group regular.
4260 * @note Description of ADC continuous conversion mode:
4261 * - single mode: one conversion per trigger
4262 * - continuous mode: after the first trigger, following
4263 * conversions launched successively automatically.
4264 * @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode
4265 * @param ADCx ADC instance
4266 * @retval Returned value can be one of the following values:
4267 * @arg @ref LL_ADC_REG_CONV_SINGLE
4268 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
4269 */
4270 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
4271 {
4272 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
4273 }
4274 /**
4275 * @brief Set ADC data transfer mode
4276 * @note Conversion data can be either:
4277 * - Available in Data Register
4278 * - Transfered by DMA in one shot mode
4279 * - Transfered by DMA in circular mode
4280 * - Transfered to DFSDM data register
4281 * @rmtoll CFGR DMNGT LL_ADC_REG_SetDataTransferMode
4282 * @param ADCx ADC instance
4283 * @param DataTransferMode Select Data Management configuration
4284 * @retval None
4285 */
4286 __STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t DataTransferMode)
4287 {
4288 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMNGT, DataTransferMode);
4289 }
4290
4291 #if defined(ADC_VER_V5_V90)
4292 /**
4293 * @brief Enable DMA requests for ADC3.
4294 * @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransfer\n
4295 * @param ADCx ADC instance
4296 * @retval None
4297 */
4298 __STATIC_INLINE void LL_ADC_EnableDMAReq (ADC_TypeDef *ADCx)
4299 {
4300 SET_BIT(ADCx->CFGR, ADC3_CFGR_DMAEN);
4301 }
4302
4303 __STATIC_INLINE void LL_ADC_DisableDMAReq(ADC_TypeDef *ADCx)
4304 {
4305 CLEAR_BIT (ADCx->CFGR, ADC3_CFGR_DMAEN);
4306 }
4307
4308 __STATIC_INLINE uint32_t LL_ADC_IsEnabledDMAReq (ADC_TypeDef *ADCx)
4309 {
4310 return ((READ_BIT(ADCx->CFGR, ADC3_CFGR_DMAEN) == (ADC3_CFGR_DMAEN)) ? 1UL : 0UL);
4311 }
4312 /**
4313 * @brief Set ADC group regular conversion data transfer: no transfer or
4314 * transfer by DMA, and DMA requests mode.
4315 * @note If transfer by DMA selected, specifies the DMA requests
4316 * mode:
4317 * - Limited mode (One shot mode): DMA transfer requests are stopped
4318 * when number of DMA data transfers (number of
4319 * ADC conversions) is reached.
4320 * This ADC mode is intended to be used with DMA mode non-circular.
4321 * - Unlimited mode: DMA transfer requests are unlimited,
4322 * whatever number of DMA data transfers (number of
4323 * ADC conversions).
4324 * This ADC mode is intended to be used with DMA mode circular.
4325 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
4326 * mode non-circular:
4327 * when DMA transfers size will be reached, DMA will stop transfers of
4328 * ADC conversions data ADC will raise an overrun error
4329 * (overrun flag and interruption if enabled).
4330 * @note For devices with several ADC instances: ADC multimode DMA
4331 * settings are available using function @ref LL_ADC_SetMultiDMATransfer().
4332 * @note To configure DMA source address (peripheral address),
4333 * use function @ref LL_ADC_DMA_GetRegAddr().
4334 * @note On this STM32 serie, setting of this feature is conditioned to
4335 * ADC state:
4336 * ADC must be disabled or enabled without conversion on going
4337 * on either groups regular or injected.
4338 * @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransferMode\n
4339 * CFGR DMACFG LL_ADC_REG_SetDMATransferMode
4340 * @param ADCx ADC instance
4341 * @param DMATransfer This parameter can be one of the following values:
4342 * @arg @ref LL_ADC3_REG_DMA_TRANSFER_NONE
4343 * @arg @ref LL_ADC3_REG_DMA_TRANSFER_LIMITED
4344 * @arg @ref LL_ADC3_REG_DMA_TRANSFER_UNLIMITED
4345 * @retval None
4346 */
4347 __STATIC_INLINE void LL_ADC_REG_SetDMATransferMode(ADC_TypeDef *ADCx, uint32_t DMATransfer)
4348 {
4349 if (ADCx == ADC3)
4350 {
4351 MODIFY_REG(ADCx->CFGR, ADC3_CFGR_DMAEN | ADC3_CFGR_DMACFG, DMATransfer);
4352 }
4353 }
4354
4355 /**
4356 * @brief Get ADC group regular conversion data transfer: no transfer or
4357 * transfer by DMA, and DMA requests mode.
4358 * @note If transfer by DMA selected, specifies the DMA requests
4359 * mode:
4360 * - Limited mode (One shot mode): DMA transfer requests are stopped
4361 * when number of DMA data transfers (number of
4362 * ADC conversions) is reached.
4363 * This ADC mode is intended to be used with DMA mode non-circular.
4364 * - Unlimited mode: DMA transfer requests are unlimited,
4365 * whatever number of DMA data transfers (number of
4366 * ADC conversions).
4367 * This ADC mode is intended to be used with DMA mode circular.
4368 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
4369 * mode non-circular:
4370 * when DMA transfers size will be reached, DMA will stop transfers of
4371 * ADC conversions data ADC will raise an overrun error
4372 * (overrun flag and interruption if enabled).
4373 * @note For devices with several ADC instances: ADC multimode DMA
4374 * settings are available using function @ref LL_ADC_GetMultiDMATransfer().
4375 * @note To configure DMA source address (peripheral address),
4376 * use function @ref LL_ADC_DMA_GetRegAddr().
4377 * @rmtoll CFGR DMAEN LL_ADC_REG_GetDMATransfer\n
4378 * CFGR DMACFG LL_ADC_REG_GetDMATransfer
4379 * @param ADCx ADC instance
4380 * @retval Returned value can be one of the following values:
4381 * @arg @ref LL_ADC3_REG_DMA_TRANSFER_NONE
4382 * @arg @ref LL_ADC3_REG_DMA_TRANSFER_LIMITED
4383 * @arg @ref LL_ADC3_REG_DMA_TRANSFER_UNLIMITED
4384 */
4385 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransferMode(ADC_TypeDef *ADCx)
4386 {
4387 if (ADCx == ADC3)
4388 {
4389 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC3_CFGR_DMAEN | ADC3_CFGR_DMACFG));
4390 }
4391 else
4392 {
4393 return 0UL;
4394 }
4395 }
4396
4397 #endif /* ADC_VER_V5_V90 */
4398
4399 /**
4400 * @brief Get ADC data transfer mode
4401 * @note Conversion data can be either:
4402 * - Available in Data Register
4403 * - Transfered by DMA in one shot mode
4404 * - Transfered by DMA in circular mode
4405 * - Transfered to DFSDM data register
4406 * @rmtoll CFGR DMNGT LL_ADC_REG_GetDataTransferMode
4407 * @param ADCx ADC instance
4408 * @retval Returned value can be one of the following values:
4409 * @arg @ref LL_ADC_REG_DR_TRANSFER
4410 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
4411 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
4412 * @arg @ref LL_ADC_REG_DFSDM_TRANSFER
4413 */
4414 __STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(ADC_TypeDef *ADCx)
4415 {
4416 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMNGT));
4417 }
4418
4419
4420 /**
4421 * @brief Set ADC group regular behavior in case of overrun:
4422 * data preserved or overwritten.
4423 * @note Compatibility with devices without feature overrun:
4424 * other devices without this feature have a behavior
4425 * equivalent to data overwritten.
4426 * The default setting of overrun is data preserved.
4427 * Therefore, for compatibility with all devices, parameter
4428 * overrun should be set to data overwritten.
4429 * @note On this STM32 serie, setting of this feature is conditioned to
4430 * ADC state:
4431 * ADC must be disabled or enabled without conversion on going
4432 * on group regular.
4433 * @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun
4434 * @param ADCx ADC instance
4435 * @param Overrun This parameter can be one of the following values:
4436 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
4437 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
4438 * @retval None
4439 */
4440 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
4441 {
4442 MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
4443 }
4444
4445 /**
4446 * @brief Get ADC group regular behavior in case of overrun:
4447 * data preserved or overwritten.
4448 * @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun
4449 * @param ADCx ADC instance
4450 * @retval Returned value can be one of the following values:
4451 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
4452 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
4453 */
4454 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
4455 {
4456 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
4457 }
4458
4459 /**
4460 * @}
4461 */
4462
4463 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
4464 * @{
4465 */
4466
4467 /**
4468 * @brief Set ADC group injected conversion trigger source:
4469 * internal (SW start) or from external peripheral (timer event,
4470 * external interrupt line).
4471 * @note On this STM32 serie, setting trigger source to external trigger
4472 * also set trigger polarity to rising edge
4473 * (default setting for compatibility with some ADC on other
4474 * STM32 families having this setting set by HW default value).
4475 * In case of need to modify trigger edge, use
4476 * function @ref LL_ADC_INJ_SetTriggerEdge().
4477 * @note Availability of parameters of trigger sources from timer
4478 * depends on timers availability on the selected device.
4479 * @note On this STM32 serie, setting of this feature is conditioned to
4480 * ADC state:
4481 * ADC must not be disabled. Can be enabled with or without conversion
4482 * on going on either groups regular or injected.
4483 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n
4484 * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
4485 * @param ADCx ADC instance
4486 * @param TriggerSource This parameter can be one of the following values:
4487 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
4488 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
4489 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4490 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
4491 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
4492 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
4493 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
4494 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
4495 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
4496 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4497 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
4498 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
4499 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
4500 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
4501 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
4502 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
4503 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
4504 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
4505 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
4506 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT
4507 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT
4508 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT
4509 * @retval None
4510 */
4511 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
4512 {
4513 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
4514 }
4515
4516 /**
4517 * @brief Get ADC group injected conversion trigger source:
4518 * internal (SW start) or from external peripheral (timer event,
4519 * external interrupt line).
4520 * @note To determine whether group injected trigger source is
4521 * internal (SW start) or external, without detail
4522 * of which peripheral is selected as external trigger,
4523 * (equivalent to
4524 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
4525 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
4526 * @note Availability of parameters of trigger sources from timer
4527 * depends on timers availability on the selected device.
4528 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n
4529 * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
4530 * @param ADCx ADC instance
4531 * @retval Returned value can be one of the following values:
4532 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
4533 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
4534 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4535 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
4536 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
4537 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
4538 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
4539 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
4540 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
4541 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4542 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
4543 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
4544 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
4545 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
4546 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
4547 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
4548 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
4549 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
4550 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
4551 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT
4552 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT
4553 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT
4554 */
4555 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
4556 {
4557 __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
4558
4559 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
4560 /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
4561 uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
4562
4563 /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
4564 /* to match with triggers literals definition. */
4565 return ((TriggerSource
4566 & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)
4567 | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)
4568 );
4569 }
4570
4571 /**
4572 * @brief Get ADC group injected conversion trigger source internal (SW start)
4573 or external
4574 * @note In case of group injected trigger source set to external trigger,
4575 * to determine which peripheral is selected as external trigger,
4576 * use function @ref LL_ADC_INJ_GetTriggerSource.
4577 * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
4578 * @param ADCx ADC instance
4579 * @retval Value "0" if trigger source external trigger
4580 * Value "1" if trigger source SW start.
4581 */
4582 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
4583 {
4584 return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
4585 }
4586
4587 /**
4588 * @brief Set ADC group injected conversion trigger polarity.
4589 * Applicable only for trigger source set to external trigger.
4590 * @note On this STM32 serie, setting of this feature is conditioned to
4591 * ADC state:
4592 * ADC must not be disabled. Can be enabled with or without conversion
4593 * on going on either groups regular or injected.
4594 * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
4595 * @param ADCx ADC instance
4596 * @param ExternalTriggerEdge This parameter can be one of the following values:
4597 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4598 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4599 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4600 * @retval None
4601 */
4602 __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4603 {
4604 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
4605 }
4606
4607 /**
4608 * @brief Get ADC group injected conversion trigger polarity.
4609 * Applicable only for trigger source set to external trigger.
4610 * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
4611 * @param ADCx ADC instance
4612 * @retval Returned value can be one of the following values:
4613 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4614 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4615 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4616 */
4617 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
4618 {
4619 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
4620 }
4621
4622 /**
4623 * @brief Set ADC group injected sequencer length and scan direction.
4624 * @note This function performs configuration of:
4625 * - Sequence length: Number of ranks in the scan sequence.
4626 * - Sequence direction: Unless specified in parameters, sequencer
4627 * scan direction is forward (from rank 1 to rank n).
4628 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4629 * ADC conversion on only 1 channel.
4630 * @note On this STM32 serie, setting of this feature is conditioned to
4631 * ADC state:
4632 * ADC must not be disabled. Can be enabled with or without conversion
4633 * on going on either groups regular or injected.
4634 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
4635 * @param ADCx ADC instance
4636 * @param SequencerNbRanks This parameter can be one of the following values:
4637 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4638 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4639 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4640 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4641 * @retval None
4642 */
4643 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
4644 {
4645 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
4646 }
4647
4648 /**
4649 * @brief Get ADC group injected sequencer length and scan direction.
4650 * @note This function retrieves:
4651 * - Sequence length: Number of ranks in the scan sequence.
4652 * - Sequence direction: Unless specified in parameters, sequencer
4653 * scan direction is forward (from rank 1 to rank n).
4654 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4655 * ADC conversion on only 1 channel.
4656 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
4657 * @param ADCx ADC instance
4658 * @retval Returned value can be one of the following values:
4659 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4660 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4661 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4662 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4663 */
4664 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
4665 {
4666 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
4667 }
4668
4669 /**
4670 * @brief Set ADC group injected sequencer discontinuous mode:
4671 * sequence subdivided and scan conversions interrupted every selected
4672 * number of ranks.
4673 * @note It is not possible to enable both ADC group injected
4674 * auto-injected mode and sequencer discontinuous mode.
4675 * @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
4676 * @param ADCx ADC instance
4677 * @param SeqDiscont This parameter can be one of the following values:
4678 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
4679 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
4680 * @retval None
4681 */
4682 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
4683 {
4684 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
4685 }
4686
4687 /**
4688 * @brief Get ADC group injected sequencer discontinuous mode:
4689 * sequence subdivided and scan conversions interrupted every selected
4690 * number of ranks.
4691 * @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
4692 * @param ADCx ADC instance
4693 * @retval Returned value can be one of the following values:
4694 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
4695 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
4696 */
4697 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
4698 {
4699 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
4700 }
4701
4702 /**
4703 * @brief Set ADC group injected sequence: channel on the selected
4704 * sequence rank.
4705 * @note Depending on devices and packages, some channels may not be available.
4706 * Refer to device datasheet for channels availability.
4707 * @note On this STM32 serie, to measure internal channels (VrefInt,
4708 * TempSensor, ...), measurement paths to internal channels must be
4709 * enabled separately.
4710 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4711 * @note On STM32H7, some fast channels are available: fast analog inputs
4712 * coming from GPIO pads (ADC_IN0..5).
4713 * @note On this STM32 serie, setting of this feature is conditioned to
4714 * ADC state:
4715 * ADC must not be disabled. Can be enabled with or without conversion
4716 * on going on either groups regular or injected.
4717 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
4718 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
4719 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
4720 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
4721 * @param ADCx ADC instance
4722 * @param Rank This parameter can be one of the following values:
4723 * @arg @ref LL_ADC_INJ_RANK_1
4724 * @arg @ref LL_ADC_INJ_RANK_2
4725 * @arg @ref LL_ADC_INJ_RANK_3
4726 * @arg @ref LL_ADC_INJ_RANK_4
4727 * @param Channel This parameter can be one of the following values:
4728 * @arg @ref LL_ADC_CHANNEL_0 (3)
4729 * @arg @ref LL_ADC_CHANNEL_1 (3)
4730 * @arg @ref LL_ADC_CHANNEL_2 (3)
4731 * @arg @ref LL_ADC_CHANNEL_3 (3)
4732 * @arg @ref LL_ADC_CHANNEL_4 (3)
4733 * @arg @ref LL_ADC_CHANNEL_5 (3)
4734 * @arg @ref LL_ADC_CHANNEL_6
4735 * @arg @ref LL_ADC_CHANNEL_7
4736 * @arg @ref LL_ADC_CHANNEL_8
4737 * @arg @ref LL_ADC_CHANNEL_9
4738 * @arg @ref LL_ADC_CHANNEL_10
4739 * @arg @ref LL_ADC_CHANNEL_11
4740 * @arg @ref LL_ADC_CHANNEL_12
4741 * @arg @ref LL_ADC_CHANNEL_13
4742 * @arg @ref LL_ADC_CHANNEL_14
4743 * @arg @ref LL_ADC_CHANNEL_15
4744 * @arg @ref LL_ADC_CHANNEL_16
4745 * @arg @ref LL_ADC_CHANNEL_17
4746 * @arg @ref LL_ADC_CHANNEL_18
4747 * @arg @ref LL_ADC_CHANNEL_19
4748 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4749 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4750 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4751 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
4752 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
4753 *
4754 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
4755 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
4756 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
4757 * Other channels are slow channels (conversion rate: refer to reference manual).
4758 * @retval None
4759 */
4760 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
4761 {
4762 /* Set bits with content of parameter "Channel" with bits position */
4763 /* in register depending on parameter "Rank". */
4764 /* Parameters "Rank" and "Channel" are used with masks because containing */
4765 /* other bits reserved for other purpose. */
4766 MODIFY_REG(ADCx->JSQR,
4767 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
4768 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
4769 }
4770
4771 /**
4772 * @brief Get ADC group injected sequence: channel on the selected
4773 * sequence rank.
4774 * @note Depending on devices and packages, some channels may not be available.
4775 * Refer to device datasheet for channels availability.
4776 * @note Usage of the returned channel number:
4777 * - To reinject this channel into another function LL_ADC_xxx:
4778 * the returned channel number is only partly formatted on definition
4779 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
4780 * with parts of literals LL_ADC_CHANNEL_x or using
4781 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4782 * Then the selected literal LL_ADC_CHANNEL_x can be used
4783 * as parameter for another function.
4784 * - To get the channel number in decimal format:
4785 * process the returned value with the helper macro
4786 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4787 * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n
4788 * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n
4789 * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n
4790 * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
4791 * @param ADCx ADC instance
4792 * @param Rank This parameter can be one of the following values:
4793 * @arg @ref LL_ADC_INJ_RANK_1
4794 * @arg @ref LL_ADC_INJ_RANK_2
4795 * @arg @ref LL_ADC_INJ_RANK_3
4796 * @arg @ref LL_ADC_INJ_RANK_4
4797 * @retval Returned value can be one of the following values:
4798 * @arg @ref LL_ADC_CHANNEL_0 (3)
4799 * @arg @ref LL_ADC_CHANNEL_1 (3)
4800 * @arg @ref LL_ADC_CHANNEL_2 (3)
4801 * @arg @ref LL_ADC_CHANNEL_3 (3)
4802 * @arg @ref LL_ADC_CHANNEL_4 (3)
4803 * @arg @ref LL_ADC_CHANNEL_5 (3)
4804 * @arg @ref LL_ADC_CHANNEL_6
4805 * @arg @ref LL_ADC_CHANNEL_7
4806 * @arg @ref LL_ADC_CHANNEL_8
4807 * @arg @ref LL_ADC_CHANNEL_9
4808 * @arg @ref LL_ADC_CHANNEL_10
4809 * @arg @ref LL_ADC_CHANNEL_11
4810 * @arg @ref LL_ADC_CHANNEL_12
4811 * @arg @ref LL_ADC_CHANNEL_13
4812 * @arg @ref LL_ADC_CHANNEL_14
4813 * @arg @ref LL_ADC_CHANNEL_15
4814 * @arg @ref LL_ADC_CHANNEL_16
4815 * @arg @ref LL_ADC_CHANNEL_17
4816 * @arg @ref LL_ADC_CHANNEL_18
4817 * @arg @ref LL_ADC_CHANNEL_19
4818 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4819 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4820 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4821 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
4822 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
4823 *
4824 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
4825 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
4826 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
4827 * Other channels are slow channels (conversion rate: refer to reference manual).\n
4828 * (1, 2) For ADC channel read back from ADC register,
4829 * comparison with internal channel parameter to be done
4830 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
4831 */
4832 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
4833 {
4834 return (uint32_t)((READ_BIT(ADCx->JSQR,
4835 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
4836 >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
4837 );
4838 }
4839
4840 /**
4841 * @brief Set ADC group injected conversion trigger:
4842 * independent or from ADC group regular.
4843 * @note This mode can be used to extend number of data registers
4844 * updated after one ADC conversion trigger and with data
4845 * permanently kept (not erased by successive conversions of scan of
4846 * ADC sequencer ranks), up to 5 data registers:
4847 * 1 data register on ADC group regular, 4 data registers
4848 * on ADC group injected.
4849 * @note If ADC group injected injected trigger source is set to an
4850 * external trigger, this feature must be must be set to
4851 * independent trigger.
4852 * ADC group injected automatic trigger is compliant only with
4853 * group injected trigger source set to SW start, without any
4854 * further action on ADC group injected conversion start or stop:
4855 * in this case, ADC group injected is controlled only
4856 * from ADC group regular.
4857 * @note It is not possible to enable both ADC group injected
4858 * auto-injected mode and sequencer discontinuous mode.
4859 * @note On this STM32 serie, setting of this feature is conditioned to
4860 * ADC state:
4861 * ADC must be disabled or enabled without conversion on going
4862 * on either groups regular or injected.
4863 * @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto
4864 * @param ADCx ADC instance
4865 * @param TrigAuto This parameter can be one of the following values:
4866 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
4867 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
4868 * @retval None
4869 */
4870 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
4871 {
4872 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
4873 }
4874
4875 /**
4876 * @brief Get ADC group injected conversion trigger:
4877 * independent or from ADC group regular.
4878 * @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto
4879 * @param ADCx ADC instance
4880 * @retval Returned value can be one of the following values:
4881 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
4882 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
4883 */
4884 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
4885 {
4886 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
4887 }
4888
4889 /**
4890 * @brief Set ADC group injected contexts queue mode.
4891 * @note A context is a setting of group injected sequencer:
4892 * - group injected trigger
4893 * - sequencer length
4894 * - sequencer ranks
4895 * If contexts queue is disabled:
4896 * - only 1 sequence can be configured
4897 * and is active perpetually.
4898 * If contexts queue is enabled:
4899 * - up to 2 contexts can be queued
4900 * and are checked in and out as a FIFO stack (first-in, first-out).
4901 * - If a new context is set when queues is full, error is triggered
4902 * by interruption "Injected Queue Overflow".
4903 * - Two behaviors are possible when all contexts have been processed:
4904 * the contexts queue can maintain the last context active perpetually
4905 * or can be empty and injected group triggers are disabled.
4906 * - Triggers can be only external (not internal SW start)
4907 * - Caution: The sequence must be fully configured in one time
4908 * (one write of register JSQR makes a check-in of a new context
4909 * into the queue).
4910 * Therefore functions to set separately injected trigger and
4911 * sequencer channels cannot be used, register JSQR must be set
4912 * using function @ref LL_ADC_INJ_ConfigQueueContext().
4913 * @note This parameter can be modified only when no conversion is on going
4914 * on either groups regular or injected.
4915 * @note A modification of the context mode (bit JQDIS) causes the contexts
4916 * queue to be flushed and the register JSQR is cleared.
4917 * @note On this STM32 serie, setting of this feature is conditioned to
4918 * ADC state:
4919 * ADC must be disabled or enabled without conversion on going
4920 * on either groups regular or injected.
4921 * @rmtoll CFGR JQM LL_ADC_INJ_SetQueueMode\n
4922 * CFGR JQDIS LL_ADC_INJ_SetQueueMode
4923 * @param ADCx ADC instance
4924 * @param QueueMode This parameter can be one of the following values:
4925 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
4926 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
4927 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
4928 * @retval None
4929 */
4930 __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
4931 {
4932 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
4933 }
4934
4935 /**
4936 * @brief Get ADC group injected context queue mode.
4937 * @rmtoll CFGR JQM LL_ADC_INJ_GetQueueMode\n
4938 * CFGR JQDIS LL_ADC_INJ_GetQueueMode
4939 * @param ADCx ADC instance
4940 * @retval Returned value can be one of the following values:
4941 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
4942 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
4943 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
4944 */
4945 __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
4946 {
4947 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
4948 }
4949
4950 /**
4951 * @brief Set one context on ADC group injected that will be checked in
4952 * contexts queue.
4953 * @note A context is a setting of group injected sequencer:
4954 * - group injected trigger
4955 * - sequencer length
4956 * - sequencer ranks
4957 * This function is intended to be used when contexts queue is enabled,
4958 * because the sequence must be fully configured in one time
4959 * (functions to set separately injected trigger and sequencer channels
4960 * cannot be used):
4961 * Refer to function @ref LL_ADC_INJ_SetQueueMode().
4962 * @note In the contexts queue, only the active context can be read.
4963 * The parameters of this function can be read using functions:
4964 * @arg @ref LL_ADC_INJ_GetTriggerSource()
4965 * @arg @ref LL_ADC_INJ_GetTriggerEdge()
4966 * @arg @ref LL_ADC_INJ_GetSequencerRanks()
4967 * @note On this STM32 serie, to measure internal channels (VrefInt,
4968 * TempSensor, ...), measurement paths to internal channels must be
4969 * enabled separately.
4970 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4971 * @note On STM32H7, some fast channels are available: fast analog inputs
4972 * coming from GPIO pads (ADC_IN0..5).
4973 * @note On this STM32 serie, setting of this feature is conditioned to
4974 * ADC state:
4975 * ADC must not be disabled. Can be enabled with or without conversion
4976 * on going on either groups regular or injected.
4977 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n
4978 * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n
4979 * JSQR JL LL_ADC_INJ_ConfigQueueContext\n
4980 * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n
4981 * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n
4982 * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n
4983 * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
4984 * @param ADCx ADC instance
4985 * @param TriggerSource This parameter can be one of the following values:
4986 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
4987 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
4988 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4989 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
4990 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
4991 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
4992 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
4993 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
4994 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
4995 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4996 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
4997 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
4998 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
4999 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
5000 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
5001 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
5002 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
5003 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
5004 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
5005 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT
5006 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT
5007 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT
5008 * @param ExternalTriggerEdge This parameter can be one of the following values:
5009 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
5010 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
5011 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
5012 *
5013 * Note: This parameter is discarded in case of SW start:
5014 * parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
5015 * @param SequencerNbRanks This parameter can be one of the following values:
5016 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
5017 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
5018 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
5019 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
5020 * @param Rank1_Channel This parameter can be one of the following values:
5021 * @arg @ref LL_ADC_CHANNEL_0 (3)
5022 * @arg @ref LL_ADC_CHANNEL_1 (3)
5023 * @arg @ref LL_ADC_CHANNEL_2 (3)
5024 * @arg @ref LL_ADC_CHANNEL_3 (3)
5025 * @arg @ref LL_ADC_CHANNEL_4 (3)
5026 * @arg @ref LL_ADC_CHANNEL_5 (3)
5027 * @arg @ref LL_ADC_CHANNEL_6
5028 * @arg @ref LL_ADC_CHANNEL_7
5029 * @arg @ref LL_ADC_CHANNEL_8
5030 * @arg @ref LL_ADC_CHANNEL_9
5031 * @arg @ref LL_ADC_CHANNEL_10
5032 * @arg @ref LL_ADC_CHANNEL_11
5033 * @arg @ref LL_ADC_CHANNEL_12
5034 * @arg @ref LL_ADC_CHANNEL_13
5035 * @arg @ref LL_ADC_CHANNEL_14
5036 * @arg @ref LL_ADC_CHANNEL_15
5037 * @arg @ref LL_ADC_CHANNEL_16
5038 * @arg @ref LL_ADC_CHANNEL_17
5039 * @arg @ref LL_ADC_CHANNEL_18
5040 * @arg @ref LL_ADC_CHANNEL_19
5041 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
5042 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
5043 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
5044 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
5045 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
5046 *
5047 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
5048 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
5049 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
5050 * Other channels are slow channels (conversion rate: refer to reference manual).
5051 * @param Rank2_Channel This parameter can be one of the following values:
5052 * @arg @ref LL_ADC_CHANNEL_0 (3)
5053 * @arg @ref LL_ADC_CHANNEL_1 (3)
5054 * @arg @ref LL_ADC_CHANNEL_2 (3)
5055 * @arg @ref LL_ADC_CHANNEL_3 (3)
5056 * @arg @ref LL_ADC_CHANNEL_4 (3)
5057 * @arg @ref LL_ADC_CHANNEL_5 (3)
5058 * @arg @ref LL_ADC_CHANNEL_6
5059 * @arg @ref LL_ADC_CHANNEL_7
5060 * @arg @ref LL_ADC_CHANNEL_8
5061 * @arg @ref LL_ADC_CHANNEL_9
5062 * @arg @ref LL_ADC_CHANNEL_10
5063 * @arg @ref LL_ADC_CHANNEL_11
5064 * @arg @ref LL_ADC_CHANNEL_12
5065 * @arg @ref LL_ADC_CHANNEL_13
5066 * @arg @ref LL_ADC_CHANNEL_14
5067 * @arg @ref LL_ADC_CHANNEL_15
5068 * @arg @ref LL_ADC_CHANNEL_16
5069 * @arg @ref LL_ADC_CHANNEL_17
5070 * @arg @ref LL_ADC_CHANNEL_18
5071 * @arg @ref LL_ADC_CHANNEL_19
5072 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
5073 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
5074 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
5075 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
5076 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
5077 *
5078 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
5079 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
5080 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
5081 * Other channels are slow channels (conversion rate: refer to reference manual).
5082 * @param Rank3_Channel This parameter can be one of the following values:
5083 * @arg @ref LL_ADC_CHANNEL_0 (3)
5084 * @arg @ref LL_ADC_CHANNEL_1 (3)
5085 * @arg @ref LL_ADC_CHANNEL_2 (3)
5086 * @arg @ref LL_ADC_CHANNEL_3 (3)
5087 * @arg @ref LL_ADC_CHANNEL_4 (3)
5088 * @arg @ref LL_ADC_CHANNEL_5 (3)
5089 * @arg @ref LL_ADC_CHANNEL_6
5090 * @arg @ref LL_ADC_CHANNEL_7
5091 * @arg @ref LL_ADC_CHANNEL_8
5092 * @arg @ref LL_ADC_CHANNEL_9
5093 * @arg @ref LL_ADC_CHANNEL_10
5094 * @arg @ref LL_ADC_CHANNEL_11
5095 * @arg @ref LL_ADC_CHANNEL_12
5096 * @arg @ref LL_ADC_CHANNEL_13
5097 * @arg @ref LL_ADC_CHANNEL_14
5098 * @arg @ref LL_ADC_CHANNEL_15
5099 * @arg @ref LL_ADC_CHANNEL_16
5100 * @arg @ref LL_ADC_CHANNEL_17
5101 * @arg @ref LL_ADC_CHANNEL_18
5102 * @arg @ref LL_ADC_CHANNEL_19
5103 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
5104 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
5105 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
5106 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
5107 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
5108 *
5109 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
5110 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
5111 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
5112 * Other channels are slow channels (conversion rate: refer to reference manual).
5113 * @param Rank4_Channel This parameter can be one of the following values:
5114 * @arg @ref LL_ADC_CHANNEL_0 (3)
5115 * @arg @ref LL_ADC_CHANNEL_1 (3)
5116 * @arg @ref LL_ADC_CHANNEL_2 (3)
5117 * @arg @ref LL_ADC_CHANNEL_3 (3)
5118 * @arg @ref LL_ADC_CHANNEL_4 (3)
5119 * @arg @ref LL_ADC_CHANNEL_5 (3)
5120 * @arg @ref LL_ADC_CHANNEL_6
5121 * @arg @ref LL_ADC_CHANNEL_7
5122 * @arg @ref LL_ADC_CHANNEL_8
5123 * @arg @ref LL_ADC_CHANNEL_9
5124 * @arg @ref LL_ADC_CHANNEL_10
5125 * @arg @ref LL_ADC_CHANNEL_11
5126 * @arg @ref LL_ADC_CHANNEL_12
5127 * @arg @ref LL_ADC_CHANNEL_13
5128 * @arg @ref LL_ADC_CHANNEL_14
5129 * @arg @ref LL_ADC_CHANNEL_15
5130 * @arg @ref LL_ADC_CHANNEL_16
5131 * @arg @ref LL_ADC_CHANNEL_17
5132 * @arg @ref LL_ADC_CHANNEL_18
5133 * @arg @ref LL_ADC_CHANNEL_19
5134 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
5135 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
5136 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
5137 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
5138 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
5139 *
5140 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
5141 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
5142 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
5143 * Other channels are slow channels (conversion rate: refer to reference manual).
5144 * @retval None
5145 */
5146 __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
5147 uint32_t TriggerSource,
5148 uint32_t ExternalTriggerEdge,
5149 uint32_t SequencerNbRanks,
5150 uint32_t Rank1_Channel,
5151 uint32_t Rank2_Channel,
5152 uint32_t Rank3_Channel,
5153 uint32_t Rank4_Channel)
5154 {
5155 /* Set bits with content of parameter "Rankx_Channel" with bits position */
5156 /* in register depending on literal "LL_ADC_INJ_RANK_x". */
5157 /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */
5158 /* because containing other bits reserved for other purpose. */
5159 /* If parameter "TriggerSource" is set to SW start, then parameter */
5160 /* "ExternalTriggerEdge" is discarded. */
5161 uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
5162 MODIFY_REG(ADCx->JSQR,
5163 ADC_JSQR_JEXTSEL |
5164 ADC_JSQR_JEXTEN |
5165 ADC_JSQR_JSQ4 |
5166 ADC_JSQR_JSQ3 |
5167 ADC_JSQR_JSQ2 |
5168 ADC_JSQR_JSQ1 |
5169 ADC_JSQR_JL,
5170 (TriggerSource & ADC_JSQR_JEXTSEL) |
5171 (ExternalTriggerEdge * (is_trigger_not_sw)) |
5172 (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5173 (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5174 (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5175 (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5176 SequencerNbRanks
5177 );
5178 }
5179
5180 /**
5181 * @}
5182 */
5183
5184 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
5185 * @{
5186 */
5187
5188 /**
5189 * @brief Set sampling time of the selected ADC channel
5190 * Unit: ADC clock cycles.
5191 * @note On this device, sampling time is on channel scope: independently
5192 * of channel mapped on ADC group regular or injected.
5193 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
5194 * converted:
5195 * sampling time constraints must be respected (sampling time can be
5196 * adjusted in function of ADC clock frequency and sampling time
5197 * setting).
5198 * Refer to device datasheet for timings values (parameters TS_vrefint,
5199 * TS_temp, ...).
5200 * @note Conversion time is the addition of sampling time and processing time.
5201 * On this STM32 serie, ADC processing time is:
5202 * - 12.5 ADC clock cycles at ADC resolution 12 bits
5203 * - 10.5 ADC clock cycles at ADC resolution 10 bits
5204 * - 8.5 ADC clock cycles at ADC resolution 8 bits
5205 * - 6.5 ADC clock cycles at ADC resolution 6 bits
5206 * @note In case of ADC conversion of internal channel (VrefInt,
5207 * temperature sensor, ...), a sampling time minimum value
5208 * is required.
5209 * Refer to device datasheet.
5210 * @note On this STM32 serie, setting of this feature is conditioned to
5211 * ADC state:
5212 * ADC must be disabled or enabled without conversion on going
5213 * on either groups regular or injected.
5214 * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n
5215 * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n
5216 * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n
5217 * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n
5218 * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n
5219 * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n
5220 * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n
5221 * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n
5222 * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n
5223 * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n
5224 * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n
5225 * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n
5226 * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n
5227 * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n
5228 * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n
5229 * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n
5230 * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n
5231 * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n
5232 * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
5233 * @param ADCx ADC instance
5234 * @param Channel This parameter can be one of the following values:
5235 * @arg @ref LL_ADC_CHANNEL_0 (3)
5236 * @arg @ref LL_ADC_CHANNEL_1 (3)
5237 * @arg @ref LL_ADC_CHANNEL_2 (3)
5238 * @arg @ref LL_ADC_CHANNEL_3 (3)
5239 * @arg @ref LL_ADC_CHANNEL_4 (3)
5240 * @arg @ref LL_ADC_CHANNEL_5 (3)
5241 * @arg @ref LL_ADC_CHANNEL_6
5242 * @arg @ref LL_ADC_CHANNEL_7
5243 * @arg @ref LL_ADC_CHANNEL_8
5244 * @arg @ref LL_ADC_CHANNEL_9
5245 * @arg @ref LL_ADC_CHANNEL_10
5246 * @arg @ref LL_ADC_CHANNEL_11
5247 * @arg @ref LL_ADC_CHANNEL_12
5248 * @arg @ref LL_ADC_CHANNEL_13
5249 * @arg @ref LL_ADC_CHANNEL_14
5250 * @arg @ref LL_ADC_CHANNEL_15
5251 * @arg @ref LL_ADC_CHANNEL_16
5252 * @arg @ref LL_ADC_CHANNEL_17
5253 * @arg @ref LL_ADC_CHANNEL_18
5254 * @arg @ref LL_ADC_CHANNEL_19
5255 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
5256 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
5257 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
5258 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
5259 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
5260 *
5261 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
5262 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
5263 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
5264 * Other channels are slow channels (conversion rate: refer to reference manual).
5265 * @param SamplingTime This parameter can be one of the following values:
5266 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
5267 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
5268 * @arg @ref LL_ADC_SAMPLINGTIME_8CYCLES_5
5269 * @arg @ref LL_ADC_SAMPLINGTIME_16CYCLES_5
5270 * @arg @ref LL_ADC_SAMPLINGTIME_32CYCLES_5
5271 * @arg @ref LL_ADC_SAMPLINGTIME_64CYCLES_5
5272 * @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5
5273 * @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5
5274 * @retval None
5275 */
5276 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
5277 {
5278 /* Set bits with content of parameter "SamplingTime" with bits position */
5279 /* in register and register position depending on parameter "Channel". */
5280 /* Parameter "Channel" is used with masks because containing */
5281 /* other bits reserved for other purpose. */
5282 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
5283
5284 MODIFY_REG(*preg,
5285 ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
5286 SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
5287 }
5288
5289 /**
5290 * @brief Get sampling time of the selected ADC channel
5291 * Unit: ADC clock cycles.
5292 * @note On this device, sampling time is on channel scope: independently
5293 * of channel mapped on ADC group regular or injected.
5294 * @note Conversion time is the addition of sampling time and processing time.
5295 * On this STM32 serie, ADC processing time is:
5296 * - 12.5 ADC clock cycles at ADC resolution 12 bits
5297 * - 10.5 ADC clock cycles at ADC resolution 10 bits
5298 * - 8.5 ADC clock cycles at ADC resolution 8 bits
5299 * - 6.5 ADC clock cycles at ADC resolution 6 bits
5300 * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n
5301 * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n
5302 * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n
5303 * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n
5304 * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n
5305 * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n
5306 * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n
5307 * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n
5308 * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n
5309 * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n
5310 * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n
5311 * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n
5312 * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n
5313 * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n
5314 * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n
5315 * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n
5316 * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n
5317 * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n
5318 * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
5319 * @param ADCx ADC instance
5320 * @param Channel This parameter can be one of the following values:
5321 * @arg @ref LL_ADC_CHANNEL_0 (3)
5322 * @arg @ref LL_ADC_CHANNEL_1 (3)
5323 * @arg @ref LL_ADC_CHANNEL_2 (3)
5324 * @arg @ref LL_ADC_CHANNEL_3 (3)
5325 * @arg @ref LL_ADC_CHANNEL_4 (3)
5326 * @arg @ref LL_ADC_CHANNEL_5 (3)
5327 * @arg @ref LL_ADC_CHANNEL_6
5328 * @arg @ref LL_ADC_CHANNEL_7
5329 * @arg @ref LL_ADC_CHANNEL_8
5330 * @arg @ref LL_ADC_CHANNEL_9
5331 * @arg @ref LL_ADC_CHANNEL_10
5332 * @arg @ref LL_ADC_CHANNEL_11
5333 * @arg @ref LL_ADC_CHANNEL_12
5334 * @arg @ref LL_ADC_CHANNEL_13
5335 * @arg @ref LL_ADC_CHANNEL_14
5336 * @arg @ref LL_ADC_CHANNEL_15
5337 * @arg @ref LL_ADC_CHANNEL_16
5338 * @arg @ref LL_ADC_CHANNEL_17
5339 * @arg @ref LL_ADC_CHANNEL_18
5340 * @arg @ref LL_ADC_CHANNEL_19
5341 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
5342 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
5343 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
5344 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
5345 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
5346 *
5347 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
5348 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
5349 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
5350 * Other channels are slow channels (conversion rate: refer to reference manual).
5351 * @retval Returned value can be one of the following values:
5352 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
5353 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
5354 * @arg @ref LL_ADC_SAMPLINGTIME_8CYCLES_5
5355 * @arg @ref LL_ADC_SAMPLINGTIME_16CYCLES_5
5356 * @arg @ref LL_ADC_SAMPLINGTIME_32CYCLES_5
5357 * @arg @ref LL_ADC_SAMPLINGTIME_64CYCLES_5
5358 * @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5
5359 * @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5
5360 */
5361 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
5362 {
5363 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
5364
5365 return (uint32_t)(READ_BIT(*preg,
5366 ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
5367 >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)
5368 );
5369 }
5370
5371 /**
5372 * @brief Set mode single-ended or differential input of the selected
5373 * ADC channel.
5374 * @note Channel ending is on channel scope: independently of channel mapped
5375 * on ADC group regular or injected.
5376 * In differential mode: Differential measurement is carried out
5377 * between the selected channel 'i' (positive input) and
5378 * channel 'i+1' (negative input). Only channel 'i' has to be
5379 * configured, channel 'i+1' is configured automatically.
5380 * @note Refer to Reference Manual to ensure the selected channel is
5381 * available in differential mode.
5382 * For example, internal channels (VrefInt, TempSensor, ...) are
5383 * not available in differential mode.
5384 * @note When configuring a channel 'i' in differential mode,
5385 * the channel 'i+1' is not usable separately.
5386 * @note On STM32H7, some channels are internally fixed to single-ended inputs
5387 * configuration:
5388 * - ADC1: Channels 0, 6, 7, 8, 9, 13, 14, 15, 17, and 19
5389 * - ADC2: Channels 0, 6, 7, 8, 9, 13, 14, 15 and 19
5390 * - ADC3: Channels 0, 6, 7, 8, 9, 12, 16, 17, and 19
5391 * @note For ADC channels configured in differential mode, both inputs
5392 * should be biased at (Vref+)/2 +/-200mV.
5393 * (Vref+ is the analog voltage reference)
5394 * @note On this STM32 serie, setting of this feature is conditioned to
5395 * ADC state:
5396 * ADC must be ADC disabled.
5397 * @note One or several values can be selected.
5398 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
5399 * @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff
5400 * @param ADCx ADC instance
5401 * @param Channel This parameter can be one of the following values:
5402 * @arg @ref LL_ADC_CHANNEL_1
5403 * @arg @ref LL_ADC_CHANNEL_2
5404 * @arg @ref LL_ADC_CHANNEL_3
5405 * @arg @ref LL_ADC_CHANNEL_4
5406 * @arg @ref LL_ADC_CHANNEL_5
5407 * @arg @ref LL_ADC_CHANNEL_10
5408 * @arg @ref LL_ADC_CHANNEL_11
5409 * @arg @ref LL_ADC_CHANNEL_12
5410 * @arg @ref LL_ADC_CHANNEL_13
5411 * @arg @ref LL_ADC_CHANNEL_14
5412 * @arg @ref LL_ADC_CHANNEL_15
5413 * @arg @ref LL_ADC_CHANNEL_16
5414 * @arg @ref LL_ADC_CHANNEL_17
5415 * @arg @ref LL_ADC_CHANNEL_18
5416 * @arg @ref LL_ADC_CHANNEL_19
5417 * @param SingleDiff This parameter can be a combination of the following values:
5418 * @arg @ref LL_ADC_SINGLE_ENDED
5419 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
5420 * @retval None
5421 */
5422 __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
5423 {
5424 #if defined(ADC_VER_V5_V90)
5425 /* Bits of channels in single or differential mode are set only for */
5426 /* differential mode (for single mode, mask of bits allowed to be set is */
5427 /* shifted out of range of bits of channels in single or differential mode. */
5428 if (ADCx == ADC3)
5429 {
5430 MODIFY_REG(ADCx->LTR2_DIFSEL,
5431 Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
5432 (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
5433 }
5434 else
5435 {
5436 MODIFY_REG(ADCx->DIFSEL_RES12,
5437 Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
5438 (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
5439 }
5440 #else /* ADC_VER_V5_V90 */
5441 /* Bits of channels in single or differential mode are set only for */
5442 /* differential mode (for single mode, mask of bits allowed to be set is */
5443 /* shifted out of range of bits of channels in single or differential mode. */
5444 MODIFY_REG(ADCx->DIFSEL,
5445 Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
5446 (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
5447 #endif
5448 }
5449
5450 /**
5451 * @brief Get mode single-ended or differential input of the selected
5452 * ADC channel.
5453 * @note When configuring a channel 'i' in differential mode,
5454 * the channel 'i+1' is not usable separately.
5455 * Therefore, to ensure a channel is configured in single-ended mode,
5456 * the configuration of channel itself and the channel 'i-1' must be
5457 * read back (to ensure that the selected channel channel has not been
5458 * configured in differential mode by the previous channel).
5459 * @note Refer to Reference Manual to ensure the selected channel is
5460 * available in differential mode.
5461 * For example, internal channels (VrefInt, TempSensor, ...) are
5462 * not available in differential mode.
5463 * @note When configuring a channel 'i' in differential mode,
5464 * the channel 'i+1' is not usable separately.
5465 * @note On STM32H7, some channels are internally fixed to single-ended inputs
5466 * configuration:
5467 * - ADC1: Channels 0, 6, 7, 8, 9, 13, 14, 15, 17, and 19
5468 * - ADC2: Channels 0, 6, 7, 8, 9, 13, 14, 15 and 19
5469 * - ADC3: Channels 0, 6, 7, 8, 9, 12, 16, 17, and 19
5470 * @note One or several values can be selected. In this case, the value
5471 * returned is null if all channels are in single ended-mode.
5472 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
5473 * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff
5474 * @param ADCx ADC instance
5475 * @param Channel This parameter can be a combination of the following values:
5476 * @arg @ref LL_ADC_CHANNEL_1
5477 * @arg @ref LL_ADC_CHANNEL_2
5478 * @arg @ref LL_ADC_CHANNEL_3
5479 * @arg @ref LL_ADC_CHANNEL_4
5480 * @arg @ref LL_ADC_CHANNEL_5
5481 * @arg @ref LL_ADC_CHANNEL_10
5482 * @arg @ref LL_ADC_CHANNEL_11
5483 * @arg @ref LL_ADC_CHANNEL_12
5484 * @arg @ref LL_ADC_CHANNEL_13
5485 * @arg @ref LL_ADC_CHANNEL_14
5486 * @arg @ref LL_ADC_CHANNEL_15
5487 * @arg @ref LL_ADC_CHANNEL_16
5488 * @arg @ref LL_ADC_CHANNEL_17
5489 * @arg @ref LL_ADC_CHANNEL_18
5490 * @arg @ref LL_ADC_CHANNEL_19
5491 * @retval 0: channel in single-ended mode, else: channel in differential mode
5492 */
5493 __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
5494 {
5495 #if defined(ADC_VER_V5_V90)
5496 return (uint32_t)(READ_BIT(ADCx->DIFSEL_RES12, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
5497 #else
5498 return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
5499 #endif
5500 }
5501
5502 /**
5503 * @}
5504 */
5505
5506 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
5507 * @{
5508 */
5509
5510 /**
5511 * @brief Set ADC analog watchdog monitored channels:
5512 * a single channel, multiple channels or all channels,
5513 * on ADC groups regular and-or injected.
5514 * @note Once monitored channels are selected, analog watchdog
5515 * is enabled.
5516 * @note In case of need to define a single channel to monitor
5517 * with analog watchdog from sequencer channel definition,
5518 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
5519 * @note On this STM32 serie, there are 2 kinds of analog watchdog
5520 * instance:
5521 * - AWD standard (instance AWD1):
5522 * - channels monitored: can monitor 1 channel or all channels.
5523 * - groups monitored: ADC groups regular and-or injected.
5524 * - resolution: resolution is not limited (corresponds to
5525 * ADC resolution configured).
5526 * - AWD flexible (instances AWD2, AWD3):
5527 * - channels monitored: flexible on channels monitored, selection is
5528 * channel wise, from from 1 to all channels.
5529 * Specificity of this analog watchdog: Multiple channels can
5530 * be selected. For example:
5531 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5532 * - groups monitored: not selection possible (monitoring on both
5533 * groups regular and injected).
5534 * Channels selected are monitored on groups regular and injected:
5535 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5536 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5537 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5538 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5539 * the 2 LSB are ignored.
5540 * @note On this STM32 serie, setting of this feature is conditioned to
5541 * ADC state:
5542 * ADC must be disabled or enabled without conversion on going
5543 * on either groups regular or injected.
5544 * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
5545 * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
5546 * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
5547 * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n
5548 * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
5549 * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
5550 * @param ADCx ADC instance
5551 * @param AWDy This parameter can be one of the following values:
5552 * @arg @ref LL_ADC_AWD1
5553 * @arg @ref LL_ADC_AWD2
5554 * @arg @ref LL_ADC_AWD3
5555 * @param AWDChannelGroup This parameter can be one of the following values:
5556 * @arg @ref LL_ADC_AWD_DISABLE
5557 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
5558 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
5559 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
5560 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
5561 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
5562 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
5563 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
5564 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
5565 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
5566 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
5567 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
5568 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
5569 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
5570 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
5571 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
5572 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
5573 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
5574 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
5575 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
5576 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
5577 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
5578 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
5579 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
5580 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
5581 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
5582 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
5583 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
5584 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
5585 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
5586 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
5587 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
5588 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
5589 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
5590 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
5591 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
5592 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
5593 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
5594 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
5595 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
5596 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
5597 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
5598 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
5599 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
5600 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
5601 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
5602 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
5603 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
5604 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
5605 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
5606 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
5607 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
5608 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
5609 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
5610 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
5611 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
5612 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
5613 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
5614 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
5615 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
5616 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
5617 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)
5618 * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)
5619 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
5620 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
5621 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
5622 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
5623 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)
5624 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
5625 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
5626 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1)
5627 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
5628 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
5629 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(2)
5630 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(2)
5631 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (2)
5632 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(2)
5633 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(2)
5634 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (2)
5635 *
5636 * (0) On STM32H7, parameter available only on analog watchdog number: AWD1.\n
5637 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
5638 * (2) On STM32H7, parameter available only on ADC instance: ADC2.
5639 * @retval None
5640 */
5641 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
5642 {
5643 /* Set bits with content of parameter "AWDChannelGroup" with bits position */
5644 /* in register and register position depending on parameter "AWDy". */
5645 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
5646 /* containing other bits reserved for other purpose. */
5647 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
5648 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5649
5650 MODIFY_REG(*preg,
5651 (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
5652 AWDChannelGroup & AWDy);
5653 }
5654
5655 /**
5656 * @brief Get ADC analog watchdog monitored channel.
5657 * @note Usage of the returned channel number:
5658 * - To reinject this channel into another function LL_ADC_xxx:
5659 * the returned channel number is only partly formatted on definition
5660 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
5661 * with parts of literals LL_ADC_CHANNEL_x or using
5662 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5663 * Then the selected literal LL_ADC_CHANNEL_x can be used
5664 * as parameter for another function.
5665 * - To get the channel number in decimal format:
5666 * process the returned value with the helper macro
5667 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5668 * Applicable only when the analog watchdog is set to monitor
5669 * one channel.
5670 * @note On this STM32 serie, there are 2 kinds of analog watchdog
5671 * instance:
5672 * - AWD standard (instance AWD1):
5673 * - channels monitored: can monitor 1 channel or all channels.
5674 * - groups monitored: ADC groups regular and-or injected.
5675 * - resolution: resolution is not limited (corresponds to
5676 * ADC resolution configured).
5677 * - AWD flexible (instances AWD2, AWD3):
5678 * - channels monitored: flexible on channels monitored, selection is
5679 * channel wise, from from 1 to all channels.
5680 * Specificity of this analog watchdog: Multiple channels can
5681 * be selected. For example:
5682 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5683 * - groups monitored: not selection possible (monitoring on both
5684 * groups regular and injected).
5685 * Channels selected are monitored on groups regular and injected:
5686 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5687 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5688 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5689 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5690 * the 2 LSB are ignored.
5691 * @note On this STM32 serie, setting of this feature is conditioned to
5692 * ADC state:
5693 * ADC must be disabled or enabled without conversion on going
5694 * on either groups regular or injected.
5695 * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
5696 * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
5697 * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
5698 * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n
5699 * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
5700 * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
5701 * @param ADCx ADC instance
5702 * @param AWDy This parameter can be one of the following values:
5703 * @arg @ref LL_ADC_AWD1
5704 * @arg @ref LL_ADC_AWD2 (1)
5705 * @arg @ref LL_ADC_AWD3 (1)
5706 *
5707 * (1) On this AWD number, monitored channel can be retrieved
5708 * if only 1 channel is programmed (or none or all channels).
5709 * This function cannot retrieve monitored channel if
5710 * multiple channels are programmed simultaneously
5711 * by bitfield.
5712 * @retval Returned value can be one of the following values:
5713 * @arg @ref LL_ADC_AWD_DISABLE
5714 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
5715 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
5716 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
5717 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
5718 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
5719 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
5720 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
5721 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
5722 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
5723 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
5724 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
5725 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
5726 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
5727 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
5728 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
5729 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
5730 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
5731 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
5732 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
5733 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
5734 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
5735 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
5736 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
5737 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
5738 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
5739 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
5740 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
5741 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
5742 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
5743 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
5744 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
5745 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
5746 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
5747 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
5748 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
5749 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
5750 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
5751 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
5752 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
5753 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
5754 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
5755 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
5756 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
5757 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
5758 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
5759 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
5760 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
5761 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
5762 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
5763 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
5764 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
5765 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
5766 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
5767 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
5768 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
5769 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
5770 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
5771 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
5772 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
5773 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
5774 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)
5775 * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)
5776 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
5777 *
5778 * (0) On STM32H7, parameter available only on analog watchdog number: AWD1.
5779 */
5780 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
5781 {
5782 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
5783 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5784
5785 uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
5786
5787 /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */
5788 /* (parameter value LL_ADC_AWD_DISABLE). */
5789 /* Else, the selected AWD is enabled and is monitoring a group of channels */
5790 /* or a single channel. */
5791 if (AnalogWDMonitChannels != 0UL)
5792 {
5793 if (AWDy == LL_ADC_AWD1)
5794 {
5795 if ((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL)
5796 {
5797 /* AWD monitoring a group of channels */
5798 AnalogWDMonitChannels = ((AnalogWDMonitChannels
5799 | (ADC_AWD_CR23_CHANNEL_MASK)
5800 )
5801 & (~(ADC_CFGR_AWD1CH))
5802 );
5803 }
5804 else
5805 {
5806 /* AWD monitoring a single channel */
5807 AnalogWDMonitChannels = (AnalogWDMonitChannels
5808 | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1CH_Pos))
5809 );
5810 }
5811 }
5812 else
5813 {
5814 if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
5815 {
5816 /* AWD monitoring a group of channels */
5817 AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK
5818 | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))
5819 );
5820 }
5821 else
5822 {
5823 /* AWD monitoring a single channel */
5824 /* AWD monitoring a group of channels */
5825 AnalogWDMonitChannels = (AnalogWDMonitChannels
5826 | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
5827 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos)
5828 );
5829 }
5830 }
5831 }
5832
5833 return AnalogWDMonitChannels;
5834 }
5835
5836 /**
5837 * @brief Set ADC analog watchdog threshold value of threshold
5838 * high or low.
5839 * @note In case of ADC resolution different of 12 bits,
5840 * analog watchdog thresholds data require a specific shift.
5841 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
5842 * @note On this STM32 serie, there are 2 kinds of analog watchdog
5843 * instance:
5844 * - AWD standard (instance AWD1):
5845 * - channels monitored: can monitor 1 channel or all channels.
5846 * - groups monitored: ADC groups regular and-or injected.
5847 * - resolution: resolution is not limited (corresponds to
5848 * ADC resolution configured).
5849 * - AWD flexible (instances AWD2, AWD3):
5850 * - channels monitored: flexible on channels monitored, selection is
5851 * channel wise, from from 1 to all channels.
5852 * Specificity of this analog watchdog: Multiple channels can
5853 * be selected. For example:
5854 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5855 * - groups monitored: not selection possible (monitoring on both
5856 * groups regular and injected).
5857 * Channels selected are monitored on groups regular and injected:
5858 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5859 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5860 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5861 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5862 * the 2 LSB are ignored.
5863 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
5864 * impacted: the comparison of analog watchdog thresholds is done
5865 * on oversampling intermediate computation (after ratio, before shift
5866 * application): intermediate register bitfield [32:7]
5867 * (26 most significant bits).
5868 * @note On this STM32 serie, setting of this feature is conditioned to
5869 * ADC state:
5870 * ADC must be disabled or enabled without conversion on going
5871 * on either ADC groups regular or injected.
5872 * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n
5873 * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n
5874 * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n
5875 * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n
5876 * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n
5877 * TR3 LT3 LL_ADC_SetAnalogWDThresholds
5878 * @param ADCx ADC instance
5879 * @param AWDy This parameter can be one of the following values:
5880 * @arg @ref LL_ADC_AWD1
5881 * @arg @ref LL_ADC_AWD2
5882 * @arg @ref LL_ADC_AWD3
5883 * @param AWDThresholdsHighLow This parameter can be one of the following values:
5884 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
5885 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
5886 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
5887 * @retval None
5888 */
5889 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
5890 {
5891 #if defined(ADC_VER_V5_V90)
5892 if (ADCx == ADC3)
5893 {
5894 /* Set bits with content of parameter "AWDThresholdValue" with bits */
5895 /* position in register and register position depending on parameters */
5896 /* "AWDThresholdsHighLow" and "AWDy". */
5897 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
5898 /* containing other bits reserved for other purpose. */
5899 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
5900
5901 MODIFY_REG(*preg,
5902 AWDThresholdsHighLow,
5903 AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
5904 }
5905 else
5906 {
5907 /* Set bits with content of parameter "AWDThresholdValue" with bits */
5908 /* position in register and register position depending on parameters */
5909 /* "AWDThresholdsHighLow" and "AWDy". */
5910 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
5911 /* containing other bits reserved for other purpose. */
5912 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
5913 + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
5914 + (AWDThresholdsHighLow));
5915
5916 MODIFY_REG(*preg, ADC_LTR_LT, AWDThresholdValue);
5917 }
5918 #else
5919 /* Set bits with content of parameter "AWDThresholdValue" with bits */
5920 /* position in register and register position depending on parameters */
5921 /* "AWDThresholdsHighLow" and "AWDy". */
5922 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
5923 /* containing other bits reserved for other purpose. */
5924 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
5925 + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
5926 + (AWDThresholdsHighLow));
5927
5928 MODIFY_REG(*preg, ADC_LTR_LT, AWDThresholdValue);
5929 #endif /* ADC_VER_V5_V90 */
5930 }
5931
5932 /**
5933 * @brief Get ADC analog watchdog threshold value of threshold high,
5934 * threshold low or raw data with ADC thresholds high and low
5935 * concatenated.
5936 * @note In case of ADC resolution different of 12 bits,
5937 * analog watchdog thresholds data require a specific shift.
5938 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
5939 * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n
5940 * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n
5941 * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n
5942 * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n
5943 * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n
5944 * TR3 LT3 LL_ADC_GetAnalogWDThresholds
5945 * @param ADCx ADC instance
5946 * @param AWDy This parameter can be one of the following values:
5947 * @arg @ref LL_ADC_AWD1
5948 * @arg @ref LL_ADC_AWD2
5949 * @arg @ref LL_ADC_AWD3
5950 * @param AWDThresholdsHighLow This parameter can be one of the following values:
5951 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
5952 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
5953 * @retval Value between Min_Data=0x000 and Max_Data=0x3FFFFFF
5954 */
5955 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
5956 {
5957 #if defined(ADC_VER_V5_V90)
5958 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
5959 + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
5960 + (AWDThresholdsHighLow));
5961
5962 return (uint32_t)(READ_BIT(*preg, ADC_LTR_LT));
5963 #else
5964 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
5965 + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
5966 + (AWDThresholdsHighLow));
5967
5968 return (uint32_t)(READ_BIT(*preg, ADC_LTR_LT));
5969 #endif
5970 }
5971
5972 #if defined(ADC_VER_V5_V90)
5973
5974 /**
5975 * @brief Set ADC analog watchdog thresholds value of both thresholds
5976 * high and low. Applicable for devices STM32H72xx and STM32H73xx.
5977 * @note If value of only one threshold high or low must be set,
5978 * use function @ref LL_ADC_SetAnalogWDThresholds().
5979 * @note In case of ADC resolution different of 12 bits,
5980 * analog watchdog thresholds data require a specific shift.
5981 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
5982 * @note On this STM32 serie, there are 2 kinds of analog watchdog
5983 * instance:
5984 * - AWD standard (instance AWD1):
5985 * - channels monitored: can monitor 1 channel or all channels.
5986 * - groups monitored: ADC groups regular and-or injected.
5987 * - resolution: resolution is not limited (corresponds to
5988 * ADC resolution configured).
5989 * - AWD flexible (instances AWD2, AWD3):
5990 * - channels monitored: flexible on channels monitored, selection is
5991 * channel wise, from from 1 to all channels.
5992 * Specificity of this analog watchdog: Multiple channels can
5993 * be selected. For example:
5994 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5995 * - groups monitored: not selection possible (monitoring on both
5996 * groups regular and injected).
5997 * Channels selected are monitored on groups regular and injected:
5998 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5999 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
6000 * - resolution: resolution is limited to 8 bits: if ADC resolution is
6001 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
6002 * the 2 LSB are ignored.
6003 * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n
6004 * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n
6005 * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n
6006 * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n
6007 * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n
6008 * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds
6009 * @param ADCx ADC instance
6010 * @param AWDy This parameter can be one of the following values:
6011 * @arg @ref LL_ADC_AWD1
6012 * @arg @ref LL_ADC_AWD2
6013 * @arg @ref LL_ADC_AWD3
6014 * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
6015 * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
6016 * @retval None
6017 */
6018 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
6019 {
6020 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
6021 /* position in register and register position depending on parameter */
6022 /* "AWDy". */
6023 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
6024 /* containing other bits reserved for other purpose. */
6025 if (ADCx == ADC3)
6026 {
6027 uint32_t __IO *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
6028
6029 MODIFY_REG(*preg,
6030 ADC3_TR1_HT1 | ADC3_TR1_LT1,
6031 (AWDThresholdHighValue << ADC3_TR1_HT1_Pos) | AWDThresholdLowValue);
6032 }
6033 else
6034 {
6035 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
6036 + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
6037 + (LL_ADC_AWD_THRESHOLD_LOW));
6038 __IO uint32_t *preg2 = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
6039 + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
6040 + (LL_ADC_AWD_THRESHOLD_HIGH));
6041
6042 MODIFY_REG(*preg, ADC_LTR_LT, AWDThresholdLowValue);
6043 MODIFY_REG(*preg2, ADC_HTR_HT, AWDThresholdHighValue);
6044 }
6045 }
6046
6047
6048 /**
6049 * @brief Set ADC analog watchdog filtering configuration
6050 * @note On this STM32 serie, setting of this feature is conditioned to
6051 * ADC state:
6052 * ADC must be disabled or enabled without conversion on going
6053 * on either groups regular or injected.
6054 * Applicable on ADC3 of devices STM32H72xx and STM32H73xx.
6055 * @note On this STM32 serie, this feature is only available on first
6056 * analog watchdog (AWD1)
6057 * @rmtoll TR1 AWDFILT LL_ADC_SetAWDFilteringConfiguration
6058 * @param ADCx ADC instance
6059 * @param AWDy This parameter can be one of the following values:
6060 * @arg @ref LL_ADC_AWD1
6061 * @param FilteringConfig This parameter can be one of the following values:
6062 * @arg @ref LL_ADC_AWD_FILTERING_NONE
6063 * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
6064 * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
6065 * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
6066 * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
6067 * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
6068 * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
6069 * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
6070 * @retval None
6071 */
6072 __STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t FilteringConfig)
6073 {
6074 if (ADCx == ADC3)
6075 {
6076 /* Prevent unused argument(s) compilation warning */
6077 (void)(AWDy);
6078 MODIFY_REG(ADCx->LTR1_TR1, ADC3_TR1_AWDFILT, FilteringConfig);
6079 }
6080 }
6081
6082 /**
6083 * @brief Get ADC analog watchdog filtering configuration
6084 * @note On this STM32 serie, this feature is only available on first
6085 * analog watchdog (AWD1)
6086 * Applicable on ADC3 of devices STM32H72xx and STM32H73xx.
6087 * @rmtoll TR1 AWDFILT LL_ADC_GetAWDFilteringConfiguration
6088 * @param ADCx ADC instance
6089 * @param AWDy This parameter can be one of the following values:
6090 * @arg @ref LL_ADC_AWD1
6091 * @retval Returned value can be:
6092 * @arg @ref LL_ADC_AWD_FILTERING_NONE
6093 * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
6094 * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
6095 * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
6096 * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
6097 * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
6098 * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
6099 * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
6100 */
6101 __STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy)
6102 {
6103 if (ADCx == ADC3)
6104 {
6105 /* Prevent unused argument(s) compilation warning */
6106 (void)(AWDy);
6107 return (uint32_t)(READ_BIT(ADCx->LTR1_TR1, ADC3_TR1_AWDFILT));
6108 }
6109 else
6110 {
6111 /* Function not available on this instance, return 0 */
6112 return 0UL;
6113 }
6114 }
6115 #endif /* ADC_VER_V5_V90 */
6116 /**
6117 * @}
6118 */
6119
6120 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
6121 * @{
6122 */
6123
6124 /**
6125 * @brief Set ADC oversampling scope: ADC groups regular and-or injected
6126 * (availability of ADC group injected depends on STM32 families).
6127 * @note If both groups regular and injected are selected,
6128 * specify behavior of ADC group injected interrupting
6129 * group regular: when ADC group injected is triggered,
6130 * the oversampling on ADC group regular is either
6131 * temporary stopped and continued, or resumed from start
6132 * (oversampler buffer reset).
6133 * @note On this STM32 serie, setting of this feature is conditioned to
6134 * ADC state:
6135 * ADC must be disabled or enabled without conversion on going
6136 * on either groups regular or injected.
6137 * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope\n
6138 * CFGR2 JOVSE LL_ADC_SetOverSamplingScope\n
6139 * CFGR2 ROVSM LL_ADC_SetOverSamplingScope
6140 * @param ADCx ADC instance
6141 * @param OvsScope This parameter can be one of the following values:
6142 * @arg @ref LL_ADC_OVS_DISABLE
6143 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
6144 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
6145 * @arg @ref LL_ADC_OVS_GRP_INJECTED
6146 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
6147 * @retval None
6148 */
6149 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
6150 {
6151 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
6152 }
6153
6154 /**
6155 * @brief Get ADC oversampling scope: ADC groups regular and-or injected
6156 * (availability of ADC group injected depends on STM32 families).
6157 * @note If both groups regular and injected are selected,
6158 * specify behavior of ADC group injected interrupting
6159 * group regular: when ADC group injected is triggered,
6160 * the oversampling on ADC group regular is either
6161 * temporary stopped and continued, or resumed from start
6162 * (oversampler buffer reset).
6163 * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope\n
6164 * CFGR2 JOVSE LL_ADC_GetOverSamplingScope\n
6165 * CFGR2 ROVSM LL_ADC_GetOverSamplingScope
6166 * @param ADCx ADC instance
6167 * @retval Returned value can be one of the following values:
6168 * @arg @ref LL_ADC_OVS_DISABLE
6169 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
6170 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
6171 * @arg @ref LL_ADC_OVS_GRP_INJECTED
6172 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
6173 */
6174 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
6175 {
6176 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
6177 }
6178
6179 /**
6180 * @brief Set ADC oversampling discontinuous mode (triggered mode)
6181 * on the selected ADC group.
6182 * @note Number of oversampled conversions are done either in:
6183 * - continuous mode (all conversions of oversampling ratio
6184 * are done from 1 trigger)
6185 * - discontinuous mode (each conversion of oversampling ratio
6186 * needs a trigger)
6187 * @note On this STM32 serie, setting of this feature is conditioned to
6188 * ADC state:
6189 * ADC must be disabled or enabled without conversion on going
6190 * on group regular.
6191 * @note On this STM32 serie, oversampling discontinuous mode
6192 * (triggered mode) can be used only when oversampling is
6193 * set on group regular only and in resumed mode.
6194 * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
6195 * @param ADCx ADC instance
6196 * @param OverSamplingDiscont This parameter can be one of the following values:
6197 * @arg @ref LL_ADC_OVS_REG_CONT
6198 * @arg @ref LL_ADC_OVS_REG_DISCONT
6199 * @retval None
6200 */
6201 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
6202 {
6203 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
6204 }
6205
6206 /**
6207 * @brief Get ADC oversampling discontinuous mode (triggered mode)
6208 * on the selected ADC group.
6209 * @note Number of oversampled conversions are done either in:
6210 * - continuous mode (all conversions of oversampling ratio
6211 * are done from 1 trigger)
6212 * - discontinuous mode (each conversion of oversampling ratio
6213 * needs a trigger)
6214 * @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont
6215 * @param ADCx ADC instance
6216 * @retval Returned value can be one of the following values:
6217 * @arg @ref LL_ADC_OVS_REG_CONT
6218 * @arg @ref LL_ADC_OVS_REG_DISCONT
6219 */
6220 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
6221 {
6222 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
6223 }
6224
6225 /**
6226 * @brief Set ADC oversampling
6227 * (impacting both ADC groups regular and injected)
6228 * @note This function set the 2 items of oversampling configuration:
6229 * - ratio
6230 * - shift
6231 * @note On this STM32 serie, setting of this feature is conditioned to
6232 * ADC state:
6233 * ADC must be disabled or enabled without conversion on going
6234 * on either groups regular or injected.
6235 * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n
6236 * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
6237 * @param ADCx ADC instance
6238 * @param Ratio This parameter can be in the range from 1 to 1024.
6239 * @param Shift This parameter can be one of the following values:
6240 * @arg @ref LL_ADC_OVS_SHIFT_NONE
6241 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
6242 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
6243 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
6244 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
6245 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
6246 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
6247 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
6248 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
6249 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9
6250 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10
6251 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11
6252 * @retval None
6253 */
6254 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
6255 {
6256 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | (((Ratio - 1UL) << ADC_CFGR2_OVSR_Pos))));
6257 }
6258
6259 /**
6260 * @brief Get ADC oversampling ratio
6261 * (impacting both ADC groups regular and injected)
6262 * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
6263 * @param ADCx ADC instance
6264 * @retval Ratio This parameter can be in the from 1 to 1024.
6265 */
6266 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
6267 {
6268 return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)) + (1UL << ADC_CFGR2_OVSR_Pos)) >> ADC_CFGR2_OVSR_Pos);
6269 }
6270
6271 /**
6272 * @brief Get ADC oversampling shift
6273 * (impacting both ADC groups regular and injected)
6274 * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
6275 * @param ADCx ADC instance
6276 * @retval Shift This parameter can be one of the following values:
6277 * @arg @ref LL_ADC_OVS_SHIFT_NONE
6278 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
6279 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
6280 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
6281 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
6282 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
6283 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
6284 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
6285 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
6286 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9
6287 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10
6288 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11
6289 */
6290 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
6291 {
6292 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
6293 }
6294
6295 /**
6296 * @}
6297 */
6298
6299 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
6300 * @{
6301 */
6302 /**
6303 * @brief Set ADC boost mode.
6304 * @note On this STM32 serie, setting of this feature is conditioned to
6305 * ADC state:
6306 * ADC boost must be configured, without calibration on going, without conversion
6307 * on going on group regular.
6308 * @rmtoll CR BOOST LL_ADC_SetBoostMode
6309 * @param ADCx ADC instance
6310 * @param BoostMode This parameter can be one of the following values:
6311 * @arg @ref LL_ADC_BOOST_MODE_6MHZ25
6312 * @arg @ref LL_ADC_BOOST_MODE_12MHZ5
6313 * @arg @ref LL_ADC_BOOST_MODE_20MHZ
6314 * @arg @ref LL_ADC_BOOST_MODE_25MHZ
6315 * @arg @ref LL_ADC_BOOST_MODE_50MHZ
6316 * @retval None
6317 */
6318 __STATIC_INLINE void LL_ADC_SetBoostMode(ADC_TypeDef *ADCx, uint32_t BoostMode)
6319 {
6320 #if defined(ADC_VER_V5_V90)
6321 if (ADCx != ADC3)
6322 {
6323 MODIFY_REG(ADCx->CR, ADC_CR_BOOST, (BoostMode & ADC_CR_BOOST));
6324 }
6325 #else /* ADC_VER_V5_V90 */
6326 if ((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Cut 1.x */
6327 {
6328 MODIFY_REG(ADCx->CR, ADC_CR_BOOST_0, (BoostMode >> 2UL));
6329 }
6330 else /* Cut 2.x */
6331 {
6332 MODIFY_REG(ADCx->CR, ADC_CR_BOOST, (BoostMode & ADC_CR_BOOST));
6333 }
6334 #endif
6335 }
6336
6337
6338 /**
6339 * @brief Get ADC boost mode.
6340 * @note On this STM32 serie, setting of this feature is conditioned to
6341 * ADC state:
6342 * ADC boost must be configured, without calibration on going, without conversion
6343 * on going on group regular.
6344 * @rmtoll CR BOOST LL_ADC_GetBoostMode
6345 * @param ADCx ADC instance
6346 * @retval 0: Boost disabled 1: Boost enabled
6347 */
6348 __STATIC_INLINE uint32_t LL_ADC_GetBoostMode(ADC_TypeDef *ADCx)
6349 {
6350 if ((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Cut 1.x */
6351 {
6352 return (uint32_t)READ_BIT(ADCx->CR, ADC_CR_BOOST_0);
6353 }
6354 else /* Cut 2.x */
6355 {
6356 return ((READ_BIT(ADCx->CR, ADC_CR_BOOST) == (ADC_CR_BOOST)) ? 1UL : 0UL);
6357 }
6358 }
6359
6360 /**
6361 * @brief Set ADC multimode configuration to operate in independent mode
6362 * or multimode (for devices with several ADC instances).
6363 * @note If multimode configuration: the selected ADC instance is
6364 * either master or slave depending on hardware.
6365 * Refer to reference manual.
6366 * @note On this STM32 serie, setting of this feature is conditioned to
6367 * ADC state:
6368 * All ADC instances of the ADC common group must be disabled.
6369 * This check can be done with function @ref LL_ADC_IsEnabled() for each
6370 * ADC instance or by using helper macro
6371 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
6372 * @rmtoll CCR DUAL LL_ADC_SetMultimode
6373 * @param ADCxy_COMMON ADC common instance
6374 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6375 * @param Multimode This parameter can be one of the following values:
6376 * @arg @ref LL_ADC_MULTI_INDEPENDENT
6377 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
6378 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
6379 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
6380 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
6381 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
6382 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
6383 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
6384 * @retval None
6385 */
6386 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
6387 {
6388 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
6389 }
6390
6391 /**
6392 * @brief Get ADC multimode configuration to operate in independent mode
6393 * or multimode (for devices with several ADC instances).
6394 * @note If multimode configuration: the selected ADC instance is
6395 * either master or slave depending on hardware.
6396 * Refer to reference manual.
6397 * @rmtoll CCR DUAL LL_ADC_GetMultimode
6398 * @param ADCxy_COMMON ADC common instance
6399 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6400 * @retval Returned value can be one of the following values:
6401 * @arg @ref LL_ADC_MULTI_INDEPENDENT
6402 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
6403 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
6404 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
6405 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
6406 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
6407 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
6408 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
6409 */
6410 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
6411 {
6412 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
6413 }
6414
6415 /**
6416 * @brief Set ADC multimode conversion data transfer: no transfer
6417 * or transfer by DMA.
6418 * @note If ADC multimode transfer by DMA is not selected:
6419 * each ADC uses its own DMA channel, with its individual
6420 * DMA transfer settings.
6421 * If ADC multimode transfer by DMA is selected:
6422 * One DMA channel is used for both ADC (DMA of ADC master)
6423 * Specifies the DMA requests mode:
6424 * - Limited mode (One shot mode): DMA transfer requests are stopped
6425 * when number of DMA data transfers (number of
6426 * ADC conversions) is reached.
6427 * This ADC mode is intended to be used with DMA mode non-circular.
6428 * - Unlimited mode: DMA transfer requests are unlimited,
6429 * whatever number of DMA data transfers (number of
6430 * ADC conversions).
6431 * This ADC mode is intended to be used with DMA mode circular.
6432 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
6433 * mode non-circular:
6434 * when DMA transfers size will be reached, DMA will stop transfers of
6435 * ADC conversions data ADC will raise an overrun error
6436 * (overrun flag and interruption if enabled).
6437 * @note How to retrieve multimode conversion data:
6438 * Whatever multimode transfer by DMA setting: using function
6439 * @ref LL_ADC_REG_ReadMultiConversionData32().
6440 * If ADC multimode transfer by DMA is selected: conversion data
6441 * is a raw data with ADC master and slave concatenated.
6442 * A macro is available to get the conversion data of
6443 * ADC master or ADC slave: see helper macro
6444 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
6445 * @note On this STM32 serie, setting of this feature is conditioned to
6446 * ADC state:
6447 * All ADC instances of the ADC common group must be disabled
6448 * or enabled without conversion on going on group regular.
6449 * @rmtoll CCR DAMDF LL_ADC_GetMultiDMATransfer\n
6450 * @param ADCxy_COMMON ADC common instance
6451 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6452 * @param MultiDMATransfer This parameter can be one of the following values:
6453 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
6454 * @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_10B
6455 * @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B
6456 * @retval None
6457 */
6458 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
6459 {
6460 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DAMDF, MultiDMATransfer);
6461 }
6462
6463 /**
6464 * @brief Get ADC multimode conversion data transfer: no transfer
6465 * or transfer by DMA.
6466 * @note If ADC multimode transfer by DMA is not selected:
6467 * each ADC uses its own DMA channel, with its individual
6468 * DMA transfer settings.
6469 * If ADC multimode transfer by DMA is selected:
6470 * One DMA channel is used for both ADC (DMA of ADC master)
6471 * Specifies the DMA requests mode:
6472 * - Limited mode (One shot mode): DMA transfer requests are stopped
6473 * when number of DMA data transfers (number of
6474 * ADC conversions) is reached.
6475 * This ADC mode is intended to be used with DMA mode non-circular.
6476 * - Unlimited mode: DMA transfer requests are unlimited,
6477 * whatever number of DMA data transfers (number of
6478 * ADC conversions).
6479 * This ADC mode is intended to be used with DMA mode circular.
6480 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
6481 * mode non-circular:
6482 * when DMA transfers size will be reached, DMA will stop transfers of
6483 * ADC conversions data ADC will raise an overrun error
6484 * (overrun flag and interruption if enabled).
6485 * @note How to retrieve multimode conversion data:
6486 * Whatever multimode transfer by DMA setting: using function
6487 * @ref LL_ADC_REG_ReadMultiConversionData32().
6488 * If ADC multimode transfer by DMA is selected: conversion data
6489 * is a raw data with ADC master and slave concatenated.
6490 * A macro is available to get the conversion data of
6491 * ADC master or ADC slave: see helper macro
6492 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
6493 * @rmtoll CCR DAMDF LL_ADC_GetMultiDMATransfer\n
6494 * @param ADCxy_COMMON ADC common instance
6495 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6496 * @retval Returned value can be one of the following values:
6497 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
6498 * @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_10B
6499 * @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B
6500 */
6501 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
6502 {
6503 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DAMDF));
6504 }
6505
6506 /**
6507 * @brief Set ADC multimode delay between 2 sampling phases.
6508 * @note The sampling delay range depends on ADC resolution:
6509 * - ADC resolution 12 bits can have maximum delay of 12 cycles.
6510 * - ADC resolution 10 bits can have maximum delay of 10 cycles.
6511 * - ADC resolution 8 bits can have maximum delay of 8 cycles.
6512 * - ADC resolution 6 bits can have maximum delay of 6 cycles.
6513 * @note On this STM32 serie, setting of this feature is conditioned to
6514 * ADC state:
6515 * All ADC instances of the ADC common group must be disabled.
6516 * This check can be done with function @ref LL_ADC_IsEnabled() for each
6517 * ADC instance or by using helper macro helper macro
6518 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
6519 * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
6520 * @param ADCxy_COMMON ADC common instance
6521 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6522 * @param MultiTwoSamplingDelay This parameter can be one of the following values:
6523 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5
6524 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5
6525 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5
6526 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 (1)
6527 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS
6528 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 (2)
6529 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS
6530 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (3)
6531 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 (4)
6532 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS
6533 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 (5)
6534 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (6)
6535 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (7)
6536 *
6537 * (1) Parameter available only if ADC resolution is 16, 14, 12 or 10 bits.
6538 * (2) Parameter available only if ADC resolution is 16, 14 or 12 bits.
6539 * (3) Parameter available only if ADC resolution is 10 or 8 bits.
6540 * (4) Parameter available only if ADC resolution is 16 or 14 bits.
6541 * (5) Parameter available only if ADC resolution is 16 bits.
6542 * (6) Parameter available only if ADC resolution is 12 bits.
6543 * (7) Parameter available only if ADC resolution is 16 or 14 bits.
6544 * @retval None
6545 */
6546 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
6547 {
6548 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
6549 }
6550
6551 /**
6552 * @brief Get ADC multimode delay between 2 sampling phases.
6553 * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
6554 * @param ADCxy_COMMON ADC common instance
6555 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6556 * @retval Returned value can be one of the following values:
6557 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5
6558 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5
6559 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5
6560 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 (1)
6561 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS
6562 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 (2)
6563 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS
6564 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (3)
6565 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 (4)
6566 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS
6567 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 (5)
6568 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (6)
6569 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (7)
6570 *
6571 * (1) Parameter available only if ADC resolution is 16, 14, 12 or 10 bits.
6572 * (2) Parameter available only if ADC resolution is 16, 14 or 12 bits.
6573 * (3) Parameter available only if ADC resolution is 10 or 8 bits.
6574 * (4) Parameter available only if ADC resolution is 16 or 14 bits.
6575 * (5) Parameter available only if ADC resolution is 16 bits.
6576 * (6) Parameter available only if ADC resolution is 12 bits.
6577 * (7) Parameter available only if ADC resolution is 16 or 14 bits.
6578 */
6579 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
6580 {
6581 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
6582 }
6583
6584 /**
6585 * @}
6586 */
6587 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
6588 * @{
6589 */
6590
6591 /**
6592 * @brief Put ADC instance in deep power down state.
6593 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
6594 * state, the internal analog calibration is lost. After exiting from
6595 * deep power down, calibration must be relaunched or calibration factor
6596 * (preliminarily saved) must be set back into calibration register.
6597 * @note On this STM32 serie, setting of this feature is conditioned to
6598 * ADC state:
6599 * ADC must be ADC disabled.
6600 * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown
6601 * @param ADCx ADC instance
6602 * @retval None
6603 */
6604 __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
6605 {
6606 /* Note: Write register with some additional bits forced to state reset */
6607 /* instead of modifying only the selected bit for this function, */
6608 /* to not interfere with bits with HW property "rs". */
6609 MODIFY_REG(ADCx->CR,
6610 ADC_CR_BITS_PROPERTY_RS,
6611 ADC_CR_DEEPPWD);
6612 }
6613
6614 /**
6615 * @brief Disable ADC deep power down mode.
6616 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
6617 * state, the internal analog calibration is lost. After exiting from
6618 * deep power down, calibration must be relaunched or calibration factor
6619 * (preliminarily saved) must be set back into calibration register.
6620 * @note On this STM32 serie, setting of this feature is conditioned to
6621 * ADC state:
6622 * ADC must be ADC disabled.
6623 * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
6624 * @param ADCx ADC instance
6625 * @retval None
6626 */
6627 __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
6628 {
6629 /* Note: Write register with some additional bits forced to state reset */
6630 /* instead of modifying only the selected bit for this function, */
6631 /* to not interfere with bits with HW property "rs". */
6632 CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
6633 }
6634
6635 /**
6636 * @brief Get the selected ADC instance deep power down state.
6637 * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
6638 * @param ADCx ADC instance
6639 * @retval 0: deep power down is disabled, 1: deep power down is enabled.
6640 */
6641 __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
6642 {
6643 return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
6644 }
6645
6646 /**
6647 * @brief Enable ADC instance internal voltage regulator.
6648 * @note On this STM32 serie, after ADC internal voltage regulator enable,
6649 * a delay for ADC internal voltage regulator stabilization
6650 * is required before performing a ADC calibration or ADC enable.
6651 * Refer to device datasheet, parameter tADCVREG_STUP.
6652 * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
6653 * @note On this STM32 serie, setting of this feature is conditioned to
6654 * ADC state:
6655 * ADC must be ADC disabled.
6656 * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
6657 * @param ADCx ADC instance
6658 * @retval None
6659 */
6660 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
6661 {
6662 /* Note: Write register with some additional bits forced to state reset */
6663 /* instead of modifying only the selected bit for this function, */
6664 /* to not interfere with bits with HW property "rs". */
6665 MODIFY_REG(ADCx->CR,
6666 ADC_CR_BITS_PROPERTY_RS,
6667 ADC_CR_ADVREGEN);
6668 }
6669
6670 /**
6671 * @brief Disable ADC internal voltage regulator.
6672 * @note On this STM32 serie, setting of this feature is conditioned to
6673 * ADC state:
6674 * ADC must be ADC disabled.
6675 * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
6676 * @param ADCx ADC instance
6677 * @retval None
6678 */
6679 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
6680 {
6681 CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
6682 }
6683
6684 /**
6685 * @brief Get the selected ADC instance internal voltage regulator state.
6686 * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
6687 * @param ADCx ADC instance
6688 * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
6689 */
6690 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
6691 {
6692 return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
6693 }
6694
6695 /**
6696 * @brief Enable the selected ADC instance.
6697 * @note On this STM32 serie, after ADC enable, a delay for
6698 * ADC internal analog stabilization is required before performing a
6699 * ADC conversion start.
6700 * Refer to device datasheet, parameter tSTAB.
6701 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6702 * is enabled and when conversion clock is active.
6703 * (not only core clock: this ADC has a dual clock domain)
6704 * @note On this STM32 serie, setting of this feature is conditioned to
6705 * ADC state:
6706 * ADC must be ADC disabled and ADC internal voltage regulator enabled.
6707 * @rmtoll CR ADEN LL_ADC_Enable
6708 * @param ADCx ADC instance
6709 * @retval None
6710 */
6711 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
6712 {
6713 /* Note: Write register with some additional bits forced to state reset */
6714 /* instead of modifying only the selected bit for this function, */
6715 /* to not interfere with bits with HW property "rs". */
6716 MODIFY_REG(ADCx->CR,
6717 ADC_CR_BITS_PROPERTY_RS,
6718 ADC_CR_ADEN);
6719 }
6720
6721 /**
6722 * @brief Disable the selected ADC instance.
6723 * @note On this STM32 serie, setting of this feature is conditioned to
6724 * ADC state:
6725 * ADC must be not disabled. Must be enabled without conversion on going
6726 * on either groups regular or injected.
6727 * @rmtoll CR ADDIS LL_ADC_Disable
6728 * @param ADCx ADC instance
6729 * @retval None
6730 */
6731 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
6732 {
6733 /* Note: Write register with some additional bits forced to state reset */
6734 /* instead of modifying only the selected bit for this function, */
6735 /* to not interfere with bits with HW property "rs". */
6736 MODIFY_REG(ADCx->CR,
6737 ADC_CR_BITS_PROPERTY_RS,
6738 ADC_CR_ADDIS);
6739 }
6740
6741 /**
6742 * @brief Get the selected ADC instance enable state.
6743 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6744 * is enabled and when conversion clock is active.
6745 * (not only core clock: this ADC has a dual clock domain)
6746 * @rmtoll CR ADEN LL_ADC_IsEnabled
6747 * @param ADCx ADC instance
6748 * @retval 0: ADC is disabled, 1: ADC is enabled.
6749 */
6750 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
6751 {
6752 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
6753 }
6754
6755 /**
6756 * @brief Get the selected ADC instance disable state.
6757 * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
6758 * @param ADCx ADC instance
6759 * @retval 0: no ADC disable command on going.
6760 */
6761 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
6762 {
6763 return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
6764 }
6765
6766 /**
6767 * @brief Start ADC calibration in the mode single-ended
6768 * or differential (for devices with differential mode available).
6769 * @note On this STM32 serie, a minimum number of ADC clock cycles
6770 * are required between ADC end of calibration and ADC enable.
6771 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
6772 * @note Calibration duration:
6773 * - Calibration of offset: 520 ADC clock cycles
6774 * - Calibration of linearity: 131072 ADC clock cycles
6775 * @note For devices with differential mode available:
6776 * Calibration of offset is specific to each of
6777 * single-ended and differential modes
6778 * (calibration run must be performed for each of these
6779 * differential modes, if used afterwards and if the application
6780 * requires their calibration).
6781 * Calibration of linearity is common to both
6782 * single-ended and differential modes
6783 * (calibration run can be performed only once).
6784 * @note On this STM32 serie, setting of this feature is conditioned to
6785 * ADC state:
6786 * ADC must be ADC disabled.
6787 * @rmtoll CR ADCAL LL_ADC_StartCalibration\n
6788 * CR ADCALDIF LL_ADC_StartCalibration\n
6789 * CR ADCALLIN LL_ADC_StartCalibration
6790 * @param ADCx ADC instance
6791 * @param CalibrationMode This parameter can be one of the following values:
6792 * @arg @ref LL_ADC_CALIB_OFFSET
6793 * @arg @ref LL_ADC_CALIB_OFFSET_LINEARITY
6794 * @param SingleDiff This parameter can be one of the following values:
6795 * @arg @ref LL_ADC_SINGLE_ENDED
6796 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
6797 * @retval None
6798 */
6799 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t CalibrationMode, uint32_t SingleDiff)
6800 {
6801 /* Note: Write register with some additional bits forced to state reset */
6802 /* instead of modifying only the selected bit for this function, */
6803 /* to not interfere with bits with HW property "rs". */
6804 MODIFY_REG(ADCx->CR,
6805 ADC_CR_ADCALLIN | ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
6806 ADC_CR_ADCAL | (CalibrationMode & ADC_CALIB_MODE_MASK) | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
6807 }
6808
6809 /**
6810 * @brief Get ADC calibration state.
6811 * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
6812 * @param ADCx ADC instance
6813 * @retval 0: calibration complete, 1: calibration in progress.
6814 */
6815 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
6816 {
6817 return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
6818 }
6819
6820 /**
6821 * @}
6822 */
6823
6824 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
6825 * @{
6826 */
6827
6828 /**
6829 * @brief Start ADC group regular conversion.
6830 * @note On this STM32 serie, this function is relevant for both
6831 * internal trigger (SW start) and external trigger:
6832 * - If ADC trigger has been set to software start, ADC conversion
6833 * starts immediately.
6834 * - If ADC trigger has been set to external trigger, ADC conversion
6835 * will start at next trigger event (on the selected trigger edge)
6836 * following the ADC start conversion command.
6837 * @note On this STM32 serie, setting of this feature is conditioned to
6838 * ADC state:
6839 * ADC must be enabled without conversion on going on group regular,
6840 * without conversion stop command on going on group regular,
6841 * without ADC disable command on going.
6842 * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
6843 * @param ADCx ADC instance
6844 * @retval None
6845 */
6846 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
6847 {
6848 /* Note: Write register with some additional bits forced to state reset */
6849 /* instead of modifying only the selected bit for this function, */
6850 /* to not interfere with bits with HW property "rs". */
6851 MODIFY_REG(ADCx->CR,
6852 ADC_CR_BITS_PROPERTY_RS,
6853 ADC_CR_ADSTART);
6854 }
6855
6856 /**
6857 * @brief Stop ADC group regular conversion.
6858 * @note On this STM32 serie, setting of this feature is conditioned to
6859 * ADC state:
6860 * ADC must be enabled with conversion on going on group regular,
6861 * without ADC disable command on going.
6862 * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
6863 * @param ADCx ADC instance
6864 * @retval None
6865 */
6866 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
6867 {
6868 /* Note: Write register with some additional bits forced to state reset */
6869 /* instead of modifying only the selected bit for this function, */
6870 /* to not interfere with bits with HW property "rs". */
6871 MODIFY_REG(ADCx->CR,
6872 ADC_CR_BITS_PROPERTY_RS,
6873 ADC_CR_ADSTP);
6874 }
6875
6876 /**
6877 * @brief Get ADC group regular conversion state.
6878 * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
6879 * @param ADCx ADC instance
6880 * @retval 0: no conversion is on going on ADC group regular.
6881 */
6882 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
6883 {
6884 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
6885 }
6886
6887 /**
6888 * @brief Get ADC group regular command of conversion stop state
6889 * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
6890 * @param ADCx ADC instance
6891 * @retval 0: no command of conversion stop is on going on ADC group regular.
6892 */
6893 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
6894 {
6895 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
6896 }
6897
6898 /**
6899 * @brief Get ADC group regular conversion data, range fit for
6900 * all ADC configurations: all ADC resolutions and
6901 * all oversampling increased data width (for devices
6902 * with feature oversampling).
6903 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
6904 * @param ADCx ADC instance
6905 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6906 */
6907 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
6908 {
6909 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6910 }
6911
6912 /**
6913 * @brief Get ADC group regular conversion data, range fit for
6914 * ADC resolution 16 bits.
6915 * @note For devices with feature oversampling: Oversampling
6916 * can increase data width, function for extended range
6917 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6918 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData16
6919 * @param ADCx ADC instance
6920 * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
6921 */
6922 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData16(ADC_TypeDef *ADCx)
6923 {
6924 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6925 }
6926
6927 /**
6928 * @brief Get ADC group regular conversion data, range fit for
6929 * ADC resolution 14 bits.
6930 * @note For devices with feature oversampling: Oversampling
6931 * can increase data width, function for extended range
6932 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6933 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData14
6934 * @param ADCx ADC instance
6935 * @retval Value between Min_Data=0x00 and Max_Data=0x3FF
6936 */
6937 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData14(ADC_TypeDef *ADCx)
6938 {
6939 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6940 }
6941
6942 /**
6943 * @brief Get ADC group regular conversion data, range fit for
6944 * ADC resolution 12 bits.
6945 * @note For devices with feature oversampling: Oversampling
6946 * can increase data width, function for extended range
6947 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6948 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
6949 * @param ADCx ADC instance
6950 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
6951 */
6952 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
6953 {
6954 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6955 }
6956
6957 /**
6958 * @brief Get ADC group regular conversion data, range fit for
6959 * ADC resolution 10 bits.
6960 * @note For devices with feature oversampling: Oversampling
6961 * can increase data width, function for extended range
6962 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6963 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
6964 * @param ADCx ADC instance
6965 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
6966 */
6967 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
6968 {
6969 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6970 }
6971
6972 /**
6973 * @brief Get ADC group regular conversion data, range fit for
6974 * ADC resolution 8 bits.
6975 * @note For devices with feature oversampling: Oversampling
6976 * can increase data width, function for extended range
6977 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6978 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
6979 * @param ADCx ADC instance
6980 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
6981 */
6982 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
6983 {
6984 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6985 }
6986 /**
6987 * @brief Get ADC multimode conversion data of ADC master, ADC slave
6988 * or raw data with ADC master and slave concatenated.
6989 * @note If raw data with ADC master and slave concatenated is retrieved,
6990 * a macro is available to get the conversion data of
6991 * ADC master or ADC slave: see helper macro
6992 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
6993 * (however this macro is mainly intended for multimode
6994 * transfer by DMA, because this function can do the same
6995 * by getting multimode conversion data of ADC master or ADC slave
6996 * separately).
6997 * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n
6998 * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32
6999 * @param ADCxy_COMMON ADC common instance
7000 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7001 * @param ConversionData This parameter can be one of the following values:
7002 * @arg @ref LL_ADC_MULTI_MASTER
7003 * @arg @ref LL_ADC_MULTI_SLAVE
7004 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
7005 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
7006 */
7007 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
7008 {
7009 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
7010 ConversionData)
7011 >> (POSITION_VAL(ConversionData) & 0x1FUL)
7012 );
7013 }
7014
7015 /**
7016 * @}
7017 */
7018
7019 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
7020 * @{
7021 */
7022
7023 /**
7024 * @brief Start ADC group injected conversion.
7025 * @note On this STM32 serie, this function is relevant for both
7026 * internal trigger (SW start) and external trigger:
7027 * - If ADC trigger has been set to software start, ADC conversion
7028 * starts immediately.
7029 * - If ADC trigger has been set to external trigger, ADC conversion
7030 * will start at next trigger event (on the selected trigger edge)
7031 * following the ADC start conversion command.
7032 * @note On this STM32 serie, setting of this feature is conditioned to
7033 * ADC state:
7034 * ADC must be enabled without conversion on going on group injected,
7035 * without conversion stop command on going on group injected,
7036 * without ADC disable command on going.
7037 * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion
7038 * @param ADCx ADC instance
7039 * @retval None
7040 */
7041 __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
7042 {
7043 /* Note: Write register with some additional bits forced to state reset */
7044 /* instead of modifying only the selected bit for this function, */
7045 /* to not interfere with bits with HW property "rs". */
7046 MODIFY_REG(ADCx->CR,
7047 ADC_CR_BITS_PROPERTY_RS,
7048 ADC_CR_JADSTART);
7049 }
7050
7051 /**
7052 * @brief Stop ADC group injected conversion.
7053 * @note On this STM32 serie, setting of this feature is conditioned to
7054 * ADC state:
7055 * ADC must be enabled with conversion on going on group injected,
7056 * without ADC disable command on going.
7057 * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
7058 * @param ADCx ADC instance
7059 * @retval None
7060 */
7061 __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
7062 {
7063 /* Note: Write register with some additional bits forced to state reset */
7064 /* instead of modifying only the selected bit for this function, */
7065 /* to not interfere with bits with HW property "rs". */
7066 MODIFY_REG(ADCx->CR,
7067 ADC_CR_BITS_PROPERTY_RS,
7068 ADC_CR_JADSTP);
7069 }
7070
7071 /**
7072 * @brief Get ADC group injected conversion state.
7073 * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
7074 * @param ADCx ADC instance
7075 * @retval 0: no conversion is on going on ADC group injected.
7076 */
7077 __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
7078 {
7079 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
7080 }
7081
7082 /**
7083 * @brief Get ADC group injected command of conversion stop state
7084 * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
7085 * @param ADCx ADC instance
7086 * @retval 0: no command of conversion stop is on going on ADC group injected.
7087 */
7088 __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
7089 {
7090 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
7091 }
7092
7093 /**
7094 * @brief Get ADC group injected conversion data, range fit for
7095 * all ADC configurations: all ADC resolutions and
7096 * all oversampling increased data width (for devices
7097 * with feature oversampling).
7098 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
7099 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
7100 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
7101 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
7102 * @param ADCx ADC instance
7103 * @param Rank This parameter can be one of the following values:
7104 * @arg @ref LL_ADC_INJ_RANK_1
7105 * @arg @ref LL_ADC_INJ_RANK_2
7106 * @arg @ref LL_ADC_INJ_RANK_3
7107 * @arg @ref LL_ADC_INJ_RANK_4
7108 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
7109 */
7110 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
7111 {
7112 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7113
7114 return (uint32_t)(READ_BIT(*preg,
7115 ADC_JDR1_JDATA)
7116 );
7117 }
7118
7119 /**
7120 * @brief Get ADC group injected conversion data, range fit for
7121 * ADC resolution 16 bits.
7122 * @note For devices with feature oversampling: Oversampling
7123 * can increase data width, function for extended range
7124 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7125 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData16\n
7126 * JDR2 JDATA LL_ADC_INJ_ReadConversionData16\n
7127 * JDR3 JDATA LL_ADC_INJ_ReadConversionData16\n
7128 * JDR4 JDATA LL_ADC_INJ_ReadConversionData16
7129 * @param ADCx ADC instance
7130 * @param Rank This parameter can be one of the following values:
7131 * @arg @ref LL_ADC_INJ_RANK_1
7132 * @arg @ref LL_ADC_INJ_RANK_2
7133 * @arg @ref LL_ADC_INJ_RANK_3
7134 * @arg @ref LL_ADC_INJ_RANK_4
7135 * @retval Value between Min_Data=0x000 and Max_Data=0xFFFF
7136 */
7137 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(ADC_TypeDef *ADCx, uint32_t Rank)
7138 {
7139 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7140
7141 return (uint16_t)(READ_BIT(*preg,
7142 ADC_JDR1_JDATA)
7143 );
7144 }
7145
7146 /**
7147 * @brief Get ADC group injected conversion data, range fit for
7148 * ADC resolution 14 bits.
7149 * @note For devices with feature oversampling: Oversampling
7150 * can increase data width, function for extended range
7151 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7152 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData14\n
7153 * JDR2 JDATA LL_ADC_INJ_ReadConversionData14\n
7154 * JDR3 JDATA LL_ADC_INJ_ReadConversionData14\n
7155 * JDR4 JDATA LL_ADC_INJ_ReadConversionData14
7156 * @param ADCx ADC instance
7157 * @param Rank This parameter can be one of the following values:
7158 * @arg @ref LL_ADC_INJ_RANK_1
7159 * @arg @ref LL_ADC_INJ_RANK_2
7160 * @arg @ref LL_ADC_INJ_RANK_3
7161 * @arg @ref LL_ADC_INJ_RANK_4
7162 * @retval Value between Min_Data=0x000 and Max_Data=0x3FFF
7163 */
7164 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(ADC_TypeDef *ADCx, uint32_t Rank)
7165 {
7166 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7167
7168 return (uint16_t)(READ_BIT(*preg,
7169 ADC_JDR1_JDATA)
7170 );
7171 }
7172
7173 /**
7174 * @brief Get ADC group injected conversion data, range fit for
7175 * ADC resolution 12 bits.
7176 * @note For devices with feature oversampling: Oversampling
7177 * can increase data width, function for extended range
7178 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7179 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
7180 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
7181 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
7182 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
7183 * @param ADCx ADC instance
7184 * @param Rank This parameter can be one of the following values:
7185 * @arg @ref LL_ADC_INJ_RANK_1
7186 * @arg @ref LL_ADC_INJ_RANK_2
7187 * @arg @ref LL_ADC_INJ_RANK_3
7188 * @arg @ref LL_ADC_INJ_RANK_4
7189 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
7190 */
7191 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
7192 {
7193 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7194
7195 return (uint16_t)(READ_BIT(*preg,
7196 ADC_JDR1_JDATA)
7197 );
7198 }
7199
7200 /**
7201 * @brief Get ADC group injected conversion data, range fit for
7202 * ADC resolution 10 bits.
7203 * @note For devices with feature oversampling: Oversampling
7204 * can increase data width, function for extended range
7205 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7206 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
7207 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
7208 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
7209 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
7210 * @param ADCx ADC instance
7211 * @param Rank This parameter can be one of the following values:
7212 * @arg @ref LL_ADC_INJ_RANK_1
7213 * @arg @ref LL_ADC_INJ_RANK_2
7214 * @arg @ref LL_ADC_INJ_RANK_3
7215 * @arg @ref LL_ADC_INJ_RANK_4
7216 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
7217 */
7218 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
7219 {
7220 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7221
7222 return (uint16_t)(READ_BIT(*preg,
7223 ADC_JDR1_JDATA)
7224 );
7225 }
7226
7227 /**
7228 * @brief Get ADC group injected conversion data, range fit for
7229 * ADC resolution 8 bits.
7230 * @note For devices with feature oversampling: Oversampling
7231 * can increase data width, function for extended range
7232 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7233 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
7234 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
7235 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
7236 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
7237 * @param ADCx ADC instance
7238 * @param Rank This parameter can be one of the following values:
7239 * @arg @ref LL_ADC_INJ_RANK_1
7240 * @arg @ref LL_ADC_INJ_RANK_2
7241 * @arg @ref LL_ADC_INJ_RANK_3
7242 * @arg @ref LL_ADC_INJ_RANK_4
7243 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
7244 */
7245 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
7246 {
7247 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7248
7249 return (uint8_t)(READ_BIT(*preg,
7250 ADC_JDR1_JDATA)
7251 );
7252 }
7253
7254 /**
7255 * @}
7256 */
7257
7258 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
7259 * @{
7260 */
7261
7262 /**
7263 * @brief Get flag ADC ready.
7264 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
7265 * is enabled and when conversion clock is active.
7266 * (not only core clock: this ADC has a dual clock domain)
7267 * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
7268 * @param ADCx ADC instance
7269 * @retval State of bit (1 or 0).
7270 */
7271 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
7272 {
7273 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
7274 }
7275
7276 /**
7277 * @brief Get flag ADC group regular end of unitary conversion.
7278 * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
7279 * @param ADCx ADC instance
7280 * @retval State of bit (1 or 0).
7281 */
7282 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
7283 {
7284 return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
7285 }
7286
7287 /**
7288 * @brief Get flag ADC group regular end of sequence conversions.
7289 * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
7290 * @param ADCx ADC instance
7291 * @retval State of bit (1 or 0).
7292 */
7293 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
7294 {
7295 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
7296 }
7297
7298 /**
7299 * @brief Get flag ADC group regular overrun.
7300 * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
7301 * @param ADCx ADC instance
7302 * @retval State of bit (1 or 0).
7303 */
7304 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
7305 {
7306 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
7307 }
7308
7309 /**
7310 * @brief Get flag ADC group regular end of sampling phase.
7311 * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
7312 * @param ADCx ADC instance
7313 * @retval State of bit (1 or 0).
7314 */
7315 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
7316 {
7317 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
7318 }
7319
7320 /**
7321 * @brief Get flag ADC group injected end of unitary conversion.
7322 * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC
7323 * @param ADCx ADC instance
7324 * @retval State of bit (1 or 0).
7325 */
7326 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)
7327 {
7328 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
7329 }
7330
7331 /**
7332 * @brief Get flag ADC group injected end of sequence conversions.
7333 * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS
7334 * @param ADCx ADC instance
7335 * @retval State of bit (1 or 0).
7336 */
7337 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
7338 {
7339 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
7340 }
7341
7342 /**
7343 * @brief Get flag ADC group injected contexts queue overflow.
7344 * @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF
7345 * @param ADCx ADC instance
7346 * @retval State of bit (1 or 0).
7347 */
7348 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
7349 {
7350 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);
7351 }
7352
7353 /**
7354 * @brief Get flag ADC analog watchdog 1 flag
7355 * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
7356 * @param ADCx ADC instance
7357 * @retval State of bit (1 or 0).
7358 */
7359 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
7360 {
7361 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
7362 }
7363
7364 /**
7365 * @brief Get flag ADC analog watchdog 2.
7366 * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
7367 * @param ADCx ADC instance
7368 * @retval State of bit (1 or 0).
7369 */
7370 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
7371 {
7372 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
7373 }
7374
7375 /**
7376 * @brief Get flag ADC analog watchdog 3.
7377 * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
7378 * @param ADCx ADC instance
7379 * @retval State of bit (1 or 0).
7380 */
7381 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
7382 {
7383 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
7384 }
7385
7386 /**
7387 * @brief Clear flag ADC ready.
7388 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
7389 * is enabled and when conversion clock is active.
7390 * (not only core clock: this ADC has a dual clock domain)
7391 * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
7392 * @param ADCx ADC instance
7393 * @retval None
7394 */
7395 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
7396 {
7397 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
7398 }
7399
7400 /**
7401 * @brief Clear flag ADC group regular end of unitary conversion.
7402 * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
7403 * @param ADCx ADC instance
7404 * @retval None
7405 */
7406 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
7407 {
7408 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
7409 }
7410
7411 /**
7412 * @brief Clear flag ADC group regular end of sequence conversions.
7413 * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
7414 * @param ADCx ADC instance
7415 * @retval None
7416 */
7417 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
7418 {
7419 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
7420 }
7421
7422 /**
7423 * @brief Clear flag ADC group regular overrun.
7424 * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
7425 * @param ADCx ADC instance
7426 * @retval None
7427 */
7428 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
7429 {
7430 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
7431 }
7432
7433 /**
7434 * @brief Clear flag ADC group regular end of sampling phase.
7435 * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
7436 * @param ADCx ADC instance
7437 * @retval None
7438 */
7439 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
7440 {
7441 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
7442 }
7443
7444 /**
7445 * @brief Clear flag ADC group injected end of unitary conversion.
7446 * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC
7447 * @param ADCx ADC instance
7448 * @retval None
7449 */
7450 __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
7451 {
7452 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
7453 }
7454
7455 /**
7456 * @brief Clear flag ADC group injected end of sequence conversions.
7457 * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS
7458 * @param ADCx ADC instance
7459 * @retval None
7460 */
7461 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
7462 {
7463 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
7464 }
7465
7466 /**
7467 * @brief Clear flag ADC group injected contexts queue overflow.
7468 * @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF
7469 * @param ADCx ADC instance
7470 * @retval None
7471 */
7472 __STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
7473 {
7474 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
7475 }
7476
7477 /**
7478 * @brief Clear flag ADC analog watchdog 1.
7479 * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
7480 * @param ADCx ADC instance
7481 * @retval None
7482 */
7483 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
7484 {
7485 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
7486 }
7487
7488 /**
7489 * @brief Clear flag ADC analog watchdog 2.
7490 * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
7491 * @param ADCx ADC instance
7492 * @retval None
7493 */
7494 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
7495 {
7496 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
7497 }
7498
7499 /**
7500 * @brief Clear flag ADC analog watchdog 3.
7501 * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
7502 * @param ADCx ADC instance
7503 * @retval None
7504 */
7505 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
7506 {
7507 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
7508 }
7509
7510 /**
7511 * @brief Get flag multimode ADC ready of the ADC master.
7512 * @rmtoll CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY
7513 * @param ADCxy_COMMON ADC common instance
7514 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7515 * @retval State of bit (1 or 0).
7516 */
7517 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
7518 {
7519 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL);
7520 }
7521
7522 /**
7523 * @brief Get flag multimode ADC ready of the ADC slave.
7524 * @rmtoll CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY
7525 * @param ADCxy_COMMON ADC common instance
7526 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7527 * @retval State of bit (1 or 0).
7528 */
7529 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
7530 {
7531 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL);
7532 }
7533
7534 /**
7535 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC master.
7536 * @rmtoll CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC
7537 * @param ADCxy_COMMON ADC common instance
7538 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7539 * @retval State of bit (1 or 0).
7540 */
7541 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
7542 {
7543 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
7544 }
7545
7546 /**
7547 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
7548 * @rmtoll CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC
7549 * @param ADCxy_COMMON ADC common instance
7550 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7551 * @retval State of bit (1 or 0).
7552 */
7553 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
7554 {
7555 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
7556 }
7557
7558 /**
7559 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master.
7560 * @rmtoll CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS
7561 * @param ADCxy_COMMON ADC common instance
7562 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7563 * @retval State of bit (1 or 0).
7564 */
7565 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
7566 {
7567 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL);
7568 }
7569
7570 /**
7571 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
7572 * @rmtoll CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS
7573 * @param ADCxy_COMMON ADC common instance
7574 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7575 * @retval State of bit (1 or 0).
7576 */
7577 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
7578 {
7579 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL);
7580 }
7581
7582 /**
7583 * @brief Get flag multimode ADC group regular overrun of the ADC master.
7584 * @rmtoll CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR
7585 * @param ADCxy_COMMON ADC common instance
7586 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7587 * @retval State of bit (1 or 0).
7588 */
7589 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
7590 {
7591 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL);
7592 }
7593
7594 /**
7595 * @brief Get flag multimode ADC group regular overrun of the ADC slave.
7596 * @rmtoll CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR
7597 * @param ADCxy_COMMON ADC common instance
7598 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7599 * @retval State of bit (1 or 0).
7600 */
7601 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
7602 {
7603 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL);
7604 }
7605
7606 /**
7607 * @brief Get flag multimode ADC group regular end of sampling of the ADC master.
7608 * @rmtoll CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP
7609 * @param ADCxy_COMMON ADC common instance
7610 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7611 * @retval State of bit (1 or 0).
7612 */
7613 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
7614 {
7615 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL);
7616 }
7617
7618 /**
7619 * @brief Get flag multimode ADC group regular end of sampling of the ADC slave.
7620 * @rmtoll CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP
7621 * @param ADCxy_COMMON ADC common instance
7622 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7623 * @retval State of bit (1 or 0).
7624 */
7625 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
7626 {
7627 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL);
7628 }
7629
7630 /**
7631 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC master.
7632 * @rmtoll CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC
7633 * @param ADCxy_COMMON ADC common instance
7634 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7635 * @retval State of bit (1 or 0).
7636 */
7637 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
7638 {
7639 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL);
7640 }
7641
7642 /**
7643 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
7644 * @rmtoll CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC
7645 * @param ADCxy_COMMON ADC common instance
7646 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7647 * @retval State of bit (1 or 0).
7648 */
7649 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
7650 {
7651 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL);
7652 }
7653
7654 /**
7655 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
7656 * @rmtoll CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS
7657 * @param ADCxy_COMMON ADC common instance
7658 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7659 * @retval State of bit (1 or 0).
7660 */
7661 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
7662 {
7663 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL);
7664 }
7665
7666 /**
7667 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
7668 * @rmtoll CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS
7669 * @param ADCxy_COMMON ADC common instance
7670 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7671 * @retval State of bit (1 or 0).
7672 */
7673 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
7674 {
7675 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL);
7676 }
7677
7678 /**
7679 * @brief Get flag multimode ADC group injected context queue overflow of the ADC master.
7680 * @rmtoll CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF
7681 * @param ADCxy_COMMON ADC common instance
7682 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7683 * @retval State of bit (1 or 0).
7684 */
7685 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
7686 {
7687 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL);
7688 }
7689
7690 /**
7691 * @brief Get flag multimode ADC group injected context queue overflow of the ADC slave.
7692 * @rmtoll CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF
7693 * @param ADCxy_COMMON ADC common instance
7694 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7695 * @retval State of bit (1 or 0).
7696 */
7697 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
7698 {
7699 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL);
7700 }
7701
7702 /**
7703 * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
7704 * @rmtoll CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1
7705 * @param ADCxy_COMMON ADC common instance
7706 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7707 * @retval State of bit (1 or 0).
7708 */
7709 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
7710 {
7711 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL);
7712 }
7713
7714 /**
7715 * @brief Get flag multimode analog watchdog 1 of the ADC slave.
7716 * @rmtoll CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1
7717 * @param ADCxy_COMMON ADC common instance
7718 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7719 * @retval State of bit (1 or 0).
7720 */
7721 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
7722 {
7723 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL);
7724 }
7725
7726 /**
7727 * @brief Get flag multimode ADC analog watchdog 2 of the ADC master.
7728 * @rmtoll CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2
7729 * @param ADCxy_COMMON ADC common instance
7730 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7731 * @retval State of bit (1 or 0).
7732 */
7733 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
7734 {
7735 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL);
7736 }
7737
7738 /**
7739 * @brief Get flag multimode ADC analog watchdog 2 of the ADC slave.
7740 * @rmtoll CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2
7741 * @param ADCxy_COMMON ADC common instance
7742 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7743 * @retval State of bit (1 or 0).
7744 */
7745 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
7746 {
7747 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL);
7748 }
7749
7750 /**
7751 * @brief Get flag multimode ADC analog watchdog 3 of the ADC master.
7752 * @rmtoll CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3
7753 * @param ADCxy_COMMON ADC common instance
7754 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7755 * @retval State of bit (1 or 0).
7756 */
7757 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
7758 {
7759 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL);
7760 }
7761
7762 /**
7763 * @brief Get flag multimode ADC analog watchdog 3 of the ADC slave.
7764 * @rmtoll CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3
7765 * @param ADCxy_COMMON ADC common instance
7766 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7767 * @retval State of bit (1 or 0).
7768 */
7769 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
7770 {
7771 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL);
7772 }
7773
7774 /**
7775 * @}
7776 */
7777
7778 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
7779 * @{
7780 */
7781
7782 /**
7783 * @brief Enable ADC ready.
7784 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
7785 * @param ADCx ADC instance
7786 * @retval None
7787 */
7788 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
7789 {
7790 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
7791 }
7792
7793 /**
7794 * @brief Enable interruption ADC group regular end of unitary conversion.
7795 * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
7796 * @param ADCx ADC instance
7797 * @retval None
7798 */
7799 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
7800 {
7801 SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
7802 }
7803
7804 /**
7805 * @brief Enable interruption ADC group regular end of sequence conversions.
7806 * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
7807 * @param ADCx ADC instance
7808 * @retval None
7809 */
7810 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
7811 {
7812 SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
7813 }
7814
7815 /**
7816 * @brief Enable ADC group regular interruption overrun.
7817 * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
7818 * @param ADCx ADC instance
7819 * @retval None
7820 */
7821 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
7822 {
7823 SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
7824 }
7825
7826 /**
7827 * @brief Enable interruption ADC group regular end of sampling.
7828 * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
7829 * @param ADCx ADC instance
7830 * @retval None
7831 */
7832 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
7833 {
7834 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
7835 }
7836
7837 /**
7838 * @brief Enable interruption ADC group injected end of unitary conversion.
7839 * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC
7840 * @param ADCx ADC instance
7841 * @retval None
7842 */
7843 __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
7844 {
7845 SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
7846 }
7847
7848 /**
7849 * @brief Enable interruption ADC group injected end of sequence conversions.
7850 * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS
7851 * @param ADCx ADC instance
7852 * @retval None
7853 */
7854 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
7855 {
7856 SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
7857 }
7858
7859 /**
7860 * @brief Enable interruption ADC group injected context queue overflow.
7861 * @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF
7862 * @param ADCx ADC instance
7863 * @retval None
7864 */
7865 __STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
7866 {
7867 SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
7868 }
7869
7870 /**
7871 * @brief Enable interruption ADC analog watchdog 1.
7872 * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
7873 * @param ADCx ADC instance
7874 * @retval None
7875 */
7876 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
7877 {
7878 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
7879 }
7880
7881 /**
7882 * @brief Enable interruption ADC analog watchdog 2.
7883 * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
7884 * @param ADCx ADC instance
7885 * @retval None
7886 */
7887 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
7888 {
7889 SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
7890 }
7891
7892 /**
7893 * @brief Enable interruption ADC analog watchdog 3.
7894 * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
7895 * @param ADCx ADC instance
7896 * @retval None
7897 */
7898 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
7899 {
7900 SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
7901 }
7902
7903 /**
7904 * @brief Disable interruption ADC ready.
7905 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
7906 * @param ADCx ADC instance
7907 * @retval None
7908 */
7909 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
7910 {
7911 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
7912 }
7913
7914 /**
7915 * @brief Disable interruption ADC group regular end of unitary conversion.
7916 * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
7917 * @param ADCx ADC instance
7918 * @retval None
7919 */
7920 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
7921 {
7922 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
7923 }
7924
7925 /**
7926 * @brief Disable interruption ADC group regular end of sequence conversions.
7927 * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
7928 * @param ADCx ADC instance
7929 * @retval None
7930 */
7931 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
7932 {
7933 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
7934 }
7935
7936 /**
7937 * @brief Disable interruption ADC group regular overrun.
7938 * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
7939 * @param ADCx ADC instance
7940 * @retval None
7941 */
7942 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
7943 {
7944 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
7945 }
7946
7947 /**
7948 * @brief Disable interruption ADC group regular end of sampling.
7949 * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
7950 * @param ADCx ADC instance
7951 * @retval None
7952 */
7953 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
7954 {
7955 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
7956 }
7957
7958 /**
7959 * @brief Disable interruption ADC group regular end of unitary conversion.
7960 * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC
7961 * @param ADCx ADC instance
7962 * @retval None
7963 */
7964 __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
7965 {
7966 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
7967 }
7968
7969 /**
7970 * @brief Disable interruption ADC group injected end of sequence conversions.
7971 * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS
7972 * @param ADCx ADC instance
7973 * @retval None
7974 */
7975 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
7976 {
7977 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
7978 }
7979
7980 /**
7981 * @brief Disable interruption ADC group injected context queue overflow.
7982 * @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF
7983 * @param ADCx ADC instance
7984 * @retval None
7985 */
7986 __STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
7987 {
7988 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
7989 }
7990
7991 /**
7992 * @brief Disable interruption ADC analog watchdog 1.
7993 * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
7994 * @param ADCx ADC instance
7995 * @retval None
7996 */
7997 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
7998 {
7999 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
8000 }
8001
8002 /**
8003 * @brief Disable interruption ADC analog watchdog 2.
8004 * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
8005 * @param ADCx ADC instance
8006 * @retval None
8007 */
8008 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
8009 {
8010 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
8011 }
8012
8013 /**
8014 * @brief Disable interruption ADC analog watchdog 3.
8015 * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
8016 * @param ADCx ADC instance
8017 * @retval None
8018 */
8019 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
8020 {
8021 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
8022 }
8023
8024 /**
8025 * @brief Get state of interruption ADC ready
8026 * (0: interrupt disabled, 1: interrupt enabled).
8027 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
8028 * @param ADCx ADC instance
8029 * @retval State of bit (1 or 0).
8030 */
8031 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
8032 {
8033 return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
8034 }
8035
8036 /**
8037 * @brief Get state of interruption ADC group regular end of unitary conversion
8038 * (0: interrupt disabled, 1: interrupt enabled).
8039 * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
8040 * @param ADCx ADC instance
8041 * @retval State of bit (1 or 0).
8042 */
8043 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
8044 {
8045 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
8046 }
8047
8048 /**
8049 * @brief Get state of interruption ADC group regular end of sequence conversions
8050 * (0: interrupt disabled, 1: interrupt enabled).
8051 * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
8052 * @param ADCx ADC instance
8053 * @retval State of bit (1 or 0).
8054 */
8055 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
8056 {
8057 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
8058 }
8059
8060 /**
8061 * @brief Get state of interruption ADC group regular overrun
8062 * (0: interrupt disabled, 1: interrupt enabled).
8063 * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
8064 * @param ADCx ADC instance
8065 * @retval State of bit (1 or 0).
8066 */
8067 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
8068 {
8069 return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
8070 }
8071
8072 /**
8073 * @brief Get state of interruption ADC group regular end of sampling
8074 * (0: interrupt disabled, 1: interrupt enabled).
8075 * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
8076 * @param ADCx ADC instance
8077 * @retval State of bit (1 or 0).
8078 */
8079 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
8080 {
8081 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
8082 }
8083
8084 /**
8085 * @brief Get state of interruption ADC group injected end of unitary conversion
8086 * (0: interrupt disabled, 1: interrupt enabled).
8087 * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC
8088 * @param ADCx ADC instance
8089 * @retval State of bit (1 or 0).
8090 */
8091 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)
8092 {
8093 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);
8094 }
8095
8096 /**
8097 * @brief Get state of interruption ADC group injected end of sequence conversions
8098 * (0: interrupt disabled, 1: interrupt enabled).
8099 * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS
8100 * @param ADCx ADC instance
8101 * @retval State of bit (1 or 0).
8102 */
8103 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
8104 {
8105 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);
8106 }
8107
8108 /**
8109 * @brief Get state of interruption ADC group injected context queue overflow interrupt state
8110 * (0: interrupt disabled, 1: interrupt enabled).
8111 * @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF
8112 * @param ADCx ADC instance
8113 * @retval State of bit (1 or 0).
8114 */
8115 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)
8116 {
8117 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);
8118 }
8119
8120 /**
8121 * @brief Get state of interruption ADC analog watchdog 1
8122 * (0: interrupt disabled, 1: interrupt enabled).
8123 * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
8124 * @param ADCx ADC instance
8125 * @retval State of bit (1 or 0).
8126 */
8127 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
8128 {
8129 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
8130 }
8131
8132 /**
8133 * @brief Get state of interruption Get ADC analog watchdog 2
8134 * (0: interrupt disabled, 1: interrupt enabled).
8135 * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
8136 * @param ADCx ADC instance
8137 * @retval State of bit (1 or 0).
8138 */
8139 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
8140 {
8141 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
8142 }
8143
8144 /**
8145 * @brief Get state of interruption Get ADC analog watchdog 3
8146 * (0: interrupt disabled, 1: interrupt enabled).
8147 * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
8148 * @param ADCx ADC instance
8149 * @retval State of bit (1 or 0).
8150 */
8151 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
8152 {
8153 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
8154 }
8155
8156 /**
8157 * @}
8158 */
8159
8160 #if defined(USE_FULL_LL_DRIVER)
8161 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
8162 * @{
8163 */
8164
8165 /* Initialization of some features of ADC common parameters and multimode */
8166 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
8167 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
8168 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
8169
8170 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
8171 /* (availability of ADC group injected depends on STM32 families) */
8172 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
8173
8174 /* Initialization of some features of ADC instance */
8175 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
8176 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
8177
8178 /* Initialization of some features of ADC instance and ADC group regular */
8179 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
8180 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
8181
8182 /* Initialization of some features of ADC instance and ADC group injected */
8183 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
8184 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
8185
8186 /**
8187 * @}
8188 */
8189 #endif /* USE_FULL_LL_DRIVER */
8190
8191 /**
8192 * @}
8193 */
8194
8195 /**
8196 * @}
8197 */
8198
8199 #endif /* ADC1 || ADC2 || ADC3 */
8200
8201 /**
8202 * @}
8203 */
8204
8205 #ifdef __cplusplus
8206 }
8207 #endif
8208
8209 #endif /* STM32H7xx_LL_ADC_H */
8210
8211 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/