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Merge pull request #11270 from haslinghuis/rename_attr
[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_ll_bdma.h
blob9faa900b8c74a0fb52ed374d1b186b967cfe6278
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_bdma.h
4 * @author MCD Application Team
5 * @brief Header file of BDMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_LL_BDMA_H
22 #define STM32H7xx_LL_BDMA_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx.h"
30 #include "stm32h7xx_ll_dmamux.h"
31
32 /** @addtogroup STM32H7xx_LL_Driver
33 * @{
34 */
35
36 #if defined (BDMA) || defined (BDMA1) || defined (BDMA2)
37
38 /** @defgroup BDMA_LL BDMA
39 * @{
40 */
41
42 /* Private types -------------------------------------------------------------*/
43 /* Private variables ---------------------------------------------------------*/
44 /** @defgroup BDMA_LL_Private_Variables BDMA Private Variables
45 * @{
46 */
47 /* Array used to get the BDMA channel register offset versus channel index LL_BDMA_CHANNEL_x */
48 static const uint8_t LL_BDMA_CH_OFFSET_TAB[] =
49 {
50 (uint8_t)(BDMA_Channel0_BASE - BDMA_BASE),
51 (uint8_t)(BDMA_Channel1_BASE - BDMA_BASE),
52 (uint8_t)(BDMA_Channel2_BASE - BDMA_BASE),
53 (uint8_t)(BDMA_Channel3_BASE - BDMA_BASE),
54 (uint8_t)(BDMA_Channel4_BASE - BDMA_BASE),
55 (uint8_t)(BDMA_Channel5_BASE - BDMA_BASE),
56 (uint8_t)(BDMA_Channel6_BASE - BDMA_BASE),
57 (uint8_t)(BDMA_Channel7_BASE - BDMA_BASE)
58 };
59 /**
60 * @}
61 */
62
63 /* Private constants ---------------------------------------------------------*/
64 /* Private macros ------------------------------------------------------------*/
65 #if !defined(UNUSED)
66 #define UNUSED(x) ((void)(x))
67 #endif
68
69 /* Exported types ------------------------------------------------------------*/
70 #if defined(USE_FULL_LL_DRIVER)
71 /** @defgroup BDMA_LL_ES_INIT BDMA Exported Init structure
72 * @{
73 */
74 typedef struct
75 {
76 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for BDMA transfer
77 or as Source base address in case of memory to memory transfer direction.
78
79 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
80
81 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
82 or as Destination base address in case of memory to memory transfer direction.
83
84 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
85
86 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
87 from memory to memory or from peripheral to memory.
88 This parameter can be a value of @ref BDMA_LL_EC_DIRECTION
89
90 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataTransferDirection(). */
91
92 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
93 This parameter can be a value of @ref BDMA_LL_EC_MODE
94 @note: The circular buffer mode cannot be used if the memory to memory
95 data transfer direction is configured on the selected Channel
96
97 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMode(). */
98
99 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
100 is incremented or not.
101 This parameter can be a value of @ref BDMA_LL_EC_PERIPH
102
103 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphIncMode(). */
104
105 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
106 is incremented or not.
107 This parameter can be a value of @ref BDMA_LL_EC_MEMORY
108
109 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMemoryIncMode(). */
110
111 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
112 in case of memory to memory transfer direction.
113 This parameter can be a value of @ref BDMA_LL_EC_PDATAALIGN
114
115 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphSize(). */
116
117 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
118 in case of memory to memory transfer direction.
119 This parameter can be a value of @ref BDMA_LL_EC_MDATAALIGN
120
121 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMemorySize(). */
122
123 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
124 The data unit is equal to the source buffer configuration set in PeripheralSize
125 or MemorySize parameters depending in the transfer direction.
126 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
127
128 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataLength(). */
129
130 uint32_t PeriphRequest; /*!< Specifies the peripheral request.
131 This parameter can be a value of @ref DMAMUX2_Request_selection
132
133 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphRequest(). */
134
135 uint32_t Priority; /*!< Specifies the channel priority level.
136 This parameter can be a value of @ref BDMA_LL_EC_PRIORITY
137
138 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetChannelPriorityLevel(). */
139
140 } LL_BDMA_InitTypeDef;
141 /**
142 * @}
143 */
144 #endif /* USE_FULL_LL_DRIVER */
145
146 /* Exported constants --------------------------------------------------------*/
147 /** @defgroup BDMA_LL_Exported_Constants BDMA Exported Constants
148 * @{
149 */
150 /** @defgroup BDMA_LL_EC_CLEAR_FLAG Clear Flags Defines
151 * @brief Flags defines which can be used with LL_BDMA_WriteReg function
152 * @{
153 */
154 #define LL_BDMA_IFCR_CGIF1 BDMA_IFCR_CGIF1 /*!< Channel 1 global flag */
155 #define LL_BDMA_IFCR_CTCIF1 BDMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
156 #define LL_BDMA_IFCR_CHTIF1 BDMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
157 #define LL_BDMA_IFCR_CTEIF1 BDMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
158 #define LL_BDMA_IFCR_CGIF2 BDMA_IFCR_CGIF2 /*!< Channel 2 global flag */
159 #define LL_BDMA_IFCR_CTCIF2 BDMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
160 #define LL_BDMA_IFCR_CHTIF2 BDMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
161 #define LL_BDMA_IFCR_CTEIF2 BDMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
162 #define LL_BDMA_IFCR_CGIF3 BDMA_IFCR_CGIF3 /*!< Channel 3 global flag */
163 #define LL_BDMA_IFCR_CTCIF3 BDMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
164 #define LL_BDMA_IFCR_CHTIF3 BDMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
165 #define LL_BDMA_IFCR_CTEIF3 BDMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
166 #define LL_BDMA_IFCR_CGIF4 BDMA_IFCR_CGIF4 /*!< Channel 4 global flag */
167 #define LL_BDMA_IFCR_CTCIF4 BDMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
168 #define LL_BDMA_IFCR_CHTIF4 BDMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
169 #define LL_BDMA_IFCR_CTEIF4 BDMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
170 #define LL_BDMA_IFCR_CGIF5 BDMA_IFCR_CGIF5 /*!< Channel 5 global flag */
171 #define LL_BDMA_IFCR_CTCIF5 BDMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
172 #define LL_BDMA_IFCR_CHTIF5 BDMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
173 #define LL_BDMA_IFCR_CTEIF5 BDMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
174 #define LL_BDMA_IFCR_CGIF6 BDMA_IFCR_CGIF6 /*!< Channel 6 global flag */
175 #define LL_BDMA_IFCR_CTCIF6 BDMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
176 #define LL_BDMA_IFCR_CHTIF6 BDMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
177 #define LL_BDMA_IFCR_CTEIF6 BDMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
178 #define LL_BDMA_IFCR_CGIF7 BDMA_IFCR_CGIF7 /*!< Channel 7 global flag */
179 #define LL_BDMA_IFCR_CTCIF7 BDMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
180 #define LL_BDMA_IFCR_CHTIF7 BDMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
181 #define LL_BDMA_IFCR_CTEIF7 BDMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
182 /**
183 * @}
184 */
185
186 /** @defgroup BDMA_LL_EC_GET_FLAG Get Flags Defines
187 * @brief Flags defines which can be used with LL_BDMA_ReadReg function
188 * @{
189 */
190 #define LL_BDMA_ISR_GIF0 BDMA_ISR_GIF0 /*!< Channel 1 global flag */
191 #define LL_BDMA_ISR_TCIF0 BDMA_ISR_TCIF0 /*!< Channel 1 transfer complete flag */
192 #define LL_BDMA_ISR_HTIF0 BDMA_ISR_HTIF0 /*!< Channel 1 half transfer flag */
193 #define LL_BDMA_ISR_TEIF0 BDMA_ISR_TEIF0 /*!< Channel 1 transfer error flag */
194 #define LL_BDMA_ISR_GIF1 BDMA_ISR_GIF1 /*!< Channel 1 global flag */
195 #define LL_BDMA_ISR_TCIF1 BDMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
196 #define LL_BDMA_ISR_HTIF1 BDMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
197 #define LL_BDMA_ISR_TEIF1 BDMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
198 #define LL_BDMA_ISR_GIF2 BDMA_ISR_GIF2 /*!< Channel 2 global flag */
199 #define LL_BDMA_ISR_TCIF2 BDMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
200 #define LL_BDMA_ISR_HTIF2 BDMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
201 #define LL_BDMA_ISR_TEIF2 BDMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
202 #define LL_BDMA_ISR_GIF3 BDMA_ISR_GIF3 /*!< Channel 3 global flag */
203 #define LL_BDMA_ISR_TCIF3 BDMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
204 #define LL_BDMA_ISR_HTIF3 BDMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
205 #define LL_BDMA_ISR_TEIF3 BDMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
206 #define LL_BDMA_ISR_GIF4 BDMA_ISR_GIF4 /*!< Channel 4 global flag */
207 #define LL_BDMA_ISR_TCIF4 BDMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
208 #define LL_BDMA_ISR_HTIF4 BDMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
209 #define LL_BDMA_ISR_TEIF4 BDMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
210 #define LL_BDMA_ISR_GIF5 BDMA_ISR_GIF5 /*!< Channel 5 global flag */
211 #define LL_BDMA_ISR_TCIF5 BDMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
212 #define LL_BDMA_ISR_HTIF5 BDMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
213 #define LL_BDMA_ISR_TEIF5 BDMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
214 #define LL_BDMA_ISR_GIF6 BDMA_ISR_GIF6 /*!< Channel 6 global flag */
215 #define LL_BDMA_ISR_TCIF6 BDMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
216 #define LL_BDMA_ISR_HTIF6 BDMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
217 #define LL_BDMA_ISR_TEIF6 BDMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
218 #define LL_BDMA_ISR_GIF7 BDMA_ISR_GIF7 /*!< Channel 7 global flag */
219 #define LL_BDMA_ISR_TCIF7 BDMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
220 #define LL_BDMA_ISR_HTIF7 BDMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
221 #define LL_BDMA_ISR_TEIF7 BDMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
222 /**
223 * @}
224 */
225
226 /** @defgroup BDMA_LL_EC_IT IT Defines
227 * @brief IT defines which can be used with LL_BDMA_ReadReg and LL_BDMA_WriteReg functions
228 * @{
229 */
230 #define LL_BDMA_CCR_TCIE BDMA_CCR_TCIE /*!< Transfer complete interrupt */
231 #define LL_BDMA_CCR_HTIE BDMA_CCR_HTIE /*!< Half Transfer interrupt */
232 #define LL_BDMA_CCR_TEIE BDMA_CCR_TEIE /*!< Transfer error interrupt */
233 /**
234 * @}
235 */
236
237 /** @defgroup BDMA_LL_EC_CHANNEL CHANNEL
238 * @{
239 */
240 #define LL_BDMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */
241 #define LL_BDMA_CHANNEL_1 0x00000001U /*!< BDMA Channel 1 */
242 #define LL_BDMA_CHANNEL_2 0x00000002U /*!< BDMA Channel 2 */
243 #define LL_BDMA_CHANNEL_3 0x00000003U /*!< BDMA Channel 3 */
244 #define LL_BDMA_CHANNEL_4 0x00000004U /*!< BDMA Channel 4 */
245 #define LL_BDMA_CHANNEL_5 0x00000005U /*!< BDMA Channel 5 */
246 #define LL_BDMA_CHANNEL_6 0x00000006U /*!< BDMA Channel 6 */
247 #define LL_BDMA_CHANNEL_7 0x00000007U /*!< BDMA Channel 7 */
248 #if defined(USE_FULL_LL_DRIVER)
249 #define LL_BDMA_CHANNEL_ALL 0xFFFF0000U /*!< BDMA Channel all (used only for function @ref LL_BDMA_DeInit(). */
250 #endif /*USE_FULL_LL_DRIVER*/
251 /**
252 * @}
253 */
254
255 /** @defgroup BDMA_LL_EC_DIRECTION Transfer Direction
256 * @{
257 */
258 #define LL_BDMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
259 #define LL_BDMA_DIRECTION_MEMORY_TO_PERIPH BDMA_CCR_DIR /*!< Memory to peripheral direction */
260 #define LL_BDMA_DIRECTION_MEMORY_TO_MEMORY BDMA_CCR_MEM2MEM /*!< Memory to memory direction */
261 /**
262 * @}
263 */
264
265 /** @defgroup BDMA_LL_EC_MODE Transfer mode
266 * @{
267 */
268 #define LL_BDMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
269 #define LL_BDMA_MODE_CIRCULAR BDMA_CCR_CIRC /*!< Circular Mode */
270 /**
271 * @}
272 */
273
274 /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
275 * @{
276 */
277 #define LL_BDMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */
278 #define LL_BDMA_DOUBLEBUFFER_MODE_ENABLE BDMA_CCR_DBM /*!< Enable double buffering mode */
279 /**
280 * @}
281 */
282
283 /** @defgroup BDMA_LL_EC_PERIPH Peripheral increment mode
284 * @{
285 */
286 #define LL_BDMA_PERIPH_INCREMENT BDMA_CCR_PINC /*!< Peripheral increment mode Enable */
287 #define LL_BDMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
288 /**
289 * @}
290 */
291
292 /** @defgroup BDMA_LL_EC_MEMORY Memory increment mode
293 * @{
294 */
295 #define LL_BDMA_MEMORY_INCREMENT BDMA_CCR_MINC /*!< Memory increment mode Enable */
296 #define LL_BDMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
297 /**
298 * @}
299 */
300
301 /** @defgroup BDMA_LL_EC_PDATAALIGN Peripheral data alignment
302 * @{
303 */
304 #define LL_BDMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
305 #define LL_BDMA_PDATAALIGN_HALFWORD BDMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
306 #define LL_BDMA_PDATAALIGN_WORD BDMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
307 /**
308 * @}
309 */
310
311 /** @defgroup BDMA_LL_EC_MDATAALIGN Memory data alignment
312 * @{
313 */
314 #define LL_BDMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
315 #define LL_BDMA_MDATAALIGN_HALFWORD BDMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
316 #define LL_BDMA_MDATAALIGN_WORD BDMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
317 /**
318 * @}
319 */
320
321 /** @defgroup BDMA_LL_EC_PRIORITY Transfer Priority level
322 * @{
323 */
324 #define LL_BDMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
325 #define LL_BDMA_PRIORITY_MEDIUM BDMA_CCR_PL_0 /*!< Priority level : Medium */
326 #define LL_BDMA_PRIORITY_HIGH BDMA_CCR_PL_1 /*!< Priority level : High */
327 #define LL_BDMA_PRIORITY_VERYHIGH BDMA_CCR_PL /*!< Priority level : Very_High */
328 /**
329 * @}
330 */
331
332 /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
333 * @{
334 */
335 #define LL_BDMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */
336 #define LL_BDMA_CURRENTTARGETMEM1 BDMA_CCR_CT /*!< Set CurrentTarget Memory to Memory 1 */
337 /**
338 * @}
339 */
340
341 /* Exported macro ------------------------------------------------------------*/
342 /** @defgroup BDMA_LL_Exported_Macros BDMA Exported Macros
343 * @{
344 */
345
346 /** @defgroup BDMA_LL_EM_WRITE_READ Common Write and read registers macros
347 * @{
348 */
349 /**
350 * @brief Write a value in BDMA register
351 * @param __INSTANCE__ BDMA Instance
352 * @param __REG__ Register to be written
353 * @param __VALUE__ Value to be written in the register
354 * @retval None
355 */
356 #define LL_BDMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
357
358 /**
359 * @brief Read a value in BDMA register
360 * @param __INSTANCE__ BDMA Instance
361 * @param __REG__ Register to be read
362 * @retval Register value
363 */
364 #define LL_BDMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
365 /**
366 * @}
367 */
368
369 /** @defgroup BDMA_LL_EM_CONVERT_DMAxCHANNELy Convert BDMAxChannely
370 * @{
371 */
372 /**
373 * @brief Convert BDMAx_Channely into BDMAx
374 * @param __CHANNEL_INSTANCE__ BDMAx_Channely
375 * @retval BDMAx
376 */
377 #if defined (BDMA1)
378 #define __LL_BDMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
379 (((uint32_t)(__CHANNEL_INSTANCE__) < LL_BDMA_CHANNEL_0) ? BDMA1 : BDMA)
380 #else
381 #define __LL_BDMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (BDMA)
382 #endif /* BDMA1 */
383
384 /**
385 * @brief Convert BDMAx_Channely into LL_BDMA_CHANNEL_y
386 * @param __CHANNEL_INSTANCE__ BDMAx_Channely
387 * @retval LL_BDMA_CHANNEL_y
388 */
389 #if defined (BDMA1)
390 #define __LL_BDMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
391 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel0)) ? LL_BDMA_CHANNEL_0 : \
392 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel0)) ? LL_BDMA_CHANNEL_0 : \
393 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel1)) ? LL_BDMA_CHANNEL_1 : \
394 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel1)) ? LL_BDMA_CHANNEL_1 : \
395 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel2)) ? LL_BDMA_CHANNEL_2 : \
396 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel2)) ? LL_BDMA_CHANNEL_2 : \
397 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel3)) ? LL_BDMA_CHANNEL_3 : \
398 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel3)) ? LL_BDMA_CHANNEL_3 : \
399 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel4)) ? LL_BDMA_CHANNEL_4 : \
400 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel4)) ? LL_BDMA_CHANNEL_4 : \
401 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel5)) ? LL_BDMA_CHANNEL_5 : \
402 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel5)) ? LL_BDMA_CHANNEL_5 : \
403 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel6)) ? LL_BDMA_CHANNEL_6 : \
404 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel6)) ? LL_BDMA_CHANNEL_6 : \
405 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel7)) ? LL_BDMA_CHANNEL_7 : \
406 LL_BDMA_CHANNEL_7)
407 #else
408 #define __LL_BDMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
409 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel0)) ? LL_BDMA_CHANNEL_0 : \
410 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel1)) ? LL_BDMA_CHANNEL_1 : \
411 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel2)) ? LL_BDMA_CHANNEL_2 : \
412 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel3)) ? LL_BDMA_CHANNEL_3 : \
413 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel4)) ? LL_BDMA_CHANNEL_4 : \
414 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel5)) ? LL_BDMA_CHANNEL_5 : \
415 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel6)) ? LL_BDMA_CHANNEL_6 : \
416 LL_BDMA_CHANNEL_7)
417 #endif /* BDMA1 */
418
419 /**
420 * @brief Convert BDMA Instance BDMAx and LL_BDMA_CHANNEL_y into BDMAx_Channely
421 * @param __BDMA_INSTANCE__ BDMAx
422 * @param __CHANNEL__ LL_BDMA_CHANNEL_y
423 * @retval BDMAx_Channely
424 */
425 #if defined (BDMA1)
426 #define __LL_BDMA_GET_CHANNEL_INSTANCE(__BDMA_INSTANCE__, __CHANNEL__) \
427 ((((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA_Channel0 : \
428 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA1_Channel0 : \
429 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA_Channel1 : \
430 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA1_Channel1 : \
431 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA_Channel2 : \
432 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA1_Channel2 : \
433 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA_Channel3 : \
434 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA1_Channel3 : \
435 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA_Channel4 : \
436 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA1_Channel4 : \
437 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA_Channel5 : \
438 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA1_Channel5 : \
439 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA_Channel6 : \
440 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA1_Channel6 : \
441 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_7))) ? BDMA_Channel7 : \
442 BDMA1_Channel7)
443 #else
444 #define __LL_BDMA_GET_CHANNEL_INSTANCE(__BDMA_INSTANCE__, __CHANNEL__) \
445 ((((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA_Channel0 : \
446 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA_Channel1 : \
447 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA_Channel2 : \
448 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA_Channel3 : \
449 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA_Channel4 : \
450 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA_Channel5 : \
451 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA_Channel6 : \
452 BDMA_Channel7)
453 #endif /* BDMA1 */
454 /**
455 * @}
456 */
457
458 /**
459 * @}
460 */
461
462 /* Exported functions --------------------------------------------------------*/
463 /** @defgroup BDMA_LL_Exported_Functions BDMA Exported Functions
464 * @{
465 */
466
467 /** @defgroup BDMA_LL_EF_Configuration Configuration
468 * @{
469 */
470 /**
471 * @brief Enable BDMA channel.
472 * @rmtoll CCR EN LL_BDMA_EnableChannel
473 * @param BDMAx BDMA Instance
474 * @param Channel This parameter can be one of the following values:
475 * @arg @ref LL_BDMA_CHANNEL_0
476 * @arg @ref LL_BDMA_CHANNEL_1
477 * @arg @ref LL_BDMA_CHANNEL_2
478 * @arg @ref LL_BDMA_CHANNEL_3
479 * @arg @ref LL_BDMA_CHANNEL_4
480 * @arg @ref LL_BDMA_CHANNEL_5
481 * @arg @ref LL_BDMA_CHANNEL_6
482 * @arg @ref LL_BDMA_CHANNEL_7
483 * @retval None
484 */
485 __STATIC_INLINE void LL_BDMA_EnableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel)
486 {
487 uint32_t bdma_base_addr = (uint32_t)BDMAx;
488
489 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN);
490 }
491
492 /**
493 * @brief Disable BDMA channel.
494 * @rmtoll CCR EN LL_BDMA_DisableChannel
495 * @param BDMAx BDMA Instance
496 * @param Channel This parameter can be one of the following values:
497 * @arg @ref LL_BDMA_CHANNEL_0
498 * @arg @ref LL_BDMA_CHANNEL_1
499 * @arg @ref LL_BDMA_CHANNEL_2
500 * @arg @ref LL_BDMA_CHANNEL_3
501 * @arg @ref LL_BDMA_CHANNEL_4
502 * @arg @ref LL_BDMA_CHANNEL_5
503 * @arg @ref LL_BDMA_CHANNEL_6
504 * @arg @ref LL_BDMA_CHANNEL_7
505 * @retval None
506 */
507 __STATIC_INLINE void LL_BDMA_DisableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel)
508 {
509 uint32_t bdma_base_addr = (uint32_t)BDMAx;
510
511 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN);
512 }
513
514 /**
515 * @brief Check if BDMA channel is enabled or disabled.
516 * @rmtoll CCR EN LL_BDMA_IsEnabledChannel
517 * @param BDMAx BDMA Instance
518 * @param Channel This parameter can be one of the following values:
519 * @arg @ref LL_BDMA_CHANNEL_0
520 * @arg @ref LL_BDMA_CHANNEL_1
521 * @arg @ref LL_BDMA_CHANNEL_2
522 * @arg @ref LL_BDMA_CHANNEL_3
523 * @arg @ref LL_BDMA_CHANNEL_4
524 * @arg @ref LL_BDMA_CHANNEL_5
525 * @arg @ref LL_BDMA_CHANNEL_6
526 * @arg @ref LL_BDMA_CHANNEL_7
527 * @retval State of bit (1 or 0).
528 */
529 __STATIC_INLINE uint32_t LL_BDMA_IsEnabledChannel(BDMA_TypeDef *BDMAx, uint32_t Channel)
530 {
531 uint32_t bdma_base_addr = (uint32_t)BDMAx;
532
533 return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN) == (BDMA_CCR_EN)) ? 1UL : 0UL);
534 }
535
536 /**
537 * @brief Configure all parameters link to BDMA transfer.
538 * @rmtoll CCR DIR LL_BDMA_ConfigTransfer\n
539 * CCR MEM2MEM LL_BDMA_ConfigTransfer\n
540 * CCR CIRC LL_BDMA_ConfigTransfer\n
541 * CCR PINC LL_BDMA_ConfigTransfer\n
542 * CCR MINC LL_BDMA_ConfigTransfer\n
543 * CCR PSIZE LL_BDMA_ConfigTransfer\n
544 * CCR MSIZE LL_BDMA_ConfigTransfer\n
545 * CCR PL LL_BDMA_ConfigTransfer
546 * @param BDMAx BDMA Instance
547 * @param Channel This parameter can be one of the following values:
548 * @arg @ref LL_BDMA_CHANNEL_0
549 * @arg @ref LL_BDMA_CHANNEL_1
550 * @arg @ref LL_BDMA_CHANNEL_2
551 * @arg @ref LL_BDMA_CHANNEL_3
552 * @arg @ref LL_BDMA_CHANNEL_4
553 * @arg @ref LL_BDMA_CHANNEL_5
554 * @arg @ref LL_BDMA_CHANNEL_6
555 * @arg @ref LL_BDMA_CHANNEL_7
556 * @param Configuration This parameter must be a combination of all the following values:
557 * @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY
558 * @arg @ref LL_BDMA_MODE_NORMAL or @ref LL_BDMA_MODE_CIRCULAR
559 * @arg @ref LL_BDMA_PERIPH_INCREMENT or @ref LL_BDMA_PERIPH_NOINCREMENT
560 * @arg @ref LL_BDMA_MEMORY_INCREMENT or @ref LL_BDMA_MEMORY_NOINCREMENT
561 * @arg @ref LL_BDMA_PDATAALIGN_BYTE or @ref LL_BDMA_PDATAALIGN_HALFWORD or @ref LL_BDMA_PDATAALIGN_WORD
562 * @arg @ref LL_BDMA_MDATAALIGN_BYTE or @ref LL_BDMA_MDATAALIGN_HALFWORD or @ref LL_BDMA_MDATAALIGN_WORD
563 * @arg @ref LL_BDMA_PRIORITY_LOW or @ref LL_BDMA_PRIORITY_MEDIUM or @ref LL_BDMA_PRIORITY_HIGH or @ref LL_BDMA_PRIORITY_VERYHIGH
564 * @retval None
565 */
566 __STATIC_INLINE void LL_BDMA_ConfigTransfer(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Configuration)
567 {
568 uint32_t bdma_base_addr = (uint32_t)BDMAx;
569
570 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
571 BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_CIRC | BDMA_CCR_PINC | BDMA_CCR_MINC | BDMA_CCR_PSIZE | BDMA_CCR_MSIZE | BDMA_CCR_PL,
572 Configuration);
573 }
574
575 /**
576 * @brief Set Data transfer direction (read from peripheral or from memory).
577 * @rmtoll CCR DIR LL_BDMA_SetDataTransferDirection\n
578 * CCR MEM2MEM LL_BDMA_SetDataTransferDirection
579 * @param BDMAx BDMA Instance
580 * @param Channel This parameter can be one of the following values:
581 * @arg @ref LL_BDMA_CHANNEL_0
582 * @arg @ref LL_BDMA_CHANNEL_1
583 * @arg @ref LL_BDMA_CHANNEL_2
584 * @arg @ref LL_BDMA_CHANNEL_3
585 * @arg @ref LL_BDMA_CHANNEL_4
586 * @arg @ref LL_BDMA_CHANNEL_5
587 * @arg @ref LL_BDMA_CHANNEL_6
588 * @arg @ref LL_BDMA_CHANNEL_7
589 * @param Direction This parameter can be one of the following values:
590 * @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY
591 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH
592 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY
593 * @retval None
594 */
595 __STATIC_INLINE void LL_BDMA_SetDataTransferDirection(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Direction)
596 {
597 uint32_t bdma_base_addr = (uint32_t)BDMAx;
598
599 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
600 BDMA_CCR_DIR | BDMA_CCR_MEM2MEM, Direction);
601 }
602
603 /**
604 * @brief Get Data transfer direction (read from peripheral or from memory).
605 * @rmtoll CCR DIR LL_BDMA_GetDataTransferDirection\n
606 * CCR MEM2MEM LL_BDMA_GetDataTransferDirection
607 * @param BDMAx BDMA Instance
608 * @param Channel This parameter can be one of the following values:
609 * @arg @ref LL_BDMA_CHANNEL_0
610 * @arg @ref LL_BDMA_CHANNEL_1
611 * @arg @ref LL_BDMA_CHANNEL_2
612 * @arg @ref LL_BDMA_CHANNEL_3
613 * @arg @ref LL_BDMA_CHANNEL_4
614 * @arg @ref LL_BDMA_CHANNEL_5
615 * @arg @ref LL_BDMA_CHANNEL_6
616 * @arg @ref LL_BDMA_CHANNEL_7
617 * @retval Returned value can be one of the following values:
618 * @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY
619 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH
620 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY
621 */
622 __STATIC_INLINE uint32_t LL_BDMA_GetDataTransferDirection(BDMA_TypeDef *BDMAx, uint32_t Channel)
623 {
624 uint32_t bdma_base_addr = (uint32_t)BDMAx;
625
626 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
627 BDMA_CCR_DIR | BDMA_CCR_MEM2MEM));
628 }
629
630 /**
631 * @brief Set BDMA mode circular or normal.
632 * @note The circular buffer mode cannot be used if the memory-to-memory
633 * data transfer is configured on the selected Channel.
634 * @rmtoll CCR CIRC LL_BDMA_SetMode
635 * @param BDMAx BDMA Instance
636 * @param Channel This parameter can be one of the following values:
637 * @arg @ref LL_BDMA_CHANNEL_0
638 * @arg @ref LL_BDMA_CHANNEL_1
639 * @arg @ref LL_BDMA_CHANNEL_2
640 * @arg @ref LL_BDMA_CHANNEL_3
641 * @arg @ref LL_BDMA_CHANNEL_4
642 * @arg @ref LL_BDMA_CHANNEL_5
643 * @arg @ref LL_BDMA_CHANNEL_6
644 * @arg @ref LL_BDMA_CHANNEL_7
645 * @param Mode This parameter can be one of the following values:
646 * @arg @ref LL_BDMA_MODE_NORMAL
647 * @arg @ref LL_BDMA_MODE_CIRCULAR
648 * @retval None
649 */
650 __STATIC_INLINE void LL_BDMA_SetMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Mode)
651 {
652 uint32_t bdma_base_addr = (uint32_t)BDMAx;
653
654 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CIRC,
655 Mode);
656 }
657
658 /**
659 * @brief Get BDMA mode circular or normal.
660 * @rmtoll CCR CIRC LL_BDMA_GetMode
661 * @param BDMAx BDMA Instance
662 * @param Channel This parameter can be one of the following values:
663 * @arg @ref LL_BDMA_CHANNEL_0
664 * @arg @ref LL_BDMA_CHANNEL_1
665 * @arg @ref LL_BDMA_CHANNEL_2
666 * @arg @ref LL_BDMA_CHANNEL_3
667 * @arg @ref LL_BDMA_CHANNEL_4
668 * @arg @ref LL_BDMA_CHANNEL_5
669 * @arg @ref LL_BDMA_CHANNEL_6
670 * @arg @ref LL_BDMA_CHANNEL_7
671 * @retval Returned value can be one of the following values:
672 * @arg @ref LL_BDMA_MODE_NORMAL
673 * @arg @ref LL_BDMA_MODE_CIRCULAR
674 */
675 __STATIC_INLINE uint32_t LL_BDMA_GetMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
676 {
677 uint32_t bdma_base_addr = (uint32_t)BDMAx;
678
679 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
680 BDMA_CCR_CIRC));
681 }
682
683 /**
684 * @brief Set Peripheral increment mode.
685 * @rmtoll CCR PINC LL_BDMA_SetPeriphIncMode
686 * @param BDMAx BDMA Instance
687 * @param Channel This parameter can be one of the following values:
688 * @arg @ref LL_BDMA_CHANNEL_0
689 * @arg @ref LL_BDMA_CHANNEL_1
690 * @arg @ref LL_BDMA_CHANNEL_2
691 * @arg @ref LL_BDMA_CHANNEL_3
692 * @arg @ref LL_BDMA_CHANNEL_4
693 * @arg @ref LL_BDMA_CHANNEL_5
694 * @arg @ref LL_BDMA_CHANNEL_6
695 * @arg @ref LL_BDMA_CHANNEL_7
696 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
697 * @arg @ref LL_BDMA_PERIPH_INCREMENT
698 * @arg @ref LL_BDMA_PERIPH_NOINCREMENT
699 * @retval None
700 */
701 __STATIC_INLINE void LL_BDMA_SetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
702 {
703 uint32_t bdma_base_addr = (uint32_t)BDMAx;
704
705 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PINC,
706 PeriphOrM2MSrcIncMode);
707 }
708
709 /**
710 * @brief Get Peripheral increment mode.
711 * @rmtoll CCR PINC LL_BDMA_GetPeriphIncMode
712 * @param BDMAx BDMA Instance
713 * @param Channel This parameter can be one of the following values:
714 * @arg @ref LL_BDMA_CHANNEL_0
715 * @arg @ref LL_BDMA_CHANNEL_1
716 * @arg @ref LL_BDMA_CHANNEL_2
717 * @arg @ref LL_BDMA_CHANNEL_3
718 * @arg @ref LL_BDMA_CHANNEL_4
719 * @arg @ref LL_BDMA_CHANNEL_5
720 * @arg @ref LL_BDMA_CHANNEL_6
721 * @arg @ref LL_BDMA_CHANNEL_7
722 * @retval Returned value can be one of the following values:
723 * @arg @ref LL_BDMA_PERIPH_INCREMENT
724 * @arg @ref LL_BDMA_PERIPH_NOINCREMENT
725 */
726 __STATIC_INLINE uint32_t LL_BDMA_GetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
727 {
728 uint32_t bdma_base_addr = (uint32_t)BDMAx;
729
730 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
731 BDMA_CCR_PINC));
732 }
733
734 /**
735 * @brief Set Memory increment mode.
736 * @rmtoll CCR MINC LL_BDMA_SetMemoryIncMode
737 * @param BDMAx BDMA Instance
738 * @param Channel This parameter can be one of the following values:
739 * @arg @ref LL_BDMA_CHANNEL_0
740 * @arg @ref LL_BDMA_CHANNEL_1
741 * @arg @ref LL_BDMA_CHANNEL_2
742 * @arg @ref LL_BDMA_CHANNEL_3
743 * @arg @ref LL_BDMA_CHANNEL_4
744 * @arg @ref LL_BDMA_CHANNEL_5
745 * @arg @ref LL_BDMA_CHANNEL_6
746 * @arg @ref LL_BDMA_CHANNEL_7
747 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
748 * @arg @ref LL_BDMA_MEMORY_INCREMENT
749 * @arg @ref LL_BDMA_MEMORY_NOINCREMENT
750 * @retval None
751 */
752 __STATIC_INLINE void LL_BDMA_SetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
753 {
754 uint32_t bdma_base_addr = (uint32_t)BDMAx;
755
756 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_MINC,
757 MemoryOrM2MDstIncMode);
758 }
759
760 /**
761 * @brief Get Memory increment mode.
762 * @rmtoll CCR MINC LL_BDMA_GetMemoryIncMode
763 * @param BDMAx BDMA Instance
764 * @param Channel This parameter can be one of the following values:
765 * @arg @ref LL_BDMA_CHANNEL_0
766 * @arg @ref LL_BDMA_CHANNEL_1
767 * @arg @ref LL_BDMA_CHANNEL_2
768 * @arg @ref LL_BDMA_CHANNEL_3
769 * @arg @ref LL_BDMA_CHANNEL_4
770 * @arg @ref LL_BDMA_CHANNEL_5
771 * @arg @ref LL_BDMA_CHANNEL_6
772 * @arg @ref LL_BDMA_CHANNEL_7
773 * @retval Returned value can be one of the following values:
774 * @arg @ref LL_BDMA_MEMORY_INCREMENT
775 * @arg @ref LL_BDMA_MEMORY_NOINCREMENT
776 */
777 __STATIC_INLINE uint32_t LL_BDMA_GetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
778 {
779 uint32_t bdma_base_addr = (uint32_t)BDMAx;
780
781 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
782 BDMA_CCR_MINC));
783 }
784
785 /**
786 * @brief Set Peripheral size.
787 * @rmtoll CCR PSIZE LL_BDMA_SetPeriphSize
788 * @param BDMAx BDMA Instance
789 * @param Channel This parameter can be one of the following values:
790 * @arg @ref LL_BDMA_CHANNEL_0
791 * @arg @ref LL_BDMA_CHANNEL_1
792 * @arg @ref LL_BDMA_CHANNEL_2
793 * @arg @ref LL_BDMA_CHANNEL_3
794 * @arg @ref LL_BDMA_CHANNEL_4
795 * @arg @ref LL_BDMA_CHANNEL_5
796 * @arg @ref LL_BDMA_CHANNEL_6
797 * @arg @ref LL_BDMA_CHANNEL_7
798 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
799 * @arg @ref LL_BDMA_PDATAALIGN_BYTE
800 * @arg @ref LL_BDMA_PDATAALIGN_HALFWORD
801 * @arg @ref LL_BDMA_PDATAALIGN_WORD
802 * @retval None
803 */
804 __STATIC_INLINE void LL_BDMA_SetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
805 {
806 uint32_t bdma_base_addr = (uint32_t)BDMAx;
807
808 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PSIZE,
809 PeriphOrM2MSrcDataSize);
810 }
811
812 /**
813 * @brief Get Peripheral size.
814 * @rmtoll CCR PSIZE LL_BDMA_GetPeriphSize
815 * @param BDMAx BDMA Instance
816 * @param Channel This parameter can be one of the following values:
817 * @arg @ref LL_BDMA_CHANNEL_0
818 * @arg @ref LL_BDMA_CHANNEL_1
819 * @arg @ref LL_BDMA_CHANNEL_2
820 * @arg @ref LL_BDMA_CHANNEL_3
821 * @arg @ref LL_BDMA_CHANNEL_4
822 * @arg @ref LL_BDMA_CHANNEL_5
823 * @arg @ref LL_BDMA_CHANNEL_6
824 * @arg @ref LL_BDMA_CHANNEL_7
825 * @retval Returned value can be one of the following values:
826 * @arg @ref LL_BDMA_PDATAALIGN_BYTE
827 * @arg @ref LL_BDMA_PDATAALIGN_HALFWORD
828 * @arg @ref LL_BDMA_PDATAALIGN_WORD
829 */
830 __STATIC_INLINE uint32_t LL_BDMA_GetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel)
831 {
832 uint32_t bdma_base_addr = (uint32_t)BDMAx;
833
834 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
835 BDMA_CCR_PSIZE));
836 }
837
838 /**
839 * @brief Set Memory size.
840 * @rmtoll CCR MSIZE LL_BDMA_SetMemorySize
841 * @param BDMAx BDMA Instance
842 * @param Channel This parameter can be one of the following values:
843 * @arg @ref LL_BDMA_CHANNEL_0
844 * @arg @ref LL_BDMA_CHANNEL_1
845 * @arg @ref LL_BDMA_CHANNEL_2
846 * @arg @ref LL_BDMA_CHANNEL_3
847 * @arg @ref LL_BDMA_CHANNEL_4
848 * @arg @ref LL_BDMA_CHANNEL_5
849 * @arg @ref LL_BDMA_CHANNEL_6
850 * @arg @ref LL_BDMA_CHANNEL_7
851 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
852 * @arg @ref LL_BDMA_MDATAALIGN_BYTE
853 * @arg @ref LL_BDMA_MDATAALIGN_HALFWORD
854 * @arg @ref LL_BDMA_MDATAALIGN_WORD
855 * @retval None
856 */
857 __STATIC_INLINE void LL_BDMA_SetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
858 {
859 uint32_t bdma_base_addr = (uint32_t)BDMAx;
860
861 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_MSIZE,
862 MemoryOrM2MDstDataSize);
863 }
864
865 /**
866 * @brief Get Memory size.
867 * @rmtoll CCR MSIZE LL_BDMA_GetMemorySize
868 * @param BDMAx BDMA Instance
869 * @param Channel This parameter can be one of the following values:
870 * @arg @ref LL_BDMA_CHANNEL_0
871 * @arg @ref LL_BDMA_CHANNEL_1
872 * @arg @ref LL_BDMA_CHANNEL_2
873 * @arg @ref LL_BDMA_CHANNEL_3
874 * @arg @ref LL_BDMA_CHANNEL_4
875 * @arg @ref LL_BDMA_CHANNEL_5
876 * @arg @ref LL_BDMA_CHANNEL_6
877 * @arg @ref LL_BDMA_CHANNEL_7
878 * @retval Returned value can be one of the following values:
879 * @arg @ref LL_BDMA_MDATAALIGN_BYTE
880 * @arg @ref LL_BDMA_MDATAALIGN_HALFWORD
881 * @arg @ref LL_BDMA_MDATAALIGN_WORD
882 */
883 __STATIC_INLINE uint32_t LL_BDMA_GetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel)
884 {
885 uint32_t bdma_base_addr = (uint32_t)BDMAx;
886
887 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
888 BDMA_CCR_MSIZE));
889 }
890
891 /**
892 * @brief Set Channel priority level.
893 * @rmtoll CCR PL LL_BDMA_SetChannelPriorityLevel
894 * @param BDMAx BDMA Instance
895 * @param Channel This parameter can be one of the following values:
896 * @arg @ref LL_BDMA_CHANNEL_0
897 * @arg @ref LL_BDMA_CHANNEL_1
898 * @arg @ref LL_BDMA_CHANNEL_2
899 * @arg @ref LL_BDMA_CHANNEL_3
900 * @arg @ref LL_BDMA_CHANNEL_4
901 * @arg @ref LL_BDMA_CHANNEL_5
902 * @arg @ref LL_BDMA_CHANNEL_6
903 * @arg @ref LL_BDMA_CHANNEL_7
904 * @param Priority This parameter can be one of the following values:
905 * @arg @ref LL_BDMA_PRIORITY_LOW
906 * @arg @ref LL_BDMA_PRIORITY_MEDIUM
907 * @arg @ref LL_BDMA_PRIORITY_HIGH
908 * @arg @ref LL_BDMA_PRIORITY_VERYHIGH
909 * @retval None
910 */
911 __STATIC_INLINE void LL_BDMA_SetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Priority)
912 {
913 uint32_t bdma_base_addr = (uint32_t)BDMAx;
914
915 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PL,
916 Priority);
917 }
918
919 /**
920 * @brief Get Channel priority level.
921 * @rmtoll CCR PL LL_BDMA_GetChannelPriorityLevel
922 * @param BDMAx BDMA Instance
923 * @param Channel This parameter can be one of the following values:
924 * @arg @ref LL_BDMA_CHANNEL_0
925 * @arg @ref LL_BDMA_CHANNEL_1
926 * @arg @ref LL_BDMA_CHANNEL_2
927 * @arg @ref LL_BDMA_CHANNEL_3
928 * @arg @ref LL_BDMA_CHANNEL_4
929 * @arg @ref LL_BDMA_CHANNEL_5
930 * @arg @ref LL_BDMA_CHANNEL_6
931 * @arg @ref LL_BDMA_CHANNEL_7
932 * @retval Returned value can be one of the following values:
933 * @arg @ref LL_BDMA_PRIORITY_LOW
934 * @arg @ref LL_BDMA_PRIORITY_MEDIUM
935 * @arg @ref LL_BDMA_PRIORITY_HIGH
936 * @arg @ref LL_BDMA_PRIORITY_VERYHIGH
937 */
938 __STATIC_INLINE uint32_t LL_BDMA_GetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32_t Channel)
939 {
940 uint32_t bdma_base_addr = (uint32_t)BDMAx;
941
942 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
943 BDMA_CCR_PL));
944 }
945
946 /**
947 * @brief Set Number of data to transfer.
948 * @note This action has no effect if
949 * channel is enabled.
950 * @rmtoll CNDTR NDT LL_BDMA_SetDataLength
951 * @param BDMAx BDMA Instance
952 * @param Channel This parameter can be one of the following values:
953 * @arg @ref LL_BDMA_CHANNEL_0
954 * @arg @ref LL_BDMA_CHANNEL_1
955 * @arg @ref LL_BDMA_CHANNEL_2
956 * @arg @ref LL_BDMA_CHANNEL_3
957 * @arg @ref LL_BDMA_CHANNEL_4
958 * @arg @ref LL_BDMA_CHANNEL_5
959 * @arg @ref LL_BDMA_CHANNEL_6
960 * @arg @ref LL_BDMA_CHANNEL_7
961 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
962 * @retval None
963 */
964 __STATIC_INLINE void LL_BDMA_SetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t NbData)
965 {
966 uint32_t bdma_base_addr = (uint32_t)BDMAx;
967
968 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CNDTR,
969 BDMA_CNDTR_NDT, NbData);
970 }
971
972 /**
973 * @brief Get Number of data to transfer.
974 * @note Once the channel is enabled, the return value indicate the
975 * remaining bytes to be transmitted.
976 * @rmtoll CNDTR NDT LL_BDMA_GetDataLength
977 * @param BDMAx BDMA Instance
978 * @param Channel This parameter can be one of the following values:
979 * @arg @ref LL_BDMA_CHANNEL_0
980 * @arg @ref LL_BDMA_CHANNEL_1
981 * @arg @ref LL_BDMA_CHANNEL_2
982 * @arg @ref LL_BDMA_CHANNEL_3
983 * @arg @ref LL_BDMA_CHANNEL_4
984 * @arg @ref LL_BDMA_CHANNEL_5
985 * @arg @ref LL_BDMA_CHANNEL_6
986 * @arg @ref LL_BDMA_CHANNEL_7
987 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
988 */
989 __STATIC_INLINE uint32_t LL_BDMA_GetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel)
990 {
991 uint32_t bdma_base_addr = (uint32_t)BDMAx;
992
993 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CNDTR,
994 BDMA_CNDTR_NDT));
995 }
996
997 /**
998 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
999 * @rmtoll CR CT LL_BDMA_SetCurrentTargetMem
1000 * @param BDMAx BDMAx Instance
1001 * @param Channel This parameter can be one of the following values:
1002 * @arg @ref LL_BDMA_CHANNEL_0
1003 * @arg @ref LL_BDMA_CHANNEL_1
1004 * @arg @ref LL_BDMA_CHANNEL_2
1005 * @arg @ref LL_BDMA_CHANNEL_3
1006 * @arg @ref LL_BDMA_CHANNEL_4
1007 * @arg @ref LL_BDMA_CHANNEL_5
1008 * @arg @ref LL_BDMA_CHANNEL_6
1009 * @arg @ref LL_BDMA_CHANNEL_7
1010 * @param CurrentMemory This parameter can be one of the following values:
1011 * @arg @ref LL_BDMA_CURRENTTARGETMEM0
1012 * @arg @ref LL_BDMA_CURRENTTARGETMEM1
1013 * @retval None
1014 */
1015 __STATIC_INLINE void LL_BDMA_SetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t CurrentMemory)
1016 {
1017 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1018
1019 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CT, CurrentMemory);
1020 }
1021
1022 /**
1023 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1024 * @rmtoll CR CT LL_BDMA_GetCurrentTargetMem
1025 * @param BDMAx BDMAx Instance
1026 * @param Channel This parameter can be one of the following values:
1027 * @arg @ref LL_BDMA_CHANNEL_0
1028 * @arg @ref LL_BDMA_CHANNEL_1
1029 * @arg @ref LL_BDMA_CHANNEL_2
1030 * @arg @ref LL_BDMA_CHANNEL_3
1031 * @arg @ref LL_BDMA_CHANNEL_4
1032 * @arg @ref LL_BDMA_CHANNEL_5
1033 * @arg @ref LL_BDMA_CHANNEL_6
1034 * @arg @ref LL_BDMA_CHANNEL_7
1035 * @retval Returned value can be one of the following values:
1036 * @arg @ref LL_BDMA_CURRENTTARGETMEM0
1037 * @arg @ref LL_BDMA_CURRENTTARGETMEM1
1038 */
1039 __STATIC_INLINE uint32_t LL_BDMA_GetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t Channel)
1040 {
1041 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1042
1043 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CT));
1044 }
1045
1046 /**
1047 * @brief Enable the double buffer mode.
1048 * @rmtoll CR DBM LL_BDMA_EnableDoubleBufferMode
1049 * @param BDMAx BDMAx Instance
1050 * @param Channel This parameter can be one of the following values:
1051 * @arg @ref LL_BDMA_CHANNEL_0
1052 * @arg @ref LL_BDMA_CHANNEL_1
1053 * @arg @ref LL_BDMA_CHANNEL_2
1054 * @arg @ref LL_BDMA_CHANNEL_3
1055 * @arg @ref LL_BDMA_CHANNEL_4
1056 * @arg @ref LL_BDMA_CHANNEL_5
1057 * @arg @ref LL_BDMA_CHANNEL_6
1058 * @arg @ref LL_BDMA_CHANNEL_7
1059 * @retval None
1060 */
1061 __STATIC_INLINE void LL_BDMA_EnableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
1062 {
1063 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1064
1065 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_DBM);
1066 }
1067
1068 /**
1069 * @brief Disable the double buffer mode.
1070 * @rmtoll CR DBM LL_BDMA_DisableDoubleBufferMode
1071 * @param BDMAx BDMAx Instance
1072 * @param Channel This parameter can be one of the following values:
1073 * @arg @ref LL_BDMA_CHANNEL_0
1074 * @arg @ref LL_BDMA_CHANNEL_1
1075 * @arg @ref LL_BDMA_CHANNEL_2
1076 * @arg @ref LL_BDMA_CHANNEL_3
1077 * @arg @ref LL_BDMA_CHANNEL_4
1078 * @arg @ref LL_BDMA_CHANNEL_5
1079 * @arg @ref LL_BDMA_CHANNEL_6
1080 * @arg @ref LL_BDMA_CHANNEL_7
1081 * @retval None
1082 */
1083 __STATIC_INLINE void LL_BDMA_DisableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
1084 {
1085 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1086
1087 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_DBM);
1088 }
1089
1090 /**
1091 * @brief Configure the Source and Destination addresses.
1092 * @note This API must not be called when the BDMA channel is enabled.
1093 * @note Each IP using BDMA provides an API to get directly the register adress (LL_PPP_BDMA_GetRegAddr).
1094 * @rmtoll CPAR PA LL_BDMA_ConfigAddresses\n
1095 * CMAR MA LL_BDMA_ConfigAddresses
1096 * @param BDMAx BDMA Instance
1097 * @param Channel This parameter can be one of the following values:
1098 * @arg @ref LL_BDMA_CHANNEL_0
1099 * @arg @ref LL_BDMA_CHANNEL_1
1100 * @arg @ref LL_BDMA_CHANNEL_2
1101 * @arg @ref LL_BDMA_CHANNEL_3
1102 * @arg @ref LL_BDMA_CHANNEL_4
1103 * @arg @ref LL_BDMA_CHANNEL_5
1104 * @arg @ref LL_BDMA_CHANNEL_6
1105 * @arg @ref LL_BDMA_CHANNEL_7
1106 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1107 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1108 * @param Direction This parameter can be one of the following values:
1109 * @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY
1110 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH
1111 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY
1112 * @retval None
1113 */
1114 __STATIC_INLINE void LL_BDMA_ConfigAddresses(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t SrcAddress,
1115 uint32_t DstAddress, uint32_t Direction)
1116 {
1117 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1118
1119 /* Direction Memory to Periph */
1120 if (Direction == LL_BDMA_DIRECTION_MEMORY_TO_PERIPH)
1121 {
1122 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, SrcAddress);
1123 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, DstAddress);
1124 }
1125 /* Direction Periph to Memory and Memory to Memory */
1126 else
1127 {
1128 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, SrcAddress);
1129 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, DstAddress);
1130 }
1131 }
1132
1133 /**
1134 * @brief Set the Memory address.
1135 * @note Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only.
1136 * @note This API must not be called when the BDMA channel is enabled.
1137 * @rmtoll CMAR MA LL_BDMA_SetMemoryAddress
1138 * @param BDMAx BDMA Instance
1139 * @param Channel This parameter can be one of the following values:
1140 * @arg @ref LL_BDMA_CHANNEL_0
1141 * @arg @ref LL_BDMA_CHANNEL_1
1142 * @arg @ref LL_BDMA_CHANNEL_2
1143 * @arg @ref LL_BDMA_CHANNEL_3
1144 * @arg @ref LL_BDMA_CHANNEL_4
1145 * @arg @ref LL_BDMA_CHANNEL_5
1146 * @arg @ref LL_BDMA_CHANNEL_6
1147 * @arg @ref LL_BDMA_CHANNEL_7
1148 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1149 * @retval None
1150 */
1151 __STATIC_INLINE void LL_BDMA_SetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress)
1152 {
1153 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1154
1155 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, MemoryAddress);
1156 }
1157
1158 /**
1159 * @brief Set the Peripheral address.
1160 * @note Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only.
1161 * @note This API must not be called when the BDMA channel is enabled.
1162 * @rmtoll CPAR PA LL_BDMA_SetPeriphAddress
1163 * @param BDMAx BDMA Instance
1164 * @param Channel This parameter can be one of the following values:
1165 * @arg @ref LL_BDMA_CHANNEL_0
1166 * @arg @ref LL_BDMA_CHANNEL_1
1167 * @arg @ref LL_BDMA_CHANNEL_2
1168 * @arg @ref LL_BDMA_CHANNEL_3
1169 * @arg @ref LL_BDMA_CHANNEL_4
1170 * @arg @ref LL_BDMA_CHANNEL_5
1171 * @arg @ref LL_BDMA_CHANNEL_6
1172 * @arg @ref LL_BDMA_CHANNEL_7
1173 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1174 * @retval None
1175 */
1176 __STATIC_INLINE void LL_BDMA_SetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphAddress)
1177 {
1178 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1179
1180 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, PeriphAddress);
1181 }
1182
1183 /**
1184 * @brief Get Memory address.
1185 * @note Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only.
1186 * @rmtoll CMAR MA LL_BDMA_GetMemoryAddress
1187 * @param BDMAx BDMA Instance
1188 * @param Channel This parameter can be one of the following values:
1189 * @arg @ref LL_BDMA_CHANNEL_0
1190 * @arg @ref LL_BDMA_CHANNEL_1
1191 * @arg @ref LL_BDMA_CHANNEL_2
1192 * @arg @ref LL_BDMA_CHANNEL_3
1193 * @arg @ref LL_BDMA_CHANNEL_4
1194 * @arg @ref LL_BDMA_CHANNEL_5
1195 * @arg @ref LL_BDMA_CHANNEL_6
1196 * @arg @ref LL_BDMA_CHANNEL_7
1197 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1198 */
1199 __STATIC_INLINE uint32_t LL_BDMA_GetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Channel)
1200 {
1201 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1202
1203 return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR));
1204 }
1205
1206 /**
1207 * @brief Get Peripheral address.
1208 * @note Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only.
1209 * @rmtoll CPAR PA LL_BDMA_GetPeriphAddress
1210 * @param BDMAx BDMA Instance
1211 * @param Channel This parameter can be one of the following values:
1212 * @arg @ref LL_BDMA_CHANNEL_0
1213 * @arg @ref LL_BDMA_CHANNEL_1
1214 * @arg @ref LL_BDMA_CHANNEL_2
1215 * @arg @ref LL_BDMA_CHANNEL_3
1216 * @arg @ref LL_BDMA_CHANNEL_4
1217 * @arg @ref LL_BDMA_CHANNEL_5
1218 * @arg @ref LL_BDMA_CHANNEL_6
1219 * @arg @ref LL_BDMA_CHANNEL_7
1220 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1221 */
1222 __STATIC_INLINE uint32_t LL_BDMA_GetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Channel)
1223 {
1224 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1225
1226 return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR));
1227 }
1228
1229 /**
1230 * @brief Set the Memory to Memory Source address.
1231 * @note Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only.
1232 * @note This API must not be called when the BDMA channel is enabled.
1233 * @rmtoll CPAR PA LL_BDMA_SetM2MSrcAddress
1234 * @param BDMAx BDMA Instance
1235 * @param Channel This parameter can be one of the following values:
1236 * @arg @ref LL_BDMA_CHANNEL_0
1237 * @arg @ref LL_BDMA_CHANNEL_1
1238 * @arg @ref LL_BDMA_CHANNEL_2
1239 * @arg @ref LL_BDMA_CHANNEL_3
1240 * @arg @ref LL_BDMA_CHANNEL_4
1241 * @arg @ref LL_BDMA_CHANNEL_5
1242 * @arg @ref LL_BDMA_CHANNEL_6
1243 * @arg @ref LL_BDMA_CHANNEL_7
1244 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1245 * @retval None
1246 */
1247 __STATIC_INLINE void LL_BDMA_SetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress)
1248 {
1249 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1250
1251 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, MemoryAddress);
1252 }
1253
1254 /**
1255 * @brief Set the Memory to Memory Destination address.
1256 * @note Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only.
1257 * @note This API must not be called when the BDMA channel is enabled.
1258 * @rmtoll CMAR MA LL_BDMA_SetM2MDstAddress
1259 * @param BDMAx BDMA Instance
1260 * @param Channel This parameter can be one of the following values:
1261 * @arg @ref LL_BDMA_CHANNEL_0
1262 * @arg @ref LL_BDMA_CHANNEL_1
1263 * @arg @ref LL_BDMA_CHANNEL_2
1264 * @arg @ref LL_BDMA_CHANNEL_3
1265 * @arg @ref LL_BDMA_CHANNEL_4
1266 * @arg @ref LL_BDMA_CHANNEL_5
1267 * @arg @ref LL_BDMA_CHANNEL_6
1268 * @arg @ref LL_BDMA_CHANNEL_7
1269 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1270 * @retval None
1271 */
1272 __STATIC_INLINE void LL_BDMA_SetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress)
1273 {
1274 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1275
1276 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, MemoryAddress);
1277 }
1278
1279 /**
1280 * @brief Get the Memory to Memory Source address.
1281 * @note Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only.
1282 * @rmtoll CPAR PA LL_BDMA_GetM2MSrcAddress
1283 * @param BDMAx BDMA Instance
1284 * @param Channel This parameter can be one of the following values:
1285 * @arg @ref LL_BDMA_CHANNEL_0
1286 * @arg @ref LL_BDMA_CHANNEL_1
1287 * @arg @ref LL_BDMA_CHANNEL_2
1288 * @arg @ref LL_BDMA_CHANNEL_3
1289 * @arg @ref LL_BDMA_CHANNEL_4
1290 * @arg @ref LL_BDMA_CHANNEL_5
1291 * @arg @ref LL_BDMA_CHANNEL_6
1292 * @arg @ref LL_BDMA_CHANNEL_7
1293 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1294 */
1295 __STATIC_INLINE uint32_t LL_BDMA_GetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Channel)
1296 {
1297 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1298
1299 return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR));
1300 }
1301
1302 /**
1303 * @brief Get the Memory to Memory Destination address.
1304 * @note Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only.
1305 * @rmtoll CMAR MA LL_BDMA_GetM2MDstAddress
1306 * @param BDMAx BDMA Instance
1307 * @param Channel This parameter can be one of the following values:
1308 * @arg @ref LL_BDMA_CHANNEL_0
1309 * @arg @ref LL_BDMA_CHANNEL_1
1310 * @arg @ref LL_BDMA_CHANNEL_2
1311 * @arg @ref LL_BDMA_CHANNEL_3
1312 * @arg @ref LL_BDMA_CHANNEL_4
1313 * @arg @ref LL_BDMA_CHANNEL_5
1314 * @arg @ref LL_BDMA_CHANNEL_6
1315 * @arg @ref LL_BDMA_CHANNEL_7
1316 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1317 */
1318 __STATIC_INLINE uint32_t LL_BDMA_GetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Channel)
1319 {
1320 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1321
1322 return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR));
1323 }
1324
1325 /**
1326 * @brief Set Memory 1 address (used in case of Double buffer mode).
1327 * @rmtoll M1AR M1A LL_BDMA_SetMemory1Address
1328 * @param BDMAx BDMAx Instance
1329 * @param Channel This parameter can be one of the following values:
1330 * @arg @ref LL_BDMA_CHANNEL_0
1331 * @arg @ref LL_BDMA_CHANNEL_1
1332 * @arg @ref LL_BDMA_CHANNEL_2
1333 * @arg @ref LL_BDMA_CHANNEL_3
1334 * @arg @ref LL_BDMA_CHANNEL_4
1335 * @arg @ref LL_BDMA_CHANNEL_5
1336 * @arg @ref LL_BDMA_CHANNEL_6
1337 * @arg @ref LL_BDMA_CHANNEL_7
1338 * @param Address Between 0 to 0xFFFFFFFF
1339 * @retval None
1340 */
1341 __STATIC_INLINE void LL_BDMA_SetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Address)
1342 {
1343 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1344
1345 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM1AR, BDMA_CM1AR_MA, Address);
1346 }
1347
1348 /**
1349 * @brief Get Memory 1 address (used in case of Double buffer mode).
1350 * @rmtoll M1AR M1A LL_BDMA_GetMemory1Address
1351 * @param BDMAx BDMAx Instance
1352 * @param Channel This parameter can be one of the following values:
1353 * @arg @ref LL_BDMA_CHANNEL_0
1354 * @arg @ref LL_BDMA_CHANNEL_1
1355 * @arg @ref LL_BDMA_CHANNEL_2
1356 * @arg @ref LL_BDMA_CHANNEL_3
1357 * @arg @ref LL_BDMA_CHANNEL_4
1358 * @arg @ref LL_BDMA_CHANNEL_5
1359 * @arg @ref LL_BDMA_CHANNEL_6
1360 * @arg @ref LL_BDMA_CHANNEL_7
1361 * @retval Between 0 to 0xFFFFFFFF
1362 */
1363 __STATIC_INLINE uint32_t LL_BDMA_GetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Channel)
1364 {
1365 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1366
1367 return (((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM1AR);
1368 }
1369
1370 /**
1371 * @brief Set BDMA request for BDMA Channels on DMAMUX Channel x.
1372 * @note DMAMUX2 channel 0 to 7 are mapped to BDMA channel 0 to 7.
1373 * @rmtoll CxCR DMAREQ_ID LL_BDMA_SetPeriphRequest
1374 * @param BDMAx BDMAx Instance
1375 * @param Channel This parameter can be one of the following values:
1376 * @arg @ref LL_BDMA_CHANNEL_0
1377 * @arg @ref LL_BDMA_CHANNEL_1
1378 * @arg @ref LL_BDMA_CHANNEL_2
1379 * @arg @ref LL_BDMA_CHANNEL_3
1380 * @arg @ref LL_BDMA_CHANNEL_4
1381 * @arg @ref LL_BDMA_CHANNEL_5
1382 * @arg @ref LL_BDMA_CHANNEL_6
1383 * @arg @ref LL_BDMA_CHANNEL_7
1384 * @param Request This parameter can be one of the following values:
1385 * @arg @ref LL_DMAMUX2_REQ_MEM2MEM
1386 * @arg @ref LL_DMAMUX2_REQ_GENERATOR0
1387 * @arg @ref LL_DMAMUX2_REQ_GENERATOR1
1388 * @arg @ref LL_DMAMUX2_REQ_GENERATOR2
1389 * @arg @ref LL_DMAMUX2_REQ_GENERATOR3
1390 * @arg @ref LL_DMAMUX2_REQ_GENERATOR4
1391 * @arg @ref LL_DMAMUX2_REQ_GENERATOR5
1392 * @arg @ref LL_DMAMUX2_REQ_GENERATOR6
1393 * @arg @ref LL_DMAMUX2_REQ_GENERATOR7
1394 * @arg @ref LL_DMAMUX2_REQ_LPUART1_RX
1395 * @arg @ref LL_DMAMUX2_REQ_LPUART1_TX
1396 * @arg @ref LL_DMAMUX2_REQ_SPI6_RX
1397 * @arg @ref LL_DMAMUX2_REQ_SPI6_TX
1398 * @arg @ref LL_DMAMUX2_REQ_I2C4_RX
1399 * @arg @ref LL_DMAMUX2_REQ_I2C4_TX
1400 * @arg @ref LL_DMAMUX2_REQ_SAI4_A (*)
1401 * @arg @ref LL_DMAMUX2_REQ_SAI4_B (*)
1402 * @arg @ref LL_DMAMUX2_REQ_ADC3 (*)
1403 * @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*)
1404 * @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*)
1405 *
1406 * @note (*) Availability depends on devices.
1407 * @retval None
1408 */
1409 __STATIC_INLINE void LL_BDMA_SetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Request)
1410 {
1411 UNUSED(BDMAx);
1412 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX2_Channel0 + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
1413 }
1414
1415 /**
1416 * @brief Get BDMA request for BDMA Channels on DMAMUX Channel x.
1417 * @note DMAMUX channel 0 to 7 are mapped to BDMA channel 0 to 7.
1418 * @rmtoll CxCR DMAREQ_ID LL_BDMA_GetPeriphRequest
1419 * @param BDMAx BDMAx Instance
1420 * @param Channel This parameter can be one of the following values:
1421 * @arg @ref LL_BDMA_CHANNEL_0
1422 * @arg @ref LL_BDMA_CHANNEL_1
1423 * @arg @ref LL_BDMA_CHANNEL_2
1424 * @arg @ref LL_BDMA_CHANNEL_3
1425 * @arg @ref LL_BDMA_CHANNEL_4
1426 * @arg @ref LL_BDMA_CHANNEL_5
1427 * @arg @ref LL_BDMA_CHANNEL_6
1428 * @arg @ref LL_BDMA_CHANNEL_7
1429 * @retval Returned value can be one of the following values:
1430 * @arg @ref LL_DMAMUX2_REQ_MEM2MEM
1431 * @arg @ref LL_DMAMUX2_REQ_GENERATOR0
1432 * @arg @ref LL_DMAMUX2_REQ_GENERATOR1
1433 * @arg @ref LL_DMAMUX2_REQ_GENERATOR2
1434 * @arg @ref LL_DMAMUX2_REQ_GENERATOR3
1435 * @arg @ref LL_DMAMUX2_REQ_GENERATOR4
1436 * @arg @ref LL_DMAMUX2_REQ_GENERATOR5
1437 * @arg @ref LL_DMAMUX2_REQ_GENERATOR6
1438 * @arg @ref LL_DMAMUX2_REQ_GENERATOR7
1439 * @arg @ref LL_DMAMUX2_REQ_LPUART1_RX
1440 * @arg @ref LL_DMAMUX2_REQ_LPUART1_TX
1441 * @arg @ref LL_DMAMUX2_REQ_SPI6_RX
1442 * @arg @ref LL_DMAMUX2_REQ_SPI6_TX
1443 * @arg @ref LL_DMAMUX2_REQ_I2C4_RX
1444 * @arg @ref LL_DMAMUX2_REQ_I2C4_TX
1445 * @arg @ref LL_DMAMUX2_REQ_SAI4_A (*)
1446 * @arg @ref LL_DMAMUX2_REQ_SAI4_B (*)
1447 * @arg @ref LL_DMAMUX2_REQ_ADC3 (*)
1448 * @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*)
1449 * @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*)
1450 *
1451 * @note (*) Availability depends on devices.
1452 */
1453 __STATIC_INLINE uint32_t LL_BDMA_GetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t Channel)
1454 {
1455 UNUSED(BDMAx);
1456 return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX2_Channel0 + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
1457 }
1458
1459 /**
1460 * @}
1461 */
1462
1463
1464 /** @defgroup BDMA_LL_EF_FLAG_Management FLAG_Management
1465 * @{
1466 */
1467 /**
1468 * @brief Get Channel 0 global interrupt flag.
1469 * @rmtoll ISR GIF0 LL_BDMA_IsActiveFlag_GI0
1470 * @param BDMAx BDMA Instance
1471 * @retval State of bit (1 or 0).
1472 */
1473 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI0(BDMA_TypeDef *BDMAx)
1474 {
1475 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF0) == (BDMA_ISR_GIF0)) ? 1UL : 0UL);
1476 }
1477
1478 /**
1479 * @brief Get Channel 1 global interrupt flag.
1480 * @rmtoll ISR GIF1 LL_BDMA_IsActiveFlag_GI1
1481 * @param BDMAx BDMA Instance
1482 * @retval State of bit (1 or 0).
1483 */
1484 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI1(BDMA_TypeDef *BDMAx)
1485 {
1486 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF1) == (BDMA_ISR_GIF1)) ? 1UL : 0UL);
1487 }
1488
1489 /**
1490 * @brief Get Channel 2 global interrupt flag.
1491 * @rmtoll ISR GIF2 LL_BDMA_IsActiveFlag_GI2
1492 * @param BDMAx BDMA Instance
1493 * @retval State of bit (1 or 0).
1494 */
1495 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI2(BDMA_TypeDef *BDMAx)
1496 {
1497 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF2) == (BDMA_ISR_GIF2)) ? 1UL : 0UL);
1498 }
1499
1500 /**
1501 * @brief Get Channel 3 global interrupt flag.
1502 * @rmtoll ISR GIF3 LL_BDMA_IsActiveFlag_GI3
1503 * @param BDMAx BDMA Instance
1504 * @retval State of bit (1 or 0).
1505 */
1506 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI3(BDMA_TypeDef *BDMAx)
1507 {
1508 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF3) == (BDMA_ISR_GIF3)) ? 1UL : 0UL);
1509 }
1510
1511 /**
1512 * @brief Get Channel 4 global interrupt flag.
1513 * @rmtoll ISR GIF4 LL_BDMA_IsActiveFlag_GI4
1514 * @param BDMAx BDMA Instance
1515 * @retval State of bit (1 or 0).
1516 */
1517 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI4(BDMA_TypeDef *BDMAx)
1518 {
1519 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF4) == (BDMA_ISR_GIF4)) ? 1UL : 0UL);
1520 }
1521
1522 /**
1523 * @brief Get Channel 5 global interrupt flag.
1524 * @rmtoll ISR GIF5 LL_BDMA_IsActiveFlag_GI5
1525 * @param BDMAx BDMA Instance
1526 * @retval State of bit (1 or 0).
1527 */
1528 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI5(BDMA_TypeDef *BDMAx)
1529 {
1530 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF5) == (BDMA_ISR_GIF5)) ? 1UL : 0UL);
1531 }
1532
1533 /**
1534 * @brief Get Channel 6 global interrupt flag.
1535 * @rmtoll ISR GIF6 LL_BDMA_IsActiveFlag_GI6
1536 * @param BDMAx BDMA Instance
1537 * @retval State of bit (1 or 0).
1538 */
1539 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI6(BDMA_TypeDef *BDMAx)
1540 {
1541 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF6) == (BDMA_ISR_GIF6)) ? 1UL : 0UL);
1542 }
1543
1544 /**
1545 * @brief Get Channel 7 global interrupt flag.
1546 * @rmtoll ISR GIF7 LL_BDMA_IsActiveFlag_GI7
1547 * @param BDMAx BDMA Instance
1548 * @retval State of bit (1 or 0).
1549 */
1550 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI7(BDMA_TypeDef *BDMAx)
1551 {
1552 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF7) == (BDMA_ISR_GIF7)) ? 1UL : 0UL);
1553 }
1554
1555 /**
1556 * @brief Get Channel 0 transfer complete flag.
1557 * @rmtoll ISR TCIF0 LL_BDMA_IsActiveFlag_TC0
1558 * @param BDMAx BDMA Instance
1559 * @retval State of bit (1 or 0).
1560 */
1561 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC0(BDMA_TypeDef *BDMAx)
1562 {
1563 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF0) == (BDMA_ISR_TCIF0)) ? 1UL : 0UL);
1564 }
1565 /**
1566 * @brief Get Channel 1 transfer complete flag.
1567 * @rmtoll ISR TCIF1 LL_BDMA_IsActiveFlag_TC1
1568 * @param BDMAx BDMA Instance
1569 * @retval State of bit (1 or 0).
1570 */
1571 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC1(BDMA_TypeDef *BDMAx)
1572 {
1573 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF1) == (BDMA_ISR_TCIF1)) ? 1UL : 0UL);
1574 }
1575
1576 /**
1577 * @brief Get Channel 2 transfer complete flag.
1578 * @rmtoll ISR TCIF2 LL_BDMA_IsActiveFlag_TC2
1579 * @param BDMAx BDMA Instance
1580 * @retval State of bit (1 or 0).
1581 */
1582 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC2(BDMA_TypeDef *BDMAx)
1583 {
1584 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF2) == (BDMA_ISR_TCIF2)) ? 1UL : 0UL);
1585 }
1586
1587 /**
1588 * @brief Get Channel 3 transfer complete flag.
1589 * @rmtoll ISR TCIF3 LL_BDMA_IsActiveFlag_TC3
1590 * @param BDMAx BDMA Instance
1591 * @retval State of bit (1 or 0).
1592 */
1593 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC3(BDMA_TypeDef *BDMAx)
1594 {
1595 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF3) == (BDMA_ISR_TCIF3)) ? 1UL : 0UL);
1596 }
1597
1598 /**
1599 * @brief Get Channel 4 transfer complete flag.
1600 * @rmtoll ISR TCIF4 LL_BDMA_IsActiveFlag_TC4
1601 * @param BDMAx BDMA Instance
1602 * @retval State of bit (1 or 0).
1603 */
1604 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC4(BDMA_TypeDef *BDMAx)
1605 {
1606 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF4) == (BDMA_ISR_TCIF4)) ? 1UL : 0UL);
1607 }
1608
1609 /**
1610 * @brief Get Channel 5 transfer complete flag.
1611 * @rmtoll ISR TCIF5 LL_BDMA_IsActiveFlag_TC5
1612 * @param BDMAx BDMA Instance
1613 * @retval State of bit (1 or 0).
1614 */
1615 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC5(BDMA_TypeDef *BDMAx)
1616 {
1617 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF5) == (BDMA_ISR_TCIF5)) ? 1UL : 0UL);
1618 }
1619
1620 /**
1621 * @brief Get Channel 6 transfer complete flag.
1622 * @rmtoll ISR TCIF6 LL_BDMA_IsActiveFlag_TC6
1623 * @param BDMAx BDMA Instance
1624 * @retval State of bit (1 or 0).
1625 */
1626 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC6(BDMA_TypeDef *BDMAx)
1627 {
1628 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF6) == (BDMA_ISR_TCIF6)) ? 1UL : 0UL);
1629 }
1630
1631 /**
1632 * @brief Get Channel 7 transfer complete flag.
1633 * @rmtoll ISR TCIF7 LL_BDMA_IsActiveFlag_TC7
1634 * @param BDMAx BDMA Instance
1635 * @retval State of bit (1 or 0).
1636 */
1637 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC7(BDMA_TypeDef *BDMAx)
1638 {
1639 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF7) == (BDMA_ISR_TCIF7)) ? 1UL : 0UL);
1640 }
1641
1642 /**
1643 * @brief Get Channel 0 half transfer flag.
1644 * @rmtoll ISR HTIF0 LL_BDMA_IsActiveFlag_HT0
1645 * @param BDMAx BDMA Instance
1646 * @retval State of bit (1 or 0).
1647 */
1648 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT0(BDMA_TypeDef *BDMAx)
1649 {
1650 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF0) == (BDMA_ISR_HTIF0)) ? 1UL : 0UL);
1651 }
1652
1653 /**
1654 * @brief Get Channel 1 half transfer flag.
1655 * @rmtoll ISR HTIF1 LL_BDMA_IsActiveFlag_HT1
1656 * @param BDMAx BDMA Instance
1657 * @retval State of bit (1 or 0).
1658 */
1659 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT1(BDMA_TypeDef *BDMAx)
1660 {
1661 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF1) == (BDMA_ISR_HTIF1)) ? 1UL : 0UL);
1662 }
1663
1664 /**
1665 * @brief Get Channel 2 half transfer flag.
1666 * @rmtoll ISR HTIF2 LL_BDMA_IsActiveFlag_HT2
1667 * @param BDMAx BDMA Instance
1668 * @retval State of bit (1 or 0).
1669 */
1670 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT2(BDMA_TypeDef *BDMAx)
1671 {
1672 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF2) == (BDMA_ISR_HTIF2)) ? 1UL : 0UL);
1673 }
1674
1675 /**
1676 * @brief Get Channel 3 half transfer flag.
1677 * @rmtoll ISR HTIF3 LL_BDMA_IsActiveFlag_HT3
1678 * @param BDMAx BDMA Instance
1679 * @retval State of bit (1 or 0).
1680 */
1681 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT3(BDMA_TypeDef *BDMAx)
1682 {
1683 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF3) == (BDMA_ISR_HTIF3)) ? 1UL : 0UL);
1684 }
1685
1686 /**
1687 * @brief Get Channel 4 half transfer flag.
1688 * @rmtoll ISR HTIF4 LL_BDMA_IsActiveFlag_HT4
1689 * @param BDMAx BDMA Instance
1690 * @retval State of bit (1 or 0).
1691 */
1692 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT4(BDMA_TypeDef *BDMAx)
1693 {
1694 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF4) == (BDMA_ISR_HTIF4)) ? 1UL : 0UL);
1695 }
1696
1697 /**
1698 * @brief Get Channel 5 half transfer flag.
1699 * @rmtoll ISR HTIF5 LL_BDMA_IsActiveFlag_HT5
1700 * @param BDMAx BDMA Instance
1701 * @retval State of bit (1 or 0).
1702 */
1703 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT5(BDMA_TypeDef *BDMAx)
1704 {
1705 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF5) == (BDMA_ISR_HTIF5)) ? 1UL : 0UL);
1706 }
1707
1708 /**
1709 * @brief Get Channel 6 half transfer flag.
1710 * @rmtoll ISR HTIF6 LL_BDMA_IsActiveFlag_HT6
1711 * @param BDMAx BDMA Instance
1712 * @retval State of bit (1 or 0).
1713 */
1714 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT6(BDMA_TypeDef *BDMAx)
1715 {
1716 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF6) == (BDMA_ISR_HTIF6)) ? 1UL : 0UL);
1717 }
1718
1719 /**
1720 * @brief Get Channel 7 half transfer flag.
1721 * @rmtoll ISR HTIF7 LL_BDMA_IsActiveFlag_HT7
1722 * @param BDMAx BDMA Instance
1723 * @retval State of bit (1 or 0).
1724 */
1725 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT7(BDMA_TypeDef *BDMAx)
1726 {
1727 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF7) == (BDMA_ISR_HTIF7)) ? 1UL : 0UL);
1728 }
1729
1730 /**
1731 * @brief Get Channel 0 transfer error flag.
1732 * @rmtoll ISR TEIF0 LL_BDMA_IsActiveFlag_TE0
1733 * @param BDMAx BDMA Instance
1734 * @retval State of bit (1 or 0).
1735 */
1736 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE0(BDMA_TypeDef *BDMAx)
1737 {
1738 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF0) == (BDMA_ISR_TEIF0)) ? 1UL : 0UL);
1739 }
1740
1741 /**
1742 * @brief Get Channel 1 transfer error flag.
1743 * @rmtoll ISR TEIF1 LL_BDMA_IsActiveFlag_TE1
1744 * @param BDMAx BDMA Instance
1745 * @retval State of bit (1 or 0).
1746 */
1747 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE1(BDMA_TypeDef *BDMAx)
1748 {
1749 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF1) == (BDMA_ISR_TEIF1)) ? 1UL : 0UL);
1750 }
1751
1752 /**
1753 * @brief Get Channel 2 transfer error flag.
1754 * @rmtoll ISR TEIF2 LL_BDMA_IsActiveFlag_TE2
1755 * @param BDMAx BDMA Instance
1756 * @retval State of bit (1 or 0).
1757 */
1758 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE2(BDMA_TypeDef *BDMAx)
1759 {
1760 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF2) == (BDMA_ISR_TEIF2)) ? 1UL : 0UL);
1761 }
1762
1763 /**
1764 * @brief Get Channel 3 transfer error flag.
1765 * @rmtoll ISR TEIF3 LL_BDMA_IsActiveFlag_TE3
1766 * @param BDMAx BDMA Instance
1767 * @retval State of bit (1 or 0).
1768 */
1769 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE3(BDMA_TypeDef *BDMAx)
1770 {
1771 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF3) == (BDMA_ISR_TEIF3)) ? 1UL : 0UL);
1772 }
1773
1774 /**
1775 * @brief Get Channel 4 transfer error flag.
1776 * @rmtoll ISR TEIF4 LL_BDMA_IsActiveFlag_TE4
1777 * @param BDMAx BDMA Instance
1778 * @retval State of bit (1 or 0).
1779 */
1780 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE4(BDMA_TypeDef *BDMAx)
1781 {
1782 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF4) == (BDMA_ISR_TEIF4)) ? 1UL : 0UL);
1783 }
1784
1785 /**
1786 * @brief Get Channel 5 transfer error flag.
1787 * @rmtoll ISR TEIF5 LL_BDMA_IsActiveFlag_TE5
1788 * @param BDMAx BDMA Instance
1789 * @retval State of bit (1 or 0).
1790 */
1791 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE5(BDMA_TypeDef *BDMAx)
1792 {
1793 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF5) == (BDMA_ISR_TEIF5)) ? 1UL : 0UL);
1794 }
1795
1796 /**
1797 * @brief Get Channel 6 transfer error flag.
1798 * @rmtoll ISR TEIF6 LL_BDMA_IsActiveFlag_TE6
1799 * @param BDMAx BDMA Instance
1800 * @retval State of bit (1 or 0).
1801 */
1802 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE6(BDMA_TypeDef *BDMAx)
1803 {
1804 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF6) == (BDMA_ISR_TEIF6)) ? 1UL : 0UL);
1805 }
1806
1807 /**
1808 * @brief Get Channel 7 transfer error flag.
1809 * @rmtoll ISR TEIF7 LL_BDMA_IsActiveFlag_TE7
1810 * @param BDMAx BDMA Instance
1811 * @retval State of bit (1 or 0).
1812 */
1813 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE7(BDMA_TypeDef *BDMAx)
1814 {
1815 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF7) == (BDMA_ISR_TEIF7)) ? 1UL : 0UL);
1816 }
1817
1818 /**
1819 * @brief Clear Channel 0 global interrupt flag.
1820 * @rmtoll IFCR CGIF0 LL_BDMA_ClearFlag_GI0
1821 * @param BDMAx BDMA Instance
1822 * @retval None
1823 */
1824 __STATIC_INLINE void LL_BDMA_ClearFlag_GI0(BDMA_TypeDef *BDMAx)
1825 {
1826 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF0);
1827 }
1828
1829 /**
1830 * @brief Clear Channel 1 global interrupt flag.
1831 * @rmtoll IFCR CGIF1 LL_BDMA_ClearFlag_GI1
1832 * @param BDMAx BDMA Instance
1833 * @retval None
1834 */
1835 __STATIC_INLINE void LL_BDMA_ClearFlag_GI1(BDMA_TypeDef *BDMAx)
1836 {
1837 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF1);
1838 }
1839
1840 /**
1841 * @brief Clear Channel 2 global interrupt flag.
1842 * @rmtoll IFCR CGIF2 LL_BDMA_ClearFlag_GI2
1843 * @param BDMAx BDMA Instance
1844 * @retval None
1845 */
1846 __STATIC_INLINE void LL_BDMA_ClearFlag_GI2(BDMA_TypeDef *BDMAx)
1847 {
1848 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF2);
1849 }
1850
1851 /**
1852 * @brief Clear Channel 3 global interrupt flag.
1853 * @rmtoll IFCR CGIF3 LL_BDMA_ClearFlag_GI3
1854 * @param BDMAx BDMA Instance
1855 * @retval None
1856 */
1857 __STATIC_INLINE void LL_BDMA_ClearFlag_GI3(BDMA_TypeDef *BDMAx)
1858 {
1859 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF3);
1860 }
1861
1862 /**
1863 * @brief Clear Channel 4 global interrupt flag.
1864 * @rmtoll IFCR CGIF4 LL_BDMA_ClearFlag_GI4
1865 * @param BDMAx BDMA Instance
1866 * @retval None
1867 */
1868 __STATIC_INLINE void LL_BDMA_ClearFlag_GI4(BDMA_TypeDef *BDMAx)
1869 {
1870 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF4);
1871 }
1872
1873 /**
1874 * @brief Clear Channel 5 global interrupt flag.
1875 * @rmtoll IFCR CGIF5 LL_BDMA_ClearFlag_GI5
1876 * @param BDMAx BDMA Instance
1877 * @retval None
1878 */
1879 __STATIC_INLINE void LL_BDMA_ClearFlag_GI5(BDMA_TypeDef *BDMAx)
1880 {
1881 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF5);
1882 }
1883
1884 /**
1885 * @brief Clear Channel 6 global interrupt flag.
1886 * @rmtoll IFCR CGIF6 LL_BDMA_ClearFlag_GI6
1887 * @param BDMAx BDMA Instance
1888 * @retval None
1889 */
1890 __STATIC_INLINE void LL_BDMA_ClearFlag_GI6(BDMA_TypeDef *BDMAx)
1891 {
1892 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF6);
1893 }
1894
1895 /**
1896 * @brief Clear Channel 7 global interrupt flag.
1897 * @rmtoll IFCR CGIF7 LL_BDMA_ClearFlag_GI7
1898 * @param BDMAx BDMA Instance
1899 * @retval None
1900 */
1901 __STATIC_INLINE void LL_BDMA_ClearFlag_GI7(BDMA_TypeDef *BDMAx)
1902 {
1903 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF7);
1904 }
1905
1906 /**
1907 * @brief Clear Channel 0 transfer complete flag.
1908 * @rmtoll IFCR CTCIF0 LL_BDMA_ClearFlag_TC0
1909 * @param BDMAx BDMA Instance
1910 * @retval None
1911 */
1912 __STATIC_INLINE void LL_BDMA_ClearFlag_TC0(BDMA_TypeDef *BDMAx)
1913 {
1914 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF0);
1915 }
1916
1917 /**
1918 * @brief Clear Channel 1 transfer complete flag.
1919 * @rmtoll IFCR CTCIF1 LL_BDMA_ClearFlag_TC1
1920 * @param BDMAx BDMA Instance
1921 * @retval None
1922 */
1923 __STATIC_INLINE void LL_BDMA_ClearFlag_TC1(BDMA_TypeDef *BDMAx)
1924 {
1925 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF1);
1926 }
1927
1928 /**
1929 * @brief Clear Channel 2 transfer complete flag.
1930 * @rmtoll IFCR CTCIF2 LL_BDMA_ClearFlag_TC2
1931 * @param BDMAx BDMA Instance
1932 * @retval None
1933 */
1934 __STATIC_INLINE void LL_BDMA_ClearFlag_TC2(BDMA_TypeDef *BDMAx)
1935 {
1936 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF2);
1937 }
1938
1939 /**
1940 * @brief Clear Channel 3 transfer complete flag.
1941 * @rmtoll IFCR CTCIF3 LL_BDMA_ClearFlag_TC3
1942 * @param BDMAx BDMA Instance
1943 * @retval None
1944 */
1945 __STATIC_INLINE void LL_BDMA_ClearFlag_TC3(BDMA_TypeDef *BDMAx)
1946 {
1947 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF3);
1948 }
1949
1950 /**
1951 * @brief Clear Channel 4 transfer complete flag.
1952 * @rmtoll IFCR CTCIF4 LL_BDMA_ClearFlag_TC4
1953 * @param BDMAx BDMA Instance
1954 * @retval None
1955 */
1956 __STATIC_INLINE void LL_BDMA_ClearFlag_TC4(BDMA_TypeDef *BDMAx)
1957 {
1958 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF4);
1959 }
1960
1961 /**
1962 * @brief Clear Channel 5 transfer complete flag.
1963 * @rmtoll IFCR CTCIF5 LL_BDMA_ClearFlag_TC5
1964 * @param BDMAx BDMA Instance
1965 * @retval None
1966 */
1967 __STATIC_INLINE void LL_BDMA_ClearFlag_TC5(BDMA_TypeDef *BDMAx)
1968 {
1969 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF5);
1970 }
1971
1972 /**
1973 * @brief Clear Channel 6 transfer complete flag.
1974 * @rmtoll IFCR CTCIF6 LL_BDMA_ClearFlag_TC6
1975 * @param BDMAx BDMA Instance
1976 * @retval None
1977 */
1978 __STATIC_INLINE void LL_BDMA_ClearFlag_TC6(BDMA_TypeDef *BDMAx)
1979 {
1980 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF6);
1981 }
1982
1983 /**
1984 * @brief Clear Channel 7 transfer complete flag.
1985 * @rmtoll IFCR CTCIF7 LL_BDMA_ClearFlag_TC7
1986 * @param BDMAx BDMA Instance
1987 * @retval None
1988 */
1989 __STATIC_INLINE void LL_BDMA_ClearFlag_TC7(BDMA_TypeDef *BDMAx)
1990 {
1991 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF7);
1992 }
1993
1994 /**
1995 * @brief Clear Channel 0 half transfer flag.
1996 * @rmtoll IFCR CHTIF0 LL_BDMA_ClearFlag_HT0
1997 * @param BDMAx BDMA Instance
1998 * @retval None
1999 */
2000 __STATIC_INLINE void LL_BDMA_ClearFlag_HT0(BDMA_TypeDef *BDMAx)
2001 {
2002 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF0);
2003 }
2004
2005 /**
2006 * @brief Clear Channel 1 half transfer flag.
2007 * @rmtoll IFCR CHTIF1 LL_BDMA_ClearFlag_HT1
2008 * @param BDMAx BDMA Instance
2009 * @retval None
2010 */
2011 __STATIC_INLINE void LL_BDMA_ClearFlag_HT1(BDMA_TypeDef *BDMAx)
2012 {
2013 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF1);
2014 }
2015
2016 /**
2017 * @brief Clear Channel 2 half transfer flag.
2018 * @rmtoll IFCR CHTIF2 LL_BDMA_ClearFlag_HT2
2019 * @param BDMAx BDMA Instance
2020 * @retval None
2021 */
2022 __STATIC_INLINE void LL_BDMA_ClearFlag_HT2(BDMA_TypeDef *BDMAx)
2023 {
2024 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF2);
2025 }
2026
2027 /**
2028 * @brief Clear Channel 3 half transfer flag.
2029 * @rmtoll IFCR CHTIF3 LL_BDMA_ClearFlag_HT3
2030 * @param BDMAx BDMA Instance
2031 * @retval None
2032 */
2033 __STATIC_INLINE void LL_BDMA_ClearFlag_HT3(BDMA_TypeDef *BDMAx)
2034 {
2035 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF3);
2036 }
2037
2038 /**
2039 * @brief Clear Channel 4 half transfer flag.
2040 * @rmtoll IFCR CHTIF4 LL_BDMA_ClearFlag_HT4
2041 * @param BDMAx BDMA Instance
2042 * @retval None
2043 */
2044 __STATIC_INLINE void LL_BDMA_ClearFlag_HT4(BDMA_TypeDef *BDMAx)
2045 {
2046 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF4);
2047 }
2048
2049 /**
2050 * @brief Clear Channel 5 half transfer flag.
2051 * @rmtoll IFCR CHTIF5 LL_BDMA_ClearFlag_HT5
2052 * @param BDMAx BDMA Instance
2053 * @retval None
2054 */
2055 __STATIC_INLINE void LL_BDMA_ClearFlag_HT5(BDMA_TypeDef *BDMAx)
2056 {
2057 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF5);
2058 }
2059
2060 /**
2061 * @brief Clear Channel 6 half transfer flag.
2062 * @rmtoll IFCR CHTIF6 LL_BDMA_ClearFlag_HT6
2063 * @param BDMAx BDMA Instance
2064 * @retval None
2065 */
2066 __STATIC_INLINE void LL_BDMA_ClearFlag_HT6(BDMA_TypeDef *BDMAx)
2067 {
2068 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF6);
2069 }
2070
2071 /**
2072 * @brief Clear Channel 7 half transfer flag.
2073 * @rmtoll IFCR CHTIF7 LL_BDMA_ClearFlag_HT7
2074 * @param BDMAx BDMA Instance
2075 * @retval None
2076 */
2077 __STATIC_INLINE void LL_BDMA_ClearFlag_HT7(BDMA_TypeDef *BDMAx)
2078 {
2079 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF7);
2080 }
2081
2082 /**
2083 * @brief Clear Channel 0 transfer error flag.
2084 * @rmtoll IFCR CTEIF0 LL_BDMA_ClearFlag_TE0
2085 * @param BDMAx BDMA Instance
2086 * @retval None
2087 */
2088 __STATIC_INLINE void LL_BDMA_ClearFlag_TE0(BDMA_TypeDef *BDMAx)
2089 {
2090 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF0);
2091 }
2092
2093 /**
2094 * @brief Clear Channel 1 transfer error flag.
2095 * @rmtoll IFCR CTEIF1 LL_BDMA_ClearFlag_TE1
2096 * @param BDMAx BDMA Instance
2097 * @retval None
2098 */
2099 __STATIC_INLINE void LL_BDMA_ClearFlag_TE1(BDMA_TypeDef *BDMAx)
2100 {
2101 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF1);
2102 }
2103
2104 /**
2105 * @brief Clear Channel 2 transfer error flag.
2106 * @rmtoll IFCR CTEIF2 LL_BDMA_ClearFlag_TE2
2107 * @param BDMAx BDMA Instance
2108 * @retval None
2109 */
2110 __STATIC_INLINE void LL_BDMA_ClearFlag_TE2(BDMA_TypeDef *BDMAx)
2111 {
2112 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF2);
2113 }
2114
2115 /**
2116 * @brief Clear Channel 3 transfer error flag.
2117 * @rmtoll IFCR CTEIF3 LL_BDMA_ClearFlag_TE3
2118 * @param BDMAx BDMA Instance
2119 * @retval None
2120 */
2121 __STATIC_INLINE void LL_BDMA_ClearFlag_TE3(BDMA_TypeDef *BDMAx)
2122 {
2123 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF3);
2124 }
2125
2126 /**
2127 * @brief Clear Channel 4 transfer error flag.
2128 * @rmtoll IFCR CTEIF4 LL_BDMA_ClearFlag_TE4
2129 * @param BDMAx BDMA Instance
2130 * @retval None
2131 */
2132 __STATIC_INLINE void LL_BDMA_ClearFlag_TE4(BDMA_TypeDef *BDMAx)
2133 {
2134 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF4);
2135 }
2136
2137 /**
2138 * @brief Clear Channel 5 transfer error flag.
2139 * @rmtoll IFCR CTEIF5 LL_BDMA_ClearFlag_TE5
2140 * @param BDMAx BDMA Instance
2141 * @retval None
2142 */
2143 __STATIC_INLINE void LL_BDMA_ClearFlag_TE5(BDMA_TypeDef *BDMAx)
2144 {
2145 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF5);
2146 }
2147
2148 /**
2149 * @brief Clear Channel 6 transfer error flag.
2150 * @rmtoll IFCR CTEIF6 LL_BDMA_ClearFlag_TE6
2151 * @param BDMAx BDMA Instance
2152 * @retval None
2153 */
2154 __STATIC_INLINE void LL_BDMA_ClearFlag_TE6(BDMA_TypeDef *BDMAx)
2155 {
2156 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF6);
2157 }
2158
2159 /**
2160 * @brief Clear Channel 7 transfer error flag.
2161 * @rmtoll IFCR CTEIF7 LL_BDMA_ClearFlag_TE7
2162 * @param BDMAx BDMA Instance
2163 * @retval None
2164 */
2165 __STATIC_INLINE void LL_BDMA_ClearFlag_TE7(BDMA_TypeDef *BDMAx)
2166 {
2167 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF7);
2168 }
2169
2170 /**
2171 * @}
2172 */
2173
2174 /** @defgroup BDMA_LL_EF_IT_Management IT_Management
2175 * @{
2176 */
2177 /**
2178 * @brief Enable Transfer complete interrupt.
2179 * @rmtoll CCR TCIE LL_BDMA_EnableIT_TC
2180 * @param BDMAx BDMA Instance
2181 * @param Channel This parameter can be one of the following values:
2182 * @arg @ref LL_BDMA_CHANNEL_0
2183 * @arg @ref LL_BDMA_CHANNEL_1
2184 * @arg @ref LL_BDMA_CHANNEL_2
2185 * @arg @ref LL_BDMA_CHANNEL_3
2186 * @arg @ref LL_BDMA_CHANNEL_4
2187 * @arg @ref LL_BDMA_CHANNEL_5
2188 * @arg @ref LL_BDMA_CHANNEL_6
2189 * @arg @ref LL_BDMA_CHANNEL_7
2190 * @retval None
2191 */
2192 __STATIC_INLINE void LL_BDMA_EnableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel)
2193 {
2194 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2195
2196 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE);
2197 }
2198
2199 /**
2200 * @brief Enable Half transfer interrupt.
2201 * @rmtoll CCR HTIE LL_BDMA_EnableIT_HT
2202 * @param BDMAx BDMA Instance
2203 * @param Channel This parameter can be one of the following values:
2204 * @arg @ref LL_BDMA_CHANNEL_0
2205 * @arg @ref LL_BDMA_CHANNEL_1
2206 * @arg @ref LL_BDMA_CHANNEL_2
2207 * @arg @ref LL_BDMA_CHANNEL_3
2208 * @arg @ref LL_BDMA_CHANNEL_4
2209 * @arg @ref LL_BDMA_CHANNEL_5
2210 * @arg @ref LL_BDMA_CHANNEL_6
2211 * @arg @ref LL_BDMA_CHANNEL_7
2212 * @retval None
2213 */
2214 __STATIC_INLINE void LL_BDMA_EnableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel)
2215 {
2216 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2217
2218 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE);
2219 }
2220
2221 /**
2222 * @brief Enable Transfer error interrupt.
2223 * @rmtoll CCR TEIE LL_BDMA_EnableIT_TE
2224 * @param BDMAx BDMA Instance
2225 * @param Channel This parameter can be one of the following values:
2226 * @arg @ref LL_BDMA_CHANNEL_0
2227 * @arg @ref LL_BDMA_CHANNEL_1
2228 * @arg @ref LL_BDMA_CHANNEL_2
2229 * @arg @ref LL_BDMA_CHANNEL_3
2230 * @arg @ref LL_BDMA_CHANNEL_4
2231 * @arg @ref LL_BDMA_CHANNEL_5
2232 * @arg @ref LL_BDMA_CHANNEL_6
2233 * @arg @ref LL_BDMA_CHANNEL_7
2234 * @retval None
2235 */
2236 __STATIC_INLINE void LL_BDMA_EnableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel)
2237 {
2238 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2239
2240 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE);
2241 }
2242
2243 /**
2244 * @brief Disable Transfer complete interrupt.
2245 * @rmtoll CCR TCIE LL_BDMA_DisableIT_TC
2246 * @param BDMAx BDMA Instance
2247 * @param Channel This parameter can be one of the following values:
2248 * @arg @ref LL_BDMA_CHANNEL_0
2249 * @arg @ref LL_BDMA_CHANNEL_1
2250 * @arg @ref LL_BDMA_CHANNEL_2
2251 * @arg @ref LL_BDMA_CHANNEL_3
2252 * @arg @ref LL_BDMA_CHANNEL_4
2253 * @arg @ref LL_BDMA_CHANNEL_5
2254 * @arg @ref LL_BDMA_CHANNEL_6
2255 * @arg @ref LL_BDMA_CHANNEL_7
2256 * @retval None
2257 */
2258 __STATIC_INLINE void LL_BDMA_DisableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel)
2259 {
2260 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2261
2262 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE);
2263 }
2264
2265 /**
2266 * @brief Disable Half transfer interrupt.
2267 * @rmtoll CCR HTIE LL_BDMA_DisableIT_HT
2268 * @param BDMAx BDMA Instance
2269 * @param Channel This parameter can be one of the following values:
2270 * @arg @ref LL_BDMA_CHANNEL_0
2271 * @arg @ref LL_BDMA_CHANNEL_1
2272 * @arg @ref LL_BDMA_CHANNEL_2
2273 * @arg @ref LL_BDMA_CHANNEL_3
2274 * @arg @ref LL_BDMA_CHANNEL_4
2275 * @arg @ref LL_BDMA_CHANNEL_5
2276 * @arg @ref LL_BDMA_CHANNEL_6
2277 * @arg @ref LL_BDMA_CHANNEL_7
2278 * @retval None
2279 */
2280 __STATIC_INLINE void LL_BDMA_DisableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel)
2281 {
2282 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2283
2284 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE);
2285 }
2286
2287 /**
2288 * @brief Disable Transfer error interrupt.
2289 * @rmtoll CCR TEIE LL_BDMA_DisableIT_TE
2290 * @param BDMAx BDMA Instance
2291 * @param Channel This parameter can be one of the following values:
2292 * @arg @ref LL_BDMA_CHANNEL_0
2293 * @arg @ref LL_BDMA_CHANNEL_1
2294 * @arg @ref LL_BDMA_CHANNEL_2
2295 * @arg @ref LL_BDMA_CHANNEL_3
2296 * @arg @ref LL_BDMA_CHANNEL_4
2297 * @arg @ref LL_BDMA_CHANNEL_5
2298 * @arg @ref LL_BDMA_CHANNEL_6
2299 * @arg @ref LL_BDMA_CHANNEL_7
2300 * @retval None
2301 */
2302 __STATIC_INLINE void LL_BDMA_DisableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel)
2303 {
2304 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2305
2306 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE);
2307 }
2308
2309 /**
2310 * @brief Check if Transfer complete Interrupt is enabled.
2311 * @rmtoll CCR TCIE LL_BDMA_IsEnabledIT_TC
2312 * @param BDMAx BDMA Instance
2313 * @param Channel This parameter can be one of the following values:
2314 * @arg @ref LL_BDMA_CHANNEL_0
2315 * @arg @ref LL_BDMA_CHANNEL_1
2316 * @arg @ref LL_BDMA_CHANNEL_2
2317 * @arg @ref LL_BDMA_CHANNEL_3
2318 * @arg @ref LL_BDMA_CHANNEL_4
2319 * @arg @ref LL_BDMA_CHANNEL_5
2320 * @arg @ref LL_BDMA_CHANNEL_6
2321 * @arg @ref LL_BDMA_CHANNEL_7
2322 * @retval State of bit (1 or 0).
2323 */
2324 __STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel)
2325 {
2326 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2327
2328 return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE) == (BDMA_CCR_TCIE)) ? 1UL : 0UL);
2329 }
2330
2331 /**
2332 * @brief Check if Half transfer Interrupt is enabled.
2333 * @rmtoll CCR HTIE LL_BDMA_IsEnabledIT_HT
2334 * @param BDMAx BDMA Instance
2335 * @param Channel This parameter can be one of the following values:
2336 * @arg @ref LL_BDMA_CHANNEL_0
2337 * @arg @ref LL_BDMA_CHANNEL_1
2338 * @arg @ref LL_BDMA_CHANNEL_2
2339 * @arg @ref LL_BDMA_CHANNEL_3
2340 * @arg @ref LL_BDMA_CHANNEL_4
2341 * @arg @ref LL_BDMA_CHANNEL_5
2342 * @arg @ref LL_BDMA_CHANNEL_6
2343 * @arg @ref LL_BDMA_CHANNEL_7
2344 * @retval State of bit (1 or 0).
2345 */
2346 __STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel)
2347 {
2348 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2349
2350 return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE) == (BDMA_CCR_HTIE)) ? 1UL : 0UL);
2351 }
2352
2353 /**
2354 * @brief Check if Transfer error Interrupt is enabled.
2355 * @rmtoll CCR TEIE LL_BDMA_IsEnabledIT_TE
2356 * @param BDMAx BDMA Instance
2357 * @param Channel This parameter can be one of the following values:
2358 * @arg @ref LL_BDMA_CHANNEL_0
2359 * @arg @ref LL_BDMA_CHANNEL_1
2360 * @arg @ref LL_BDMA_CHANNEL_2
2361 * @arg @ref LL_BDMA_CHANNEL_3
2362 * @arg @ref LL_BDMA_CHANNEL_4
2363 * @arg @ref LL_BDMA_CHANNEL_5
2364 * @arg @ref LL_BDMA_CHANNEL_6
2365 * @arg @ref LL_BDMA_CHANNEL_7
2366 * @retval State of bit (1 or 0).
2367 */
2368 __STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel)
2369 {
2370 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2371
2372 return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE) == (BDMA_CCR_TEIE)) ? 1UL : 0UL);
2373 }
2374
2375 /**
2376 * @}
2377 */
2378
2379 #if defined(USE_FULL_LL_DRIVER)
2380 /** @defgroup BDMA_LL_EF_Init Initialization and de-initialization functions
2381 * @{
2382 */
2383
2384 uint32_t LL_BDMA_Init(BDMA_TypeDef *BDMAx, uint32_t Channel, LL_BDMA_InitTypeDef *BDMA_InitStruct);
2385 uint32_t LL_BDMA_DeInit(BDMA_TypeDef *BDMAx, uint32_t Channel);
2386 void LL_BDMA_StructInit(LL_BDMA_InitTypeDef *BDMA_InitStruct);
2387
2388 /**
2389 * @}
2390 */
2391 #endif /* USE_FULL_LL_DRIVER */
2392
2393 /**
2394 * @}
2395 */
2396
2397 /**
2398 * @}
2399 */
2400
2401 #endif /* BDMA || BDMA1 || BDMA2 */
2402 /**
2403 * @}
2404 */
2405
2406 /**
2407 * @}
2408 */
2409
2410 /**
2411 * @}
2412 */
2413
2414 #ifdef __cplusplus
2415 }
2416 #endif
2417
2418 #endif /* STM32H7xx_LL_BDMA_H */
2419
2420 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/