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Merge pull request #11270 from haslinghuis/rename_attr
[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_ll_bus.h
blob022cf6d23000abe28a09bb9dd36f60d9116312f0
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_bus.h
4 * @author MCD Application Team
5 * @version $VERSION$
6 * @date $DATE$
7 * @brief Header file of BUS LL module.
8
9 @verbatim
10 ##### RCC Limitations #####
11 ==============================================================================
12 [..]
13 A delay between an RCC peripheral clock enable and the effective peripheral
14 enabling should be taken into account in order to manage the peripheral read/write
15 from/to registers.
16 (+) This delay depends on the peripheral mapping.
17 (++) AHB & APB peripherals, 1 dummy read is necessary
18
19 [..]
20 Workarounds:
21 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
22 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
23
24 @endverbatim
25 ******************************************************************************
26 * @attention
27 *
28 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
29 * All rights reserved.</center></h2>
30 *
31 * This software component is licensed by ST under BSD 3-Clause license,
32 * the "License"; You may not use this file except in compliance with the
33 * License. You may obtain a copy of the License at:
34 * opensource.org/licenses/BSD-3-Clause
35 *
36 ******************************************************************************
37 */
38
39 /* Define to prevent recursive inclusion -------------------------------------*/
40 #ifndef STM32H7xx_LL_BUS_H
41 #define STM32H7xx_LL_BUS_H
42
43 #ifdef __cplusplus
44 extern "C" {
45 #endif
46
47 /* Includes ------------------------------------------------------------------*/
48 #include "stm32h7xx.h"
49
50 /** @addtogroup STM32H7xx_LL_Driver
51 * @{
52 */
53
54 #if defined(RCC)
55
56 /** @defgroup BUS_LL BUS
57 * @{
58 */
59
60 /* Private variables ---------------------------------------------------------*/
61
62 /* Private constants ---------------------------------------------------------*/
63
64 /* Private macros ------------------------------------------------------------*/
65
66 /* Exported types ------------------------------------------------------------*/
67
68 /* Exported constants --------------------------------------------------------*/
69 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
70 * @{
71 */
72
73 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
74 * @{
75 */
76 #define LL_AHB3_GRP1_PERIPH_MDMA RCC_AHB3ENR_MDMAEN
77 #define LL_AHB3_GRP1_PERIPH_DMA2D RCC_AHB3ENR_DMA2DEN
78
79 #if defined(JPEG)
80 #define LL_AHB3_GRP1_PERIPH_JPGDEC RCC_AHB3ENR_JPGDECEN
81 #endif /* JPEG */
82
83 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
84 #if defined(QUADSPI)
85 #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
86 #endif /* QUADSPI */
87 #if defined(OCTOSPI1) || defined(OCTOSPI2)
88 #define LL_AHB3_GRP1_PERIPH_OSPI1 RCC_AHB3ENR_OSPI1EN
89 #define LL_AHB3_GRP1_PERIPH_OSPI2 RCC_AHB3ENR_OSPI2EN
90 #endif /*(OCTOSPI1) || (OCTOSPI2)*/
91 #if defined(OCTOSPIM)
92 #define LL_AHB3_GRP1_PERIPH_OCTOSPIM RCC_AHB3ENR_IOMNGREN
93 #endif /* OCTOSPIM */
94 #if defined(OTFDEC1) || defined(OTFDEC2)
95 #define LL_AHB3_GRP1_PERIPH_OTFDEC1 RCC_AHB3ENR_OTFDEC1EN
96 #define LL_AHB3_GRP1_PERIPH_OTFDEC2 RCC_AHB3ENR_OTFDEC2EN
97 #endif /* (OTFDEC1) || (OTFDEC2) */
98 #if defined(GFXMMU)
99 #define LL_AHB3_GRP1_PERIPH_GFXMMU RCC_AHB3ENR_GFXMMUEN
100 #endif /* GFXMMU */
101 #define LL_AHB3_GRP1_PERIPH_SDMMC1 RCC_AHB3ENR_SDMMC1EN
102 #define LL_AHB3_GRP1_PERIPH_FLASH RCC_AHB3LPENR_FLASHLPEN
103 #define LL_AHB3_GRP1_PERIPH_DTCM1 RCC_AHB3LPENR_DTCM1LPEN
104 #define LL_AHB3_GRP1_PERIPH_DTCM2 RCC_AHB3LPENR_DTCM2LPEN
105 #define LL_AHB3_GRP1_PERIPH_ITCM RCC_AHB3LPENR_ITCMLPEN
106 #if defined(RCC_AHB3LPENR_AXISRAMLPEN)
107 #define LL_AHB3_GRP1_PERIPH_AXISRAM RCC_AHB3LPENR_AXISRAMLPEN
108 #else
109 #define LL_AHB3_GRP1_PERIPH_AXISRAM1 RCC_AHB3LPENR_AXISRAM1LPEN
110 #define LL_AHB3_GRP1_PERIPH_AXISRAM LL_AHB3_GRP1_PERIPH_AXISRAM1 /* for backward compatibility*/
111 #endif /* RCC_AHB3LPENR_AXISRAMLPEN */
112 #if defined(CD_AXISRAM2_BASE)
113 #define LL_AHB3_GRP1_PERIPH_AXISRAM2 RCC_AHB3LPENR_AXISRAM2LPEN
114 #endif /* CD_AXISRAM2_BASE */
115 #if defined(CD_AXISRAM3_BASE)
116 #define LL_AHB3_GRP1_PERIPH_AXISRAM3 RCC_AHB3LPENR_AXISRAM3LPEN
117 #endif /* CD_AXISRAM3_BASE */
118 /**
119 * @}
120 */
121
122
123 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
124 * @{
125 */
126 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
127 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
128 #define LL_AHB1_GRP1_PERIPH_ADC12 RCC_AHB1ENR_ADC12EN
129 #if defined(DUAL_CORE)
130 #define LL_AHB1_GRP1_PERIPH_ART RCC_AHB1ENR_ARTEN
131 #endif /* DUAL_CORE */
132 #if defined(RCC_AHB1ENR_CRCEN)
133 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
134 #endif /* RCC_AHB1ENR_CRCEN */
135 #if defined(ETH)
136 #define LL_AHB1_GRP1_PERIPH_ETH1MAC RCC_AHB1ENR_ETH1MACEN
137 #define LL_AHB1_GRP1_PERIPH_ETH1TX RCC_AHB1ENR_ETH1TXEN
138 #define LL_AHB1_GRP1_PERIPH_ETH1RX RCC_AHB1ENR_ETH1RXEN
139 #endif /* ETH */
140 #define LL_AHB1_GRP1_PERIPH_USB1OTGHS RCC_AHB1ENR_USB1OTGHSEN
141 #define LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI RCC_AHB1ENR_USB1OTGHSULPIEN
142 #if defined(USB2_OTG_FS)
143 #define LL_AHB1_GRP1_PERIPH_USB2OTGHS RCC_AHB1ENR_USB2OTGHSEN
144 #define LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI RCC_AHB1ENR_USB2OTGHSULPIEN
145 #endif /* USB2_OTG_FS */
146 /**
147 * @}
148 */
149
150
151 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
152 * @{
153 */
154 #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN
155 #if defined(HSEM) && defined(RCC_AHB2ENR_HSEMEN)
156 #define LL_AHB2_GRP1_PERIPH_HSEM RCC_AHB2ENR_HSEMEN
157 #endif /* HSEM && RCC_AHB2ENR_HSEMEN */
158 #if defined(CRYP)
159 #define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN
160 #endif /* CRYP */
161 #if defined(HASH)
162 #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
163 #endif /* HASH */
164 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
165 #define LL_AHB2_GRP1_PERIPH_SDMMC2 RCC_AHB2ENR_SDMMC2EN
166 #if defined(FMAC)
167 #define LL_AHB2_GRP1_PERIPH_FMAC RCC_AHB2ENR_FMACEN
168 #endif /* FMAC */
169 #if defined(CORDIC)
170 #define LL_AHB2_GRP1_PERIPH_CORDIC RCC_AHB2ENR_CORDICEN
171 #endif /* CORDIC */
172 #if defined(BDMA1)
173 #define LL_AHB2_GRP1_PERIPH_BDMA1 RCC_AHB2ENR_BDMA1EN
174 #endif /* BDMA1 */
175 #if defined(RCC_AHB2ENR_D2SRAM1EN)
176 #define LL_AHB2_GRP1_PERIPH_D2SRAM1 RCC_AHB2ENR_D2SRAM1EN
177 #else
178 #define LL_AHB2_GRP1_PERIPH_AHBSRAM1 RCC_AHB2ENR_AHBSRAM1EN
179 #define LL_AHB2_GRP1_PERIPH_D2SRAM1 LL_AHB2_GRP1_PERIPH_AHBSRAM1 /* for backward compatibility*/
180 #endif /* RCC_AHB2ENR_D2SRAM1EN */
181 #if defined(RCC_AHB2ENR_D2SRAM2EN)
182 #define LL_AHB2_GRP1_PERIPH_D2SRAM2 RCC_AHB2ENR_D2SRAM2EN
183 #else
184 #define LL_AHB2_GRP1_PERIPH_AHBSRAM2 RCC_AHB2ENR_AHBSRAM2EN
185 #define LL_AHB2_GRP1_PERIPH_D2SRAM2 LL_AHB2_GRP1_PERIPH_AHBSRAM2 /* for backward compatibility*/
186 #endif /* RCC_AHB2ENR_D2SRAM2EN */
187 #if defined(RCC_AHB2ENR_D2SRAM3EN)
188 #define LL_AHB2_GRP1_PERIPH_D2SRAM3 RCC_AHB2ENR_D2SRAM3EN
189 #endif /* RCC_AHB2ENR_D2SRAM3EN */
190 /**
191 * @}
192 */
193
194
195 /** @defgroup BUS_LL_EC_AHB4_GRP1_PERIPH AHB4 GRP1 PERIPH
196 * @{
197 */
198 #define LL_AHB4_GRP1_PERIPH_GPIOA RCC_AHB4ENR_GPIOAEN
199 #define LL_AHB4_GRP1_PERIPH_GPIOB RCC_AHB4ENR_GPIOBEN
200 #define LL_AHB4_GRP1_PERIPH_GPIOC RCC_AHB4ENR_GPIOCEN
201 #define LL_AHB4_GRP1_PERIPH_GPIOD RCC_AHB4ENR_GPIODEN
202 #define LL_AHB4_GRP1_PERIPH_GPIOE RCC_AHB4ENR_GPIOEEN
203 #define LL_AHB4_GRP1_PERIPH_GPIOF RCC_AHB4ENR_GPIOFEN
204 #define LL_AHB4_GRP1_PERIPH_GPIOG RCC_AHB4ENR_GPIOGEN
205 #define LL_AHB4_GRP1_PERIPH_GPIOH RCC_AHB4ENR_GPIOHEN
206 #if defined(GPIOI)
207 #define LL_AHB4_GRP1_PERIPH_GPIOI RCC_AHB4ENR_GPIOIEN
208 #endif /* GPIOI */
209 #define LL_AHB4_GRP1_PERIPH_GPIOJ RCC_AHB4ENR_GPIOJEN
210 #define LL_AHB4_GRP1_PERIPH_GPIOK RCC_AHB4ENR_GPIOKEN
211 #if defined(RCC_AHB4ENR_CRCEN)
212 #define LL_AHB4_GRP1_PERIPH_CRC RCC_AHB4ENR_CRCEN
213 #endif /* RCC_AHB4ENR_CRCEN */
214 #if defined(BDMA2)
215 #define LL_AHB4_GRP1_PERIPH_BDMA2 RCC_AHB4ENR_BDMA2EN
216 #define LL_AHB4_GRP1_PERIPH_BDMA LL_AHB4_GRP1_PERIPH_BDMA2 /* for backward compatibility*/
217 #else
218 #define LL_AHB4_GRP1_PERIPH_BDMA RCC_AHB4ENR_BDMAEN
219 #endif /* BDMA2 */
220 #if defined(ADC3)
221 #define LL_AHB4_GRP1_PERIPH_ADC3 RCC_AHB4ENR_ADC3EN
222 #endif /* ADC3 */
223 #if defined(HSEM) && defined(RCC_AHB4ENR_HSEMEN)
224 #define LL_AHB4_GRP1_PERIPH_HSEM RCC_AHB4ENR_HSEMEN
225 #endif /* HSEM && RCC_AHB4ENR_HSEMEN*/
226 #define LL_AHB4_GRP1_PERIPH_BKPRAM RCC_AHB4ENR_BKPRAMEN
227 #if defined(RCC_AHB4LPENR_SRAM4LPEN)
228 #define LL_AHB4_GRP1_PERIPH_SRAM4 RCC_AHB4LPENR_SRAM4LPEN
229 #define LL_AHB4_GRP1_PERIPH_D3SRAM1 LL_AHB4_GRP1_PERIPH_SRAM4
230 #else
231 #define LL_AHB4_GRP1_PERIPH_SRDSRAM RCC_AHB4ENR_SRDSRAMEN
232 #define LL_AHB4_GRP1_PERIPH_SRAM4 LL_AHB4_GRP1_PERIPH_SRDSRAM /* for backward compatibility*/
233 #define LL_AHB4_GRP1_PERIPH_D3SRAM1 LL_AHB4_GRP1_PERIPH_SRDSRAM /* for backward compatibility*/
234 #endif /* RCC_AHB4ENR_D3SRAM1EN */
235 /**
236 * @}
237 */
238
239
240 /** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH APB3 GRP1 PERIPH
241 * @{
242 */
243 #if defined(LTDC)
244 #define LL_APB3_GRP1_PERIPH_LTDC RCC_APB3ENR_LTDCEN
245 #endif /* LTDC */
246 #if defined(DSI)
247 #define LL_APB3_GRP1_PERIPH_DSI RCC_APB3ENR_DSIEN
248 #endif /* DSI */
249 #define LL_APB3_GRP1_PERIPH_WWDG1 RCC_APB3ENR_WWDG1EN
250 #if defined(RCC_APB3ENR_WWDGEN)
251 #define LL_APB3_GRP1_PERIPH_WWDG LL_APB3_GRP1_PERIPH_WWDG1 /* for backward compatibility*/
252 #endif
253 /**
254 * @}
255 */
256
257
258 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
259 * @{
260 */
261 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1LENR_TIM2EN
262 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1LENR_TIM3EN
263 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1LENR_TIM4EN
264 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1LENR_TIM5EN
265 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1LENR_TIM6EN
266 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1LENR_TIM7EN
267 #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1LENR_TIM12EN
268 #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1LENR_TIM13EN
269 #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1LENR_TIM14EN
270 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1LENR_LPTIM1EN
271 #if defined(DUAL_CORE)
272 #define LL_APB1_GRP1_PERIPH_WWDG2 RCC_APB1LENR_WWDG2EN
273 #endif /*DUAL_CORE*/
274 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1LENR_SPI2EN
275 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1LENR_SPI3EN
276 #define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1LENR_SPDIFRXEN
277 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1LENR_USART2EN
278 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1LENR_USART3EN
279 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1LENR_UART4EN
280 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1LENR_UART5EN
281 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1LENR_I2C1EN
282 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1LENR_I2C2EN
283 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1LENR_I2C3EN
284 #if defined(I2C5)
285 #define LL_APB1_GRP1_PERIPH_I2C5 RCC_APB1LENR_I2C5EN
286 #endif /* I2C5 */
287 #if defined(RCC_APB1LENR_CECEN)
288 #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1LENR_CECEN
289 #else
290 #define LL_APB1_GRP1_PERIPH_HDMICEC RCC_APB1LENR_HDMICECEN
291 #define LL_APB1_GRP1_PERIPH_CEC LL_APB1_GRP1_PERIPH_HDMICEC /* for backward compatibility*/
292 #endif /* RCC_APB1LENR_CECEN */
293 #define LL_APB1_GRP1_PERIPH_DAC12 RCC_APB1LENR_DAC12EN
294 #define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1LENR_UART7EN
295 #define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1LENR_UART8EN
296 /**
297 * @}
298 */
299
300
301 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
302 * @{
303 */
304 #define LL_APB1_GRP2_PERIPH_CRS RCC_APB1HENR_CRSEN
305 #define LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1HENR_SWPMIEN
306 #define LL_APB1_GRP2_PERIPH_OPAMP RCC_APB1HENR_OPAMPEN
307 #define LL_APB1_GRP2_PERIPH_MDIOS RCC_APB1HENR_MDIOSEN
308 #define LL_APB1_GRP2_PERIPH_FDCAN RCC_APB1HENR_FDCANEN
309 #if defined(TIM23)
310 #define LL_APB1_GRP2_PERIPH_TIM23 RCC_APB1HENR_TIM23EN
311 #endif /* TIM23 */
312 #if defined(TIM24)
313 #define LL_APB1_GRP2_PERIPH_TIM24 RCC_APB1HENR_TIM24EN
314 #endif /* TIM24 */
315 /**
316 * @}
317 */
318
319
320 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
321 * @{
322 */
323 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
324 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
325 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
326 #define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN
327 #if defined(UART9)
328 #define LL_APB2_GRP1_PERIPH_UART9 RCC_APB2ENR_UART9EN
329 #endif /* UART9 */
330 #if defined(USART10)
331 #define LL_APB2_GRP1_PERIPH_USART10 RCC_APB2ENR_USART10EN
332 #endif /* USART10 */
333 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
334 #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
335 #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
336 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
337 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
338 #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN
339 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
340 #if defined(SAI2)
341 #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
342 #endif /* SAI2 */
343 #if defined(SAI3)
344 #define LL_APB2_GRP1_PERIPH_SAI3 RCC_APB2ENR_SAI3EN
345 #endif /* SAI3 */
346 #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN
347 #if defined(HRTIM1)
348 #define LL_APB2_GRP1_PERIPH_HRTIM RCC_APB2ENR_HRTIMEN
349 #endif /* HRTIM1 */
350 /**
351 * @}
352 */
353
354
355 /** @defgroup BUS_LL_EC_APB4_GRP1_PERIPH APB4 GRP1 PERIPH
356 * @{
357 */
358 #define LL_APB4_GRP1_PERIPH_SYSCFG RCC_APB4ENR_SYSCFGEN
359 #define LL_APB4_GRP1_PERIPH_LPUART1 RCC_APB4ENR_LPUART1EN
360 #define LL_APB4_GRP1_PERIPH_SPI6 RCC_APB4ENR_SPI6EN
361 #define LL_APB4_GRP1_PERIPH_I2C4 RCC_APB4ENR_I2C4EN
362 #define LL_APB4_GRP1_PERIPH_LPTIM2 RCC_APB4ENR_LPTIM2EN
363 #define LL_APB4_GRP1_PERIPH_LPTIM3 RCC_APB4ENR_LPTIM3EN
364 #if defined(LPTIM4)
365 #define LL_APB4_GRP1_PERIPH_LPTIM4 RCC_APB4ENR_LPTIM4EN
366 #endif /* LPTIM4 */
367 #if defined(LPTIM5)
368 #define LL_APB4_GRP1_PERIPH_LPTIM5 RCC_APB4ENR_LPTIM5EN
369 #endif /* LPTIM5 */
370 #if defined(DAC2)
371 #define LL_APB4_GRP1_PERIPH_DAC2 RCC_APB4ENR_DAC2EN
372 #endif /* DAC2 */
373 #define LL_APB4_GRP1_PERIPH_COMP12 RCC_APB4ENR_COMP12EN
374 #define LL_APB4_GRP1_PERIPH_VREF RCC_APB4ENR_VREFEN
375 #define LL_APB4_GRP1_PERIPH_RTCAPB RCC_APB4ENR_RTCAPBEN
376 #if defined(SAI4)
377 #define LL_APB4_GRP1_PERIPH_SAI4 RCC_APB4ENR_SAI4EN
378 #endif /* SAI4 */
379 #if defined(DTS)
380 #define LL_APB4_GRP1_PERIPH_DTS RCC_APB4ENR_DTSEN
381 #endif /*DTS*/
382 #if defined(DFSDM2_BASE)
383 #define LL_APB4_GRP1_PERIPH_DFSDM2 RCC_APB4ENR_DFSDM2EN
384 #endif /* DFSDM2_BASE */
385 /**
386 * @}
387 */
388
389 /** @defgroup BUS_LL_EC_CLKAM_PERIPH CLKAM PERIPH
390 * @{
391 */
392 #if defined(RCC_D3AMR_BDMAAMEN)
393 #define LL_CLKAM_PERIPH_BDMA RCC_D3AMR_BDMAAMEN
394 #else
395 #define LL_CLKAM_PERIPH_BDMA2 RCC_SRDAMR_BDMA2AMEN
396 #define LL_CLKAM_PERIPH_BDMA LL_CLKAM_PERIPH_BDMA2 /* for backward compatibility*/
397 #endif /* RCC_D3AMR_BDMAAMEN */
398 #if defined(RCC_SRDAMR_GPIOAMEN)
399 #define LL_CLKAM_PERIPH_GPIO RCC_SRDAMR_GPIOAMEN
400 #endif /* RCC_SRDAMR_GPIOAMEN */
401 #if defined(RCC_D3AMR_LPUART1AMEN)
402 #define LL_CLKAM_PERIPH_LPUART1 RCC_D3AMR_LPUART1AMEN
403 #else
404 #define LL_CLKAM_PERIPH_LPUART1 RCC_SRDAMR_LPUART1AMEN
405 #endif /* RCC_D3AMR_LPUART1AMEN */
406 #if defined(RCC_D3AMR_SPI6AMEN)
407 #define LL_CLKAM_PERIPH_SPI6 RCC_D3AMR_SPI6AMEN
408 #else
409 #define LL_CLKAM_PERIPH_SPI6 RCC_SRDAMR_SPI6AMEN
410 #endif /* RCC_D3AMR_SPI6AMEN */
411 #if defined(RCC_D3AMR_I2C4AMEN)
412 #define LL_CLKAM_PERIPH_I2C4 RCC_D3AMR_I2C4AMEN
413 #else
414 #define LL_CLKAM_PERIPH_I2C4 RCC_SRDAMR_I2C4AMEN
415 #endif /* RCC_D3AMR_I2C4AMEN */
416 #if defined(RCC_D3AMR_LPTIM2AMEN)
417 #define LL_CLKAM_PERIPH_LPTIM2 RCC_D3AMR_LPTIM2AMEN
418 #else
419 #define LL_CLKAM_PERIPH_LPTIM2 RCC_SRDAMR_LPTIM2AMEN
420 #endif /* RCC_D3AMR_LPTIM2AMEN */
421 #if defined(RCC_D3AMR_LPTIM3AMEN)
422 #define LL_CLKAM_PERIPH_LPTIM3 RCC_D3AMR_LPTIM3AMEN
423 #else
424 #define LL_CLKAM_PERIPH_LPTIM3 RCC_SRDAMR_LPTIM3AMEN
425 #endif /* RCC_D3AMR_LPTIM3AMEN */
426 #if defined(RCC_D3AMR_LPTIM4AMEN)
427 #define LL_CLKAM_PERIPH_LPTIM4 RCC_D3AMR_LPTIM4AMEN
428 #endif /* RCC_D3AMR_LPTIM4AMEN */
429 #if defined(RCC_D3AMR_LPTIM5AMEN)
430 #define LL_CLKAM_PERIPH_LPTIM5 RCC_D3AMR_LPTIM5AMEN
431 #endif /* RCC_D3AMR_LPTIM5AMEN */
432 #if defined(DAC2)
433 #define LL_CLKAM_PERIPH_DAC2 RCC_SRDAMR_DAC2AMEN
434 #endif /* DAC2 */
435 #if defined(RCC_D3AMR_COMP12AMEN)
436 #define LL_CLKAM_PERIPH_COMP12 RCC_D3AMR_COMP12AMEN
437 #else
438 #define LL_CLKAM_PERIPH_COMP12 RCC_SRDAMR_COMP12AMEN
439 #endif /* RCC_D3AMR_COMP12AMEN */
440 #if defined(RCC_D3AMR_VREFAMEN)
441 #define LL_CLKAM_PERIPH_VREF RCC_D3AMR_VREFAMEN
442 #else
443 #define LL_CLKAM_PERIPH_VREF RCC_SRDAMR_VREFAMEN
444 #endif /* RCC_D3AMR_VREFAMEN */
445 #if defined(RCC_D3AMR_RTCAMEN)
446 #define LL_CLKAM_PERIPH_RTC RCC_D3AMR_RTCAMEN
447 #else
448 #define LL_CLKAM_PERIPH_RTC RCC_SRDAMR_RTCAMEN
449 #endif /* RCC_D3AMR_RTCAMEN */
450 #if defined(RCC_D3AMR_CRCAMEN)
451 #define LL_CLKAM_PERIPH_CRC RCC_D3AMR_CRCAMEN
452 #endif /* RCC_D3AMR_CRCAMEN */
453 #if defined(SAI4)
454 #define LL_CLKAM_PERIPH_SAI4 RCC_D3AMR_SAI4AMEN
455 #endif /* SAI4 */
456 #if defined(ADC3)
457 #define LL_CLKAM_PERIPH_ADC3 RCC_D3AMR_ADC3AMEN
458 #endif /* ADC3 */
459 #if defined(RCC_SRDAMR_DTSAMEN)
460 #define LL_CLKAM_PERIPH_DTS RCC_SRDAMR_DTSAMEN
461 #endif /* RCC_SRDAMR_DTSAMEN */
462 #if defined(RCC_D3AMR_DTSAMEN)
463 #define LL_CLKAM_PERIPH_DTS RCC_D3AMR_DTSAMEN
464 #endif /* RCC_D3AMR_DTSAMEN */
465 #if defined(DFSDM2_BASE)
466 #define LL_CLKAM_PERIPH_DFSDM2 RCC_SRDAMR_DFSDM2AMEN
467 #endif /* DFSDM2_BASE */
468 #if defined(RCC_D3AMR_BKPRAMAMEN)
469 #define LL_CLKAM_PERIPH_BKPRAM RCC_D3AMR_BKPRAMAMEN
470 #else
471 #define LL_CLKAM_PERIPH_BKPRAM RCC_SRDAMR_BKPRAMAMEN
472 #endif /* RCC_D3AMR_BKPRAMAMEN */
473 #if defined(RCC_D3AMR_SRAM4AMEN)
474 #define LL_CLKAM_PERIPH_SRAM4 RCC_D3AMR_SRAM4AMEN
475 #else
476 #define LL_CLKAM_PERIPH_SRDSRAM RCC_SRDAMR_SRDSRAMAMEN
477 #define LL_CLKAM_PERIPH_SRAM4 LL_CLKAM_PERIPH_SRDSRAM
478 #endif /* RCC_D3AMR_SRAM4AMEN */
479 /**
480 * @}
481 */
482
483 #if defined(RCC_CKGAENR_AXICKG)
484 /** @defgroup BUS_LL_EC_CKGA_PERIPH CKGA (AXI Clocks Gating) PERIPH
485 * @{
486 */
487 #define LL_CKGA_PERIPH_AXI RCC_CKGAENR_AXICKG
488 #define LL_CKGA_PERIPH_AHB RCC_CKGAENR_AHBCKG
489 #define LL_CKGA_PERIPH_CPU RCC_CKGAENR_CPUCKG
490 #define LL_CKGA_PERIPH_SDMMC RCC_CKGAENR_SDMMCCKG
491 #define LL_CKGA_PERIPH_MDMA RCC_CKGAENR_MDMACKG
492 #define LL_CKGA_PERIPH_DMA2D RCC_CKGAENR_DMA2DCKG
493 #define LL_CKGA_PERIPH_LTDC RCC_CKGAENR_LTDCCKG
494 #define LL_CKGA_PERIPH_GFXMMUM RCC_CKGAENR_GFXMMUMCKG
495 #define LL_CKGA_PERIPH_AHB12 RCC_CKGAENR_AHB12CKG
496 #define LL_CKGA_PERIPH_AHB34 RCC_CKGAENR_AHB34CKG
497 #define LL_CKGA_PERIPH_FLIFT RCC_CKGAENR_FLIFTCKG
498 #define LL_CKGA_PERIPH_OCTOSPI2 RCC_CKGAENR_OCTOSPI2CKG
499 #define LL_CKGA_PERIPH_FMC RCC_CKGAENR_FMCCKG
500 #define LL_CKGA_PERIPH_OCTOSPI1 RCC_CKGAENR_OCTOSPI1CKG
501 #define LL_CKGA_PERIPH_AXIRAM1 RCC_CKGAENR_AXIRAM1CKG
502 #define LL_CKGA_PERIPH_AXIRAM2 RCC_CKGAENR_AXIRAM2CKG
503 #define LL_CKGA_PERIPH_AXIRAM3 RCC_CKGAENR_AXIRAM3CKG
504 #define LL_CKGA_PERIPH_GFXMMUS RCC_CKGAENR_GFXMMUSCKG
505 #define LL_CKGA_PERIPH_ECCRAM RCC_CKGAENR_ECCRAMCKG
506 #define LL_CKGA_PERIPH_EXTI RCC_CKGAENR_EXTICKG
507 #define LL_CKGA_PERIPH_JTAG RCC_CKGAENR_JTAGCKG
508 /**
509 * @}
510 */
511 #endif /* RCC_CKGAENR_AXICKG */
512
513 /**
514 * @}
515 */
516
517 /* Exported macro ------------------------------------------------------------*/
518
519 /* Exported functions --------------------------------------------------------*/
520
521 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
522 * @{
523 */
524
525 /** @defgroup BUS_LL_EF_AHB3 AHB3
526 * @{
527 */
528
529 /**
530 * @brief Enable AHB3 peripherals clock.
531 * @rmtoll AHB3ENR MDMAEN LL_AHB3_GRP1_EnableClock\n
532 * AHB3ENR DMA2DEN LL_AHB3_GRP1_EnableClock\n
533 * AHB3ENR JPGDECEN LL_AHB3_GRP1_EnableClock\n
534 * AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n
535 * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock\n (*)
536 * AHB3ENR OSPI1EN LL_AHB3_GRP1_EnableClock\n (*)
537 * AHB3ENR OSPI2EN LL_AHB3_GRP1_EnableClock\n (*)
538 * AHB3ENR IOMNGREN LL_AHB3_GRP1_EnableClock\n (*)
539 * AHB3ENR OTFDEC1EN LL_AHB3_GRP1_EnableClock\n (*)
540 * AHB3ENR OTFDEC2EN LL_AHB3_GRP1_EnableClock\n (*)
541 * AHB3ENR GFXMMU LL_AHB3_GRP1_EnableClock\n (*)
542 * AHB3ENR SDMMC1EN LL_AHB3_GRP1_EnableClock\n
543 * AHB3ENR FLASHEN LL_AHB3_GRP1_EnableClock\n (*)
544 * AHB3ENR DTCM1EN LL_AHB3_GRP1_EnableClock\n (*)
545 * AHB3ENR DTCM2EN LL_AHB3_GRP1_EnableClock\n (*)
546 * AHB3ENR ITCMEN LL_AHB3_GRP1_EnableClock\n (*)
547 * AHB3ENR AXISRAMEN LL_AHB3_GRP1_EnableClock (*)
548 * @param Periphs This parameter can be a combination of the following values:
549 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
550 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
551 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
552 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
553 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
554 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
555 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
556 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
557 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
558 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
559 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
560 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
561 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)
562 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)
563 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)
564 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)
565 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
566 *
567 * (*) value not defined in all devices.
568 * @retval None
569 */
570 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
571 {
572 __IO uint32_t tmpreg;
573 SET_BIT(RCC->AHB3ENR, Periphs);
574 /* Delay after an RCC peripheral clock enabling */
575 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
576 (void)tmpreg;
577 }
578
579 /**
580 * @brief Check if AHB3 peripheral clock is enabled or not
581 * @rmtoll AHB3ENR MDMAEN LL_AHB3_GRP1_IsEnabledClock\n
582 * AHB3ENR DMA2DEN LL_AHB3_GRP1_IsEnabledClock\n
583 * AHB3ENR JPGDECEN LL_AHB3_GRP1_IsEnabledClock\n
584 * AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n
585 * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock\n (*)
586 * AHB3ENR OSPI1EN LL_AHB3_GRP1_IsEnabledClock\n (*)
587 * AHB3ENR OSPI2EN LL_AHB3_GRP1_IsEnabledClock\n (*)
588 * AHB3ENR IOMNGREN LL_AHB3_GRP1_IsEnabledClock\n (*)
589 * AHB3ENR OTFDEC1EN LL_AHB3_GRP1_IsEnabledClock\n (*)
590 * AHB3ENR OTFDEC2EN LL_AHB3_GRP1_IsEnabledClock\n (*)
591 * AHB3ENR GFXMMU LL_AHB3_GRP1_IsEnabledClock\n (*)
592 * AHB3ENR SDMMC1EN LL_AHB3_GRP1_IsEnabledClock\n
593 * AHB3ENR FLASHEN LL_AHB3_GRP1_IsEnabledClock\n (*)
594 * AHB3ENR DTCM1EN LL_AHB3_GRP1_IsEnabledClock\n (*)
595 * AHB3ENR DTCM2EN LL_AHB3_GRP1_IsEnabledClock\n (*)
596 * AHB3ENR ITCMEN LL_AHB3_GRP1_IsEnabledClock\n (*)
597 * AHB3ENR AXISRAMEN LL_AHB3_GRP1_IsEnabledClock (*)
598 * @param Periphs This parameter can be a combination of the following values:
599 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
600 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
601 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
602 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
603 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
604 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
605 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
606 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
607 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
608 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
609 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
610 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
611 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)
612 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)
613 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)
614 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)
615 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
616 *
617 * (*) value not defined in all devices.
618 * @retval uint32_t
619 */
620 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
621 {
622 return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs)?1U:0U);
623 }
624
625 /**
626 * @brief Disable AHB3 peripherals clock.
627 * @rmtoll AHB3ENR MDMAEN LL_AHB3_GRP1_DisableClock\n
628 * AHB3ENR DMA2DEN LL_AHB3_GRP1_DisableClock\n
629 * AHB3ENR JPGDECEN LL_AHB3_GRP1_DisableClock\n
630 * AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n
631 * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock\n (*)
632 * AHB3ENR OSPI1EN LL_AHB3_GRP1_DisableClock\n (*)
633 * AHB3ENR OSPI2EN LL_AHB3_GRP1_DisableClock\n (*)
634 * AHB3ENR IOMNGREN LL_AHB3_GRP1_DisableClock\n (*)
635 * AHB3ENR OTFDEC1EN LL_AHB3_GRP1_DisableClock\n (*)
636 * AHB3ENR OTFDEC2EN LL_AHB3_GRP1_DisableClock\n (*)
637 * AHB3ENR GFXMMU LL_AHB3_GRP1_DisableClock\n (*)
638 * AHB3ENR SDMMC1EN LL_AHB3_GRP1_DisableClock\n (*)
639 * AHB3ENR FLASHEN LL_AHB3_GRP1_DisableClock\n (*)
640 * AHB3ENR DTCM1EN LL_AHB3_GRP1_DisableClock\n (*)
641 * AHB3ENR DTCM2EN LL_AHB3_GRP1_DisableClock\n (*)
642 * AHB3ENR ITCMEN LL_AHB3_GRP1_DisableClock\n (*)
643 * AHB3ENR AXISRAMEN LL_AHB3_GRP1_DisableClock
644 * @param Periphs This parameter can be a combination of the following values:
645 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
646 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
647 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
648 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
649 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
650 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
651 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
652 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
653 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
654 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
655 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
656 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
657 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)
658 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)
659 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)
660 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)
661 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
662 *
663 * (*) value not defined in all devices.
664 * @retval None
665 */
666 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
667 {
668 CLEAR_BIT(RCC->AHB3ENR, Periphs);
669 }
670
671 /**
672 * @brief Force AHB3 peripherals reset.
673 * @rmtoll AHB3RSTR MDMARST LL_AHB3_GRP1_ForceReset\n
674 * AHB3RSTR DMA2DRST LL_AHB3_GRP1_ForceReset\n
675 * AHB3RSTR JPGDECRST LL_AHB3_GRP1_ForceReset\n
676 * AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
677 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset\n (*)
678 * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ForceReset\n (*)
679 * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ForceReset\n (*)
680 * AHB3RSTR IOMNGRRST LL_AHB3_GRP1_ForceReset\n (*)
681 * AHB3RSTR OTFDEC1RST LL_AHB3_GRP1_ForceReset\n (*)
682 * AHB3RSTR OTFDEC2RST LL_AHB3_GRP1_ForceReset\n (*)
683 * AHB3RSTR GFXMMURST LL_AHB3_GRP1_ForceReset\n (*)
684 * AHB3RSTR SDMMC1RST LL_AHB3_GRP1_ForceReset
685 * @param Periphs This parameter can be a combination of the following values:
686 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
687 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
688 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
689 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
690 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
691 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
692 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
693 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
694 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
695 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
696 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
697 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
698 *
699 * (*) value not defined in all devices.
700 * @retval None
701 */
702 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
703 {
704 SET_BIT(RCC->AHB3RSTR, Periphs);
705 }
706
707 /**
708 * @brief Release AHB3 peripherals reset.
709 * @rmtoll AHB3RSTR MDMARST LL_AHB3_GRP1_ReleaseReset\n
710 * AHB3RSTR DMA2DRST LL_AHB3_GRP1_ReleaseReset\n
711 * AHB3RSTR JPGDECRST LL_AHB3_GRP1_ReleaseReset\n
712 * AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n
713 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset\n
714 * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ReleaseReset\n (*)
715 * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ReleaseReset\n (*)
716 * AHB3RSTR IOMNGRRST LL_AHB3_GRP1_ReleaseReset\n (*)
717 * AHB3RSTR OTFDEC1RST LL_AHB3_GRP1_ReleaseReset\n (*)
718 * AHB3RSTR OTFDEC2RST LL_AHB3_GRP1_ReleaseReset\n (*)
719 * AHB3RSTR GFXMMURST LL_AHB3_GRP1_ReleaseReset\n (*)
720 * AHB3RSTR SDMMC1RST LL_AHB3_GRP1_ReleaseReset
721 * @param Periphs This parameter can be a combination of the following values:
722 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
723 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
724 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
725 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
726 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
727 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
728 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
729 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
730 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
731 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
732 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
733 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
734 *
735 * (*) value not defined in all devices.
736 * @retval None
737 */
738 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
739 {
740 CLEAR_BIT(RCC->AHB3RSTR, Periphs);
741 }
742
743 /**
744 * @brief Enable AHB3 peripherals clock during Low Power (Sleep) mode.
745 * @rmtoll AHB3LPENR MDMALPEN LL_AHB3_GRP1_EnableClockSleep\n
746 * AHB3LPENR DMA2DLPEN LL_AHB3_GRP1_EnableClockSleep\n
747 * AHB3LPENR JPGDECLPEN LL_AHB3_GRP1_EnableClockSleep\n
748 * AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockSleep\n
749 * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockSleep\n (*)
750 * AHB3LPENR OSPI1LPEN LL_AHB3_GRP1_EnableClockSleep\n (*)
751 * AHB3LPENR OSPI2LPEN LL_AHB3_GRP1_EnableClockSleep\n (*)
752 * AHB3LPENR IOMNGRLPEN LL_AHB3_GRP1_EnableClockSleep\n (*)
753 * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_EnableClockSleep\n (*)
754 * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_EnableClockSleep\n (*)
755 * AHB3LPENR GFXMMULPEN LL_AHB3_GRP1_EnableClockSleep\n (*)
756 * AHB3LPENR SDMMC1LPEN LL_AHB3_GRP1_EnableClockSleep\n
757 * AHB3LPENR FLASHLPEN LL_AHB3_GRP1_EnableClockSleep\n
758 * AHB3LPENR DTCM1LPEN LL_AHB3_GRP1_EnableClockSleep\n
759 * AHB3LPENR DTCM2LPEN LL_AHB3_GRP1_EnableClockSleep\n
760 * AHB3LPENR ITCMLPEN LL_AHB3_GRP1_EnableClockSleep\n
761 * AHB3LPENR AXISRAMLPEN LL_AHB3_GRP1_EnableClockSleep
762 * @param Periphs This parameter can be a combination of the following values:
763 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
764 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
765 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
766 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
767 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
768 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
769 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
770 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
771 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
772 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
773 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
774 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
775 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
776 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
777 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
778 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
779 *
780 * (*) value not defined in all devices.
781 * @retval None
782 */
783 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
784 {
785 __IO uint32_t tmpreg;
786 SET_BIT(RCC->AHB3LPENR, Periphs);
787 /* Delay after an RCC peripheral clock enabling */
788 tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);
789 (void)tmpreg;
790 }
791
792 /**
793 * @brief Disable AHB3 peripherals clock during Low Power (Sleep) mode.
794 * @rmtoll AHB3LPENR MDMALPEN LL_AHB3_GRP1_DisableClockSleep\n
795 * AHB3LPENR DMA2DLPEN LL_AHB3_GRP1_DisableClockSleep\n
796 * AHB3LPENR JPGDECLPEN LL_AHB3_GRP1_DisableClockSleep\n
797 * AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockSleep\n
798 * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockSleep\n
799 * AHB3LPENR OSPI1LPEN LL_AHB3_GRP1_DisableClockSleep\n (*)
800 * AHB3LPENR OSPI2LPEN LL_AHB3_GRP1_DisableClockSleep\n (*)
801 * AHB3LPENR IOMNGRLPEN LL_AHB3_GRP1_DisableClockSleep\n (*)
802 * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_DisableClockSleep\n (*)
803 * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_DisableClockSleep\n (*)
804 * AHB3LPENR GFXMMULPEN LL_AHB3_GRP1_DisableClockSleep\n (*)
805 * AHB3LPENR SDMMC1LPEN LL_AHB3_GRP1_DisableClockSleep\n
806 * AHB3LPENR FLASHLPEN LL_AHB3_GRP1_DisableClockSleep\n
807 * AHB3LPENR DTCM1LPEN LL_AHB3_GRP1_DisableClockSleep\n
808 * AHB3LPENR DTCM2LPEN LL_AHB3_GRP1_DisableClockSleep\n
809 * AHB3LPENR ITCMLPEN LL_AHB3_GRP1_DisableClockSleep\n
810 * AHB3LPENR AXISRAMLPEN LL_AHB3_GRP1_DisableClockSleep
811 * @param Periphs This parameter can be a combination of the following values:
812 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
813 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
814 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
815 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
816 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
817 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
818 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
819 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
820 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
821 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
822 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
823 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
824 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
825 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
826 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
827 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
828 *
829 * (*) value not defined in all devices.
830 * @retval None
831 */
832 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
833 {
834 CLEAR_BIT(RCC->AHB3LPENR, Periphs);
835 }
836
837 /**
838 * @}
839 */
840
841 /** @defgroup BUS_LL_EF_AHB1 AHB1
842 * @{
843 */
844
845 /**
846 * @brief Enable AHB1 peripherals clock.
847 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
848 * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
849 * AHB1ENR ADC12EN LL_AHB1_GRP1_EnableClock\n
850 * AHB1ENR ARTEN LL_AHB1_GRP1_EnableClock\n
851 * AHB1ENR ETH1MACEN LL_AHB1_GRP1_EnableClock\n (*)
852 * AHB1ENR ETH1TXEN LL_AHB1_GRP1_EnableClock\n (*)
853 * AHB1ENR ETH1RXEN LL_AHB1_GRP1_EnableClock\n (*)
854 * AHB1ENR USB1OTGHSEN LL_AHB1_GRP1_EnableClock\n
855 * AHB1ENR USB1OTGHSULPIEN LL_AHB1_GRP1_EnableClock\n
856 * AHB1ENR USB2OTGHSEN LL_AHB1_GRP1_EnableClock\n (*)
857 * AHB1ENR USB2OTGHSULPIEN LL_AHB1_GRP1_EnableClock (*)
858 * @param Periphs This parameter can be a combination of the following values:
859 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
860 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
861 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
862 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
863 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
864 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
865 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
866 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
867 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
868 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
869 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
870 *
871 * (*) value not defined in all devices.
872 * @retval None
873 */
874 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
875 {
876 __IO uint32_t tmpreg;
877 SET_BIT(RCC->AHB1ENR, Periphs);
878 /* Delay after an RCC peripheral clock enabling */
879 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
880 (void)tmpreg;
881 }
882
883 /**
884 * @brief Check if AHB1 peripheral clock is enabled or not
885 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
886 * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
887 * AHB1ENR ADC12EN LL_AHB1_GRP1_IsEnabledClock\n
888 * AHB1ENR ARTEN LL_AHB1_GRP1_IsEnabledClock\n (*)
889 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n (*)
890 * AHB1ENR ETH1MACEN LL_AHB1_GRP1_IsEnabledClock\n (*)
891 * AHB1ENR ETH1TXEN LL_AHB1_GRP1_IsEnabledClock\n (*)
892 * AHB1ENR ETH1RXEN LL_AHB1_GRP1_IsEnabledClock\n (*)
893 * AHB1ENR USB1OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n
894 * AHB1ENR USB1OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock\n
895 * AHB1ENR USB2OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n (*)
896 * AHB1ENR USB2OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock (*)
897 * @param Periphs This parameter can be a combination of the following values:
898 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
899 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
900 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
901 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
902 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
903 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
904 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
905 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
906 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
907 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
908 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
909 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
910 *
911 * (*) value not defined in all devices.
912 * @retval uint32_t
913 */
914 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
915 {
916 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs)?1U:0U);
917 }
918
919 /**
920 * @brief Disable AHB1 peripherals clock.
921 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
922 * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
923 * AHB1ENR ADC12EN LL_AHB1_GRP1_DisableClock\n
924 * AHB1ENR ARTEN LL_AHB1_GRP1_DisableClock\n (*)
925 * AHB1ENR ETH1MACEN LL_AHB1_GRP1_DisableClock\n (*)
926 * AHB1ENR ETH1TXEN LL_AHB1_GRP1_DisableClock\n (*)
927 * AHB1ENR ETH1RXEN LL_AHB1_GRP1_DisableClock\n (*)
928 * AHB1ENR USB1OTGHSEN LL_AHB1_GRP1_DisableClock\n
929 * AHB1ENR USB1OTGHSULPIEN LL_AHB1_GRP1_DisableClock\n
930 * AHB1ENR USB2OTGHSEN LL_AHB1_GRP1_DisableClock\n (*)
931 * AHB1ENR USB2OTGHSULPIEN LL_AHB1_GRP1_DisableClock (*)
932 * @param Periphs This parameter can be a combination of the following values:
933 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
934 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
935 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
936 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
937 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
938 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
939 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
940 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
941 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
942 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
943 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
944 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
945 *
946 * (*) value not defined in all devices.
947 * @retval None
948 */
949 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
950 {
951 CLEAR_BIT(RCC->AHB1ENR, Periphs);
952 }
953
954 /**
955 * @brief Force AHB1 peripherals reset.
956 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
957 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
958 * AHB1RSTR ADC12RST LL_AHB1_GRP1_ForceReset\n
959 * AHB1RSTR ARTRST LL_AHB1_GRP1_ForceReset\n (*)
960 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n (*)
961 * AHB1RSTR ETH1MACRST LL_AHB1_GRP1_ForceReset\n (*)
962 * AHB1RSTR USB1OTGHSRST LL_AHB1_GRP1_ForceReset\n
963 * AHB1RSTR USB2OTGHSRST LL_AHB1_GRP1_ForceReset (*)
964 * @param Periphs This parameter can be a combination of the following values:
965 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
966 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
967 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
968 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
969 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
970 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
971 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
972 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
973 *
974 * (*) value not defined in all devices.
975 * @retval None
976 */
977 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
978 {
979 SET_BIT(RCC->AHB1RSTR, Periphs);
980 }
981
982 /**
983 * @brief Release AHB1 peripherals reset.
984 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
985 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
986 * AHB1RSTR ADC12RST LL_AHB1_GRP1_ReleaseReset\n
987 * AHB1RSTR ARTRST LL_AHB1_GRP1_ReleaseReset\n (*)
988 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n (*)
989 * AHB1RSTR ETH1MACRST LL_AHB1_GRP1_ReleaseReset\n (*)
990 * AHB1RSTR USB1OTGHSRST LL_AHB1_GRP1_ReleaseReset\n
991 * AHB1RSTR USB2OTGHSRST LL_AHB1_GRP1_ReleaseReset (*)
992 * @param Periphs This parameter can be a combination of the following values:
993 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
994 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
995 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
996 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
997 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
998 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
999 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
1000 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
1001 *
1002 * (*) value not defined in all devices.
1003 * @retval None
1004 */
1005 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
1006 {
1007 CLEAR_BIT(RCC->AHB1RSTR, Periphs);
1008 }
1009
1010 /**
1011 * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode.
1012 * @rmtoll AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockSleep\n
1013 * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockSleep\n
1014 * AHB1LPENR ADC12LPEN LL_AHB1_GRP1_EnableClockSleep\n
1015 * AHB1LPENR ARTLPEN LL_AHB1_GRP1_EnableClockSleep\n (*)
1016 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockSleep\n (*)
1017 * AHB1LPENR ETH1MACLPEN LL_AHB1_GRP1_EnableClockSleep\n (*)
1018 * AHB1LPENR ETH1TXLPEN LL_AHB1_GRP1_EnableClockSleep\n (*)
1019 * AHB1LPENR ETH1RXLPEN LL_AHB1_GRP1_EnableClockSleep\n
1020 * AHB1LPENR USB1OTGHSLPEN LL_AHB1_GRP1_EnableClockSleep\n
1021 * AHB1LPENR USB1OTGHSULPILPEN LL_AHB1_GRP1_EnableClockSleep\n
1022 * AHB1LPENR USB2OTGHSLPEN LL_AHB1_GRP1_EnableClockSleep\n (*)
1023 * AHB1LPENR USB2OTGHSULPILPEN LL_AHB1_GRP1_EnableClockSleep (*)
1024 * @param Periphs This parameter can be a combination of the following values:
1025 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
1026 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
1027 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
1028 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
1029 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
1030 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
1031 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
1032 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
1033 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
1034 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
1035 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
1036 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
1037 *
1038 * (*) value not defined in all devices.
1039 * @retval None
1040 */
1041 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
1042 {
1043 __IO uint32_t tmpreg;
1044 SET_BIT(RCC->AHB1LPENR, Periphs);
1045 /* Delay after an RCC peripheral clock enabling */
1046 tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
1047 (void)tmpreg;
1048 }
1049
1050 /**
1051 * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode.
1052 * @rmtoll AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockSleep\n
1053 * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockSleep\n
1054 * AHB1LPENR ADC12LPEN LL_AHB1_GRP1_DisableClockSleep\n
1055 * AHB1LPENR ARTLPEN LL_AHB1_GRP1_DisableClockSleep\n (*)
1056 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockSleep\n (*)
1057 * AHB1LPENR ETH1MACLPEN LL_AHB1_GRP1_DisableClockSleep\n (*)
1058 * AHB1LPENR ETH1TXLPEN LL_AHB1_GRP1_DisableClockSleep\n (*)
1059 * AHB1LPENR ETH1RXLPEN LL_AHB1_GRP1_DisableClockSleep\n (*)
1060 * AHB1LPENR USB1OTGHSLPEN LL_AHB1_GRP1_DisableClockSleep\n
1061 * AHB1LPENR USB1OTGHSULPILPEN LL_AHB1_GRP1_DisableClockSleep\n
1062 * AHB1LPENR USB2OTGHSLPEN LL_AHB1_GRP1_DisableClockSleep\n (*)
1063 * AHB1LPENR USB2OTGHSULPILPEN LL_AHB1_GRP1_DisableClockSleep (*)
1064 * @param Periphs This parameter can be a combination of the following values:
1065 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
1066 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
1067 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
1068 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
1069 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
1070 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
1071 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
1072 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
1073 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
1074 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
1075 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
1076 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
1077 *
1078 * (*) value not defined in all devices.
1079 * @retval None
1080 */
1081 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
1082 {
1083 CLEAR_BIT(RCC->AHB1LPENR, Periphs);
1084 }
1085
1086 /**
1087 * @}
1088 */
1089
1090 /** @defgroup BUS_LL_EF_AHB2 AHB2
1091 * @{
1092 */
1093
1094 /**
1095 * @brief Enable AHB2 peripherals clock.
1096 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n
1097 * AHB2ENR HSEMEN LL_AHB2_GRP1_EnableClock\n (*)
1098 * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n (*)
1099 * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n (*)
1100 * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n
1101 * AHB2ENR SDMMC2EN LL_AHB2_GRP1_EnableClock\n
1102 * AHB2ENR BDMA1EN LL_AHB2_GRP1_EnableClock\n (*)
1103 * AHB2ENR FMACEN LL_AHB2_GRP1_EnableClock\n
1104 * AHB2ENR CORDICEN LL_AHB2_GRP1_EnableClock\n
1105 * AHB2ENR D2SRAM1EN LL_AHB2_GRP1_EnableClock\n
1106 * AHB2ENR D2SRAM2EN LL_AHB2_GRP1_EnableClock\n
1107 * AHB2ENR D2SRAM3EN LL_AHB2_GRP1_EnableClock (*)
1108 * @param Periphs This parameter can be a combination of the following values:
1109 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
1110 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
1111 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
1112 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
1113 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1114 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
1115 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
1116 * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*)
1117 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
1118 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
1119 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
1120 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
1121 *
1122 * (*) value not defined in all devices.
1123 * @retval None
1124 */
1125 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
1126 {
1127 __IO uint32_t tmpreg;
1128 SET_BIT(RCC->AHB2ENR, Periphs);
1129 /* Delay after an RCC peripheral clock enabling */
1130 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
1131 (void)tmpreg;
1132 }
1133
1134 /**
1135 * @brief Check if AHB2 peripheral clock is enabled or not
1136 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n
1137 * AHB2ENR HSEMEN LL_AHB2_GRP1_IsEnabledClock\n (*)
1138 * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n (*)
1139 * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n (*)
1140 * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n
1141 * AHB2ENR SDMMC2EN LL_AHB2_GRP1_IsEnabledClock\n
1142 * AHB2ENR BDMA1EN LL_AHB2_GRP1_IsEnabledClock\n (*)
1143 * AHB2ENR FMACEN LL_AHB2_GRP1_IsEnabledClock\n
1144 * AHB2ENR CORDICEN LL_AHB2_GRP1_IsEnabledClock\n
1145 * AHB2ENR D2SRAM1EN LL_AHB2_GRP1_IsEnabledClock\n
1146 * AHB2ENR D2SRAM2EN LL_AHB2_GRP1_IsEnabledClock\n
1147 * AHB2ENR D2SRAM3EN LL_AHB2_GRP1_IsEnabledClock (*)
1148 * @param Periphs This parameter can be a combination of the following values:
1149 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
1150 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
1151 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
1152 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
1153 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1154 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
1155 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
1156 * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*)
1157 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
1158 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
1159 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
1160 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
1161 *
1162 * (*) value not defined in all devices.
1163 * @retval uint32_t
1164 */
1165 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
1166 {
1167 return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs)?1U:0U);
1168 }
1169
1170 /**
1171 * @brief Disable AHB2 peripherals clock.
1172 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n
1173 * AHB2ENR HSEMEN LL_AHB2_GRP1_DisableClock\n (*)
1174 * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n (*)
1175 * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n (*)
1176 * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n
1177 * AHB2ENR SDMMC2EN LL_AHB2_GRP1_DisableClock\n
1178 * AHB2ENR BDMA1EN LL_AHB2_GRP1_DisableClock\n (*)
1179 * AHB2ENR FMACEN LL_AHB2_GRP1_DisableClock\n
1180 * AHB2ENR CORDICEN LL_AHB2_GRP1_DisableClock\n
1181 * AHB2ENR D2SRAM1EN LL_AHB2_GRP1_DisableClock\n
1182 * AHB2ENR D2SRAM2EN LL_AHB2_GRP1_DisableClock\n
1183 * AHB2ENR D2SRAM3EN LL_AHB2_GRP1_DisableClock (*)
1184 * @param Periphs This parameter can be a combination of the following values:
1185 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
1186 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
1187 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
1188 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
1189 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1190 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
1191 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
1192 * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*)
1193 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
1194 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
1195 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
1196 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
1197 *
1198 * (*) value not defined in all devices.
1199 * @retval None
1200 */
1201 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
1202 {
1203 CLEAR_BIT(RCC->AHB2ENR, Periphs);
1204 }
1205
1206 /**
1207 * @brief Force AHB2 peripherals reset.
1208 * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n
1209 * AHB2RSTR HSEMRST LL_AHB2_GRP1_ForceReset\n (*)
1210 * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n (*)
1211 * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n (*)
1212 * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n
1213 * AHB2RSTR SDMMC2RST LL_AHB2_GRP1_ForceReset\n
1214 * AHB2RSTR BDMA1RST LL_AHB2_GRP1_ForceReset (*)
1215 * AHB2RSTR FMACRST LL_AHB2_GRP1_ForceReset\n
1216 * AHB2RSTR CORDICRST LL_AHB2_GRP1_ForceReset
1217 * @param Periphs This parameter can be a combination of the following values:
1218 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
1219 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
1220 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
1221 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
1222 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1223 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
1224 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
1225 * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*)
1226 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
1227 *
1228 * (*) value not defined in all devices.
1229 * @retval None
1230 */
1231 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
1232 {
1233 SET_BIT(RCC->AHB2RSTR, Periphs);
1234 }
1235
1236 /**
1237 * @brief Release AHB2 peripherals reset.
1238 * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n
1239 * AHB2RSTR HSEMRST LL_AHB2_GRP1_ReleaseReset\n (*)
1240 * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n (*)
1241 * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n (*)
1242 * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n
1243 * AHB2RSTR SDMMC2RST LL_AHB2_GRP1_ReleaseReset\n
1244 * AHB2RSTR BDMA1RST LL_AHB2_GRP1_ReleaseReset (*)
1245 * AHB2RSTR FMACRST LL_AHB2_GRP1_ReleaseReset\n
1246 * AHB2RSTR CORDICRST LL_AHB2_GRP1_ReleaseReset
1247 * @param Periphs This parameter can be a combination of the following values:
1248 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
1249 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
1250 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
1251 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
1252 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1253 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
1254 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
1255 * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*)
1256 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
1257 *
1258 * (*) value not defined in all devices.
1259 * @retval None
1260 */
1261 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
1262 {
1263 CLEAR_BIT(RCC->AHB2RSTR, Periphs);
1264 }
1265
1266 /**
1267 * @brief Enable AHB2 peripherals clock during Low Power (Sleep) mode.
1268 * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockSleep\n
1269 * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockSleep\n (*)
1270 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockSleep\n (*)
1271 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockSleep\n
1272 * AHB2LPENR SDMMC2LPEN LL_AHB2_GRP1_EnableClockSleep\n
1273 * AHB2LPENR BDMA1LPEN LL_AHB2_GRP1_EnableClockSleep\n (*)
1274 * AHB2LPENR FMACLPEN LL_AHB2_GRP1_EnableClockSleep\n
1275 * AHB2LPENR CORDICLPEN LL_AHB2_GRP1_EnableClockSleep\n
1276 * AHB2LPENR D2SRAM1LPEN LL_AHB2_GRP1_EnableClockSleep\n
1277 * AHB2LPENR D2SRAM2LPEN LL_AHB2_GRP1_EnableClockSleep\n
1278 * AHB2LPENR D2SRAM3LPEN LL_AHB2_GRP1_EnableClockSleep (*)
1279 * @param Periphs This parameter can be a combination of the following values:
1280 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
1281 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
1282 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
1283 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1284 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
1285 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
1286 * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*)
1287 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
1288 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
1289 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
1290 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
1291 *
1292 * (*) value not defined in all devices.
1293 * @retval None
1294 */
1295 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
1296 {
1297 __IO uint32_t tmpreg;
1298 SET_BIT(RCC->AHB2LPENR, Periphs);
1299 /* Delay after an RCC peripheral clock enabling */
1300 tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
1301 (void)tmpreg;
1302 }
1303
1304 /**
1305 * @brief Disable AHB2 peripherals clock during Low Power (Sleep) mode.
1306 * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockSleep\n
1307 * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockSleep\n (*)
1308 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockSleep\n (*)
1309 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockSleep\n
1310 * AHB2LPENR SDMMC2LPEN LL_AHB2_GRP1_DisableClockSleep\n
1311 * AHB2LPENR BDMA1LPEN LL_AHB2_GRP1_DisableClockSleep\n (*)
1312 * AHB2LPENR D2SRAM1LPEN LL_AHB2_GRP1_DisableClockSleep\n
1313 * AHB2LPENR D2SRAM2LPEN LL_AHB2_GRP1_DisableClockSleep\n
1314 * AHB2LPENR D2SRAM3LPEN LL_AHB2_GRP1_DisableClockSleep (*)
1315 * @param Periphs This parameter can be a combination of the following values:
1316 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
1317 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
1318 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
1319 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1320 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
1321 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
1322 * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*)
1323 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*)
1324 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
1325 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
1326 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
1327 *
1328 * (*) value not defined in all devices.
1329 * @retval None
1330 */
1331 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
1332 {
1333 CLEAR_BIT(RCC->AHB2LPENR, Periphs);
1334 }
1335
1336 /**
1337 * @}
1338 */
1339
1340 /** @defgroup BUS_LL_EF_AHB4 AHB4
1341 * @{
1342 */
1343
1344 /**
1345 * @brief Enable AHB4 peripherals clock.
1346 * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_EnableClock\n
1347 * AHB4ENR GPIOBEN LL_AHB4_GRP1_EnableClock\n
1348 * AHB4ENR GPIOCEN LL_AHB4_GRP1_EnableClock\n
1349 * AHB4ENR GPIODEN LL_AHB4_GRP1_EnableClock\n
1350 * AHB4ENR GPIOEEN LL_AHB4_GRP1_EnableClock\n
1351 * AHB4ENR GPIOFEN LL_AHB4_GRP1_EnableClock\n
1352 * AHB4ENR GPIOGEN LL_AHB4_GRP1_EnableClock\n
1353 * AHB4ENR GPIOHEN LL_AHB4_GRP1_EnableClock\n
1354 * AHB4ENR GPIOIEN LL_AHB4_GRP1_EnableClock\n (*)
1355 * AHB4ENR GPIOJEN LL_AHB4_GRP1_EnableClock\n
1356 * AHB4ENR GPIOKEN LL_AHB4_GRP1_EnableClock\n
1357 * AHB4ENR CRCEN LL_AHB4_GRP1_EnableClock\n (*)
1358 * AHB4ENR BDMAEN LL_AHB4_GRP1_EnableClock\n
1359 * AHB4ENR ADC3EN LL_AHB4_GRP1_EnableClock\n (*)
1360 * AHB4ENR HSEMEN LL_AHB4_GRP1_EnableClock\n (*)
1361 * AHB4ENR BKPRAMEN LL_AHB4_GRP1_EnableClock\n
1362 * AHB4ENR SRAM4EN LL_AHB4_GRP1_EnableClock
1363 * @param Periphs This parameter can be a combination of the following values:
1364 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
1365 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
1366 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
1367 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
1368 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
1369 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
1370 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1371 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1372 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
1373 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
1374 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
1375 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
1376 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
1377 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
1378 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
1379 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
1380 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
1381 *
1382 * (*) value not defined in all devices.
1383 * @retval None
1384 */
1385 __STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs)
1386 {
1387 __IO uint32_t tmpreg;
1388 SET_BIT(RCC->AHB4ENR, Periphs);
1389 /* Delay after an RCC peripheral clock enabling */
1390 tmpreg = READ_BIT(RCC->AHB4ENR, Periphs);
1391 (void)tmpreg;
1392 }
1393
1394 /**
1395 * @brief Check if AHB4 peripheral clock is enabled or not
1396 * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_IsEnabledClock\n
1397 * AHB4ENR GPIOBEN LL_AHB4_GRP1_IsEnabledClock\n
1398 * AHB4ENR GPIOCEN LL_AHB4_GRP1_IsEnabledClock\n
1399 * AHB4ENR GPIODEN LL_AHB4_GRP1_IsEnabledClock\n
1400 * AHB4ENR GPIOEEN LL_AHB4_GRP1_IsEnabledClock\n
1401 * AHB4ENR GPIOFEN LL_AHB4_GRP1_IsEnabledClock\n
1402 * AHB4ENR GPIOGEN LL_AHB4_GRP1_IsEnabledClock\n
1403 * AHB4ENR GPIOHEN LL_AHB4_GRP1_IsEnabledClock\n
1404 * AHB4ENR GPIOIEN LL_AHB4_GRP1_IsEnabledClock\n (*)
1405 * AHB4ENR GPIOJEN LL_AHB4_GRP1_IsEnabledClock\n
1406 * AHB4ENR GPIOKEN LL_AHB4_GRP1_IsEnabledClock\n
1407 * AHB4ENR CRCEN LL_AHB4_GRP1_IsEnabledClock\n (*)
1408 * AHB4ENR BDMAEN LL_AHB4_GRP1_IsEnabledClock\n
1409 * AHB4ENR ADC3EN LL_AHB4_GRP1_IsEnabledClock\n (*)
1410 * AHB4ENR HSEMEN LL_AHB4_GRP1_IsEnabledClock\n (*)
1411 * AHB4ENR BKPRAMEN LL_AHB4_GRP1_IsEnabledClock\n
1412 * AHB4ENR SRAM4EN LL_AHB4_GRP1_IsEnabledClock
1413 * @param Periphs This parameter can be a combination of the following values:
1414 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
1415 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
1416 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
1417 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
1418 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
1419 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
1420 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1421 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1422 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
1423 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
1424 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
1425 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
1426 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
1427 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
1428 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
1429 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
1430 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
1431 *
1432 * (*) value not defined in all devices.
1433 * @retval uint32_t
1434 */
1435 __STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
1436 {
1437 return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs)?1U:0U);
1438 }
1439
1440 /**
1441 * @brief Disable AHB4 peripherals clock.
1442 * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_DisableClock\n
1443 * AHB4ENR GPIOBEN LL_AHB4_GRP1_DisableClock\n
1444 * AHB4ENR GPIOCEN LL_AHB4_GRP1_DisableClock\n
1445 * AHB4ENR GPIODEN LL_AHB4_GRP1_DisableClock\n
1446 * AHB4ENR GPIOEEN LL_AHB4_GRP1_DisableClock\n
1447 * AHB4ENR GPIOFEN LL_AHB4_GRP1_DisableClock\n
1448 * AHB4ENR GPIOGEN LL_AHB4_GRP1_DisableClock\n
1449 * AHB4ENR GPIOHEN LL_AHB4_GRP1_DisableClock\n
1450 * AHB4ENR GPIOIEN LL_AHB4_GRP1_DisableClock\n (*)
1451 * AHB4ENR GPIOJEN LL_AHB4_GRP1_DisableClock\n
1452 * AHB4ENR GPIOKEN LL_AHB4_GRP1_DisableClock\n
1453 * AHB4ENR CRCEN LL_AHB4_GRP1_DisableClock\n (*)
1454 * AHB4ENR BDMAEN LL_AHB4_GRP1_DisableClock\n
1455 * AHB4ENR ADC3EN LL_AHB4_GRP1_DisableClock\n (*)
1456 * AHB4ENR HSEMEN LL_AHB4_GRP1_DisableClock\n (*)
1457 * AHB4ENR BKPRAMEN LL_AHB4_GRP1_DisableClock\n
1458 * AHB4ENR SRAM4EN LL_AHB4_GRP1_DisableClock
1459 * @param Periphs This parameter can be a combination of the following values:
1460 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
1461 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
1462 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
1463 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
1464 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
1465 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
1466 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1467 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1468 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
1469 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
1470 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
1471 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
1472 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
1473 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
1474 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
1475 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
1476 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
1477 *
1478 * (*) value not defined in all devices.
1479 * @retval None
1480 */
1481 __STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs)
1482 {
1483 CLEAR_BIT(RCC->AHB4ENR, Periphs);
1484 }
1485
1486 /**
1487 * @brief Force AHB4 peripherals reset.
1488 * @rmtoll AHB4RSTR GPIOARST LL_AHB4_GRP1_ForceReset\n
1489 * AHB4RSTR GPIOBRST LL_AHB4_GRP1_ForceReset\n
1490 * AHB4RSTR GPIOCRST LL_AHB4_GRP1_ForceReset\n
1491 * AHB4RSTR GPIODRST LL_AHB4_GRP1_ForceReset\n
1492 * AHB4RSTR GPIOERST LL_AHB4_GRP1_ForceReset\n
1493 * AHB4RSTR GPIOFRST LL_AHB4_GRP1_ForceReset\n
1494 * AHB4RSTR GPIOGRST LL_AHB4_GRP1_ForceReset\n
1495 * AHB4RSTR GPIOHRST LL_AHB4_GRP1_ForceReset\n
1496 * AHB4RSTR GPIOIRST LL_AHB4_GRP1_ForceReset\n (*)
1497 * AHB4RSTR GPIOJRST LL_AHB4_GRP1_ForceReset\n
1498 * AHB4RSTR GPIOKRST LL_AHB4_GRP1_ForceReset\n
1499 * AHB4RSTR CRCRST LL_AHB4_GRP1_ForceReset\n (*)
1500 * AHB4RSTR BDMARST LL_AHB4_GRP1_ForceReset\n
1501 * AHB4RSTR ADC3RST LL_AHB4_GRP1_ForceReset\n (*)
1502 * AHB4RSTR HSEMRST LL_AHB4_GRP1_ForceReset (*)
1503 * @param Periphs This parameter can be a combination of the following values:
1504 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
1505 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
1506 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
1507 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
1508 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
1509 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
1510 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1511 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1512 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
1513 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
1514 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
1515 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
1516 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
1517 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
1518 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
1519 *
1520 * (*) value not defined in all devices.
1521 * @retval None
1522 */
1523 __STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs)
1524 {
1525 SET_BIT(RCC->AHB4RSTR, Periphs);
1526 }
1527
1528 /**
1529 * @brief Release AHB4 peripherals reset.
1530 * @rmtoll AHB4RSTR GPIOARST LL_AHB4_GRP1_ReleaseReset\n
1531 * AHB4RSTR GPIOBRST LL_AHB4_GRP1_ReleaseReset\n
1532 * AHB4RSTR GPIOCRST LL_AHB4_GRP1_ReleaseReset\n
1533 * AHB4RSTR GPIODRST LL_AHB4_GRP1_ReleaseReset\n
1534 * AHB4RSTR GPIOERST LL_AHB4_GRP1_ReleaseReset\n
1535 * AHB4RSTR GPIOFRST LL_AHB4_GRP1_ReleaseReset\n
1536 * AHB4RSTR GPIOGRST LL_AHB4_GRP1_ReleaseReset\n
1537 * AHB4RSTR GPIOHRST LL_AHB4_GRP1_ReleaseReset\n
1538 * AHB4RSTR GPIOIRST LL_AHB4_GRP1_ReleaseReset\n (*)
1539 * AHB4RSTR GPIOJRST LL_AHB4_GRP1_ReleaseReset\n
1540 * AHB4RSTR GPIOKRST LL_AHB4_GRP1_ReleaseReset\n
1541 * AHB4RSTR CRCRST LL_AHB4_GRP1_ReleaseReset\n (*)
1542 * AHB4RSTR BDMARST LL_AHB4_GRP1_ReleaseReset\n
1543 * AHB4RSTR ADC3RST LL_AHB4_GRP1_ReleaseReset\n (*)
1544 * AHB4RSTR HSEMRST LL_AHB4_GRP1_ReleaseReset (*)
1545 * @param Periphs This parameter can be a combination of the following values:
1546 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
1547 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
1548 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
1549 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
1550 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
1551 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
1552 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1553 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1554 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
1555 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
1556 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
1557 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
1558 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
1559 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
1560 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
1561 *
1562 * (*) value not defined in all devices.
1563 * @retval None
1564 */
1565 __STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs)
1566 {
1567 CLEAR_BIT(RCC->AHB4RSTR, Periphs);
1568 }
1569
1570 /**
1571 * @brief Enable AHB4 peripherals clock during Low Power (Sleep) mode.
1572 * @rmtoll AHB4LPENR GPIOALPEN LL_AHB4_GRP1_EnableClockSleep\n
1573 * AHB4LPENR GPIOBLPEN LL_AHB4_GRP1_EnableClockSleep\n
1574 * AHB4LPENR GPIOCLPEN LL_AHB4_GRP1_EnableClockSleep\n
1575 * AHB4LPENR GPIODLPEN LL_AHB4_GRP1_EnableClockSleep\n
1576 * AHB4LPENR GPIOELPEN LL_AHB4_GRP1_EnableClockSleep\n
1577 * AHB4LPENR GPIOFLPEN LL_AHB4_GRP1_EnableClockSleep\n
1578 * AHB4LPENR GPIOGLPEN LL_AHB4_GRP1_EnableClockSleep\n
1579 * AHB4LPENR GPIOHLPEN LL_AHB4_GRP1_EnableClockSleep\n
1580 * AHB4LPENR GPIOILPEN LL_AHB4_GRP1_EnableClockSleep\n (*)
1581 * AHB4LPENR GPIOJLPEN LL_AHB4_GRP1_EnableClockSleep\n
1582 * AHB4LPENR GPIOKLPEN LL_AHB4_GRP1_EnableClockSleep\n
1583 * AHB4LPENR CRCLPEN LL_AHB4_GRP1_EnableClockSleep\n (*)
1584 * AHB4LPENR BDMALPEN LL_AHB4_GRP1_EnableClockSleep\n
1585 * AHB4LPENR ADC3LPEN LL_AHB4_GRP1_EnableClockSleep\n (*)
1586 * AHB4LPENR BKPRAMLPEN LL_AHB4_GRP1_EnableClockSleep\n
1587 * AHB4LPENR SRAM4LPEN LL_AHB4_GRP1_EnableClockSleep
1588 * @param Periphs This parameter can be a combination of the following values:
1589 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
1590 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
1591 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
1592 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
1593 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
1594 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
1595 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1596 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1597 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
1598 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
1599 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
1600 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
1601 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
1602 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
1603 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
1604 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
1605 * @retval None
1606 */
1607 __STATIC_INLINE void LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)
1608 {
1609 __IO uint32_t tmpreg;
1610 SET_BIT(RCC->AHB4LPENR, Periphs);
1611 /* Delay after an RCC peripheral clock enabling */
1612 tmpreg = READ_BIT(RCC->AHB4LPENR, Periphs);
1613 (void)tmpreg;
1614 }
1615
1616 /**
1617 * @brief Disable AHB4 peripherals clock during Low Power (Sleep) mode.
1618 * @rmtoll AHB4LPENR GPIOALPEN LL_AHB4_GRP1_DisableClockSleep\n
1619 * AHB4LPENR GPIOBLPEN LL_AHB4_GRP1_DisableClockSleep\n
1620 * AHB4LPENR GPIOCLPEN LL_AHB4_GRP1_DisableClockSleep\n
1621 * AHB4LPENR GPIODLPEN LL_AHB4_GRP1_DisableClockSleep\n
1622 * AHB4LPENR GPIOELPEN LL_AHB4_GRP1_DisableClockSleep\n
1623 * AHB4LPENR GPIOFLPEN LL_AHB4_GRP1_DisableClockSleep\n
1624 * AHB4LPENR GPIOGLPEN LL_AHB4_GRP1_DisableClockSleep\n
1625 * AHB4LPENR GPIOHLPEN LL_AHB4_GRP1_DisableClockSleep\n
1626 * AHB4LPENR GPIOILPEN LL_AHB4_GRP1_DisableClockSleep\n (*)
1627 * AHB4LPENR GPIOJLPEN LL_AHB4_GRP1_DisableClockSleep\n
1628 * AHB4LPENR GPIOKLPEN LL_AHB4_GRP1_DisableClockSleep\n
1629 * AHB4LPENR CRCLPEN LL_AHB4_GRP1_DisableClockSleep\n (*)
1630 * AHB4LPENR BDMALPEN LL_AHB4_GRP1_DisableClockSleep\n
1631 * AHB4LPENR ADC3LPEN LL_AHB4_GRP1_DisableClockSleep\n (*)
1632 * AHB4LPENR BKPRAMLPEN LL_AHB4_GRP1_DisableClockSleep\n
1633 * AHB4LPENR SRAM4LPEN LL_AHB4_GRP1_DisableClockSleep
1634 * @param Periphs This parameter can be a combination of the following values:
1635 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
1636 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
1637 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
1638 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
1639 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
1640 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
1641 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1642 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1643 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
1644 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
1645 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
1646 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
1647 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
1648 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
1649 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
1650 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
1651 * @retval None
1652 */
1653 __STATIC_INLINE void LL_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)
1654 {
1655 CLEAR_BIT(RCC->AHB4LPENR, Periphs);
1656 }
1657
1658 /**
1659 * @}
1660 */
1661
1662 /** @defgroup BUS_LL_EF_APB3 APB3
1663 * @{
1664 */
1665
1666 /**
1667 * @brief Enable APB3 peripherals clock.
1668 * @rmtoll APB3ENR LTDCEN LL_APB3_GRP1_EnableClock\n (*)
1669 * APB3ENR DSIEN LL_APB3_GRP1_EnableClock\n (*)
1670 * APB3ENR WWDG1EN LL_APB3_GRP1_EnableClock
1671 * @param Periphs This parameter can be a combination of the following values:
1672 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
1673 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
1674 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
1675 *
1676 * (*) value not defined in all devices.
1677 * @retval None
1678 */
1679 __STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs)
1680 {
1681 __IO uint32_t tmpreg;
1682 SET_BIT(RCC->APB3ENR, Periphs);
1683 /* Delay after an RCC peripheral clock enabling */
1684 tmpreg = READ_BIT(RCC->APB3ENR, Periphs);
1685 (void)tmpreg;
1686 }
1687
1688 /**
1689 * @brief Check if APB3 peripheral clock is enabled or not
1690 * @rmtoll APB3ENR LTDCEN LL_APB3_GRP1_IsEnabledClock\n (*)
1691 * APB3ENR DSIEN LL_APB3_GRP1_IsEnabledClock\n (*)
1692 * APB3ENR WWDG1EN LL_APB3_GRP1_IsEnabledClock
1693 * @param Periphs This parameter can be a combination of the following values:
1694 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
1695 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
1696 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
1697 *
1698 * (*) value not defined in all devices.
1699 * @retval uint32_t
1700 */
1701 __STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
1702 {
1703 return ((READ_BIT(RCC->APB3ENR, Periphs) == Periphs)?1U:0U);
1704 }
1705
1706 /**
1707 * @brief Disable APB3 peripherals clock.
1708 * @rmtoll APB3ENR LTDCEN LL_APB3_GRP1_DisableClock\n
1709 * APB3ENR DSIEN LL_APB3_GRP1_DisableClock\n
1710 * APB3ENR WWDG1EN LL_APB3_GRP1_DisableClock
1711 * @param Periphs This parameter can be a combination of the following values:
1712 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
1713 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
1714 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
1715 *
1716 * (*) value not defined in all devices.
1717 * @retval None
1718 */
1719 __STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t Periphs)
1720 {
1721 CLEAR_BIT(RCC->APB3ENR, Periphs);
1722 }
1723
1724 /**
1725 * @brief Force APB3 peripherals reset.
1726 * @rmtoll APB3RSTR LTDCRST LL_APB3_GRP1_ForceReset\n (*)
1727 * APB3RSTR DSIRST LL_APB3_GRP1_ForceReset (*)
1728 * @param Periphs This parameter can be a combination of the following values:
1729 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
1730 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
1731 *
1732 * (*) value not defined in all devices.
1733 * @retval None
1734 */
1735 __STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs)
1736 {
1737 SET_BIT(RCC->APB3RSTR, Periphs);
1738 }
1739
1740 /**
1741 * @brief Release APB3 peripherals reset.
1742 * @rmtoll APB3RSTR LTDCRST LL_APB3_GRP1_ReleaseReset\n
1743 * APB3RSTR DSIRST LL_APB3_GRP1_ReleaseReset
1744 * @param Periphs This parameter can be a combination of the following values:
1745 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
1746 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
1747 *
1748 * (*) value not defined in all devices.
1749 * @retval None
1750 */
1751 __STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)
1752 {
1753 CLEAR_BIT(RCC->APB3RSTR, Periphs);
1754 }
1755
1756 /**
1757 * @brief Enable APB3 peripherals clock during Low Power (Sleep) mode.
1758 * @rmtoll APB3LPENR LTDCLPEN LL_APB3_GRP1_EnableClockSleep\n (*)
1759 * APB3LPENR DSILPEN LL_APB3_GRP1_EnableClockSleep\n (*)
1760 * APB3LPENR WWDG1LPEN LL_APB3_GRP1_EnableClockSleep
1761 * @param Periphs This parameter can be a combination of the following values:
1762 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
1763 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
1764 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
1765 *
1766 * (*) value not defined in all devices.
1767 * @retval None
1768 */
1769 __STATIC_INLINE void LL_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
1770 {
1771 __IO uint32_t tmpreg;
1772 SET_BIT(RCC->APB3LPENR, Periphs);
1773 /* Delay after an RCC peripheral clock enabling */
1774 tmpreg = READ_BIT(RCC->APB3LPENR, Periphs);
1775 (void)tmpreg;
1776 }
1777
1778 /**
1779 * @brief Disable APB3 peripherals clock during Low Power (Sleep) mode.
1780 * @rmtoll APB3LPENR LTDCLPEN LL_APB3_GRP1_DisableClockSleep\n (*)
1781 * APB3LPENR DSILPEN LL_APB3_GRP1_DisableClockSleep\n (*)
1782 * APB3LPENR WWDG1LPEN LL_APB3_GRP1_DisableClockSleep
1783 * @param Periphs This parameter can be a combination of the following values:
1784 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
1785 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
1786 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
1787 *
1788 * (*) value not defined in all devices.
1789 * @retval None
1790 */
1791 __STATIC_INLINE void LL_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
1792 {
1793 CLEAR_BIT(RCC->APB3LPENR, Periphs);
1794 }
1795
1796 /**
1797 * @}
1798 */
1799
1800 /** @defgroup BUS_LL_EF_APB1 APB1
1801 * @{
1802 */
1803
1804 /**
1805 * @brief Enable APB1 peripherals clock.
1806 * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_EnableClock\n
1807 * APB1LENR TIM3EN LL_APB1_GRP1_EnableClock\n
1808 * APB1LENR TIM4EN LL_APB1_GRP1_EnableClock\n
1809 * APB1LENR TIM5EN LL_APB1_GRP1_EnableClock\n
1810 * APB1LENR TIM6EN LL_APB1_GRP1_EnableClock\n
1811 * APB1LENR TIM7EN LL_APB1_GRP1_EnableClock\n
1812 * APB1LENR TIM12EN LL_APB1_GRP1_EnableClock\n
1813 * APB1LENR TIM13EN LL_APB1_GRP1_EnableClock\n
1814 * APB1LENR TIM14EN LL_APB1_GRP1_EnableClock\n
1815 * APB1LENR LPTIM1EN LL_APB1_GRP1_EnableClock\n
1816 * APB1LENR WWDG2EN LL_APB1_GRP1_EnableClock\n (*)
1817 * APB1LENR SPI2EN LL_APB1_GRP1_EnableClock\n
1818 * APB1LENR SPI3EN LL_APB1_GRP1_EnableClock\n
1819 * APB1LENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n
1820 * APB1LENR USART2EN LL_APB1_GRP1_EnableClock\n
1821 * APB1LENR USART3EN LL_APB1_GRP1_EnableClock\n
1822 * APB1LENR UART4EN LL_APB1_GRP1_EnableClock\n
1823 * APB1LENR UART5EN LL_APB1_GRP1_EnableClock\n
1824 * APB1LENR I2C1EN LL_APB1_GRP1_EnableClock\n
1825 * APB1LENR I2C2EN LL_APB1_GRP1_EnableClock\n
1826 * APB1LENR I2C3EN LL_APB1_GRP1_EnableClock\n
1827 * APB1LENR I2C5EN LL_APB1_GRP1_EnableClock\n (*)
1828 * APB1LENR CECEN LL_APB1_GRP1_EnableClock\n
1829 * APB1LENR DAC12EN LL_APB1_GRP1_EnableClock\n
1830 * APB1LENR UART7EN LL_APB1_GRP1_EnableClock\n
1831 * APB1LENR UART8EN LL_APB1_GRP1_EnableClock
1832 * @param Periphs This parameter can be a combination of the following values:
1833 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1834 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1835 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1836 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1837 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1838 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1839 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1840 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1841 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1842 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1843 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
1844 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1845 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1846 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
1847 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1848 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1849 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1850 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1851 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1852 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1853 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1854 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
1855 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
1856 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
1857 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1858 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1859 *
1860 * (*) value not defined in all devices.
1861 * @retval None
1862 */
1863 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
1864 {
1865 __IO uint32_t tmpreg;
1866 SET_BIT(RCC->APB1LENR, Periphs);
1867 /* Delay after an RCC peripheral clock enabling */
1868 tmpreg = READ_BIT(RCC->APB1LENR, Periphs);
1869 (void)tmpreg;
1870 }
1871
1872 /**
1873 * @brief Check if APB1 peripheral clock is enabled or not
1874 * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
1875 * APB1LENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
1876 * APB1LENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
1877 * APB1LENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
1878 * APB1LENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
1879 * APB1LENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
1880 * APB1LENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
1881 * APB1LENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
1882 * APB1LENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
1883 * APB1LENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n
1884 * APB1LENR WWDG2EN LL_APB1_GRP1_IsEnabledClock\n (*)
1885 * APB1LENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
1886 * APB1LENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
1887 * APB1LENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n
1888 * APB1LENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
1889 * APB1LENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
1890 * APB1LENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
1891 * APB1LENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
1892 * APB1LENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
1893 * APB1LENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
1894 * APB1LENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n
1895 * APB1LENR I2C5EN LL_APB1_GRP1_IsEnabledClock\n (*)
1896 * APB1LENR CECEN LL_APB1_GRP1_IsEnabledClock\n
1897 * APB1LENR DAC12EN LL_APB1_GRP1_IsEnabledClock\n
1898 * APB1LENR UART7EN LL_APB1_GRP1_IsEnabledClock\n
1899 * APB1LENR UART8EN LL_APB1_GRP1_IsEnabledClock
1900 * @param Periphs This parameter can be a combination of the following values:
1901 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1902 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1903 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1904 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1905 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1906 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1907 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1908 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1909 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1910 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1911 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
1912 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1913 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1914 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
1915 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1916 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1917 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1918 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1919 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1920 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1921 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1922 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
1923 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
1924 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
1925 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1926 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1927 *
1928 * (*) value not defined in all devices.
1929 * @retval uint32_t
1930 */
1931 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
1932 {
1933 return ((READ_BIT(RCC->APB1LENR, Periphs) == Periphs)?1U:0U);
1934 }
1935
1936 /**
1937 * @brief Disable APB1 peripherals clock.
1938 * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_DisableClock\n
1939 * APB1LENR TIM3EN LL_APB1_GRP1_DisableClock\n
1940 * APB1LENR TIM4EN LL_APB1_GRP1_DisableClock\n
1941 * APB1LENR TIM5EN LL_APB1_GRP1_DisableClock\n
1942 * APB1LENR TIM6EN LL_APB1_GRP1_DisableClock\n
1943 * APB1LENR TIM7EN LL_APB1_GRP1_DisableClock\n
1944 * APB1LENR TIM12EN LL_APB1_GRP1_DisableClock\n
1945 * APB1LENR TIM13EN LL_APB1_GRP1_DisableClock\n
1946 * APB1LENR TIM14EN LL_APB1_GRP1_DisableClock\n
1947 * APB1LENR LPTIM1EN LL_APB1_GRP1_DisableClock\n
1948 * APB1LENR WWDG2EN LL_APB1_GRP1_DisableClock\n (*)
1949 * APB1LENR SPI2EN LL_APB1_GRP1_DisableClock\n
1950 * APB1LENR SPI3EN LL_APB1_GRP1_DisableClock\n
1951 * APB1LENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n
1952 * APB1LENR USART2EN LL_APB1_GRP1_DisableClock\n
1953 * APB1LENR USART3EN LL_APB1_GRP1_DisableClock\n
1954 * APB1LENR UART4EN LL_APB1_GRP1_DisableClock\n
1955 * APB1LENR UART5EN LL_APB1_GRP1_DisableClock\n
1956 * APB1LENR I2C1EN LL_APB1_GRP1_DisableClock\n
1957 * APB1LENR I2C2EN LL_APB1_GRP1_DisableClock\n
1958 * APB1LENR I2C3EN LL_APB1_GRP1_DisableClock\n
1959 * APB1LENR I2C5EN LL_APB1_GRP1_DisableClock\n (*)
1960 * APB1LENR CECEN LL_APB1_GRP1_DisableClock\n
1961 * APB1LENR DAC12EN LL_APB1_GRP1_DisableClock\n
1962 * APB1LENR UART7EN LL_APB1_GRP1_DisableClock\n
1963 * APB1LENR UART8EN LL_APB1_GRP1_DisableClock
1964 * @param Periphs This parameter can be a combination of the following values:
1965 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1966 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1967 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1968 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1969 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1970 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1971 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1972 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1973 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1974 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1975 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
1976 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1977 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1978 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
1979 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1980 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1981 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1982 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1983 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1984 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1985 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1986 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
1987 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
1988 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
1989 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1990 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1991 *
1992 * (*) value not defined in all devices.
1993 * @retval None
1994 */
1995 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
1996 {
1997 CLEAR_BIT(RCC->APB1LENR, Periphs);
1998 }
1999
2000 /**
2001 * @brief Force APB1 peripherals reset.
2002 * @rmtoll APB1LRSTR TIM2RST LL_APB1_GRP1_ForceReset\n
2003 * APB1LRSTR TIM3RST LL_APB1_GRP1_ForceReset\n
2004 * APB1LRSTR TIM4RST LL_APB1_GRP1_ForceReset\n
2005 * APB1LRSTR TIM5RST LL_APB1_GRP1_ForceReset\n
2006 * APB1LRSTR TIM6RST LL_APB1_GRP1_ForceReset\n
2007 * APB1LRSTR TIM7RST LL_APB1_GRP1_ForceReset\n
2008 * APB1LRSTR TIM12RST LL_APB1_GRP1_ForceReset\n
2009 * APB1LRSTR TIM13RST LL_APB1_GRP1_ForceReset\n
2010 * APB1LRSTR TIM14RST LL_APB1_GRP1_ForceReset\n
2011 * APB1LRSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n
2012 * APB1LRSTR SPI2RST LL_APB1_GRP1_ForceReset\n
2013 * APB1LRSTR SPI3RST LL_APB1_GRP1_ForceReset\n
2014 * APB1LRSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n
2015 * APB1LRSTR USART2RST LL_APB1_GRP1_ForceReset\n
2016 * APB1LRSTR USART3RST LL_APB1_GRP1_ForceReset\n
2017 * APB1LRSTR UART4RST LL_APB1_GRP1_ForceReset\n
2018 * APB1LRSTR UART5RST LL_APB1_GRP1_ForceReset\n
2019 * APB1LRSTR I2C1RST LL_APB1_GRP1_ForceReset\n
2020 * APB1LRSTR I2C2RST LL_APB1_GRP1_ForceReset\n
2021 * APB1LRSTR I2C3RST LL_APB1_GRP1_ForceReset\n
2022 * APB1LRSTR I2C5RST LL_APB1_GRP5_ForceReset\n (*)
2023 * APB1LRSTR CECRST LL_APB1_GRP1_ForceReset\n
2024 * APB1LRSTR DAC12RST LL_APB1_GRP1_ForceReset\n
2025 * APB1LRSTR UART7RST LL_APB1_GRP1_ForceReset\n
2026 * APB1LRSTR UART8RST LL_APB1_GRP1_ForceReset
2027 * @param Periphs This parameter can be a combination of the following values:
2028 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
2029 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
2030 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
2031 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
2032 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
2033 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
2034 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
2035 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
2036 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
2037 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
2038 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
2039 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
2040 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
2041 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
2042 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
2043 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
2044 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
2045 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
2046 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
2047 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
2048 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
2049 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
2050 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
2051 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
2052 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
2053 *
2054 * (*) value not defined in all devices.
2055 * @retval None
2056 */
2057 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
2058 {
2059 SET_BIT(RCC->APB1LRSTR, Periphs);
2060 }
2061
2062 /**
2063 * @brief Release APB1 peripherals reset.
2064 * @rmtoll APB1LRSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
2065 * APB1LRSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
2066 * APB1LRSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
2067 * APB1LRSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
2068 * APB1LRSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
2069 * APB1LRSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
2070 * APB1LRSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
2071 * APB1LRSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
2072 * APB1LRSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
2073 * APB1LRSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n
2074 * APB1LRSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
2075 * APB1LRSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
2076 * APB1LRSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n
2077 * APB1LRSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
2078 * APB1LRSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
2079 * APB1LRSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
2080 * APB1LRSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
2081 * APB1LRSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
2082 * APB1LRSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
2083 * APB1LRSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n
2084 * APB1LRSTR I2C5RST LL_APB1_GRP1_ReleaseReset\n (*)
2085 * APB1LRSTR CECRST LL_APB1_GRP1_ReleaseReset\n
2086 * APB1LRSTR DAC12RST LL_APB1_GRP1_ReleaseReset\n
2087 * APB1LRSTR UART7RST LL_APB1_GRP1_ReleaseReset\n
2088 * APB1LRSTR UART8RST LL_APB1_GRP1_ReleaseReset
2089 * @param Periphs This parameter can be a combination of the following values:
2090 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
2091 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
2092 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
2093 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
2094 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
2095 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
2096 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
2097 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
2098 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
2099 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
2100 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
2101 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
2102 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
2103 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
2104 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
2105 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
2106 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
2107 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
2108 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
2109 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
2110 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
2111 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
2112 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
2113 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
2114 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
2115 *
2116 * (*) value not defined in all devices.
2117 * @retval None
2118 */
2119 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
2120 {
2121 CLEAR_BIT(RCC->APB1LRSTR, Periphs);
2122 }
2123
2124 /**
2125 * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode.
2126 * @rmtoll APB1LLPENR TIM2LPEN LL_APB1_GRP1_EnableClockSleep\n
2127 * APB1LLPENR TIM3LPEN LL_APB1_GRP1_EnableClockSleep\n
2128 * APB1LLPENR TIM4LPEN LL_APB1_GRP1_EnableClockSleep\n
2129 * APB1LLPENR TIM5LPEN LL_APB1_GRP1_EnableClockSleep\n
2130 * APB1LLPENR TIM6LPEN LL_APB1_GRP1_EnableClockSleep\n
2131 * APB1LLPENR TIM7LPEN LL_APB1_GRP1_EnableClockSleep\n
2132 * APB1LLPENR TIM12LPEN LL_APB1_GRP1_EnableClockSleep\n
2133 * APB1LLPENR TIM13LPEN LL_APB1_GRP1_EnableClockSleep\n
2134 * APB1LLPENR TIM14LPEN LL_APB1_GRP1_EnableClockSleep\n
2135 * APB1LLPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockSleep\n
2136 * APB1LLPENR WWDG2LPEN LL_APB1_GRP1_EnableClockSleep\n (*)
2137 * APB1LLPENR SPI2LPEN LL_APB1_GRP1_EnableClockSleep\n
2138 * APB1LLPENR SPI3LPEN LL_APB1_GRP1_EnableClockSleep\n
2139 * APB1LLPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockSleep\n
2140 * APB1LLPENR USART2LPEN LL_APB1_GRP1_EnableClockSleep\n
2141 * APB1LLPENR USART3LPEN LL_APB1_GRP1_EnableClockSleep\n
2142 * APB1LLPENR UART4LPEN LL_APB1_GRP1_EnableClockSleep\n
2143 * APB1LLPENR UART5LPEN LL_APB1_GRP1_EnableClockSleep\n
2144 * APB1LLPENR I2C1LPEN LL_APB1_GRP1_EnableClockSleep\n
2145 * APB1LLPENR I2C2LPEN LL_APB1_GRP1_EnableClockSleep\n
2146 * APB1LLPENR I2C3LPEN LL_APB1_GRP1_EnableClockSleep\n
2147 * APB1LLPENR I2C5LPEN LL_APB1_GRP1_EnableClockSleep\n (*)
2148 * APB1LLPENR CECLPEN LL_APB1_GRP1_EnableClockSleep\n
2149 * APB1LLPENR DAC12LPEN LL_APB1_GRP1_EnableClockSleep\n
2150 * APB1LLPENR UART7LPEN LL_APB1_GRP1_EnableClockSleep\n
2151 * APB1LLPENR UART8LPEN LL_APB1_GRP1_EnableClockSleep
2152 * @param Periphs This parameter can be a combination of the following values:
2153 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
2154 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
2155 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
2156 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
2157 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
2158 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
2159 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
2160 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
2161 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
2162 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
2163 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
2164 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
2165 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
2166 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
2167 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
2168 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
2169 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
2170 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
2171 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
2172 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
2173 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
2174 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
2175 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
2176 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
2177 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
2178 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
2179 *
2180 * (*) value not defined in all devices.
2181 * @retval None
2182 */
2183 __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
2184 {
2185 __IO uint32_t tmpreg;
2186 SET_BIT(RCC->APB1LLPENR, Periphs);
2187 /* Delay after an RCC peripheral clock enabling */
2188 tmpreg = READ_BIT(RCC->APB1LLPENR, Periphs);
2189 (void)tmpreg;
2190 }
2191
2192 /**
2193 * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode.
2194 * @rmtoll APB1LLPENR TIM2LPEN LL_APB1_GRP1_DisableClockSleep\n
2195 * APB1LLPENR TIM3LPEN LL_APB1_GRP1_DisableClockSleep\n
2196 * APB1LLPENR TIM4LPEN LL_APB1_GRP1_DisableClockSleep\n
2197 * APB1LLPENR TIM5LPEN LL_APB1_GRP1_DisableClockSleep\n
2198 * APB1LLPENR TIM6LPEN LL_APB1_GRP1_DisableClockSleep\n
2199 * APB1LLPENR TIM7LPEN LL_APB1_GRP1_DisableClockSleep\n
2200 * APB1LLPENR TIM12LPEN LL_APB1_GRP1_DisableClockSleep\n
2201 * APB1LLPENR TIM13LPEN LL_APB1_GRP1_DisableClockSleep\n
2202 * APB1LLPENR TIM14LPEN LL_APB1_GRP1_DisableClockSleep\n
2203 * APB1LLPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockSleep\n
2204 * APB1LLPENR WWDG2LPEN LL_APB1_GRP1_DisableClockSleep\n (*)
2205 * APB1LLPENR SPI2LPEN LL_APB1_GRP1_DisableClockSleep\n
2206 * APB1LLPENR SPI3LPEN LL_APB1_GRP1_DisableClockSleep\n
2207 * APB1LLPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockSleep\n
2208 * APB1LLPENR USART2LPEN LL_APB1_GRP1_DisableClockSleep\n
2209 * APB1LLPENR USART3LPEN LL_APB1_GRP1_DisableClockSleep\n
2210 * APB1LLPENR UART4LPEN LL_APB1_GRP1_DisableClockSleep\n
2211 * APB1LLPENR UART5LPEN LL_APB1_GRP1_DisableClockSleep\n
2212 * APB1LLPENR I2C1LPEN LL_APB1_GRP1_DisableClockSleep\n
2213 * APB1LLPENR I2C2LPEN LL_APB1_GRP1_DisableClockSleep\n
2214 * APB1LLPENR I2C3LPEN LL_APB1_GRP1_DisableClockSleep\n
2215 * APB1LLPENR I2C5LPEN LL_APB1_GRP1_DisableClockSleep\n (*)
2216 * APB1LLPENR CECLPEN LL_APB1_GRP1_DisableClockSleep\n
2217 * APB1LLPENR DAC12LPEN LL_APB1_GRP1_DisableClockSleep\n
2218 * APB1LLPENR UART7LPEN LL_APB1_GRP1_DisableClockSleep\n
2219 * APB1LLPENR UART8LPEN LL_APB1_GRP1_DisableClockSleep
2220 * @param Periphs This parameter can be a combination of the following values:
2221 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
2222 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
2223 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
2224 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
2225 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
2226 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
2227 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
2228 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
2229 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
2230 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
2231 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
2232 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
2233 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
2234 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
2235 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
2236 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
2237 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
2238 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
2239 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
2240 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
2241 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
2242 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*)
2243 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
2244 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
2245 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
2246 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
2247 *
2248 * (*) value not defined in all devices.
2249 * @retval None
2250 */
2251 __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
2252 {
2253 CLEAR_BIT(RCC->APB1LLPENR, Periphs);
2254 }
2255
2256 /**
2257 * @brief Enable APB1 peripherals clock.
2258 * @rmtoll APB1HENR CRSEN LL_APB1_GRP2_EnableClock\n
2259 * APB1HENR SWPMIEN LL_APB1_GRP2_EnableClock\n
2260 * APB1HENR OPAMPEN LL_APB1_GRP2_EnableClock\n
2261 * APB1HENR MDIOSEN LL_APB1_GRP2_EnableClock\n
2262 * APB1HENR FDCANEN LL_APB1_GRP2_EnableClock
2263 * @param Periphs This parameter can be a combination of the following values:
2264 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
2265 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
2266 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
2267 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
2268 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2269 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
2270 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
2271 *
2272 * (*) value not defined in all devices.
2273 * @retval None
2274 */
2275 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
2276 {
2277 __IO uint32_t tmpreg;
2278 SET_BIT(RCC->APB1HENR, Periphs);
2279 /* Delay after an RCC peripheral clock enabling */
2280 tmpreg = READ_BIT(RCC->APB1HENR, Periphs);
2281 (void)tmpreg;
2282 }
2283
2284 /**
2285 * @brief Check if APB1 peripheral clock is enabled or not
2286 * @rmtoll APB1HENR CRSEN LL_APB1_GRP2_IsEnabledClock\n
2287 * APB1HENR SWPMIEN LL_APB1_GRP2_IsEnabledClock\n
2288 * APB1HENR OPAMPEN LL_APB1_GRP2_IsEnabledClock\n
2289 * APB1HENR MDIOSEN LL_APB1_GRP2_IsEnabledClock\n
2290 * APB1HENR FDCANEN LL_APB1_GRP2_IsEnabledClock
2291 * @param Periphs This parameter can be a combination of the following values:
2292 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
2293 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
2294 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
2295 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
2296 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2297 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
2298 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
2299 *
2300 * (*) value not defined in all devices.
2301 * @retval uint32_t
2302 */
2303 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
2304 {
2305 return ((READ_BIT(RCC->APB1HENR, Periphs) == Periphs)?1U:0U);
2306 }
2307
2308 /**
2309 * @brief Disable APB1 peripherals clock.
2310 * @rmtoll APB1HENR CRSEN LL_APB1_GRP2_DisableClock\n
2311 * APB1HENR SWPMIEN LL_APB1_GRP2_DisableClock\n
2312 * APB1HENR OPAMPEN LL_APB1_GRP2_DisableClock\n
2313 * APB1HENR MDIOSEN LL_APB1_GRP2_DisableClock\n
2314 * APB1HENR FDCANEN LL_APB1_GRP2_DisableClock
2315 * @param Periphs This parameter can be a combination of the following values:
2316 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
2317 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
2318 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
2319 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
2320 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2321 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
2322 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
2323 *
2324 * (*) value not defined in all devices.
2325 * @retval None
2326 */
2327 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
2328 {
2329 CLEAR_BIT(RCC->APB1HENR, Periphs);
2330 }
2331
2332 /**
2333 * @brief Force APB1 peripherals reset.
2334 * @rmtoll APB1HRSTR CRSRST LL_APB1_GRP2_ForceReset\n
2335 * APB1HRSTR SWPMIRST LL_APB1_GRP2_ForceReset\n
2336 * APB1HRSTR OPAMPRST LL_APB1_GRP2_ForceReset\n
2337 * APB1HRSTR MDIOSRST LL_APB1_GRP2_ForceReset\n
2338 * APB1HRSTR FDCANRST LL_APB1_GRP2_ForceReset
2339 * @param Periphs This parameter can be a combination of the following values:
2340 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
2341 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
2342 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
2343 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
2344 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2345 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
2346 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
2347 *
2348 * (*) value not defined in all devices.
2349 * @retval None
2350 */
2351 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
2352 {
2353 SET_BIT(RCC->APB1HRSTR, Periphs);
2354 }
2355
2356 /**
2357 * @brief Release APB1 peripherals reset.
2358 * @rmtoll APB1HRSTR CRSRST LL_APB1_GRP2_ReleaseReset\n
2359 * APB1HRSTR SWPMIRST LL_APB1_GRP2_ReleaseReset\n
2360 * APB1HRSTR OPAMPRST LL_APB1_GRP2_ReleaseReset\n
2361 * APB1HRSTR MDIOSRST LL_APB1_GRP2_ReleaseReset\n
2362 * APB1HRSTR FDCANRST LL_APB1_GRP2_ReleaseReset
2363 * @param Periphs This parameter can be a combination of the following values:
2364 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
2365 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
2366 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
2367 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
2368 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2369 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
2370 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
2371 *
2372 * (*) value not defined in all devices.
2373 * @retval None
2374 */
2375 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
2376 {
2377 CLEAR_BIT(RCC->APB1HRSTR, Periphs);
2378 }
2379
2380 /**
2381 * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode.
2382 * @rmtoll APB1HLPENR CRSLPEN LL_APB1_GRP2_EnableClockSleep\n
2383 * APB1HLPENR SWPMILPEN LL_APB1_GRP2_EnableClockSleep\n
2384 * APB1HLPENR OPAMPLPEN LL_APB1_GRP2_EnableClockSleep\n
2385 * APB1HLPENR MDIOSLPEN LL_APB1_GRP2_EnableClockSleep\n
2386 * APB1HLPENR FDCANLPEN LL_APB1_GRP2_EnableClockSleep
2387 * @param Periphs This parameter can be a combination of the following values:
2388 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
2389 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
2390 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
2391 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
2392 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2393 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
2394 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
2395 *
2396 * (*) value not defined in all devices.
2397 * @retval None
2398 */
2399 __STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
2400 {
2401 __IO uint32_t tmpreg;
2402 SET_BIT(RCC->APB1HLPENR, Periphs);
2403 /* Delay after an RCC peripheral clock enabling */
2404 tmpreg = READ_BIT(RCC->APB1HLPENR, Periphs);
2405 (void)tmpreg;
2406 }
2407
2408 /**
2409 * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode.
2410 * @rmtoll APB1HLPENR CRSLPEN LL_APB1_GRP2_DisableClockSleep\n
2411 * APB1HLPENR SWPMILPEN LL_APB1_GRP2_DisableClockSleep\n
2412 * APB1HLPENR OPAMPLPEN LL_APB1_GRP2_DisableClockSleep\n
2413 * APB1HLPENR MDIOSLPEN LL_APB1_GRP2_DisableClockSleep\n
2414 * APB1HLPENR FDCANLPEN LL_APB1_GRP2_DisableClockSleep
2415 * @param Periphs This parameter can be a combination of the following values:
2416 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
2417 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
2418 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
2419 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
2420 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2421 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
2422 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
2423 *
2424 * (*) value not defined in all devices.
2425 * @retval None
2426 */
2427 __STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
2428 {
2429 CLEAR_BIT(RCC->APB1HLPENR, Periphs);
2430 }
2431
2432 /**
2433 * @}
2434 */
2435
2436 /** @defgroup BUS_LL_EF_APB2 APB2
2437 * @{
2438 */
2439
2440 /**
2441 * @brief Enable APB2 peripherals clock.
2442 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
2443 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
2444 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
2445 * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n
2446 * APB2ENR UART9EN LL_APB2_GRP1_EnableClock\n (*)
2447 * APB2ENR USART10EN LL_APB2_GRP1_EnableClock\n (*)
2448 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
2449 * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n
2450 * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
2451 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
2452 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
2453 * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n
2454 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
2455 * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n
2456 * APB2ENR SAI3EN LL_APB2_GRP1_EnableClock\n (*)
2457 * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n
2458 * APB2ENR HRTIMEN LL_APB2_GRP1_EnableClock (*)
2459 * @param Periphs This parameter can be a combination of the following values:
2460 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2461 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2462 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2463 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
2464 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
2465 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
2466 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2467 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2468 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2469 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2470 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2471 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2472 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2473 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2474 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
2475 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
2476 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
2477 *
2478 * (*) value not defined in all devices.
2479 * @retval None
2480 */
2481 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
2482 {
2483 __IO uint32_t tmpreg;
2484 SET_BIT(RCC->APB2ENR, Periphs);
2485 /* Delay after an RCC peripheral clock enabling */
2486 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
2487 (void)tmpreg;
2488 }
2489
2490 /**
2491 * @brief Check if APB2 peripheral clock is enabled or not
2492 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
2493 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
2494 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
2495 * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n
2496 * APB2ENR UART9EN LL_APB2_GRP1_IsEnabledClock\n (*)
2497 * APB2ENR USART10EN LL_APB2_GRP1_IsEnabledClock\n (*)
2498 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
2499 * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n
2500 * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
2501 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
2502 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
2503 * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n
2504 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
2505 * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n
2506 * APB2ENR SAI3EN LL_APB2_GRP1_IsEnabledClock\n
2507 * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n
2508 * APB2ENR HRTIMEN LL_APB2_GRP1_IsEnabledClock
2509 * @param Periphs This parameter can be a combination of the following values:
2510 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2511 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2512 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2513 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
2514 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
2515 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
2516 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2517 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2518 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2519 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2520 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2521 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2522 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2523 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2524 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
2525 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
2526 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
2527 *
2528 * (*) value not defined in all devices.
2529 * @retval uint32_t
2530 */
2531 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
2532 {
2533 return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs)?1U:0U);
2534 }
2535
2536 /**
2537 * @brief Disable APB2 peripherals clock.
2538 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
2539 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
2540 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
2541 * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n
2542 * APB2ENR UART9EN LL_APB2_GRP1_DisableClock\n (*)
2543 * APB2ENR USART10EN LL_APB2_GRP1_DisableClock\n (*)
2544 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
2545 * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n
2546 * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
2547 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
2548 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
2549 * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n
2550 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
2551 * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n
2552 * APB2ENR SAI3EN LL_APB2_GRP1_DisableClock\n (*)
2553 * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n
2554 * APB2ENR HRTIMEN LL_APB2_GRP1_DisableClock (*)
2555 * @param Periphs This parameter can be a combination of the following values:
2556 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2557 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2558 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2559 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
2560 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
2561 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
2562 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2563 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2564 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2565 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2566 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2567 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2568 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2569 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2570 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
2571 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
2572 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
2573 *
2574 * (*) value not defined in all devices.
2575 * @retval None
2576 */
2577 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
2578 {
2579 CLEAR_BIT(RCC->APB2ENR, Periphs);
2580 }
2581
2582 /**
2583 * @brief Force APB2 peripherals reset.
2584 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
2585 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
2586 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
2587 * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n
2588 * APB2ENR UART9RST LL_APB2_GRP1_ForceReset\n (*)
2589 * APB2ENR USART10RST LL_APB2_GRP1_ForceReset\n (*)
2590 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
2591 * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
2592 * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
2593 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
2594 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
2595 * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n
2596 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
2597 * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n
2598 * APB2RSTR SAI3RST LL_APB2_GRP1_ForceReset\n (*)
2599 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n
2600 * APB2RSTR HRTIMRST LL_APB2_GRP1_ForceReset (*)
2601 * @param Periphs This parameter can be a combination of the following values:
2602 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2603 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2604 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2605 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
2606 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
2607 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
2608 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2609 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2610 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2611 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2612 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2613 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2614 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2615 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2616 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
2617 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
2618 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
2619 *
2620 * (*) value not defined in all devices.
2621 * @retval None
2622 */
2623 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
2624 {
2625 SET_BIT(RCC->APB2RSTR, Periphs);
2626 }
2627
2628 /**
2629 * @brief Release APB2 peripherals reset.
2630 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
2631 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
2632 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
2633 * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n
2634 * APB2ENR UART9RST LL_APB2_GRP1_ReleaseReset\n (*)
2635 * APB2ENR USART10RST LL_APB2_GRP1_ReleaseReset\n (*)
2636 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
2637 * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n
2638 * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
2639 * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
2640 * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
2641 * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n
2642 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
2643 * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n
2644 * APB2RSTR SAI3RST LL_APB2_GRP1_ReleaseReset\n (*)
2645 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n
2646 * APB2RSTR HRTIMRST LL_APB2_GRP1_ReleaseReset (*)
2647 * @param Periphs This parameter can be a combination of the following values:
2648 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2649 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2650 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2651 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
2652 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
2653 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
2654 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2655 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2656 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2657 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2658 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2659 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2660 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2661 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2662 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
2663 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
2664 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
2665 *
2666 * (*) value not defined in all devices.
2667 * @retval None
2668 */
2669 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
2670 {
2671 CLEAR_BIT(RCC->APB2RSTR, Periphs);
2672 }
2673
2674 /**
2675 * @brief Enable APB2 peripherals clock during Low Power (Sleep) mode.
2676 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockSleep\n
2677 * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockSleep\n
2678 * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockSleep\n
2679 * APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockSleep\n
2680 * APB2ENR UART9LPEN LL_APB2_GRP1_EnableClockSleep\n (*)
2681 * APB2ENR USART10LPEN LL_APB2_GRP1_EnableClockSleep\n (*)
2682 * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockSleep\n
2683 * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockSleep\n
2684 * APB2LPENR TIM15LPEN LL_APB2_GRP1_EnableClockSleep\n
2685 * APB2LPENR TIM16LPEN LL_APB2_GRP1_EnableClockSleep\n
2686 * APB2LPENR TIM17LPEN LL_APB2_GRP1_EnableClockSleep\n
2687 * APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockSleep\n
2688 * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockSleep\n
2689 * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockSleep\n
2690 * APB2LPENR SAI3LPEN LL_APB2_GRP1_EnableClockSleep\n (*)
2691 * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockSleep\n
2692 * APB2LPENR HRTIMLPEN LL_APB2_GRP1_EnableClockSleep (*)
2693 * @param Periphs This parameter can be a combination of the following values:
2694 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2695 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2696 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2697 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
2698 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
2699 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
2700 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2701 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2702 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2703 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2704 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2705 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2706 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2707 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2708 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
2709 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
2710 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
2711 *
2712 * (*) value not defined in all devices.
2713 * @retval None
2714 */
2715 __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
2716 {
2717 __IO uint32_t tmpreg;
2718 SET_BIT(RCC->APB2LPENR, Periphs);
2719 /* Delay after an RCC peripheral clock enabling */
2720 tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
2721 (void)tmpreg;
2722 }
2723
2724 /**
2725 * @brief Disable APB2 peripherals clock during Low Power (Sleep) mode.
2726 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockSleep\n
2727 * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockSleep\n
2728 * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockSleep\n
2729 * APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockSleep\n
2730 * APB2ENR UART9LPEN LL_APB2_GRP1_DisableClockSleep\n (*)
2731 * APB2ENR USART10LPEN LL_APB2_GRP1_DisableClockSleep\n (*)
2732 * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockSleep\n
2733 * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockSleep\n
2734 * APB2LPENR TIM15LPEN LL_APB2_GRP1_DisableClockSleep\n
2735 * APB2LPENR TIM16LPEN LL_APB2_GRP1_DisableClockSleep\n
2736 * APB2LPENR TIM17LPEN LL_APB2_GRP1_DisableClockSleep\n
2737 * APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockSleep\n
2738 * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockSleep\n
2739 * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockSleep\n
2740 * APB2LPENR SAI3LPEN LL_APB2_GRP1_DisableClockSleep\n (*)
2741 * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockSleep\n
2742 * APB2LPENR HRTIMLPEN LL_APB2_GRP1_DisableClockSleep (*)
2743 * @param Periphs This parameter can be a combination of the following values:
2744 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2745 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2746 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2747 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
2748 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
2749 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
2750 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2751 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2752 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2753 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2754 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2755 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2756 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2757 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2758 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
2759 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
2760 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
2761 *
2762 * (*) value not defined in all devices.
2763 * @retval None
2764 */
2765 __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
2766 {
2767 CLEAR_BIT(RCC->APB2LPENR, Periphs);
2768 }
2769
2770 /**
2771 * @}
2772 */
2773
2774 /** @defgroup BUS_LL_EF_APB4 APB4
2775 * @{
2776 */
2777
2778 /**
2779 * @brief Enable APB4 peripherals clock.
2780 * @rmtoll APB4ENR SYSCFGEN LL_APB4_GRP1_EnableClock\n
2781 * APB4ENR LPUART1EN LL_APB4_GRP1_EnableClock\n
2782 * APB4ENR SPI6EN LL_APB4_GRP1_EnableClock\n
2783 * APB4ENR I2C4EN LL_APB4_GRP1_EnableClock\n
2784 * APB4ENR LPTIM2EN LL_APB4_GRP1_EnableClock\n
2785 * APB4ENR LPTIM3EN LL_APB4_GRP1_EnableClock\n
2786 * APB4ENR LPTIM4EN LL_APB4_GRP1_EnableClock\n (*)
2787 * APB4ENR LPTIM5EN LL_APB4_GRP1_EnableClock\n (*)
2788 * APB4ENR DAC2EN LL_APB4_GRP1_EnableClock\n (*)
2789 * APB4ENR COMP12EN LL_APB4_GRP1_EnableClock\n
2790 * APB4ENR VREFEN LL_APB4_GRP1_EnableClock\n
2791 * APB4ENR RTCAPBEN LL_APB4_GRP1_EnableClock\n
2792 * APB4ENR SAI4EN LL_APB4_GRP1_EnableClock\n (*)
2793 * APB4ENR DTSEN LL_APB4_GRP1_EnableClock\n (*)
2794 * APB4ENR DFSDM2EN LL_APB4_GRP1_EnableClock (*)
2795 * @param Periphs This parameter can be a combination of the following values:
2796 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
2797 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
2798 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
2799 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
2800 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
2801 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
2802 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
2803 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
2804 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*)
2805 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
2806 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
2807 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
2808 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
2809 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
2810 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
2811 *
2812 * (*) value not defined in all devices.
2813 * @retval None
2814 */
2815 __STATIC_INLINE void LL_APB4_GRP1_EnableClock(uint32_t Periphs)
2816 {
2817 __IO uint32_t tmpreg;
2818 SET_BIT(RCC->APB4ENR, Periphs);
2819 /* Delay after an RCC peripheral clock enabling */
2820 tmpreg = READ_BIT(RCC->APB4ENR, Periphs);
2821 (void)tmpreg;
2822 }
2823
2824 /**
2825 * @brief Check if APB4 peripheral clock is enabled or not
2826 * @rmtoll APB4ENR SYSCFGEN LL_APB4_GRP1_IsEnabledClock\n
2827 * APB4ENR LPUART1EN LL_APB4_GRP1_IsEnabledClock\n
2828 * APB4ENR SPI6EN LL_APB4_GRP1_IsEnabledClock\n
2829 * APB4ENR I2C4EN LL_APB4_GRP1_IsEnabledClock\n
2830 * APB4ENR LPTIM2EN LL_APB4_GRP1_IsEnabledClock\n
2831 * APB4ENR LPTIM3EN LL_APB4_GRP1_IsEnabledClock\n
2832 * APB4ENR LPTIM4EN LL_APB4_GRP1_IsEnabledClock\n (*)
2833 * APB4ENR LPTIM5EN LL_APB4_GRP1_IsEnabledClock\n (*)
2834 * APB4ENR DAC2EN LL_APB4_GRP1_IsEnabledClock\n (*)
2835 * APB4ENR COMP12EN LL_APB4_GRP1_IsEnabledClock\n
2836 * APB4ENR VREFEN LL_APB4_GRP1_IsEnabledClock\n
2837 * APB4ENR RTCAPBEN LL_APB4_GRP1_IsEnabledClock\n
2838 * APB4ENR SAI4EN LL_APB4_GRP1_IsEnabledClock\n (*)
2839 * APB4ENR DTSEN LL_APB4_GRP1_IsEnabledClock\n (*)
2840 * APB4ENR DFSDM2EN LL_APB4_GRP1_IsEnabledClock (*)
2841 * @param Periphs This parameter can be a combination of the following values:
2842 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
2843 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
2844 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
2845 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
2846 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
2847 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
2848 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
2849 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
2850 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*)
2851 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
2852 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
2853 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
2854 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
2855 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
2856 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
2857 *
2858 * (*) value not defined in all devices.
2859 * @retval uint32_t
2860 */
2861 __STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
2862 {
2863 return ((READ_BIT(RCC->APB4ENR, Periphs) == Periphs)?1U:0U);
2864 }
2865
2866 /**
2867 * @brief Disable APB4 peripherals clock.
2868 * @rmtoll APB4ENR SYSCFGEN LL_APB4_GRP1_DisableClock\n
2869 * APB4ENR LPUART1EN LL_APB4_GRP1_DisableClock\n
2870 * APB4ENR SPI6EN LL_APB4_GRP1_DisableClock\n
2871 * APB4ENR I2C4EN LL_APB4_GRP1_DisableClock\n
2872 * APB4ENR LPTIM2EN LL_APB4_GRP1_DisableClock\n
2873 * APB4ENR LPTIM3EN LL_APB4_GRP1_DisableClock\n
2874 * APB4ENR LPTIM4EN LL_APB4_GRP1_DisableClock\n (*)
2875 * APB4ENR LPTIM5EN LL_APB4_GRP1_DisableClock\n (*)
2876 * APB4ENR DAC2EN LL_APB4_GRP1_DisableClock\n (*)
2877 * APB4ENR COMP12EN LL_APB4_GRP1_DisableClock\n
2878 * APB4ENR VREFEN LL_APB4_GRP1_DisableClock\n
2879 * APB4ENR RTCAPBEN LL_APB4_GRP1_DisableClock\n
2880 * APB4ENR SAI4EN LL_APB4_GRP1_DisableClock\n (*)
2881 * APB4ENR DTSEN LL_APB4_GRP1_DisableClock\n (*)
2882 * APB4ENR DFSDM2EN LL_APB4_GRP1_DisableClock (*)
2883 * @param Periphs This parameter can be a combination of the following values:
2884 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
2885 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
2886 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
2887 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
2888 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
2889 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
2890 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
2891 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
2892 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*)
2893 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
2894 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
2895 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
2896 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
2897 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
2898 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
2899 *
2900 * (*) value not defined in all devices.
2901 * @retval None
2902 */
2903 __STATIC_INLINE void LL_APB4_GRP1_DisableClock(uint32_t Periphs)
2904 {
2905 CLEAR_BIT(RCC->APB4ENR, Periphs);
2906 }
2907
2908 /**
2909 * @brief Force APB4 peripherals reset.
2910 * @rmtoll APB4RSTR SYSCFGRST LL_APB4_GRP1_ForceReset\n
2911 * APB4RSTR LPUART1RST LL_APB4_GRP1_ForceReset\n
2912 * APB4RSTR SPI6RST LL_APB4_GRP1_ForceReset\n
2913 * APB4RSTR I2C4RST LL_APB4_GRP1_ForceReset\n
2914 * APB4RSTR LPTIM2RST LL_APB4_GRP1_ForceReset\n
2915 * APB4RSTR LPTIM3RST LL_APB4_GRP1_ForceReset\n
2916 * APB4RSTR LPTIM4RST LL_APB4_GRP1_ForceReset\n (*)
2917 * APB4RSTR LPTIM5RST LL_APB4_GRP1_ForceReset\n (*)
2918 * APB4RSTR DAC2EN LL_APB4_GRP1_ForceReset\n (*)
2919 * APB4RSTR COMP12RST LL_APB4_GRP1_ForceReset\n
2920 * APB4RSTR VREFRST LL_APB4_GRP1_ForceReset\n
2921 * APB4RSTR SAI4RST LL_APB4_GRP1_ForceReset\n (*)
2922 * APB4RSTR DTSRST LL_APB4_GRP1_ForceReset\n (*)
2923 * APB4RSTR DFSDM2RST LL_APB4_GRP1_ForceReset (*)
2924 * @param Periphs This parameter can be a combination of the following values:
2925 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
2926 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
2927 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
2928 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
2929 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
2930 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
2931 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
2932 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
2933 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*)
2934 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
2935 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
2936 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
2937 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
2938 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
2939 *
2940 * (*) value not defined in all devices.
2941 * @retval None
2942 */
2943 __STATIC_INLINE void LL_APB4_GRP1_ForceReset(uint32_t Periphs)
2944 {
2945 SET_BIT(RCC->APB4RSTR, Periphs);
2946 }
2947
2948 /**
2949 * @brief Release APB4 peripherals reset.
2950 * @rmtoll APB4RSTR SYSCFGRST LL_APB4_GRP1_ReleaseReset\n
2951 * APB4RSTR LPUART1RST LL_APB4_GRP1_ReleaseReset\n
2952 * APB4RSTR SPI6RST LL_APB4_GRP1_ReleaseReset\n
2953 * APB4RSTR I2C4RST LL_APB4_GRP1_ReleaseReset\n
2954 * APB4RSTR LPTIM2RST LL_APB4_GRP1_ReleaseReset\n
2955 * APB4RSTR LPTIM3RST LL_APB4_GRP1_ReleaseReset\n
2956 * APB4RSTR LPTIM4RST LL_APB4_GRP1_ReleaseReset\n (*)
2957 * APB4RSTR LPTIM5RST LL_APB4_GRP1_ReleaseReset\n (*)
2958 * APB4RSTR DAC2RST LL_APB4_GRP1_ReleaseReset\n (*)
2959 * APB4RSTR COMP12RST LL_APB4_GRP1_ReleaseReset\n
2960 * APB4RSTR VREFRST LL_APB4_GRP1_ReleaseReset\n
2961 * APB4RSTR SAI4RST LL_APB4_GRP1_ReleaseReset\n
2962 * APB4RSTR DTSRST LL_APB4_GRP1_ReleaseReset\n (*)
2963 * APB4RSTR DFSDM2RST LL_APB4_GRP1_ReleaseReset (*)
2964 * @param Periphs This parameter can be a combination of the following values:
2965 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
2966 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
2967 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
2968 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
2969 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
2970 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
2971 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
2972 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
2973 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*)
2974 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
2975 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
2976 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
2977 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
2978 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
2979 *
2980 * (*) value not defined in all devices.
2981 * @retval None
2982 */
2983 __STATIC_INLINE void LL_APB4_GRP1_ReleaseReset(uint32_t Periphs)
2984 {
2985 CLEAR_BIT(RCC->APB4RSTR, Periphs);
2986 }
2987
2988 /**
2989 * @brief Enable APB4 peripherals clock during Low Power (Sleep) mode.
2990 * @rmtoll APB4LPENR SYSCFGLPEN LL_APB4_GRP1_EnableClockSleep\n
2991 * APB4LPENR LPUART1LPEN LL_APB4_GRP1_EnableClockSleep\n
2992 * APB4LPENR SPI6LPEN LL_APB4_GRP1_EnableClockSleep\n
2993 * APB4LPENR I2C4LPEN LL_APB4_GRP1_EnableClockSleep\n
2994 * APB4LPENR LPTIM2LPEN LL_APB4_GRP1_EnableClockSleep\n
2995 * APB4LPENR LPTIM3LPEN LL_APB4_GRP1_EnableClockSleep\n
2996 * APB4LPENR LPTIM4LPEN LL_APB4_GRP1_EnableClockSleep\n (*)
2997 * APB4LPENR LPTIM5LPEN LL_APB4_GRP1_EnableClockSleep\n (*)
2998 * APB4LPENR DAC2LPEN LL_APB4_GRP1_EnableClockSleep\n (*)
2999 * APB4LPENR COMP12LPEN LL_APB4_GRP1_EnableClockSleep\n
3000 * APB4LPENR VREFLPEN LL_APB4_GRP1_EnableClockSleep\n
3001 * APB4LPENR RTCAPBLPEN LL_APB4_GRP1_EnableClockSleep\n
3002 * APB4LPENR SAI4LPEN LL_APB4_GRP1_EnableClockSleep\n (*)
3003 * APB4LPENR DTSLPEN LL_APB4_GRP1_EnableClockSleep\n (*)
3004 * APB4LPENR DFSDM2LPEN LL_APB4_GRP1_EnableClockSleep (*)
3005 * @param Periphs This parameter can be a combination of the following values:
3006 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
3007 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
3008 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
3009 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
3010 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
3011 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
3012 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
3013 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
3014 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*)
3015 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
3016 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
3017 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
3018 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
3019 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
3020 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
3021 *
3022 * (*) value not defined in all devices.
3023 * @retval None
3024 */
3025 __STATIC_INLINE void LL_APB4_GRP1_EnableClockSleep(uint32_t Periphs)
3026 {
3027 __IO uint32_t tmpreg;
3028 SET_BIT(RCC->APB4LPENR, Periphs);
3029 /* Delay after an RCC peripheral clock enabling */
3030 tmpreg = READ_BIT(RCC->APB4LPENR, Periphs);
3031 (void)tmpreg;
3032 }
3033
3034 /**
3035 * @brief Disable APB4 peripherals clock during Low Power (Sleep) mode.
3036 * @rmtoll APB4LPENR SYSCFGLPEN LL_APB4_GRP1_DisableClockSleep\n
3037 * APB4LPENR LPUART1LPEN LL_APB4_GRP1_DisableClockSleep\n
3038 * APB4LPENR SPI6LPEN LL_APB4_GRP1_DisableClockSleep\n
3039 * APB4LPENR I2C4LPEN LL_APB4_GRP1_DisableClockSleep\n
3040 * APB4LPENR LPTIM2LPEN LL_APB4_GRP1_DisableClockSleep\n
3041 * APB4LPENR LPTIM3LPEN LL_APB4_GRP1_DisableClockSleep\n
3042 * APB4LPENR LPTIM4LPEN LL_APB4_GRP1_DisableClockSleep\n (*)
3043 * APB4LPENR LPTIM5LPEN LL_APB4_GRP1_DisableClockSleep\n (*)
3044 * APB4LPENR DAC2LPEN LL_APB4_GRP1_DisableClockSleep\n (*)
3045 * APB4LPENR COMP12LPEN LL_APB4_GRP1_DisableClockSleep\n
3046 * APB4LPENR VREFLPEN LL_APB4_GRP1_DisableClockSleep\n
3047 * APB4LPENR RTCAPBLPEN LL_APB4_GRP1_DisableClockSleep\n
3048 * APB4LPENR SAI4LPEN LL_APB4_GRP1_DisableClockSleep\n (*)
3049 * APB4LPENR DTSLPEN LL_APB4_GRP1_DisableClockSleep\n (*)
3050 * APB4LPENR DFSDM2LPEN LL_APB4_GRP1_DisableClockSleep (*)
3051 * @param Periphs This parameter can be a combination of the following values:
3052 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
3053 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
3054 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
3055 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
3056 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
3057 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
3058 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
3059 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
3060 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*)
3061 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
3062 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
3063 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
3064 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
3065 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
3066 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
3067 *
3068 * (*) value not defined in all devices.
3069 * @retval None
3070 */
3071 __STATIC_INLINE void LL_APB4_GRP1_DisableClockSleep(uint32_t Periphs)
3072 {
3073 CLEAR_BIT(RCC->APB4LPENR, Periphs);
3074 }
3075
3076 /**
3077 * @}
3078 */
3079
3080 /** @defgroup BUS_LL_EF_CLKAM CLKAM
3081 * @{
3082 */
3083
3084 /**
3085 * @brief Enable peripherals clock for CLKAM Mode.
3086 * @rmtoll D3AMR / SRDAMR BDMA LL_CLKAM_Enable\n
3087 * D3AMR / SRDAMR LPUART1 LL_CLKAM_Enable\n
3088 * D3AMR / SRDAMR SPI6 LL_CLKAM_Enable\n
3089 * D3AMR / SRDAMR I2C4 LL_CLKAM_Enable\n
3090 * D3AMR / SRDAMR LPTIM2 LL_CLKAM_Enable\n
3091 * D3AMR / SRDAMR LPTIM3 LL_CLKAM_Enable\n
3092 * D3AMR / SRDAMR LPTIM4 LL_CLKAM_Enable\n (*)
3093 * D3AMR / SRDAMR LPTIM5 LL_CLKAM_Enable\n (*)
3094 * D3AMR / SRDAMR DAC2 LL_CLKAM_Enable\n (*)
3095 * D3AMR / SRDAMR COMP12 LL_CLKAM_Enable\n
3096 * D3AMR / SRDAMR VREF LL_CLKAM_Enable\n
3097 * D3AMR / SRDAMR RTC LL_CLKAM_Enable\n
3098 * D3AMR / SRDAMR CRC LL_CLKAM_Enable\n
3099 * D3AMR / SRDAMR SAI4 LL_CLKAM_Enable\n (*)
3100 * D3AMR / SRDAMR ADC3 LL_CLKAM_Enable\n (*)
3101 * D3AMR / SRDAMR DTS LL_CLKAM_Enable\n (*)
3102 * D3AMR / SRDAMR DFSDM2 LL_CLKAM_Enable\n (*)
3103 * D3AMR / SRDAMR BKPRAM LL_CLKAM_Enable\n
3104 * D3AMR / SRDAMR SRAM4 LL_CLKAM_Enable
3105 * @param Periphs This parameter can be a combination of the following values:
3106 * @arg @ref LL_CLKAM_PERIPH_BDMA
3107 * @arg @ref LL_CLKAM_PERIPH_GPIO (*)
3108 * @arg @ref LL_CLKAM_PERIPH_LPUART1
3109 * @arg @ref LL_CLKAM_PERIPH_SPI6
3110 * @arg @ref LL_CLKAM_PERIPH_I2C4
3111 * @arg @ref LL_CLKAM_PERIPH_LPTIM2
3112 * @arg @ref LL_CLKAM_PERIPH_LPTIM3
3113 * @arg @ref LL_CLKAM_PERIPH_LPTIM4 (*)
3114 * @arg @ref LL_CLKAM_PERIPH_LPTIM5 (*)
3115 * @arg @ref LL_CLKAM_PERIPH_DAC2 (*)
3116 * @arg @ref LL_CLKAM_PERIPH_COMP12
3117 * @arg @ref LL_CLKAM_PERIPH_VREF
3118 * @arg @ref LL_CLKAM_PERIPH_RTC
3119 * @arg @ref LL_CLKAM_PERIPH_CRC (*)
3120 * @arg @ref LL_CLKAM_PERIPH_SAI4 (*)
3121 * @arg @ref LL_CLKAM_PERIPH_ADC3 (*)
3122 * @arg @ref LL_CLKAM_PERIPH_DTS (*)
3123 * @arg @ref LL_CLKAM_PERIPH_DFSDM2 (*)
3124 * @arg @ref LL_CLKAM_PERIPH_BKPRAM
3125 * @arg @ref LL_CLKAM_PERIPH_SRAM4
3126 *
3127 * (*) value not defined in all devices.
3128 * @retval None
3129 */
3130 __STATIC_INLINE void LL_CLKAM_Enable(uint32_t Periphs)
3131 {
3132 __IO uint32_t tmpreg;
3133
3134 #if defined(RCC_D3AMR_BDMAAMEN)
3135 SET_BIT(RCC->D3AMR, Periphs);
3136 /* Delay after an RCC peripheral clock enabling */
3137 tmpreg = READ_BIT(RCC->D3AMR, Periphs);
3138 #else
3139 SET_BIT(RCC->SRDAMR, Periphs);
3140 /* Delay after an RCC peripheral clock enabling */
3141 tmpreg = READ_BIT(RCC->SRDAMR, Periphs);
3142 #endif /* RCC_D3AMR_BDMAAMEN */
3143 (void)tmpreg;
3144 }
3145
3146 /**
3147 * @brief Disable peripherals clock for CLKAM Mode.
3148 * @rmtoll D3AMR / SRDAMR BDMA LL_CLKAM_Disable\n
3149 * D3AMR / SRDAMR LPUART1 LL_CLKAM_Disable\n
3150 * D3AMR / SRDAMR SPI6 LL_CLKAM_Disable\n
3151 * D3AMR / SRDAMR I2C4 LL_CLKAM_Disable\n
3152 * D3AMR / SRDAMR LPTIM2 LL_CLKAM_Disable\n
3153 * D3AMR / SRDAMR LPTIM3 LL_CLKAM_Disable\n
3154 * D3AMR / SRDAMR LPTIM4 LL_CLKAM_Disable\n (*)
3155 * D3AMR / SRDAMR LPTIM5 LL_CLKAM_Disable\n (*)
3156 * D3AMR / SRDAMR DAC2 LL_CLKAM_Disable\n (*)
3157 * D3AMR / SRDAMR COMP12 LL_CLKAM_Disable\n
3158 * D3AMR / SRDAMR VREF LL_CLKAM_Disable\n
3159 * D3AMR / SRDAMR RTC LL_CLKAM_Disable\n
3160 * D3AMR / SRDAMR CRC LL_CLKAM_Disable\n
3161 * D3AMR / SRDAMR SAI4 LL_CLKAM_Disable\n (*)
3162 * D3AMR / SRDAMR ADC3 LL_CLKAM_Disable\n (*)
3163 * D3AMR / SRDAMR DTS LL_CLKAM_Disable\n (*)
3164 * D3AMR / SRDAMR DFSDM2 LL_CLKAM_Disable\n (*)
3165 * D3AMR / SRDAMR BKPRAM LL_CLKAM_Disable\n
3166 * D3AMR / SRDAMR SRAM4 LL_CLKAM_Disable
3167 * @param Periphs This parameter can be a combination of the following values:
3168 * @arg @ref LL_CLKAM_PERIPH_BDMA
3169 * @arg @ref LL_CLKAM_PERIPH_GPIO (*)
3170 * @arg @ref LL_CLKAM_PERIPH_LPUART1
3171 * @arg @ref LL_CLKAM_PERIPH_SPI6
3172 * @arg @ref LL_CLKAM_PERIPH_I2C4
3173 * @arg @ref LL_CLKAM_PERIPH_LPTIM2
3174 * @arg @ref LL_CLKAM_PERIPH_LPTIM3
3175 * @arg @ref LL_CLKAM_PERIPH_LPTIM4 (*)
3176 * @arg @ref LL_CLKAM_PERIPH_LPTIM5 (*)
3177 * @arg @ref LL_CLKAM_PERIPH_DAC2 (*)
3178 * @arg @ref LL_CLKAM_PERIPH_COMP12
3179 * @arg @ref LL_CLKAM_PERIPH_VREF
3180 * @arg @ref LL_CLKAM_PERIPH_RTC
3181 * @arg @ref LL_CLKAM_PERIPH_CRC (*)
3182 * @arg @ref LL_CLKAM_PERIPH_SAI4 (*)
3183 * @arg @ref LL_CLKAM_PERIPH_ADC3 (*)
3184 * @arg @ref LL_CLKAM_PERIPH_DTS (*)
3185 * @arg @ref LL_CLKAM_PERIPH_DFSDM2 (*)
3186 * @arg @ref LL_CLKAM_PERIPH_BKPRAM
3187 * @arg @ref LL_CLKAM_PERIPH_SRAM4
3188 *
3189 * (*) value not defined in all devices.
3190 * @retval None
3191 */
3192 __STATIC_INLINE void LL_CLKAM_Disable(uint32_t Periphs)
3193 {
3194 #if defined(RCC_D3AMR_BDMAAMEN)
3195 CLEAR_BIT(RCC->D3AMR, Periphs);
3196 #else
3197 CLEAR_BIT(RCC->SRDAMR, Periphs);
3198 #endif /* RCC_D3AMR_BDMAAMEN */
3199 }
3200
3201 /**
3202 * @}
3203 */
3204
3205 /** @defgroup BUS_LL_EF_CKGA CKGA
3206 * @{
3207 */
3208
3209 #if defined(RCC_CKGAENR_AXICKG)
3210
3211
3212 /**
3213 * @brief Enable clock gating for AXI bus peripherals.
3214 * @rmtoll
3215 * @param :
3216 * @retval None
3217 */
3218 __STATIC_INLINE void LL_CKGA_Enable(uint32_t Periphs)
3219 {
3220 __IO uint32_t tmpreg;
3221 SET_BIT(RCC->CKGAENR, Periphs);
3222 /* Delay after an RCC peripheral clock enabling */
3223 tmpreg = READ_BIT(RCC->CKGAENR, Periphs);
3224 (void)tmpreg;
3225 }
3226
3227 #endif /* RCC_CKGAENR_AXICKG */
3228
3229 #if defined(RCC_CKGAENR_AXICKG)
3230
3231 /**
3232 * @brief Disable clock gating for AXI bus peripherals.
3233 * @rmtoll
3234 * @param :
3235 * @retval None
3236 */
3237 __STATIC_INLINE void LL_CKGA_Disable(uint32_t Periphs)
3238 {
3239 CLEAR_BIT(RCC->CKGAENR, Periphs);
3240 }
3241
3242 #endif /* RCC_CKGAENR_AXICKG */
3243
3244 /**
3245 * @}
3246 */
3247
3248 #if defined(DUAL_CORE)
3249 /** @addtogroup BUS_LL_EF_AHB3 AHB3
3250 * @{
3251 */
3252
3253 /**
3254 * @brief Enable C1 AHB3 peripherals clock.
3255 * @rmtoll AHB3ENR MDMAEN LL_C1_AHB3_GRP1_EnableClock\n
3256 * AHB3ENR DMA2DEN LL_C1_AHB3_GRP1_EnableClock\n
3257 * AHB3ENR JPGDECEN LL_C1_AHB3_GRP1_EnableClock\n
3258 * AHB3ENR FMCEN LL_C1_AHB3_GRP1_EnableClock\n
3259 * AHB3ENR QSPIEN LL_C1_AHB3_GRP1_EnableClock\n (*)
3260 * AHB3ENR OSPI1EN LL_C1_AHB3_GRP1_EnableClock\n (*)
3261 * AHB3ENR OSPI2EN LL_C1_AHB3_GRP1_EnableClock\n (*)
3262 * AHB3ENR IOMNGREN LL_C1_AHB3_GRP1_EnableClock\n (*)
3263 * AHB3ENR OTFDEC1EN LL_C1_AHB3_GRP1_EnableClock\n (*)
3264 * AHB3ENR OTFDEC2EN LL_C1_AHB3_GRP1_EnableClock\n (*)
3265 * AHB3ENR GFXMMU LL_C1_AHB3_GRP1_EnableClock\n (*)
3266 * AHB3ENR SDMMC1EN LL_C1_AHB3_GRP1_EnableClock
3267 * @param Periphs This parameter can be a combination of the following values:
3268 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
3269 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
3270 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
3271 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
3272 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
3273 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
3274 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
3275 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
3276 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
3277 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
3278 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
3279 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
3280 *
3281 * (*) value not defined in all devices.
3282 * @retval None
3283 */
3284 __STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClock(uint32_t Periphs)
3285 {
3286 __IO uint32_t tmpreg;
3287 SET_BIT(RCC_C1->AHB3ENR, Periphs);
3288 /* Delay after an RCC peripheral clock enabling */
3289 tmpreg = READ_BIT(RCC_C1->AHB3ENR, Periphs);
3290 (void)tmpreg;
3291 }
3292
3293 /**
3294 * @brief Check if C1 AHB3 peripheral clock is enabled or not
3295 * @rmtoll AHB3ENR MDMAEN LL_C1_AHB3_GRP1_IsEnabledClock\n
3296 * AHB3ENR DMA2DEN LL_C1_AHB3_GRP1_IsEnabledClock\n
3297 * AHB3ENR JPGDECEN LL_C1_AHB3_GRP1_IsEnabledClock\n
3298 * AHB3ENR FMCEN LL_C1_AHB3_GRP1_IsEnabledClock\n
3299 * AHB3ENR QSPIEN LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
3300 * AHB3ENR OSPI1EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
3301 * AHB3ENR OSPI2EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
3302 * AHB3ENR IOMNGREN LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
3303 * AHB3ENR OTFDEC1EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
3304 * AHB3ENR OTFDEC2EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
3305 * AHB3ENR GFXMMU LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
3306 * AHB3ENR SDMMC1EN LL_C1_AHB3_GRP1_IsEnabledClock
3307 * @param Periphs This parameter can be a combination of the following values:
3308 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
3309 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
3310 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
3311 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
3312 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
3313 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
3314 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
3315 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
3316 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
3317 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
3318 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
3319 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
3320 *
3321 * (*) value not defined in all devices.
3322 * @retval uint32_t
3323 */
3324 __STATIC_INLINE uint32_t LL_C1_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
3325 {
3326 return ((READ_BIT(RCC_C1->AHB3ENR, Periphs) == Periphs)?1U:0U);
3327 }
3328
3329 /**
3330 * @brief Disable C1 AHB3 peripherals clock.
3331 * @rmtoll AHB3ENR MDMAEN LL_C1_AHB3_GRP1_DisableClock\n
3332 * AHB3ENR DMA2DEN LL_C1_AHB3_GRP1_DisableClock\n
3333 * AHB3ENR JPGDECEN LL_C1_AHB3_GRP1_DisableClock\n
3334 * AHB3ENR FMCEN LL_C1_AHB3_GRP1_DisableClock\n
3335 * AHB3ENR QSPIEN LL_C1_AHB3_GRP1_DisableClock\n (*)
3336 * AHB3ENR OSPI1EN LL_C1_AHB3_GRP1_DisableClock\n (*)
3337 * AHB3ENR OSPI2EN LL_C1_AHB3_GRP1_DisableClock\n (*)
3338 * AHB3ENR IOMNGREN LL_C1_AHB3_GRP1_DisableClock\n (*)
3339 * AHB3ENR OTFDEC1EN LL_C1_AHB3_GRP1_DisableClock\n (*)
3340 * AHB3ENR OTFDEC2EN LL_C1_AHB3_GRP1_DisableClock\n (*)
3341 * AHB3ENR GFXMMU LL_C1_AHB3_GRP1_DisableClock\n (*)
3342 * AHB3ENR SDMMC1EN LL_C1_AHB3_GRP1_DisableClock
3343 * @param Periphs This parameter can be a combination of the following values:
3344 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
3345 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
3346 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
3347 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
3348 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
3349 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
3350 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
3351 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
3352 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
3353 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
3354 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
3355 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
3356 *
3357 * (*) value not defined in all devices.
3358 * @retval None
3359 */
3360 __STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClock(uint32_t Periphs)
3361 {
3362 CLEAR_BIT(RCC_C1->AHB3ENR, Periphs);
3363 }
3364
3365 /**
3366 * @brief Enable C1 AHB3 peripherals clock during Low Power (Sleep) mode.
3367 * @rmtoll AHB3LPENR MDMALPEN LL_C1_AHB3_GRP1_EnableClockSleep\n
3368 * AHB3LPENR DMA2DLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n
3369 * AHB3LPENR JPGDECLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n
3370 * AHB3LPENR FMCLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n
3371 * AHB3LPENR QSPILPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*)
3372 * AHB3LPENR OSPI1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*)
3373 * AHB3LPENR OSPI2LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*)
3374 * AHB3LPENR IOMNGRLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*)
3375 * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*)
3376 * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*)
3377 * AHB3LPENR GFXMMULPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*)
3378 * AHB3LPENR SDMMC1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n
3379 * AHB3LPENR FLASHLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n
3380 * AHB3LPENR DTCM1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n
3381 * AHB3LPENR DTCM2LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n
3382 * AHB3LPENR ITCMLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n
3383 * AHB3LPENR AXISRAMLPEN LL_C1_AHB3_GRP1_EnableClockSleep
3384 * @param Periphs This parameter can be a combination of the following values:
3385 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
3386 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
3387 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
3388 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
3389 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
3390 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
3391 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
3392 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
3393 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
3394 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
3395 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
3396 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
3397 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
3398 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
3399 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
3400 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
3401 *
3402 * (*) value not defined in all devices.
3403 * @retval None
3404 */
3405 __STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
3406 {
3407 __IO uint32_t tmpreg;
3408 SET_BIT(RCC_C1->AHB3LPENR, Periphs);
3409 /* Delay after an RCC peripheral clock enabling */
3410 tmpreg = READ_BIT(RCC_C1->AHB3LPENR, Periphs);
3411 (void)tmpreg;
3412 }
3413
3414 /**
3415 * @brief Disable C1 AHB3 peripherals clock during Low Power (Sleep) mode.
3416 * @rmtoll AHB3LPENR MDMALPEN LL_C1_AHB3_GRP1_DisableClockSleep\n
3417 * AHB3LPENR DMA2DLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n
3418 * AHB3LPENR JPGDECLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n
3419 * AHB3LPENR FMCLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n
3420 * AHB3LPENR QSPILPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*)
3421 * AHB3LPENR OSPI1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*)
3422 * AHB3LPENR OSPI2LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*)
3423 * AHB3LPENR IOMNGRLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*)
3424 * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*)
3425 * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*)
3426 * AHB3LPENR GFXMMULPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*)
3427 * AHB3LPENR SDMMC1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n
3428 * AHB3LPENR FLASHLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n
3429 * AHB3LPENR DTCM1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n
3430 * AHB3LPENR DTCM2LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n
3431 * AHB3LPENR ITCMLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n
3432 * AHB3LPENR AXISRAMLPEN LL_C1_AHB3_GRP1_DisableClockSleep
3433 * @param Periphs This parameter can be a combination of the following values:
3434 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
3435 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
3436 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
3437 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
3438 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
3439 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
3440 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
3441 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
3442 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
3443 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
3444 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
3445 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
3446 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
3447 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
3448 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
3449 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
3450 *
3451 * (*) value not defined in all devices.
3452 * @retval None
3453 */
3454 __STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
3455 {
3456 CLEAR_BIT(RCC_C1->AHB3LPENR, Periphs);
3457 }
3458
3459 /**
3460 * @}
3461 */
3462
3463 /** @addtogroup BUS_LL_EF_AHB1 AHB1
3464 * @{
3465 */
3466
3467 /**
3468 * @brief Enable C1 AHB1 peripherals clock.
3469 * @rmtoll AHB1ENR DMA1EN LL_C1_AHB1_GRP1_EnableClock\n
3470 * AHB1ENR DMA2EN LL_C1_AHB1_GRP1_EnableClock\n
3471 * AHB1ENR ADC12EN LL_C1_AHB1_GRP1_EnableClock\n
3472 * AHB1ENR CRCEN LL_C1_AHB1_GRP1_EnableClock\n (*)
3473 * AHB1ENR ARTEN LL_C1_AHB1_GRP1_EnableClock\n (*)
3474 * AHB1ENR ETH1MACEN LL_C1_AHB1_GRP1_EnableClock\n (*)
3475 * AHB1ENR ETH1TXEN LL_C1_AHB1_GRP1_EnableClock\n (*)
3476 * AHB1ENR ETH1RXEN LL_C1_AHB1_GRP1_EnableClock\n (*)
3477 * AHB1ENR USB1OTGHSEN LL_C1_AHB1_GRP1_EnableClock\n
3478 * AHB1ENR USB1OTGHSULPIEN LL_C1_AHB1_GRP1_EnableClock\n
3479 * AHB1ENR USB2OTGHSEN LL_C1_AHB1_GRP1_EnableClock\n (*)
3480 * AHB1ENR USB2OTGHSULPIEN LL_C1_AHB1_GRP1_EnableClock (*)
3481 * @param Periphs This parameter can be a combination of the following values:
3482 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
3483 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
3484 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
3485 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
3486 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
3487 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
3488 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
3489 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
3490 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
3491 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
3492 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
3493 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
3494 *
3495 * (*) value not defined in all devices.
3496 * @retval None
3497 */
3498 __STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClock(uint32_t Periphs)
3499 {
3500 __IO uint32_t tmpreg;
3501 SET_BIT(RCC_C1->AHB1ENR, Periphs);
3502 /* Delay after an RCC peripheral clock enabling */
3503 tmpreg = READ_BIT(RCC_C1->AHB1ENR, Periphs);
3504 (void)tmpreg;
3505 }
3506
3507 /**
3508 * @brief Check if C1 AHB1 peripheral clock is enabled or not
3509 * @rmtoll AHB1ENR DMA1EN LL_C1_AHB1_GRP1_IsEnabledClock\n
3510 * AHB1ENR DMA2EN LL_C1_AHB1_GRP1_IsEnabledClock\n
3511 * AHB1ENR ADC12EN LL_C1_AHB1_GRP1_IsEnabledClock\n
3512 * AHB1ENR CRCEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*)
3513 * AHB1ENR ARTEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*)
3514 * AHB1ENR ETH1MACEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*)
3515 * AHB1ENR ETH1TXEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*)
3516 * AHB1ENR ETH1RXEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*)
3517 * AHB1ENR USB1OTGHSEN LL_C1_AHB1_GRP1_IsEnabledClock\n
3518 * AHB1ENR USB1OTGHSULPIEN LL_C1_AHB1_GRP1_IsEnabledClock\n
3519 * AHB1ENR USB2OTGHSEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*)
3520 * AHB1ENR USB2OTGHSULPIEN LL_C1_AHB1_GRP1_IsEnabledClock (*)
3521 * @param Periphs This parameter can be a combination of the following values:
3522 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
3523 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
3524 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
3525 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
3526 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
3527 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
3528 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
3529 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
3530 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
3531 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
3532 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
3533 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
3534 *
3535 * (*) value not defined in all devices.
3536 * @retval uint32_t
3537 */
3538 __STATIC_INLINE uint32_t LL_C1_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
3539 {
3540 return ((READ_BIT(RCC_C1->AHB1ENR, Periphs) == Periphs)?1U:0U);
3541 }
3542
3543 /**
3544 * @brief Disable C1 AHB1 peripherals clock.
3545 * @rmtoll AHB1ENR DMA1EN LL_C1_AHB1_GRP1_DisableClock\n
3546 * AHB1ENR DMA2EN LL_C1_AHB1_GRP1_DisableClock\n
3547 * AHB1ENR ADC12EN LL_C1_AHB1_GRP1_DisableClock\n
3548 * AHB1ENR CRCEN LL_C1_AHB1_GRP1_DisableClock\n (*)
3549 * AHB1ENR ARTEN LL_C1_AHB1_GRP1_DisableClock\n (*)
3550 * AHB1ENR ETH1MACEN LL_C1_AHB1_GRP1_DisableClock\n (*)
3551 * AHB1ENR ETH1TXEN LL_C1_AHB1_GRP1_DisableClock\n (*)
3552 * AHB1ENR ETH1RXEN LL_C1_AHB1_GRP1_DisableClock\n (*)
3553 * AHB1ENR USB1OTGHSEN LL_C1_AHB1_GRP1_DisableClock\n
3554 * AHB1ENR USB1OTGHSULPIEN LL_C1_AHB1_GRP1_DisableClock\n
3555 * AHB1ENR USB2OTGHSEN LL_C1_AHB1_GRP1_DisableClock\n (*)
3556 * AHB1ENR USB2OTGHSULPIEN LL_C1_AHB1_GRP1_DisableClock (*)
3557 * @param Periphs This parameter can be a combination of the following values:
3558 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
3559 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
3560 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
3561 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
3562 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
3563 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
3564 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
3565 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
3566 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
3567 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
3568 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
3569 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
3570 *
3571 * (*) value not defined in all devices.
3572 * @retval None
3573 */
3574 __STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClock(uint32_t Periphs)
3575 {
3576 CLEAR_BIT(RCC_C1->AHB1ENR, Periphs);
3577 }
3578
3579 /**
3580 * @brief Enable C1 AHB1 peripherals clock during Low Power (Sleep) mode.
3581 * @rmtoll AHB1LPENR DMA1LPEN LL_C1_AHB1_GRP1_EnableClockSleep\n
3582 * AHB1LPENR DMA2LPEN LL_C1_AHB1_GRP1_EnableClockSleep\n
3583 * AHB1LPENR ADC12LPEN LL_C1_AHB1_GRP1_EnableClockSleep\n
3584 * AHB1LPENR CRCLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
3585 * AHB1LPENR ARTLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
3586 * AHB1LPENR ETH1MACLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
3587 * AHB1LPENR ETH1TXLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
3588 * AHB1LPENR ETH1RXLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
3589 * AHB1LPENR USB1OTGHSLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n
3590 * AHB1LPENR USB1OTGHSULPILPEN LL_C1_AHB1_GRP1_EnableClockSleep\n
3591 * AHB1LPENR USB2OTGHSLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
3592 * AHB1LPENR USB2OTGHSULPILPEN LL_C1_AHB1_GRP1_EnableClockSleep (*)
3593 * @param Periphs This parameter can be a combination of the following values:
3594 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
3595 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
3596 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
3597 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
3598 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
3599 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
3600 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
3601 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
3602 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
3603 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
3604 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
3605 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
3606 *
3607 * (*) value not defined in all devices.
3608 * @retval None
3609 */
3610 __STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
3611 {
3612 __IO uint32_t tmpreg;
3613 SET_BIT(RCC_C1->AHB1LPENR, Periphs);
3614 /* Delay after an RCC peripheral clock enabling */
3615 tmpreg = READ_BIT(RCC_C1->AHB1LPENR, Periphs);
3616 (void)tmpreg;
3617 }
3618
3619 /**
3620 * @brief Disable C1 AHB1 peripherals clock during Low Power (Sleep) mode.
3621 * @rmtoll AHB1LPENR DMA1LPEN LL_C1_AHB1_GRP1_DisableClockSleep\n
3622 * AHB1LPENR DMA2LPEN LL_C1_AHB1_GRP1_DisableClockSleep\n
3623 * AHB1LPENR ADC12LPEN LL_C1_AHB1_GRP1_DisableClockSleep\n
3624 * AHB1LPENR CRCLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
3625 * AHB1LPENR ARTLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
3626 * AHB1LPENR ETH1MACLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
3627 * AHB1LPENR ETH1TXLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
3628 * AHB1LPENR ETH1RXLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
3629 * AHB1LPENR USB1OTGHSLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n
3630 * AHB1LPENR USB1OTGHSULPILPEN LL_C1_AHB1_GRP1_DisableClockSleep\n
3631 * AHB1LPENR USB2OTGHSLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
3632 * AHB1LPENR USB2OTGHSULPILPEN LL_C1_AHB1_GRP1_DisableClockSleep (*)
3633 * @param Periphs This parameter can be a combination of the following values:
3634 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
3635 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
3636 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
3637 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
3638 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
3639 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
3640 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
3641 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
3642 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
3643 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
3644 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
3645 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
3646 *
3647 * (*) value not defined in all devices.
3648 * @retval None
3649 */
3650 __STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
3651 {
3652 CLEAR_BIT(RCC_C1->AHB1LPENR, Periphs);
3653 }
3654
3655 /**
3656 * @}
3657 */
3658
3659 /** @addtogroup BUS_LL_EF_AHB2 AHB2
3660 * @{
3661 */
3662
3663 /**
3664 * @brief Enable C1 AHB2 peripherals clock.
3665 * @rmtoll AHB2ENR DCMIEN LL_C1_AHB2_GRP1_EnableClock\n
3666 * AHB2ENR HSEMEN LL_C1_AHB2_GRP1_EnableClock\n (*)
3667 * AHB2ENR CRYPEN LL_C1_AHB2_GRP1_EnableClock\n (*)
3668 * AHB2ENR HASHEN LL_C1_AHB2_GRP1_EnableClock\n (*)
3669 * AHB2ENR RNGEN LL_C1_AHB2_GRP1_EnableClock\n
3670 * AHB2ENR SDMMC2EN LL_C1_AHB2_GRP1_EnableClock\n
3671 * AHB2ENR BDMA1EN LL_C1_AHB2_GRP1_EnableClock\n (*)
3672 * AHB2ENR D2SRAM1EN LL_C1_AHB2_GRP1_EnableClock\n
3673 * AHB2ENR D2SRAM2EN LL_C1_AHB2_GRP1_EnableClock\n
3674 * AHB2ENR D2SRAM3EN LL_C1_AHB2_GRP1_EnableClock (*)
3675 * @param Periphs This parameter can be a combination of the following values:
3676 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
3677 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
3678 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
3679 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
3680 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
3681 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
3682 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
3683 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
3684 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
3685 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
3686 *
3687 * (*) value not defined in all devices.
3688 * @retval None
3689 */
3690 __STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClock(uint32_t Periphs)
3691 {
3692 __IO uint32_t tmpreg;
3693 SET_BIT(RCC_C1->AHB2ENR, Periphs);
3694 /* Delay after an RCC peripheral clock enabling */
3695 tmpreg = READ_BIT(RCC_C1->AHB2ENR, Periphs);
3696 (void)tmpreg;
3697 }
3698
3699 /**
3700 * @brief Check if C1 AHB2 peripheral clock is enabled or not
3701 * @rmtoll AHB2ENR DCMIEN LL_C1_AHB2_GRP1_IsEnabledClock\n
3702 * AHB2ENR HSEMEN LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
3703 * AHB2ENR CRYPEN LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
3704 * AHB2ENR HASHEN LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
3705 * AHB2ENR RNGEN LL_C1_AHB2_GRP1_IsEnabledClock\n
3706 * AHB2ENR SDMMC2EN LL_C1_AHB2_GRP1_IsEnabledClock\n
3707 * AHB2ENR BDMA1EN LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
3708 * AHB2ENR D2SRAM1EN LL_C1_AHB2_GRP1_IsEnabledClock\n
3709 * AHB2ENR D2SRAM2EN LL_C1_AHB2_GRP1_IsEnabledClock\n
3710 * AHB2ENR D2SRAM3EN LL_C1_AHB2_GRP1_IsEnabledClock (*)
3711 * @param Periphs This parameter can be a combination of the following values:
3712 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
3713 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
3714 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
3715 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
3716 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
3717 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
3718 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
3719 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
3720 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
3721 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
3722 *
3723 * (*) value not defined in all devices.
3724 * @retval uint32_t
3725 */
3726 __STATIC_INLINE uint32_t LL_C1_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
3727 {
3728 return ((READ_BIT(RCC_C1->AHB2ENR, Periphs) == Periphs)?1U:0U);
3729 }
3730
3731 /**
3732 * @brief Disable C1 AHB2 peripherals clock.
3733 * @rmtoll AHB2ENR DCMIEN LL_C1_AHB2_GRP1_DisableClock\n
3734 * AHB2ENR HSEMEN LL_C1_AHB2_GRP1_DisableClock\n (*)
3735 * AHB2ENR CRYPEN LL_C1_AHB2_GRP1_DisableClock\n (*)
3736 * AHB2ENR HASHEN LL_C1_AHB2_GRP1_DisableClock\n (*)
3737 * AHB2ENR RNGEN LL_C1_AHB2_GRP1_DisableClock\n
3738 * AHB2ENR SDMMC2EN LL_C1_AHB2_GRP1_DisableClock\n
3739 * AHB2ENR BDMA1EN LL_C1_AHB2_GRP1_DisableClock\n (*)
3740 * AHB2ENR D2SRAM1EN LL_C1_AHB2_GRP1_DisableClock\n
3741 * AHB2ENR D2SRAM2EN LL_C1_AHB2_GRP1_DisableClock\n
3742 * AHB2ENR D2SRAM3EN LL_C1_AHB2_GRP1_DisableClock (*)
3743 * @param Periphs This parameter can be a combination of the following values:
3744 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
3745 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
3746 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
3747 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
3748 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
3749 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
3750 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
3751 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
3752 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
3753 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
3754 *
3755 * (*) value not defined in all devices.
3756 * @retval None
3757 */
3758 __STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClock(uint32_t Periphs)
3759 {
3760 CLEAR_BIT(RCC_C1->AHB2ENR, Periphs);
3761 }
3762
3763 /**
3764 * @brief Enable C1 AHB2 peripherals clock during Low Power (Sleep) mode.
3765 * @rmtoll AHB2LPENR DCMILPEN LL_C1_AHB2_GRP1_EnableClockSleep\n
3766 * AHB2LPENR CRYPLPEN LL_C1_AHB2_GRP1_EnableClockSleep\n (*)
3767 * AHB2LPENR HASHLPEN LL_C1_AHB2_GRP1_EnableClockSleep\n (*)
3768 * AHB2LPENR RNGLPEN LL_C1_AHB2_GRP1_EnableClockSleep\n
3769 * AHB2LPENR SDMMC2LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n
3770 * AHB2LPENR D2SRAM1LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n
3771 * AHB2LPENR BDAM1LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n (*)
3772 * AHB2LPENR D2SRAM2LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n
3773 * AHB2LPENR D2SRAM3LPEN LL_C1_AHB2_GRP1_EnableClockSleep (*)
3774 * @param Periphs This parameter can be a combination of the following values:
3775 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
3776 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
3777 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
3778 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
3779 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
3780 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
3781 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
3782 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
3783 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
3784 *
3785 * (*) value not defined in all devices.
3786 * @retval None
3787 */
3788 __STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
3789 {
3790 __IO uint32_t tmpreg;
3791 SET_BIT(RCC_C1->AHB2LPENR, Periphs);
3792 /* Delay after an RCC peripheral clock enabling */
3793 tmpreg = READ_BIT(RCC_C1->AHB2LPENR, Periphs);
3794 (void)tmpreg;
3795 }
3796
3797 /**
3798 * @brief Disable C1 AHB2 peripherals clock during Low Power (Sleep) mode.
3799 * @rmtoll AHB2LPENR DCMILPEN LL_C1_AHB2_GRP1_DisableClockSleep\n
3800 * AHB2LPENR CRYPLPEN LL_C1_AHB2_GRP1_DisableClockSleep\n (*)
3801 * AHB2LPENR HASHLPEN LL_C1_AHB2_GRP1_DisableClockSleep\n (*)
3802 * AHB2LPENR RNGLPEN LL_C1_AHB2_GRP1_DisableClockSleep\n
3803 * AHB2LPENR SDMMC2LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n
3804 * AHB2LPENR BDAM1LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n (*)
3805 * AHB2LPENR D2SRAM1LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n
3806 * AHB2LPENR D2SRAM2LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n
3807 * AHB2LPENR D2SRAM3LPEN LL_C1_AHB2_GRP1_DisableClockSleep
3808 * @param Periphs This parameter can be a combination of the following values:
3809 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
3810 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
3811 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
3812 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
3813 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
3814 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
3815 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
3816 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
3817 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
3818 *
3819 * (*) value not defined in all devices.
3820 * @retval None
3821 */
3822 __STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
3823 {
3824 CLEAR_BIT(RCC_C1->AHB2LPENR, Periphs);
3825 }
3826
3827 /**
3828 * @}
3829 */
3830
3831 /** @addtogroup BUS_LL_EF_AHB4 AHB4
3832 * @{
3833 */
3834
3835 /**
3836 * @brief Enable C1 AHB4 peripherals clock.
3837 * @rmtoll AHB4ENR GPIOAEN LL_C1_AHB4_GRP1_EnableClock\n
3838 * AHB4ENR GPIOBEN LL_C1_AHB4_GRP1_EnableClock\n
3839 * AHB4ENR GPIOCEN LL_C1_AHB4_GRP1_EnableClock\n
3840 * AHB4ENR GPIODEN LL_C1_AHB4_GRP1_EnableClock\n
3841 * AHB4ENR GPIOEEN LL_C1_AHB4_GRP1_EnableClock\n
3842 * AHB4ENR GPIOFEN LL_C1_AHB4_GRP1_EnableClock\n
3843 * AHB4ENR GPIOGEN LL_C1_AHB4_GRP1_EnableClock\n
3844 * AHB4ENR GPIOHEN LL_C1_AHB4_GRP1_EnableClock\n
3845 * AHB4ENR GPIOIEN LL_C1_AHB4_GRP1_EnableClock\n
3846 * AHB4ENR GPIOJEN LL_C1_AHB4_GRP1_EnableClock\n
3847 * AHB4ENR GPIOKEN LL_C1_AHB4_GRP1_EnableClock\n
3848 * AHB4ENR CRCEN LL_C1_AHB4_GRP1_EnableClock\n (*)
3849 * AHB4ENR BDMAEN LL_C1_AHB4_GRP1_EnableClock\n
3850 * AHB4ENR ADC3EN LL_C1_AHB4_GRP1_EnableClock\n (*)
3851 * AHB4ENR HSEMEN LL_C1_AHB4_GRP1_EnableClock\n (*)
3852 * AHB4ENR BKPRAMEN LL_C1_AHB4_GRP1_EnableClock\n
3853 * AHB4ENR SRAM4EN LL_C1_AHB4_GRP1_EnableClock
3854 * @param Periphs This parameter can be a combination of the following values:
3855 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
3856 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
3857 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
3858 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
3859 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
3860 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
3861 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
3862 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
3863 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
3864 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
3865 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
3866 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
3867 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
3868 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
3869 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
3870 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
3871 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
3872 *
3873 * (*) value not defined in all devices.
3874 * @retval None
3875 */
3876 __STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClock(uint32_t Periphs)
3877 {
3878 __IO uint32_t tmpreg;
3879 SET_BIT(RCC_C1->AHB4ENR, Periphs);
3880 /* Delay after an RCC peripheral clock enabling */
3881 tmpreg = READ_BIT(RCC_C1->AHB4ENR, Periphs);
3882 (void)tmpreg;
3883 }
3884
3885 /**
3886 * @brief Check if C1 AHB4 peripheral clock is enabled or not
3887 * @rmtoll AHB4ENR GPIOAEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3888 * AHB4ENR GPIOBEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3889 * AHB4ENR GPIOCEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3890 * AHB4ENR GPIODEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3891 * AHB4ENR GPIOEEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3892 * AHB4ENR GPIOFEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3893 * AHB4ENR GPIOGEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3894 * AHB4ENR GPIOHEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3895 * AHB4ENR GPIOIEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3896 * AHB4ENR GPIOJEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3897 * AHB4ENR GPIOKEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3898 * AHB4ENR CRCEN LL_C1_AHB4_GRP1_IsEnabledClock\n (*)
3899 * AHB4ENR BDMAEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3900 * AHB4ENR ADC3EN LL_C1_AHB4_GRP1_IsEnabledClock\n (*)
3901 * AHB4ENR HSEMEN LL_C1_AHB4_GRP1_IsEnabledClock\n (*)
3902 * AHB4ENR BKPRAMEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3903 * AHB4ENR SRAM4EN LL_C1_AHB4_GRP1_IsEnabledClock
3904 * @param Periphs This parameter can be a combination of the following values:
3905 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
3906 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
3907 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
3908 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
3909 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
3910 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
3911 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
3912 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
3913 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
3914 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
3915 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
3916 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
3917 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
3918 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
3919 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
3920 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
3921 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
3922 *
3923 * (*) value not defined in all devices.
3924 * @retval uint32_t
3925 */
3926 __STATIC_INLINE uint32_t LL_C1_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
3927 {
3928 return ((READ_BIT(RCC_C1->AHB4ENR, Periphs) == Periphs)?1U:0U);
3929 }
3930
3931 /**
3932 * @brief Disable C1 AHB4 peripherals clock.
3933 * @rmtoll AHB4ENR GPIOAEN LL_C1_AHB4_GRP1_DisableClock\n
3934 * AHB4ENR GPIOBEN LL_C1_AHB4_GRP1_DisableClock\n
3935 * AHB4ENR GPIOCEN LL_C1_AHB4_GRP1_DisableClock\n
3936 * AHB4ENR GPIODEN LL_C1_AHB4_GRP1_DisableClock\n
3937 * AHB4ENR GPIOEEN LL_C1_AHB4_GRP1_DisableClock\n
3938 * AHB4ENR GPIOFEN LL_C1_AHB4_GRP1_DisableClock\n
3939 * AHB4ENR GPIOGEN LL_C1_AHB4_GRP1_DisableClock\n
3940 * AHB4ENR GPIOHEN LL_C1_AHB4_GRP1_DisableClock\n
3941 * AHB4ENR GPIOIEN LL_C1_AHB4_GRP1_DisableClock\n
3942 * AHB4ENR GPIOJEN LL_C1_AHB4_GRP1_DisableClock\n
3943 * AHB4ENR GPIOKEN LL_C1_AHB4_GRP1_DisableClock\n
3944 * AHB4ENR CRCEN LL_C1_AHB4_GRP1_DisableClock\n (*)
3945 * AHB4ENR BDMAEN LL_C1_AHB4_GRP1_DisableClock\n
3946 * AHB4ENR ADC3EN LL_C1_AHB4_GRP1_DisableClock\n (*)
3947 * AHB4ENR HSEMEN LL_C1_AHB4_GRP1_DisableClock\n (*)
3948 * AHB4ENR BKPRAMEN LL_C1_AHB4_GRP1_DisableClock\n
3949 * AHB4ENR SRAM4EN LL_C1_AHB4_GRP1_DisableClock
3950 * @param Periphs This parameter can be a combination of the following values:
3951 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
3952 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
3953 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
3954 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
3955 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
3956 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
3957 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
3958 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
3959 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
3960 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
3961 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
3962 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
3963 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
3964 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
3965 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
3966 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
3967 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
3968 *
3969 * (*) value not defined in all devices.
3970 * @retval None
3971 */
3972 __STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClock(uint32_t Periphs)
3973 {
3974 CLEAR_BIT(RCC_C1->AHB4ENR, Periphs);
3975 }
3976
3977 /**
3978 * @brief Enable C1 AHB4 peripherals clock during Low Power (Sleep) mode.
3979 * @rmtoll AHB4LPENR GPIOALPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
3980 * AHB4LPENR GPIOBLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
3981 * AHB4LPENR GPIOCLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
3982 * AHB4LPENR GPIODLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
3983 * AHB4LPENR GPIOELPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
3984 * AHB4LPENR GPIOFLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
3985 * AHB4LPENR GPIOGLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
3986 * AHB4LPENR GPIOHLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
3987 * AHB4LPENR GPIOILPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
3988 * AHB4LPENR GPIOJLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
3989 * AHB4LPENR GPIOKLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
3990 * AHB4LPENR CRCLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n (*)
3991 * AHB4LPENR BDMALPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
3992 * AHB4LPENR ADC3LPEN LL_C1_AHB4_GRP1_EnableClockSleep\n (*)
3993 * AHB4LPENR BKPRAMLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
3994 * AHB4LPENR SRAM4LPEN LL_C1_AHB4_GRP1_EnableClockSleep
3995 * @param Periphs This parameter can be a combination of the following values:
3996 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
3997 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
3998 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
3999 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
4000 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
4001 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
4002 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
4003 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
4004 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
4005 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
4006 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
4007 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
4008 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
4009 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
4010 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
4011 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
4012 * @retval None
4013 */
4014 __STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)
4015 {
4016 __IO uint32_t tmpreg;
4017 SET_BIT(RCC_C1->AHB4LPENR, Periphs);
4018 /* Delay after an RCC peripheral clock enabling */
4019 tmpreg = READ_BIT(RCC_C1->AHB4LPENR, Periphs);
4020 (void)tmpreg;
4021 }
4022
4023 /**
4024 * @brief Disable C1 AHB4 peripherals clock during Low Power (Sleep) mode.
4025 * @rmtoll AHB4LPENR GPIOALPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
4026 * AHB4LPENR GPIOBLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
4027 * AHB4LPENR GPIOCLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
4028 * AHB4LPENR GPIODLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
4029 * AHB4LPENR GPIOELPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
4030 * AHB4LPENR GPIOFLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
4031 * AHB4LPENR GPIOGLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
4032 * AHB4LPENR GPIOHLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
4033 * AHB4LPENR GPIOILPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
4034 * AHB4LPENR GPIOJLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
4035 * AHB4LPENR GPIOKLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
4036 * AHB4LPENR CRCLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n (*)
4037 * AHB4LPENR BDMALPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
4038 * AHB4LPENR ADC3LPEN LL_C1_AHB4_GRP1_DisableClockSleep\n (*)
4039 * AHB4LPENR BKPRAMLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
4040 * AHB4LPENR SRAM4LPEN LL_C1_AHB4_GRP1_DisableClockSleep
4041 * @param Periphs This parameter can be a combination of the following values:
4042 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
4043 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
4044 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
4045 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
4046 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
4047 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
4048 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
4049 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
4050 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
4051 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
4052 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
4053 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
4054 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
4055 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
4056 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
4057 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
4058 * @retval None
4059 */
4060 __STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)
4061 {
4062 CLEAR_BIT(RCC_C1->AHB4LPENR, Periphs);
4063 }
4064
4065 /**
4066 * @}
4067 */
4068
4069 /** @addtogroup BUS_LL_EF_APB3 APB3
4070 * @{
4071 */
4072
4073 /**
4074 * @brief Enable C1 APB3 peripherals clock.
4075 * @rmtoll APB3ENR LTDCEN LL_C1_APB3_GRP1_EnableClock\n (*)
4076 * APB3ENR DSIEN LL_C1_APB3_GRP1_EnableClock\n (*)
4077 * APB3ENR WWDG1EN LL_C1_APB3_GRP1_EnableClock
4078 * @param Periphs This parameter can be a combination of the following values:
4079 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
4080 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
4081 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
4082 *
4083 * (*) value not defined in all devices.
4084 * @retval None
4085 */
4086 __STATIC_INLINE void LL_C1_APB3_GRP1_EnableClock(uint32_t Periphs)
4087 {
4088 __IO uint32_t tmpreg;
4089 SET_BIT(RCC_C1->APB3ENR, Periphs);
4090 /* Delay after an RCC peripheral clock enabling */
4091 tmpreg = READ_BIT(RCC_C1->APB3ENR, Periphs);
4092 (void)tmpreg;
4093 }
4094
4095 /**
4096 * @brief Check if C1 APB3 peripheral clock is enabled or not
4097 * @rmtoll APB3ENR LTDCEN LL_C1_APB3_GRP1_IsEnabledClock\n (*)
4098 * APB3ENR DSIEN LL_C1_APB3_GRP1_IsEnabledClock\n (*)
4099 * APB3ENR WWDG1EN LL_C1_APB3_GRP1_IsEnabledClock
4100 * @param Periphs This parameter can be a combination of the following values:
4101 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
4102 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
4103 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
4104 *
4105 * (*) value not defined in all devices.
4106 * @retval uint32_t
4107 */
4108 __STATIC_INLINE uint32_t LL_C1_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
4109 {
4110 return ((READ_BIT(RCC_C1->APB3ENR, Periphs) == Periphs)?1U:0U);
4111 }
4112
4113 /**
4114 * @brief Disable C1 APB3 peripherals clock.
4115 * @rmtoll APB3ENR LTDCEN LL_C1_APB3_GRP1_DisableClock\n (*)
4116 * APB3ENR DSIEN LL_C1_APB3_GRP1_DisableClock\n (*)
4117 * APB3ENR WWDG1EN LL_C1_APB3_GRP1_DisableClock
4118 * @param Periphs This parameter can be a combination of the following values:
4119 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
4120
4121 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
4122 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
4123 *
4124 * (*) value not defined in all devices.
4125 * @retval None
4126 */
4127 __STATIC_INLINE void LL_C1_APB3_GRP1_DisableClock(uint32_t Periphs)
4128 {
4129 CLEAR_BIT(RCC_C1->APB3ENR, Periphs);
4130 }
4131
4132 /**
4133 * @brief Enable C1 APB3 peripherals clock during Low Power (Sleep) mode.
4134 * @rmtoll APB3LPENR LTDCLPEN LL_C1_APB3_GRP1_EnableClockSleep\n (*)
4135 * APB3LPENR DSILPEN LL_C1_APB3_GRP1_EnableClockSleep\n (*)
4136 * APB3LPENR WWDG1LPEN LL_C1_APB3_GRP1_EnableClockSleep
4137 * @param Periphs This parameter can be a combination of the following values:
4138 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
4139 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
4140 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
4141 *
4142 * (*) value not defined in all devices.
4143 * @retval None
4144 */
4145 __STATIC_INLINE void LL_C1_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
4146 {
4147 __IO uint32_t tmpreg;
4148 SET_BIT(RCC_C1->APB3LPENR, Periphs);
4149 /* Delay after an RCC peripheral clock enabling */
4150 tmpreg = READ_BIT(RCC_C1->APB3LPENR, Periphs);
4151 (void)tmpreg;
4152 }
4153
4154 /**
4155 * @brief Disable C1 APB3 peripherals clock during Low Power (Sleep) mode.
4156 * @rmtoll APB3LPENR LTDCLPEN LL_C1_APB3_GRP1_DisableClockSleep\n (*)
4157 * APB3LPENR DSILPEN LL_C1_APB3_GRP1_DisableClockSleep\n (*)
4158 * APB3LPENR WWDG1LPEN LL_C1_APB3_GRP1_DisableClockSleep
4159 * @param Periphs This parameter can be a combination of the following values:
4160 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
4161 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
4162 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
4163 *
4164 * (*) value not defined in all devices.
4165 * @retval None
4166 */
4167 __STATIC_INLINE void LL_C1_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
4168 {
4169 CLEAR_BIT(RCC_C1->APB3LPENR, Periphs);
4170 }
4171
4172 /**
4173 * @}
4174 */
4175
4176 /** @addtogroup BUS_LL_EF_APB1 APB1
4177 * @{
4178 */
4179
4180 /**
4181 * @brief Enable C1 APB1 peripherals clock.
4182 * @rmtoll APB1LENR TIM2EN LL_C1_APB1_GRP1_EnableClock\n
4183 * APB1LENR TIM3EN LL_C1_APB1_GRP1_EnableClock\n
4184 * APB1LENR TIM4EN LL_C1_APB1_GRP1_EnableClock\n
4185 * APB1LENR TIM5EN LL_C1_APB1_GRP1_EnableClock\n
4186 * APB1LENR TIM6EN LL_C1_APB1_GRP1_EnableClock\n
4187 * APB1LENR TIM7EN LL_C1_APB1_GRP1_EnableClock\n
4188 * APB1LENR TIM12EN LL_C1_APB1_GRP1_EnableClock\n
4189 * APB1LENR TIM13EN LL_C1_APB1_GRP1_EnableClock\n
4190 * APB1LENR TIM14EN LL_C1_APB1_GRP1_EnableClock\n
4191 * APB1LENR LPTIM1EN LL_C1_APB1_GRP1_EnableClock\n
4192 * APB1LENR WWDG2EN LL_C1_APB1_GRP1_EnableClock\n (*)
4193 * APB1LENR SPI2EN LL_C1_APB1_GRP1_EnableClock\n
4194 * APB1LENR SPI3EN LL_C1_APB1_GRP1_EnableClock\n
4195 * APB1LENR SPDIFRXEN LL_C1_APB1_GRP1_EnableClock\n
4196 * APB1LENR USART2EN LL_C1_APB1_GRP1_EnableClock\n
4197 * APB1LENR USART3EN LL_C1_APB1_GRP1_EnableClock\n
4198 * APB1LENR UART4EN LL_C1_APB1_GRP1_EnableClock\n
4199 * APB1LENR UART5EN LL_C1_APB1_GRP1_EnableClock\n
4200 * APB1LENR I2C1EN LL_C1_APB1_GRP1_EnableClock\n
4201 * APB1LENR I2C2EN LL_C1_APB1_GRP1_EnableClock\n
4202 * APB1LENR I2C3EN LL_C1_APB1_GRP1_EnableClock\n
4203 * APB1LENR CECEN LL_C1_APB1_GRP1_EnableClock\n
4204 * APB1LENR DAC12EN LL_C1_APB1_GRP1_EnableClock\n
4205 * APB1LENR UART7EN LL_C1_APB1_GRP1_EnableClock\n
4206 * APB1LENR UART8EN LL_C1_APB1_GRP1_EnableClock
4207 * @param Periphs This parameter can be a combination of the following values:
4208 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
4209 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
4210 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
4211 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
4212 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
4213 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
4214 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
4215 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
4216 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
4217 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
4218 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
4219 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
4220 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
4221 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
4222 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
4223 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
4224 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
4225 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
4226 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
4227 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
4228 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
4229 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
4230 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
4231 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
4232 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
4233 *
4234 * (*) value not defined in all devices.
4235 * @retval None
4236 */
4237 __STATIC_INLINE void LL_C1_APB1_GRP1_EnableClock(uint32_t Periphs)
4238 {
4239 __IO uint32_t tmpreg;
4240 SET_BIT(RCC_C1->APB1LENR, Periphs);
4241 /* Delay after an RCC peripheral clock enabling */
4242 tmpreg = READ_BIT(RCC_C1->APB1LENR, Periphs);
4243 (void)tmpreg;
4244 }
4245
4246 /**
4247 * @brief Check if C1 APB1 peripheral clock is enabled or not
4248 * @rmtoll APB1LENR TIM2EN LL_C1_APB1_GRP1_IsEnabledClock\n
4249 * APB1LENR TIM3EN LL_C1_APB1_GRP1_IsEnabledClock\n
4250 * APB1LENR TIM4EN LL_C1_APB1_GRP1_IsEnabledClock\n
4251 * APB1LENR TIM5EN LL_C1_APB1_GRP1_IsEnabledClock\n
4252 * APB1LENR TIM6EN LL_C1_APB1_GRP1_IsEnabledClock\n
4253 * APB1LENR TIM7EN LL_C1_APB1_GRP1_IsEnabledClock\n
4254 * APB1LENR TIM12EN LL_C1_APB1_GRP1_IsEnabledClock\n
4255 * APB1LENR TIM13EN LL_C1_APB1_GRP1_IsEnabledClock\n
4256 * APB1LENR TIM14EN LL_C1_APB1_GRP1_IsEnabledClock\n
4257 * APB1LENR LPTIM1EN LL_C1_APB1_GRP1_IsEnabledClock\n
4258 * APB1LENR WWDG2EN LL_C1_APB1_GRP1_IsEnabledClock\n (*)
4259 * APB1LENR SPI2EN LL_C1_APB1_GRP1_IsEnabledClock\n
4260 * APB1LENR SPI3EN LL_C1_APB1_GRP1_IsEnabledClock\n
4261 * APB1LENR SPDIFRXEN LL_C1_APB1_GRP1_IsEnabledClock\n
4262 * APB1LENR USART2EN LL_C1_APB1_GRP1_IsEnabledClock\n
4263 * APB1LENR USART3EN LL_C1_APB1_GRP1_IsEnabledClock\n
4264 * APB1LENR UART4EN LL_C1_APB1_GRP1_IsEnabledClock\n
4265 * APB1LENR UART5EN LL_C1_APB1_GRP1_IsEnabledClock\n
4266 * APB1LENR I2C1EN LL_C1_APB1_GRP1_IsEnabledClock\n
4267 * APB1LENR I2C2EN LL_C1_APB1_GRP1_IsEnabledClock\n
4268 * APB1LENR I2C3EN LL_C1_APB1_GRP1_IsEnabledClock\n
4269 * APB1LENR CECEN LL_C1_APB1_GRP1_IsEnabledClock\n
4270 * APB1LENR DAC12EN LL_C1_APB1_GRP1_IsEnabledClock\n
4271 * APB1LENR UART7EN LL_C1_APB1_GRP1_IsEnabledClock\n
4272 * APB1LENR UART8EN LL_C1_APB1_GRP1_IsEnabledClock
4273 * @param Periphs This parameter can be a combination of the following values:
4274 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
4275 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
4276 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
4277 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
4278 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
4279 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
4280 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
4281 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
4282 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
4283 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
4284 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
4285 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
4286 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
4287 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
4288 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
4289 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
4290 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
4291 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
4292 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
4293 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
4294 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
4295 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
4296 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
4297 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
4298 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
4299 *
4300 * (*) value not defined in all devices.
4301 * @retval uint32_t
4302 */
4303 __STATIC_INLINE uint32_t LL_C1_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
4304 {
4305 return ((READ_BIT(RCC_C1->APB1LENR, Periphs) == Periphs)?1U:0U);
4306 }
4307
4308 /**
4309 * @brief Disable C1 APB1 peripherals clock.
4310 * @rmtoll APB1LENR TIM2EN LL_C1_APB1_GRP1_DisableClock\n
4311 * APB1LENR TIM3EN LL_C1_APB1_GRP1_DisableClock\n
4312 * APB1LENR TIM4EN LL_C1_APB1_GRP1_DisableClock\n
4313 * APB1LENR TIM5EN LL_C1_APB1_GRP1_DisableClock\n
4314 * APB1LENR TIM6EN LL_C1_APB1_GRP1_DisableClock\n
4315 * APB1LENR TIM7EN LL_C1_APB1_GRP1_DisableClock\n
4316 * APB1LENR TIM12EN LL_C1_APB1_GRP1_DisableClock\n
4317 * APB1LENR TIM13EN LL_C1_APB1_GRP1_DisableClock\n
4318 * APB1LENR TIM14EN LL_C1_APB1_GRP1_DisableClock\n
4319 * APB1LENR LPTIM1EN LL_C1_APB1_GRP1_DisableClock\n
4320 * APB1LENR WWDG2EN LL_C1_APB1_GRP1_DisableClock\n (*)
4321 * APB1LENR SPI2EN LL_C1_APB1_GRP1_DisableClock\n
4322 * APB1LENR SPI3EN LL_C1_APB1_GRP1_DisableClock\n
4323 * APB1LENR SPDIFRXEN LL_C1_APB1_GRP1_DisableClock\n
4324 * APB1LENR USART2EN LL_C1_APB1_GRP1_DisableClock\n
4325 * APB1LENR USART3EN LL_C1_APB1_GRP1_DisableClock\n
4326 * APB1LENR UART4EN LL_C1_APB1_GRP1_DisableClock\n
4327 * APB1LENR UART5EN LL_C1_APB1_GRP1_DisableClock\n
4328 * APB1LENR I2C1EN LL_C1_APB1_GRP1_DisableClock\n
4329 * APB1LENR I2C2EN LL_C1_APB1_GRP1_DisableClock\n
4330 * APB1LENR I2C3EN LL_C1_APB1_GRP1_DisableClock\n
4331 * APB1LENR CECEN LL_C1_APB1_GRP1_DisableClock\n
4332 * APB1LENR DAC12EN LL_C1_APB1_GRP1_DisableClock\n
4333 * APB1LENR UART7EN LL_C1_APB1_GRP1_DisableClock\n
4334 * APB1LENR UART8EN LL_C1_APB1_GRP1_DisableClock
4335 * @param Periphs This parameter can be a combination of the following values:
4336 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
4337 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
4338 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
4339 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
4340 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
4341 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
4342 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
4343 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
4344 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
4345 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
4346 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
4347 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
4348 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
4349 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
4350 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
4351 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
4352 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
4353 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
4354 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
4355 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
4356 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
4357 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
4358 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
4359 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
4360 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
4361 *
4362 * (*) value not defined in all devices.
4363 * @retval uint32_t
4364 */
4365 __STATIC_INLINE void LL_C1_APB1_GRP1_DisableClock(uint32_t Periphs)
4366 {
4367 CLEAR_BIT(RCC_C1->APB1LENR, Periphs);
4368 }
4369
4370 /**
4371 * @brief Enable C1 APB1 peripherals clock during Low Power (Sleep) mode.
4372 * @rmtoll APB1LLPENR TIM2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4373 * APB1LLPENR TIM3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4374 * APB1LLPENR TIM4LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4375 * APB1LLPENR TIM5LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4376 * APB1LLPENR TIM6LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4377 * APB1LLPENR TIM7LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4378 * APB1LLPENR TIM12LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4379 * APB1LLPENR TIM13LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4380 * APB1LLPENR TIM14LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4381 * APB1LLPENR LPTIM1LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4382 * APB1LLPENR WWDG2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n (*)
4383 * APB1LLPENR SPI2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4384 * APB1LLPENR SPI3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4385 * APB1LLPENR SPDIFRXLPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4386 * APB1LLPENR USART2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4387 * APB1LLPENR USART3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4388 * APB1LLPENR UART4LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4389 * APB1LLPENR UART5LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4390 * APB1LLPENR I2C1LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4391 * APB1LLPENR I2C2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4392 * APB1LLPENR I2C3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4393 * APB1LLPENR CECLPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4394 * APB1LLPENR DAC12LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4395 * APB1LLPENR UART7LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4396 * APB1LLPENR UART8LPEN LL_C1_APB1_GRP1_EnableClockSleep
4397 * @param Periphs This parameter can be a combination of the following values:
4398 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
4399 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
4400 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
4401 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
4402 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
4403 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
4404 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
4405 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
4406 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
4407 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
4408 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
4409 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
4410 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
4411 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
4412 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
4413 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
4414 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
4415 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
4416 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
4417 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
4418 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
4419 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
4420 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
4421 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
4422 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
4423 *
4424 * (*) value not defined in all devices.
4425 * @retval None
4426 */
4427 __STATIC_INLINE void LL_C1_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
4428 {
4429 __IO uint32_t tmpreg;
4430 SET_BIT(RCC_C1->APB1LLPENR, Periphs);
4431 /* Delay after an RCC peripheral clock enabling */
4432 tmpreg = READ_BIT(RCC_C1->APB1LLPENR, Periphs);
4433 (void)tmpreg;
4434 }
4435
4436 /**
4437 * @brief Disable C1 APB1 peripherals clock during Low Power (Sleep) mode.
4438 * @rmtoll APB1LLPENR TIM2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4439 * APB1LLPENR TIM3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4440 * APB1LLPENR TIM4LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4441 * APB1LLPENR TIM5LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4442 * APB1LLPENR TIM6LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4443 * APB1LLPENR TIM7LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4444 * APB1LLPENR TIM12LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4445 * APB1LLPENR TIM13LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4446 * APB1LLPENR TIM14LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4447 * APB1LLPENR LPTIM1LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4448 * APB1LLPENR WWDG2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n (*)
4449 * APB1LLPENR SPI2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4450 * APB1LLPENR SPI3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4451 * APB1LLPENR SPDIFRXLPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4452 * APB1LLPENR USART2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4453 * APB1LLPENR USART3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4454 * APB1LLPENR UART4LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4455 * APB1LLPENR UART5LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4456 * APB1LLPENR I2C1LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4457 * APB1LLPENR I2C2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4458 * APB1LLPENR I2C3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4459 * APB1LLPENR CECLPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4460 * APB1LLPENR DAC12LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4461 * APB1LLPENR UART7LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4462 * APB1LLPENR UART8LPEN LL_C1_APB1_GRP1_DisableClockSleep
4463 * @param Periphs This parameter can be a combination of the following values:
4464 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
4465 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
4466 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
4467 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
4468 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
4469 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
4470 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
4471 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
4472 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
4473 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
4474 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
4475 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
4476 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
4477 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
4478 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
4479 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
4480 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
4481 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
4482 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
4483 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
4484 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
4485 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
4486 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
4487 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
4488 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
4489 *
4490 * (*) value not defined in all devices.
4491 * @retval None
4492 */
4493 __STATIC_INLINE void LL_C1_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
4494 {
4495 CLEAR_BIT(RCC_C1->APB1LLPENR, Periphs);
4496 }
4497
4498 /**
4499 * @brief Enable C1 APB1 peripherals clock.
4500 * @rmtoll APB1HENR CRSEN LL_C1_APB1_GRP2_EnableClock\n
4501 * APB1HENR SWPMIEN LL_C1_APB1_GRP2_EnableClock\n
4502 * APB1HENR OPAMPEN LL_C1_APB1_GRP2_EnableClock\n
4503 * APB1HENR MDIOSEN LL_C1_APB1_GRP2_EnableClock\n
4504 * APB1HENR FDCANEN LL_C1_APB1_GRP2_EnableClock
4505 * @param Periphs This parameter can be a combination of the following values:
4506 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
4507 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
4508 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
4509 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
4510 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
4511 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
4512 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
4513 *
4514 * (*) value not defined in all devices.
4515 * @retval None
4516 */
4517 __STATIC_INLINE void LL_C1_APB1_GRP2_EnableClock(uint32_t Periphs)
4518 {
4519 __IO uint32_t tmpreg;
4520 SET_BIT(RCC_C1->APB1HENR, Periphs);
4521 /* Delay after an RCC peripheral clock enabling */
4522 tmpreg = READ_BIT(RCC_C1->APB1HENR, Periphs);
4523 (void)tmpreg;
4524 }
4525
4526 /**
4527 * @brief Check if C1 APB1 peripheral clock is enabled or not
4528 * @rmtoll APB1HENR CRSEN LL_C1_APB1_GRP2_IsEnabledClock\n
4529 * APB1HENR SWPMIEN LL_C1_APB1_GRP2_IsEnabledClock\n
4530 * APB1HENR OPAMPEN LL_C1_APB1_GRP2_IsEnabledClock\n
4531 * APB1HENR MDIOSEN LL_C1_APB1_GRP2_IsEnabledClock\n
4532 * APB1HENR FDCANEN LL_C1_APB1_GRP2_IsEnabledClock
4533 * @param Periphs This parameter can be a combination of the following values:
4534 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
4535 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
4536 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
4537 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
4538 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
4539 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
4540 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
4541 *
4542 * (*) value not defined in all devices.
4543 * @retval uint32_t
4544 */
4545 __STATIC_INLINE uint32_t LL_C1_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
4546 {
4547 return ((READ_BIT(RCC_C1->APB1HENR, Periphs) == Periphs)?1U:0U);
4548 }
4549
4550 /**
4551 * @brief Disable C1 APB1 peripherals clock.
4552 * @rmtoll APB1HENR CRSEN LL_C1_APB1_GRP2_DisableClock\n
4553 * APB1HENR SWPMIEN LL_C1_APB1_GRP2_DisableClock\n
4554 * APB1HENR OPAMPEN LL_C1_APB1_GRP2_DisableClock\n
4555 * APB1HENR MDIOSEN LL_C1_APB1_GRP2_DisableClock\n
4556 * APB1HENR FDCANEN LL_C1_APB1_GRP2_DisableClock
4557 * @param Periphs This parameter can be a combination of the following values:
4558 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
4559 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
4560 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
4561 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
4562 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
4563 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
4564 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
4565 *
4566 * (*) value not defined in all devices.
4567 * @retval None
4568 */
4569 __STATIC_INLINE void LL_C1_APB1_GRP2_DisableClock(uint32_t Periphs)
4570 {
4571 CLEAR_BIT(RCC_C1->APB1HENR, Periphs);
4572 }
4573
4574 /**
4575 * @brief Enable C1 APB1 peripherals clock during Low Power (Sleep) mode.
4576 * @rmtoll APB1HLPENR CRSLPEN LL_C1_APB1_GRP2_EnableClockSleep\n
4577 * APB1HLPENR SWPMILPEN LL_C1_APB1_GRP2_EnableClockSleep\n
4578 * APB1HLPENR OPAMPLPEN LL_C1_APB1_GRP2_EnableClockSleep\n
4579 * APB1HLPENR MDIOSLPEN LL_C1_APB1_GRP2_EnableClockSleep\n
4580 * APB1HLPENR FDCANLPEN LL_C1_APB1_GRP2_EnableClockSleep
4581 * @param Periphs This parameter can be a combination of the following values:
4582 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
4583 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
4584 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
4585 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
4586 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
4587 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
4588 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
4589 *
4590 * (*) value not defined in all devices.
4591 * @retval None
4592 */
4593 __STATIC_INLINE void LL_C1_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
4594 {
4595 __IO uint32_t tmpreg;
4596 SET_BIT(RCC_C1->APB1HLPENR, Periphs);
4597 /* Delay after an RCC peripheral clock enabling */
4598 tmpreg = READ_BIT(RCC_C1->APB1HLPENR, Periphs);
4599 (void)tmpreg;
4600 }
4601
4602 /**
4603 * @brief Disable C1 APB1 peripherals clock during Low Power (Sleep) mode.
4604 * @rmtoll APB1HLPENR CRSLPEN LL_C1_APB1_GRP2_DisableClockSleep\n
4605 * APB1HLPENR SWPMILPEN LL_C1_APB1_GRP2_DisableClockSleep\n
4606 * APB1HLPENR OPAMPLPEN LL_C1_APB1_GRP2_DisableClockSleep\n
4607 * APB1HLPENR MDIOSLPEN LL_C1_APB1_GRP2_DisableClockSleep\n
4608 * APB1HLPENR FDCANLPEN LL_C1_APB1_GRP2_DisableClockSleep
4609 * @param Periphs This parameter can be a combination of the following values:
4610 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
4611 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
4612 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
4613 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
4614 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
4615 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
4616 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
4617 *
4618 * (*) value not defined in all devices.
4619 * @retval None
4620 */
4621 __STATIC_INLINE void LL_C1_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
4622 {
4623 CLEAR_BIT(RCC_C1->APB1HLPENR, Periphs);
4624 }
4625
4626 /**
4627 * @}
4628 */
4629
4630 /** @addtogroup BUS_LL_EF_APB2 APB2
4631 * @{
4632 */
4633
4634 /**
4635 * @brief Enable C1 APB2 peripherals clock.
4636 * @rmtoll APB2ENR TIM1EN LL_C1_APB2_GRP1_EnableClock\n
4637 * APB2ENR TIM8EN LL_C1_APB2_GRP1_EnableClock\n
4638 * APB2ENR USART1EN LL_C1_APB2_GRP1_EnableClock\n
4639 * APB2ENR USART6EN LL_C1_APB2_GRP1_EnableClock\n
4640 * APB2ENR UART9EN LL_C1_APB2_GRP1_EnableClock\n (*)
4641 * APB2ENR USART10EN LL_C1_APB2_GRP1_EnableClock\n (*)
4642 * APB2ENR SPI1EN LL_C1_APB2_GRP1_EnableClock\n
4643 * APB2ENR SPI4EN LL_C1_APB2_GRP1_EnableClock\n
4644 * APB2ENR TIM15EN LL_C1_APB2_GRP1_EnableClock\n
4645 * APB2ENR TIM16EN LL_C1_APB2_GRP1_EnableClock\n
4646 * APB2ENR TIM17EN LL_C1_APB2_GRP1_EnableClock\n
4647 * APB2ENR SPI5EN LL_C1_APB2_GRP1_EnableClock\n
4648 * APB2ENR SAI1EN LL_C1_APB2_GRP1_EnableClock\n
4649 * APB2ENR SAI2EN LL_C1_APB2_GRP1_EnableClock\n
4650 * APB2ENR SAI3EN LL_C1_APB2_GRP1_EnableClock\n (*)
4651 * APB2ENR DFSDM1EN LL_C1_APB2_GRP1_EnableClock\n
4652 * APB2ENR HRTIMEN LL_C1_APB2_GRP1_EnableClock (*)
4653 * @param Periphs This parameter can be a combination of the following values:
4654 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
4655 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
4656 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
4657 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
4658 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
4659 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
4660 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
4661 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
4662 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
4663 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
4664 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
4665 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
4666 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
4667 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
4668 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
4669 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
4670 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
4671 *
4672 * (*) value not defined in all devices.
4673 * @retval None
4674 */
4675 __STATIC_INLINE void LL_C1_APB2_GRP1_EnableClock(uint32_t Periphs)
4676 {
4677 __IO uint32_t tmpreg;
4678 SET_BIT(RCC_C1->APB2ENR, Periphs);
4679 /* Delay after an RCC peripheral clock enabling */
4680 tmpreg = READ_BIT(RCC_C1->APB2ENR, Periphs);
4681 (void)tmpreg;
4682 }
4683
4684 /**
4685 * @brief Check if C1 APB2 peripheral clock is enabled or not
4686 * @rmtoll APB2ENR TIM1EN LL_C1_APB2_GRP1_IsEnabledClock\n
4687 * APB2ENR TIM8EN LL_C1_APB2_GRP1_IsEnabledClock\n
4688 * APB2ENR USART1EN LL_C1_APB2_GRP1_IsEnabledClock\n
4689 * APB2ENR USART6EN LL_C1_APB2_GRP1_IsEnabledClock\n
4690 * APB2ENR UART9EN LL_C1_APB2_GRP1_IsEnabledClock\n (*)
4691 * APB2ENR USART10EN LL_C1_APB2_GRP1_IsEnabledClock\n (*)
4692 * APB2ENR SPI1EN LL_C1_APB2_GRP1_IsEnabledClock\n
4693 * APB2ENR SPI4EN LL_C1_APB2_GRP1_IsEnabledClock\n
4694 * APB2ENR TIM15EN LL_C1_APB2_GRP1_IsEnabledClock\n
4695 * APB2ENR TIM16EN LL_C1_APB2_GRP1_IsEnabledClock\n
4696 * APB2ENR TIM17EN LL_C1_APB2_GRP1_IsEnabledClock\n
4697 * APB2ENR SPI5EN LL_C1_APB2_GRP1_IsEnabledClock\n
4698 * APB2ENR SAI1EN LL_C1_APB2_GRP1_IsEnabledClock\n
4699 * APB2ENR SAI2EN LL_C1_APB2_GRP1_IsEnabledClock\n
4700 * APB2ENR SAI3EN LL_C1_APB2_GRP1_IsEnabledClock\n (*)
4701 * APB2ENR DFSDM1EN LL_C1_APB2_GRP1_IsEnabledClock\n
4702 * APB2ENR HRTIMEN LL_C1_APB2_GRP1_IsEnabledClock (*)
4703 * @param Periphs This parameter can be a combination of the following values:
4704 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
4705 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
4706 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
4707 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
4708 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
4709 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
4710 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
4711 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
4712 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
4713 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
4714 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
4715 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
4716 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
4717 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
4718 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
4719 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
4720 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
4721 *
4722 * (*) value not defined in all devices.
4723 * @retval None
4724 */
4725 __STATIC_INLINE uint32_t LL_C1_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
4726 {
4727 return ((READ_BIT(RCC_C1->APB2ENR, Periphs) == Periphs)?1U:0U);
4728 }
4729
4730 /**
4731 * @brief Disable C1 APB2 peripherals clock.
4732 * @rmtoll APB2ENR TIM1EN LL_C1_APB2_GRP1_DisableClock\n
4733 * APB2ENR TIM8EN LL_C1_APB2_GRP1_DisableClock\n
4734 * APB2ENR USART1EN LL_C1_APB2_GRP1_DisableClock\n
4735 * APB2ENR USART6EN LL_C1_APB2_GRP1_DisableClock\n
4736 * APB2ENR UART9EN LL_C1_APB2_GRP1_DisableClock\n (*)
4737 * APB2ENR USART10EN LL_C1_APB2_GRP1_DisableClock\n (*)
4738 * APB2ENR SPI1EN LL_C1_APB2_GRP1_DisableClock\n
4739 * APB2ENR SPI4EN LL_C1_APB2_GRP1_DisableClock\n
4740 * APB2ENR TIM15EN LL_C1_APB2_GRP1_DisableClock\n
4741 * APB2ENR TIM16EN LL_C1_APB2_GRP1_DisableClock\n
4742 * APB2ENR TIM17EN LL_C1_APB2_GRP1_DisableClock\n
4743 * APB2ENR SPI5EN LL_C1_APB2_GRP1_DisableClock\n
4744 * APB2ENR SAI1EN LL_C1_APB2_GRP1_DisableClock\n
4745 * APB2ENR SAI2EN LL_C1_APB2_GRP1_DisableClock\n
4746 * APB2ENR SAI3EN LL_C1_APB2_GRP1_DisableClock\n (*)
4747 * APB2ENR DFSDM1EN LL_C1_APB2_GRP1_DisableClock\n
4748 * APB2ENR HRTIMEN LL_C1_APB2_GRP1_DisableClock (*)
4749 * @param Periphs This parameter can be a combination of the following values:
4750 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
4751 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
4752 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
4753 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
4754 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
4755 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
4756 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
4757 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
4758 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
4759 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
4760 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
4761 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
4762 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
4763 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
4764 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
4765 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
4766 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
4767 *
4768 * (*) value not defined in all devices.
4769 * @retval None
4770 */
4771 __STATIC_INLINE void LL_C1_APB2_GRP1_DisableClock(uint32_t Periphs)
4772 {
4773 CLEAR_BIT(RCC_C1->APB2ENR, Periphs);
4774 }
4775
4776 /**
4777 * @brief Enable C1 APB2 peripherals clock during Low Power (Sleep) mode.
4778 * @rmtoll APB2LPENR TIM1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4779 * APB2LPENR TIM8LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4780 * APB2LPENR USART1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4781 * APB2LPENR USART6LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4782 * APB2ENR UART9EN LL_C1_APB2_GRP1_EnableClockSleep\n (*)
4783 * APB2ENR USART10EN LL_C1_APB2_GRP1_EnableClockSleep\n (*)
4784 * APB2LPENR SPI1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4785 * APB2LPENR SPI4LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4786 * APB2LPENR TIM15LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4787 * APB2LPENR TIM16LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4788 * APB2LPENR TIM17LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4789 * APB2LPENR SPI5LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4790 * APB2LPENR SAI1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4791 * APB2LPENR SAI2LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4792 * APB2LPENR SAI3LPEN LL_C1_APB2_GRP1_EnableClockSleep\n (*)
4793 * APB2LPENR DFSDM1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4794 * APB2LPENR HRTIMLPEN LL_C1_APB2_GRP1_EnableClockSleep (*)
4795 * @param Periphs This parameter can be a combination of the following values:
4796 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
4797 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
4798 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
4799 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
4800 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
4801 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
4802 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
4803 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
4804 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
4805 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
4806 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
4807 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
4808 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
4809 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
4810 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
4811 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
4812 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
4813 *
4814 * (*) value not defined in all devices.
4815 * @retval None
4816 */
4817 __STATIC_INLINE void LL_C1_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
4818 {
4819 __IO uint32_t tmpreg;
4820 SET_BIT(RCC_C1->APB2LPENR, Periphs);
4821 /* Delay after an RCC peripheral clock enabling */
4822 tmpreg = READ_BIT(RCC_C1->APB2LPENR, Periphs);
4823 (void)tmpreg;
4824 }
4825
4826 /**
4827 * @brief Disable C1 APB2 peripherals clock during Low Power (Sleep) mode.
4828 * @rmtoll APB2LPENR TIM1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4829 * APB2LPENR TIM8LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4830 * APB2LPENR USART1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4831 * APB2LPENR UART9LPEN LL_C1_APB2_GRP1_DisableClockSleep\n (*)
4832 * APB2LPENR USART10LPEN LL_C1_APB2_GRP1_DisableClockSleep\n (*)
4833 * APB2LPENR USART6LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4834 * APB2LPENR SPI1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4835 * APB2LPENR SPI4LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4836 * APB2LPENR TIM15LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4837 * APB2LPENR TIM16LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4838 * APB2LPENR TIM17LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4839 * APB2LPENR SPI5LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4840 * APB2LPENR SAI1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4841 * APB2LPENR SAI2LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4842 * APB2LPENR SAI3LPEN LL_C1_APB2_GRP1_DisableClockSleep\n (*)
4843 * APB2LPENR DFSDM1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4844 * APB2LPENR HRTIMLPEN LL_C1_APB2_GRP1_DisableClockSleep (*)
4845 * @param Periphs This parameter can be a combination of the following values:
4846 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
4847 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
4848 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
4849 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
4850 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
4851 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
4852 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
4853 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
4854 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
4855 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
4856 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
4857 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
4858 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
4859 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
4860 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
4861 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
4862 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
4863 *
4864 * (*) value not defined in all devices.
4865 * @retval None
4866 */
4867 __STATIC_INLINE void LL_C1_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
4868 {
4869 CLEAR_BIT(RCC_C1->APB2LPENR, Periphs);
4870 }
4871
4872 /**
4873 * @}
4874 */
4875
4876 /** @addtogroup BUS_LL_EF_APB4 APB4
4877 * @{
4878 */
4879
4880 /**
4881 * @brief Enable C1 APB4 peripherals clock.
4882 * @rmtoll APB4ENR SYSCFGEN LL_C1_APB4_GRP1_EnableClock\n
4883 * APB4ENR LPUART1EN LL_C1_APB4_GRP1_EnableClock\n
4884 * APB4ENR SPI6EN LL_C1_APB4_GRP1_EnableClock\n
4885 * APB4ENR I2C4EN LL_C1_APB4_GRP1_EnableClock\n
4886 * APB4ENR LPTIM2EN LL_C1_APB4_GRP1_EnableClock\n
4887 * APB4ENR LPTIM3EN LL_C1_APB4_GRP1_EnableClock\n
4888 * APB4ENR LPTIM4EN LL_C1_APB4_GRP1_EnableClock\n (*)
4889 * APB4ENR LPTIM5EN LL_C1_APB4_GRP1_EnableClock\n (*)
4890 * APB4ENR DAC2EN LL_C1_APB4_GRP1_EnableClock\n (*)
4891 * APB4ENR COMP12EN LL_C1_APB4_GRP1_EnableClock\n
4892 * APB4ENR VREFEN LL_C1_APB4_GRP1_EnableClock\n
4893 * APB4ENR RTCAPBEN LL_C1_APB4_GRP1_EnableClock\n
4894 * APB4ENR SAI4EN LL_C1_APB4_GRP1_EnableClock\n (*)
4895 * APB4ENR DTSEN LL_C1_APB4_GRP1_EnableClock\n (*)
4896 * APB4ENR DFSDM2EN LL_C1_APB4_GRP1_EnableClock (*)
4897 * @param Periphs This parameter can be a combination of the following values:
4898 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
4899 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
4900 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
4901 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
4902 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
4903 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
4904 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
4905 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
4906 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
4907 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
4908 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
4909 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
4910 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
4911 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
4912 *
4913 * (*) value not defined in all devices.
4914 * @retval None
4915 */
4916 __STATIC_INLINE void LL_C1_APB4_GRP1_EnableClock(uint32_t Periphs)
4917 {
4918 __IO uint32_t tmpreg;
4919 SET_BIT(RCC_C1->APB4ENR, Periphs);
4920 /* Delay after an RCC peripheral clock enabling */
4921 tmpreg = READ_BIT(RCC_C1->APB4ENR, Periphs);
4922 (void)tmpreg;
4923 }
4924
4925 /**
4926 * @brief Check if C1 APB4 peripheral clock is enabled or not
4927 * @rmtoll APB4ENR SYSCFGEN LL_C1_APB4_GRP1_IsEnabledClock\n
4928 * APB4ENR LPUART1EN LL_C1_APB4_GRP1_IsEnabledClock\n
4929 * APB4ENR SPI6EN LL_C1_APB4_GRP1_IsEnabledClock\n
4930 * APB4ENR I2C4EN LL_C1_APB4_GRP1_IsEnabledClock\n
4931 * APB4ENR LPTIM2EN LL_C1_APB4_GRP1_IsEnabledClock\n
4932 * APB4ENR LPTIM3EN LL_C1_APB4_GRP1_IsEnabledClock\n
4933 * APB4ENR LPTIM4EN LL_C1_APB4_GRP1_IsEnabledClock\n (*)
4934 * APB4ENR LPTIM5EN LL_C1_APB4_GRP1_IsEnabledClock\n (*)
4935 * APB4ENR COMP12EN LL_C1_APB4_GRP1_IsEnabledClock\n
4936 * APB4ENR VREFEN LL_C1_APB4_GRP1_IsEnabledClock\n
4937 * APB4ENR RTCAPBEN LL_C1_APB4_GRP1_IsEnabledClock\n
4938 * APB4ENR SAI4EN LL_C1_APB4_GRP1_IsEnabledClock\n (*)
4939 * APB4ENR DTSEN LL_C1_APB4_GRP1_IsEnabledClock\n (*)
4940 * APB4ENR DFSDM2EN LL_C1_APB4_GRP1_IsEnabledClock (*)
4941 * @param Periphs This parameter can be a combination of the following values:
4942 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
4943 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
4944 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
4945 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
4946 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
4947 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
4948 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
4949 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
4950 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
4951 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
4952 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
4953 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
4954 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
4955 *
4956 * (*) value not defined in all devices.
4957 * @retval uint32_t
4958 */
4959 __STATIC_INLINE uint32_t LL_C1_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
4960 {
4961 return ((READ_BIT(RCC_C1->APB4ENR, Periphs) == Periphs)?1U:0U);
4962 }
4963
4964 /**
4965 * @brief Disable C1 APB4 peripherals clock.
4966 * @rmtoll APB4ENR SYSCFGEN LL_C1_APB4_GRP1_DisableClock\n
4967 * APB4ENR LPUART1EN LL_C1_APB4_GRP1_DisableClock\n
4968 * APB4ENR SPI6EN LL_C1_APB4_GRP1_DisableClock\n
4969 * APB4ENR I2C4EN LL_C1_APB4_GRP1_DisableClock\n
4970 * APB4ENR LPTIM2EN LL_C1_APB4_GRP1_DisableClock\n
4971 * APB4ENR LPTIM3EN LL_C1_APB4_GRP1_DisableClock\n
4972 * APB4ENR LPTIM4EN LL_C1_APB4_GRP1_DisableClock\n (*)
4973 * APB4ENR LPTIM5EN LL_C1_APB4_GRP1_DisableClock\n (*)
4974 * APB4ENR COMP12EN LL_C1_APB4_GRP1_DisableClock\n
4975 * APB4ENR VREFEN LL_C1_APB4_GRP1_DisableClock\n
4976 * APB4ENR RTCAPBEN LL_C1_APB4_GRP1_DisableClock\n
4977 * APB4ENR SAI4EN LL_C1_APB4_GRP1_DisableClock\n (*)
4978 * APB4ENR DTSEN LL_C1_APB4_GRP1_DisableClock\n (*)
4979 * APB4ENR DFSDM2EN LL_C1_APB4_GRP1_DisableClock (*)
4980 * @param Periphs This parameter can be a combination of the following values:
4981 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
4982 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
4983 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
4984 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
4985 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
4986 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
4987 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
4988 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
4989 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
4990 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
4991 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
4992 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
4993 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
4994 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
4995 *
4996 * (*) value not defined in all devices.
4997 * @retval None
4998 */
4999 __STATIC_INLINE void LL_C1_APB4_GRP1_DisableClock(uint32_t Periphs)
5000 {
5001 CLEAR_BIT(RCC_C1->APB4ENR, Periphs);
5002 }
5003
5004 /**
5005 * @brief Enable C1 APB4 peripherals clock during Low Power (Sleep) mode.
5006 * @rmtoll APB4LPENR SYSCFGLPEN LL_C1_APB4_GRP1_EnableClockSleep\n
5007 * APB4LPENR LPUART1LPEN LL_C1_APB4_GRP1_EnableClockSleep\n
5008 * APB4LPENR SPI6LPEN LL_C1_APB4_GRP1_EnableClockSleep\n
5009 * APB4LPENR I2C4LPEN LL_C1_APB4_GRP1_EnableClockSleep\n
5010 * APB4LPENR LPTIM2LPEN LL_C1_APB4_GRP1_EnableClockSleep\n
5011 * APB4LPENR LPTIM3LPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*)
5012 * APB4LPENR LPTIM4LPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*)
5013 * APB4LPENR LPTIM5LPEN LL_C1_APB4_GRP1_EnableClockSleep\n
5014 * APB4LPENR COMP12LPEN LL_C1_APB4_GRP1_EnableClockSleep\n
5015 * APB4LPENR VREFLPEN LL_C1_APB4_GRP1_EnableClockSleep\n
5016 * APB4LPENR RTCAPBLPEN LL_C1_APB4_GRP1_EnableClockSleep\n
5017 * APB4LPENR SAI4LPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*)
5018 * APB4ENR DTSLPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*)
5019 * APB4ENR DFSDM2LPEN LL_C1_APB4_GRP1_EnableClockSleep (*)
5020 * @param Periphs This parameter can be a combination of the following values:
5021 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
5022 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
5023 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
5024 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
5025 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
5026 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
5027 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
5028 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
5029 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
5030 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
5031 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
5032 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
5033 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
5034 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
5035 *
5036 * (*) value not defined in all devices.
5037 * @retval None
5038 */
5039 __STATIC_INLINE void LL_C1_APB4_GRP1_EnableClockSleep(uint32_t Periphs)
5040 {
5041 __IO uint32_t tmpreg;
5042 SET_BIT(RCC_C1->APB4LPENR, Periphs);
5043 /* Delay after an RCC peripheral clock enabling */
5044 tmpreg = READ_BIT(RCC_C1->APB4LPENR, Periphs);
5045 (void)tmpreg;
5046 }
5047
5048 /**
5049 * @brief Disable C1 APB4 peripherals clock during Low Power (Sleep) mode.
5050 * @rmtoll APB4LPENR SYSCFGLPEN LL_C1_APB4_GRP1_DisableClockSleep\n
5051 * APB4LPENR LPUART1LPEN LL_C1_APB4_GRP1_DisableClockSleep\n
5052 * APB4LPENR SPI6LPEN LL_C1_APB4_GRP1_DisableClockSleep\n
5053 * APB4LPENR I2C4LPEN LL_C1_APB4_GRP1_DisableClockSleep\n
5054 * APB4LPENR LPTIM2LPEN LL_C1_APB4_GRP1_DisableClockSleep\n
5055 * APB4LPENR LPTIM3LPEN LL_C1_APB4_GRP1_DisableClockSleep\n
5056 * APB4LPENR LPTIM4LPEN LL_C1_APB4_GRP1_DisableClockSleep\n
5057 * APB4LPENR LPTIM5LPEN LL_C1_APB4_GRP1_DisableClockSleep\n
5058 * APB4LPENR COMP12LPEN LL_C1_APB4_GRP1_DisableClockSleep\n
5059 * APB4LPENR VREFLPEN LL_C1_APB4_GRP1_DisableClockSleep\n
5060 * APB4LPENR RTCAPBLPEN LL_C1_APB4_GRP1_DisableClockSleep\n
5061 * APB4LPENR SAI4LPEN LL_C1_APB4_GRP1_DisableClockSleep\n (*)
5062 * APB4ENR DTSLPEN LL_C1_APB4_GRP1_DisableClockSleep\n (*)
5063 * APB4ENR DFSDM2LPEN LL_C1_APB4_GRP1_DisableClockSleep (*)
5064 * @param Periphs This parameter can be a combination of the following values:
5065 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
5066 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
5067 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
5068 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
5069 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
5070 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
5071 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
5072 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
5073 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
5074 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
5075 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
5076 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
5077 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
5078 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
5079 *
5080 * (*) value not defined in all devices.
5081 * @retval None
5082 */
5083 __STATIC_INLINE void LL_C1_APB4_GRP1_DisableClockSleep(uint32_t Periphs)
5084 {
5085 CLEAR_BIT(RCC_C1->APB4LPENR, Periphs);
5086 }
5087
5088 /**
5089 * @}
5090 */
5091
5092 /** @addtogroup BUS_LL_EF_AHB3 AHB3
5093 * @{
5094 */
5095
5096 /**
5097 * @brief Enable C2 AHB3 peripherals clock.
5098 * @rmtoll AHB3ENR MDMAEN LL_C2_AHB3_GRP1_EnableClock\n
5099 * AHB3ENR DMA2DEN LL_C2_AHB3_GRP1_EnableClock\n
5100 * AHB3ENR JPGDECEN LL_C2_AHB3_GRP1_EnableClock\n
5101 * AHB3ENR FMCEN LL_C2_AHB3_GRP1_EnableClock\n
5102 * AHB3ENR QSPIEN LL_C2_AHB3_GRP1_EnableClock\n
5103 * AHB3ENR SDMMC1EN LL_C2_AHB3_GRP1_EnableClock\n
5104 * AHB3ENR FLASHEN LL_C2_AHB3_GRP1_EnableClock\n
5105 * AHB3ENR DTCM1EN LL_C2_AHB3_GRP1_EnableClock\n
5106 * AHB3ENR DTCM2EN LL_C2_AHB3_GRP1_EnableClock\n
5107 * AHB3ENR ITCMEN LL_C2_AHB3_GRP1_EnableClock\n
5108 * AHB3ENR AXISRAMEN LL_C2_AHB3_GRP1_EnableClock
5109 * @param Periphs This parameter can be a combination of the following values:
5110 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
5111 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
5112 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
5113 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
5114 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
5115 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
5116 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
5117 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
5118 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
5119 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
5120 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
5121 * @retval None
5122 */
5123 __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs)
5124 {
5125 __IO uint32_t tmpreg;
5126 SET_BIT(RCC_C2->AHB3ENR, Periphs);
5127 /* Delay after an RCC peripheral clock enabling */
5128 tmpreg = READ_BIT(RCC_C2->AHB3ENR, Periphs);
5129 (void)tmpreg;
5130 }
5131
5132 /**
5133 * @brief Check if C2 AHB3 peripheral clock is enabled or not
5134 * @rmtoll AHB3ENR MDMAEN LL_C2_AHB3_GRP1_IsEnabledClock\n
5135 * AHB3ENR DMA2DEN LL_C2_AHB3_GRP1_IsEnabledClock\n
5136 * AHB3ENR JPGDECEN LL_C2_AHB3_GRP1_IsEnabledClock\n
5137 * AHB3ENR FMCEN LL_C2_AHB3_GRP1_IsEnabledClock\n
5138 * AHB3ENR QSPIEN LL_C2_AHB3_GRP1_IsEnabledClock\n
5139 * AHB3ENR SDMMC1EN LL_C2_AHB3_GRP1_IsEnabledClock\n
5140 * AHB3ENR FLASHEN LL_C2_AHB3_GRP1_IsEnabledClock\n
5141 * AHB3ENR DTCM1EN LL_C2_AHB3_GRP1_IsEnabledClock\n
5142 * AHB3ENR DTCM2EN LL_C2_AHB3_GRP1_IsEnabledClock\n
5143 * AHB3ENR ITCMEN LL_C2_AHB3_GRP1_IsEnabledClock\n
5144 * AHB3ENR AXISRAMEN LL_C2_AHB3_GRP1_IsEnabledClock
5145 * @param Periphs This parameter can be a combination of the following values:
5146 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
5147 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
5148 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
5149 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
5150 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
5151 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
5152 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
5153 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
5154 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
5155 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
5156 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
5157 * @retval uint32_t
5158 */
5159 __STATIC_INLINE uint32_t LL_C2_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
5160 {
5161 return ((READ_BIT(RCC_C2->AHB3ENR, Periphs) == Periphs)?1U:0U);
5162 }
5163
5164 /**
5165 * @brief Disable C2 AHB3 peripherals clock.
5166 * @rmtoll AHB3ENR MDMAEN LL_C2_AHB3_GRP1_DisableClock\n
5167 * AHB3ENR DMA2DEN LL_C2_AHB3_GRP1_DisableClock\n
5168 * AHB3ENR JPGDECEN LL_C2_AHB3_GRP1_DisableClock\n
5169 * AHB3ENR FMCEN LL_C2_AHB3_GRP1_DisableClock\n
5170 * AHB3ENR QSPIEN LL_C2_AHB3_GRP1_DisableClock\n
5171 * AHB3ENR SDMMC1EN LL_C2_AHB3_GRP1_DisableClock\n
5172 * AHB3ENR FLASHEN LL_C2_AHB3_GRP1_DisableClock\n
5173 * AHB3ENR DTCM1EN LL_C2_AHB3_GRP1_DisableClock\n
5174 * AHB3ENR DTCM2EN LL_C2_AHB3_GRP1_DisableClock\n
5175 * AHB3ENR ITCMEN LL_C2_AHB3_GRP1_DisableClock\n
5176 * AHB3ENR AXISRAMEN LL_C2_AHB3_GRP1_DisableClock
5177 * @param Periphs This parameter can be a combination of the following values:
5178 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
5179 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
5180 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
5181 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
5182 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
5183 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
5184 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
5185 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
5186 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
5187 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
5188 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
5189 * @retval None
5190 */
5191 __STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClock(uint32_t Periphs)
5192 {
5193 CLEAR_BIT(RCC_C2->AHB3ENR, Periphs);
5194 }
5195
5196 /**
5197 * @brief Enable C2 AHB3 peripherals clock during Low Power (Sleep) mode.
5198 * @rmtoll AHB3LPENR MDMALPEN LL_C2_AHB3_GRP1_EnableClockSleep\n
5199 * AHB3LPENR DMA2DLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n
5200 * AHB3LPENR JPGDECLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n
5201 * AHB3LPENR FMCLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n
5202 * AHB3LPENR QSPILPEN LL_C2_AHB3_GRP1_EnableClockSleep\n
5203 * AHB3LPENR SDMMC1LPEN LL_C2_AHB3_GRP1_EnableClockSleep\n
5204 * AHB3LPENR FLASHLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n
5205 * AHB3LPENR DTCM1LPEN LL_C2_AHB3_GRP1_EnableClockSleep\n
5206 * AHB3LPENR DTCM2LPEN LL_C2_AHB3_GRP1_EnableClockSleep\n
5207 * AHB3LPENR ITCMLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n
5208 * AHB3LPENR AXISRAMLPEN LL_C2_AHB3_GRP1_EnableClockSleep
5209 * @param Periphs This parameter can be a combination of the following values:
5210 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
5211 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
5212 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
5213 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
5214 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
5215 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
5216 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
5217 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
5218 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
5219 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
5220 * @retval None
5221 */
5222 __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
5223 {
5224 __IO uint32_t tmpreg;
5225 SET_BIT(RCC_C2->AHB3LPENR, Periphs);
5226 /* Delay after an RCC peripheral clock enabling */
5227 tmpreg = READ_BIT(RCC_C2->AHB3LPENR, Periphs);
5228 (void)tmpreg;
5229 }
5230
5231 /**
5232 * @brief Disable C2 AHB3 peripherals clock during Low Power (Sleep) mode.
5233 * @rmtoll AHB3LPENR MDMALPEN LL_C2_AHB3_GRP1_DisableClockSleep\n
5234 * AHB3LPENR DMA2DLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n
5235 * AHB3LPENR JPGDECLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n
5236 * AHB3LPENR FMCLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n
5237 * AHB3LPENR QSPILPEN LL_C2_AHB3_GRP1_DisableClockSleep\n
5238 * AHB3LPENR SDMMC1LPEN LL_C2_AHB3_GRP1_DisableClockSleep\n
5239 * AHB3LPENR FLASHLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n
5240 * AHB3LPENR DTCM1LPEN LL_C2_AHB3_GRP1_DisableClockSleep\n
5241 * AHB3LPENR DTCM2LPEN LL_C2_AHB3_GRP1_DisableClockSleep\n
5242 * AHB3LPENR ITCMLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n
5243 * AHB3LPENR AXISRAMLPEN LL_C2_AHB3_GRP1_DisableClockSleep
5244 * @param Periphs This parameter can be a combination of the following values:
5245 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
5246 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
5247 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
5248 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
5249 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
5250 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
5251 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
5252 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
5253 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
5254 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
5255 * @retval None
5256 */
5257 __STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
5258 {
5259 CLEAR_BIT(RCC_C2->AHB3LPENR, Periphs);
5260 }
5261
5262 /**
5263 * @}
5264 */
5265
5266 /** @addtogroup BUS_LL_EF_AHB1 AHB1
5267 * @{
5268 */
5269
5270 /**
5271 * @brief Enable C2 AHB1 peripherals clock.
5272 * @rmtoll AHB1ENR DMA1EN LL_C2_AHB1_GRP1_EnableClock\n
5273 * AHB1ENR DMA2EN LL_C2_AHB1_GRP1_EnableClock\n
5274 * AHB1ENR ADC12EN LL_C2_AHB1_GRP1_EnableClock\n
5275 * AHB1ENR ARTEN LL_C2_AHB1_GRP1_EnableClock\n
5276 * AHB1ENR ETH1MACEN LL_C2_AHB1_GRP1_EnableClock\n
5277 * AHB1ENR ETH1TXEN LL_C2_AHB1_GRP1_EnableClock\n
5278 * AHB1ENR ETH1RXEN LL_C2_AHB1_GRP1_EnableClock\n
5279 * AHB1ENR USB1OTGHSEN LL_C2_AHB1_GRP1_EnableClock\n
5280 * AHB1ENR USB1OTGHSULPIEN LL_C2_AHB1_GRP1_EnableClock\n
5281 * AHB1ENR USB2OTGHSEN LL_C2_AHB1_GRP1_EnableClock\n
5282 * AHB1ENR USB2OTGHSULPIEN LL_C2_AHB1_GRP1_EnableClock
5283 * @param Periphs This parameter can be a combination of the following values:
5284 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
5285 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
5286 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
5287 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
5288 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
5289 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
5290 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
5291 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
5292 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
5293 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
5294 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
5295 *
5296 * (*) value not defined in all devices.
5297 * @retval None
5298 */
5299 __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs)
5300 {
5301 __IO uint32_t tmpreg;
5302 SET_BIT(RCC_C2->AHB1ENR, Periphs);
5303 /* Delay after an RCC peripheral clock enabling */
5304 tmpreg = READ_BIT(RCC_C2->AHB1ENR, Periphs);
5305 (void)tmpreg;
5306 }
5307
5308 /**
5309 * @brief Check if C2 AHB1 peripheral clock is enabled or not
5310 * @rmtoll AHB1ENR DMA1EN LL_C2_AHB1_GRP1_IsEnabledClock\n
5311 * AHB1ENR DMA2EN LL_C2_AHB1_GRP1_IsEnabledClock\n
5312 * AHB1ENR ADC12EN LL_C2_AHB1_GRP1_IsEnabledClock\n
5313 * AHB1ENR ARTEN LL_C2_AHB1_GRP1_IsEnabledClock\n
5314 * AHB1ENR ETH1MACEN LL_C2_AHB1_GRP1_IsEnabledClock\n
5315 * AHB1ENR ETH1TXEN LL_C2_AHB1_GRP1_IsEnabledClock\n
5316 * AHB1ENR ETH1RXEN LL_C2_AHB1_GRP1_IsEnabledClock\n
5317 * AHB1ENR USB1OTGHSEN LL_C2_AHB1_GRP1_IsEnabledClock\n
5318 * AHB1ENR USB1OTGHSULPIEN LL_C2_AHB1_GRP1_IsEnabledClock\n
5319 * AHB1ENR USB2OTGHSEN LL_C2_AHB1_GRP1_IsEnabledClock\n
5320 * AHB1ENR USB2OTGHSULPIEN LL_C2_AHB1_GRP1_IsEnabledClock
5321 * @param Periphs This parameter can be a combination of the following values:
5322 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
5323 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
5324 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
5325 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
5326 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
5327 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
5328 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
5329 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
5330 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
5331 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
5332 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
5333 *
5334 * (*) value not defined in all devices.
5335 * @retval uint32_t
5336 */
5337 __STATIC_INLINE uint32_t LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
5338 {
5339 return ((READ_BIT(RCC_C2->AHB1ENR, Periphs) == Periphs)?1U:0U);
5340 }
5341
5342 /**
5343 * @brief Disable C2 AHB1 peripherals clock.
5344 * @rmtoll AHB1ENR DMA1EN LL_C2_AHB1_GRP1_DisableClock\n
5345 * AHB1ENR DMA2EN LL_C2_AHB1_GRP1_DisableClock\n
5346 * AHB1ENR ADC12EN LL_C2_AHB1_GRP1_DisableClock\n
5347 * AHB1ENR ARTEN LL_C2_AHB1_GRP1_DisableClock\n
5348 * AHB1ENR ETH1MACEN LL_C2_AHB1_GRP1_DisableClock\n
5349 * AHB1ENR ETH1TXEN LL_C2_AHB1_GRP1_DisableClock\n
5350 * AHB1ENR ETH1RXEN LL_C2_AHB1_GRP1_DisableClock\n
5351 * AHB1ENR USB1OTGHSEN LL_C2_AHB1_GRP1_DisableClock\n
5352 * AHB1ENR USB1OTGHSULPIEN LL_C2_AHB1_GRP1_DisableClock\n
5353 * AHB1ENR USB2OTGHSEN LL_C2_AHB1_GRP1_DisableClock\n
5354 * AHB1ENR USB2OTGHSULPIEN LL_C2_AHB1_GRP1_DisableClock
5355 * @param Periphs This parameter can be a combination of the following values:
5356 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
5357 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
5358 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
5359 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
5360 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
5361 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
5362 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
5363 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
5364 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
5365 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
5366 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
5367 *
5368 * (*) value not defined in all devices.
5369 * @retval None
5370 */
5371 __STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClock(uint32_t Periphs)
5372 {
5373 CLEAR_BIT(RCC_C2->AHB1ENR, Periphs);
5374 }
5375
5376 /**
5377 * @brief Enable C2 AHB1 peripherals clock during Low Power (Sleep) mode.
5378 * @rmtoll AHB1LPENR DMA1LPEN LL_C2_AHB1_GRP1_EnableClockSleep\n
5379 * AHB1LPENR DMA2LPEN LL_C2_AHB1_GRP1_EnableClockSleep\n
5380 * AHB1LPENR ADC12LPEN LL_C2_AHB1_GRP1_EnableClockSleep\n
5381 * AHB1LPENR ARTLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n
5382 * AHB1LPENR ETH1MACLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n
5383 * AHB1LPENR ETH1TXLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n
5384 * AHB1LPENR ETH1RXLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n
5385 * AHB1LPENR USB1OTGHSLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n
5386 * AHB1LPENR USB1OTGHSULPILPEN LL_C2_AHB1_GRP1_EnableClockSleep\n
5387 * AHB1LPENR USB2OTGHSLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n
5388 * AHB1LPENR USB2OTGHSULPILPEN LL_C2_AHB1_GRP1_EnableClockSleep
5389 * @param Periphs This parameter can be a combination of the following values:
5390 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
5391 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
5392 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
5393 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
5394 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
5395 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
5396 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
5397 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
5398 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
5399 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
5400 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
5401 *
5402 * (*) value not defined in all devices.
5403 * @retval None
5404 */
5405 __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
5406 {
5407 __IO uint32_t tmpreg;
5408 SET_BIT(RCC_C2->AHB1LPENR, Periphs);
5409 /* Delay after an RCC peripheral clock enabling */
5410 tmpreg = READ_BIT(RCC_C2->AHB1LPENR, Periphs);
5411 (void)tmpreg;
5412 }
5413
5414 /**
5415 * @brief Disable C2 AHB1 peripherals clock during Low Power (Sleep) mode.
5416 * @rmtoll AHB1LPENR DMA1LPEN LL_C2_AHB1_GRP1_DisableClockSleep\n
5417 * AHB1LPENR DMA2LPEN LL_C2_AHB1_GRP1_DisableClockSleep\n
5418 * AHB1LPENR ADC12LPEN LL_C2_AHB1_GRP1_DisableClockSleep\n
5419 * AHB1LPENR ARTLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n
5420 * AHB1LPENR ETH1MACLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n
5421 * AHB1LPENR ETH1TXLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n
5422 * AHB1LPENR ETH1RXLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n
5423 * AHB1LPENR USB1OTGHSLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n
5424 * AHB1LPENR USB1OTGHSULPILPEN LL_C2_AHB1_GRP1_DisableClockSleep\n
5425 * AHB1LPENR USB2OTGHSLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n
5426 * AHB1LPENR USB2OTGHSULPILPEN LL_C2_AHB1_GRP1_DisableClockSleep
5427 * @param Periphs This parameter can be a combination of the following values:
5428 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
5429 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
5430 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
5431 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
5432 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
5433 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
5434 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
5435 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
5436 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
5437 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
5438 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
5439 *
5440 * (*) value not defined in all devices.
5441 * @retval None
5442 */
5443 __STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
5444 {
5445 CLEAR_BIT(RCC_C2->AHB1LPENR, Periphs);
5446 }
5447
5448 /**
5449 * @}
5450 */
5451
5452 /** @addtogroup BUS_LL_EF_AHB2 AHB2
5453 * @{
5454 */
5455
5456 /**
5457 * @brief Enable C2 AHB2 peripherals clock.
5458 * @rmtoll AHB2ENR DCMIEN LL_C2_AHB2_GRP1_EnableClock\n
5459 * AHB2ENR CRYPEN LL_C2_AHB2_GRP1_EnableClock\n
5460 * AHB2ENR HASHEN LL_C2_AHB2_GRP1_EnableClock\n
5461 * AHB2ENR RNGEN LL_C2_AHB2_GRP1_EnableClock\n
5462 * AHB2ENR SDMMC2EN LL_C2_AHB2_GRP1_EnableClock
5463 * @param Periphs This parameter can be a combination of the following values:
5464 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
5465 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
5466 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
5467 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
5468 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
5469 *
5470 * (*) value not defined in all devices.
5471 * @retval None
5472 */
5473 __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClock(uint32_t Periphs)
5474 {
5475 __IO uint32_t tmpreg;
5476 SET_BIT(RCC_C2->AHB2ENR, Periphs);
5477 /* Delay after an RCC peripheral clock enabling */
5478 tmpreg = READ_BIT(RCC_C2->AHB2ENR, Periphs);
5479 (void)tmpreg;
5480 }
5481
5482 /**
5483 * @brief Check if C2 AHB2 peripheral clock is enabled or not
5484 * @rmtoll AHB2ENR DCMIEN LL_C2_AHB2_GRP1_IsEnabledClock\n
5485 * AHB2ENR CRYPEN LL_C2_AHB2_GRP1_IsEnabledClock\n
5486 * AHB2ENR HASHEN LL_C2_AHB2_GRP1_IsEnabledClock\n
5487 * AHB2ENR RNGEN LL_C2_AHB2_GRP1_IsEnabledClock\n
5488 * AHB2ENR SDMMC2EN LL_C2_AHB2_GRP1_IsEnabledClock
5489 * @param Periphs This parameter can be a combination of the following values:
5490 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
5491 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
5492 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
5493 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
5494 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
5495 *
5496 * (*) value not defined in all devices.
5497 * @retval uint32_t
5498 */
5499 __STATIC_INLINE uint32_t LL_C2_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
5500 {
5501 return ((READ_BIT(RCC_C2->AHB2ENR, Periphs) == Periphs)?1U:0U);
5502 }
5503
5504 /**
5505 * @brief Disable C2 AHB2 peripherals clock.
5506 * @rmtoll AHB2ENR DCMIEN LL_C2_AHB2_GRP1_DisableClock\n
5507 * AHB2ENR CRYPEN LL_C2_AHB2_GRP1_DisableClock\n
5508 * AHB2ENR HASHEN LL_C2_AHB2_GRP1_DisableClock\n
5509 * AHB2ENR RNGEN LL_C2_AHB2_GRP1_DisableClock\n
5510 * AHB2ENR SDMMC2EN LL_C2_AHB2_GRP1_DisableClock
5511 * @param Periphs This parameter can be a combination of the following values:
5512 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
5513 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
5514 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
5515 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
5516 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
5517 *
5518 * (*) value not defined in all devices.
5519 * @retval None
5520 */
5521 __STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClock(uint32_t Periphs)
5522 {
5523 CLEAR_BIT(RCC_C2->AHB2ENR, Periphs);
5524 }
5525
5526 /**
5527 * @brief Enable C2 AHB2 peripherals clock during Low Power (Sleep) mode.
5528 * @rmtoll AHB2LPENR DCMILPEN LL_C2_AHB2_GRP1_EnableClockSleep\n
5529 * AHB2LPENR CRYPLPEN LL_C2_AHB2_GRP1_EnableClockSleep\n
5530 * AHB2LPENR HASHLPEN LL_C2_AHB2_GRP1_EnableClockSleep\n
5531 * AHB2LPENR RNGLPEN LL_C2_AHB2_GRP1_EnableClockSleep\n
5532 * AHB2LPENR SDMMC2LPEN LL_C2_AHB2_GRP1_EnableClockSleep\n
5533 * AHB2LPENR D2SRAM1LPEN LL_C2_AHB2_GRP1_EnableClockSleep\n
5534 * AHB2LPENR D2SRAM2LPEN LL_C2_AHB2_GRP1_EnableClockSleep\n
5535 * AHB2LPENR D2SRAM3LPEN LL_C2_AHB2_GRP1_EnableClockSleep
5536 * @param Periphs This parameter can be a combination of the following values:
5537 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
5538 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
5539 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
5540 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
5541 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
5542 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
5543 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
5544 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
5545 *
5546 * (*) value not defined in all devices.
5547 * @retval None
5548 */
5549 __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
5550 {
5551 __IO uint32_t tmpreg;
5552 SET_BIT(RCC_C2->AHB2LPENR, Periphs);
5553 /* Delay after an RCC peripheral clock enabling */
5554 tmpreg = READ_BIT(RCC_C2->AHB2LPENR, Periphs);
5555 (void)tmpreg;
5556 }
5557
5558 /**
5559 * @brief Disable C2 AHB2 peripherals clock during Low Power (Sleep) mode.
5560 * @rmtoll AHB2LPENR DCMILPEN LL_C2_AHB2_GRP1_DisableClockSleep\n
5561 * AHB2LPENR CRYPLPEN LL_C2_AHB2_GRP1_DisableClockSleep\n
5562 * AHB2LPENR HASHLPEN LL_C2_AHB2_GRP1_DisableClockSleep\n
5563 * AHB2LPENR RNGLPEN LL_C2_AHB2_GRP1_DisableClockSleep\n
5564 * AHB2LPENR SDMMC2LPEN LL_C2_AHB2_GRP1_DisableClockSleep\n
5565 * AHB2LPENR D2SRAM1LPEN LL_C2_AHB2_GRP1_DisableClockSleep\n
5566 * AHB2LPENR D2SRAM2LPEN LL_C2_AHB2_GRP1_DisableClockSleep\n
5567 * AHB2LPENR D2SRAM3LPEN LL_C2_AHB2_GRP1_DisableClockSleep
5568 * @param Periphs This parameter can be a combination of the following values:
5569 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
5570 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
5571 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
5572 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
5573 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
5574 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
5575 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
5576 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
5577 *
5578 * (*) value not defined in all devices.
5579 * @retval None
5580 */
5581 __STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
5582 {
5583 CLEAR_BIT(RCC_C2->AHB2LPENR, Periphs);
5584 }
5585
5586 /**
5587 * @}
5588 */
5589
5590 /** @addtogroup BUS_LL_EF_AHB4 AHB4
5591 * @{
5592 */
5593
5594 /**
5595 * @brief Enable C2 AHB4 peripherals clock.
5596 * @rmtoll AHB4ENR GPIOAEN LL_C2_AHB4_GRP1_EnableClock\n
5597 * AHB4ENR GPIOBEN LL_C2_AHB4_GRP1_EnableClock\n
5598 * AHB4ENR GPIOCEN LL_C2_AHB4_GRP1_EnableClock\n
5599 * AHB4ENR GPIODEN LL_C2_AHB4_GRP1_EnableClock\n
5600 * AHB4ENR GPIOEEN LL_C2_AHB4_GRP1_EnableClock\n
5601 * AHB4ENR GPIOFEN LL_C2_AHB4_GRP1_EnableClock\n
5602 * AHB4ENR GPIOGEN LL_C2_AHB4_GRP1_EnableClock\n
5603 * AHB4ENR GPIOHEN LL_C2_AHB4_GRP1_EnableClock\n
5604 * AHB4ENR GPIOIEN LL_C2_AHB4_GRP1_EnableClock\n
5605 * AHB4ENR GPIOJEN LL_C2_AHB4_GRP1_EnableClock\n
5606 * AHB4ENR GPIOKEN LL_C2_AHB4_GRP1_EnableClock\n
5607 * AHB4ENR CRCEN LL_C2_AHB4_GRP1_EnableClock\n
5608 * AHB4ENR BDMAEN LL_C2_AHB4_GRP1_EnableClock\n
5609 * AHB4ENR ADC3EN LL_C2_AHB4_GRP1_EnableClock\n
5610 * AHB4ENR HSEMEN LL_C2_AHB4_GRP1_EnableClock\n
5611 * AHB4ENR BKPRAMEN LL_C2_AHB4_GRP1_EnableClock\n
5612 * AHB4ENR SRAM4EN LL_C2_AHB4_GRP1_EnableClock
5613 * @param Periphs This parameter can be a combination of the following values:
5614 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
5615 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
5616 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
5617 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
5618 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
5619 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
5620 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
5621 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
5622 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
5623 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
5624 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
5625 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
5626 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
5627 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
5628 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
5629 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
5630 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
5631 *
5632 * (*) value not defined in all devices.
5633 * @retval None
5634 */
5635 __STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClock(uint32_t Periphs)
5636 {
5637 __IO uint32_t tmpreg;
5638 SET_BIT(RCC_C2->AHB4ENR, Periphs);
5639 /* Delay after an RCC peripheral clock enabling */
5640 tmpreg = READ_BIT(RCC_C2->AHB4ENR, Periphs);
5641 (void)tmpreg;
5642 }
5643
5644 /**
5645 * @brief Check if C2 AHB4 peripheral clock is enabled or not
5646 * @rmtoll AHB4ENR GPIOAEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5647 * AHB4ENR GPIOBEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5648 * AHB4ENR GPIOCEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5649 * AHB4ENR GPIODEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5650 * AHB4ENR GPIOEEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5651 * AHB4ENR GPIOFEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5652 * AHB4ENR GPIOGEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5653 * AHB4ENR GPIOHEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5654 * AHB4ENR GPIOIEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5655 * AHB4ENR GPIOJEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5656 * AHB4ENR GPIOKEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5657 * AHB4ENR CRCEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5658 * AHB4ENR BDMAEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5659 * AHB4ENR ADC3EN LL_C2_AHB4_GRP1_IsEnabledClock\n
5660 * AHB4ENR HSEMEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5661 * AHB4ENR BKPRAMEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5662 * AHB4ENR SRAM4EN LL_C2_AHB4_GRP1_IsEnabledClock
5663 * @param Periphs This parameter can be a combination of the following values:
5664 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
5665 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
5666 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
5667 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
5668 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
5669 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
5670 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
5671 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
5672 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
5673 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
5674 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
5675 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
5676 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
5677 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
5678 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
5679 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
5680 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
5681 *
5682 * (*) value not defined in all devices.
5683 * @retval uint32_t
5684 */
5685 __STATIC_INLINE uint32_t LL_C2_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
5686 {
5687 return ((READ_BIT(RCC_C2->AHB4ENR, Periphs) == Periphs)?1U:0U);
5688 }
5689
5690 /**
5691 * @brief Disable C2 AHB4 peripherals clock.
5692 * @rmtoll AHB4ENR GPIOAEN LL_C2_AHB4_GRP1_DisableClock\n
5693 * AHB4ENR GPIOBEN LL_C2_AHB4_GRP1_DisableClock\n
5694 * AHB4ENR GPIOCEN LL_C2_AHB4_GRP1_DisableClock\n
5695 * AHB4ENR GPIODEN LL_C2_AHB4_GRP1_DisableClock\n
5696 * AHB4ENR GPIOEEN LL_C2_AHB4_GRP1_DisableClock\n
5697 * AHB4ENR GPIOFEN LL_C2_AHB4_GRP1_DisableClock\n
5698 * AHB4ENR GPIOGEN LL_C2_AHB4_GRP1_DisableClock\n
5699 * AHB4ENR GPIOHEN LL_C2_AHB4_GRP1_DisableClock\n
5700 * AHB4ENR GPIOIEN LL_C2_AHB4_GRP1_DisableClock\n
5701 * AHB4ENR GPIOJEN LL_C2_AHB4_GRP1_DisableClock\n
5702 * AHB4ENR GPIOKEN LL_C2_AHB4_GRP1_DisableClock\n
5703 * AHB4ENR CRCEN LL_C2_AHB4_GRP1_DisableClock\n
5704 * AHB4ENR BDMAEN LL_C2_AHB4_GRP1_DisableClock\n
5705 * AHB4ENR ADC3EN LL_C2_AHB4_GRP1_DisableClock\n
5706 * AHB4ENR HSEMEN LL_C2_AHB4_GRP1_DisableClock\n
5707 * AHB4ENR BKPRAMEN LL_C2_AHB4_GRP1_DisableClock\n
5708 * AHB4ENR SRAM4EN LL_C2_AHB4_GRP1_DisableClock
5709 * @param Periphs This parameter can be a combination of the following values:
5710 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
5711 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
5712 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
5713 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
5714 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
5715 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
5716 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
5717 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
5718 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
5719 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
5720 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
5721 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
5722 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
5723 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
5724 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
5725 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
5726 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
5727 *
5728 * (*) value not defined in all devices.
5729 * @retval None
5730 */
5731 __STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClock(uint32_t Periphs)
5732 {
5733 CLEAR_BIT(RCC_C2->AHB4ENR, Periphs);
5734 }
5735
5736 /**
5737 * @brief Enable C2 AHB4 peripherals clock during Low Power (Sleep) mode.
5738 * @rmtoll AHB4LPENR GPIOALPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5739 * AHB4LPENR GPIOBLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5740 * AHB4LPENR GPIOCLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5741 * AHB4LPENR GPIODLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5742 * AHB4LPENR GPIOELPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5743 * AHB4LPENR GPIOFLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5744 * AHB4LPENR GPIOGLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5745 * AHB4LPENR GPIOHLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5746 * AHB4LPENR GPIOILPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5747 * AHB4LPENR GPIOJLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5748 * AHB4LPENR GPIOKLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5749 * AHB4LPENR CRCLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5750 * AHB4LPENR BDMALPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5751 * AHB4LPENR ADC3LPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5752 * AHB4LPENR BKPRAMLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5753 * AHB4LPENR SRAM4LPEN LL_C2_AHB4_GRP1_EnableClockSleep
5754 * @param Periphs This parameter can be a combination of the following values:
5755 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
5756 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
5757 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
5758 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
5759 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
5760 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
5761 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
5762 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
5763 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
5764 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
5765 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
5766 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
5767 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
5768 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
5769 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
5770 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
5771 * @retval None
5772 */
5773 __STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)
5774 {
5775 __IO uint32_t tmpreg;
5776 SET_BIT(RCC_C2->AHB4LPENR, Periphs);
5777 /* Delay after an RCC peripheral clock enabling */
5778 tmpreg = READ_BIT(RCC_C2->AHB4LPENR, Periphs);
5779 (void)tmpreg;
5780 }
5781
5782 /**
5783 * @brief Disable C2 AHB4 peripherals clock during Low Power (Sleep) mode.
5784 * @rmtoll AHB4LPENR GPIOALPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5785 * AHB4LPENR GPIOBLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5786 * AHB4LPENR GPIOCLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5787 * AHB4LPENR GPIODLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5788 * AHB4LPENR GPIOELPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5789 * AHB4LPENR GPIOFLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5790 * AHB4LPENR GPIOGLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5791 * AHB4LPENR GPIOHLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5792 * AHB4LPENR GPIOILPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5793 * AHB4LPENR GPIOJLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5794 * AHB4LPENR GPIOKLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5795 * AHB4LPENR CRCLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5796 * AHB4LPENR BDMALPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5797 * AHB4LPENR ADC3LPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5798 * AHB4LPENR BKPRAMLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5799 * AHB4LPENR SRAM4LPEN LL_C2_AHB4_GRP1_DisableClockSleep
5800 * @param Periphs This parameter can be a combination of the following values:
5801 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
5802 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
5803 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
5804 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
5805 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
5806 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
5807 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
5808 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
5809 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*)
5810 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
5811 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
5812 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
5813 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
5814 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
5815 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
5816 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
5817 * @retval None
5818 */
5819 __STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)
5820 {
5821 CLEAR_BIT(RCC_C2->AHB4LPENR, Periphs);
5822 }
5823
5824 /**
5825 * @}
5826 */
5827
5828 /** @addtogroup BUS_LL_EF_APB3 APB3
5829 * @{
5830 */
5831
5832 /**
5833 * @brief Enable C2 APB3 peripherals clock.
5834 * @rmtoll APB3ENR LTDCEN LL_C2_APB3_GRP1_EnableClock\n
5835 * APB3ENR DSIEN LL_C2_APB3_GRP1_EnableClock\n
5836 * APB3ENR WWDG1EN LL_C2_APB3_GRP1_EnableClock
5837 * @param Periphs This parameter can be a combination of the following values:
5838 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
5839 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
5840 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
5841 *
5842 * (*) value not defined in all devices.
5843 * @retval None
5844 */
5845 __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClock(uint32_t Periphs)
5846 {
5847 __IO uint32_t tmpreg;
5848 SET_BIT(RCC_C2->APB3ENR, Periphs);
5849 /* Delay after an RCC peripheral clock enabling */
5850 tmpreg = READ_BIT(RCC_C2->APB3ENR, Periphs);
5851 (void)tmpreg;
5852 }
5853
5854 /**
5855 * @brief Check if C2 APB3 peripheral clock is enabled or not
5856 * @rmtoll APB3ENR LTDCEN LL_C2_APB3_GRP1_IsEnabledClock\n
5857 * APB3ENR DSIEN LL_C2_APB3_GRP1_IsEnabledClock\n
5858 * APB3ENR WWDG1EN LL_C2_APB3_GRP1_IsEnabledClock
5859 * @param Periphs This parameter can be a combination of the following values:
5860 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
5861 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
5862 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
5863 *
5864 * (*) value not defined in all devices.
5865 * @retval uint32_t
5866 */
5867 __STATIC_INLINE uint32_t LL_C2_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
5868 {
5869 return ((READ_BIT(RCC_C2->APB3ENR, Periphs) == Periphs)?1U:0U);
5870 }
5871
5872 /**
5873 * @brief Disable C2 APB3 peripherals clock.
5874 * @rmtoll APB3ENR LTDCEN LL_C2_APB3_GRP1_DisableClock\n
5875 * APB3ENR DSIEN LL_C2_APB3_GRP1_DisableClock\n
5876 * APB3ENR WWDG1EN LL_C2_APB3_GRP1_DisableClock
5877 * @param Periphs This parameter can be a combination of the following values:
5878 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
5879 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
5880 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
5881 *
5882 * (*) value not defined in all devices.
5883 * @retval None
5884 */
5885 __STATIC_INLINE void LL_C2_APB3_GRP1_DisableClock(uint32_t Periphs)
5886 {
5887 CLEAR_BIT(RCC_C2->APB3ENR, Periphs);
5888 }
5889
5890 /**
5891 * @brief Enable C2 APB3 peripherals clock during Low Power (Sleep) mode.
5892 * @rmtoll APB3LPENR LTDCLPEN LL_C2_APB3_GRP1_EnableClockSleep\n
5893 * APB3LPENR DSILPEN LL_C2_APB3_GRP1_EnableClockSleep\n
5894 * APB3LPENR WWDG1LPEN LL_C2_APB3_GRP1_EnableClockSleep
5895 * @param Periphs This parameter can be a combination of the following values:
5896 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
5897 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
5898 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
5899 *
5900 * (*) value not defined in all devices.
5901 * @retval None
5902 */
5903 __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
5904 {
5905 __IO uint32_t tmpreg;
5906 SET_BIT(RCC_C2->APB3LPENR, Periphs);
5907 /* Delay after an RCC peripheral clock enabling */
5908 tmpreg = READ_BIT(RCC_C2->APB3LPENR, Periphs);
5909 (void)tmpreg;
5910 }
5911
5912 /**
5913 * @brief Disable C2 APB3 peripherals clock during Low Power (Sleep) mode.
5914 * @rmtoll APB3LPENR LTDCLPEN LL_C2_APB3_GRP1_DisableClockSleep\n
5915 * APB3LPENR DSILPEN LL_C2_APB3_GRP1_DisableClockSleep\n
5916 * APB3LPENR WWDG1LPEN LL_C2_APB3_GRP1_DisableClockSleep
5917 * @param Periphs This parameter can be a combination of the following values:
5918 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
5919 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
5920 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
5921 *
5922 * (*) value not defined in all devices.
5923 * @retval None
5924 */
5925 __STATIC_INLINE void LL_C2_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
5926 {
5927 CLEAR_BIT(RCC_C2->APB3LPENR, Periphs);
5928 }
5929
5930 /**
5931 * @}
5932 */
5933
5934 /** @addtogroup BUS_LL_EF_APB1 APB1
5935 * @{
5936 */
5937
5938 /**
5939 * @brief Enable C2 APB1 peripherals clock.
5940 * @rmtoll APB1LENR TIM2EN LL_C2_APB1_GRP1_EnableClock\n
5941 * APB1LENR TIM3EN LL_C2_APB1_GRP1_EnableClock\n
5942 * APB1LENR TIM4EN LL_C2_APB1_GRP1_EnableClock\n
5943 * APB1LENR TIM5EN LL_C2_APB1_GRP1_EnableClock\n
5944 * APB1LENR TIM6EN LL_C2_APB1_GRP1_EnableClock\n
5945 * APB1LENR TIM7EN LL_C2_APB1_GRP1_EnableClock\n
5946 * APB1LENR TIM12EN LL_C2_APB1_GRP1_EnableClock\n
5947 * APB1LENR TIM13EN LL_C2_APB1_GRP1_EnableClock\n
5948 * APB1LENR TIM14EN LL_C2_APB1_GRP1_EnableClock\n
5949 * APB1LENR LPTIM1EN LL_C2_APB1_GRP1_EnableClock\n
5950 * APB1LENR WWDG2EN LL_C2_APB1_GRP1_EnableClock\n
5951 * APB1LENR SPI2EN LL_C2_APB1_GRP1_EnableClock\n
5952 * APB1LENR SPI3EN LL_C2_APB1_GRP1_EnableClock\n
5953 * APB1LENR SPDIFRXEN LL_C2_APB1_GRP1_EnableClock\n
5954 * APB1LENR USART2EN LL_C2_APB1_GRP1_EnableClock\n
5955 * APB1LENR USART3EN LL_C2_APB1_GRP1_EnableClock\n
5956 * APB1LENR UART4EN LL_C2_APB1_GRP1_EnableClock\n
5957 * APB1LENR UART5EN LL_C2_APB1_GRP1_EnableClock\n
5958 * APB1LENR I2C1EN LL_C2_APB1_GRP1_EnableClock\n
5959 * APB1LENR I2C2EN LL_C2_APB1_GRP1_EnableClock\n
5960 * APB1LENR I2C3EN LL_C2_APB1_GRP1_EnableClock\n
5961 * APB1LENR CECEN LL_C2_APB1_GRP1_EnableClock\n
5962 * APB1LENR DAC12EN LL_C2_APB1_GRP1_EnableClock\n
5963 * APB1LENR UART7EN LL_C2_APB1_GRP1_EnableClock\n
5964 * APB1LENR UART8EN LL_C2_APB1_GRP1_EnableClock
5965 * @param Periphs This parameter can be a combination of the following values:
5966 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
5967 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
5968 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
5969 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
5970 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
5971 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
5972 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
5973 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
5974 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
5975 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
5976 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
5977 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
5978 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
5979 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
5980 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
5981 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
5982 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
5983 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
5984 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
5985 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
5986 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
5987 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
5988 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
5989 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
5990 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
5991 *
5992 * (*) value not defined in all devices.
5993 * @retval None
5994 */
5995 __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs)
5996 {
5997 __IO uint32_t tmpreg;
5998 SET_BIT(RCC_C2->APB1LENR, Periphs);
5999 /* Delay after an RCC peripheral clock enabling */
6000 tmpreg = READ_BIT(RCC_C2->APB1LENR, Periphs);
6001 (void)tmpreg;
6002 }
6003
6004 /**
6005 * @brief Check if C2 APB1 peripheral clock is enabled or not
6006 * @rmtoll APB1LENR TIM2EN LL_C2_APB1_GRP1_IsEnabledClock\n
6007 * APB1LENR TIM3EN LL_C2_APB1_GRP1_IsEnabledClock\n
6008 * APB1LENR TIM4EN LL_C2_APB1_GRP1_IsEnabledClock\n
6009 * APB1LENR TIM5EN LL_C2_APB1_GRP1_IsEnabledClock\n
6010 * APB1LENR TIM6EN LL_C2_APB1_GRP1_IsEnabledClock\n
6011 * APB1LENR TIM7EN LL_C2_APB1_GRP1_IsEnabledClock\n
6012 * APB1LENR TIM12EN LL_C2_APB1_GRP1_IsEnabledClock\n
6013 * APB1LENR TIM13EN LL_C2_APB1_GRP1_IsEnabledClock\n
6014 * APB1LENR TIM14EN LL_C2_APB1_GRP1_IsEnabledClock\n
6015 * APB1LENR LPTIM1EN LL_C2_APB1_GRP1_IsEnabledClock\n
6016 * APB1LENR WWDG2EN LL_C2_APB1_GRP1_IsEnabledClock\n
6017 * APB1LENR SPI2EN LL_C2_APB1_GRP1_IsEnabledClock\n
6018 * APB1LENR SPI3EN LL_C2_APB1_GRP1_IsEnabledClock\n
6019 * APB1LENR SPDIFRXEN LL_C2_APB1_GRP1_IsEnabledClock\n
6020 * APB1LENR USART2EN LL_C2_APB1_GRP1_IsEnabledClock\n
6021 * APB1LENR USART3EN LL_C2_APB1_GRP1_IsEnabledClock\n
6022 * APB1LENR UART4EN LL_C2_APB1_GRP1_IsEnabledClock\n
6023 * APB1LENR UART5EN LL_C2_APB1_GRP1_IsEnabledClock\n
6024 * APB1LENR I2C1EN LL_C2_APB1_GRP1_IsEnabledClock\n
6025 * APB1LENR I2C2EN LL_C2_APB1_GRP1_IsEnabledClock\n
6026 * APB1LENR I2C3EN LL_C2_APB1_GRP1_IsEnabledClock\n
6027 * APB1LENR CECEN LL_C2_APB1_GRP1_IsEnabledClock\n
6028 * APB1LENR DAC12EN LL_C2_APB1_GRP1_IsEnabledClock\n
6029 * APB1LENR UART7EN LL_C2_APB1_GRP1_IsEnabledClock\n
6030 * APB1LENR UART8EN LL_C2_APB1_GRP1_IsEnabledClock
6031 * @param Periphs This parameter can be a combination of the following values:
6032 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
6033 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
6034 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
6035 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
6036 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
6037 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
6038 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
6039 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
6040 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
6041 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
6042 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
6043 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
6044 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
6045 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
6046 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
6047 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
6048 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
6049 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
6050 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
6051 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
6052 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
6053 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
6054 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
6055 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
6056 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
6057 *
6058 * (*) value not defined in all devices.
6059 * @retval uint32_t
6060 */
6061 __STATIC_INLINE uint32_t LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
6062 {
6063 return ((READ_BIT(RCC_C2->APB1LENR, Periphs) == Periphs)?1U:0U);
6064 }
6065
6066 /**
6067 * @brief Disable C2 APB1 peripherals clock.
6068 * @rmtoll APB1LENR TIM2EN LL_C2_APB1_GRP1_DisableClock\n
6069 * APB1LENR TIM3EN LL_C2_APB1_GRP1_DisableClock\n
6070 * APB1LENR TIM4EN LL_C2_APB1_GRP1_DisableClock\n
6071 * APB1LENR TIM5EN LL_C2_APB1_GRP1_DisableClock\n
6072 * APB1LENR TIM6EN LL_C2_APB1_GRP1_DisableClock\n
6073 * APB1LENR TIM7EN LL_C2_APB1_GRP1_DisableClock\n
6074 * APB1LENR TIM12EN LL_C2_APB1_GRP1_DisableClock\n
6075 * APB1LENR TIM13EN LL_C2_APB1_GRP1_DisableClock\n
6076 * APB1LENR TIM14EN LL_C2_APB1_GRP1_DisableClock\n
6077 * APB1LENR LPTIM1EN LL_C2_APB1_GRP1_DisableClock\n
6078 * APB1LENR WWDG2EN LL_C2_APB1_GRP1_DisableClock\n
6079 * APB1LENR SPI2EN LL_C2_APB1_GRP1_DisableClock\n
6080 * APB1LENR SPI3EN LL_C2_APB1_GRP1_DisableClock\n
6081 * APB1LENR SPDIFRXEN LL_C2_APB1_GRP1_DisableClock\n
6082 * APB1LENR USART2EN LL_C2_APB1_GRP1_DisableClock\n
6083 * APB1LENR USART3EN LL_C2_APB1_GRP1_DisableClock\n
6084 * APB1LENR UART4EN LL_C2_APB1_GRP1_DisableClock\n
6085 * APB1LENR UART5EN LL_C2_APB1_GRP1_DisableClock\n
6086 * APB1LENR I2C1EN LL_C2_APB1_GRP1_DisableClock\n
6087 * APB1LENR I2C2EN LL_C2_APB1_GRP1_DisableClock\n
6088 * APB1LENR I2C3EN LL_C2_APB1_GRP1_DisableClock\n
6089 * APB1LENR CECEN LL_C2_APB1_GRP1_DisableClock\n
6090 * APB1LENR DAC12EN LL_C2_APB1_GRP1_DisableClock\n
6091 * APB1LENR UART7EN LL_C2_APB1_GRP1_DisableClock\n
6092 * APB1LENR UART8EN LL_C2_APB1_GRP1_DisableClock
6093 * @param Periphs This parameter can be a combination of the following values:
6094 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
6095 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
6096 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
6097 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
6098 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
6099 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
6100 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
6101 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
6102 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
6103 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
6104 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
6105 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
6106 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
6107 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
6108 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
6109 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
6110 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
6111 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
6112 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
6113 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
6114 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
6115 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
6116 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
6117 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
6118 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
6119 *
6120 * (*) value not defined in all devices.
6121 * @retval None
6122 */
6123 __STATIC_INLINE void LL_C2_APB1_GRP1_DisableClock(uint32_t Periphs)
6124 {
6125 CLEAR_BIT(RCC_C2->APB1LENR, Periphs);
6126 }
6127
6128 /**
6129 * @brief Enable C2 APB1 peripherals clock during Low Power (Sleep) mode.
6130 * @rmtoll APB1LLPENR TIM2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6131 * APB1LLPENR TIM3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6132 * APB1LLPENR TIM4LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6133 * APB1LLPENR TIM5LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6134 * APB1LLPENR TIM6LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6135 * APB1LLPENR TIM7LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6136 * APB1LLPENR TIM12LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6137 * APB1LLPENR TIM13LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6138 * APB1LLPENR TIM14LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6139 * APB1LLPENR LPTIM1LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6140 * APB1LLPENR WWDG2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6141 * APB1LLPENR SPI2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6142 * APB1LLPENR SPI3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6143 * APB1LLPENR SPDIFRXLPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6144 * APB1LLPENR USART2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6145 * APB1LLPENR USART3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6146 * APB1LLPENR UART4LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6147 * APB1LLPENR UART5LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6148 * APB1LLPENR I2C1LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6149 * APB1LLPENR I2C2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6150 * APB1LLPENR I2C3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6151 * APB1LLPENR CECLPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6152 * APB1LLPENR DAC12LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6153 * APB1LLPENR UART7LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6154 * APB1LLPENR UART8LPEN LL_C2_APB1_GRP1_EnableClockSleep
6155 * @param Periphs This parameter can be a combination of the following values:
6156 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
6157 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
6158 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
6159 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
6160 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
6161 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
6162 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
6163 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
6164 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
6165 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
6166 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
6167 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
6168 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
6169 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
6170 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
6171 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
6172 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
6173 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
6174 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
6175 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
6176 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
6177 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
6178 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
6179 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
6180 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
6181 *
6182 * (*) value not defined in all devices.
6183 * @retval None
6184 */
6185 __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
6186 {
6187 __IO uint32_t tmpreg;
6188 SET_BIT(RCC_C2->APB1LLPENR, Periphs);
6189 /* Delay after an RCC peripheral clock enabling */
6190 tmpreg = READ_BIT(RCC_C2->APB1LLPENR, Periphs);
6191 (void)tmpreg;
6192 }
6193
6194 /**
6195 * @brief Disable C2 APB1 peripherals clock during Low Power (Sleep) mode.
6196 * @rmtoll APB1LLPENR TIM2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6197 * APB1LLPENR TIM3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6198 * APB1LLPENR TIM4LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6199 * APB1LLPENR TIM5LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6200 * APB1LLPENR TIM6LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6201 * APB1LLPENR TIM7LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6202 * APB1LLPENR TIM12LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6203 * APB1LLPENR TIM13LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6204 * APB1LLPENR TIM14LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6205 * APB1LLPENR LPTIM1LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6206 * APB1LLPENR WWDG2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6207 * APB1LLPENR SPI2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6208 * APB1LLPENR SPI3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6209 * APB1LLPENR SPDIFRXLPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6210 * APB1LLPENR USART2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6211 * APB1LLPENR USART3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6212 * APB1LLPENR UART4LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6213 * APB1LLPENR UART5LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6214 * APB1LLPENR I2C1LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6215 * APB1LLPENR I2C2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6216 * APB1LLPENR I2C3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6217 * APB1LLPENR CECLPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6218 * APB1LLPENR DAC12LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6219 * APB1LLPENR UART7LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6220 * APB1LLPENR UART8LPEN LL_C2_APB1_GRP1_DisableClockSleep
6221 * @param Periphs This parameter can be a combination of the following values:
6222 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
6223 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
6224 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
6225 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
6226 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
6227 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
6228 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
6229 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
6230 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
6231 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
6232 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
6233 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
6234 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
6235 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
6236 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
6237 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
6238 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
6239 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
6240 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
6241 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
6242 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
6243 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
6244 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
6245 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
6246 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
6247 *
6248 * (*) value not defined in all devices.
6249 * @retval None
6250 */
6251 __STATIC_INLINE void LL_C2_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
6252 {
6253 CLEAR_BIT(RCC_C2->APB1LLPENR, Periphs);
6254 }
6255
6256 /**
6257 * @brief Enable C2 APB1 peripherals clock.
6258 * @rmtoll APB1HENR CRSEN LL_C2_APB1_GRP2_EnableClock\n
6259 * APB1HENR SWPMIEN LL_C2_APB1_GRP2_EnableClock\n
6260 * APB1HENR OPAMPEN LL_C2_APB1_GRP2_EnableClock\n
6261 * APB1HENR MDIOSEN LL_C2_APB1_GRP2_EnableClock\n
6262 * APB1HENR FDCANEN LL_C2_APB1_GRP2_EnableClock
6263 * @param Periphs This parameter can be a combination of the following values:
6264 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
6265 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
6266 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
6267 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
6268 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
6269 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
6270 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
6271 *
6272 * (*) value not defined in all devices.
6273 * @retval None
6274 */
6275 __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs)
6276 {
6277 __IO uint32_t tmpreg;
6278 SET_BIT(RCC_C2->APB1HENR, Periphs);
6279 /* Delay after an RCC peripheral clock enabling */
6280 tmpreg = READ_BIT(RCC_C2->APB1HENR, Periphs);
6281 (void)tmpreg;
6282 }
6283
6284 /**
6285 * @brief Check if C2 APB1 peripheral clock is enabled or not
6286 * @rmtoll APB1HENR CRSEN LL_C2_APB1_GRP2_IsEnabledClock\n
6287 * APB1HENR SWPMIEN LL_C2_APB1_GRP2_IsEnabledClock\n
6288 * APB1HENR OPAMPEN LL_C2_APB1_GRP2_IsEnabledClock\n
6289 * APB1HENR MDIOSEN LL_C2_APB1_GRP2_IsEnabledClock\n
6290 * APB1HENR FDCANEN LL_C2_APB1_GRP2_IsEnabledClock
6291 * @param Periphs This parameter can be a combination of the following values:
6292 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
6293 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
6294 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
6295 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
6296 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
6297 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
6298 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
6299 *
6300 * (*) value not defined in all devices.
6301 * @retval uint32_t
6302 */
6303 __STATIC_INLINE uint32_t LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
6304 {
6305 return ((READ_BIT(RCC_C2->APB1HENR, Periphs) == Periphs)?1U:0U);
6306 }
6307
6308 /**
6309 * @brief Disable C2 APB1 peripherals clock.
6310 * @rmtoll APB1HENR CRSEN LL_C2_APB1_GRP2_DisableClock\n
6311 * APB1HENR SWPMIEN LL_C2_APB1_GRP2_DisableClock\n
6312 * APB1HENR OPAMPEN LL_C2_APB1_GRP2_DisableClock\n
6313 * APB1HENR MDIOSEN LL_C2_APB1_GRP2_DisableClock\n
6314 * APB1HENR FDCANEN LL_C2_APB1_GRP2_DisableClock
6315 * @param Periphs This parameter can be a combination of the following values:
6316 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
6317 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
6318 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
6319 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
6320 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
6321 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
6322 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
6323 *
6324 * (*) value not defined in all devices.
6325 * @retval None
6326 */
6327 __STATIC_INLINE void LL_C2_APB1_GRP2_DisableClock(uint32_t Periphs)
6328 {
6329 CLEAR_BIT(RCC_C2->APB1HENR, Periphs);
6330 }
6331
6332 /**
6333 * @brief Enable C2 APB1 peripherals clock during Low Power (Sleep) mode.
6334 * @rmtoll APB1HLPENR CRSLPEN LL_C2_APB1_GRP2_EnableClockSleep\n
6335 * APB1HLPENR SWPMILPEN LL_C2_APB1_GRP2_EnableClockSleep\n
6336 * APB1HLPENR OPAMPLPEN LL_C2_APB1_GRP2_EnableClockSleep\n
6337 * APB1HLPENR MDIOSLPEN LL_C2_APB1_GRP2_EnableClockSleep\n
6338 * APB1HLPENR FDCANLPEN LL_C2_APB1_GRP2_EnableClockSleep
6339 * @param Periphs This parameter can be a combination of the following values:
6340 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
6341 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
6342 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
6343 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
6344 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
6345 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
6346 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
6347 *
6348 * (*) value not defined in all devices.
6349 * @retval None
6350 */
6351 __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
6352 {
6353 __IO uint32_t tmpreg;
6354 SET_BIT(RCC_C2->APB1HLPENR, Periphs);
6355 /* Delay after an RCC peripheral clock enabling */
6356 tmpreg = READ_BIT(RCC_C2->APB1HLPENR, Periphs);
6357 (void)tmpreg;
6358 }
6359
6360 /**
6361 * @brief Disable C2 APB1 peripherals clock during Low Power (Sleep) mode.
6362 * @rmtoll APB1HLPENR CRSLPEN LL_C2_APB1_GRP2_DisableClockSleep\n
6363 * APB1HLPENR SWPMILPEN LL_C2_APB1_GRP2_DisableClockSleep\n
6364 * APB1HLPENR OPAMPLPEN LL_C2_APB1_GRP2_DisableClockSleep\n
6365 * APB1HLPENR MDIOSLPEN LL_C2_APB1_GRP2_DisableClockSleep\n
6366 * APB1HLPENR FDCANLPEN LL_C2_APB1_GRP2_DisableClockSleep
6367 * @param Periphs This parameter can be a combination of the following values:
6368 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
6369 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
6370 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
6371 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
6372 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
6373 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*)
6374 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*)
6375 *
6376 * (*) value not defined in all devices.
6377 * @retval None
6378 */
6379 __STATIC_INLINE void LL_C2_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
6380 {
6381 CLEAR_BIT(RCC_C2->APB1HLPENR, Periphs);
6382 }
6383
6384 /**
6385 * @}
6386 */
6387
6388 /** @addtogroup BUS_LL_EF_APB2 APB2
6389 * @{
6390 */
6391
6392 /**
6393 * @brief Enable C2 APB2 peripherals clock.
6394 * @rmtoll APB2ENR TIM1EN LL_C2_APB2_GRP1_EnableClock\n
6395 * APB2ENR TIM8EN LL_C2_APB2_GRP1_EnableClock\n
6396 * APB2ENR USART1EN LL_C2_APB2_GRP1_EnableClock\n
6397 * APB2ENR USART6EN LL_C2_APB2_GRP1_EnableClock\n
6398 * APB2ENR SPI1EN LL_C2_APB2_GRP1_EnableClock\n
6399 * APB2ENR SPI4EN LL_C2_APB2_GRP1_EnableClock\n
6400 * APB2ENR TIM15EN LL_C2_APB2_GRP1_EnableClock\n
6401 * APB2ENR TIM16EN LL_C2_APB2_GRP1_EnableClock\n
6402 * APB2ENR TIM17EN LL_C2_APB2_GRP1_EnableClock\n
6403 * APB2ENR SPI5EN LL_C2_APB2_GRP1_EnableClock\n
6404 * APB2ENR SAI1EN LL_C2_APB2_GRP1_EnableClock\n
6405 * APB2ENR SAI2EN LL_C2_APB2_GRP1_EnableClock\n
6406 * APB2ENR SAI3EN LL_C2_APB2_GRP1_EnableClock\n
6407 * APB2ENR DFSDM1EN LL_C2_APB2_GRP1_EnableClock\n
6408 * APB2ENR HRTIMEN LL_C2_APB2_GRP1_EnableClock
6409 * @param Periphs This parameter can be a combination of the following values:
6410 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
6411 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
6412 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
6413 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
6414 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
6415 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
6416 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
6417 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
6418 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
6419 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
6420 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
6421 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
6422 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
6423 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
6424 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
6425 *
6426 * (*) value not defined in all devices.
6427
6428 * @retval None
6429 */
6430 __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs)
6431 {
6432 __IO uint32_t tmpreg;
6433 SET_BIT(RCC_C2->APB2ENR, Periphs);
6434 /* Delay after an RCC peripheral clock enabling */
6435 tmpreg = READ_BIT(RCC_C2->APB2ENR, Periphs);
6436 (void)tmpreg;
6437 }
6438
6439 /**
6440 * @brief Check if C2 APB2 peripheral clock is enabled or not
6441 * @rmtoll APB2ENR TIM1EN LL_C2_APB2_GRP1_IsEnabledClock\n
6442 * APB2ENR TIM8EN LL_C2_APB2_GRP1_IsEnabledClock\n
6443 * APB2ENR USART1EN LL_C2_APB2_GRP1_IsEnabledClock\n
6444 * APB2ENR USART6EN LL_C2_APB2_GRP1_IsEnabledClock\n
6445 * APB2ENR SPI1EN LL_C2_APB2_GRP1_IsEnabledClock\n
6446 * APB2ENR SPI4EN LL_C2_APB2_GRP1_IsEnabledClock\n
6447 * APB2ENR TIM15EN LL_C2_APB2_GRP1_IsEnabledClock\n
6448 * APB2ENR TIM16EN LL_C2_APB2_GRP1_IsEnabledClock\n
6449 * APB2ENR TIM17EN LL_C2_APB2_GRP1_IsEnabledClock\n
6450 * APB2ENR SPI5EN LL_C2_APB2_GRP1_IsEnabledClock\n
6451 * APB2ENR SAI1EN LL_C2_APB2_GRP1_IsEnabledClock\n
6452 * APB2ENR SAI2EN LL_C2_APB2_GRP1_IsEnabledClock\n
6453 * APB2ENR SAI3EN LL_C2_APB2_GRP1_IsEnabledClock\n
6454 * APB2ENR DFSDM1EN LL_C2_APB2_GRP1_IsEnabledClock\n
6455 * APB2ENR HRTIMEN LL_C2_APB2_GRP1_IsEnabledClock
6456 * @param Periphs This parameter can be a combination of the following values:
6457 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
6458 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
6459 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
6460 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
6461 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
6462 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
6463 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
6464 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
6465 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
6466 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
6467 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
6468 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
6469 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
6470 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
6471 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
6472 *
6473 * (*) value not defined in all devices.
6474 * @retval uint32_t
6475 */
6476 __STATIC_INLINE uint32_t LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
6477 {
6478 return ((READ_BIT(RCC_C2->APB2ENR, Periphs) == Periphs)?1U:0U);
6479 }
6480
6481 /**
6482 * @brief Disable C2 APB2 peripherals clock.
6483 * @rmtoll APB2ENR TIM1EN LL_C2_APB2_GRP1_DisableClock\n
6484 * APB2ENR TIM8EN LL_C2_APB2_GRP1_DisableClock\n
6485 * APB2ENR USART1EN LL_C2_APB2_GRP1_DisableClock\n
6486 * APB2ENR USART6EN LL_C2_APB2_GRP1_DisableClock\n
6487 * APB2ENR SPI1EN LL_C2_APB2_GRP1_DisableClock\n
6488 * APB2ENR SPI4EN LL_C2_APB2_GRP1_DisableClock\n
6489 * APB2ENR TIM15EN LL_C2_APB2_GRP1_DisableClock\n
6490 * APB2ENR TIM16EN LL_C2_APB2_GRP1_DisableClock\n
6491 * APB2ENR TIM17EN LL_C2_APB2_GRP1_DisableClock\n
6492 * APB2ENR SPI5EN LL_C2_APB2_GRP1_DisableClock\n
6493 * APB2ENR SAI1EN LL_C2_APB2_GRP1_DisableClock\n
6494 * APB2ENR SAI2EN LL_C2_APB2_GRP1_DisableClock\n
6495 * APB2ENR SAI3EN LL_C2_APB2_GRP1_DisableClock\n
6496 * APB2ENR DFSDM1EN LL_C2_APB2_GRP1_DisableClock\n
6497 * APB2ENR HRTIMEN LL_C2_APB2_GRP1_DisableClock
6498 * @param Periphs This parameter can be a combination of the following values:
6499 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
6500 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
6501 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
6502 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
6503 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
6504 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
6505 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
6506 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
6507 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
6508 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
6509 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
6510 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
6511 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
6512 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
6513 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
6514 *
6515 * (*) value not defined in all devices.
6516 * @retval None
6517 */
6518 __STATIC_INLINE void LL_C2_APB2_GRP1_DisableClock(uint32_t Periphs)
6519 {
6520 CLEAR_BIT(RCC_C2->APB2ENR, Periphs);
6521 }
6522
6523 /**
6524 * @brief Enable C2 APB2 peripherals clock during Low Power (Sleep) mode.
6525 * @rmtoll APB2LPENR TIM1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6526 * APB2LPENR TIM8LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6527 * APB2LPENR USART1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6528 * APB2LPENR USART6LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6529 * APB2LPENR SPI1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6530 * APB2LPENR SPI4LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6531 * APB2LPENR TIM15LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6532 * APB2LPENR TIM16LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6533 * APB2LPENR TIM17LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6534 * APB2LPENR SPI5LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6535 * APB2LPENR SAI1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6536 * APB2LPENR SAI2LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6537 * APB2LPENR SAI3LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6538 * APB2LPENR DFSDM1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6539 * APB2LPENR HRTIMLPEN LL_C2_APB2_GRP1_EnableClockSleep
6540 * @param Periphs This parameter can be a combination of the following values:
6541 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
6542 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
6543 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
6544 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
6545 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
6546 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
6547 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
6548 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
6549 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
6550 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
6551 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
6552 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
6553 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
6554 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
6555 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
6556 *
6557 * (*) value not defined in all devices.
6558 * @retval None
6559 */
6560 __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
6561 {
6562 __IO uint32_t tmpreg;
6563 SET_BIT(RCC_C2->APB2LPENR, Periphs);
6564 /* Delay after an RCC peripheral clock enabling */
6565 tmpreg = READ_BIT(RCC_C2->APB2LPENR, Periphs);
6566 (void)tmpreg;
6567 }
6568
6569 /**
6570 * @brief Disable C2 APB2 peripherals clock during Low Power (Sleep) mode.
6571 * @rmtoll APB2LPENR TIM1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6572 * APB2LPENR TIM8LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6573 * APB2LPENR USART1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6574 * APB2LPENR USART6LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6575 * APB2LPENR SPI1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6576 * APB2LPENR SPI4LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6577 * APB2LPENR TIM15LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6578 * APB2LPENR TIM16LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6579 * APB2LPENR TIM17LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6580 * APB2LPENR SPI5LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6581 * APB2LPENR SAI1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6582 * APB2LPENR SAI2LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6583 * APB2LPENR SAI3LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6584 * APB2LPENR DFSDM1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6585 * APB2LPENR HRTIMLPEN LL_C2_APB2_GRP1_DisableClockSleep
6586 * @param Periphs This parameter can be a combination of the following values:
6587 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
6588 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
6589 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
6590 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
6591 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
6592 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
6593 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
6594 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
6595 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
6596 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
6597 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
6598 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
6599 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
6600 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
6601 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
6602 *
6603 * (*) value not defined in all devices.
6604 * @retval None
6605 */
6606 __STATIC_INLINE void LL_C2_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
6607 {
6608 CLEAR_BIT(RCC_C2->APB2LPENR, Periphs);
6609 }
6610
6611 /**
6612 * @}
6613 */
6614
6615 /** @addtogroup BUS_LL_EF_APB4 APB4
6616 * @{
6617 */
6618
6619 /**
6620 * @brief Enable C2 APB4 peripherals clock.
6621 * @rmtoll APB4ENR SYSCFGEN LL_C2_APB4_GRP1_EnableClock\n
6622 * APB4ENR LPUART1EN LL_C2_APB4_GRP1_EnableClock\n
6623 * APB4ENR SPI6EN LL_C2_APB4_GRP1_EnableClock\n
6624 * APB4ENR I2C4EN LL_C2_APB4_GRP1_EnableClock\n
6625 * APB4ENR LPTIM2EN LL_C2_APB4_GRP1_EnableClock\n
6626 * APB4ENR LPTIM3EN LL_C2_APB4_GRP1_EnableClock\n
6627 * APB4ENR LPTIM4EN LL_C2_APB4_GRP1_EnableClock\n
6628 * APB4ENR LPTIM5EN LL_C2_APB4_GRP1_EnableClock\n
6629 * APB4ENR COMP12EN LL_C2_APB4_GRP1_EnableClock\n
6630 * APB4ENR VREFEN LL_C2_APB4_GRP1_EnableClock\n
6631 * APB4ENR RTCAPBEN LL_C2_APB4_GRP1_EnableClock\n
6632 * APB4ENR SAI4EN LL_C2_APB4_GRP1_EnableClock
6633 * @param Periphs This parameter can be a combination of the following values:
6634 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
6635 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
6636 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
6637 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
6638 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
6639 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
6640 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
6641 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
6642 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
6643 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
6644 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
6645 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
6646 *
6647 * (*) value not defined in all devices
6648 * @retval None
6649 */
6650 __STATIC_INLINE void LL_C2_APB4_GRP1_EnableClock(uint32_t Periphs)
6651 {
6652 __IO uint32_t tmpreg;
6653 SET_BIT(RCC_C2->APB4ENR, Periphs);
6654 /* Delay after an RCC peripheral clock enabling */
6655 tmpreg = READ_BIT(RCC_C2->APB4ENR, Periphs);
6656 (void)tmpreg;
6657 }
6658
6659 /**
6660 * @brief Check if C2 APB4 peripheral clock is enabled or not
6661 * @rmtoll APB4ENR SYSCFGEN LL_C2_APB4_GRP1_IsEnabledClock\n
6662 * APB4ENR LPUART1EN LL_C2_APB4_GRP1_IsEnabledClock\n
6663 * APB4ENR SPI6EN LL_C2_APB4_GRP1_IsEnabledClock\n
6664 * APB4ENR I2C4EN LL_C2_APB4_GRP1_IsEnabledClock\n
6665 * APB4ENR LPTIM2EN LL_C2_APB4_GRP1_IsEnabledClock\n
6666 * APB4ENR LPTIM3EN LL_C2_APB4_GRP1_IsEnabledClock\n
6667 * APB4ENR LPTIM4EN LL_C2_APB4_GRP1_IsEnabledClock\n
6668 * APB4ENR LPTIM5EN LL_C2_APB4_GRP1_IsEnabledClock\n
6669 * APB4ENR COMP12EN LL_C2_APB4_GRP1_IsEnabledClock\n
6670 * APB4ENR VREFEN LL_C2_APB4_GRP1_IsEnabledClock\n
6671 * APB4ENR RTCAPBEN LL_C2_APB4_GRP1_IsEnabledClock\n
6672 * APB4ENR SAI4EN LL_C2_APB4_GRP1_IsEnabledClock
6673 * @param Periphs This parameter can be a combination of the following values:
6674 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
6675 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
6676 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
6677 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
6678 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
6679 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
6680 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
6681 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
6682 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
6683 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
6684 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
6685 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
6686 *
6687 * (*) value not defined in all devices
6688 * @retval uint32_t
6689 */
6690 __STATIC_INLINE uint32_t LL_C2_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
6691 {
6692 return ((READ_BIT(RCC_C2->APB4ENR, Periphs) == Periphs)?1U:0U);
6693 }
6694
6695 /**
6696 * @brief Disable C2 APB4 peripherals clock.
6697 * @rmtoll APB4ENR SYSCFGEN LL_C2_APB4_GRP1_DisableClock\n
6698 * APB4ENR LPUART1EN LL_C2_APB4_GRP1_DisableClock\n
6699 * APB4ENR SPI6EN LL_C2_APB4_GRP1_DisableClock\n
6700 * APB4ENR I2C4EN LL_C2_APB4_GRP1_DisableClock\n
6701 * APB4ENR LPTIM2EN LL_C2_APB4_GRP1_DisableClock\n
6702 * APB4ENR LPTIM3EN LL_C2_APB4_GRP1_DisableClock\n
6703 * APB4ENR LPTIM4EN LL_C2_APB4_GRP1_DisableClock\n
6704 * APB4ENR LPTIM5EN LL_C2_APB4_GRP1_DisableClock\n
6705 * APB4ENR COMP12EN LL_C2_APB4_GRP1_DisableClock\n
6706 * APB4ENR VREFEN LL_C2_APB4_GRP1_DisableClock\n
6707 * APB4ENR RTCAPBEN LL_C2_APB4_GRP1_DisableClock\n
6708 * APB4ENR SAI4EN LL_C2_APB4_GRP1_DisableClock
6709 * @param Periphs This parameter can be a combination of the following values:
6710 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
6711 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
6712 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
6713 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
6714 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
6715 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
6716 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
6717 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
6718 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
6719 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
6720 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
6721 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
6722 *
6723 * (*) value not defined in all devices
6724 * @retval None
6725 */
6726 __STATIC_INLINE void LL_C2_APB4_GRP1_DisableClock(uint32_t Periphs)
6727 {
6728 CLEAR_BIT(RCC_C2->APB4ENR, Periphs);
6729 }
6730
6731 /**
6732 * @brief Enable C2 APB4 peripherals clock during Low Power (Sleep) mode.
6733 * @rmtoll APB4LPENR SYSCFGLPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6734 * APB4LPENR LPUART1LPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6735 * APB4LPENR SPI6LPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6736 * APB4LPENR I2C4LPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6737 * APB4LPENR LPTIM2LPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6738 * APB4LPENR LPTIM3LPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6739 * APB4LPENR LPTIM4LPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6740 * APB4LPENR LPTIM5LPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6741 * APB4LPENR COMP12LPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6742 * APB4LPENR VREFLPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6743 * APB4LPENR RTCAPBLPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6744 * APB4LPENR SAI4LPEN LL_C2_APB4_GRP1_EnableClockSleep
6745 * @param Periphs This parameter can be a combination of the following values:
6746 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
6747 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
6748 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
6749 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
6750 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
6751 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
6752 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
6753 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
6754 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
6755 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
6756 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
6757 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
6758 *
6759 * (*) value not defined in all devices
6760 * @retval None
6761 */
6762 __STATIC_INLINE void LL_C2_APB4_GRP1_EnableClockSleep(uint32_t Periphs)
6763 {
6764 __IO uint32_t tmpreg;
6765 SET_BIT(RCC_C2->APB4LPENR, Periphs);
6766 /* Delay after an RCC peripheral clock enabling */
6767 tmpreg = READ_BIT(RCC_C2->APB4LPENR, Periphs);
6768 (void)tmpreg;
6769 }
6770
6771 /**
6772 * @brief Disable C2 APB4 peripherals clock during Low Power (Sleep) mode.
6773 * @rmtoll APB4LPENR SYSCFGLPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6774 * APB4LPENR LPUART1LPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6775 * APB4LPENR SPI6LPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6776 * APB4LPENR I2C4LPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6777 * APB4LPENR LPTIM2LPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6778 * APB4LPENR LPTIM3LPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6779 * APB4LPENR LPTIM4LPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6780 * APB4LPENR LPTIM5LPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6781 * APB4LPENR COMP12LPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6782 * APB4LPENR VREFLPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6783 * APB4LPENR RTCAPBLPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6784 * APB4LPENR SAI4LPEN LL_C2_APB4_GRP1_DisableClockSleep
6785 * @param Periphs This parameter can be a combination of the following values:
6786 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
6787 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
6788 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
6789 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
6790 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
6791 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
6792 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
6793 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
6794 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
6795 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
6796 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
6797 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
6798 *
6799 * (*) value not defined in all devices
6800 * @retval None
6801 */
6802 __STATIC_INLINE void LL_C2_APB4_GRP1_DisableClockSleep(uint32_t Periphs)
6803 {
6804 CLEAR_BIT(RCC_C2->APB4LPENR, Periphs);
6805 }
6806
6807 /**
6808 * @}
6809 */
6810
6811 #endif /*DUAL_CORE*/
6812
6813 /**
6814 * @}
6815 */
6816
6817 /**
6818 * @}
6819 */
6820
6821 #endif /* defined(RCC) */
6822
6823 /**
6824 * @}
6825 */
6826
6827 #ifdef __cplusplus
6828 }
6829 #endif
6830
6831 #endif /* STM32H7xx_LL_BUS_H */
6832
6833 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/