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Merge pull request #11270 from haslinghuis/rename_attr
[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_ll_dac.h
blob5870a17250e890d0b12913bda366b612e3b50b1b
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_dac.h
4 * @author MCD Application Team
5 * @brief Header file of DAC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_LL_DAC_H
22 #define STM32H7xx_LL_DAC_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx.h"
30
31 /** @addtogroup STM32H7xx_LL_Driver
32 * @{
33 */
34
35 #if defined(DAC1) || defined(DAC2)
36
37 /** @defgroup DAC_LL DAC
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
46 * @{
47 */
48
49 /* Internal masks for DAC channels definition */
50 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
51 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
52 /* - channel bits position into register SWTRIG */
53 /* - channel register offset of data holding register DHRx */
54 /* - channel register offset of data output register DORx */
55 /* - channel register offset of sample-and-hold sample time register SHSRx */
56 #define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
57 #define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
58 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
59
60 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
61 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
62 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
63
64 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
65 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
66 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
67 #define DAC_REG_DHR12R2_REGOFFSET 0x30000000UL /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */
68 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
69 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
70 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
71 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
72 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
73 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
74
75 #define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
76 #define DAC_REG_DOR2_REGOFFSET 0x00000020UL /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 5 bits) */
77 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
78 #define DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */
79 #define DAC_REG_SHSR2_REGOFFSET 0x00000040UL /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 6 bits) */
80 #define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
81
82
83 #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx, DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
84 #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted to position 0 */
85 #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted to position 0 */
86
87 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */
88 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
89 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
90 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 5 bits) */
91 #define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx channel 1 or 2 versus SHSRx channel 1 (shifted left of 6 bits) */
92
93 /* DAC registers bits positions */
94 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
95 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
96 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
97
98 /* Miscellaneous data */
99 #define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
100
101 /**
102 * @}
103 */
104
105
106 /* Private macros ------------------------------------------------------------*/
107 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
108 * @{
109 */
110
111 /**
112 * @brief Driver macro reserved for internal use: set a pointer to
113 * a register from a register basis from which an offset
114 * is applied.
115 * @param __REG__ Register basis from which the offset is applied.
116 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
117 * @retval Pointer to register address
118 */
119 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
120 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
121
122 /**
123 * @}
124 */
125
126
127 /* Exported types ------------------------------------------------------------*/
128 #if defined(USE_FULL_LL_DRIVER)
129 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
130 * @{
131 */
132
133 /**
134 * @brief Structure definition of some features of DAC instance.
135 */
136 typedef struct
137 {
138 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external peripheral (timer event, external interrupt line).
139 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
140
141 This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
142
143 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
144 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
145
146 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
147
148 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
149 If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
150 If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
151 @note If waveform automatic generation mode is disabled, this parameter is discarded.
152
153 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR(), @ref LL_DAC_SetWaveTriangleAmplitude()
154 depending on the wave automatic generation selected. */
155
156 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
157 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
158
159 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
160
161 uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel.
162 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
163
164 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputConnection(). */
165
166 uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC channel.
167 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
168
169 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputMode(). */
170 } LL_DAC_InitTypeDef;
171
172 /**
173 * @}
174 */
175 #endif /* USE_FULL_LL_DRIVER */
176
177 /* Exported constants --------------------------------------------------------*/
178 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
179 * @{
180 */
181
182 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
183 * @brief Flags defines which can be used with LL_DAC_ReadReg function
184 * @{
185 */
186 /* DAC channel 1 flags */
187 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
188 #define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */
189 #define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1) /*!< DAC channel 1 flag busy writing sample time */
190
191 /* DAC channel 2 flags */
192 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
193 #define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */
194 #define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2) /*!< DAC channel 2 flag busy writing sample time */
195 /**
196 * @}
197 */
198
199 /** @defgroup DAC_LL_EC_IT DAC interruptions
200 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
201 * @{
202 */
203 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
204 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
205 /**
206 * @}
207 */
208
209 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
210 * @{
211 */
212 #define LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
213 #define LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
214 /**
215 * @}
216 */
217
218 /** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode
219 * @{
220 */
221 #define LL_DAC_MODE_NORMAL_OPERATION 0x00000000UL /*!< DAC channel in mode normal operation */
222 #define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1) /*!< DAC channel in mode calibration */
223 /**
224 * @}
225 */
226
227 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
228 * @{
229 */
230 #define LL_DAC_TRIG_SOFTWARE 0x00000000U /*!< DAC channel conversion trigger internal (SW start) */
231 #define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM1 TRGO. */
232 #define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */
233 #define LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */
234 #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */
235 #define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */
236 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */
237 #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */
238 #define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. */
239 #if defined (HRTIM1)
240 #define LL_DAC_TRIG_EXT_HRTIM_TRGO1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0) /*!< HR1 TRGO1 selected as external conversion trigger for DAC channel 1 */
241 #define LL_DAC_TRIG_EXT_HRTIM_TRGO2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 ) /*!< HR1 TRGO2 selected as external conversion trigger for DAC channel 2 */
242 #endif
243 #define LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: LPTIM1 TRGO. */
244 #define LL_DAC_TRIG_EXT_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM2 TRGO. */
245 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */
246 #if defined(TIM23)
247 #define LL_DAC_TRIG_EXT_TIM23_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM23 TRGO. */
248 #endif
249 #if defined(TIM24)
250 #define LL_DAC_TRIG_EXT_TIM24_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM24 TRGO. */
251 #endif
252 #if defined (DAC2)
253 #define LL_DAC_TRIG_EXT_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM3 TRGO. */
254 #endif
255 /**
256 * @}
257 */
258
259 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
260 * @{
261 */
262 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */
263 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
264 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
265 /**
266 * @}
267 */
268
269 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
270 * @{
271 */
272 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
273 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
274 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
275 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
276 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
277 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
278 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
279 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
280 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
281 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
282 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
283 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
284 /**
285 * @}
286 */
287
288 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
289 * @{
290 */
291 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
292 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
293 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
294 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
295 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
296 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
297 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
298 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
299 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
300 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
301 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
302 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
303 /**
304 * @}
305 */
306
307 /** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode
308 * @{
309 */
310 #define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000UL /*!< The selected DAC channel output is on mode normal. */
311 #define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2) /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */
312 /**
313 * @}
314 */
315
316 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
317 * @{
318 */
319 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
320 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
321 /**
322 * @}
323 */
324
325 /** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection
326 * @{
327 */
328 #define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000UL /*!< The selected DAC channel output is connected to external pin */
329 #define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 serie, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
330 /**
331 * @}
332 */
333
334 /** @defgroup DAC_LL_EC_LEGACY DAC literals legacy naming
335 * @{
336 */
337 #define LL_DAC_TRIGGER_SOFTWARE (LL_DAC_TRIG_SOFTWARE)
338 #define LL_DAC_TRIGGER_TIM2_TRGO (LL_DAC_TRIG_EXT_TIM2_TRGO)
339 #define LL_DAC_TRIGGER_TIM4_TRGO (LL_DAC_TRIG_EXT_TIM4_TRGO)
340 #define LL_DAC_TRIGGER_TIM6_TRGO (LL_DAC_TRIG_EXT_TIM6_TRGO)
341 #define LL_DAC_TRIGGER_TIM7_TRGO (LL_DAC_TRIG_EXT_TIM7_TRGO)
342 #define LL_DAC_TRIGGER_TIM8_TRGO (LL_DAC_TRIG_EXT_TIM8_TRGO)
343 #define LL_DAC_TRIGGER_EXT_IT9 (LL_DAC_TRIG_EXT_EXTI_LINE9)
344
345 #define LL_DAC_WAVEGENERATION_NONE (LL_DAC_WAVE_AUTO_GENERATION_NONE)
346 #define LL_DAC_WAVEGENERATION_NOISE (LL_DAC_WAVE_AUTO_GENERATION_NOISE)
347 #define LL_DAC_WAVEGENERATION_TRIANGLE (LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE)
348
349 #define LL_DAC_CONNECT_GPIO (LL_DAC_OUTPUT_CONNECT_GPIO)
350 #define LL_DAC_CONNECT_INTERNAL (LL_DAC_OUTPUT_CONNECT_INTERNAL)
351 /**
352 * @}
353 */
354 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
355 * @{
356 */
357 #define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */
358 #define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */
359 /**
360 * @}
361 */
362
363 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
364 * @{
365 */
366 /* List of DAC registers intended to be used (most commonly) with */
367 /* DMA transfer. */
368 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
369 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
370 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
371 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
372 /**
373 * @}
374 */
375
376 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
377 * @note Only DAC peripheral HW delays are defined in DAC LL driver driver,
378 * not timeout values.
379 * For details on delays values, refer to descriptions in source code
380 * above each literal definition.
381 * @{
382 */
383
384 /* Delay for DAC channel voltage settling time from DAC channel startup */
385 /* (transition from disable to enable). */
386 /* Note: DAC channel startup time depends on board application environment: */
387 /* impedance connected to DAC channel output. */
388 /* The delay below is specified under conditions: */
389 /* - voltage maximum transition (lowest to highest value) */
390 /* - until voltage reaches final value +-1LSB */
391 /* - DAC channel output buffer enabled */
392 /* - load impedance of 5kOhm (min), 50pF (max) */
393 /* Literal set to maximum value (refer to device datasheet, */
394 /* parameter "tWAKEUP"). */
395 /* Unit: us */
396 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
397
398 /* Delay for DAC channel voltage settling time. */
399 /* Note: DAC channel startup time depends on board application environment: */
400 /* impedance connected to DAC channel output. */
401 /* The delay below is specified under conditions: */
402 /* - voltage maximum transition (lowest to highest value) */
403 /* - until voltage reaches final value +-1LSB */
404 /* - DAC channel output buffer enabled */
405 /* - load impedance of 5kOhm min, 50pF max */
406 /* Literal set to maximum value (refer to device datasheet, */
407 /* parameter "tSETTLING"). */
408 /* Unit: us */
409 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3UL /*!< Delay for DAC channel voltage settling time */
410
411 /**
412 * @}
413 */
414
415 /**
416 * @}
417 */
418
419 /* Exported macro ------------------------------------------------------------*/
420 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
421 * @{
422 */
423
424 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
425 * @{
426 */
427
428 /**
429 * @brief Write a value in DAC register
430 * @param __INSTANCE__ DAC Instance
431 * @param __REG__ Register to be written
432 * @param __VALUE__ Value to be written in the register
433 * @retval None
434 */
435 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
436
437 /**
438 * @brief Read a value in DAC register
439 * @param __INSTANCE__ DAC Instance
440 * @param __REG__ Register to be read
441 * @retval Register value
442 */
443 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
444
445 /**
446 * @}
447 */
448
449 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
450 * @{
451 */
452
453 /**
454 * @brief Helper macro to get DAC channel number in decimal format
455 * from literals LL_DAC_CHANNEL_x.
456 * Example:
457 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
458 * will return decimal number "1".
459 * @note The input can be a value from functions where a channel
460 * number is returned.
461 * @param __CHANNEL__ This parameter can be one of the following values:
462 * @arg @ref LL_DAC_CHANNEL_1
463 * @arg @ref LL_DAC_CHANNEL_2
464 * @retval 1...2
465 */
466 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
467 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
468
469 /**
470 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
471 * from number in decimal format.
472 * Example:
473 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
474 * will return a data equivalent to "LL_DAC_CHANNEL_1".
475 * @note If the input parameter does not correspond to a DAC channel,
476 * this macro returns value '0'.
477 * @param __DECIMAL_NB__ 1...2
478 * @retval Returned value can be one of the following values:
479 * @arg @ref LL_DAC_CHANNEL_1
480 * @arg @ref LL_DAC_CHANNEL_2
481 */
482 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
483 (((__DECIMAL_NB__) == 1UL) \
484 ? ( \
485 LL_DAC_CHANNEL_1 \
486 ) \
487 : \
488 (((__DECIMAL_NB__) == 2UL) \
489 ? ( \
490 LL_DAC_CHANNEL_2 \
491 ) \
492 : \
493 ( \
494 0UL \
495 ) \
496 ) \
497 )
498
499 /**
500 * @brief Helper macro to define the DAC conversion data full-scale digital
501 * value corresponding to the selected DAC resolution.
502 * @note DAC conversion data full-scale corresponds to voltage range
503 * determined by analog voltage references Vref+ and Vref-
504 * (refer to reference manual).
505 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
506 * @arg @ref LL_DAC_RESOLUTION_12B
507 * @arg @ref LL_DAC_RESOLUTION_8B
508 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
509 */
510 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
511 ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
512
513 /**
514 * @brief Helper macro to calculate the DAC conversion data (unit: digital
515 * value) corresponding to a voltage (unit: mVolt).
516 * @note This helper macro is intended to provide input data in voltage
517 * rather than digital value,
518 * to be used with LL DAC functions such as
519 * @ref LL_DAC_ConvertData12RightAligned().
520 * @note Analog reference voltage (Vref+) must be either known from
521 * user board environment or can be calculated using ADC measurement
522 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
523 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
524 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
525 * (unit: mVolt).
526 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
527 * @arg @ref LL_DAC_RESOLUTION_12B
528 * @arg @ref LL_DAC_RESOLUTION_8B
529 * @retval DAC conversion data (unit: digital value)
530 */
531 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
532 __DAC_VOLTAGE__,\
533 __DAC_RESOLUTION__) \
534 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
535 / (__VREFANALOG_VOLTAGE__) \
536 )
537
538 /**
539 * @}
540 */
541
542 /**
543 * @}
544 */
545
546
547 /* Exported functions --------------------------------------------------------*/
548 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
549 * @{
550 */
551 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
552 * @{
553 */
554
555 /**
556 * @brief Set the operating mode for the selected DAC channel:
557 * calibration or normal operating mode.
558 * @rmtoll CR CEN1 LL_DAC_SetMode\n
559 * CR CEN2 LL_DAC_SetMode
560 * @param DACx DAC instance
561 * @param DAC_Channel This parameter can be one of the following values:
562 * @arg @ref LL_DAC_CHANNEL_1
563 * @arg @ref LL_DAC_CHANNEL_2
564 * @param ChannelMode This parameter can be one of the following values:
565 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION
566 * @arg @ref LL_DAC_MODE_CALIBRATION
567 * @retval None
568 */
569 __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
570 {
571 MODIFY_REG(DACx->CR,
572 DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
573 ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
574 }
575
576 /**
577 * @brief Get the operating mode for the selected DAC channel:
578 * calibration or normal operating mode.
579 * @rmtoll CR CEN1 LL_DAC_GetMode\n
580 * CR CEN2 LL_DAC_GetMode
581 * @param DACx DAC instance
582 * @param DAC_Channel This parameter can be one of the following values:
583 * @arg @ref LL_DAC_CHANNEL_1
584 * @arg @ref LL_DAC_CHANNEL_2
585 * @retval Returned value can be one of the following values:
586 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION
587 * @arg @ref LL_DAC_MODE_CALIBRATION
588 */
589 __STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
590 {
591 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
592 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
593 );
594 }
595
596 /**
597 * @brief Set the offset trimming value for the selected DAC channel.
598 * Trimming has an impact when output buffer is enabled
599 * and is intended to replace factory calibration default values.
600 * @rmtoll CCR OTRIM1 LL_DAC_SetTrimmingValue\n
601 * CCR OTRIM2 LL_DAC_SetTrimmingValue
602 * @param DACx DAC instance
603 * @param DAC_Channel This parameter can be one of the following values:
604 * @arg @ref LL_DAC_CHANNEL_1
605 * @arg @ref LL_DAC_CHANNEL_2
606 * @param TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
607 * @retval None
608 */
609 __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
610 {
611 MODIFY_REG(DACx->CCR,
612 DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
613 TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
614 }
615
616 /**
617 * @brief Get the offset trimming value for the selected DAC channel.
618 * Trimming has an impact when output buffer is enabled
619 * and is intended to replace factory calibration default values.
620 * @rmtoll CCR OTRIM1 LL_DAC_GetTrimmingValue\n
621 * CCR OTRIM2 LL_DAC_GetTrimmingValue
622 * @param DACx DAC instance
623 * @param DAC_Channel This parameter can be one of the following values:
624 * @arg @ref LL_DAC_CHANNEL_1
625 * @arg @ref LL_DAC_CHANNEL_2
626 * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
627 */
628 __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel)
629 {
630 return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
631 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
632 );
633 }
634
635 /**
636 * @brief Set the conversion trigger source for the selected DAC channel.
637 * @note For conversion trigger source to be effective, DAC trigger
638 * must be enabled using function @ref LL_DAC_EnableTrigger().
639 * @note To set conversion trigger source, DAC channel must be disabled.
640 * Otherwise, the setting is discarded.
641 * @note Availability of parameters of trigger sources from timer
642 * depends on timers availability on the selected device.
643 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
644 * CR TSEL2 LL_DAC_SetTriggerSource
645 * @param DACx DAC instance
646 * @param DAC_Channel This parameter can be one of the following values:
647 * @arg @ref LL_DAC_CHANNEL_1
648 * @arg @ref LL_DAC_CHANNEL_2
649 * @param TriggerSource This parameter can be one of the following values:
650 * @arg @ref LL_DAC_TRIG_SOFTWARE
651 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
652 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
653 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
654 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
655 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
656 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
657 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
658 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
659 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1 (1)
660 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2 (1)
661 * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
662 * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT
663 * @arg @ref LL_DAC_TRIG_EXT_LPTIM3_OUT (2)
664 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
665 * @arg @ref LL_DAC_TRIG_EXT_TIM23_TRGO (3)
666 * @arg @ref LL_DAC_TRIG_EXT_TIM24_TRGO (4)
667 *
668 * (1) On this STM32 serie, parameter not available on all devices.
669 * Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
670 * (2) On this STM32 serie, parameter only available on DAC2.
671 * (3) On this STM32 serie, parameter not available on all devices.
672 * Only available if TIM23 feature is supported (refer to device datasheet for supported features list)
673 * (4) On this STM32 serie, parameter not available on all devices.
674 * Only available if TIM24 feature is supported (refer to device datasheet for supported features list)
675 * @retval None
676 */
677 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
678 {
679 MODIFY_REG(DACx->CR,
680 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
681 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
682 }
683
684 /**
685 * @brief Get the conversion trigger source for the selected DAC channel.
686 * @note For conversion trigger source to be effective, DAC trigger
687 * must be enabled using function @ref LL_DAC_EnableTrigger().
688 * @note Availability of parameters of trigger sources from timer
689 * depends on timers availability on the selected device.
690 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
691 * CR TSEL2 LL_DAC_GetTriggerSource
692 * @param DACx DAC instance
693 * @param DAC_Channel This parameter can be one of the following values:
694 * @arg @ref LL_DAC_CHANNEL_1
695 * @arg @ref LL_DAC_CHANNEL_2
696 * @retval Returned value can be one of the following values:
697 * @arg @ref LL_DAC_TRIG_SOFTWARE
698 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
699 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
700 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
701 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
702 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
703 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
704 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
705 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
706 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1 (1)
707 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2 (1)
708 * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
709 * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT
710 * @arg @ref LL_DAC_TRIG_EXT_LPTIM3_OUT (2)
711 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
712 * @arg @ref LL_DAC_TRIG_EXT_TIM23_TRGO (3)
713 * @arg @ref LL_DAC_TRIG_EXT_TIM24_TRGO (4)
714 *
715 * (1) On this STM32 serie, parameter not available on all devices.
716 * Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
717 * (2) On this STM32 serie, parameter only available on DAC2.
718 * (3) On this STM32 serie, parameter not available on all devices.
719 * Only available if TIM23 feature is supported (refer to device datasheet for supported features list)
720 * (4) On this STM32 serie, parameter not available on all devices.
721 * Only available if TIM24 feature is supported (refer to device datasheet for supported features list)
722 */
723 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
724 {
725 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
726 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
727 );
728 }
729
730 /**
731 * @brief Set the waveform automatic generation mode
732 * for the selected DAC channel.
733 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
734 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
735 * @param DACx DAC instance
736 * @param DAC_Channel This parameter can be one of the following values:
737 * @arg @ref LL_DAC_CHANNEL_1
738 * @arg @ref LL_DAC_CHANNEL_2
739 * @param WaveAutoGeneration This parameter can be one of the following values:
740 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
741 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
742 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
743 * @retval None
744 */
745 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
746 {
747 MODIFY_REG(DACx->CR,
748 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
749 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
750 }
751
752 /**
753 * @brief Get the waveform automatic generation mode
754 * for the selected DAC channel.
755 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
756 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
757 * @param DACx DAC instance
758 * @param DAC_Channel This parameter can be one of the following values:
759 * @arg @ref LL_DAC_CHANNEL_1
760 * @arg @ref LL_DAC_CHANNEL_2
761 * @retval Returned value can be one of the following values:
762 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
763 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
764 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
765 */
766 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
767 {
768 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
769 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
770 );
771 }
772
773 /**
774 * @brief Set the noise waveform generation for the selected DAC channel:
775 * Noise mode and parameters LFSR (linear feedback shift register).
776 * @note For wave generation to be effective, DAC channel
777 * wave generation mode must be enabled using
778 * function @ref LL_DAC_SetWaveAutoGeneration().
779 * @note This setting can be set when the selected DAC channel is disabled
780 * (otherwise, the setting operation is ignored).
781 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
782 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
783 * @param DACx DAC instance
784 * @param DAC_Channel This parameter can be one of the following values:
785 * @arg @ref LL_DAC_CHANNEL_1
786 * @arg @ref LL_DAC_CHANNEL_2
787 * @param NoiseLFSRMask This parameter can be one of the following values:
788 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
789 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
790 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
791 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
792 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
793 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
794 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
795 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
796 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
797 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
798 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
799 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
800 * @retval None
801 */
802 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
803 {
804 MODIFY_REG(DACx->CR,
805 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
806 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
807 }
808
809 /**
810 * @brief Get the noise waveform generation for the selected DAC channel:
811 * Noise mode and parameters LFSR (linear feedback shift register).
812 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
813 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
814 * @param DACx DAC instance
815 * @param DAC_Channel This parameter can be one of the following values:
816 * @arg @ref LL_DAC_CHANNEL_1
817 * @arg @ref LL_DAC_CHANNEL_2
818 * @retval Returned value can be one of the following values:
819 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
820 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
821 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
822 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
823 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
824 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
825 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
826 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
827 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
828 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
829 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
830 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
831 */
832 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
833 {
834 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
835 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
836 );
837 }
838
839 /**
840 * @brief Set the triangle waveform generation for the selected DAC channel:
841 * triangle mode and amplitude.
842 * @note For wave generation to be effective, DAC channel
843 * wave generation mode must be enabled using
844 * function @ref LL_DAC_SetWaveAutoGeneration().
845 * @note This setting can be set when the selected DAC channel is disabled
846 * (otherwise, the setting operation is ignored).
847 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
848 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
849 * @param DACx DAC instance
850 * @param DAC_Channel This parameter can be one of the following values:
851 * @arg @ref LL_DAC_CHANNEL_1
852 * @arg @ref LL_DAC_CHANNEL_2
853 * @param TriangleAmplitude This parameter can be one of the following values:
854 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
855 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
856 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
857 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
858 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
859 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
860 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
861 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
862 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
863 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
864 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
865 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
866 * @retval None
867 */
868 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
869 uint32_t TriangleAmplitude)
870 {
871 MODIFY_REG(DACx->CR,
872 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
873 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
874 }
875
876 /**
877 * @brief Get the triangle waveform generation for the selected DAC channel:
878 * triangle mode and amplitude.
879 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
880 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
881 * @param DACx DAC instance
882 * @param DAC_Channel This parameter can be one of the following values:
883 * @arg @ref LL_DAC_CHANNEL_1
884 * @arg @ref LL_DAC_CHANNEL_2
885 * @retval Returned value can be one of the following values:
886 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
887 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
888 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
889 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
890 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
891 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
892 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
893 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
894 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
895 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
896 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
897 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
898 */
899 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
900 {
901 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
902 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
903 );
904 }
905
906 /**
907 * @brief Set the output for the selected DAC channel.
908 * @note This function set several features:
909 * - mode normal or sample-and-hold
910 * - buffer
911 * - connection to GPIO or internal path.
912 * These features can also be set individually using
913 * dedicated functions:
914 * - @ref LL_DAC_SetOutputBuffer()
915 * - @ref LL_DAC_SetOutputMode()
916 * - @ref LL_DAC_SetOutputConnection()
917 * @note On this STM32 serie, output connection depends on output mode
918 * (normal or sample and hold) and output buffer state.
919 * - if output connection is set to internal path and output buffer
920 * is enabled (whatever output mode):
921 * output connection is also connected to GPIO pin
922 * (both connections to GPIO pin and internal path).
923 * - if output connection is set to GPIO pin, output buffer
924 * is disabled, output mode set to sample and hold:
925 * output connection is also connected to internal path
926 * (both connections to GPIO pin and internal path).
927 * @note Mode sample-and-hold requires an external capacitor
928 * to be connected between DAC channel output and ground.
929 * Capacitor value depends on load on DAC channel output and
930 * sample-and-hold timings configured.
931 * As indication, capacitor typical value is 100nF
932 * (refer to device datasheet, parameter "CSH").
933 * @rmtoll CR MODE1 LL_DAC_ConfigOutput\n
934 * CR MODE2 LL_DAC_ConfigOutput
935 * @param DACx DAC instance
936 * @param DAC_Channel This parameter can be one of the following values:
937 * @arg @ref LL_DAC_CHANNEL_1
938 * @arg @ref LL_DAC_CHANNEL_2
939 * @param OutputMode This parameter can be one of the following values:
940 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
941 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
942 * @param OutputBuffer This parameter can be one of the following values:
943 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
944 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
945 * @param OutputConnection This parameter can be one of the following values:
946 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
947 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
948 * @retval None
949 */
950 __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode,
951 uint32_t OutputBuffer, uint32_t OutputConnection)
952 {
953 MODIFY_REG(DACx->MCR,
954 (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
955 (OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
956 }
957
958 /**
959 * @brief Set the output mode normal or sample-and-hold
960 * for the selected DAC channel.
961 * @note Mode sample-and-hold requires an external capacitor
962 * to be connected between DAC channel output and ground.
963 * Capacitor value depends on load on DAC channel output and
964 * sample-and-hold timings configured.
965 * As indication, capacitor typical value is 100nF
966 * (refer to device datasheet, parameter "CSH").
967 * @rmtoll CR MODE1 LL_DAC_SetOutputMode\n
968 * CR MODE2 LL_DAC_SetOutputMode
969 * @param DACx DAC instance
970 * @param DAC_Channel This parameter can be one of the following values:
971 * @arg @ref LL_DAC_CHANNEL_1
972 * @arg @ref LL_DAC_CHANNEL_2
973 * @param OutputMode This parameter can be one of the following values:
974 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
975 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
976 * @retval None
977 */
978 __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
979 {
980 MODIFY_REG(DACx->MCR,
981 (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
982 OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
983 }
984
985 /**
986 * @brief Get the output mode normal or sample-and-hold for the selected DAC channel.
987 * @rmtoll CR MODE1 LL_DAC_GetOutputMode\n
988 * CR MODE2 LL_DAC_GetOutputMode
989 * @param DACx DAC instance
990 * @param DAC_Channel This parameter can be one of the following values:
991 * @arg @ref LL_DAC_CHANNEL_1
992 * @arg @ref LL_DAC_CHANNEL_2
993 * @retval Returned value can be one of the following values:
994 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
995 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
996 */
997 __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
998 {
999 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1000 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1001 );
1002 }
1003
1004 /**
1005 * @brief Set the output buffer for the selected DAC channel.
1006 * @note On this STM32 serie, when buffer is enabled, its offset can be
1007 * trimmed: factory calibration default values can be
1008 * replaced by user trimming values, using function
1009 * @ref LL_DAC_SetTrimmingValue().
1010 * @rmtoll CR MODE1 LL_DAC_SetOutputBuffer\n
1011 * CR MODE2 LL_DAC_SetOutputBuffer
1012 * @param DACx DAC instance
1013 * @param DAC_Channel This parameter can be one of the following values:
1014 * @arg @ref LL_DAC_CHANNEL_1
1015 * @arg @ref LL_DAC_CHANNEL_2
1016 * @param OutputBuffer This parameter can be one of the following values:
1017 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
1018 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
1019 * @retval None
1020 */
1021 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
1022 {
1023 MODIFY_REG(DACx->MCR,
1024 (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1025 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1026 }
1027
1028 /**
1029 * @brief Get the output buffer state for the selected DAC channel.
1030 * @rmtoll CR MODE1 LL_DAC_GetOutputBuffer\n
1031 * CR MODE2 LL_DAC_GetOutputBuffer
1032 * @param DACx DAC instance
1033 * @param DAC_Channel This parameter can be one of the following values:
1034 * @arg @ref LL_DAC_CHANNEL_1
1035 * @arg @ref LL_DAC_CHANNEL_2
1036 * @retval Returned value can be one of the following values:
1037 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
1038 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
1039 */
1040 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1041 {
1042 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1043 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1044 );
1045 }
1046
1047 /**
1048 * @brief Set the output connection for the selected DAC channel.
1049 * @note On this STM32 serie, output connection depends on output mode (normal or
1050 * sample and hold) and output buffer state.
1051 * - if output connection is set to internal path and output buffer
1052 * is enabled (whatever output mode):
1053 * output connection is also connected to GPIO pin
1054 * (both connections to GPIO pin and internal path).
1055 * - if output connection is set to GPIO pin, output buffer
1056 * is disabled, output mode set to sample and hold:
1057 * output connection is also connected to internal path
1058 * (both connections to GPIO pin and internal path).
1059 * @rmtoll CR MODE1 LL_DAC_SetOutputConnection\n
1060 * CR MODE2 LL_DAC_SetOutputConnection
1061 * @param DACx DAC instance
1062 * @param DAC_Channel This parameter can be one of the following values:
1063 * @arg @ref LL_DAC_CHANNEL_1
1064 * @arg @ref LL_DAC_CHANNEL_2
1065 * @param OutputConnection This parameter can be one of the following values:
1066 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1067 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1068 * @retval None
1069 */
1070 __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
1071 {
1072 MODIFY_REG(DACx->MCR,
1073 (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1074 OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1075 }
1076
1077 /**
1078 * @brief Get the output connection for the selected DAC channel.
1079 * @note On this STM32 serie, output connection depends on output mode (normal or
1080 * sample and hold) and output buffer state.
1081 * - if output connection is set to internal path and output buffer
1082 * is enabled (whatever output mode):
1083 * output connection is also connected to GPIO pin
1084 * (both connections to GPIO pin and internal path).
1085 * - if output connection is set to GPIO pin, output buffer
1086 * is disabled, output mode set to sample and hold:
1087 * output connection is also connected to internal path
1088 * (both connections to GPIO pin and internal path).
1089 * @rmtoll CR MODE1 LL_DAC_GetOutputConnection\n
1090 * CR MODE2 LL_DAC_GetOutputConnection
1091 * @param DACx DAC instance
1092 * @param DAC_Channel This parameter can be one of the following values:
1093 * @arg @ref LL_DAC_CHANNEL_1
1094 * @arg @ref LL_DAC_CHANNEL_2
1095 * @retval Returned value can be one of the following values:
1096 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1097 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1098 */
1099 __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1100 {
1101 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1102 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1103 );
1104 }
1105
1106 /**
1107 * @brief Set the sample-and-hold timing for the selected DAC channel:
1108 * sample time
1109 * @note Sample time must be set when DAC channel is disabled
1110 * or during DAC operation when DAC channel flag BWSTx is reset,
1111 * otherwise the setting is ignored.
1112 * Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
1113 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_SetSampleAndHoldSampleTime\n
1114 * SHSR2 TSAMPLE2 LL_DAC_SetSampleAndHoldSampleTime
1115 * @param DACx DAC instance
1116 * @param DAC_Channel This parameter can be one of the following values:
1117 * @arg @ref LL_DAC_CHANNEL_1
1118 * @arg @ref LL_DAC_CHANNEL_2
1119 * @param SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF
1120 * @retval None
1121 */
1122 __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
1123 {
1124 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1125
1126 MODIFY_REG(*preg,
1127 DAC_SHSR1_TSAMPLE1,
1128 SampleTime);
1129 }
1130
1131 /**
1132 * @brief Get the sample-and-hold timing for the selected DAC channel:
1133 * sample time
1134 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_GetSampleAndHoldSampleTime\n
1135 * SHSR2 TSAMPLE2 LL_DAC_GetSampleAndHoldSampleTime
1136 * @param DACx DAC instance
1137 * @param DAC_Channel This parameter can be one of the following values:
1138 * @arg @ref LL_DAC_CHANNEL_1
1139 * @arg @ref LL_DAC_CHANNEL_2
1140 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1141 */
1142 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1143 {
1144 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1145
1146 return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
1147 }
1148
1149 /**
1150 * @brief Set the sample-and-hold timing for the selected DAC channel:
1151 * hold time
1152 * @rmtoll SHHR THOLD1 LL_DAC_SetSampleAndHoldHoldTime\n
1153 * SHHR THOLD2 LL_DAC_SetSampleAndHoldHoldTime
1154 * @param DACx DAC instance
1155 * @param DAC_Channel This parameter can be one of the following values:
1156 * @arg @ref LL_DAC_CHANNEL_1
1157 * @arg @ref LL_DAC_CHANNEL_2
1158 * @param HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF
1159 * @retval None
1160 */
1161 __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
1162 {
1163 MODIFY_REG(DACx->SHHR,
1164 DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1165 HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1166 }
1167
1168 /**
1169 * @brief Get the sample-and-hold timing for the selected DAC channel:
1170 * hold time
1171 * @rmtoll SHHR THOLD1 LL_DAC_GetSampleAndHoldHoldTime\n
1172 * SHHR THOLD2 LL_DAC_GetSampleAndHoldHoldTime
1173 * @param DACx DAC instance
1174 * @param DAC_Channel This parameter can be one of the following values:
1175 * @arg @ref LL_DAC_CHANNEL_1
1176 * @arg @ref LL_DAC_CHANNEL_2
1177 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1178 */
1179 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1180 {
1181 return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1182 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1183 );
1184 }
1185
1186 /**
1187 * @brief Set the sample-and-hold timing for the selected DAC channel:
1188 * refresh time
1189 * @rmtoll SHRR TREFRESH1 LL_DAC_SetSampleAndHoldRefreshTime\n
1190 * SHRR TREFRESH2 LL_DAC_SetSampleAndHoldRefreshTime
1191 * @param DACx DAC instance
1192 * @param DAC_Channel This parameter can be one of the following values:
1193 * @arg @ref LL_DAC_CHANNEL_1
1194 * @arg @ref LL_DAC_CHANNEL_2
1195 * @param RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF
1196 * @retval None
1197 */
1198 __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
1199 {
1200 MODIFY_REG(DACx->SHRR,
1201 DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1202 RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1203 }
1204
1205 /**
1206 * @brief Get the sample-and-hold timing for the selected DAC channel:
1207 * refresh time
1208 * @rmtoll SHRR TREFRESH1 LL_DAC_GetSampleAndHoldRefreshTime\n
1209 * SHRR TREFRESH2 LL_DAC_GetSampleAndHoldRefreshTime
1210 * @param DACx DAC instance
1211 * @param DAC_Channel This parameter can be one of the following values:
1212 * @arg @ref LL_DAC_CHANNEL_1
1213 * @arg @ref LL_DAC_CHANNEL_2
1214 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1215 */
1216 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1217 {
1218 return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1219 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1220 );
1221 }
1222
1223 /**
1224 * @}
1225 */
1226
1227 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
1228 * @{
1229 */
1230
1231 /**
1232 * @brief Enable DAC DMA transfer request of the selected channel.
1233 * @note To configure DMA source address (peripheral address),
1234 * use function @ref LL_DAC_DMA_GetRegAddr().
1235 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
1236 * CR DMAEN2 LL_DAC_EnableDMAReq
1237 * @param DACx DAC instance
1238 * @param DAC_Channel This parameter can be one of the following values:
1239 * @arg @ref LL_DAC_CHANNEL_1
1240 * @arg @ref LL_DAC_CHANNEL_2
1241 * @retval None
1242 */
1243 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1244 {
1245 SET_BIT(DACx->CR,
1246 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1247 }
1248
1249 /**
1250 * @brief Disable DAC DMA transfer request of the selected channel.
1251 * @note To configure DMA source address (peripheral address),
1252 * use function @ref LL_DAC_DMA_GetRegAddr().
1253 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
1254 * CR DMAEN2 LL_DAC_DisableDMAReq
1255 * @param DACx DAC instance
1256 * @param DAC_Channel This parameter can be one of the following values:
1257 * @arg @ref LL_DAC_CHANNEL_1
1258 * @arg @ref LL_DAC_CHANNEL_2
1259 * @retval None
1260 */
1261 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1262 {
1263 CLEAR_BIT(DACx->CR,
1264 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1265 }
1266
1267 /**
1268 * @brief Get DAC DMA transfer request state of the selected channel.
1269 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
1270 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
1271 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
1272 * @param DACx DAC instance
1273 * @param DAC_Channel This parameter can be one of the following values:
1274 * @arg @ref LL_DAC_CHANNEL_1
1275 * @arg @ref LL_DAC_CHANNEL_2
1276 * @retval State of bit (1 or 0).
1277 */
1278 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1279 {
1280 return ((READ_BIT(DACx->CR,
1281 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1282 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1283 }
1284
1285 /**
1286 * @brief Function to help to configure DMA transfer to DAC: retrieve the
1287 * DAC register address from DAC instance and a list of DAC registers
1288 * intended to be used (most commonly) with DMA transfer.
1289 * @note These DAC registers are data holding registers:
1290 * when DAC conversion is requested, DAC generates a DMA transfer
1291 * request to have data available in DAC data holding registers.
1292 * @note This macro is intended to be used with LL DMA driver, refer to
1293 * function "LL_DMA_ConfigAddresses()".
1294 * Example:
1295 * LL_DMA_ConfigAddresses(DMA1,
1296 * LL_DMA_CHANNEL_1,
1297 * (uint32_t)&< array or variable >,
1298 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
1299 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
1300 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1301 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1302 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1303 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
1304 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
1305 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
1306 * @param DACx DAC instance
1307 * @param DAC_Channel This parameter can be one of the following values:
1308 * @arg @ref LL_DAC_CHANNEL_1
1309 * @arg @ref LL_DAC_CHANNEL_2
1310 * @param Register This parameter can be one of the following values:
1311 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
1312 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
1313 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
1314 * @retval DAC register address
1315 */
1316 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
1317 {
1318 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
1319 /* DAC channel selected. */
1320 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1,
1321 ((DAC_Channel >> (Register & 0x1FUL)) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
1322 }
1323 /**
1324 * @}
1325 */
1326
1327 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
1328 * @{
1329 */
1330
1331 /**
1332 * @brief Enable DAC selected channel.
1333 * @rmtoll CR EN1 LL_DAC_Enable\n
1334 * CR EN2 LL_DAC_Enable
1335 * @note After enable from off state, DAC channel requires a delay
1336 * for output voltage to reach accuracy +/- 1 LSB.
1337 * Refer to device datasheet, parameter "tWAKEUP".
1338 * @param DACx DAC instance
1339 * @param DAC_Channel This parameter can be one of the following values:
1340 * @arg @ref LL_DAC_CHANNEL_1
1341 * @arg @ref LL_DAC_CHANNEL_2
1342 * @retval None
1343 */
1344 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1345 {
1346 SET_BIT(DACx->CR,
1347 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1348 }
1349
1350 /**
1351 * @brief Disable DAC selected channel.
1352 * @rmtoll CR EN1 LL_DAC_Disable\n
1353 * CR EN2 LL_DAC_Disable
1354 * @param DACx DAC instance
1355 * @param DAC_Channel This parameter can be one of the following values:
1356 * @arg @ref LL_DAC_CHANNEL_1
1357 * @arg @ref LL_DAC_CHANNEL_2
1358 * @retval None
1359 */
1360 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1361 {
1362 CLEAR_BIT(DACx->CR,
1363 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1364 }
1365
1366 /**
1367 * @brief Get DAC enable state of the selected channel.
1368 * (0: DAC channel is disabled, 1: DAC channel is enabled)
1369 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
1370 * CR EN2 LL_DAC_IsEnabled
1371 * @param DACx DAC instance
1372 * @param DAC_Channel This parameter can be one of the following values:
1373 * @arg @ref LL_DAC_CHANNEL_1
1374 * @arg @ref LL_DAC_CHANNEL_2
1375 * @retval State of bit (1 or 0).
1376 */
1377 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1378 {
1379 return ((READ_BIT(DACx->CR,
1380 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1381 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1382 }
1383
1384 /**
1385 * @brief Enable DAC trigger of the selected channel.
1386 * @note - If DAC trigger is disabled, DAC conversion is performed
1387 * automatically once the data holding register is updated,
1388 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1389 * @ref LL_DAC_ConvertData12RightAligned(), ...
1390 * - If DAC trigger is enabled, DAC conversion is performed
1391 * only when a hardware of software trigger event is occurring.
1392 * Select trigger source using
1393 * function @ref LL_DAC_SetTriggerSource().
1394 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
1395 * CR TEN2 LL_DAC_EnableTrigger
1396 * @param DACx DAC instance
1397 * @param DAC_Channel This parameter can be one of the following values:
1398 * @arg @ref LL_DAC_CHANNEL_1
1399 * @arg @ref LL_DAC_CHANNEL_2
1400 * @retval None
1401 */
1402 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1403 {
1404 SET_BIT(DACx->CR,
1405 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1406 }
1407
1408 /**
1409 * @brief Disable DAC trigger of the selected channel.
1410 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
1411 * CR TEN2 LL_DAC_DisableTrigger
1412 * @param DACx DAC instance
1413 * @param DAC_Channel This parameter can be one of the following values:
1414 * @arg @ref LL_DAC_CHANNEL_1
1415 * @arg @ref LL_DAC_CHANNEL_2
1416 * @retval None
1417 */
1418 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1419 {
1420 CLEAR_BIT(DACx->CR,
1421 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1422 }
1423
1424 /**
1425 * @brief Get DAC trigger state of the selected channel.
1426 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
1427 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
1428 * CR TEN2 LL_DAC_IsTriggerEnabled
1429 * @param DACx DAC instance
1430 * @param DAC_Channel This parameter can be one of the following values:
1431 * @arg @ref LL_DAC_CHANNEL_1
1432 * @arg @ref LL_DAC_CHANNEL_2
1433 * @retval State of bit (1 or 0).
1434 */
1435 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1436 {
1437 return ((READ_BIT(DACx->CR,
1438 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1439 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1440 }
1441
1442 /**
1443 * @brief Trig DAC conversion by software for the selected DAC channel.
1444 * @note Preliminarily, DAC trigger must be set to software trigger
1445 * using function
1446 * @ref LL_DAC_Init()
1447 * @ref LL_DAC_SetTriggerSource()
1448 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
1449 * and DAC trigger must be enabled using
1450 * function @ref LL_DAC_EnableTrigger().
1451 * @note For devices featuring DAC with 2 channels: this function
1452 * can perform a SW start of both DAC channels simultaneously.
1453 * Two channels can be selected as parameter.
1454 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
1455 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
1456 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
1457 * @param DACx DAC instance
1458 * @param DAC_Channel This parameter can a combination of the following values:
1459 * @arg @ref LL_DAC_CHANNEL_1
1460 * @arg @ref LL_DAC_CHANNEL_2
1461 * @retval None
1462 */
1463 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1464 {
1465 SET_BIT(DACx->SWTRIGR,
1466 (DAC_Channel & DAC_SWTR_CHX_MASK));
1467 }
1468
1469 /**
1470 * @brief Set the data to be loaded in the data holding register
1471 * in format 12 bits left alignment (LSB aligned on bit 0),
1472 * for the selected DAC channel.
1473 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
1474 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
1475 * @param DACx DAC instance
1476 * @param DAC_Channel This parameter can be one of the following values:
1477 * @arg @ref LL_DAC_CHANNEL_1
1478 * @arg @ref LL_DAC_CHANNEL_2
1479 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1480 * @retval None
1481 */
1482 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1483 {
1484 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1485
1486 MODIFY_REG(*preg,
1487 DAC_DHR12R1_DACC1DHR,
1488 Data);
1489 }
1490
1491 /**
1492 * @brief Set the data to be loaded in the data holding register
1493 * in format 12 bits left alignment (MSB aligned on bit 15),
1494 * for the selected DAC channel.
1495 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
1496 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
1497 * @param DACx DAC instance
1498 * @param DAC_Channel This parameter can be one of the following values:
1499 * @arg @ref LL_DAC_CHANNEL_1
1500 * @arg @ref LL_DAC_CHANNEL_2
1501 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1502 * @retval None
1503 */
1504 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1505 {
1506 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1507
1508 MODIFY_REG(*preg,
1509 DAC_DHR12L1_DACC1DHR,
1510 Data);
1511 }
1512
1513 /**
1514 * @brief Set the data to be loaded in the data holding register
1515 * in format 8 bits left alignment (LSB aligned on bit 0),
1516 * for the selected DAC channel.
1517 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
1518 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
1519 * @param DACx DAC instance
1520 * @param DAC_Channel This parameter can be one of the following values:
1521 * @arg @ref LL_DAC_CHANNEL_1
1522 * @arg @ref LL_DAC_CHANNEL_2
1523 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1524 * @retval None
1525 */
1526 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1527 {
1528 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1529
1530 MODIFY_REG(*preg,
1531 DAC_DHR8R1_DACC1DHR,
1532 Data);
1533 }
1534
1535
1536 /**
1537 * @brief Set the data to be loaded in the data holding register
1538 * in format 12 bits left alignment (LSB aligned on bit 0),
1539 * for both DAC channels.
1540 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
1541 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
1542 * @param DACx DAC instance
1543 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1544 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1545 * @retval None
1546 */
1547 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1548 uint32_t DataChannel2)
1549 {
1550 MODIFY_REG(DACx->DHR12RD,
1551 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
1552 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1553 }
1554
1555 /**
1556 * @brief Set the data to be loaded in the data holding register
1557 * in format 12 bits left alignment (MSB aligned on bit 15),
1558 * for both DAC channels.
1559 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
1560 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
1561 * @param DACx DAC instance
1562 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1563 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1564 * @retval None
1565 */
1566 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1567 uint32_t DataChannel2)
1568 {
1569 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
1570 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
1571 /* the 4 LSB must be taken into account for the shift value. */
1572 MODIFY_REG(DACx->DHR12LD,
1573 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
1574 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
1575 }
1576
1577 /**
1578 * @brief Set the data to be loaded in the data holding register
1579 * in format 8 bits left alignment (LSB aligned on bit 0),
1580 * for both DAC channels.
1581 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
1582 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
1583 * @param DACx DAC instance
1584 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
1585 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
1586 * @retval None
1587 */
1588 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1589 uint32_t DataChannel2)
1590 {
1591 MODIFY_REG(DACx->DHR8RD,
1592 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
1593 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1594 }
1595
1596
1597 /**
1598 * @brief Retrieve output data currently generated for the selected DAC channel.
1599 * @note Whatever alignment and resolution settings
1600 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1601 * @ref LL_DAC_ConvertData12RightAligned(), ...),
1602 * output data format is 12 bits right aligned (LSB aligned on bit 0).
1603 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
1604 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
1605 * @param DACx DAC instance
1606 * @param DAC_Channel This parameter can be one of the following values:
1607 * @arg @ref LL_DAC_CHANNEL_1
1608 * @arg @ref LL_DAC_CHANNEL_2
1609 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1610 */
1611 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1612 {
1613 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
1614
1615 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1616 }
1617
1618 /**
1619 * @}
1620 */
1621
1622 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
1623 * @{
1624 */
1625 /**
1626 * @brief Get DAC calibration offset flag for DAC channel 1
1627 * @rmtoll SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1
1628 * @param DACx DAC instance
1629 * @retval State of bit (1 or 0).
1630 */
1631 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx)
1632 {
1633 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL);
1634 }
1635
1636
1637 /**
1638 * @brief Get DAC calibration offset flag for DAC channel 2
1639 * @rmtoll SR CAL_FLAG2 LL_DAC_IsActiveFlag_CAL2
1640 * @param DACx DAC instance
1641 * @retval State of bit (1 or 0).
1642 */
1643 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx)
1644 {
1645 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL);
1646 }
1647
1648
1649 /**
1650 * @brief Get DAC busy writing sample time flag for DAC channel 1
1651 * @rmtoll SR BWST1 LL_DAC_IsActiveFlag_BWST1
1652 * @param DACx DAC instance
1653 * @retval State of bit (1 or 0).
1654 */
1655 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx)
1656 {
1657 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
1658 }
1659
1660
1661 /**
1662 * @brief Get DAC busy writing sample time flag for DAC channel 2
1663 * @rmtoll SR BWST2 LL_DAC_IsActiveFlag_BWST2
1664 * @param DACx DAC instance
1665 * @retval State of bit (1 or 0).
1666 */
1667 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx)
1668 {
1669 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL);
1670 }
1671
1672
1673 /**
1674 * @brief Get DAC underrun flag for DAC channel 1
1675 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
1676 * @param DACx DAC instance
1677 * @retval State of bit (1 or 0).
1678 */
1679 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
1680 {
1681 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
1682 }
1683
1684
1685 /**
1686 * @brief Get DAC underrun flag for DAC channel 2
1687 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
1688 * @param DACx DAC instance
1689 * @retval State of bit (1 or 0).
1690 */
1691 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
1692 {
1693 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
1694 }
1695
1696
1697 /**
1698 * @brief Clear DAC underrun flag for DAC channel 1
1699 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
1700 * @param DACx DAC instance
1701 * @retval None
1702 */
1703 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1704 {
1705 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1706 }
1707
1708
1709 /**
1710 * @brief Clear DAC underrun flag for DAC channel 2
1711 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
1712 * @param DACx DAC instance
1713 * @retval None
1714 */
1715 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
1716 {
1717 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
1718 }
1719
1720
1721 /**
1722 * @}
1723 */
1724
1725 /** @defgroup DAC_LL_EF_IT_Management IT management
1726 * @{
1727 */
1728
1729 /**
1730 * @brief Enable DMA underrun interrupt for DAC channel 1
1731 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
1732 * @param DACx DAC instance
1733 * @retval None
1734 */
1735 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1736 {
1737 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1738 }
1739
1740
1741 /**
1742 * @brief Enable DMA underrun interrupt for DAC channel 2
1743 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
1744 * @param DACx DAC instance
1745 * @retval None
1746 */
1747 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
1748 {
1749 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1750 }
1751
1752
1753 /**
1754 * @brief Disable DMA underrun interrupt for DAC channel 1
1755 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
1756 * @param DACx DAC instance
1757 * @retval None
1758 */
1759 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1760 {
1761 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1762 }
1763
1764
1765 /**
1766 * @brief Disable DMA underrun interrupt for DAC channel 2
1767 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
1768 * @param DACx DAC instance
1769 * @retval None
1770 */
1771 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
1772 {
1773 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1774 }
1775
1776
1777 /**
1778 * @brief Get DMA underrun interrupt for DAC channel 1
1779 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
1780 * @param DACx DAC instance
1781 * @retval State of bit (1 or 0).
1782 */
1783 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
1784 {
1785 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
1786 }
1787
1788
1789 /**
1790 * @brief Get DMA underrun interrupt for DAC channel 2
1791 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
1792 * @param DACx DAC instance
1793 * @retval State of bit (1 or 0).
1794 */
1795 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
1796 {
1797 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
1798 }
1799
1800
1801 /**
1802 * @}
1803 */
1804
1805 #if defined(USE_FULL_LL_DRIVER)
1806 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
1807 * @{
1808 */
1809
1810 ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);
1811 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct);
1812 void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
1813
1814 /**
1815 * @}
1816 */
1817 #endif /* USE_FULL_LL_DRIVER */
1818
1819 /**
1820 * @}
1821 */
1822
1823 /**
1824 * @}
1825 */
1826
1827 #endif /* DAC1 || DAC2 */
1828
1829 /**
1830 * @}
1831 */
1832
1833 #ifdef __cplusplus
1834 }
1835 #endif
1836
1837 #endif /* STM32H7xx_LL_DAC_H */
1838
1839 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/