| blob | 5dae9e13d34482ed4e75b5d198f292be46ce5222 |
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_LL_DMA_H
22 #define STM32H7xx_LL_DMA_H
24 #ifdef __cplusplus
26 #endif
28 /* Includes ------------------------------------------------------------------*/
32 /** @addtogroup STM32H7xx_LL_Driver
33 * @{
34 */
36 #if defined (DMA1) || defined (DMA2)
38 /** @defgroup DMA_LL DMA
39 * @{
40 */
42 /* Private types -------------------------------------------------------------*/
43 /* Private variables ---------------------------------------------------------*/
44 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
45 * @{
46 */
47 /* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
49 {
58 };
61 /**
62 * @}
63 */
65 /* Private macros ------------------------------------------------------------*/
67 /**
68 * @brief Helper macro to convert DMA Instance DMAx into DMAMUX channel
69 * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
70 * DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
71 * @param __DMA_INSTANCE__ DMAx
72 * @retval Channel_Offset (LL_DMAMUX_CHANNEL_8 or 0).
73 */
74 #define LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \
75 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0UL : 8UL)
77 /* Exported types ------------------------------------------------------------*/
78 #if defined(USE_FULL_LL_DRIVER)
79 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
80 * @{
81 */
83 {
85 or as Source base address in case of memory to memory transfer direction.
87 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
90 or as Destination base address in case of memory to memory transfer direction.
92 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
95 from memory to memory or from peripheral to memory.
96 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
98 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
101 This parameter can be a value of @ref DMA_LL_EC_MODE
102 @note The circular buffer mode cannot be used if the memory to memory
103 data transfer direction is configured on the selected Stream
105 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
107 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
108 is incremented or not.
109 This parameter can be a value of @ref DMA_LL_EC_PERIPH
111 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
113 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
114 is incremented or not.
115 This parameter can be a value of @ref DMA_LL_EC_MEMORY
117 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
119 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
120 in case of memory to memory transfer direction.
121 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
123 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
125 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
126 in case of memory to memory transfer direction.
127 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
129 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
132 The data unit is equal to the source buffer configuration set in PeripheralSize
133 or MemorySize parameters depending in the transfer direction.
134 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
136 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
139 This parameter can be a value of @ref DMAMUX1_Request_selection
141 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
144 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
146 This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
148 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
149 This parameter can be a value of @ref DMA_LL_FIFOMODE
150 @note The Direct mode (FIFO mode disabled) cannot be used if the
151 memory-to-memory data transfer is configured on the selected stream
153 This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
156 This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
158 This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
161 It specifies the amount of data to be transferred in a single non interruptible
162 transaction.
163 This parameter can be a value of @ref DMA_LL_EC_MBURST
164 @note The burst mode is possible only if the address Increment mode is enabled.
166 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
168 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
169 It specifies the amount of data to be transferred in a single non interruptible
170 transaction.
171 This parameter can be a value of @ref DMA_LL_EC_PBURST
172 @note The burst mode is possible only if the address Increment mode is enabled.
174 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
177 /**
178 * @}
179 */
181 /* Exported constants --------------------------------------------------------*/
182 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
183 * @{
184 */
186 /** @defgroup DMA_LL_EC_STREAM STREAM
187 * @{
188 */
189 #define LL_DMA_STREAM_0 0x00000000U
190 #define LL_DMA_STREAM_1 0x00000001U
191 #define LL_DMA_STREAM_2 0x00000002U
192 #define LL_DMA_STREAM_3 0x00000003U
193 #define LL_DMA_STREAM_4 0x00000004U
194 #define LL_DMA_STREAM_5 0x00000005U
195 #define LL_DMA_STREAM_6 0x00000006U
196 #define LL_DMA_STREAM_7 0x00000007U
197 #define LL_DMA_STREAM_ALL 0xFFFF0000U
198 /**
199 * @}
200 */
203 /** @defgroup DMA_LL_EC_DIRECTION DIRECTION
204 * @{
205 */
209 /**
210 * @}
211 */
213 /** @defgroup DMA_LL_EC_MODE MODE
214 * @{
215 */
219 /**
220 * @}
221 */
223 /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
224 * @{
225 */
228 /**
229 * @}
230 */
232 /** @defgroup DMA_LL_EC_PERIPH PERIPH
233 * @{
234 */
237 /**
238 * @}
239 */
241 /** @defgroup DMA_LL_EC_MEMORY MEMORY
242 * @{
243 */
246 /**
247 * @}
248 */
250 /** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
251 * @{
252 */
254 #define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
256 /**
257 * @}
258 */
260 /** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
261 * @{
262 */
266 /**
267 * @}
268 */
270 /** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
271 * @{
272 */
273 #define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */
274 #define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */
275 /**
276 * @}
277 */
279 /** @defgroup DMA_LL_EC_PRIORITY PRIORITY
280 * @{
281 */
286 /**
287 * @}
288 */
291 /** @defgroup DMA_LL_EC_MBURST MBURST
292 * @{
293 */
295 #define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */
296 #define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */
297 #define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */
298 /**
299 * @}
300 */
302 /** @defgroup DMA_LL_EC_PBURST PBURST
303 * @{
304 */
306 #define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */
307 #define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */
308 #define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */
309 /**
310 * @}
311 */
313 /** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
314 * @{
315 */
318 /**
319 * @}
320 */
322 /** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
323 * @{
324 */
328 #define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */
331 /**
332 * @}
333 */
335 /** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
336 * @{
337 */
340 #define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */
342 /**
343 * @}
344 */
346 /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
347 * @{
348 */
351 /**
352 * @}
353 */
355 /**
356 * @}
357 */
359 /* Exported macro ------------------------------------------------------------*/
360 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
361 * @{
362 */
364 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
365 * @{
366 */
367 /**
368 * @brief Write a value in DMA register
369 * @param __INSTANCE__ DMA Instance
370 * @param __REG__ Register to be written
371 * @param __VALUE__ Value to be written in the register
372 * @retval None
373 */
374 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
376 /**
377 * @brief Read a value in DMA register
378 * @param __INSTANCE__ DMA Instance
379 * @param __REG__ Register to be read
380 * @retval Register value
381 */
382 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
383 /**
384 * @}
385 */
387 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
388 * @{
389 */
390 /**
391 * @brief Convert DMAx_Streamy into DMAx
392 * @param __STREAM_INSTANCE__ DMAx_Streamy
393 * @retval DMAx
394 */
395 #define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \
396 (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1)
398 /**
399 * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y
400 * @param __STREAM_INSTANCE__ DMAx_Streamy
401 * @retval LL_DMA_STREAM_y
402 */
403 #define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \
404 (((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
405 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
406 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
407 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
408 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
409 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
410 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
411 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
412 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
413 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
414 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
415 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
416 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
417 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
418 LL_DMA_STREAM_7)
420 /**
421 * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
422 * @param __DMA_INSTANCE__ DMAx
423 * @param __STREAM__ LL_DMA_STREAM_y
424 * @retval DMAx_Streamy
425 */
426 #define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \
427 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \
428 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \
429 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \
430 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \
431 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \
432 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \
433 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \
434 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \
435 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \
436 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \
437 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
438 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \
439 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \
440 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \
441 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \
442 DMA2_Stream7)
444 /**
445 * @}
446 */
448 /**
449 * @}
450 */
453 /* Exported functions --------------------------------------------------------*/
454 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
455 * @{
456 */
458 /** @defgroup DMA_LL_EF_Configuration Configuration
459 * @{
460 */
461 /**
462 * @brief Enable DMA stream.
463 * @rmtoll CR EN LL_DMA_EnableStream
464 * @param DMAx DMAx Instance
465 * @param Stream This parameter can be one of the following values:
466 * @arg @ref LL_DMA_STREAM_0
467 * @arg @ref LL_DMA_STREAM_1
468 * @arg @ref LL_DMA_STREAM_2
469 * @arg @ref LL_DMA_STREAM_3
470 * @arg @ref LL_DMA_STREAM_4
471 * @arg @ref LL_DMA_STREAM_5
472 * @arg @ref LL_DMA_STREAM_6
473 * @arg @ref LL_DMA_STREAM_7
474 * @retval None
475 */
477 {
480 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN);
481 }
483 /**
484 * @brief Disable DMA stream.
485 * @rmtoll CR EN LL_DMA_DisableStream
486 * @param DMAx DMAx Instance
487 * @param Stream This parameter can be one of the following values:
488 * @arg @ref LL_DMA_STREAM_0
489 * @arg @ref LL_DMA_STREAM_1
490 * @arg @ref LL_DMA_STREAM_2
491 * @arg @ref LL_DMA_STREAM_3
492 * @arg @ref LL_DMA_STREAM_4
493 * @arg @ref LL_DMA_STREAM_5
494 * @arg @ref LL_DMA_STREAM_6
495 * @arg @ref LL_DMA_STREAM_7
496 * @retval None
497 */
499 {
502 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN);
503 }
505 /**
506 * @brief Check if DMA stream is enabled or disabled.
507 * @rmtoll CR EN LL_DMA_IsEnabledStream
508 * @param DMAx DMAx Instance
509 * @param Stream This parameter can be one of the following values:
510 * @arg @ref LL_DMA_STREAM_0
511 * @arg @ref LL_DMA_STREAM_1
512 * @arg @ref LL_DMA_STREAM_2
513 * @arg @ref LL_DMA_STREAM_3
514 * @arg @ref LL_DMA_STREAM_4
515 * @arg @ref LL_DMA_STREAM_5
516 * @arg @ref LL_DMA_STREAM_6
517 * @arg @ref LL_DMA_STREAM_7
518 * @retval State of bit (1 or 0).
519 */
521 {
524 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)) ? 1UL : 0UL);
525 }
527 /**
528 * @brief Configure all parameters linked to DMA transfer.
529 * @rmtoll CR DIR LL_DMA_ConfigTransfer\n
530 * CR CIRC LL_DMA_ConfigTransfer\n
531 * CR PINC LL_DMA_ConfigTransfer\n
532 * CR MINC LL_DMA_ConfigTransfer\n
533 * CR PSIZE LL_DMA_ConfigTransfer\n
534 * CR MSIZE LL_DMA_ConfigTransfer\n
535 * CR PL LL_DMA_ConfigTransfer\n
536 * CR PFCTRL LL_DMA_ConfigTransfer
537 * @param DMAx DMAx Instance
538 * @param Stream This parameter can be one of the following values:
539 * @arg @ref LL_DMA_STREAM_0
540 * @arg @ref LL_DMA_STREAM_1
541 * @arg @ref LL_DMA_STREAM_2
542 * @arg @ref LL_DMA_STREAM_3
543 * @arg @ref LL_DMA_STREAM_4
544 * @arg @ref LL_DMA_STREAM_5
545 * @arg @ref LL_DMA_STREAM_6
546 * @arg @ref LL_DMA_STREAM_7
547 * @param Configuration This parameter must be a combination of all the following values:
548 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
549 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL
550 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
551 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
552 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
553 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
554 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
555 *@retval None
556 */
557 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
558 {
562 DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL,
563 Configuration);
564 }
566 /**
567 * @brief Set Data transfer direction (read from peripheral or from memory).
568 * @rmtoll CR DIR LL_DMA_SetDataTransferDirection
569 * @param DMAx DMAx Instance
570 * @param Stream This parameter can be one of the following values:
571 * @arg @ref LL_DMA_STREAM_0
572 * @arg @ref LL_DMA_STREAM_1
573 * @arg @ref LL_DMA_STREAM_2
574 * @arg @ref LL_DMA_STREAM_3
575 * @arg @ref LL_DMA_STREAM_4
576 * @arg @ref LL_DMA_STREAM_5
577 * @arg @ref LL_DMA_STREAM_6
578 * @arg @ref LL_DMA_STREAM_7
579 * @param Direction This parameter can be one of the following values:
580 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
581 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
582 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
583 * @retval None
584 */
585 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction)
586 {
589 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR, Direction);
590 }
592 /**
593 * @brief Get Data transfer direction (read from peripheral or from memory).
594 * @rmtoll CR DIR LL_DMA_GetDataTransferDirection
595 * @param DMAx DMAx Instance
596 * @param Stream This parameter can be one of the following values:
597 * @arg @ref LL_DMA_STREAM_0
598 * @arg @ref LL_DMA_STREAM_1
599 * @arg @ref LL_DMA_STREAM_2
600 * @arg @ref LL_DMA_STREAM_3
601 * @arg @ref LL_DMA_STREAM_4
602 * @arg @ref LL_DMA_STREAM_5
603 * @arg @ref LL_DMA_STREAM_6
604 * @arg @ref LL_DMA_STREAM_7
605 * @retval Returned value can be one of the following values:
606 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
607 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
608 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
609 */
611 {
614 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR));
615 }
617 /**
618 * @brief Set DMA mode normal, circular or peripheral flow control.
619 * @rmtoll CR CIRC LL_DMA_SetMode\n
620 * CR PFCTRL LL_DMA_SetMode
621 * @param DMAx DMAx Instance
622 * @param Stream This parameter can be one of the following values:
623 * @arg @ref LL_DMA_STREAM_0
624 * @arg @ref LL_DMA_STREAM_1
625 * @arg @ref LL_DMA_STREAM_2
626 * @arg @ref LL_DMA_STREAM_3
627 * @arg @ref LL_DMA_STREAM_4
628 * @arg @ref LL_DMA_STREAM_5
629 * @arg @ref LL_DMA_STREAM_6
630 * @arg @ref LL_DMA_STREAM_7
631 * @param Mode This parameter can be one of the following values:
632 * @arg @ref LL_DMA_MODE_NORMAL
633 * @arg @ref LL_DMA_MODE_CIRCULAR
634 * @arg @ref LL_DMA_MODE_PFCTRL
635 * @retval None
636 */
638 {
641 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode);
642 }
644 /**
645 * @brief Get DMA mode normal, circular or peripheral flow control.
646 * @rmtoll CR CIRC LL_DMA_GetMode\n
647 * CR PFCTRL LL_DMA_GetMode
648 * @param DMAx DMAx Instance
649 * @param Stream This parameter can be one of the following values:
650 * @arg @ref LL_DMA_STREAM_0
651 * @arg @ref LL_DMA_STREAM_1
652 * @arg @ref LL_DMA_STREAM_2
653 * @arg @ref LL_DMA_STREAM_3
654 * @arg @ref LL_DMA_STREAM_4
655 * @arg @ref LL_DMA_STREAM_5
656 * @arg @ref LL_DMA_STREAM_6
657 * @arg @ref LL_DMA_STREAM_7
658 * @retval Returned value can be one of the following values:
659 * @arg @ref LL_DMA_MODE_NORMAL
660 * @arg @ref LL_DMA_MODE_CIRCULAR
661 * @arg @ref LL_DMA_MODE_PFCTRL
662 */
664 {
667 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL));
668 }
670 /**
671 * @brief Set Peripheral increment mode.
672 * @rmtoll CR PINC LL_DMA_SetPeriphIncMode
673 * @param DMAx DMAx Instance
674 * @param Stream This parameter can be one of the following values:
675 * @arg @ref LL_DMA_STREAM_0
676 * @arg @ref LL_DMA_STREAM_1
677 * @arg @ref LL_DMA_STREAM_2
678 * @arg @ref LL_DMA_STREAM_3
679 * @arg @ref LL_DMA_STREAM_4
680 * @arg @ref LL_DMA_STREAM_5
681 * @arg @ref LL_DMA_STREAM_6
682 * @arg @ref LL_DMA_STREAM_7
683 * @param IncrementMode This parameter can be one of the following values:
684 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
685 * @arg @ref LL_DMA_PERIPH_INCREMENT
686 * @retval None
687 */
688 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
689 {
692 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC, IncrementMode);
693 }
695 /**
696 * @brief Get Peripheral increment mode.
697 * @rmtoll CR PINC LL_DMA_GetPeriphIncMode
698 * @param DMAx DMAx Instance
699 * @param Stream This parameter can be one of the following values:
700 * @arg @ref LL_DMA_STREAM_0
701 * @arg @ref LL_DMA_STREAM_1
702 * @arg @ref LL_DMA_STREAM_2
703 * @arg @ref LL_DMA_STREAM_3
704 * @arg @ref LL_DMA_STREAM_4
705 * @arg @ref LL_DMA_STREAM_5
706 * @arg @ref LL_DMA_STREAM_6
707 * @arg @ref LL_DMA_STREAM_7
708 * @retval Returned value can be one of the following values:
709 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
710 * @arg @ref LL_DMA_PERIPH_INCREMENT
711 */
713 {
716 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC));
717 }
719 /**
720 * @brief Set Memory increment mode.
721 * @rmtoll CR MINC LL_DMA_SetMemoryIncMode
722 * @param DMAx DMAx Instance
723 * @param Stream This parameter can be one of the following values:
724 * @arg @ref LL_DMA_STREAM_0
725 * @arg @ref LL_DMA_STREAM_1
726 * @arg @ref LL_DMA_STREAM_2
727 * @arg @ref LL_DMA_STREAM_3
728 * @arg @ref LL_DMA_STREAM_4
729 * @arg @ref LL_DMA_STREAM_5
730 * @arg @ref LL_DMA_STREAM_6
731 * @arg @ref LL_DMA_STREAM_7
732 * @param IncrementMode This parameter can be one of the following values:
733 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
734 * @arg @ref LL_DMA_MEMORY_INCREMENT
735 * @retval None
736 */
737 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
738 {
741 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC, IncrementMode);
742 }
744 /**
745 * @brief Get Memory increment mode.
746 * @rmtoll CR MINC LL_DMA_GetMemoryIncMode
747 * @param DMAx DMAx Instance
748 * @param Stream This parameter can be one of the following values:
749 * @arg @ref LL_DMA_STREAM_0
750 * @arg @ref LL_DMA_STREAM_1
751 * @arg @ref LL_DMA_STREAM_2
752 * @arg @ref LL_DMA_STREAM_3
753 * @arg @ref LL_DMA_STREAM_4
754 * @arg @ref LL_DMA_STREAM_5
755 * @arg @ref LL_DMA_STREAM_6
756 * @arg @ref LL_DMA_STREAM_7
757 * @retval Returned value can be one of the following values:
758 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
759 * @arg @ref LL_DMA_MEMORY_INCREMENT
760 */
762 {
765 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC));
766 }
768 /**
769 * @brief Set Peripheral size.
770 * @rmtoll CR PSIZE LL_DMA_SetPeriphSize
771 * @param DMAx DMAx Instance
772 * @param Stream This parameter can be one of the following values:
773 * @arg @ref LL_DMA_STREAM_0
774 * @arg @ref LL_DMA_STREAM_1
775 * @arg @ref LL_DMA_STREAM_2
776 * @arg @ref LL_DMA_STREAM_3
777 * @arg @ref LL_DMA_STREAM_4
778 * @arg @ref LL_DMA_STREAM_5
779 * @arg @ref LL_DMA_STREAM_6
780 * @arg @ref LL_DMA_STREAM_7
781 * @param Size This parameter can be one of the following values:
782 * @arg @ref LL_DMA_PDATAALIGN_BYTE
783 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
784 * @arg @ref LL_DMA_PDATAALIGN_WORD
785 * @retval None
786 */
788 {
791 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE, Size);
792 }
794 /**
795 * @brief Get Peripheral size.
796 * @rmtoll CR PSIZE LL_DMA_GetPeriphSize
797 * @param DMAx DMAx Instance
798 * @param Stream This parameter can be one of the following values:
799 * @arg @ref LL_DMA_STREAM_0
800 * @arg @ref LL_DMA_STREAM_1
801 * @arg @ref LL_DMA_STREAM_2
802 * @arg @ref LL_DMA_STREAM_3
803 * @arg @ref LL_DMA_STREAM_4
804 * @arg @ref LL_DMA_STREAM_5
805 * @arg @ref LL_DMA_STREAM_6
806 * @arg @ref LL_DMA_STREAM_7
807 * @retval Returned value can be one of the following values:
808 * @arg @ref LL_DMA_PDATAALIGN_BYTE
809 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
810 * @arg @ref LL_DMA_PDATAALIGN_WORD
811 */
813 {
816 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE));
817 }
819 /**
820 * @brief Set Memory size.
821 * @rmtoll CR MSIZE LL_DMA_SetMemorySize
822 * @param DMAx DMAx Instance
823 * @param Stream This parameter can be one of the following values:
824 * @arg @ref LL_DMA_STREAM_0
825 * @arg @ref LL_DMA_STREAM_1
826 * @arg @ref LL_DMA_STREAM_2
827 * @arg @ref LL_DMA_STREAM_3
828 * @arg @ref LL_DMA_STREAM_4
829 * @arg @ref LL_DMA_STREAM_5
830 * @arg @ref LL_DMA_STREAM_6
831 * @arg @ref LL_DMA_STREAM_7
832 * @param Size This parameter can be one of the following values:
833 * @arg @ref LL_DMA_MDATAALIGN_BYTE
834 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
835 * @arg @ref LL_DMA_MDATAALIGN_WORD
836 * @retval None
837 */
839 {
842 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE, Size);
843 }
845 /**
846 * @brief Get Memory size.
847 * @rmtoll CR MSIZE LL_DMA_GetMemorySize
848 * @param DMAx DMAx Instance
849 * @param Stream This parameter can be one of the following values:
850 * @arg @ref LL_DMA_STREAM_0
851 * @arg @ref LL_DMA_STREAM_1
852 * @arg @ref LL_DMA_STREAM_2
853 * @arg @ref LL_DMA_STREAM_3
854 * @arg @ref LL_DMA_STREAM_4
855 * @arg @ref LL_DMA_STREAM_5
856 * @arg @ref LL_DMA_STREAM_6
857 * @arg @ref LL_DMA_STREAM_7
858 * @retval Returned value can be one of the following values:
859 * @arg @ref LL_DMA_MDATAALIGN_BYTE
860 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
861 * @arg @ref LL_DMA_MDATAALIGN_WORD
862 */
864 {
867 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE));
868 }
870 /**
871 * @brief Set Peripheral increment offset size.
872 * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize
873 * @param DMAx DMAx Instance
874 * @param Stream This parameter can be one of the following values:
875 * @arg @ref LL_DMA_STREAM_0
876 * @arg @ref LL_DMA_STREAM_1
877 * @arg @ref LL_DMA_STREAM_2
878 * @arg @ref LL_DMA_STREAM_3
879 * @arg @ref LL_DMA_STREAM_4
880 * @arg @ref LL_DMA_STREAM_5
881 * @arg @ref LL_DMA_STREAM_6
882 * @arg @ref LL_DMA_STREAM_7
883 * @param OffsetSize This parameter can be one of the following values:
884 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE
885 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
886 * @retval None
887 */
888 __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
889 {
892 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS, OffsetSize);
893 }
895 /**
896 * @brief Get Peripheral increment offset size.
897 * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize
898 * @param DMAx DMAx Instance
899 * @param Stream This parameter can be one of the following values:
900 * @arg @ref LL_DMA_STREAM_0
901 * @arg @ref LL_DMA_STREAM_1
902 * @arg @ref LL_DMA_STREAM_2
903 * @arg @ref LL_DMA_STREAM_3
904 * @arg @ref LL_DMA_STREAM_4
905 * @arg @ref LL_DMA_STREAM_5
906 * @arg @ref LL_DMA_STREAM_6
907 * @arg @ref LL_DMA_STREAM_7
908 * @retval Returned value can be one of the following values:
909 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE
910 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
911 */
913 {
916 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS));
917 }
919 /**
920 * @brief Set Stream priority level.
921 * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel
922 * @param DMAx DMAx Instance
923 * @param Stream This parameter can be one of the following values:
924 * @arg @ref LL_DMA_STREAM_0
925 * @arg @ref LL_DMA_STREAM_1
926 * @arg @ref LL_DMA_STREAM_2
927 * @arg @ref LL_DMA_STREAM_3
928 * @arg @ref LL_DMA_STREAM_4
929 * @arg @ref LL_DMA_STREAM_5
930 * @arg @ref LL_DMA_STREAM_6
931 * @arg @ref LL_DMA_STREAM_7
932 * @param Priority This parameter can be one of the following values:
933 * @arg @ref LL_DMA_PRIORITY_LOW
934 * @arg @ref LL_DMA_PRIORITY_MEDIUM
935 * @arg @ref LL_DMA_PRIORITY_HIGH
936 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
937 * @retval None
938 */
939 __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority)
940 {
943 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL, Priority);
944 }
946 /**
947 * @brief Get Stream priority level.
948 * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel
949 * @param DMAx DMAx Instance
950 * @param Stream This parameter can be one of the following values:
951 * @arg @ref LL_DMA_STREAM_0
952 * @arg @ref LL_DMA_STREAM_1
953 * @arg @ref LL_DMA_STREAM_2
954 * @arg @ref LL_DMA_STREAM_3
955 * @arg @ref LL_DMA_STREAM_4
956 * @arg @ref LL_DMA_STREAM_5
957 * @arg @ref LL_DMA_STREAM_6
958 * @arg @ref LL_DMA_STREAM_7
959 * @retval Returned value can be one of the following values:
960 * @arg @ref LL_DMA_PRIORITY_LOW
961 * @arg @ref LL_DMA_PRIORITY_MEDIUM
962 * @arg @ref LL_DMA_PRIORITY_HIGH
963 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
964 */
966 {
969 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL));
970 }
972 /**
973 * @brief Enable DMA stream bufferable transfer.
974 * @rmtoll CR TRBUFF LL_DMA_EnableBufferableTransfer
975 * @param DMAx DMAx Instance
976 * @param Stream This parameter can be one of the following values:
977 * @arg @ref LL_DMA_STREAM_0
978 * @arg @ref LL_DMA_STREAM_1
979 * @arg @ref LL_DMA_STREAM_2
980 * @arg @ref LL_DMA_STREAM_3
981 * @arg @ref LL_DMA_STREAM_4
982 * @arg @ref LL_DMA_STREAM_5
983 * @arg @ref LL_DMA_STREAM_6
984 * @arg @ref LL_DMA_STREAM_7
985 * @retval None
986 */
988 {
991 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF);
992 }
994 /**
995 * @brief Disable DMA stream bufferable transfer.
996 * @rmtoll CR TRBUFF LL_DMA_DisableBufferableTransfer
997 * @param DMAx DMAx Instance
998 * @param Stream This parameter can be one of the following values:
999 * @arg @ref LL_DMA_STREAM_0
1000 * @arg @ref LL_DMA_STREAM_1
1001 * @arg @ref LL_DMA_STREAM_2
1002 * @arg @ref LL_DMA_STREAM_3
1003 * @arg @ref LL_DMA_STREAM_4
1004 * @arg @ref LL_DMA_STREAM_5
1005 * @arg @ref LL_DMA_STREAM_6
1006 * @arg @ref LL_DMA_STREAM_7
1007 * @retval None
1008 */
1010 {
1013 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF);
1014 }
1016 /**
1017 * @brief Set Number of data to transfer.
1018 * @rmtoll NDTR NDT LL_DMA_SetDataLength
1019 * @note This action has no effect if
1020 * stream is enabled.
1021 * @param DMAx DMAx Instance
1022 * @param Stream This parameter can be one of the following values:
1023 * @arg @ref LL_DMA_STREAM_0
1024 * @arg @ref LL_DMA_STREAM_1
1025 * @arg @ref LL_DMA_STREAM_2
1026 * @arg @ref LL_DMA_STREAM_3
1027 * @arg @ref LL_DMA_STREAM_4
1028 * @arg @ref LL_DMA_STREAM_5
1029 * @arg @ref LL_DMA_STREAM_6
1030 * @arg @ref LL_DMA_STREAM_7
1031 * @param NbData Between 0 to 0xFFFFFFFF
1032 * @retval None
1033 */
1035 {
1038 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT, NbData);
1039 }
1041 /**
1042 * @brief Get Number of data to transfer.
1043 * @rmtoll NDTR NDT LL_DMA_GetDataLength
1044 * @note Once the stream is enabled, the return value indicate the
1045 * remaining bytes to be transmitted.
1046 * @param DMAx DMAx Instance
1047 * @param Stream This parameter can be one of the following values:
1048 * @arg @ref LL_DMA_STREAM_0
1049 * @arg @ref LL_DMA_STREAM_1
1050 * @arg @ref LL_DMA_STREAM_2
1051 * @arg @ref LL_DMA_STREAM_3
1052 * @arg @ref LL_DMA_STREAM_4
1053 * @arg @ref LL_DMA_STREAM_5
1054 * @arg @ref LL_DMA_STREAM_6
1055 * @arg @ref LL_DMA_STREAM_7
1056 * @retval Between 0 to 0xFFFFFFFF
1057 */
1059 {
1062 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT));
1063 }
1064 /**
1065 * @brief Set DMA request for DMA Streams on DMAMUX Channel x.
1066 * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
1067 * DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
1068 * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest
1069 * @param DMAx DMAx Instance
1070 * @param Stream This parameter can be one of the following values:
1071 * @arg @ref LL_DMA_STREAM_0
1072 * @arg @ref LL_DMA_STREAM_1
1073 * @arg @ref LL_DMA_STREAM_2
1074 * @arg @ref LL_DMA_STREAM_3
1075 * @arg @ref LL_DMA_STREAM_4
1076 * @arg @ref LL_DMA_STREAM_5
1077 * @arg @ref LL_DMA_STREAM_6
1078 * @arg @ref LL_DMA_STREAM_7
1079 * @param Request This parameter can be one of the following values:
1080 * @arg @ref LL_DMAMUX1_REQ_MEM2MEM
1081 * @arg @ref LL_DMAMUX1_REQ_GENERATOR0
1082 * @arg @ref LL_DMAMUX1_REQ_GENERATOR1
1083 * @arg @ref LL_DMAMUX1_REQ_GENERATOR2
1084 * @arg @ref LL_DMAMUX1_REQ_GENERATOR3
1085 * @arg @ref LL_DMAMUX1_REQ_GENERATOR4
1086 * @arg @ref LL_DMAMUX1_REQ_GENERATOR5
1087 * @arg @ref LL_DMAMUX1_REQ_GENERATOR6
1088 * @arg @ref LL_DMAMUX1_REQ_GENERATOR7
1089 * @arg @ref LL_DMAMUX1_REQ_ADC1
1090 * @arg @ref LL_DMAMUX1_REQ_ADC2
1091 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
1092 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
1093 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
1094 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
1095 * @arg @ref LL_DMAMUX1_REQ_TIM1_UP
1096 * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
1097 * @arg @ref LL_DMAMUX1_REQ_TIM1_COM
1098 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
1099 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
1100 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
1101 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
1102 * @arg @ref LL_DMAMUX1_REQ_TIM2_UP
1103 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
1104 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
1105 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
1106 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
1107 * @arg @ref LL_DMAMUX1_REQ_TIM3_UP
1108 * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
1109 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
1110 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
1111 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
1112 * @arg @ref LL_DMAMUX1_REQ_TIM4_UP
1113 * @arg @ref LL_DMAMUX1_REQ_I2C1_RX
1114 * @arg @ref LL_DMAMUX1_REQ_I2C1_TX
1115 * @arg @ref LL_DMAMUX1_REQ_I2C2_RX
1116 * @arg @ref LL_DMAMUX1_REQ_I2C2_TX
1117 * @arg @ref LL_DMAMUX1_REQ_SPI1_RX
1118 * @arg @ref LL_DMAMUX1_REQ_SPI1_TX
1119 * @arg @ref LL_DMAMUX1_REQ_SPI2_RX
1120 * @arg @ref LL_DMAMUX1_REQ_SPI2_TX
1121 * @arg @ref LL_DMAMUX1_REQ_USART1_RX
1122 * @arg @ref LL_DMAMUX1_REQ_USART1_TX
1123 * @arg @ref LL_DMAMUX1_REQ_USART2_RX
1124 * @arg @ref LL_DMAMUX1_REQ_USART2_TX
1125 * @arg @ref LL_DMAMUX1_REQ_USART3_RX
1126 * @arg @ref LL_DMAMUX1_REQ_USART3_TX
1127 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
1128 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
1129 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
1130 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
1131 * @arg @ref LL_DMAMUX1_REQ_TIM8_UP
1132 * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
1133 * @arg @ref LL_DMAMUX1_REQ_TIM8_COM
1134 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
1135 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
1136 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
1137 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
1138 * @arg @ref LL_DMAMUX1_REQ_TIM5_UP
1139 * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
1140 * @arg @ref LL_DMAMUX1_REQ_SPI3_RX
1141 * @arg @ref LL_DMAMUX1_REQ_SPI3_TX
1142 * @arg @ref LL_DMAMUX1_REQ_UART4_RX
1143 * @arg @ref LL_DMAMUX1_REQ_UART4_TX
1144 * @arg @ref LL_DMAMUX1_REQ_UART5_RX
1145 * @arg @ref LL_DMAMUX1_REQ_UART5_TX
1146 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
1147 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
1148 * @arg @ref LL_DMAMUX1_REQ_TIM6_UP
1149 * @arg @ref LL_DMAMUX1_REQ_TIM7_UP
1150 * @arg @ref LL_DMAMUX1_REQ_USART6_RX
1151 * @arg @ref LL_DMAMUX1_REQ_USART6_TX
1152 * @arg @ref LL_DMAMUX1_REQ_I2C3_RX
1153 * @arg @ref LL_DMAMUX1_REQ_I2C3_TX
1154 * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*)
1155 * @arg @ref LL_DMAMUX1_REQ_CRYP_IN
1156 * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
1157 * @arg @ref LL_DMAMUX1_REQ_HASH_IN
1158 * @arg @ref LL_DMAMUX1_REQ_UART7_RX
1159 * @arg @ref LL_DMAMUX1_REQ_UART7_TX
1160 * @arg @ref LL_DMAMUX1_REQ_UART8_RX
1161 * @arg @ref LL_DMAMUX1_REQ_UART8_TX
1162 * @arg @ref LL_DMAMUX1_REQ_SPI4_RX
1163 * @arg @ref LL_DMAMUX1_REQ_SPI4_TX
1164 * @arg @ref LL_DMAMUX1_REQ_SPI5_RX
1165 * @arg @ref LL_DMAMUX1_REQ_SPI5_TX
1166 * @arg @ref LL_DMAMUX1_REQ_SAI1_A
1167 * @arg @ref LL_DMAMUX1_REQ_SAI1_B
1168 * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*)
1169 * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*)
1170 * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
1171 * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
1172 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
1173 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
1174 * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
1175 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
1176 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
1177 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
1178 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
1179 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
1180 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
1181 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
1182 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
1183 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
1184 * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
1185 * @arg @ref LL_DMAMUX1_REQ_TIM15_UP
1186 * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
1187 * @arg @ref LL_DMAMUX1_REQ_TIM15_COM
1188 * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
1189 * @arg @ref LL_DMAMUX1_REQ_TIM16_UP
1190 * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
1191 * @arg @ref LL_DMAMUX1_REQ_TIM17_UP
1192 * @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
1193 * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
1194 * @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
1195 * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
1196 * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)
1197 * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
1198 * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)
1199 * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*)
1200 * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*)
1201 * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*)
1202 * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*)
1203 * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*)
1204 * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*)
1205 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*)
1206 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*)
1207 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*)
1208 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*)
1209 * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*)
1210 * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*)
1211 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*)
1212 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*)
1213 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*)
1214 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*)
1215 * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*)
1216 * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*)
1217 *
1218 * @note (*) Availability depends on devices.
1219 * @retval None
1220 */
1221 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Request)
1222 {
1223 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
1224 }
1226 /**
1227 * @brief Get DMA request for DMA Channels on DMAMUX Channel x.
1228 * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
1229 * DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
1230 * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest
1231 * @param DMAx DMAx Instance
1232 * @param Stream This parameter can be one of the following values:
1233 * @arg @ref LL_DMA_STREAM_0
1234 * @arg @ref LL_DMA_STREAM_1
1235 * @arg @ref LL_DMA_STREAM_2
1236 * @arg @ref LL_DMA_STREAM_3
1237 * @arg @ref LL_DMA_STREAM_4
1238 * @arg @ref LL_DMA_STREAM_5
1239 * @arg @ref LL_DMA_STREAM_6
1240 * @arg @ref LL_DMA_STREAM_7
1241 * @retval Returned value can be one of the following values:
1242 * @arg @ref LL_DMAMUX1_REQ_MEM2MEM
1243 * @arg @ref LL_DMAMUX1_REQ_GENERATOR0
1244 * @arg @ref LL_DMAMUX1_REQ_GENERATOR1
1245 * @arg @ref LL_DMAMUX1_REQ_GENERATOR2
1246 * @arg @ref LL_DMAMUX1_REQ_GENERATOR3
1247 * @arg @ref LL_DMAMUX1_REQ_GENERATOR4
1248 * @arg @ref LL_DMAMUX1_REQ_GENERATOR5
1249 * @arg @ref LL_DMAMUX1_REQ_GENERATOR6
1250 * @arg @ref LL_DMAMUX1_REQ_GENERATOR7
1251 * @arg @ref LL_DMAMUX1_REQ_ADC1
1252 * @arg @ref LL_DMAMUX1_REQ_ADC2
1253 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
1254 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
1255 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
1256 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
1257 * @arg @ref LL_DMAMUX1_REQ_TIM1_UP
1258 * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
1259 * @arg @ref LL_DMAMUX1_REQ_TIM1_COM
1260 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
1261 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
1262 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
1263 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
1264 * @arg @ref LL_DMAMUX1_REQ_TIM2_UP
1265 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
1266 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
1267 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
1268 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
1269 * @arg @ref LL_DMAMUX1_REQ_TIM3_UP
1270 * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
1271 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
1272 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
1273 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
1274 * @arg @ref LL_DMAMUX1_REQ_TIM4_UP
1275 * @arg @ref LL_DMAMUX1_REQ_I2C1_RX
1276 * @arg @ref LL_DMAMUX1_REQ_I2C1_TX
1277 * @arg @ref LL_DMAMUX1_REQ_I2C2_RX
1278 * @arg @ref LL_DMAMUX1_REQ_I2C2_TX
1279 * @arg @ref LL_DMAMUX1_REQ_SPI1_RX
1280 * @arg @ref LL_DMAMUX1_REQ_SPI1_TX
1281 * @arg @ref LL_DMAMUX1_REQ_SPI2_RX
1282 * @arg @ref LL_DMAMUX1_REQ_SPI2_TX
1283 * @arg @ref LL_DMAMUX1_REQ_USART1_RX
1284 * @arg @ref LL_DMAMUX1_REQ_USART1_TX
1285 * @arg @ref LL_DMAMUX1_REQ_USART2_RX
1286 * @arg @ref LL_DMAMUX1_REQ_USART2_TX
1287 * @arg @ref LL_DMAMUX1_REQ_USART3_RX
1288 * @arg @ref LL_DMAMUX1_REQ_USART3_TX
1289 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
1290 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
1291 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
1292 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
1293 * @arg @ref LL_DMAMUX1_REQ_TIM8_UP
1294 * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
1295 * @arg @ref LL_DMAMUX1_REQ_TIM8_COM
1296 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
1297 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
1298 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
1299 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
1300 * @arg @ref LL_DMAMUX1_REQ_TIM5_UP
1301 * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
1302 * @arg @ref LL_DMAMUX1_REQ_SPI3_RX
1303 * @arg @ref LL_DMAMUX1_REQ_SPI3_TX
1304 * @arg @ref LL_DMAMUX1_REQ_UART4_RX
1305 * @arg @ref LL_DMAMUX1_REQ_UART4_TX
1306 * @arg @ref LL_DMAMUX1_REQ_UART5_RX
1307 * @arg @ref LL_DMAMUX1_REQ_UART5_TX
1308 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
1309 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
1310 * @arg @ref LL_DMAMUX1_REQ_TIM6_UP
1311 * @arg @ref LL_DMAMUX1_REQ_TIM7_UP
1312 * @arg @ref LL_DMAMUX1_REQ_USART6_RX
1313 * @arg @ref LL_DMAMUX1_REQ_USART6_TX
1314 * @arg @ref LL_DMAMUX1_REQ_I2C3_RX
1315 * @arg @ref LL_DMAMUX1_REQ_I2C3_TX
1316 * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*)
1317 * @arg @ref LL_DMAMUX1_REQ_CRYP_IN
1318 * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
1319 * @arg @ref LL_DMAMUX1_REQ_HASH_IN
1320 * @arg @ref LL_DMAMUX1_REQ_UART7_RX
1321 * @arg @ref LL_DMAMUX1_REQ_UART7_TX
1322 * @arg @ref LL_DMAMUX1_REQ_UART8_RX
1323 * @arg @ref LL_DMAMUX1_REQ_UART8_TX
1324 * @arg @ref LL_DMAMUX1_REQ_SPI4_RX
1325 * @arg @ref LL_DMAMUX1_REQ_SPI4_TX
1326 * @arg @ref LL_DMAMUX1_REQ_SPI5_RX
1327 * @arg @ref LL_DMAMUX1_REQ_SPI5_TX
1328 * @arg @ref LL_DMAMUX1_REQ_SAI1_A
1329 * @arg @ref LL_DMAMUX1_REQ_SAI1_B
1330 * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*)
1331 * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*)
1332 * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
1333 * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
1334 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
1335 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
1336 * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
1337 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
1338 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
1339 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
1340 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
1341 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
1342 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
1343 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
1344 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
1345 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
1346 * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
1347 * @arg @ref LL_DMAMUX1_REQ_TIM15_UP
1348 * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
1349 * @arg @ref LL_DMAMUX1_REQ_TIM15_COM
1350 * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
1351 * @arg @ref LL_DMAMUX1_REQ_TIM16_UP
1352 * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
1353 * @arg @ref LL_DMAMUX1_REQ_TIM17_UP
1354 * @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
1355 * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
1356 * @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
1357 * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
1358 * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)
1359 * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
1360 * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)
1361 * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*)
1362 * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*)
1363 * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*)
1364 * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*)
1365 * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*)
1366 * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*)
1367 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*)
1368 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*)
1369 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*)
1370 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*)
1371 * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*)
1372 * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*)
1373 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*)
1374 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*)
1375 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*)
1376 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*)
1377 * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*)
1378 * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*)
1379 *
1380 * @note (*) Availability depends on devices.
1381 */
1383 {
1384 return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
1385 }
1387 /**
1388 * @brief Set Memory burst transfer configuration.
1389 * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer
1390 * @param DMAx DMAx Instance
1391 * @param Stream This parameter can be one of the following values:
1392 * @arg @ref LL_DMA_STREAM_0
1393 * @arg @ref LL_DMA_STREAM_1
1394 * @arg @ref LL_DMA_STREAM_2
1395 * @arg @ref LL_DMA_STREAM_3
1396 * @arg @ref LL_DMA_STREAM_4
1397 * @arg @ref LL_DMA_STREAM_5
1398 * @arg @ref LL_DMA_STREAM_6
1399 * @arg @ref LL_DMA_STREAM_7
1400 * @param Mburst This parameter can be one of the following values:
1401 * @arg @ref LL_DMA_MBURST_SINGLE
1402 * @arg @ref LL_DMA_MBURST_INC4
1403 * @arg @ref LL_DMA_MBURST_INC8
1404 * @arg @ref LL_DMA_MBURST_INC16
1405 * @retval None
1406 */
1407 __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
1408 {
1411 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST, Mburst);
1412 }
1414 /**
1415 * @brief Get Memory burst transfer configuration.
1416 * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer
1417 * @param DMAx DMAx Instance
1418 * @param Stream This parameter can be one of the following values:
1419 * @arg @ref LL_DMA_STREAM_0
1420 * @arg @ref LL_DMA_STREAM_1
1421 * @arg @ref LL_DMA_STREAM_2
1422 * @arg @ref LL_DMA_STREAM_3
1423 * @arg @ref LL_DMA_STREAM_4
1424 * @arg @ref LL_DMA_STREAM_5
1425 * @arg @ref LL_DMA_STREAM_6
1426 * @arg @ref LL_DMA_STREAM_7
1427 * @retval Returned value can be one of the following values:
1428 * @arg @ref LL_DMA_MBURST_SINGLE
1429 * @arg @ref LL_DMA_MBURST_INC4
1430 * @arg @ref LL_DMA_MBURST_INC8
1431 * @arg @ref LL_DMA_MBURST_INC16
1432 */
1434 {
1437 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST));
1438 }
1440 /**
1441 * @brief Set Peripheral burst transfer configuration.
1442 * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer
1443 * @param DMAx DMAx Instance
1444 * @param Stream This parameter can be one of the following values:
1445 * @arg @ref LL_DMA_STREAM_0
1446 * @arg @ref LL_DMA_STREAM_1
1447 * @arg @ref LL_DMA_STREAM_2
1448 * @arg @ref LL_DMA_STREAM_3
1449 * @arg @ref LL_DMA_STREAM_4
1450 * @arg @ref LL_DMA_STREAM_5
1451 * @arg @ref LL_DMA_STREAM_6
1452 * @arg @ref LL_DMA_STREAM_7
1453 * @param Pburst This parameter can be one of the following values:
1454 * @arg @ref LL_DMA_PBURST_SINGLE
1455 * @arg @ref LL_DMA_PBURST_INC4
1456 * @arg @ref LL_DMA_PBURST_INC8
1457 * @arg @ref LL_DMA_PBURST_INC16
1458 * @retval None
1459 */
1460 __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
1461 {
1464 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST, Pburst);
1465 }
1467 /**
1468 * @brief Get Peripheral burst transfer configuration.
1469 * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer
1470 * @param DMAx DMAx Instance
1471 * @param Stream This parameter can be one of the following values:
1472 * @arg @ref LL_DMA_STREAM_0
1473 * @arg @ref LL_DMA_STREAM_1
1474 * @arg @ref LL_DMA_STREAM_2
1475 * @arg @ref LL_DMA_STREAM_3
1476 * @arg @ref LL_DMA_STREAM_4
1477 * @arg @ref LL_DMA_STREAM_5
1478 * @arg @ref LL_DMA_STREAM_6
1479 * @arg @ref LL_DMA_STREAM_7
1480 * @retval Returned value can be one of the following values:
1481 * @arg @ref LL_DMA_PBURST_SINGLE
1482 * @arg @ref LL_DMA_PBURST_INC4
1483 * @arg @ref LL_DMA_PBURST_INC8
1484 * @arg @ref LL_DMA_PBURST_INC16
1485 */
1487 {
1490 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST));
1491 }
1493 /**
1494 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1495 * @rmtoll CR CT LL_DMA_SetCurrentTargetMem
1496 * @param DMAx DMAx Instance
1497 * @param Stream This parameter can be one of the following values:
1498 * @arg @ref LL_DMA_STREAM_0
1499 * @arg @ref LL_DMA_STREAM_1
1500 * @arg @ref LL_DMA_STREAM_2
1501 * @arg @ref LL_DMA_STREAM_3
1502 * @arg @ref LL_DMA_STREAM_4
1503 * @arg @ref LL_DMA_STREAM_5
1504 * @arg @ref LL_DMA_STREAM_6
1505 * @arg @ref LL_DMA_STREAM_7
1506 * @param CurrentMemory This parameter can be one of the following values:
1507 * @arg @ref LL_DMA_CURRENTTARGETMEM0
1508 * @arg @ref LL_DMA_CURRENTTARGETMEM1
1509 * @retval None
1510 */
1511 __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
1512 {
1515 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT, CurrentMemory);
1516 }
1518 /**
1519 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1520 * @rmtoll CR CT LL_DMA_GetCurrentTargetMem
1521 * @param DMAx DMAx Instance
1522 * @param Stream This parameter can be one of the following values:
1523 * @arg @ref LL_DMA_STREAM_0
1524 * @arg @ref LL_DMA_STREAM_1
1525 * @arg @ref LL_DMA_STREAM_2
1526 * @arg @ref LL_DMA_STREAM_3
1527 * @arg @ref LL_DMA_STREAM_4
1528 * @arg @ref LL_DMA_STREAM_5
1529 * @arg @ref LL_DMA_STREAM_6
1530 * @arg @ref LL_DMA_STREAM_7
1531 * @retval Returned value can be one of the following values:
1532 * @arg @ref LL_DMA_CURRENTTARGETMEM0
1533 * @arg @ref LL_DMA_CURRENTTARGETMEM1
1534 */
1536 {
1539 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT));
1540 }
1542 /**
1543 * @brief Enable the double buffer mode.
1544 * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode
1545 * @param DMAx DMAx Instance
1546 * @param Stream This parameter can be one of the following values:
1547 * @arg @ref LL_DMA_STREAM_0
1548 * @arg @ref LL_DMA_STREAM_1
1549 * @arg @ref LL_DMA_STREAM_2
1550 * @arg @ref LL_DMA_STREAM_3
1551 * @arg @ref LL_DMA_STREAM_4
1552 * @arg @ref LL_DMA_STREAM_5
1553 * @arg @ref LL_DMA_STREAM_6
1554 * @arg @ref LL_DMA_STREAM_7
1555 * @retval None
1556 */
1558 {
1561 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM);
1562 }
1564 /**
1565 * @brief Disable the double buffer mode.
1566 * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode
1567 * @param DMAx DMAx Instance
1568 * @param Stream This parameter can be one of the following values:
1569 * @arg @ref LL_DMA_STREAM_0
1570 * @arg @ref LL_DMA_STREAM_1
1571 * @arg @ref LL_DMA_STREAM_2
1572 * @arg @ref LL_DMA_STREAM_3
1573 * @arg @ref LL_DMA_STREAM_4
1574 * @arg @ref LL_DMA_STREAM_5
1575 * @arg @ref LL_DMA_STREAM_6
1576 * @arg @ref LL_DMA_STREAM_7
1577 * @retval None
1578 */
1580 {
1583 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM);
1584 }
1586 /**
1587 * @brief Get FIFO status.
1588 * @rmtoll FCR FS LL_DMA_GetFIFOStatus
1589 * @param DMAx DMAx Instance
1590 * @param Stream This parameter can be one of the following values:
1591 * @arg @ref LL_DMA_STREAM_0
1592 * @arg @ref LL_DMA_STREAM_1
1593 * @arg @ref LL_DMA_STREAM_2
1594 * @arg @ref LL_DMA_STREAM_3
1595 * @arg @ref LL_DMA_STREAM_4
1596 * @arg @ref LL_DMA_STREAM_5
1597 * @arg @ref LL_DMA_STREAM_6
1598 * @arg @ref LL_DMA_STREAM_7
1599 * @retval Returned value can be one of the following values:
1600 * @arg @ref LL_DMA_FIFOSTATUS_0_25
1601 * @arg @ref LL_DMA_FIFOSTATUS_25_50
1602 * @arg @ref LL_DMA_FIFOSTATUS_50_75
1603 * @arg @ref LL_DMA_FIFOSTATUS_75_100
1604 * @arg @ref LL_DMA_FIFOSTATUS_EMPTY
1605 * @arg @ref LL_DMA_FIFOSTATUS_FULL
1606 */
1608 {
1611 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FS));
1612 }
1614 /**
1615 * @brief Disable Fifo mode.
1616 * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode
1617 * @param DMAx DMAx Instance
1618 * @param Stream This parameter can be one of the following values:
1619 * @arg @ref LL_DMA_STREAM_0
1620 * @arg @ref LL_DMA_STREAM_1
1621 * @arg @ref LL_DMA_STREAM_2
1622 * @arg @ref LL_DMA_STREAM_3
1623 * @arg @ref LL_DMA_STREAM_4
1624 * @arg @ref LL_DMA_STREAM_5
1625 * @arg @ref LL_DMA_STREAM_6
1626 * @arg @ref LL_DMA_STREAM_7
1627 * @retval None
1628 */
1630 {
1633 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS);
1634 }
1636 /**
1637 * @brief Enable Fifo mode.
1638 * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode
1639 * @param DMAx DMAx Instance
1640 * @param Stream This parameter can be one of the following values:
1641 * @arg @ref LL_DMA_STREAM_0
1642 * @arg @ref LL_DMA_STREAM_1
1643 * @arg @ref LL_DMA_STREAM_2
1644 * @arg @ref LL_DMA_STREAM_3
1645 * @arg @ref LL_DMA_STREAM_4
1646 * @arg @ref LL_DMA_STREAM_5
1647 * @arg @ref LL_DMA_STREAM_6
1648 * @arg @ref LL_DMA_STREAM_7
1649 * @retval None
1650 */
1652 {
1655 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS);
1656 }
1658 /**
1659 * @brief Select FIFO threshold.
1660 * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold
1661 * @param DMAx DMAx Instance
1662 * @param Stream This parameter can be one of the following values:
1663 * @arg @ref LL_DMA_STREAM_0
1664 * @arg @ref LL_DMA_STREAM_1
1665 * @arg @ref LL_DMA_STREAM_2
1666 * @arg @ref LL_DMA_STREAM_3
1667 * @arg @ref LL_DMA_STREAM_4
1668 * @arg @ref LL_DMA_STREAM_5
1669 * @arg @ref LL_DMA_STREAM_6
1670 * @arg @ref LL_DMA_STREAM_7
1671 * @param Threshold This parameter can be one of the following values:
1672 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1673 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1674 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1675 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1676 * @retval None
1677 */
1678 __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
1679 {
1682 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH, Threshold);
1683 }
1685 /**
1686 * @brief Get FIFO threshold.
1687 * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold
1688 * @param DMAx DMAx Instance
1689 * @param Stream This parameter can be one of the following values:
1690 * @arg @ref LL_DMA_STREAM_0
1691 * @arg @ref LL_DMA_STREAM_1
1692 * @arg @ref LL_DMA_STREAM_2
1693 * @arg @ref LL_DMA_STREAM_3
1694 * @arg @ref LL_DMA_STREAM_4
1695 * @arg @ref LL_DMA_STREAM_5
1696 * @arg @ref LL_DMA_STREAM_6
1697 * @arg @ref LL_DMA_STREAM_7
1698 * @retval Returned value can be one of the following values:
1699 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1700 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1701 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1702 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1703 */
1705 {
1708 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH));
1709 }
1711 /**
1712 * @brief Configure the FIFO .
1713 * @rmtoll FCR FTH LL_DMA_ConfigFifo\n
1714 * FCR DMDIS LL_DMA_ConfigFifo
1715 * @param DMAx DMAx Instance
1716 * @param Stream This parameter can be one of the following values:
1717 * @arg @ref LL_DMA_STREAM_0
1718 * @arg @ref LL_DMA_STREAM_1
1719 * @arg @ref LL_DMA_STREAM_2
1720 * @arg @ref LL_DMA_STREAM_3
1721 * @arg @ref LL_DMA_STREAM_4
1722 * @arg @ref LL_DMA_STREAM_5
1723 * @arg @ref LL_DMA_STREAM_6
1724 * @arg @ref LL_DMA_STREAM_7
1725 * @param FifoMode This parameter can be one of the following values:
1726 * @arg @ref LL_DMA_FIFOMODE_ENABLE
1727 * @arg @ref LL_DMA_FIFOMODE_DISABLE
1728 * @param FifoThreshold This parameter can be one of the following values:
1729 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1730 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1731 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1732 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1733 * @retval None
1734 */
1735 __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
1736 {
1739 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH | DMA_SxFCR_DMDIS, FifoMode | FifoThreshold);
1740 }
1742 /**
1743 * @brief Configure the Source and Destination addresses.
1744 * @note This API must not be called when the DMA stream is enabled.
1745 * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n
1746 * PAR PA LL_DMA_ConfigAddresses
1747 * @param DMAx DMAx Instance
1748 * @param Stream This parameter can be one of the following values:
1749 * @arg @ref LL_DMA_STREAM_0
1750 * @arg @ref LL_DMA_STREAM_1
1751 * @arg @ref LL_DMA_STREAM_2
1752 * @arg @ref LL_DMA_STREAM_3
1753 * @arg @ref LL_DMA_STREAM_4
1754 * @arg @ref LL_DMA_STREAM_5
1755 * @arg @ref LL_DMA_STREAM_6
1756 * @arg @ref LL_DMA_STREAM_7
1757 * @param SrcAddress Between 0 to 0xFFFFFFFF
1758 * @param DstAddress Between 0 to 0xFFFFFFFF
1759 * @param Direction This parameter can be one of the following values:
1760 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
1761 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
1762 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
1763 * @retval None
1764 */
1765 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
1766 {
1769 /* Direction Memory to Periph */
1771 {
1772 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, SrcAddress);
1773 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, DstAddress);
1774 }
1775 /* Direction Periph to Memory and Memory to Memory */
1776 else
1777 {
1778 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, SrcAddress);
1779 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, DstAddress);
1780 }
1781 }
1783 /**
1784 * @brief Set the Memory address.
1785 * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress
1786 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1787 * @note This API must not be called when the DMA stream is enabled.
1788 * @param DMAx DMAx Instance
1789 * @param Stream This parameter can be one of the following values:
1790 * @arg @ref LL_DMA_STREAM_0
1791 * @arg @ref LL_DMA_STREAM_1
1792 * @arg @ref LL_DMA_STREAM_2
1793 * @arg @ref LL_DMA_STREAM_3
1794 * @arg @ref LL_DMA_STREAM_4
1795 * @arg @ref LL_DMA_STREAM_5
1796 * @arg @ref LL_DMA_STREAM_6
1797 * @arg @ref LL_DMA_STREAM_7
1798 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1799 * @retval None
1800 */
1801 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
1802 {
1805 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress);
1806 }
1808 /**
1809 * @brief Set the Peripheral address.
1810 * @rmtoll PAR PA LL_DMA_SetPeriphAddress
1811 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1812 * @note This API must not be called when the DMA stream is enabled.
1813 * @param DMAx DMAx Instance
1814 * @param Stream This parameter can be one of the following values:
1815 * @arg @ref LL_DMA_STREAM_0
1816 * @arg @ref LL_DMA_STREAM_1
1817 * @arg @ref LL_DMA_STREAM_2
1818 * @arg @ref LL_DMA_STREAM_3
1819 * @arg @ref LL_DMA_STREAM_4
1820 * @arg @ref LL_DMA_STREAM_5
1821 * @arg @ref LL_DMA_STREAM_6
1822 * @arg @ref LL_DMA_STREAM_7
1823 * @param PeriphAddress Between 0 to 0xFFFFFFFF
1824 * @retval None
1825 */
1826 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress)
1827 {
1830 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, PeriphAddress);
1831 }
1833 /**
1834 * @brief Get the Memory address.
1835 * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress
1836 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1837 * @param DMAx DMAx Instance
1838 * @param Stream This parameter can be one of the following values:
1839 * @arg @ref LL_DMA_STREAM_0
1840 * @arg @ref LL_DMA_STREAM_1
1841 * @arg @ref LL_DMA_STREAM_2
1842 * @arg @ref LL_DMA_STREAM_3
1843 * @arg @ref LL_DMA_STREAM_4
1844 * @arg @ref LL_DMA_STREAM_5
1845 * @arg @ref LL_DMA_STREAM_6
1846 * @arg @ref LL_DMA_STREAM_7
1847 * @retval Between 0 to 0xFFFFFFFF
1848 */
1850 {
1853 return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR));
1854 }
1856 /**
1857 * @brief Get the Peripheral address.
1858 * @rmtoll PAR PA LL_DMA_GetPeriphAddress
1859 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1860 * @param DMAx DMAx Instance
1861 * @param Stream This parameter can be one of the following values:
1862 * @arg @ref LL_DMA_STREAM_0
1863 * @arg @ref LL_DMA_STREAM_1
1864 * @arg @ref LL_DMA_STREAM_2
1865 * @arg @ref LL_DMA_STREAM_3
1866 * @arg @ref LL_DMA_STREAM_4
1867 * @arg @ref LL_DMA_STREAM_5
1868 * @arg @ref LL_DMA_STREAM_6
1869 * @arg @ref LL_DMA_STREAM_7
1870 * @retval Between 0 to 0xFFFFFFFF
1871 */
1873 {
1876 return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR));
1877 }
1879 /**
1880 * @brief Set the Memory to Memory Source address.
1881 * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress
1882 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1883 * @note This API must not be called when the DMA stream is enabled.
1884 * @param DMAx DMAx Instance
1885 * @param Stream This parameter can be one of the following values:
1886 * @arg @ref LL_DMA_STREAM_0
1887 * @arg @ref LL_DMA_STREAM_1
1888 * @arg @ref LL_DMA_STREAM_2
1889 * @arg @ref LL_DMA_STREAM_3
1890 * @arg @ref LL_DMA_STREAM_4
1891 * @arg @ref LL_DMA_STREAM_5
1892 * @arg @ref LL_DMA_STREAM_6
1893 * @arg @ref LL_DMA_STREAM_7
1894 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1895 * @retval None
1896 */
1897 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
1898 {
1901 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, MemoryAddress);
1902 }
1904 /**
1905 * @brief Set the Memory to Memory Destination address.
1906 * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress
1907 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1908 * @note This API must not be called when the DMA stream is enabled.
1909 * @param DMAx DMAx Instance
1910 * @param Stream This parameter can be one of the following values:
1911 * @arg @ref LL_DMA_STREAM_0
1912 * @arg @ref LL_DMA_STREAM_1
1913 * @arg @ref LL_DMA_STREAM_2
1914 * @arg @ref LL_DMA_STREAM_3
1915 * @arg @ref LL_DMA_STREAM_4
1916 * @arg @ref LL_DMA_STREAM_5
1917 * @arg @ref LL_DMA_STREAM_6
1918 * @arg @ref LL_DMA_STREAM_7
1919 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1920 * @retval None
1921 */
1922 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
1923 {
1926 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress);
1927 }
1929 /**
1930 * @brief Get the Memory to Memory Source address.
1931 * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress
1932 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1933 * @param DMAx DMAx Instance
1934 * @param Stream This parameter can be one of the following values:
1935 * @arg @ref LL_DMA_STREAM_0
1936 * @arg @ref LL_DMA_STREAM_1
1937 * @arg @ref LL_DMA_STREAM_2
1938 * @arg @ref LL_DMA_STREAM_3
1939 * @arg @ref LL_DMA_STREAM_4
1940 * @arg @ref LL_DMA_STREAM_5
1941 * @arg @ref LL_DMA_STREAM_6
1942 * @arg @ref LL_DMA_STREAM_7
1943 * @retval Between 0 to 0xFFFFFFFF
1944 */
1946 {
1949 return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR));
1950 }
1952 /**
1953 * @brief Get the Memory to Memory Destination address.
1954 * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress
1955 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1956 * @param DMAx DMAx Instance
1957 * @param Stream This parameter can be one of the following values:
1958 * @arg @ref LL_DMA_STREAM_0
1959 * @arg @ref LL_DMA_STREAM_1
1960 * @arg @ref LL_DMA_STREAM_2
1961 * @arg @ref LL_DMA_STREAM_3
1962 * @arg @ref LL_DMA_STREAM_4
1963 * @arg @ref LL_DMA_STREAM_5
1964 * @arg @ref LL_DMA_STREAM_6
1965 * @arg @ref LL_DMA_STREAM_7
1966 * @retval Between 0 to 0xFFFFFFFF
1967 */
1969 {
1972 return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR));
1973 }
1975 /**
1976 * @brief Set Memory 1 address (used in case of Double buffer mode).
1977 * @rmtoll M1AR M1A LL_DMA_SetMemory1Address
1978 * @param DMAx DMAx Instance
1979 * @param Stream This parameter can be one of the following values:
1980 * @arg @ref LL_DMA_STREAM_0
1981 * @arg @ref LL_DMA_STREAM_1
1982 * @arg @ref LL_DMA_STREAM_2
1983 * @arg @ref LL_DMA_STREAM_3
1984 * @arg @ref LL_DMA_STREAM_4
1985 * @arg @ref LL_DMA_STREAM_5
1986 * @arg @ref LL_DMA_STREAM_6
1987 * @arg @ref LL_DMA_STREAM_7
1988 * @param Address Between 0 to 0xFFFFFFFF
1989 * @retval None
1990 */
1991 __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
1992 {
1995 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR, DMA_SxM1AR_M1A, Address);
1996 }
1998 /**
1999 * @brief Get Memory 1 address (used in case of Double buffer mode).
2000 * @rmtoll M1AR M1A LL_DMA_GetMemory1Address
2001 * @param DMAx DMAx Instance
2002 * @param Stream This parameter can be one of the following values:
2003 * @arg @ref LL_DMA_STREAM_0
2004 * @arg @ref LL_DMA_STREAM_1
2005 * @arg @ref LL_DMA_STREAM_2
2006 * @arg @ref LL_DMA_STREAM_3
2007 * @arg @ref LL_DMA_STREAM_4
2008 * @arg @ref LL_DMA_STREAM_5
2009 * @arg @ref LL_DMA_STREAM_6
2010 * @arg @ref LL_DMA_STREAM_7
2011 * @retval Between 0 to 0xFFFFFFFF
2012 */
2014 {
2018 }
2020 /**
2021 * @}
2022 */
2024 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
2025 * @{
2026 */
2028 /**
2029 * @brief Get Stream 0 half transfer flag.
2030 * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0
2031 * @param DMAx DMAx Instance
2032 * @retval State of bit (1 or 0).
2033 */
2035 {
2037 }
2039 /**
2040 * @brief Get Stream 1 half transfer flag.
2041 * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1
2042 * @param DMAx DMAx Instance
2043 * @retval State of bit (1 or 0).
2044 */
2046 {
2048 }
2050 /**
2051 * @brief Get Stream 2 half transfer flag.
2052 * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2
2053 * @param DMAx DMAx Instance
2054 * @retval State of bit (1 or 0).
2055 */
2057 {
2059 }
2061 /**
2062 * @brief Get Stream 3 half transfer flag.
2063 * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3
2064 * @param DMAx DMAx Instance
2065 * @retval State of bit (1 or 0).
2066 */
2068 {
2070 }
2072 /**
2073 * @brief Get Stream 4 half transfer flag.
2074 * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4
2075 * @param DMAx DMAx Instance
2076 * @retval State of bit (1 or 0).
2077 */
2079 {
2081 }
2083 /**
2084 * @brief Get Stream 5 half transfer flag.
2085 * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5
2086 * @param DMAx DMAx Instance
2087 * @retval State of bit (1 or 0).
2088 */
2090 {
2092 }
2094 /**
2095 * @brief Get Stream 6 half transfer flag.
2096 * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6
2097 * @param DMAx DMAx Instance
2098 * @retval State of bit (1 or 0).
2099 */
2101 {
2103 }
2105 /**
2106 * @brief Get Stream 7 half transfer flag.
2107 * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7
2108 * @param DMAx DMAx Instance
2109 * @retval State of bit (1 or 0).
2110 */
2112 {
2114 }
2116 /**
2117 * @brief Get Stream 0 transfer complete flag.
2118 * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0
2119 * @param DMAx DMAx Instance
2120 * @retval State of bit (1 or 0).
2121 */
2123 {
2125 }
2127 /**
2128 * @brief Get Stream 1 transfer complete flag.
2129 * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1
2130 * @param DMAx DMAx Instance
2131 * @retval State of bit (1 or 0).
2132 */
2134 {
2136 }
2138 /**
2139 * @brief Get Stream 2 transfer complete flag.
2140 * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2
2141 * @param DMAx DMAx Instance
2142 * @retval State of bit (1 or 0).
2143 */
2145 {
2147 }
2149 /**
2150 * @brief Get Stream 3 transfer complete flag.
2151 * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3
2152 * @param DMAx DMAx Instance
2153 * @retval State of bit (1 or 0).
2154 */
2156 {
2158 }
2160 /**
2161 * @brief Get Stream 4 transfer complete flag.
2162 * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4
2163 * @param DMAx DMAx Instance
2164 * @retval State of bit (1 or 0).
2165 */
2167 {
2169 }
2171 /**
2172 * @brief Get Stream 5 transfer complete flag.
2173 * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5
2174 * @param DMAx DMAx Instance
2175 * @retval State of bit (1 or 0).
2176 */
2178 {
2180 }
2182 /**
2183 * @brief Get Stream 6 transfer complete flag.
2184 * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6
2185 * @param DMAx DMAx Instance
2186 * @retval State of bit (1 or 0).
2187 */
2189 {
2191 }
2193 /**
2194 * @brief Get Stream 7 transfer complete flag.
2195 * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7
2196 * @param DMAx DMAx Instance
2197 * @retval State of bit (1 or 0).
2198 */
2200 {
2202 }
2204 /**
2205 * @brief Get Stream 0 transfer error flag.
2206 * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0
2207 * @param DMAx DMAx Instance
2208 * @retval State of bit (1 or 0).
2209 */
2211 {
2213 }
2215 /**
2216 * @brief Get Stream 1 transfer error flag.
2217 * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1
2218 * @param DMAx DMAx Instance
2219 * @retval State of bit (1 or 0).
2220 */
2222 {
2224 }
2226 /**
2227 * @brief Get Stream 2 transfer error flag.
2228 * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2
2229 * @param DMAx DMAx Instance
2230 * @retval State of bit (1 or 0).
2231 */
2233 {
2235 }
2237 /**
2238 * @brief Get Stream 3 transfer error flag.
2239 * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3
2240 * @param DMAx DMAx Instance
2241 * @retval State of bit (1 or 0).
2242 */
2244 {
2246 }
2248 /**
2249 * @brief Get Stream 4 transfer error flag.
2250 * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4
2251 * @param DMAx DMAx Instance
2252 * @retval State of bit (1 or 0).
2253 */
2255 {
2257 }
2259 /**
2260 * @brief Get Stream 5 transfer error flag.
2261 * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5
2262 * @param DMAx DMAx Instance
2263 * @retval State of bit (1 or 0).
2264 */
2266 {
2268 }
2270 /**
2271 * @brief Get Stream 6 transfer error flag.
2272 * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6
2273 * @param DMAx DMAx Instance
2274 * @retval State of bit (1 or 0).
2275 */
2277 {
2279 }
2281 /**
2282 * @brief Get Stream 7 transfer error flag.
2283 * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7
2284 * @param DMAx DMAx Instance
2285 * @retval State of bit (1 or 0).
2286 */
2288 {
2290 }
2292 /**
2293 * @brief Get Stream 0 direct mode error flag.
2294 * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0
2295 * @param DMAx DMAx Instance
2296 * @retval State of bit (1 or 0).
2297 */
2299 {
2301 }
2303 /**
2304 * @brief Get Stream 1 direct mode error flag.
2305 * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1
2306 * @param DMAx DMAx Instance
2307 * @retval State of bit (1 or 0).
2308 */
2310 {
2312 }
2314 /**
2315 * @brief Get Stream 2 direct mode error flag.
2316 * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2
2317 * @param DMAx DMAx Instance
2318 * @retval State of bit (1 or 0).
2319 */
2321 {
2323 }
2325 /**
2326 * @brief Get Stream 3 direct mode error flag.
2327 * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3
2328 * @param DMAx DMAx Instance
2329 * @retval State of bit (1 or 0).
2330 */
2332 {
2334 }
2336 /**
2337 * @brief Get Stream 4 direct mode error flag.
2338 * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4
2339 * @param DMAx DMAx Instance
2340 * @retval State of bit (1 or 0).
2341 */
2343 {
2345 }
2347 /**
2348 * @brief Get Stream 5 direct mode error flag.
2349 * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5
2350 * @param DMAx DMAx Instance
2351 * @retval State of bit (1 or 0).
2352 */
2354 {
2356 }
2358 /**
2359 * @brief Get Stream 6 direct mode error flag.
2360 * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6
2361 * @param DMAx DMAx Instance
2362 * @retval State of bit (1 or 0).
2363 */
2365 {
2367 }
2369 /**
2370 * @brief Get Stream 7 direct mode error flag.
2371 * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7
2372 * @param DMAx DMAx Instance
2373 * @retval State of bit (1 or 0).
2374 */
2376 {
2378 }
2380 /**
2381 * @brief Get Stream 0 FIFO error flag.
2382 * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0
2383 * @param DMAx DMAx Instance
2384 * @retval State of bit (1 or 0).
2385 */
2387 {
2389 }
2391 /**
2392 * @brief Get Stream 1 FIFO error flag.
2393 * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1
2394 * @param DMAx DMAx Instance
2395 * @retval State of bit (1 or 0).
2396 */
2398 {
2400 }
2402 /**
2403 * @brief Get Stream 2 FIFO error flag.
2404 * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2
2405 * @param DMAx DMAx Instance
2406 * @retval State of bit (1 or 0).
2407 */
2409 {
2411 }
2413 /**
2414 * @brief Get Stream 3 FIFO error flag.
2415 * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3
2416 * @param DMAx DMAx Instance
2417 * @retval State of bit (1 or 0).
2418 */
2420 {
2422 }
2424 /**
2425 * @brief Get Stream 4 FIFO error flag.
2426 * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4
2427 * @param DMAx DMAx Instance
2428 * @retval State of bit (1 or 0).
2429 */
2431 {
2433 }
2435 /**
2436 * @brief Get Stream 5 FIFO error flag.
2437 * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5
2438 * @param DMAx DMAx Instance
2439 * @retval State of bit (1 or 0).
2440 */
2442 {
2444 }
2446 /**
2447 * @brief Get Stream 6 FIFO error flag.
2448 * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6
2449 * @param DMAx DMAx Instance
2450 * @retval State of bit (1 or 0).
2451 */
2453 {
2455 }
2457 /**
2458 * @brief Get Stream 7 FIFO error flag.
2459 * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7
2460 * @param DMAx DMAx Instance
2461 * @retval State of bit (1 or 0).
2462 */
2464 {
2466 }
2468 /**
2469 * @brief Clear Stream 0 half transfer flag.
2470 * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0
2471 * @param DMAx DMAx Instance
2472 * @retval None
2473 */
2475 {
2477 }
2479 /**
2480 * @brief Clear Stream 1 half transfer flag.
2481 * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1
2482 * @param DMAx DMAx Instance
2483 * @retval None
2484 */
2486 {
2488 }
2490 /**
2491 * @brief Clear Stream 2 half transfer flag.
2492 * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2
2493 * @param DMAx DMAx Instance
2494 * @retval None
2495 */
2497 {
2499 }
2501 /**
2502 * @brief Clear Stream 3 half transfer flag.
2503 * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3
2504 * @param DMAx DMAx Instance
2505 * @retval None
2506 */
2508 {
2510 }
2512 /**
2513 * @brief Clear Stream 4 half transfer flag.
2514 * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4
2515 * @param DMAx DMAx Instance
2516 * @retval None
2517 */
2519 {
2521 }
2523 /**
2524 * @brief Clear Stream 5 half transfer flag.
2525 * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5
2526 * @param DMAx DMAx Instance
2527 * @retval None
2528 */
2530 {
2532 }
2534 /**
2535 * @brief Clear Stream 6 half transfer flag.
2536 * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6
2537 * @param DMAx DMAx Instance
2538 * @retval None
2539 */
2541 {
2543 }
2545 /**
2546 * @brief Clear Stream 7 half transfer flag.
2547 * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7
2548 * @param DMAx DMAx Instance
2549 * @retval None
2550 */
2552 {
2554 }
2556 /**
2557 * @brief Clear Stream 0 transfer complete flag.
2558 * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0
2559 * @param DMAx DMAx Instance
2560 * @retval None
2561 */
2563 {
2565 }
2567 /**
2568 * @brief Clear Stream 1 transfer complete flag.
2569 * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1
2570 * @param DMAx DMAx Instance
2571 * @retval None
2572 */
2574 {
2576 }
2578 /**
2579 * @brief Clear Stream 2 transfer complete flag.
2580 * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2
2581 * @param DMAx DMAx Instance
2582 * @retval None
2583 */
2585 {
2587 }
2589 /**
2590 * @brief Clear Stream 3 transfer complete flag.
2591 * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3
2592 * @param DMAx DMAx Instance
2593 * @retval None
2594 */
2596 {
2598 }
2600 /**
2601 * @brief Clear Stream 4 transfer complete flag.
2602 * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4
2603 * @param DMAx DMAx Instance
2604 * @retval None
2605 */
2607 {
2609 }
2611 /**
2612 * @brief Clear Stream 5 transfer complete flag.
2613 * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5
2614 * @param DMAx DMAx Instance
2615 * @retval None
2616 */
2618 {
2620 }
2622 /**
2623 * @brief Clear Stream 6 transfer complete flag.
2624 * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6
2625 * @param DMAx DMAx Instance
2626 * @retval None
2627 */
2629 {
2631 }
2633 /**
2634 * @brief Clear Stream 7 transfer complete flag.
2635 * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7
2636 * @param DMAx DMAx Instance
2637 * @retval None
2638 */
2640 {
2642 }
2644 /**
2645 * @brief Clear Stream 0 transfer error flag.
2646 * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0
2647 * @param DMAx DMAx Instance
2648 * @retval None
2649 */
2651 {
2653 }
2655 /**
2656 * @brief Clear Stream 1 transfer error flag.
2657 * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1
2658 * @param DMAx DMAx Instance
2659 * @retval None
2660 */
2662 {
2664 }
2666 /**
2667 * @brief Clear Stream 2 transfer error flag.
2668 * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2
2669 * @param DMAx DMAx Instance
2670 * @retval None
2671 */
2673 {
2675 }
2677 /**
2678 * @brief Clear Stream 3 transfer error flag.
2679 * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3
2680 * @param DMAx DMAx Instance
2681 * @retval None
2682 */
2684 {
2686 }
2688 /**
2689 * @brief Clear Stream 4 transfer error flag.
2690 * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4
2691 * @param DMAx DMAx Instance
2692 * @retval None
2693 */
2695 {
2697 }
2699 /**
2700 * @brief Clear Stream 5 transfer error flag.
2701 * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5
2702 * @param DMAx DMAx Instance
2703 * @retval None
2704 */
2706 {
2708 }
2710 /**
2711 * @brief Clear Stream 6 transfer error flag.
2712 * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6
2713 * @param DMAx DMAx Instance
2714 * @retval None
2715 */
2717 {
2719 }
2721 /**
2722 * @brief Clear Stream 7 transfer error flag.
2723 * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7
2724 * @param DMAx DMAx Instance
2725 * @retval None
2726 */
2728 {
2730 }
2732 /**
2733 * @brief Clear Stream 0 direct mode error flag.
2734 * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0
2735 * @param DMAx DMAx Instance
2736 * @retval None
2737 */
2739 {
2741 }
2743 /**
2744 * @brief Clear Stream 1 direct mode error flag.
2745 * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1
2746 * @param DMAx DMAx Instance
2747 * @retval None
2748 */
2750 {
2752 }
2754 /**
2755 * @brief Clear Stream 2 direct mode error flag.
2756 * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2
2757 * @param DMAx DMAx Instance
2758 * @retval None
2759 */
2761 {
2763 }
2765 /**
2766 * @brief Clear Stream 3 direct mode error flag.
2767 * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3
2768 * @param DMAx DMAx Instance
2769 * @retval None
2770 */
2772 {
2774 }
2776 /**
2777 * @brief Clear Stream 4 direct mode error flag.
2778 * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4
2779 * @param DMAx DMAx Instance
2780 * @retval None
2781 */
2783 {
2785 }
2787 /**
2788 * @brief Clear Stream 5 direct mode error flag.
2789 * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5
2790 * @param DMAx DMAx Instance
2791 * @retval None
2792 */
2794 {
2796 }
2798 /**
2799 * @brief Clear Stream 6 direct mode error flag.
2800 * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6
2801 * @param DMAx DMAx Instance
2802 * @retval None
2803 */
2805 {
2807 }
2809 /**
2810 * @brief Clear Stream 7 direct mode error flag.
2811 * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7
2812 * @param DMAx DMAx Instance
2813 * @retval None
2814 */
2816 {
2818 }
2820 /**
2821 * @brief Clear Stream 0 FIFO error flag.
2822 * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0
2823 * @param DMAx DMAx Instance
2824 * @retval None
2825 */
2827 {
2829 }
2831 /**
2832 * @brief Clear Stream 1 FIFO error flag.
2833 * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1
2834 * @param DMAx DMAx Instance
2835 * @retval None
2836 */
2838 {
2840 }
2842 /**
2843 * @brief Clear Stream 2 FIFO error flag.
2844 * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2
2845 * @param DMAx DMAx Instance
2846 * @retval None
2847 */
2849 {
2851 }
2853 /**
2854 * @brief Clear Stream 3 FIFO error flag.
2855 * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3
2856 * @param DMAx DMAx Instance
2857 * @retval None
2858 */
2860 {
2862 }
2864 /**
2865 * @brief Clear Stream 4 FIFO error flag.
2866 * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4
2867 * @param DMAx DMAx Instance
2868 * @retval None
2869 */
2871 {
2873 }
2875 /**
2876 * @brief Clear Stream 5 FIFO error flag.
2877 * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5
2878 * @param DMAx DMAx Instance
2879 * @retval None
2880 */
2882 {
2884 }
2886 /**
2887 * @brief Clear Stream 6 FIFO error flag.
2888 * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6
2889 * @param DMAx DMAx Instance
2890 * @retval None
2891 */
2893 {
2895 }
2897 /**
2898 * @brief Clear Stream 7 FIFO error flag.
2899 * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7
2900 * @param DMAx DMAx Instance
2901 * @retval None
2902 */
2904 {
2906 }
2908 /**
2909 * @}
2910 */
2912 /** @defgroup DMA_LL_EF_IT_Management IT_Management
2913 * @{
2914 */
2916 /**
2917 * @brief Enable Half transfer interrupt.
2918 * @rmtoll CR HTIE LL_DMA_EnableIT_HT
2919 * @param DMAx DMAx Instance
2920 * @param Stream This parameter can be one of the following values:
2921 * @arg @ref LL_DMA_STREAM_0
2922 * @arg @ref LL_DMA_STREAM_1
2923 * @arg @ref LL_DMA_STREAM_2
2924 * @arg @ref LL_DMA_STREAM_3
2925 * @arg @ref LL_DMA_STREAM_4
2926 * @arg @ref LL_DMA_STREAM_5
2927 * @arg @ref LL_DMA_STREAM_6
2928 * @arg @ref LL_DMA_STREAM_7
2929 * @retval None
2930 */
2932 {
2935 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE);
2936 }
2938 /**
2939 * @brief Enable Transfer error interrupt.
2940 * @rmtoll CR TEIE LL_DMA_EnableIT_TE
2941 * @param DMAx DMAx Instance
2942 * @param Stream This parameter can be one of the following values:
2943 * @arg @ref LL_DMA_STREAM_0
2944 * @arg @ref LL_DMA_STREAM_1
2945 * @arg @ref LL_DMA_STREAM_2
2946 * @arg @ref LL_DMA_STREAM_3
2947 * @arg @ref LL_DMA_STREAM_4
2948 * @arg @ref LL_DMA_STREAM_5
2949 * @arg @ref LL_DMA_STREAM_6
2950 * @arg @ref LL_DMA_STREAM_7
2951 * @retval None
2952 */
2954 {
2957 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE);
2958 }
2960 /**
2961 * @brief Enable Transfer complete interrupt.
2962 * @rmtoll CR TCIE LL_DMA_EnableIT_TC
2963 * @param DMAx DMAx Instance
2964 * @param Stream This parameter can be one of the following values:
2965 * @arg @ref LL_DMA_STREAM_0
2966 * @arg @ref LL_DMA_STREAM_1
2967 * @arg @ref LL_DMA_STREAM_2
2968 * @arg @ref LL_DMA_STREAM_3
2969 * @arg @ref LL_DMA_STREAM_4
2970 * @arg @ref LL_DMA_STREAM_5
2971 * @arg @ref LL_DMA_STREAM_6
2972 * @arg @ref LL_DMA_STREAM_7
2973 * @retval None
2974 */
2976 {
2979 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE);
2980 }
2982 /**
2983 * @brief Enable Direct mode error interrupt.
2984 * @rmtoll CR DMEIE LL_DMA_EnableIT_DME
2985 * @param DMAx DMAx Instance
2986 * @param Stream This parameter can be one of the following values:
2987 * @arg @ref LL_DMA_STREAM_0
2988 * @arg @ref LL_DMA_STREAM_1
2989 * @arg @ref LL_DMA_STREAM_2
2990 * @arg @ref LL_DMA_STREAM_3
2991 * @arg @ref LL_DMA_STREAM_4
2992 * @arg @ref LL_DMA_STREAM_5
2993 * @arg @ref LL_DMA_STREAM_6
2994 * @arg @ref LL_DMA_STREAM_7
2995 * @retval None
2996 */
2998 {
3001 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE);
3002 }
3004 /**
3005 * @brief Enable FIFO error interrupt.
3006 * @rmtoll FCR FEIE LL_DMA_EnableIT_FE
3007 * @param DMAx DMAx Instance
3008 * @param Stream This parameter can be one of the following values:
3009 * @arg @ref LL_DMA_STREAM_0
3010 * @arg @ref LL_DMA_STREAM_1
3011 * @arg @ref LL_DMA_STREAM_2
3012 * @arg @ref LL_DMA_STREAM_3
3013 * @arg @ref LL_DMA_STREAM_4
3014 * @arg @ref LL_DMA_STREAM_5
3015 * @arg @ref LL_DMA_STREAM_6
3016 * @arg @ref LL_DMA_STREAM_7
3017 * @retval None
3018 */
3020 {
3023 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE);
3024 }
3026 /**
3027 * @brief Disable Half transfer interrupt.
3028 * @rmtoll CR HTIE LL_DMA_DisableIT_HT
3029 * @param DMAx DMAx Instance
3030 * @param Stream This parameter can be one of the following values:
3031 * @arg @ref LL_DMA_STREAM_0
3032 * @arg @ref LL_DMA_STREAM_1
3033 * @arg @ref LL_DMA_STREAM_2
3034 * @arg @ref LL_DMA_STREAM_3
3035 * @arg @ref LL_DMA_STREAM_4
3036 * @arg @ref LL_DMA_STREAM_5
3037 * @arg @ref LL_DMA_STREAM_6
3038 * @arg @ref LL_DMA_STREAM_7
3039 * @retval None
3040 */
3042 {
3045 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE);
3046 }
3048 /**
3049 * @brief Disable Transfer error interrupt.
3050 * @rmtoll CR TEIE LL_DMA_DisableIT_TE
3051 * @param DMAx DMAx Instance
3052 * @param Stream This parameter can be one of the following values:
3053 * @arg @ref LL_DMA_STREAM_0
3054 * @arg @ref LL_DMA_STREAM_1
3055 * @arg @ref LL_DMA_STREAM_2
3056 * @arg @ref LL_DMA_STREAM_3
3057 * @arg @ref LL_DMA_STREAM_4
3058 * @arg @ref LL_DMA_STREAM_5
3059 * @arg @ref LL_DMA_STREAM_6
3060 * @arg @ref LL_DMA_STREAM_7
3061 * @retval None
3062 */
3064 {
3067 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE);
3068 }
3070 /**
3071 * @brief Disable Transfer complete interrupt.
3072 * @rmtoll CR TCIE LL_DMA_DisableIT_TC
3073 * @param DMAx DMAx Instance
3074 * @param Stream This parameter can be one of the following values:
3075 * @arg @ref LL_DMA_STREAM_0
3076 * @arg @ref LL_DMA_STREAM_1
3077 * @arg @ref LL_DMA_STREAM_2
3078 * @arg @ref LL_DMA_STREAM_3
3079 * @arg @ref LL_DMA_STREAM_4
3080 * @arg @ref LL_DMA_STREAM_5
3081 * @arg @ref LL_DMA_STREAM_6
3082 * @arg @ref LL_DMA_STREAM_7
3083 * @retval None
3084 */
3086 {
3089 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE);
3090 }
3092 /**
3093 * @brief Disable Direct mode error interrupt.
3094 * @rmtoll CR DMEIE LL_DMA_DisableIT_DME
3095 * @param DMAx DMAx Instance
3096 * @param Stream This parameter can be one of the following values:
3097 * @arg @ref LL_DMA_STREAM_0
3098 * @arg @ref LL_DMA_STREAM_1
3099 * @arg @ref LL_DMA_STREAM_2
3100 * @arg @ref LL_DMA_STREAM_3
3101 * @arg @ref LL_DMA_STREAM_4
3102 * @arg @ref LL_DMA_STREAM_5
3103 * @arg @ref LL_DMA_STREAM_6
3104 * @arg @ref LL_DMA_STREAM_7
3105 * @retval None
3106 */
3108 {
3111 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE);
3112 }
3114 /**
3115 * @brief Disable FIFO error interrupt.
3116 * @rmtoll FCR FEIE LL_DMA_DisableIT_FE
3117 * @param DMAx DMAx Instance
3118 * @param Stream This parameter can be one of the following values:
3119 * @arg @ref LL_DMA_STREAM_0
3120 * @arg @ref LL_DMA_STREAM_1
3121 * @arg @ref LL_DMA_STREAM_2
3122 * @arg @ref LL_DMA_STREAM_3
3123 * @arg @ref LL_DMA_STREAM_4
3124 * @arg @ref LL_DMA_STREAM_5
3125 * @arg @ref LL_DMA_STREAM_6
3126 * @arg @ref LL_DMA_STREAM_7
3127 * @retval None
3128 */
3130 {
3133 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE);
3134 }
3136 /**
3137 * @brief Check if Half transfer interrup is enabled.
3138 * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT
3139 * @param DMAx DMAx Instance
3140 * @param Stream This parameter can be one of the following values:
3141 * @arg @ref LL_DMA_STREAM_0
3142 * @arg @ref LL_DMA_STREAM_1
3143 * @arg @ref LL_DMA_STREAM_2
3144 * @arg @ref LL_DMA_STREAM_3
3145 * @arg @ref LL_DMA_STREAM_4
3146 * @arg @ref LL_DMA_STREAM_5
3147 * @arg @ref LL_DMA_STREAM_6
3148 * @arg @ref LL_DMA_STREAM_7
3149 * @retval State of bit (1 or 0).
3150 */
3152 {
3155 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE) ? 1UL : 0UL);
3156 }
3158 /**
3159 * @brief Check if Transfer error nterrup is enabled.
3160 * @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE
3161 * @param DMAx DMAx Instance
3162 * @param Stream This parameter can be one of the following values:
3163 * @arg @ref LL_DMA_STREAM_0
3164 * @arg @ref LL_DMA_STREAM_1
3165 * @arg @ref LL_DMA_STREAM_2
3166 * @arg @ref LL_DMA_STREAM_3
3167 * @arg @ref LL_DMA_STREAM_4
3168 * @arg @ref LL_DMA_STREAM_5
3169 * @arg @ref LL_DMA_STREAM_6
3170 * @arg @ref LL_DMA_STREAM_7
3171 * @retval State of bit (1 or 0).
3172 */
3174 {
3177 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE) ? 1UL : 0UL);
3178 }
3180 /**
3181 * @brief Check if Transfer complete interrup is enabled.
3182 * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC
3183 * @param DMAx DMAx Instance
3184 * @param Stream This parameter can be one of the following values:
3185 * @arg @ref LL_DMA_STREAM_0
3186 * @arg @ref LL_DMA_STREAM_1
3187 * @arg @ref LL_DMA_STREAM_2
3188 * @arg @ref LL_DMA_STREAM_3
3189 * @arg @ref LL_DMA_STREAM_4
3190 * @arg @ref LL_DMA_STREAM_5
3191 * @arg @ref LL_DMA_STREAM_6
3192 * @arg @ref LL_DMA_STREAM_7
3193 * @retval State of bit (1 or 0).
3194 */
3196 {
3199 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE) ? 1UL : 0UL);
3200 }
3202 /**
3203 * @brief Check if Direct mode error interrupt is enabled.
3204 * @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME
3205 * @param DMAx DMAx Instance
3206 * @param Stream This parameter can be one of the following values:
3207 * @arg @ref LL_DMA_STREAM_0
3208 * @arg @ref LL_DMA_STREAM_1
3209 * @arg @ref LL_DMA_STREAM_2
3210 * @arg @ref LL_DMA_STREAM_3
3211 * @arg @ref LL_DMA_STREAM_4
3212 * @arg @ref LL_DMA_STREAM_5
3213 * @arg @ref LL_DMA_STREAM_6
3214 * @arg @ref LL_DMA_STREAM_7
3215 * @retval State of bit (1 or 0).
3216 */
3218 {
3221 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE) ? 1UL : 0UL);
3222 }
3224 /**
3225 * @brief Check if FIFO error interrup is enabled.
3226 * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE
3227 * @param DMAx DMAx Instance
3228 * @param Stream This parameter can be one of the following values:
3229 * @arg @ref LL_DMA_STREAM_0
3230 * @arg @ref LL_DMA_STREAM_1
3231 * @arg @ref LL_DMA_STREAM_2
3232 * @arg @ref LL_DMA_STREAM_3
3233 * @arg @ref LL_DMA_STREAM_4
3234 * @arg @ref LL_DMA_STREAM_5
3235 * @arg @ref LL_DMA_STREAM_6
3236 * @arg @ref LL_DMA_STREAM_7
3237 * @retval State of bit (1 or 0).
3238 */
3240 {
3243 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE) ? 1UL : 0UL);
3244 }
3246 /**
3247 * @}
3248 */
3250 #if defined(USE_FULL_LL_DRIVER)
3251 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
3252 * @{
3253 */
3259 /**
3260 * @}
3261 */
3264 /**
3265 * @}
3266 */
3268 /**
3269 * @}
3270 */
3274 /**
3275 * @}
3276 */
3278 #ifdef __cplusplus
3279 }
3280 #endif
3284 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/