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Merge pull request #11270 from haslinghuis/rename_attr
[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_ll_dma2d.h
blob6bfc46799196ba7b7edab0404896ca67475206b0
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_dma2d.h
4 * @author MCD Application Team
5 * @brief Header file of DMA2D LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_LL_DMA2D_H
22 #define STM32H7xx_LL_DMA2D_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx.h"
30
31 /** @addtogroup STM32H7xx_LL_Driver
32 * @{
33 */
34
35 #if defined (DMA2D)
36
37 /** @defgroup DMA2D_LL DMA2D
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /* Private macros ------------------------------------------------------------*/
45 #if defined(USE_FULL_LL_DRIVER)
46 /** @defgroup DMA2D_LL_Private_Macros DMA2D Private Macros
47 * @{
48 */
49
50 /**
51 * @}
52 */
53 #endif /*USE_FULL_LL_DRIVER*/
54
55 /* Exported types ------------------------------------------------------------*/
56 #if defined(USE_FULL_LL_DRIVER)
57 /** @defgroup DMA2D_LL_ES_Init_Struct DMA2D Exported Init structures
58 * @{
59 */
60
61 /**
62 * @brief LL DMA2D Init Structure Definition
63 */
64 typedef struct
65 {
66 uint32_t Mode; /*!< Specifies the DMA2D transfer mode.
67 - This parameter can be one value of @ref DMA2D_LL_EC_MODE.
68
69 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetMode().*/
70
71 uint32_t ColorMode; /*!< Specifies the color format of the output image.
72 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
73
74 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */
75
76 uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
77 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
78 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
79 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
80 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
81 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
82
83 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
84 function @ref LL_DMA2D_ConfigOutputColor(). */
85
86 uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
87 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
88 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
89 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
90 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
91 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
92
93 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
94 function @ref LL_DMA2D_ConfigOutputColor(). */
95
96 uint32_t OutputRed; /*!< Specifies the Red value of the output image.
97 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
98 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
99 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
100 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
101 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
102
103 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
104 function @ref LL_DMA2D_ConfigOutputColor(). */
105
106 uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
107 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
108 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
109 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
110 - This parameter is not considered if RGB888 or RGB565 color mode is selected.
111
112 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
113 function @ref LL_DMA2D_ConfigOutputColor(). */
114
115 uint32_t OutputMemoryAddress; /*!< Specifies the memory address.
116 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
117
118 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
119
120 uint32_t OutputSwapMode; /*!< Specifies the output swap mode color format of the output image.
121 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_SWAP_MODE.
122
123 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputSwapMode(). */
124
125 uint32_t LineOffsetMode; /*!< Specifies the output line offset mode.
126 - This parameter can be one value of @ref DMA2D_LL_EC_LINE_OFFSET_MODE.
127
128 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffsetMode(). */
129
130 uint32_t LineOffset; /*!< Specifies the output line offset value.
131 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
132
133 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffset(). */
134
135 uint32_t NbrOfLines; /*!< Specifies the number of lines of the area to be transferred.
136 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
137
138 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
139
140 uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transfered.
141 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
142
143 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
144
145 uint32_t AlphaInversionMode; /*!< Specifies the output alpha inversion mode.
146 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
147
148 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */
149
150 uint32_t RBSwapMode; /*!< Specifies the output Red Blue swap mode.
151 - This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP.
152
153 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */
154
155 } LL_DMA2D_InitTypeDef;
156
157 /**
158 * @brief LL DMA2D Layer Configuration Structure Definition
159 */
160 typedef struct
161 {
162 uint32_t MemoryAddress; /*!< Specifies the foreground or background memory address.
163 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
164
165 This parameter can be modified afterwards using unitary functions
166 - @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer,
167 - @ref LL_DMA2D_BGND_SetMemAddr() for background layer. */
168
169 uint32_t LineOffset; /*!< Specifies the foreground or background line offset value.
170 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
171
172 This parameter can be modified afterwards using unitary functions
173 - @ref LL_DMA2D_FGND_SetLineOffset() for foreground layer,
174 - @ref LL_DMA2D_BGND_SetLineOffset() for background layer. */
175
176 uint32_t ColorMode; /*!< Specifies the foreground or background color mode.
177 - This parameter can be one value of @ref DMA2D_LL_EC_INPUT_COLOR_MODE.
178
179 This parameter can be modified afterwards using unitary functions
180 - @ref LL_DMA2D_FGND_SetColorMode() for foreground layer,
181 - @ref LL_DMA2D_BGND_SetColorMode() for background layer. */
182
183 uint32_t CLUTColorMode; /*!< Specifies the foreground or background CLUT color mode.
184 - This parameter can be one value of @ref DMA2D_LL_EC_CLUT_COLOR_MODE.
185
186 This parameter can be modified afterwards using unitary functions
187 - @ref LL_DMA2D_FGND_SetCLUTColorMode() for foreground layer,
188 - @ref LL_DMA2D_BGND_SetCLUTColorMode() for background layer. */
189
190 uint32_t CLUTSize; /*!< Specifies the foreground or background CLUT size.
191 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
192
193 This parameter can be modified afterwards using unitary functions
194 - @ref LL_DMA2D_FGND_SetCLUTSize() for foreground layer,
195 - @ref LL_DMA2D_BGND_SetCLUTSize() for background layer. */
196
197 uint32_t AlphaMode; /*!< Specifies the foreground or background alpha mode.
198 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_MODE.
199
200 This parameter can be modified afterwards using unitary functions
201 - @ref LL_DMA2D_FGND_SetAlphaMode() for foreground layer,
202 - @ref LL_DMA2D_BGND_SetAlphaMode() for background layer. */
203
204 uint32_t Alpha; /*!< Specifies the foreground or background Alpha value.
205 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
206
207 This parameter can be modified afterwards using unitary functions
208 - @ref LL_DMA2D_FGND_SetAlpha() for foreground layer,
209 - @ref LL_DMA2D_BGND_SetAlpha() for background layer. */
210
211 uint32_t Blue; /*!< Specifies the foreground or background Blue color value.
212 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
213
214 This parameter can be modified afterwards using unitary functions
215 - @ref LL_DMA2D_FGND_SetBlueColor() for foreground layer,
216 - @ref LL_DMA2D_BGND_SetBlueColor() for background layer. */
217
218 uint32_t Green; /*!< Specifies the foreground or background Green color value.
219 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
220
221 This parameter can be modified afterwards using unitary functions
222 - @ref LL_DMA2D_FGND_SetGreenColor() for foreground layer,
223 - @ref LL_DMA2D_BGND_SetGreenColor() for background layer. */
224
225 uint32_t Red; /*!< Specifies the foreground or background Red color value.
226 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
227
228 This parameter can be modified afterwards using unitary functions
229 - @ref LL_DMA2D_FGND_SetRedColor() for foreground layer,
230 - @ref LL_DMA2D_BGND_SetRedColor() for background layer. */
231
232 uint32_t CLUTMemoryAddress; /*!< Specifies the foreground or background CLUT memory address.
233 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
234
235 This parameter can be modified afterwards using unitary functions
236 - @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer,
237 - @ref LL_DMA2D_BGND_SetCLUTMemAddr() for background layer. */
238
239 uint32_t AlphaInversionMode; /*!< Specifies the foreground or background alpha inversion mode.
240 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
241
242 This parameter can be modified afterwards using unitary functions
243 - @ref LL_DMA2D_FGND_SetAlphaInvMode() for foreground layer,
244 - @ref LL_DMA2D_BGND_SetAlphaInvMode() for background layer. */
245
246 uint32_t RBSwapMode; /*!< Specifies the foreground or background Red Blue swap mode.
247 This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP .
248
249 This parameter can be modified afterwards using unitary functions
250 - @ref LL_DMA2D_FGND_SetRBSwapMode() for foreground layer,
251 - @ref LL_DMA2D_BGND_SetRBSwapMode() for background layer. */
252
253 uint32_t ChromaSubSampling; /*!< Configure the chroma sub-sampling mode for the YCbCr color mode
254 This parameter is applicable for foreground layer only.
255 This parameter can be one value of @ref DMA2D_LL_CHROMA_SUB_SAMPLING
256
257 This parameter can be modified afterwards using unitary functions
258 - @ref LL_DMA2D_FGND_SetChrSubSampling() for foreground layer. */
259
260 } LL_DMA2D_LayerCfgTypeDef;
261
262 /**
263 * @brief LL DMA2D Output Color Structure Definition
264 */
265 typedef struct
266 {
267 uint32_t ColorMode; /*!< Specifies the color format of the output image.
268 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
269
270 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */
271
272 uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
273 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
274 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
275 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
276 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
277 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
278
279 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
280 function @ref LL_DMA2D_ConfigOutputColor(). */
281
282 uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
283 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
284 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
285 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
286 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
287 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
288
289 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
290 function @ref LL_DMA2D_ConfigOutputColor(). */
291
292 uint32_t OutputRed; /*!< Specifies the Red value of the output image.
293 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
294 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
295 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
296 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
297 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
298
299 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
300 function @ref LL_DMA2D_ConfigOutputColor(). */
301
302 uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
303 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
304 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
305 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
306 - This parameter is not considered if RGB888 or RGB565 color mode is selected.
307
308 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
309 function @ref LL_DMA2D_ConfigOutputColor(). */
310
311 } LL_DMA2D_ColorTypeDef;
312
313 /**
314 * @}
315 */
316 #endif /* USE_FULL_LL_DRIVER */
317
318 /* Exported constants --------------------------------------------------------*/
319 /** @defgroup DMA2D_LL_Exported_Constants DMA2D Exported Constants
320 * @{
321 */
322
323 /** @defgroup DMA2D_LL_EC_GET_FLAG Get Flags Defines
324 * @brief Flags defines which can be used with LL_DMA2D_ReadReg function
325 * @{
326 */
327 #define LL_DMA2D_FLAG_CEIF DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
328 #define LL_DMA2D_FLAG_CTCIF DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */
329 #define LL_DMA2D_FLAG_CAEIF DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */
330 #define LL_DMA2D_FLAG_TWIF DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
331 #define LL_DMA2D_FLAG_TCIF DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
332 #define LL_DMA2D_FLAG_TEIF DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
333 /**
334 * @}
335 */
336
337 /** @defgroup DMA2D_LL_EC_IT IT Defines
338 * @brief IT defines which can be used with LL_DMA2D_ReadReg and LL_DMA2D_WriteReg functions
339 * @{
340 */
341 #define LL_DMA2D_IT_CEIE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
342 #define LL_DMA2D_IT_CTCIE DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */
343 #define LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
344 #define LL_DMA2D_IT_TWIE DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
345 #define LL_DMA2D_IT_TCIE DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
346 #define LL_DMA2D_IT_TEIE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
347 /**
348 * @}
349 */
350
351 /** @defgroup DMA2D_LL_EC_MODE Mode
352 * @{
353 */
354 #define LL_DMA2D_MODE_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */
355 #define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
356 #define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
357 #define LL_DMA2D_MODE_R2M (DMA2D_CR_MODE_0|DMA2D_CR_MODE_1) /*!< DMA2D register to memory transfer mode */
358 #define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color foreground */
359 #define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG (DMA2D_CR_MODE_0|DMA2D_CR_MODE_2) /*!< DMA2D memory to memory with blending transfer mode and fixed color background */
360 /**
361 * @}
362 */
363
364 /** @defgroup DMA2D_LL_EC_OUTPUT_COLOR_MODE Output Color Mode
365 * @{
366 */
367 #define LL_DMA2D_OUTPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
368 #define LL_DMA2D_OUTPUT_MODE_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 */
369 #define LL_DMA2D_OUTPUT_MODE_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 */
370 #define LL_DMA2D_OUTPUT_MODE_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 */
371 #define LL_DMA2D_OUTPUT_MODE_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 */
372 /**
373 * @}
374 */
375
376 /** @defgroup DMA2D_LL_EC_INPUT_COLOR_MODE Input Color Mode
377 * @{
378 */
379 #define LL_DMA2D_INPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
380 #define LL_DMA2D_INPUT_MODE_RGB888 DMA2D_FGPFCCR_CM_0 /*!< RGB888 */
381 #define LL_DMA2D_INPUT_MODE_RGB565 DMA2D_FGPFCCR_CM_1 /*!< RGB565 */
382 #define LL_DMA2D_INPUT_MODE_ARGB1555 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1) /*!< ARGB1555 */
383 #define LL_DMA2D_INPUT_MODE_ARGB4444 DMA2D_FGPFCCR_CM_2 /*!< ARGB4444 */
384 #define LL_DMA2D_INPUT_MODE_L8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2) /*!< L8 */
385 #define LL_DMA2D_INPUT_MODE_AL44 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL44 */
386 #define LL_DMA2D_INPUT_MODE_AL88 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL88 */
387 #define LL_DMA2D_INPUT_MODE_L4 DMA2D_FGPFCCR_CM_3 /*!< L4 */
388 #define LL_DMA2D_INPUT_MODE_A8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3) /*!< A8 */
389 #define LL_DMA2D_INPUT_MODE_A4 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< A4 */
390 #define LL_DMA2D_INPUT_MODE_YCBCR (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< YCbCr */
391 /**
392 * @}
393 */
394
395 /** @defgroup DMA2D_LL_EC_ALPHA_MODE Alpha Mode
396 * @{
397 */
398 #define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U /*!< No modification of the alpha channel value */
399 #define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by programmed alpha value */
400 #define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by programmed alpha value
401 with original alpha channel value */
402 /**
403 * @}
404 */
405
406 /** @defgroup DMA2D_LL_EC_OUTPUT_SWAP_MODE Swap Mode
407 * @{
408 */
409 #define LL_DMA2D_SWAP_MODE_REGULAR 0x00000000U /*!< Regular order */
410 #define LL_DMA2D_SWAP_MODE_TWO_BY_TWO DMA2D_OPFCCR_SB /*!< Bytes swapped two by two */
411 /**
412 * @}
413 */
414
415 /** @defgroup DMA2D_LL_EC_RED_BLUE_SWAP Red Blue Swap
416 * @{
417 */
418 #define LL_DMA2D_RB_MODE_REGULAR 0x00000000U /*!< RGB or ARGB */
419 #define LL_DMA2D_RB_MODE_SWAP DMA2D_FGPFCCR_RBS /*!< BGR or ABGR */
420 /**
421 * @}
422 */
423
424 /** @defgroup DMA2D_LL_EC_ALPHA_INVERSION Alpha Inversion
425 * @{
426 */
427 #define LL_DMA2D_ALPHA_REGULAR 0x00000000U /*!< Regular alpha */
428 #define LL_DMA2D_ALPHA_INVERTED DMA2D_FGPFCCR_AI /*!< Inverted alpha */
429 /**
430 * @}
431 */
432
433
434 /** @defgroup DMA2D_LL_EC_LINE_OFFSET_MODE Line Offset Mode
435 * @{
436 */
437 #define LL_DMA2D_LINE_OFFSET_PIXELS 0x00000000U /*!< Line offsets are expressed in pixels */
438 #define LL_DMA2D_LINE_OFFSET_BYTES DMA2D_CR_LOM /*!< Line offsets are expressed in bytes */
439 /**
440 * @}
441 */
442
443 /** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode
444 * @{
445 */
446 #define LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
447 #define LL_DMA2D_CLUT_COLOR_MODE_RGB888 DMA2D_FGPFCCR_CCM /*!< RGB888 */
448 /**
449 * @}
450 */
451
452 /** @defgroup DMA2D_LL_CHROMA_SUB_SAMPLING Chroma Sub Sampling
453 * @{
454 */
455 #define LL_DMA2D_CSS_444 0x00000000U /*!< No chroma sub-sampling 4:4:4 */
456 #define LL_DMA2D_CSS_422 DMA2D_FGPFCCR_CSS_0 /*!< chroma sub-sampling 4:2:2 */
457 #define LL_DMA2D_CSS_420 DMA2D_FGPFCCR_CSS_1 /*!< chroma sub-sampling 4:2:0 */
458 /**
459 * @}
460 */
461
462 /**
463 * @}
464 */
465
466 /* Exported macro ------------------------------------------------------------*/
467 /** @defgroup DMA2D_LL_Exported_Macros DMA2D Exported Macros
468 * @{
469 */
470
471 /** @defgroup DMA2D_LL_EM_WRITE_READ Common Write and read registers Macros
472 * @{
473 */
474
475 /**
476 * @brief Write a value in DMA2D register.
477 * @param __INSTANCE__ DMA2D Instance
478 * @param __REG__ Register to be written
479 * @param __VALUE__ Value to be written in the register
480 * @retval None
481 */
482 #define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
483
484 /**
485 * @brief Read a value in DMA2D register.
486 * @param __INSTANCE__ DMA2D Instance
487 * @param __REG__ Register to be read
488 * @retval Register value
489 */
490 #define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
491 /**
492 * @}
493 */
494
495 /**
496 * @}
497 */
498
499 /* Exported functions --------------------------------------------------------*/
500 /** @defgroup DMA2D_LL_Exported_Functions DMA2D Exported Functions
501 * @{
502 */
503
504 /** @defgroup DMA2D_LL_EF_Configuration Configuration Functions
505 * @{
506 */
507
508 /**
509 * @brief Start a DMA2D transfer.
510 * @rmtoll CR START LL_DMA2D_Start
511 * @param DMA2Dx DMA2D Instance
512 * @retval None
513 */
514 __STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx)
515 {
516 SET_BIT(DMA2Dx->CR, DMA2D_CR_START);
517 }
518
519 /**
520 * @brief Indicate if a DMA2D transfer is ongoing.
521 * @rmtoll CR START LL_DMA2D_IsTransferOngoing
522 * @param DMA2Dx DMA2D Instance
523 * @retval State of bit (1 or 0).
524 */
525 __STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx)
526 {
527 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL);
528 }
529
530 /**
531 * @brief Suspend DMA2D transfer.
532 * @note This API can be used to suspend automatic foreground or background CLUT loading.
533 * @rmtoll CR SUSP LL_DMA2D_Suspend
534 * @param DMA2Dx DMA2D Instance
535 * @retval None
536 */
537 __STATIC_INLINE void LL_DMA2D_Suspend(DMA2D_TypeDef *DMA2Dx)
538 {
539 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);
540 }
541
542 /**
543 * @brief Resume DMA2D transfer.
544 * @note This API can be used to resume automatic foreground or background CLUT loading.
545 * @rmtoll CR SUSP LL_DMA2D_Resume
546 * @param DMA2Dx DMA2D Instance
547 * @retval None
548 */
549 __STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx)
550 {
551 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START);
552 }
553
554 /**
555 * @brief Indicate if DMA2D transfer is suspended.
556 * @note This API can be used to indicate whether or not automatic foreground or
557 * background CLUT loading is suspended.
558 * @rmtoll CR SUSP LL_DMA2D_IsSuspended
559 * @param DMA2Dx DMA2D Instance
560 * @retval State of bit (1 or 0).
561 */
562 __STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx)
563 {
564 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL);
565 }
566
567 /**
568 * @brief Abort DMA2D transfer.
569 * @note This API can be used to abort automatic foreground or background CLUT loading.
570 * @rmtoll CR ABORT LL_DMA2D_Abort
571 * @param DMA2Dx DMA2D Instance
572 * @retval None
573 */
574 __STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx)
575 {
576 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);
577 }
578
579 /**
580 * @brief Indicate if DMA2D transfer is aborted.
581 * @note This API can be used to indicate whether or not automatic foreground or
582 * background CLUT loading is aborted.
583 * @rmtoll CR ABORT LL_DMA2D_IsAborted
584 * @param DMA2Dx DMA2D Instance
585 * @retval State of bit (1 or 0).
586 */
587 __STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx)
588 {
589 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL);
590 }
591
592 /**
593 * @brief Set DMA2D mode.
594 * @rmtoll CR MODE LL_DMA2D_SetMode
595 * @param DMA2Dx DMA2D Instance
596 * @param Mode This parameter can be one of the following values:
597 * @arg @ref LL_DMA2D_MODE_M2M
598 * @arg @ref LL_DMA2D_MODE_M2M_PFC
599 * @arg @ref LL_DMA2D_MODE_M2M_BLEND
600 * @arg @ref LL_DMA2D_MODE_R2M
601 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG
602 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG
603 * @retval None
604 */
605 __STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode)
606 {
607 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_MODE, Mode);
608 }
609
610 /**
611 * @brief Return DMA2D mode
612 * @rmtoll CR MODE LL_DMA2D_GetMode
613 * @param DMA2Dx DMA2D Instance
614 * @retval Returned value can be one of the following values:
615 * @arg @ref LL_DMA2D_MODE_M2M
616 * @arg @ref LL_DMA2D_MODE_M2M_PFC
617 * @arg @ref LL_DMA2D_MODE_M2M_BLEND
618 * @arg @ref LL_DMA2D_MODE_R2M
619 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG
620 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG
621 */
622 __STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx)
623 {
624 return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE));
625 }
626
627 /**
628 * @brief Set DMA2D output color mode.
629 * @rmtoll OPFCCR CM LL_DMA2D_SetOutputColorMode
630 * @param DMA2Dx DMA2D Instance
631 * @param ColorMode This parameter can be one of the following values:
632 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
633 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
634 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
635 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
636 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
637 * @retval None
638 */
639 __STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
640 {
641 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, ColorMode);
642 }
643
644 /**
645 * @brief Return DMA2D output color mode.
646 * @rmtoll OPFCCR CM LL_DMA2D_GetOutputColorMode
647 * @param DMA2Dx DMA2D Instance
648 * @retval Returned value can be one of the following values:
649 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
650 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
651 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
652 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
653 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
654 */
655 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx)
656 {
657 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM));
658 }
659
660 /**
661 * @brief Set DMA2D output Red Blue swap mode.
662 * @rmtoll OPFCCR RBS LL_DMA2D_SetOutputRBSwapMode
663 * @param DMA2Dx DMA2D Instance
664 * @param RBSwapMode This parameter can be one of the following values:
665 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
666 * @arg @ref LL_DMA2D_RB_MODE_SWAP
667 * @retval None
668 */
669 __STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
670 {
671 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS, RBSwapMode);
672 }
673
674 /**
675 * @brief Return DMA2D output Red Blue swap mode.
676 * @rmtoll OPFCCR RBS LL_DMA2D_GetOutputRBSwapMode
677 * @param DMA2Dx DMA2D Instance
678 * @retval Returned value can be one of the following values:
679 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
680 * @arg @ref LL_DMA2D_RB_MODE_SWAP
681 */
682 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx)
683 {
684 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS));
685 }
686
687 /**
688 * @brief Set DMA2D output alpha inversion mode.
689 * @rmtoll OPFCCR AI LL_DMA2D_SetOutputAlphaInvMode
690 * @param DMA2Dx DMA2D Instance
691 * @param AlphaInversionMode This parameter can be one of the following values:
692 * @arg @ref LL_DMA2D_ALPHA_REGULAR
693 * @arg @ref LL_DMA2D_ALPHA_INVERTED
694 * @retval None
695 */
696 __STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
697 {
698 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI, AlphaInversionMode);
699 }
700
701 /**
702 * @brief Return DMA2D output alpha inversion mode.
703 * @rmtoll OPFCCR AI LL_DMA2D_GetOutputAlphaInvMode
704 * @param DMA2Dx DMA2D Instance
705 * @retval Returned value can be one of the following values:
706 * @arg @ref LL_DMA2D_ALPHA_REGULAR
707 * @arg @ref LL_DMA2D_ALPHA_INVERTED
708 */
709 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
710 {
711 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI));
712 }
713
714
715 /**
716 * @brief Set DMA2D output swap mode.
717 * @rmtoll OPFCCR SB LL_DMA2D_SetOutputSwapMode
718 * @param DMA2Dx DMA2D Instance
719 * @param OutputSwapMode This parameter can be one of the following values:
720 * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR
721 * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO
722 * @retval None
723 */
724 __STATIC_INLINE void LL_DMA2D_SetOutputSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t OutputSwapMode)
725 {
726 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB, OutputSwapMode);
727 }
728
729 /**
730 * @brief Return DMA2D output swap mode.
731 * @rmtoll OPFCCR SB LL_DMA2D_GetOutputSwapMode
732 * @param DMA2Dx DMA2D Instance
733 * @retval Returned value can be one of the following values:
734 * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR
735 * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO
736 */
737 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode(DMA2D_TypeDef *DMA2Dx)
738 {
739 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB));
740 }
741
742 /**
743 * @brief Set DMA2D line offset mode.
744 * @rmtoll CR LOM LL_DMA2D_SetLineOffsetMode
745 * @param DMA2Dx DMA2D Instance
746 * @param LineOffsetMode This parameter can be one of the following values:
747 * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS
748 * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES
749 * @retval None
750 */
751 __STATIC_INLINE void LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffsetMode)
752 {
753 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_LOM, LineOffsetMode);
754 }
755
756 /**
757 * @brief Return DMA2D line offset mode.
758 * @rmtoll CR LOM LL_DMA2D_GetLineOffsetMode
759 * @param DMA2Dx DMA2D Instance
760 * @retval Returned value can be one of the following values:
761 * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS
762 * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES
763 */
764 __STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(DMA2D_TypeDef *DMA2Dx)
765 {
766 return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_LOM));
767 }
768
769 /**
770 * @brief Set DMA2D line offset, expressed on 14 bits ([13:0] bits).
771 * @rmtoll OOR LO LL_DMA2D_SetLineOffset
772 * @param DMA2Dx DMA2D Instance
773 * @param LineOffset Value between Min_Data=0 and Max_Data=0xFFFF
774 * @retval None
775 */
776 __STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
777 {
778 MODIFY_REG(DMA2Dx->OOR, DMA2D_OOR_LO, LineOffset);
779 }
780
781 /**
782 * @brief Return DMA2D line offset, expressed on 14 bits ([13:0] bits).
783 * @rmtoll OOR LO LL_DMA2D_GetLineOffset
784 * @param DMA2Dx DMA2D Instance
785 * @retval Line offset value between Min_Data=0 and Max_Data=0xFFFF
786 */
787 __STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
788 {
789 return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO));
790 }
791
792 /**
793 * @brief Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits).
794 * @rmtoll NLR PL LL_DMA2D_SetNbrOfPixelsPerLines
795 * @param DMA2Dx DMA2D Instance
796 * @param NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF
797 * @retval None
798 */
799 __STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines)
800 {
801 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_PL, (NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos));
802 }
803
804 /**
805 * @brief Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits)
806 * @rmtoll NLR PL LL_DMA2D_GetNbrOfPixelsPerLines
807 * @param DMA2Dx DMA2D Instance
808 * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF
809 */
810 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx)
811 {
812 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos);
813 }
814
815 /**
816 * @brief Set DMA2D number of lines, expressed on 16 bits ([15:0] bits).
817 * @rmtoll NLR NL LL_DMA2D_SetNbrOfLines
818 * @param DMA2Dx DMA2D Instance
819 * @param NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF
820 * @retval None
821 */
822 __STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines)
823 {
824 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_NL, NbrOfLines);
825 }
826
827 /**
828 * @brief Return DMA2D number of lines, expressed on 16 bits ([15:0] bits).
829 * @rmtoll NLR NL LL_DMA2D_GetNbrOfLines
830 * @param DMA2Dx DMA2D Instance
831 * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF
832 */
833 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx)
834 {
835 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL));
836 }
837
838 /**
839 * @brief Set DMA2D output memory address, expressed on 32 bits ([31:0] bits).
840 * @rmtoll OMAR MA LL_DMA2D_SetOutputMemAddr
841 * @param DMA2Dx DMA2D Instance
842 * @param OutputMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
843 * @retval None
844 */
845 __STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress)
846 {
847 LL_DMA2D_WriteReg(DMA2Dx, OMAR, OutputMemoryAddress);
848 }
849
850 /**
851 * @brief Get DMA2D output memory address, expressed on 32 bits ([31:0] bits).
852 * @rmtoll OMAR MA LL_DMA2D_GetOutputMemAddr
853 * @param DMA2Dx DMA2D Instance
854 * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
855 */
856 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx)
857 {
858 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR));
859 }
860
861 /**
862 * @brief Set DMA2D output color, expressed on 32 bits ([31:0] bits).
863 * @note Output color format depends on output color mode, ARGB8888, RGB888,
864 * RGB565, ARGB1555 or ARGB4444.
865 * @note LL_DMA2D_ConfigOutputColor() API may be used instead if colors values formatting
866 * with respect to color mode is not done by the user code.
867 * @rmtoll OCOLR BLUE LL_DMA2D_SetOutputColor\n
868 * OCOLR GREEN LL_DMA2D_SetOutputColor\n
869 * OCOLR RED LL_DMA2D_SetOutputColor\n
870 * OCOLR ALPHA LL_DMA2D_SetOutputColor
871 * @param DMA2Dx DMA2D Instance
872 * @param OutputColor Value between Min_Data=0 and Max_Data=0xFFFFFFFF
873 * @retval None
874 */
875 __STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor)
876 {
877 MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1), \
878 OutputColor);
879 }
880
881 /**
882 * @brief Get DMA2D output color, expressed on 32 bits ([31:0] bits).
883 * @note Alpha channel and red, green, blue color values must be retrieved from the returned
884 * value based on the output color mode (ARGB8888, RGB888, RGB565, ARGB1555 or ARGB4444)
885 * as set by @ref LL_DMA2D_SetOutputColorMode.
886 * @rmtoll OCOLR BLUE LL_DMA2D_GetOutputColor\n
887 * OCOLR GREEN LL_DMA2D_GetOutputColor\n
888 * OCOLR RED LL_DMA2D_GetOutputColor\n
889 * OCOLR ALPHA LL_DMA2D_GetOutputColor
890 * @param DMA2Dx DMA2D Instance
891 * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF
892 */
893 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx)
894 {
895 return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \
896 (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1)));
897 }
898
899 /**
900 * @brief Set DMA2D line watermark, expressed on 16 bits ([15:0] bits).
901 * @rmtoll LWR LW LL_DMA2D_SetLineWatermark
902 * @param DMA2Dx DMA2D Instance
903 * @param LineWatermark Value between Min_Data=0 and Max_Data=0xFFFF
904 * @retval None
905 */
906 __STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark)
907 {
908 MODIFY_REG(DMA2Dx->LWR, DMA2D_LWR_LW, LineWatermark);
909 }
910
911 /**
912 * @brief Return DMA2D line watermark, expressed on 16 bits ([15:0] bits).
913 * @rmtoll LWR LW LL_DMA2D_GetLineWatermark
914 * @param DMA2Dx DMA2D Instance
915 * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF
916 */
917 __STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx)
918 {
919 return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW));
920 }
921
922 /**
923 * @brief Set DMA2D dead time, expressed on 8 bits ([7:0] bits).
924 * @rmtoll AMTCR DT LL_DMA2D_SetDeadTime
925 * @param DMA2Dx DMA2D Instance
926 * @param DeadTime Value between Min_Data=0 and Max_Data=0xFF
927 * @retval None
928 */
929 __STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime)
930 {
931 MODIFY_REG(DMA2Dx->AMTCR, DMA2D_AMTCR_DT, (DeadTime << DMA2D_AMTCR_DT_Pos));
932 }
933
934 /**
935 * @brief Return DMA2D dead time, expressed on 8 bits ([7:0] bits).
936 * @rmtoll AMTCR DT LL_DMA2D_GetDeadTime
937 * @param DMA2Dx DMA2D Instance
938 * @retval Dead time value between Min_Data=0 and Max_Data=0xFF
939 */
940 __STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx)
941 {
942 return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos);
943 }
944
945 /**
946 * @brief Enable DMA2D dead time functionality.
947 * @rmtoll AMTCR EN LL_DMA2D_EnableDeadTime
948 * @param DMA2Dx DMA2D Instance
949 * @retval None
950 */
951 __STATIC_INLINE void LL_DMA2D_EnableDeadTime(DMA2D_TypeDef *DMA2Dx)
952 {
953 SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
954 }
955
956 /**
957 * @brief Disable DMA2D dead time functionality.
958 * @rmtoll AMTCR EN LL_DMA2D_DisableDeadTime
959 * @param DMA2Dx DMA2D Instance
960 * @retval None
961 */
962 __STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx)
963 {
964 CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
965 }
966
967 /**
968 * @brief Indicate if DMA2D dead time functionality is enabled.
969 * @rmtoll AMTCR EN LL_DMA2D_IsEnabledDeadTime
970 * @param DMA2Dx DMA2D Instance
971 * @retval State of bit (1 or 0).
972 */
973 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx)
974 {
975 return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL);
976 }
977
978 /** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions
979 * @{
980 */
981
982 /**
983 * @brief Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
984 * @rmtoll FGMAR MA LL_DMA2D_FGND_SetMemAddr
985 * @param DMA2Dx DMA2D Instance
986 * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
987 * @retval None
988 */
989 __STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
990 {
991 LL_DMA2D_WriteReg(DMA2Dx, FGMAR, MemoryAddress);
992 }
993
994 /**
995 * @brief Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
996 * @rmtoll FGMAR MA LL_DMA2D_FGND_GetMemAddr
997 * @param DMA2Dx DMA2D Instance
998 * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
999 */
1000 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
1001 {
1002 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR));
1003 }
1004
1005 /**
1006 * @brief Enable DMA2D foreground CLUT loading.
1007 * @rmtoll FGPFCCR START LL_DMA2D_FGND_EnableCLUTLoad
1008 * @param DMA2Dx DMA2D Instance
1009 * @retval None
1010 */
1011 __STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1012 {
1013 SET_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START);
1014 }
1015
1016 /**
1017 * @brief Indicate if DMA2D foreground CLUT loading is enabled.
1018 * @rmtoll FGPFCCR START LL_DMA2D_FGND_IsEnabledCLUTLoad
1019 * @param DMA2Dx DMA2D Instance
1020 * @retval State of bit (1 or 0).
1021 */
1022 __STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1023 {
1024 return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL);
1025 }
1026
1027 /**
1028 * @brief Set DMA2D foreground color mode.
1029 * @rmtoll FGPFCCR CM LL_DMA2D_FGND_SetColorMode
1030 * @param DMA2Dx DMA2D Instance
1031 * @param ColorMode This parameter can be one of the following values:
1032 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1033 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1034 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1035 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1036 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1037 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1038 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1039 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1040 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1041 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1042 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1043 * @retval None
1044 */
1045 __STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
1046 {
1047 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM, ColorMode);
1048 }
1049
1050 /**
1051 * @brief Return DMA2D foreground color mode.
1052 * @rmtoll FGPFCCR CM LL_DMA2D_FGND_GetColorMode
1053 * @param DMA2Dx DMA2D Instance
1054 * @retval Returned value can be one of the following values:
1055 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1056 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1057 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1058 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1059 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1060 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1061 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1062 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1063 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1064 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1065 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1066 */
1067 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
1068 {
1069 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM));
1070 }
1071
1072 /**
1073 * @brief Set DMA2D foreground alpha mode.
1074 * @rmtoll FGPFCCR AM LL_DMA2D_FGND_SetAlphaMode
1075 * @param DMA2Dx DMA2D Instance
1076 * @param AphaMode This parameter can be one of the following values:
1077 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1078 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1079 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1080 * @retval None
1081 */
1082 __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
1083 {
1084 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM, AphaMode);
1085 }
1086
1087 /**
1088 * @brief Return DMA2D foreground alpha mode.
1089 * @rmtoll FGPFCCR AM LL_DMA2D_FGND_GetAlphaMode
1090 * @param DMA2Dx DMA2D Instance
1091 * @retval Returned value can be one of the following values:
1092 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1093 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1094 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1095 */
1096 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
1097 {
1098 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM));
1099 }
1100
1101 /**
1102 * @brief Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
1103 * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_SetAlpha
1104 * @param DMA2Dx DMA2D Instance
1105 * @param Alpha Value between Min_Data=0 and Max_Data=0xFF
1106 * @retval None
1107 */
1108 __STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
1109 {
1110 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA, (Alpha << DMA2D_FGPFCCR_ALPHA_Pos));
1111 }
1112
1113 /**
1114 * @brief Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
1115 * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_GetAlpha
1116 * @param DMA2Dx DMA2D Instance
1117 * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
1118 */
1119 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
1120 {
1121 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos);
1122 }
1123
1124 /**
1125 * @brief Set DMA2D foreground Red Blue swap mode.
1126 * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_SetRBSwapMode
1127 * @param DMA2Dx DMA2D Instance
1128 * @param RBSwapMode This parameter can be one of the following values:
1129 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1130 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1131 * @retval None
1132 */
1133 __STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
1134 {
1135 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS, RBSwapMode);
1136 }
1137
1138 /**
1139 * @brief Return DMA2D foreground Red Blue swap mode.
1140 * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_GetRBSwapMode
1141 * @param DMA2Dx DMA2D Instance
1142 * @retval Returned value can be one of the following values:
1143 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1144 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1145 */
1146 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)
1147 {
1148 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS));
1149 }
1150
1151 /**
1152 * @brief Set DMA2D foreground alpha inversion mode.
1153 * @rmtoll FGPFCCR AI LL_DMA2D_FGND_SetAlphaInvMode
1154 * @param DMA2Dx DMA2D Instance
1155 * @param AlphaInversionMode This parameter can be one of the following values:
1156 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1157 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1158 * @retval None
1159 */
1160 __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
1161 {
1162 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI, AlphaInversionMode);
1163 }
1164
1165 /**
1166 * @brief Return DMA2D foreground alpha inversion mode.
1167 * @rmtoll FGPFCCR AI LL_DMA2D_FGND_GetAlphaInvMode
1168 * @param DMA2Dx DMA2D Instance
1169 * @retval Returned value can be one of the following values:
1170 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1171 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1172 */
1173 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
1174 {
1175 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI));
1176 }
1177
1178 /**
1179 * @brief Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
1180 * @rmtoll FGOR LO LL_DMA2D_FGND_SetLineOffset
1181 * @param DMA2Dx DMA2D Instance
1182 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
1183 * @retval None
1184 */
1185 __STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
1186 {
1187 MODIFY_REG(DMA2Dx->FGOR, DMA2D_FGOR_LO, LineOffset);
1188 }
1189
1190 /**
1191 * @brief Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
1192 * @rmtoll FGOR LO LL_DMA2D_FGND_GetLineOffset
1193 * @param DMA2Dx DMA2D Instance
1194 * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF
1195 */
1196 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
1197 {
1198 return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO));
1199 }
1200
1201 /**
1202 * @brief Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits).
1203 * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetColor
1204 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetColor
1205 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetColor
1206 * @param DMA2Dx DMA2D Instance
1207 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1208 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1209 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1210 * @retval None
1211 */
1212 __STATIC_INLINE void LL_DMA2D_FGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
1213 {
1214 MODIFY_REG(DMA2Dx->FGCOLR, (DMA2D_FGCOLR_RED | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_BLUE), \
1215 ((Red << DMA2D_FGCOLR_RED_Pos) | (Green << DMA2D_FGCOLR_GREEN_Pos) | Blue));
1216 }
1217
1218 /**
1219 * @brief Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
1220 * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetRedColor
1221 * @param DMA2Dx DMA2D Instance
1222 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1223 * @retval None
1224 */
1225 __STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
1226 {
1227 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED, (Red << DMA2D_FGCOLR_RED_Pos));
1228 }
1229
1230 /**
1231 * @brief Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
1232 * @rmtoll FGCOLR RED LL_DMA2D_FGND_GetRedColor
1233 * @param DMA2Dx DMA2D Instance
1234 * @retval Red color value between Min_Data=0 and Max_Data=0xFF
1235 */
1236 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
1237 {
1238 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos);
1239 }
1240
1241 /**
1242 * @brief Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
1243 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetGreenColor
1244 * @param DMA2Dx DMA2D Instance
1245 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1246 * @retval None
1247 */
1248 __STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
1249 {
1250 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN, (Green << DMA2D_FGCOLR_GREEN_Pos));
1251 }
1252
1253 /**
1254 * @brief Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
1255 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_GetGreenColor
1256 * @param DMA2Dx DMA2D Instance
1257 * @retval Green color value between Min_Data=0 and Max_Data=0xFF
1258 */
1259 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
1260 {
1261 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos);
1262 }
1263
1264 /**
1265 * @brief Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
1266 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetBlueColor
1267 * @param DMA2Dx DMA2D Instance
1268 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1269 * @retval None
1270 */
1271 __STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
1272 {
1273 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE, Blue);
1274 }
1275
1276 /**
1277 * @brief Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
1278 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_GetBlueColor
1279 * @param DMA2Dx DMA2D Instance
1280 * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
1281 */
1282 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
1283 {
1284 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE));
1285 }
1286
1287 /**
1288 * @brief Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
1289 * @rmtoll FGCMAR MA LL_DMA2D_FGND_SetCLUTMemAddr
1290 * @param DMA2Dx DMA2D Instance
1291 * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1292 * @retval None
1293 */
1294 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
1295 {
1296 LL_DMA2D_WriteReg(DMA2Dx, FGCMAR, CLUTMemoryAddress);
1297 }
1298
1299 /**
1300 * @brief Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
1301 * @rmtoll FGCMAR MA LL_DMA2D_FGND_GetCLUTMemAddr
1302 * @param DMA2Dx DMA2D Instance
1303 * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1304 */
1305 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
1306 {
1307 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR));
1308 }
1309
1310 /**
1311 * @brief Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
1312 * @rmtoll FGPFCCR CS LL_DMA2D_FGND_SetCLUTSize
1313 * @param DMA2Dx DMA2D Instance
1314 * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
1315 * @retval None
1316 */
1317 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
1318 {
1319 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS, (CLUTSize << DMA2D_FGPFCCR_CS_Pos));
1320 }
1321
1322 /**
1323 * @brief Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
1324 * @rmtoll FGPFCCR CS LL_DMA2D_FGND_GetCLUTSize
1325 * @param DMA2Dx DMA2D Instance
1326 * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF
1327 */
1328 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
1329 {
1330 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos);
1331 }
1332
1333 /**
1334 * @brief Set DMA2D foreground CLUT color mode.
1335 * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_SetCLUTColorMode
1336 * @param DMA2Dx DMA2D Instance
1337 * @param CLUTColorMode This parameter can be one of the following values:
1338 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1339 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1340 * @retval None
1341 */
1342 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
1343 {
1344 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM, CLUTColorMode);
1345 }
1346
1347 /**
1348 * @brief Return DMA2D foreground CLUT color mode.
1349 * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_GetCLUTColorMode
1350 * @param DMA2Dx DMA2D Instance
1351 * @retval Returned value can be one of the following values:
1352 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1353 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1354 */
1355 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
1356 {
1357 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM));
1358 }
1359
1360 /**
1361 * @brief Set DMA2D foreground Chroma Sub Sampling (for YCbCr input color mode).
1362 * @rmtoll FGPFCCR CSS LL_DMA2D_FGND_SetChrSubSampling
1363 * @param DMA2Dx DMA2D Instance
1364 * @param ChromaSubSampling This parameter can be one of the following values:
1365 * @arg @ref LL_DMA2D_CSS_444
1366 * @arg @ref LL_DMA2D_CSS_422
1367 * @arg @ref LL_DMA2D_CSS_420
1368 * @retval None
1369 */
1370 __STATIC_INLINE void LL_DMA2D_FGND_SetChrSubSampling(DMA2D_TypeDef *DMA2Dx, uint32_t ChromaSubSampling)
1371 {
1372 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CSS, ChromaSubSampling);
1373 }
1374
1375 /**
1376 * @brief Return DMA2D foreground Chroma Sub Sampling (for YCbCr input color mode).
1377 * @rmtoll FGPFCCR CSS LL_DMA2D_FGND_GetChrSubSampling
1378 * @param DMA2Dx DMA2D Instance
1379 * @retval Returned value can be one of the following values:
1380 * @arg @ref LL_DMA2D_CSS_444
1381 * @arg @ref LL_DMA2D_CSS_422
1382 * @arg @ref LL_DMA2D_CSS_420
1383 */
1384 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetChrSubSampling(DMA2D_TypeDef *DMA2Dx)
1385 {
1386 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CSS));
1387 }
1388 /**
1389 * @}
1390 */
1391
1392 /** @defgroup DMA2D_LL_EF_BGND_Configuration Background Configuration Functions
1393 * @{
1394 */
1395
1396 /**
1397 * @brief Set DMA2D background memory address, expressed on 32 bits ([31:0] bits).
1398 * @rmtoll BGMAR MA LL_DMA2D_BGND_SetMemAddr
1399 * @param DMA2Dx DMA2D Instance
1400 * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1401 * @retval None
1402 */
1403 __STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
1404 {
1405 LL_DMA2D_WriteReg(DMA2Dx, BGMAR, MemoryAddress);
1406 }
1407
1408 /**
1409 * @brief Get DMA2D background memory address, expressed on 32 bits ([31:0] bits).
1410 * @rmtoll BGMAR MA LL_DMA2D_BGND_GetMemAddr
1411 * @param DMA2Dx DMA2D Instance
1412 * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1413 */
1414 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
1415 {
1416 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR));
1417 }
1418
1419 /**
1420 * @brief Enable DMA2D background CLUT loading.
1421 * @rmtoll BGPFCCR START LL_DMA2D_BGND_EnableCLUTLoad
1422 * @param DMA2Dx DMA2D Instance
1423 * @retval None
1424 */
1425 __STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1426 {
1427 SET_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START);
1428 }
1429
1430 /**
1431 * @brief Indicate if DMA2D background CLUT loading is enabled.
1432 * @rmtoll BGPFCCR START LL_DMA2D_BGND_IsEnabledCLUTLoad
1433 * @param DMA2Dx DMA2D Instance
1434 * @retval State of bit (1 or 0).
1435 */
1436 __STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1437 {
1438 return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL);
1439 }
1440
1441 /**
1442 * @brief Set DMA2D background color mode.
1443 * @rmtoll BGPFCCR CM LL_DMA2D_BGND_SetColorMode
1444 * @param DMA2Dx DMA2D Instance
1445 * @param ColorMode This parameter can be one of the following values:
1446 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1447 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1448 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1449 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1450 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1451 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1452 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1453 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1454 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1455 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1456 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1457 * @retval None
1458 */
1459 __STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
1460 {
1461 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM, ColorMode);
1462 }
1463
1464 /**
1465 * @brief Return DMA2D background color mode.
1466 * @rmtoll BGPFCCR CM LL_DMA2D_BGND_GetColorMode
1467 * @param DMA2Dx DMA2D Instance
1468 * @retval Returned value can be one of the following values:
1469 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1470 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1471 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1472 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1473 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1474 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1475 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1476 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1477 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1478 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1479 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1480 */
1481 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
1482 {
1483 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM));
1484 }
1485
1486 /**
1487 * @brief Set DMA2D background alpha mode.
1488 * @rmtoll BGPFCCR AM LL_DMA2D_BGND_SetAlphaMode
1489 * @param DMA2Dx DMA2D Instance
1490 * @param AphaMode This parameter can be one of the following values:
1491 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1492 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1493 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1494 * @retval None
1495 */
1496 __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
1497 {
1498 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM, AphaMode);
1499 }
1500
1501 /**
1502 * @brief Return DMA2D background alpha mode.
1503 * @rmtoll BGPFCCR AM LL_DMA2D_BGND_GetAlphaMode
1504 * @param DMA2Dx DMA2D Instance
1505 * @retval Returned value can be one of the following values:
1506 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1507 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1508 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1509 */
1510 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
1511 {
1512 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM));
1513 }
1514
1515 /**
1516 * @brief Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
1517 * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_SetAlpha
1518 * @param DMA2Dx DMA2D Instance
1519 * @param Alpha Value between Min_Data=0 and Max_Data=0xFF
1520 * @retval None
1521 */
1522 __STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
1523 {
1524 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA, (Alpha << DMA2D_BGPFCCR_ALPHA_Pos));
1525 }
1526
1527 /**
1528 * @brief Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
1529 * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_GetAlpha
1530 * @param DMA2Dx DMA2D Instance
1531 * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
1532 */
1533 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
1534 {
1535 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos);
1536 }
1537
1538 /**
1539 * @brief Set DMA2D background Red Blue swap mode.
1540 * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_SetRBSwapMode
1541 * @param DMA2Dx DMA2D Instance
1542 * @param RBSwapMode This parameter can be one of the following values:
1543 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1544 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1545 * @retval None
1546 */
1547 __STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
1548 {
1549 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS, RBSwapMode);
1550 }
1551
1552 /**
1553 * @brief Return DMA2D background Red Blue swap mode.
1554 * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_GetRBSwapMode
1555 * @param DMA2Dx DMA2D Instance
1556 * @retval Returned value can be one of the following values:
1557 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1558 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1559 */
1560 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)
1561 {
1562 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS));
1563 }
1564
1565 /**
1566 * @brief Set DMA2D background alpha inversion mode.
1567 * @rmtoll BGPFCCR AI LL_DMA2D_BGND_SetAlphaInvMode
1568 * @param DMA2Dx DMA2D Instance
1569 * @param AlphaInversionMode This parameter can be one of the following values:
1570 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1571 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1572 * @retval None
1573 */
1574 __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
1575 {
1576 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI, AlphaInversionMode);
1577 }
1578
1579 /**
1580 * @brief Return DMA2D background alpha inversion mode.
1581 * @rmtoll BGPFCCR AI LL_DMA2D_BGND_GetAlphaInvMode
1582 * @param DMA2Dx DMA2D Instance
1583 * @retval Returned value can be one of the following values:
1584 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1585 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1586 */
1587 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
1588 {
1589 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI));
1590 }
1591
1592 /**
1593 * @brief Set DMA2D background line offset, expressed on 14 bits ([13:0] bits).
1594 * @rmtoll BGOR LO LL_DMA2D_BGND_SetLineOffset
1595 * @param DMA2Dx DMA2D Instance
1596 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
1597 * @retval None
1598 */
1599 __STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
1600 {
1601 MODIFY_REG(DMA2Dx->BGOR, DMA2D_BGOR_LO, LineOffset);
1602 }
1603
1604 /**
1605 * @brief Return DMA2D background line offset, expressed on 14 bits ([13:0] bits).
1606 * @rmtoll BGOR LO LL_DMA2D_BGND_GetLineOffset
1607 * @param DMA2Dx DMA2D Instance
1608 * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF
1609 */
1610 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
1611 {
1612 return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO));
1613 }
1614
1615 /**
1616 * @brief Set DMA2D background color values, expressed on 24 bits ([23:0] bits).
1617 * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetColor
1618 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetColor
1619 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetColor
1620 * @param DMA2Dx DMA2D Instance
1621 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1622 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1623 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1624 * @retval None
1625 */
1626 __STATIC_INLINE void LL_DMA2D_BGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
1627 {
1628 MODIFY_REG(DMA2Dx->BGCOLR, (DMA2D_BGCOLR_RED | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_BLUE), \
1629 ((Red << DMA2D_BGCOLR_RED_Pos) | (Green << DMA2D_BGCOLR_GREEN_Pos) | Blue));
1630 }
1631
1632 /**
1633 * @brief Set DMA2D background red color value, expressed on 8 bits ([7:0] bits).
1634 * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetRedColor
1635 * @param DMA2Dx DMA2D Instance
1636 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1637 * @retval None
1638 */
1639 __STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
1640 {
1641 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED, (Red << DMA2D_BGCOLR_RED_Pos));
1642 }
1643
1644 /**
1645 * @brief Return DMA2D background red color value, expressed on 8 bits ([7:0] bits).
1646 * @rmtoll BGCOLR RED LL_DMA2D_BGND_GetRedColor
1647 * @param DMA2Dx DMA2D Instance
1648 * @retval Red color value between Min_Data=0 and Max_Data=0xFF
1649 */
1650 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
1651 {
1652 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos);
1653 }
1654
1655 /**
1656 * @brief Set DMA2D background green color value, expressed on 8 bits ([7:0] bits).
1657 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetGreenColor
1658 * @param DMA2Dx DMA2D Instance
1659 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1660 * @retval None
1661 */
1662 __STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
1663 {
1664 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN, (Green << DMA2D_BGCOLR_GREEN_Pos));
1665 }
1666
1667 /**
1668 * @brief Return DMA2D background green color value, expressed on 8 bits ([7:0] bits).
1669 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_GetGreenColor
1670 * @param DMA2Dx DMA2D Instance
1671 * @retval Green color value between Min_Data=0 and Max_Data=0xFF
1672 */
1673 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
1674 {
1675 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos);
1676 }
1677
1678 /**
1679 * @brief Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
1680 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetBlueColor
1681 * @param DMA2Dx DMA2D Instance
1682 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1683 * @retval None
1684 */
1685 __STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
1686 {
1687 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE, Blue);
1688 }
1689
1690 /**
1691 * @brief Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
1692 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_GetBlueColor
1693 * @param DMA2Dx DMA2D Instance
1694 * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
1695 */
1696 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
1697 {
1698 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE));
1699 }
1700
1701 /**
1702 * @brief Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
1703 * @rmtoll BGCMAR MA LL_DMA2D_BGND_SetCLUTMemAddr
1704 * @param DMA2Dx DMA2D Instance
1705 * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1706 * @retval None
1707 */
1708 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
1709 {
1710 LL_DMA2D_WriteReg(DMA2Dx, BGCMAR, CLUTMemoryAddress);
1711 }
1712
1713 /**
1714 * @brief Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
1715 * @rmtoll BGCMAR MA LL_DMA2D_BGND_GetCLUTMemAddr
1716 * @param DMA2Dx DMA2D Instance
1717 * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1718 */
1719 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
1720 {
1721 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR));
1722 }
1723
1724 /**
1725 * @brief Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
1726 * @rmtoll BGPFCCR CS LL_DMA2D_BGND_SetCLUTSize
1727 * @param DMA2Dx DMA2D Instance
1728 * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
1729 * @retval None
1730 */
1731 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
1732 {
1733 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS, (CLUTSize << DMA2D_BGPFCCR_CS_Pos));
1734 }
1735
1736 /**
1737 * @brief Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
1738 * @rmtoll BGPFCCR CS LL_DMA2D_BGND_GetCLUTSize
1739 * @param DMA2Dx DMA2D Instance
1740 * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF
1741 */
1742 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
1743 {
1744 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos);
1745 }
1746
1747 /**
1748 * @brief Set DMA2D background CLUT color mode.
1749 * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_SetCLUTColorMode
1750 * @param DMA2Dx DMA2D Instance
1751 * @param CLUTColorMode This parameter can be one of the following values:
1752 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1753 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1754 * @retval None
1755 */
1756 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
1757 {
1758 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM, CLUTColorMode);
1759 }
1760
1761 /**
1762 * @brief Return DMA2D background CLUT color mode.
1763 * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_GetCLUTColorMode
1764 * @param DMA2Dx DMA2D Instance
1765 * @retval Returned value can be one of the following values:
1766 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1767 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1768 */
1769 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
1770 {
1771 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM));
1772 }
1773
1774 /**
1775 * @}
1776 */
1777
1778 /**
1779 * @}
1780 */
1781
1782
1783 /** @defgroup DMA2D_LL_EF_FLAG_MANAGEMENT Flag Management
1784 * @{
1785 */
1786
1787 /**
1788 * @brief Check if the DMA2D Configuration Error Interrupt Flag is set or not
1789 * @rmtoll ISR CEIF LL_DMA2D_IsActiveFlag_CE
1790 * @param DMA2Dx DMA2D Instance
1791 * @retval State of bit (1 or 0).
1792 */
1793 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx)
1794 {
1795 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL);
1796 }
1797
1798 /**
1799 * @brief Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not
1800 * @rmtoll ISR CTCIF LL_DMA2D_IsActiveFlag_CTC
1801 * @param DMA2Dx DMA2D Instance
1802 * @retval State of bit (1 or 0).
1803 */
1804 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx)
1805 {
1806 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL);
1807 }
1808
1809 /**
1810 * @brief Check if the DMA2D CLUT Access Error Interrupt Flag is set or not
1811 * @rmtoll ISR CAEIF LL_DMA2D_IsActiveFlag_CAE
1812 * @param DMA2Dx DMA2D Instance
1813 * @retval State of bit (1 or 0).
1814 */
1815 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx)
1816 {
1817 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL);
1818 }
1819
1820 /**
1821 * @brief Check if the DMA2D Transfer Watermark Interrupt Flag is set or not
1822 * @rmtoll ISR TWIF LL_DMA2D_IsActiveFlag_TW
1823 * @param DMA2Dx DMA2D Instance
1824 * @retval State of bit (1 or 0).
1825 */
1826 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx)
1827 {
1828 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL);
1829 }
1830
1831 /**
1832 * @brief Check if the DMA2D Transfer Complete Interrupt Flag is set or not
1833 * @rmtoll ISR TCIF LL_DMA2D_IsActiveFlag_TC
1834 * @param DMA2Dx DMA2D Instance
1835 * @retval State of bit (1 or 0).
1836 */
1837 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx)
1838 {
1839 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL);
1840 }
1841
1842 /**
1843 * @brief Check if the DMA2D Transfer Error Interrupt Flag is set or not
1844 * @rmtoll ISR TEIF LL_DMA2D_IsActiveFlag_TE
1845 * @param DMA2Dx DMA2D Instance
1846 * @retval State of bit (1 or 0).
1847 */
1848 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx)
1849 {
1850 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL);
1851 }
1852
1853 /**
1854 * @brief Clear DMA2D Configuration Error Interrupt Flag
1855 * @rmtoll IFCR CCEIF LL_DMA2D_ClearFlag_CE
1856 * @param DMA2Dx DMA2D Instance
1857 * @retval None
1858 */
1859 __STATIC_INLINE void LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef *DMA2Dx)
1860 {
1861 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCEIF);
1862 }
1863
1864 /**
1865 * @brief Clear DMA2D CLUT Transfer Complete Interrupt Flag
1866 * @rmtoll IFCR CCTCIF LL_DMA2D_ClearFlag_CTC
1867 * @param DMA2Dx DMA2D Instance
1868 * @retval None
1869 */
1870 __STATIC_INLINE void LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef *DMA2Dx)
1871 {
1872 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCTCIF);
1873 }
1874
1875 /**
1876 * @brief Clear DMA2D CLUT Access Error Interrupt Flag
1877 * @rmtoll IFCR CAECIF LL_DMA2D_ClearFlag_CAE
1878 * @param DMA2Dx DMA2D Instance
1879 * @retval None
1880 */
1881 __STATIC_INLINE void LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef *DMA2Dx)
1882 {
1883 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CAECIF);
1884 }
1885
1886 /**
1887 * @brief Clear DMA2D Transfer Watermark Interrupt Flag
1888 * @rmtoll IFCR CTWIF LL_DMA2D_ClearFlag_TW
1889 * @param DMA2Dx DMA2D Instance
1890 * @retval None
1891 */
1892 __STATIC_INLINE void LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef *DMA2Dx)
1893 {
1894 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTWIF);
1895 }
1896
1897 /**
1898 * @brief Clear DMA2D Transfer Complete Interrupt Flag
1899 * @rmtoll IFCR CTCIF LL_DMA2D_ClearFlag_TC
1900 * @param DMA2Dx DMA2D Instance
1901 * @retval None
1902 */
1903 __STATIC_INLINE void LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef *DMA2Dx)
1904 {
1905 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTCIF);
1906 }
1907
1908 /**
1909 * @brief Clear DMA2D Transfer Error Interrupt Flag
1910 * @rmtoll IFCR CTEIF LL_DMA2D_ClearFlag_TE
1911 * @param DMA2Dx DMA2D Instance
1912 * @retval None
1913 */
1914 __STATIC_INLINE void LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef *DMA2Dx)
1915 {
1916 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTEIF);
1917 }
1918
1919 /**
1920 * @}
1921 */
1922
1923 /** @defgroup DMA2D_LL_EF_IT_MANAGEMENT Interruption Management
1924 * @{
1925 */
1926
1927 /**
1928 * @brief Enable Configuration Error Interrupt
1929 * @rmtoll CR CEIE LL_DMA2D_EnableIT_CE
1930 * @param DMA2Dx DMA2D Instance
1931 * @retval None
1932 */
1933 __STATIC_INLINE void LL_DMA2D_EnableIT_CE(DMA2D_TypeDef *DMA2Dx)
1934 {
1935 SET_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
1936 }
1937
1938 /**
1939 * @brief Enable CLUT Transfer Complete Interrupt
1940 * @rmtoll CR CTCIE LL_DMA2D_EnableIT_CTC
1941 * @param DMA2Dx DMA2D Instance
1942 * @retval None
1943 */
1944 __STATIC_INLINE void LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef *DMA2Dx)
1945 {
1946 SET_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
1947 }
1948
1949 /**
1950 * @brief Enable CLUT Access Error Interrupt
1951 * @rmtoll CR CAEIE LL_DMA2D_EnableIT_CAE
1952 * @param DMA2Dx DMA2D Instance
1953 * @retval None
1954 */
1955 __STATIC_INLINE void LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef *DMA2Dx)
1956 {
1957 SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
1958 }
1959
1960 /**
1961 * @brief Enable Transfer Watermark Interrupt
1962 * @rmtoll CR TWIE LL_DMA2D_EnableIT_TW
1963 * @param DMA2Dx DMA2D Instance
1964 * @retval None
1965 */
1966 __STATIC_INLINE void LL_DMA2D_EnableIT_TW(DMA2D_TypeDef *DMA2Dx)
1967 {
1968 SET_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
1969 }
1970
1971 /**
1972 * @brief Enable Transfer Complete Interrupt
1973 * @rmtoll CR TCIE LL_DMA2D_EnableIT_TC
1974 * @param DMA2Dx DMA2D Instance
1975 * @retval None
1976 */
1977 __STATIC_INLINE void LL_DMA2D_EnableIT_TC(DMA2D_TypeDef *DMA2Dx)
1978 {
1979 SET_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
1980 }
1981
1982 /**
1983 * @brief Enable Transfer Error Interrupt
1984 * @rmtoll CR TEIE LL_DMA2D_EnableIT_TE
1985 * @param DMA2Dx DMA2D Instance
1986 * @retval None
1987 */
1988 __STATIC_INLINE void LL_DMA2D_EnableIT_TE(DMA2D_TypeDef *DMA2Dx)
1989 {
1990 SET_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
1991 }
1992
1993 /**
1994 * @brief Disable Configuration Error Interrupt
1995 * @rmtoll CR CEIE LL_DMA2D_DisableIT_CE
1996 * @param DMA2Dx DMA2D Instance
1997 * @retval None
1998 */
1999 __STATIC_INLINE void LL_DMA2D_DisableIT_CE(DMA2D_TypeDef *DMA2Dx)
2000 {
2001 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
2002 }
2003
2004 /**
2005 * @brief Disable CLUT Transfer Complete Interrupt
2006 * @rmtoll CR CTCIE LL_DMA2D_DisableIT_CTC
2007 * @param DMA2Dx DMA2D Instance
2008 * @retval None
2009 */
2010 __STATIC_INLINE void LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef *DMA2Dx)
2011 {
2012 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
2013 }
2014
2015 /**
2016 * @brief Disable CLUT Access Error Interrupt
2017 * @rmtoll CR CAEIE LL_DMA2D_DisableIT_CAE
2018 * @param DMA2Dx DMA2D Instance
2019 * @retval None
2020 */
2021 __STATIC_INLINE void LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef *DMA2Dx)
2022 {
2023 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
2024 }
2025
2026 /**
2027 * @brief Disable Transfer Watermark Interrupt
2028 * @rmtoll CR TWIE LL_DMA2D_DisableIT_TW
2029 * @param DMA2Dx DMA2D Instance
2030 * @retval None
2031 */
2032 __STATIC_INLINE void LL_DMA2D_DisableIT_TW(DMA2D_TypeDef *DMA2Dx)
2033 {
2034 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
2035 }
2036
2037 /**
2038 * @brief Disable Transfer Complete Interrupt
2039 * @rmtoll CR TCIE LL_DMA2D_DisableIT_TC
2040 * @param DMA2Dx DMA2D Instance
2041 * @retval None
2042 */
2043 __STATIC_INLINE void LL_DMA2D_DisableIT_TC(DMA2D_TypeDef *DMA2Dx)
2044 {
2045 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
2046 }
2047
2048 /**
2049 * @brief Disable Transfer Error Interrupt
2050 * @rmtoll CR TEIE LL_DMA2D_DisableIT_TE
2051 * @param DMA2Dx DMA2D Instance
2052 * @retval None
2053 */
2054 __STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx)
2055 {
2056 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
2057 }
2058
2059 /**
2060 * @brief Check if the DMA2D Configuration Error interrupt source is enabled or disabled.
2061 * @rmtoll CR CEIE LL_DMA2D_IsEnabledIT_CE
2062 * @param DMA2Dx DMA2D Instance
2063 * @retval State of bit (1 or 0).
2064 */
2065 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx)
2066 {
2067 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL);
2068 }
2069
2070 /**
2071 * @brief Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled.
2072 * @rmtoll CR CTCIE LL_DMA2D_IsEnabledIT_CTC
2073 * @param DMA2Dx DMA2D Instance
2074 * @retval State of bit (1 or 0).
2075 */
2076 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx)
2077 {
2078 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL);
2079 }
2080
2081 /**
2082 * @brief Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled.
2083 * @rmtoll CR CAEIE LL_DMA2D_IsEnabledIT_CAE
2084 * @param DMA2Dx DMA2D Instance
2085 * @retval State of bit (1 or 0).
2086 */
2087 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx)
2088 {
2089 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL);
2090 }
2091
2092 /**
2093 * @brief Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled.
2094 * @rmtoll CR TWIE LL_DMA2D_IsEnabledIT_TW
2095 * @param DMA2Dx DMA2D Instance
2096 * @retval State of bit (1 or 0).
2097 */
2098 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx)
2099 {
2100 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL);
2101 }
2102
2103 /**
2104 * @brief Check if the DMA2D Transfer Complete interrupt source is enabled or disabled.
2105 * @rmtoll CR TCIE LL_DMA2D_IsEnabledIT_TC
2106 * @param DMA2Dx DMA2D Instance
2107 * @retval State of bit (1 or 0).
2108 */
2109 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx)
2110 {
2111 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL);
2112 }
2113
2114 /**
2115 * @brief Check if the DMA2D Transfer Error interrupt source is enabled or disabled.
2116 * @rmtoll CR TEIE LL_DMA2D_IsEnabledIT_TE
2117 * @param DMA2Dx DMA2D Instance
2118 * @retval State of bit (1 or 0).
2119 */
2120 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx)
2121 {
2122 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL);
2123 }
2124
2125
2126
2127 /**
2128 * @}
2129 */
2130
2131 #if defined(USE_FULL_LL_DRIVER)
2132 /** @defgroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions
2133 * @{
2134 */
2135
2136 ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx);
2137 ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
2138 void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
2139 void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx);
2140 void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg);
2141 void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct);
2142 uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2143 uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2144 uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2145 uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2146 void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines);
2147
2148 /**
2149 * @}
2150 */
2151 #endif /* USE_FULL_LL_DRIVER */
2152
2153 /**
2154 * @}
2155 */
2156
2157 /**
2158 * @}
2159 */
2160
2161 #endif /* defined (DMA2D) */
2162
2163 /**
2164 * @}
2165 */
2166
2167 #ifdef __cplusplus
2168 }
2169 #endif
2170
2171 #endif /* STM32H7xx_LL_DMA2D_H */
2172
2173 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/