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Merge pull request #11270 from haslinghuis/rename_attr
[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_ll_dmamux.h
blob24cb55570cf696576c415de2efc13f3ef4b77d32
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_dmamux.h
4 * @author MCD Application Team
5 * @brief Header file of DMAMUX LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_LL_DMAMUX_H
22 #define STM32H7xx_LL_DMAMUX_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx.h"
30
31 /** @addtogroup STM32H7xx_LL_Driver
32 * @{
33 */
34
35 #if defined (DMAMUX1) || defined (DMAMUX2)
36
37 /** @defgroup DMAMUX_LL DMAMUX
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants
45 * @{
46 */
47 /* Define used to get DMAMUX CCR register size */
48 #define DMAMUX_CCR_SIZE 0x00000004U
49
50 /* Define used to get DMAMUX RGCR register size */
51 #define DMAMUX_RGCR_SIZE 0x00000004U
52
53 /* Define used to get DMAMUX RequestGenerator offset */
54 #define DMAMUX_REQ_GEN_OFFSET (DMAMUX1_RequestGenerator0_BASE - DMAMUX1_BASE)
55 /* Define used to get DMAMUX Channel Status offset */
56 #define DMAMUX_CH_STATUS_OFFSET (DMAMUX1_ChannelStatus_BASE - DMAMUX1_BASE)
57 /* Define used to get DMAMUX RequestGenerator status offset */
58 #define DMAMUX_REQ_GEN_STATUS_OFFSET (DMAMUX1_RequestGenStatus_BASE - DMAMUX1_BASE)
59
60 /**
61 * @}
62 */
63
64 /* Private macros ------------------------------------------------------------*/
65 /* Exported types ------------------------------------------------------------*/
66 /* Exported constants --------------------------------------------------------*/
67 /** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants
68 * @{
69 */
70 /** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines
71 * @brief Flags defines which can be used with LL_DMAMUX_WriteReg function
72 * @{
73 */
74 #define LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0 /*!< Synchronization Event Overrun Flag Channel 0 */
75 #define LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1 /*!< Synchronization Event Overrun Flag Channel 1 */
76 #define LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2 /*!< Synchronization Event Overrun Flag Channel 2 */
77 #define LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3 /*!< Synchronization Event Overrun Flag Channel 3 */
78 #define LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4 /*!< Synchronization Event Overrun Flag Channel 4 */
79 #define LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5 /*!< Synchronization Event Overrun Flag Channel 5 */
80 #define LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6 /*!< Synchronization Event Overrun Flag Channel 6 */
81 #define LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7 /*!< Synchronization Event Overrun Flag Channel 7 */
82 #define LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8 /*!< Synchronization Event Overrun Flag Channel 8 */
83 #define LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9 /*!< Synchronization Event Overrun Flag Channel 9 */
84 #define LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10 /*!< Synchronization Event Overrun Flag Channel 10 */
85 #define LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11 /*!< Synchronization Event Overrun Flag Channel 11 */
86 #define LL_DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12 /*!< Synchronization Event Overrun Flag Channel 12 */
87 #define LL_DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13 /*!< Synchronization Event Overrun Flag Channel 13 */
88 #define LL_DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14 /*!< Synchronization Event Overrun Flag Channel 14 */
89 #define LL_DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15 /*!< Synchronization Event Overrun Flag Channel 15 */
90 #define LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0 /*!< Request Generator 0 Trigger Event Overrun Flag */
91 #define LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1 /*!< Request Generator 1 Trigger Event Overrun Flag */
92 #define LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2 /*!< Request Generator 2 Trigger Event Overrun Flag */
93 #define LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3 /*!< Request Generator 3 Trigger Event Overrun Flag */
94 #define LL_DMAMUX_RGCFR_RGCOF4 DMAMUX_RGCFR_COF4 /*!< Request Generator 4 Trigger Event Overrun Flag */
95 #define LL_DMAMUX_RGCFR_RGCOF5 DMAMUX_RGCFR_COF5 /*!< Request Generator 5 Trigger Event Overrun Flag */
96 #define LL_DMAMUX_RGCFR_RGCOF6 DMAMUX_RGCFR_COF6 /*!< Request Generator 6 Trigger Event Overrun Flag */
97 #define LL_DMAMUX_RGCFR_RGCOF7 DMAMUX_RGCFR_COF7 /*!< Request Generator 7 Trigger Event Overrun Flag */
98 /**
99 * @}
100 */
101
102 /** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines
103 * @brief Flags defines which can be used with LL_DMAMUX_ReadReg function
104 * @{
105 */
106 #define LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0 /*!< Synchronization Event Overrun Flag Channel 0 */
107 #define LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1 /*!< Synchronization Event Overrun Flag Channel 1 */
108 #define LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2 /*!< Synchronization Event Overrun Flag Channel 2 */
109 #define LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3 /*!< Synchronization Event Overrun Flag Channel 3 */
110 #define LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4 /*!< Synchronization Event Overrun Flag Channel 4 */
111 #define LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5 /*!< Synchronization Event Overrun Flag Channel 5 */
112 #define LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6 /*!< Synchronization Event Overrun Flag Channel 6 */
113 #define LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7 /*!< Synchronization Event Overrun Flag Channel 7 */
114 #define LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8 /*!< Synchronization Event Overrun Flag Channel 8 */
115 #define LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9 /*!< Synchronization Event Overrun Flag Channel 9 */
116 #define LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10 /*!< Synchronization Event Overrun Flag Channel 10 */
117 #define LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11 /*!< Synchronization Event Overrun Flag Channel 11 */
118 #define LL_DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12 /*!< Synchronization Event Overrun Flag Channel 12 */
119 #define LL_DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13 /*!< Synchronization Event Overrun Flag Channel 13 */
120 #define LL_DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14 /*!< Synchronization Event Overrun Flag Channel 14 */
121 #define LL_DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15 /*!< Synchronization Event Overrun Flag Channel 15 */
122 #define LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0 /*!< Request Generator 0 Trigger Event Overrun Flag */
123 #define LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1 /*!< Request Generator 1 Trigger Event Overrun Flag */
124 #define LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2 /*!< Request Generator 2 Trigger Event Overrun Flag */
125 #define LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3 /*!< Request Generator 3 Trigger Event Overrun Flag */
126 #define LL_DMAMUX_RGSR_RGOF4 DMAMUX_RGSR_OF4 /*!< Request Generator 4 Trigger Event Overrun Flag */
127 #define LL_DMAMUX_RGSR_RGOF5 DMAMUX_RGSR_OF5 /*!< Request Generator 5 Trigger Event Overrun Flag */
128 #define LL_DMAMUX_RGSR_RGOF6 DMAMUX_RGSR_OF6 /*!< Request Generator 6 Trigger Event Overrun Flag */
129 #define LL_DMAMUX_RGSR_RGOF7 DMAMUX_RGSR_OF7 /*!< Request Generator 7 Trigger Event Overrun Flag */
130 /**
131 * @}
132 */
133
134 /** @defgroup DMAMUX_LL_EC_IT IT Defines
135 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions
136 * @{
137 */
138 #define LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE /*!< Synchronization Event Overrun Interrupt */
139 #define LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE /*!< Request Generation Trigger Event Overrun Interrupt */
140 /**
141 * @}
142 */
143
144 /** @defgroup DMAMUX1_Request_selection DMAMUX1 Request selection
145 * @brief DMAMUX1 Request selection
146 * @{
147 */
148 /* DMAMUX1 requests */
149 #define LL_DMAMUX1_REQ_MEM2MEM 0U /*!< memory to memory transfer */
150 #define LL_DMAMUX1_REQ_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */
151 #define LL_DMAMUX1_REQ_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */
152 #define LL_DMAMUX1_REQ_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */
153 #define LL_DMAMUX1_REQ_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */
154 #define LL_DMAMUX1_REQ_GENERATOR4 5U /*!< DMAMUX1 request generator 4 */
155 #define LL_DMAMUX1_REQ_GENERATOR5 6U /*!< DMAMUX1 request generator 5 */
156 #define LL_DMAMUX1_REQ_GENERATOR6 7U /*!< DMAMUX1 request generator 6 */
157 #define LL_DMAMUX1_REQ_GENERATOR7 8U /*!< DMAMUX1 request generator 7 */
158 #define LL_DMAMUX1_REQ_ADC1 9U /*!< DMAMUX1 ADC1 request */
159 #define LL_DMAMUX1_REQ_ADC2 10U /*!< DMAMUX1 ADC2 request */
160 #define LL_DMAMUX1_REQ_TIM1_CH1 11U /*!< DMAMUX1 TIM1 CH1 request */
161 #define LL_DMAMUX1_REQ_TIM1_CH2 12U /*!< DMAMUX1 TIM1 CH2 request */
162 #define LL_DMAMUX1_REQ_TIM1_CH3 13U /*!< DMAMUX1 TIM1 CH3 request */
163 #define LL_DMAMUX1_REQ_TIM1_CH4 14U /*!< DMAMUX1 TIM1 CH4 request */
164 #define LL_DMAMUX1_REQ_TIM1_UP 15U /*!< DMAMUX1 TIM1 UP request */
165 #define LL_DMAMUX1_REQ_TIM1_TRIG 16U /*!< DMAMUX1 TIM1 TRIG request */
166 #define LL_DMAMUX1_REQ_TIM1_COM 17U /*!< DMAMUX1 TIM1 COM request */
167 #define LL_DMAMUX1_REQ_TIM2_CH1 18U /*!< DMAMUX1 TIM2 CH1 request */
168 #define LL_DMAMUX1_REQ_TIM2_CH2 19U /*!< DMAMUX1 TIM2 CH2 request */
169 #define LL_DMAMUX1_REQ_TIM2_CH3 20U /*!< DMAMUX1 TIM2 CH3 request */
170 #define LL_DMAMUX1_REQ_TIM2_CH4 21U /*!< DMAMUX1 TIM2 CH4 request */
171 #define LL_DMAMUX1_REQ_TIM2_UP 22U /*!< DMAMUX1 TIM2 UP request */
172 #define LL_DMAMUX1_REQ_TIM3_CH1 23U /*!< DMAMUX1 TIM3 CH1 request */
173 #define LL_DMAMUX1_REQ_TIM3_CH2 24U /*!< DMAMUX1 TIM3 CH2 request */
174 #define LL_DMAMUX1_REQ_TIM3_CH3 25U /*!< DMAMUX1 TIM3 CH3 request */
175 #define LL_DMAMUX1_REQ_TIM3_CH4 26U /*!< DMAMUX1 TIM3 CH4 request */
176 #define LL_DMAMUX1_REQ_TIM3_UP 27U /*!< DMAMUX1 TIM3 UP request */
177 #define LL_DMAMUX1_REQ_TIM3_TRIG 28U /*!< DMAMUX1 TIM3 TRIG request */
178 #define LL_DMAMUX1_REQ_TIM4_CH1 29U /*!< DMAMUX1 TIM4 CH1 request */
179 #define LL_DMAMUX1_REQ_TIM4_CH2 30U /*!< DMAMUX1 TIM4 CH2 request */
180 #define LL_DMAMUX1_REQ_TIM4_CH3 31U /*!< DMAMUX1 TIM4 CH3 request */
181 #define LL_DMAMUX1_REQ_TIM4_UP 32U /*!< DMAMUX1 TIM4 UP request */
182 #define LL_DMAMUX1_REQ_I2C1_RX 33U /*!< DMAMUX1 I2C1 RX request */
183 #define LL_DMAMUX1_REQ_I2C1_TX 34U /*!< DMAMUX1 I2C1 TX request */
184 #define LL_DMAMUX1_REQ_I2C2_RX 35U /*!< DMAMUX1 I2C2 RX request */
185 #define LL_DMAMUX1_REQ_I2C2_TX 36U /*!< DMAMUX1 I2C2 TX request */
186 #define LL_DMAMUX1_REQ_SPI1_RX 37U /*!< DMAMUX1 SPI1 RX request */
187 #define LL_DMAMUX1_REQ_SPI1_TX 38U /*!< DMAMUX1 SPI1 TX request */
188 #define LL_DMAMUX1_REQ_SPI2_RX 39U /*!< DMAMUX1 SPI2 RX request */
189 #define LL_DMAMUX1_REQ_SPI2_TX 40U /*!< DMAMUX1 SPI2 TX request */
190 #define LL_DMAMUX1_REQ_USART1_RX 41U /*!< DMAMUX1 USART1 RX request */
191 #define LL_DMAMUX1_REQ_USART1_TX 42U /*!< DMAMUX1 USART1 TX request */
192 #define LL_DMAMUX1_REQ_USART2_RX 43U /*!< DMAMUX1 USART2 RX request */
193 #define LL_DMAMUX1_REQ_USART2_TX 44U /*!< DMAMUX1 USART2 TX request */
194 #define LL_DMAMUX1_REQ_USART3_RX 45U /*!< DMAMUX1 USART3 RX request */
195 #define LL_DMAMUX1_REQ_USART3_TX 46U /*!< DMAMUX1 USART3 TX request */
196 #define LL_DMAMUX1_REQ_TIM8_CH1 47U /*!< DMAMUX1 TIM8 CH1 request */
197 #define LL_DMAMUX1_REQ_TIM8_CH2 48U /*!< DMAMUX1 TIM8 CH2 request */
198 #define LL_DMAMUX1_REQ_TIM8_CH3 49U /*!< DMAMUX1 TIM8 CH3 request */
199 #define LL_DMAMUX1_REQ_TIM8_CH4 50U /*!< DMAMUX1 TIM8 CH4 request */
200 #define LL_DMAMUX1_REQ_TIM8_UP 51U /*!< DMAMUX1 TIM8 UP request */
201 #define LL_DMAMUX1_REQ_TIM8_TRIG 52U /*!< DMAMUX1 TIM8 TRIG request */
202 #define LL_DMAMUX1_REQ_TIM8_COM 53U /*!< DMAMUX1 TIM8 COM request */
203 #define LL_DMAMUX1_REQ_TIM5_CH1 55U /*!< DMAMUX1 TIM5 CH1 request */
204 #define LL_DMAMUX1_REQ_TIM5_CH2 56U /*!< DMAMUX1 TIM5 CH2 request */
205 #define LL_DMAMUX1_REQ_TIM5_CH3 57U /*!< DMAMUX1 TIM5 CH3 request */
206 #define LL_DMAMUX1_REQ_TIM5_CH4 58U /*!< DMAMUX1 TIM5 CH4 request */
207 #define LL_DMAMUX1_REQ_TIM5_UP 59U /*!< DMAMUX1 TIM5 UP request */
208 #define LL_DMAMUX1_REQ_TIM5_TRIG 60U /*!< DMAMUX1 TIM5 TRIG request */
209 #define LL_DMAMUX1_REQ_SPI3_RX 61U /*!< DMAMUX1 SPI3 RX request */
210 #define LL_DMAMUX1_REQ_SPI3_TX 62U /*!< DMAMUX1 SPI3 TX request */
211 #define LL_DMAMUX1_REQ_UART4_RX 63U /*!< DMAMUX1 UART4 RX request */
212 #define LL_DMAMUX1_REQ_UART4_TX 64U /*!< DMAMUX1 UART4 TX request */
213 #define LL_DMAMUX1_REQ_UART5_RX 65U /*!< DMAMUX1 UART5 RX request */
214 #define LL_DMAMUX1_REQ_UART5_TX 66U /*!< DMAMUX1 UART5 TX request */
215 #define LL_DMAMUX1_REQ_DAC1_CH1 67U /*!< DMAMUX1 DAC1 Channel 1 request */
216 #define LL_DMAMUX1_REQ_DAC1_CH2 68U /*!< DMAMUX1 DAC1 Channel 2 request */
217 #define LL_DMAMUX1_REQ_TIM6_UP 69U /*!< DMAMUX1 TIM6 UP request */
218 #define LL_DMAMUX1_REQ_TIM7_UP 70U /*!< DMAMUX1 TIM7 UP request */
219 #define LL_DMAMUX1_REQ_USART6_RX 71U /*!< DMAMUX1 USART6 RX request */
220 #define LL_DMAMUX1_REQ_USART6_TX 72U /*!< DMAMUX1 USART6 TX request */
221 #define LL_DMAMUX1_REQ_I2C3_RX 73U /*!< DMAMUX1 I2C3 RX request */
222 #define LL_DMAMUX1_REQ_I2C3_TX 74U /*!< DMAMUX1 I2C3 TX request */
223 #if defined (PSSI)
224 #define LL_DMAMUX1_REQ_DCMI_PSSI 75U /*!< DMAMUX1 DCMI/PSSI request */
225 #define LL_DMAMUX1_REQ_DCMI LL_DMAMUX1_REQ_DCMI_PSSI /* Legacy define */
226 #else
227 #define LL_DMAMUX1_REQ_DCMI 75U /*!< DMAMUX1 DCMI request */
228 #endif /* PSSI */
229 #define LL_DMAMUX1_REQ_CRYP_IN 76U /*!< DMAMUX1 CRYP IN request */
230 #define LL_DMAMUX1_REQ_CRYP_OUT 77U /*!< DMAMUX1 CRYP OUT request */
231 #define LL_DMAMUX1_REQ_HASH_IN 78U /*!< DMAMUX1 HASH IN request */
232 #define LL_DMAMUX1_REQ_UART7_RX 79U /*!< DMAMUX1 UART7 RX request */
233 #define LL_DMAMUX1_REQ_UART7_TX 80U /*!< DMAMUX1 UART7 TX request */
234 #define LL_DMAMUX1_REQ_UART8_RX 81U /*!< DMAMUX1 UART8 RX request */
235 #define LL_DMAMUX1_REQ_UART8_TX 82U /*!< DMAMUX1 UART8 TX request */
236 #define LL_DMAMUX1_REQ_SPI4_RX 83U /*!< DMAMUX1 SPI4 RX request */
237 #define LL_DMAMUX1_REQ_SPI4_TX 84U /*!< DMAMUX1 SPI4 TX request */
238 #define LL_DMAMUX1_REQ_SPI5_RX 85U /*!< DMAMUX1 SPI5 RX request */
239 #define LL_DMAMUX1_REQ_SPI5_TX 86U /*!< DMAMUX1 SPI5 TX request */
240 #define LL_DMAMUX1_REQ_SAI1_A 87U /*!< DMAMUX1 SAI1 A request */
241 #define LL_DMAMUX1_REQ_SAI1_B 88U /*!< DMAMUX1 SAI1 B request */
242 #if defined(SAI2)
243 #define LL_DMAMUX1_REQ_SAI2_A 89U /*!< DMAMUX1 SAI2 A request */
244 #define LL_DMAMUX1_REQ_SAI2_B 90U /*!< DMAMUX1 SAI2 B request */
245 #endif /* SAI2 */
246 #define LL_DMAMUX1_REQ_SWPMI_RX 91U /*!< DMAMUX1 SWPMI RX request */
247 #define LL_DMAMUX1_REQ_SWPMI_TX 92U /*!< DMAMUX1 SWPMI TX request */
248 #define LL_DMAMUX1_REQ_SPDIF_RX_DT 93U /*!< DMAMUX1 SPDIF RXDT request */
249 #define LL_DMAMUX1_REQ_SPDIF_RX_CS 94U /*!< DMAMUX1 SPDIF RXCS request */
250 #if defined (HRTIM1)
251 #define LL_DMAMUX1_REQ_HRTIM_MASTER 95U /*!< DMAMUX1 HRTIM1 Master request 1 */
252 #define LL_DMAMUX1_REQ_HRTIM_TIMER_A 96U /*!< DMAMUX1 HRTIM1 TimerA request 2 */
253 #define LL_DMAMUX1_REQ_HRTIM_TIMER_B 97U /*!< DMAMUX1 HRTIM1 TimerB request 3 */
254 #define LL_DMAMUX1_REQ_HRTIM_TIMER_C 98U /*!< DMAMUX1 HRTIM1 TimerC request 4 */
255 #define LL_DMAMUX1_REQ_HRTIM_TIMER_D 99U /*!< DMAMUX1 HRTIM1 TimerD request 5 */
256 #define LL_DMAMUX1_REQ_HRTIM_TIMER_E 100U /*!< DMAMUX1 HRTIM1 TimerE request 6 */
257 #endif /* HRTIM1 */
258 #define LL_DMAMUX1_REQ_DFSDM1_FLT0 101U /*!< DMAMUX1 DFSDM1 Filter0 request */
259 #define LL_DMAMUX1_REQ_DFSDM1_FLT1 102U /*!< DMAMUX1 DFSDM1 Filter1 request */
260 #define LL_DMAMUX1_REQ_DFSDM1_FLT2 103U /*!< DMAMUX1 DFSDM1 Filter2 request */
261 #define LL_DMAMUX1_REQ_DFSDM1_FLT3 104U /*!< DMAMUX1 DFSDM1 Filter3 request */
262 #define LL_DMAMUX1_REQ_TIM15_CH1 105U /*!< DMAMUX1 TIM15 CH1 request */
263 #define LL_DMAMUX1_REQ_TIM15_UP 106U /*!< DMAMUX1 TIM15 UP request */
264 #define LL_DMAMUX1_REQ_TIM15_TRIG 107U /*!< DMAMUX1 TIM15 TRIG request */
265 #define LL_DMAMUX1_REQ_TIM15_COM 108U /*!< DMAMUX1 TIM15 COM request */
266 #define LL_DMAMUX1_REQ_TIM16_CH1 109U /*!< DMAMUX1 TIM16 CH1 request */
267 #define LL_DMAMUX1_REQ_TIM16_UP 110U /*!< DMAMUX1 TIM16 UP request */
268 #define LL_DMAMUX1_REQ_TIM17_CH1 111U /*!< DMAMUX1 TIM17 CH1 request */
269 #define LL_DMAMUX1_REQ_TIM17_UP 112U /*!< DMAMUX1 TIM17 UP request */
270 #if defined (SAI3)
271 #define LL_DMAMUX1_REQ_SAI3_A 113U /*!< DMAMUX1 SAI3 A request */
272 #define LL_DMAMUX1_REQ_SAI3_B 114U /*!< DMAMUX1 SAI3 B request */
273 #endif /* SAI3 */
274 #if defined (ADC3)
275 #define LL_DMAMUX1_REQ_ADC3 115U /*!< DMAMUX1 ADC3 request */
276 #endif /* ADC3 */
277 #if defined (UART9)
278 #define LL_DMAMUX1_REQ_UART9_RX 116U /*!< DMAMUX1 UART9 RX request */
279 #define LL_DMAMUX1_REQ_UART9_TX 117U /*!< DMAMUX1 UART9 TX request */
280 #endif /* UART9 */
281 #if defined (USART10)
282 #define LL_DMAMUX1_REQ_USART10_RX 118U /*!< DMAMUX1 USART10 RX request */
283 #define LL_DMAMUX1_REQ_USART10_TX 119U /*!< DMAMUX1 USART10 TX request */
284 #endif /* USART10 */
285 #if defined(FMAC)
286 #define LL_DMAMUX1_REQ_FMAC_READ 120U /*!< DMAMUX1 FMAC Read request */
287 #define LL_DMAMUX1_REQ_FMAC_WRITE 121U /*!< DMAMUX1 FMAC Write request */
288 #endif /* FMAC */
289 #if defined(CORDIC)
290 #define LL_DMAMUX1_REQ_CORDIC_READ 122U /*!< DMAMUX1 CORDIC Read request */
291 #define LL_DMAMUX1_REQ_CORDIC_WRITE 123U /*!< DMAMUX1 CORDIC Write request */
292 #endif /* CORDIC */
293 #if defined(I2C5)
294 #define LL_DMAMUX1_REQ_I2C5_RX 124U /*!< DMAMUX1 I2C5 RX request */
295 #define LL_DMAMUX1_REQ_I2C5_TX 125U /*!< DMAMUX1 I2C5 TX request */
296 #endif /* I2C5 */
297 #if defined(TIM23)
298 #define LL_DMAMUX1_REQ_TIM23_CH1 126U /*!< DMAMUX1 TIM23 CH1 request */
299 #define LL_DMAMUX1_REQ_TIM23_CH2 127U /*!< DMAMUX1 TIM23 CH2 request */
300 #define LL_DMAMUX1_REQ_TIM23_CH3 128U /*!< DMAMUX1 TIM23 CH3 request */
301 #define LL_DMAMUX1_REQ_TIM23_CH4 129U /*!< DMAMUX1 TIM23 CH4 request */
302 #define LL_DMAMUX1_REQ_TIM23_UP 130U /*!< DMAMUX1 TIM23 UP request */
303 #define LL_DMAMUX1_REQ_TIM23_TRIG 131U /*!< DMAMUX1 TIM23 TRIG request */
304 #endif /* TIM23 */
305 #if defined(TIM24)
306 #define LL_DMAMUX1_REQ_TIM24_CH1 132U /*!< DMAMUX1 TIM24 CH1 request */
307 #define LL_DMAMUX1_REQ_TIM24_CH2 133U /*!< DMAMUX1 TIM24 CH2 request */
308 #define LL_DMAMUX1_REQ_TIM24_CH3 134U /*!< DMAMUX1 TIM24 CH3 request */
309 #define LL_DMAMUX1_REQ_TIM24_CH4 135U /*!< DMAMUX1 TIM24 CH4 request */
310 #define LL_DMAMUX1_REQ_TIM24_UP 136U /*!< DMAMUX1 TIM24 UP request */
311 #define LL_DMAMUX1_REQ_TIM24_TRIG 137U /*!< DMAMUX1 TIM24 TRIG request */
312 #endif /* TIM24 */
313 /**
314 * @}
315 */
316
317 /** @defgroup DMAMUX2_Request_selection DMAMUX2 Request selection
318 * @brief DMAMUX2 Request selection
319 * @{
320 */
321 /* DMAMUX2 requests */
322 #define LL_DMAMUX2_REQ_MEM2MEM 0U /*!< memory to memory transfer */
323 #define LL_DMAMUX2_REQ_GENERATOR0 1U /*!< DMAMUX2 request generator 0 */
324 #define LL_DMAMUX2_REQ_GENERATOR1 2U /*!< DMAMUX2 request generator 1 */
325 #define LL_DMAMUX2_REQ_GENERATOR2 3U /*!< DMAMUX2 request generator 2 */
326 #define LL_DMAMUX2_REQ_GENERATOR3 4U /*!< DMAMUX2 request generator 3 */
327 #define LL_DMAMUX2_REQ_GENERATOR4 5U /*!< DMAMUX2 request generator 4 */
328 #define LL_DMAMUX2_REQ_GENERATOR5 6U /*!< DMAMUX2 request generator 5 */
329 #define LL_DMAMUX2_REQ_GENERATOR6 7U /*!< DMAMUX2 request generator 6 */
330 #define LL_DMAMUX2_REQ_GENERATOR7 8U /*!< DMAMUX2 request generator 7 */
331 #define LL_DMAMUX2_REQ_LPUART1_RX 9U /*!< DMAMUX2 LP_UART1_RX request */
332 #define LL_DMAMUX2_REQ_LPUART1_TX 10U /*!< DMAMUX2 LP_UART1_TX request */
333 #define LL_DMAMUX2_REQ_SPI6_RX 11U /*!< DMAMUX2 SPI6 RX request */
334 #define LL_DMAMUX2_REQ_SPI6_TX 12U /*!< DMAMUX2 SPI6 TX request */
335 #define LL_DMAMUX2_REQ_I2C4_RX 13U /*!< DMAMUX2 I2C4 RX request */
336 #define LL_DMAMUX2_REQ_I2C4_TX 14U /*!< DMAMUX2 I2C4 TX request */
337 #if defined (SAI4)
338 #define LL_DMAMUX2_REQ_SAI4_A 15U /*!< DMAMUX2 SAI4 A request */
339 #define LL_DMAMUX2_REQ_SAI4_B 16U /*!< DMAMUX2 SAI4 B request */
340 #endif /* SAI4 */
341 #if defined (ADC3)
342 #define LL_DMAMUX2_REQ_ADC3 17U /*!< DMAMUX2 ADC3 request */
343 #endif /* ADC3 */
344 #if defined (DAC2)
345 #define LL_DMAMUX2_REQ_DAC2_CH1 17U /*!< DMAMUX2 DAC2 CH1 request */
346 #endif /* DAC2 */
347 #if defined (DFSDM2_Channel0)
348 #define LL_DMAMUX2_REQ_DFSDM2_FLT0 18U /*!< DMAMUX2 DFSDM2 Filter0 request */
349 #endif /* DFSDM2_Channel0 */
350 /**
351 * @}
352 */
353
354
355 /** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel
356 * @{
357 */
358 #define LL_DMAMUX_CHANNEL_0 0x00000000U /*!< DMAMUX1 Channel 0 connected to DMA1 Channel 0 , DMAMUX2 Channel 0 connected to BDMA Channel 0 */
359 #define LL_DMAMUX_CHANNEL_1 0x00000001U /*!< DMAMUX1 Channel 1 connected to DMA1 Channel 1 , DMAMUX2 Channel 1 connected to BDMA Channel 1 */
360 #define LL_DMAMUX_CHANNEL_2 0x00000002U /*!< DMAMUX1 Channel 2 connected to DMA1 Channel 2 , DMAMUX2 Channel 2 connected to BDMA Channel 2 */
361 #define LL_DMAMUX_CHANNEL_3 0x00000003U /*!< DMAMUX1 Channel 3 connected to DMA1 Channel 3 , DMAMUX2 Channel 3 connected to BDMA Channel 3 */
362 #define LL_DMAMUX_CHANNEL_4 0x00000004U /*!< DMAMUX1 Channel 4 connected to DMA1 Channel 4 , DMAMUX2 Channel 4 connected to BDMA Channel 4 */
363 #define LL_DMAMUX_CHANNEL_5 0x00000005U /*!< DMAMUX1 Channel 5 connected to DMA1 Channel 5 , DMAMUX2 Channel 5 connected to BDMA Channel 5 */
364 #define LL_DMAMUX_CHANNEL_6 0x00000006U /*!< DMAMUX1 Channel 6 connected to DMA1 Channel 6 , DMAMUX2 Channel 6 connected to BDMA Channel 6 */
365 #define LL_DMAMUX_CHANNEL_7 0x00000007U /*!< DMAMUX1 Channel 7 connected to DMA1 Channel 7 , DMAMUX2 Channel 7 connected to BDMA Channel 7 */
366 #define LL_DMAMUX_CHANNEL_8 0x00000008U /*!< DMAMUX1 Channel 8 connected to DMA2 Channel 0 */
367 #define LL_DMAMUX_CHANNEL_9 0x00000009U /*!< DMAMUX1 Channel 9 connected to DMA2 Channel 1 */
368 #define LL_DMAMUX_CHANNEL_10 0x0000000AU /*!< DMAMUX1 Channel 10 connected to DMA2 Channel 2 */
369 #define LL_DMAMUX_CHANNEL_11 0x0000000BU /*!< DMAMUX1 Channel 11 connected to DMA2 Channel 3 */
370 #define LL_DMAMUX_CHANNEL_12 0x0000000CU /*!< DMAMUX1 Channel 12 connected to DMA2 Channel 4 */
371 #define LL_DMAMUX_CHANNEL_13 0x0000000DU /*!< DMAMUX1 Channel 13 connected to DMA2 Channel 5 */
372 #define LL_DMAMUX_CHANNEL_14 0x0000000EU /*!< DMAMUX1 Channel 14 connected to DMA2 Channel 6 */
373 #define LL_DMAMUX_CHANNEL_15 0x0000000FU /*!< DMAMUX1 Channel 15 connected to DMA2 Channel 7 */
374 /**
375 * @}
376 */
377
378 /** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity
379 * @{
380 */
381 #define LL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< All requests are blocked */
382 #define LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0 /*!< Synchronization on event on rising edge */
383 #define LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1 /*!< Synchronization on event on falling edge */
384 #define LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */
385 /**
386 * @}
387 */
388
389 /** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event
390 * @{
391 */
392 #define LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 0x00000000U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel0 Event */
393 #define LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 0x01000000U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel1 Event */
394 #define LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 0x02000000U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel2 Event */
395 #define LL_DMAMUX1_SYNC_LPTIM1_OUT 0x03000000U /*!< DMAMUX1 synchronization Signal is LPTIM1 OUT */
396 #define LL_DMAMUX1_SYNC_LPTIM2_OUT 0x04000000U /*!< DMAMUX1 synchronization Signal is LPTIM2 OUT */
397 #define LL_DMAMUX1_SYNC_LPTIM3_OUT 0x05000000U /*!< DMAMUX1 synchronization Signal is LPTIM3 OUT */
398 #define LL_DMAMUX1_SYNC_EXTI0 0x06000000U /*!< DMAMUX1 synchronization Signal is EXTI0 IT */
399 #define LL_DMAMUX1_SYNC_TIM12_TRGO 0x07000000U /*!< DMAMUX1 synchronization Signal is TIM12 TRGO */
400
401 #define LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT 0x00000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel0 Event */
402 #define LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT 0x01000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel1 Event */
403 #define LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT 0x02000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel2 Event */
404 #define LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT 0x03000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel3 Event */
405 #define LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT 0x04000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel4 Event */
406 #define LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT 0x05000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel5 Event */
407 #define LL_DMAMUX2_SYNC_LPUART1_RX_WKUP 0x06000000U /*!< DMAMUX2 synchronization Signal is LPUART1 RX Wakeup */
408 #define LL_DMAMUX2_SYNC_LPUART1_TX_WKUP 0x07000000U /*!< DMAMUX2 synchronization Signal is LPUART1 TX Wakeup */
409 #define LL_DMAMUX2_SYNC_LPTIM2_OUT 0x08000000U /*!< DMAMUX2 synchronization Signal is LPTIM2 output */
410 #define LL_DMAMUX2_SYNC_LPTIM3_OUT 0x09000000U /*!< DMAMUX2 synchronization Signal is LPTIM3 output */
411 #define LL_DMAMUX2_SYNC_I2C4_WKUP 0x0A000000U /*!< DMAMUX2 synchronization Signal is I2C4 Wakeup */
412 #define LL_DMAMUX2_SYNC_SPI6_WKUP 0x0B000000U /*!< DMAMUX2 synchronization Signal is SPI6 Wakeup */
413 #define LL_DMAMUX2_SYNC_COMP1_OUT 0x0C000000U /*!< DMAMUX2 synchronization Signal is Comparator 1 output */
414 #define LL_DMAMUX2_SYNC_RTC_WKUP 0x0D000000U /*!< DMAMUX2 synchronization Signal is RTC Wakeup */
415 #define LL_DMAMUX2_SYNC_EXTI0 0x0E000000U /*!< DMAMUX2 synchronization Signal is EXTI0 IT */
416 #define LL_DMAMUX2_SYNC_EXTI2 0x0F000000U /*!< DMAMUX2 synchronization Signal is EXTI2 IT */
417
418 /**
419 * @}
420 */
421
422 /** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel
423 * @{
424 */
425 #define LL_DMAMUX_REQ_GEN_0 0x00000000U
426 #define LL_DMAMUX_REQ_GEN_1 0x00000001U
427 #define LL_DMAMUX_REQ_GEN_2 0x00000002U
428 #define LL_DMAMUX_REQ_GEN_3 0x00000003U
429 #define LL_DMAMUX_REQ_GEN_4 0x00000004U
430 #define LL_DMAMUX_REQ_GEN_5 0x00000005U
431 #define LL_DMAMUX_REQ_GEN_6 0x00000006U
432 #define LL_DMAMUX_REQ_GEN_7 0x00000007U
433 /**
434 * @}
435 */
436
437 /** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity
438 * @{
439 */
440 #define LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< No external DMA request generation */
441 #define LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0 /*!< External DMA request generation on event on rising edge */
442 #define LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1 /*!< External DMA request generation on event on falling edge */
443 #define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1) /*!< External DMA request generation on rising and falling edge */
444 /**
445 * @}
446 */
447
448 /** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation
449 * @{
450 */
451 #define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 0U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel0 Event */
452 #define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 1U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel1 Event */
453 #define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 2U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel2 Event */
454 #define LL_DMAMUX1_REQ_GEN_LPTIM1_OUT 3U /*!< DMAMUX1 Request generator Signal is LPTIM1 OUT */
455 #define LL_DMAMUX1_REQ_GEN_LPTIM2_OUT 4U /*!< DMAMUX1 Request generator Signal is LPTIM2 OUT */
456 #define LL_DMAMUX1_REQ_GEN_LPTIM3_OUT 5U /*!< DMAMUX1 Request generator Signal is LPTIM3 OUT */
457 #define LL_DMAMUX1_REQ_GEN_EXTI0 6U /*!< DMAMUX1 Request generator Signal is EXTI0 IT */
458 #define LL_DMAMUX1_REQ_GEN_TIM12_TRGO 7U /*!< DMAMUX1 Request generator Signal is TIM12 TRGO */
459
460 #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 0U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel0 Event */
461 #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 1U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel1 Event */
462 #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 2U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel2 Event */
463 #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 3U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel3 Event */
464 #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 4U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel4 Event */
465 #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 5U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel5 Event */
466 #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 6U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel6 Event */
467 #define LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 7U /*!< DMAMUX2 Request generator Signal is LPUART1 RX Wakeup */
468 #define LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 8U /*!< DMAMUX2 Request generator Signal is LPUART1 TX Wakeup */
469 #define LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 9U /*!< DMAMUX2 Request generator Signal is LPTIM2 Wakeup */
470 #define LL_DMAMUX2_REQ_GEN_LPTIM2_OUT 10U /*!< DMAMUX2 Request generator Signal is LPTIM2 OUT */
471 #define LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 11U /*!< DMAMUX2 Request generator Signal is LPTIM3 Wakeup */
472 #define LL_DMAMUX2_REQ_GEN_LPTIM3_OUT 12U /*!< DMAMUX2 Request generator Signal is LPTIM3 OUT */
473 #if defined (LPTIM4)
474 #define LL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 13U /*!< DMAMUX2 Request generator Signal is LPTIM4 Wakeup */
475 #endif /* LPTIM4 */
476 #if defined (LPTIM5)
477 #define LL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 14U /*!< DMAMUX2 Request generator Signal is LPTIM5 Wakeup */
478 #endif /* LPTIM5 */
479 #define LL_DMAMUX2_REQ_GEN_I2C4_WKUP 15U /*!< DMAMUX2 Request generator Signal is I2C4 Wakeup */
480 #define LL_DMAMUX2_REQ_GEN_SPI6_WKUP 16U /*!< DMAMUX2 Request generator Signal is SPI6 Wakeup */
481 #define LL_DMAMUX2_REQ_GEN_COMP1_OUT 17U /*!< DMAMUX2 Request generator Signal is Comparator 1 output */
482 #define LL_DMAMUX2_REQ_GEN_COMP2_OUT 18U /*!< DMAMUX2 Request generator Signal is Comparator 2 output */
483 #define LL_DMAMUX2_REQ_GEN_RTC_WKUP 19U /*!< DMAMUX2 Request generator Signal is RTC Wakeup */
484 #define LL_DMAMUX2_REQ_GEN_EXTI0 20U /*!< DMAMUX2 Request generator Signal is EXTI0 */
485 #define LL_DMAMUX2_REQ_GEN_EXTI2 21U /*!< DMAMUX2 Request generator Signal is EXTI2 */
486 #define LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 22U /*!< DMAMUX2 Request generator Signal is I2C4 IT Event */
487 #define LL_DMAMUX2_REQ_GEN_SPI6_IT 23U /*!< DMAMUX2 Request generator Signal is SPI6 IT */
488 #define LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 24U /*!< DMAMUX2 Request generator Signal is LPUART1 Tx IT */
489 #define LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 25U /*!< DMAMUX2 Request generator Signal is LPUART1 Rx IT */
490 #if defined (ADC3)
491 #define LL_DMAMUX2_REQ_GEN_ADC3_IT 26U /*!< DMAMUX2 Request generator Signal is ADC3 IT */
492 #define LL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 27U /*!< DMAMUX2 Request generator Signal is ADC3 Analog Watchdog 1 output */
493 #endif /* ADC3 */
494 #define LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 28U /*!< DMAMUX2 Request generator Signal is BDMA Channel 0 IT */
495 #define LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 29U /*!< DMAMUX2 Request generator Signal is BDMA Channel 1 IT */
496 /**
497 * @}
498 */
499
500 /**
501 * @}
502 */
503
504 /* Exported macro ------------------------------------------------------------*/
505 /** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros
506 * @{
507 */
508
509 /** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros
510 * @{
511 */
512 /**
513 * @brief Write a value in DMAMUX register
514 * @param __INSTANCE__ DMAMUX Instance
515 * @param __REG__ Register to be written
516 * @param __VALUE__ Value to be written in the register
517 * @retval None
518 */
519 #define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
520
521 /**
522 * @brief Read a value in DMAMUX register
523 * @param __INSTANCE__ DMAMUX Instance
524 * @param __REG__ Register to be read
525 * @retval Register value
526 */
527 #define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
528 /**
529 * @}
530 */
531
532 /**
533 * @}
534 */
535
536 /* Exported functions --------------------------------------------------------*/
537 /** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions
538 * @{
539 */
540
541 /** @defgroup DMAMUX_LL_EF_Configuration Configuration
542 * @{
543 */
544 /**
545 * @brief Set DMAMUX request ID for DMAMUX Channel x.
546 * @note DMAMUX1 channel 0 to 7 are mapped to DMA1 channel 0 to 7.
547 * DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7.
548 * DMAMUX2 channel 0 to 7 are mapped to BDMA channel 0 to 7.
549 * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_SetRequestID
550 * @param DMAMUXx DMAMUXx Instance
551 * @param Channel This parameter can be one of the following values:
552 * @arg @ref LL_DMAMUX_CHANNEL_0
553 * @arg @ref LL_DMAMUX_CHANNEL_1
554 * @arg @ref LL_DMAMUX_CHANNEL_2
555 * @arg @ref LL_DMAMUX_CHANNEL_3
556 * @arg @ref LL_DMAMUX_CHANNEL_4
557 * @arg @ref LL_DMAMUX_CHANNEL_5
558 * @arg @ref LL_DMAMUX_CHANNEL_6
559 * @arg @ref LL_DMAMUX_CHANNEL_7
560 * @arg @ref LL_DMAMUX_CHANNEL_8
561 * @arg @ref LL_DMAMUX_CHANNEL_9
562 * @arg @ref LL_DMAMUX_CHANNEL_10
563 * @arg @ref LL_DMAMUX_CHANNEL_11
564 * @arg @ref LL_DMAMUX_CHANNEL_12
565 * @arg @ref LL_DMAMUX_CHANNEL_13
566 * @arg @ref LL_DMAMUX_CHANNEL_14
567 * @arg @ref LL_DMAMUX_CHANNEL_15
568 * @param Request This parameter can be one of the following values:
569 * @arg @ref LL_DMAMUX1_REQ_MEM2MEM
570 * @arg @ref LL_DMAMUX1_REQ_GENERATOR0
571 * @arg @ref LL_DMAMUX1_REQ_GENERATOR1
572 * @arg @ref LL_DMAMUX1_REQ_GENERATOR2
573 * @arg @ref LL_DMAMUX1_REQ_GENERATOR3
574 * @arg @ref LL_DMAMUX1_REQ_GENERATOR4
575 * @arg @ref LL_DMAMUX1_REQ_GENERATOR5
576 * @arg @ref LL_DMAMUX1_REQ_GENERATOR6
577 * @arg @ref LL_DMAMUX1_REQ_GENERATOR7
578 * @arg @ref LL_DMAMUX1_REQ_ADC1
579 * @arg @ref LL_DMAMUX1_REQ_ADC2
580 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
581 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
582 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
583 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
584 * @arg @ref LL_DMAMUX1_REQ_TIM1_UP
585 * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
586 * @arg @ref LL_DMAMUX1_REQ_TIM1_COM
587 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
588 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
589 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
590 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
591 * @arg @ref LL_DMAMUX1_REQ_TIM2_UP
592 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
593 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
594 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
595 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
596 * @arg @ref LL_DMAMUX1_REQ_TIM3_UP
597 * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
598 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
599 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
600 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
601 * @arg @ref LL_DMAMUX1_REQ_TIM4_UP
602 * @arg @ref LL_DMAMUX1_REQ_I2C1_RX
603 * @arg @ref LL_DMAMUX1_REQ_I2C1_TX
604 * @arg @ref LL_DMAMUX1_REQ_I2C2_RX
605 * @arg @ref LL_DMAMUX1_REQ_I2C2_TX
606 * @arg @ref LL_DMAMUX1_REQ_SPI1_RX
607 * @arg @ref LL_DMAMUX1_REQ_SPI1_TX
608 * @arg @ref LL_DMAMUX1_REQ_SPI2_RX
609 * @arg @ref LL_DMAMUX1_REQ_SPI2_TX
610 * @arg @ref LL_DMAMUX1_REQ_USART1_RX
611 * @arg @ref LL_DMAMUX1_REQ_USART1_TX
612 * @arg @ref LL_DMAMUX1_REQ_USART2_RX
613 * @arg @ref LL_DMAMUX1_REQ_USART2_TX
614 * @arg @ref LL_DMAMUX1_REQ_USART3_RX
615 * @arg @ref LL_DMAMUX1_REQ_USART3_TX
616 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
617 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
618 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
619 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
620 * @arg @ref LL_DMAMUX1_REQ_TIM8_UP
621 * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
622 * @arg @ref LL_DMAMUX1_REQ_TIM8_COM
623 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
624 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
625 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
626 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
627 * @arg @ref LL_DMAMUX1_REQ_TIM5_UP
628 * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
629 * @arg @ref LL_DMAMUX1_REQ_SPI3_RX
630 * @arg @ref LL_DMAMUX1_REQ_SPI3_TX
631 * @arg @ref LL_DMAMUX1_REQ_UART4_RX
632 * @arg @ref LL_DMAMUX1_REQ_UART4_TX
633 * @arg @ref LL_DMAMUX1_REQ_UART5_RX
634 * @arg @ref LL_DMAMUX1_REQ_UART5_TX
635 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
636 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
637 * @arg @ref LL_DMAMUX1_REQ_TIM6_UP
638 * @arg @ref LL_DMAMUX1_REQ_TIM7_UP
639 * @arg @ref LL_DMAMUX1_REQ_USART6_RX
640 * @arg @ref LL_DMAMUX1_REQ_USART6_TX
641 * @arg @ref LL_DMAMUX1_REQ_I2C3_RX
642 * @arg @ref LL_DMAMUX1_REQ_I2C3_TX
643 * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*)
644 * @arg @ref LL_DMAMUX1_REQ_CRYP_IN
645 * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
646 * @arg @ref LL_DMAMUX1_REQ_HASH_IN
647 * @arg @ref LL_DMAMUX1_REQ_UART7_RX
648 * @arg @ref LL_DMAMUX1_REQ_UART7_TX
649 * @arg @ref LL_DMAMUX1_REQ_UART8_RX
650 * @arg @ref LL_DMAMUX1_REQ_UART8_TX
651 * @arg @ref LL_DMAMUX1_REQ_SPI4_RX
652 * @arg @ref LL_DMAMUX1_REQ_SPI4_TX
653 * @arg @ref LL_DMAMUX1_REQ_SPI5_RX
654 * @arg @ref LL_DMAMUX1_REQ_SPI5_TX
655 * @arg @ref LL_DMAMUX1_REQ_SAI1_A
656 * @arg @ref LL_DMAMUX1_REQ_SAI1_B
657 * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*)
658 * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*)
659 * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
660 * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
661 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
662 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
663 * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
664 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
665 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
666 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
667 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
668 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
669 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
670 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
671 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
672 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
673 * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
674 * @arg @ref LL_DMAMUX1_REQ_TIM15_UP
675 * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
676 * @arg @ref LL_DMAMUX1_REQ_TIM15_COM
677 * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
678 * @arg @ref LL_DMAMUX1_REQ_TIM16_UP
679 * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
680 * @arg @ref LL_DMAMUX1_REQ_TIM17_UP
681 * @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
682 * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
683 * @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
684 * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
685 * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)
686 * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
687 * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)
688 * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*)
689 * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*)
690 * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*)
691 * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*)
692 * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*)
693 * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*)
694 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*)
695 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*)
696 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*)
697 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*)
698 * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*)
699 * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*)
700 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*)
701 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*)
702 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*)
703 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*)
704 * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*)
705 * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*)
706 * @arg @ref LL_DMAMUX2_REQ_MEM2MEM
707 * @arg @ref LL_DMAMUX2_REQ_GENERATOR0
708 * @arg @ref LL_DMAMUX2_REQ_GENERATOR1
709 * @arg @ref LL_DMAMUX2_REQ_GENERATOR2
710 * @arg @ref LL_DMAMUX2_REQ_GENERATOR3
711 * @arg @ref LL_DMAMUX2_REQ_GENERATOR4
712 * @arg @ref LL_DMAMUX2_REQ_GENERATOR5
713 * @arg @ref LL_DMAMUX2_REQ_GENERATOR6
714 * @arg @ref LL_DMAMUX2_REQ_GENERATOR7
715 * @arg @ref LL_DMAMUX2_REQ_LPUART1_RX
716 * @arg @ref LL_DMAMUX2_REQ_LPUART1_TX
717 * @arg @ref LL_DMAMUX2_REQ_SPI6_RX
718 * @arg @ref LL_DMAMUX2_REQ_SPI6_TX
719 * @arg @ref LL_DMAMUX2_REQ_I2C4_RX
720 * @arg @ref LL_DMAMUX2_REQ_I2C4_TX
721 * @arg @ref LL_DMAMUX2_REQ_SAI4_A (*)
722 * @arg @ref LL_DMAMUX2_REQ_SAI4_B (*)
723 * @arg @ref LL_DMAMUX2_REQ_ADC3 (*)
724 * @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*)
725 * @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*)
726 *
727 * @note (*) Availability depends on devices.
728 * @retval None
729 */
730 __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
731 {
732 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
733
734 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
735 }
736
737 /**
738 * @brief Get DMAMUX request ID for DMAMUX Channel x.
739 * @note DMAMUX1 channel 0 to 7 are mapped to DMA1 channel 0 to 7.
740 * DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7.
741 * DMAMUX2 channel 0 to 7 are mapped to BDMA channel 0 to 7.
742 * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_GetRequestID
743 * @param DMAMUXx DMAMUXx Instance
744 * @param Channel This parameter can be one of the following values:
745 * @arg @ref LL_DMAMUX_CHANNEL_0
746 * @arg @ref LL_DMAMUX_CHANNEL_1
747 * @arg @ref LL_DMAMUX_CHANNEL_2
748 * @arg @ref LL_DMAMUX_CHANNEL_3
749 * @arg @ref LL_DMAMUX_CHANNEL_4
750 * @arg @ref LL_DMAMUX_CHANNEL_5
751 * @arg @ref LL_DMAMUX_CHANNEL_6
752 * @arg @ref LL_DMAMUX_CHANNEL_7
753 * @arg @ref LL_DMAMUX_CHANNEL_8
754 * @arg @ref LL_DMAMUX_CHANNEL_9
755 * @arg @ref LL_DMAMUX_CHANNEL_10
756 * @arg @ref LL_DMAMUX_CHANNEL_11
757 * @arg @ref LL_DMAMUX_CHANNEL_12
758 * @arg @ref LL_DMAMUX_CHANNEL_13
759 * @arg @ref LL_DMAMUX_CHANNEL_14
760 * @arg @ref LL_DMAMUX_CHANNEL_15
761 * @retval Returned value can be one of the following values:
762 * @arg @ref LL_DMAMUX1_REQ_MEM2MEM
763 * @arg @ref LL_DMAMUX1_REQ_GENERATOR0
764 * @arg @ref LL_DMAMUX1_REQ_GENERATOR1
765 * @arg @ref LL_DMAMUX1_REQ_GENERATOR2
766 * @arg @ref LL_DMAMUX1_REQ_GENERATOR3
767 * @arg @ref LL_DMAMUX1_REQ_GENERATOR4
768 * @arg @ref LL_DMAMUX1_REQ_GENERATOR5
769 * @arg @ref LL_DMAMUX1_REQ_GENERATOR6
770 * @arg @ref LL_DMAMUX1_REQ_GENERATOR7
771 * @arg @ref LL_DMAMUX1_REQ_ADC1
772 * @arg @ref LL_DMAMUX1_REQ_ADC2
773 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
774 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
775 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
776 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
777 * @arg @ref LL_DMAMUX1_REQ_TIM1_UP
778 * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
779 * @arg @ref LL_DMAMUX1_REQ_TIM1_COM
780 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
781 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
782 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
783 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
784 * @arg @ref LL_DMAMUX1_REQ_TIM2_UP
785 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
786 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
787 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
788 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
789 * @arg @ref LL_DMAMUX1_REQ_TIM3_UP
790 * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
791 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
792 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
793 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
794 * @arg @ref LL_DMAMUX1_REQ_TIM4_UP
795 * @arg @ref LL_DMAMUX1_REQ_I2C1_RX
796 * @arg @ref LL_DMAMUX1_REQ_I2C1_TX
797 * @arg @ref LL_DMAMUX1_REQ_I2C2_RX
798 * @arg @ref LL_DMAMUX1_REQ_I2C2_TX
799 * @arg @ref LL_DMAMUX1_REQ_SPI1_RX
800 * @arg @ref LL_DMAMUX1_REQ_SPI1_TX
801 * @arg @ref LL_DMAMUX1_REQ_SPI2_RX
802 * @arg @ref LL_DMAMUX1_REQ_SPI2_TX
803 * @arg @ref LL_DMAMUX1_REQ_USART1_RX
804 * @arg @ref LL_DMAMUX1_REQ_USART1_TX
805 * @arg @ref LL_DMAMUX1_REQ_USART2_RX
806 * @arg @ref LL_DMAMUX1_REQ_USART2_TX
807 * @arg @ref LL_DMAMUX1_REQ_USART3_RX
808 * @arg @ref LL_DMAMUX1_REQ_USART3_TX
809 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
810 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
811 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
812 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
813 * @arg @ref LL_DMAMUX1_REQ_TIM8_UP
814 * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
815 * @arg @ref LL_DMAMUX1_REQ_TIM8_COM
816 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
817 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
818 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
819 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
820 * @arg @ref LL_DMAMUX1_REQ_TIM5_UP
821 * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
822 * @arg @ref LL_DMAMUX1_REQ_SPI3_RX
823 * @arg @ref LL_DMAMUX1_REQ_SPI3_TX
824 * @arg @ref LL_DMAMUX1_REQ_UART4_RX
825 * @arg @ref LL_DMAMUX1_REQ_UART4_TX
826 * @arg @ref LL_DMAMUX1_REQ_UART5_RX
827 * @arg @ref LL_DMAMUX1_REQ_UART5_TX
828 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
829 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
830 * @arg @ref LL_DMAMUX1_REQ_TIM6_UP
831 * @arg @ref LL_DMAMUX1_REQ_TIM7_UP
832 * @arg @ref LL_DMAMUX1_REQ_USART6_RX
833 * @arg @ref LL_DMAMUX1_REQ_USART6_TX
834 * @arg @ref LL_DMAMUX1_REQ_I2C3_RX
835 * @arg @ref LL_DMAMUX1_REQ_I2C3_TX
836 * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*)
837 * @arg @ref LL_DMAMUX1_REQ_CRYP_IN
838 * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
839 * @arg @ref LL_DMAMUX1_REQ_HASH_IN
840 * @arg @ref LL_DMAMUX1_REQ_UART7_RX
841 * @arg @ref LL_DMAMUX1_REQ_UART7_TX
842 * @arg @ref LL_DMAMUX1_REQ_UART8_RX
843 * @arg @ref LL_DMAMUX1_REQ_UART8_TX
844 * @arg @ref LL_DMAMUX1_REQ_SPI4_RX
845 * @arg @ref LL_DMAMUX1_REQ_SPI4_TX
846 * @arg @ref LL_DMAMUX1_REQ_SPI5_RX
847 * @arg @ref LL_DMAMUX1_REQ_SPI5_TX
848 * @arg @ref LL_DMAMUX1_REQ_SAI1_A
849 * @arg @ref LL_DMAMUX1_REQ_SAI1_B
850 * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*)
851 * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*)
852 * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
853 * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
854 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
855 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
856 * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
857 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
858 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
859 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
860 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
861 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
862 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
863 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
864 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
865 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
866 * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
867 * @arg @ref LL_DMAMUX1_REQ_TIM15_UP
868 * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
869 * @arg @ref LL_DMAMUX1_REQ_TIM15_COM
870 * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
871 * @arg @ref LL_DMAMUX1_REQ_TIM16_UP
872 * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
873 * @arg @ref LL_DMAMUX1_REQ_TIM17_UP
874 * @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
875 * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
876 * @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
877 * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
878 * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)
879 * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
880 * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)
881 * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*)
882 * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*)
883 * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*)
884 * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*)
885 * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*)
886 * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*)
887 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*)
888 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*)
889 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*)
890 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*)
891 * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*)
892 * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*)
893 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*)
894 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*)
895 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*)
896 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*)
897 * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*)
898 * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*)
899 * @arg @ref LL_DMAMUX2_REQ_MEM2MEM
900 * @arg @ref LL_DMAMUX2_REQ_GENERATOR0
901 * @arg @ref LL_DMAMUX2_REQ_GENERATOR1
902 * @arg @ref LL_DMAMUX2_REQ_GENERATOR2
903 * @arg @ref LL_DMAMUX2_REQ_GENERATOR3
904 * @arg @ref LL_DMAMUX2_REQ_GENERATOR4
905 * @arg @ref LL_DMAMUX2_REQ_GENERATOR5
906 * @arg @ref LL_DMAMUX2_REQ_GENERATOR6
907 * @arg @ref LL_DMAMUX2_REQ_GENERATOR7
908 * @arg @ref LL_DMAMUX2_REQ_LPUART1_RX
909 * @arg @ref LL_DMAMUX2_REQ_LPUART1_TX
910 * @arg @ref LL_DMAMUX2_REQ_SPI6_RX
911 * @arg @ref LL_DMAMUX2_REQ_SPI6_TX
912 * @arg @ref LL_DMAMUX2_REQ_I2C4_RX
913 * @arg @ref LL_DMAMUX2_REQ_I2C4_TX
914 * @arg @ref LL_DMAMUX2_REQ_SAI4_A (*)
915 * @arg @ref LL_DMAMUX2_REQ_SAI4_B (*)
916 * @arg @ref LL_DMAMUX2_REQ_ADC3 (*)
917 * @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*)
918 * @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*)
919 *
920 * @note (*) Availability depends on devices.
921 * @retval None
922 */
923 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
924 {
925 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
926
927 return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
928 }
929
930 /**
931 * @brief Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
932 * @rmtoll CxCR NBREQ LL_DMAMUX_SetSyncRequestNb
933 * @param DMAMUXx DMAMUXx Instance
934 * @param Channel This parameter can be one of the following values:
935 * @arg @ref LL_DMAMUX_CHANNEL_0
936 * @arg @ref LL_DMAMUX_CHANNEL_1
937 * @arg @ref LL_DMAMUX_CHANNEL_2
938 * @arg @ref LL_DMAMUX_CHANNEL_3
939 * @arg @ref LL_DMAMUX_CHANNEL_4
940 * @arg @ref LL_DMAMUX_CHANNEL_5
941 * @arg @ref LL_DMAMUX_CHANNEL_6
942 * @arg @ref LL_DMAMUX_CHANNEL_7
943 * @arg @ref LL_DMAMUX_CHANNEL_8
944 * @arg @ref LL_DMAMUX_CHANNEL_9
945 * @arg @ref LL_DMAMUX_CHANNEL_10
946 * @arg @ref LL_DMAMUX_CHANNEL_11
947 * @arg @ref LL_DMAMUX_CHANNEL_12
948 * @arg @ref LL_DMAMUX_CHANNEL_13
949 * @arg @ref LL_DMAMUX_CHANNEL_14
950 * @arg @ref LL_DMAMUX_CHANNEL_15
951 * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
952 * @retval None
953 */
954 __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
955 {
956 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
957
958 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ, (RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos);
959 }
960
961 /**
962 * @brief Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
963 * @rmtoll CxCR NBREQ LL_DMAMUX_GetSyncRequestNb
964 * @param DMAMUXx DMAMUXx Instance
965 * @param Channel This parameter can be one of the following values:
966 * @arg @ref LL_DMAMUX_CHANNEL_0
967 * @arg @ref LL_DMAMUX_CHANNEL_1
968 * @arg @ref LL_DMAMUX_CHANNEL_2
969 * @arg @ref LL_DMAMUX_CHANNEL_3
970 * @arg @ref LL_DMAMUX_CHANNEL_4
971 * @arg @ref LL_DMAMUX_CHANNEL_5
972 * @arg @ref LL_DMAMUX_CHANNEL_6
973 * @arg @ref LL_DMAMUX_CHANNEL_7
974 * @arg @ref LL_DMAMUX_CHANNEL_8
975 * @arg @ref LL_DMAMUX_CHANNEL_9
976 * @arg @ref LL_DMAMUX_CHANNEL_10
977 * @arg @ref LL_DMAMUX_CHANNEL_11
978 * @arg @ref LL_DMAMUX_CHANNEL_12
979 * @arg @ref LL_DMAMUX_CHANNEL_13
980 * @arg @ref LL_DMAMUX_CHANNEL_14
981 * @arg @ref LL_DMAMUX_CHANNEL_15
982 * @retval Between Min_Data = 1 and Max_Data = 32
983 */
984 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
985 {
986 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
987
988 return (uint32_t)((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ) >> DMAMUX_CxCR_NBREQ_Pos) + 1U);
989 }
990
991 /**
992 * @brief Set the polarity of the signal on which the DMA request is synchronized.
993 * @rmtoll CxCR SPOL LL_DMAMUX_SetSyncPolarity
994 * @param DMAMUXx DMAMUXx Instance
995 * @param Channel This parameter can be one of the following values:
996 * @arg @ref LL_DMAMUX_CHANNEL_0
997 * @arg @ref LL_DMAMUX_CHANNEL_1
998 * @arg @ref LL_DMAMUX_CHANNEL_2
999 * @arg @ref LL_DMAMUX_CHANNEL_3
1000 * @arg @ref LL_DMAMUX_CHANNEL_4
1001 * @arg @ref LL_DMAMUX_CHANNEL_5
1002 * @arg @ref LL_DMAMUX_CHANNEL_6
1003 * @arg @ref LL_DMAMUX_CHANNEL_7
1004 * @arg @ref LL_DMAMUX_CHANNEL_8
1005 * @arg @ref LL_DMAMUX_CHANNEL_9
1006 * @arg @ref LL_DMAMUX_CHANNEL_10
1007 * @arg @ref LL_DMAMUX_CHANNEL_11
1008 * @arg @ref LL_DMAMUX_CHANNEL_12
1009 * @arg @ref LL_DMAMUX_CHANNEL_13
1010 * @arg @ref LL_DMAMUX_CHANNEL_14
1011 * @arg @ref LL_DMAMUX_CHANNEL_15
1012 * @param Polarity This parameter can be one of the following values:
1013 * @arg @ref LL_DMAMUX_SYNC_NO_EVENT
1014 * @arg @ref LL_DMAMUX_SYNC_POL_RISING
1015 * @arg @ref LL_DMAMUX_SYNC_POL_FALLING
1016 * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
1017 * @retval None
1018 */
1019 __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
1020 {
1021 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1022
1023 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL, Polarity);
1024 }
1025
1026 /**
1027 * @brief Get the polarity of the signal on which the DMA request is synchronized.
1028 * @rmtoll CxCR SPOL LL_DMAMUX_GetSyncPolarity
1029 * @param DMAMUXx DMAMUXx Instance
1030 * @param Channel This parameter can be one of the following values:
1031 * @arg @ref LL_DMAMUX_CHANNEL_0
1032 * @arg @ref LL_DMAMUX_CHANNEL_1
1033 * @arg @ref LL_DMAMUX_CHANNEL_2
1034 * @arg @ref LL_DMAMUX_CHANNEL_3
1035 * @arg @ref LL_DMAMUX_CHANNEL_4
1036 * @arg @ref LL_DMAMUX_CHANNEL_5
1037 * @arg @ref LL_DMAMUX_CHANNEL_6
1038 * @arg @ref LL_DMAMUX_CHANNEL_7
1039 * @arg @ref LL_DMAMUX_CHANNEL_8
1040 * @arg @ref LL_DMAMUX_CHANNEL_9
1041 * @arg @ref LL_DMAMUX_CHANNEL_10
1042 * @arg @ref LL_DMAMUX_CHANNEL_11
1043 * @arg @ref LL_DMAMUX_CHANNEL_12
1044 * @arg @ref LL_DMAMUX_CHANNEL_13
1045 * @arg @ref LL_DMAMUX_CHANNEL_14
1046 * @arg @ref LL_DMAMUX_CHANNEL_15
1047 * @retval Returned value can be one of the following values:
1048 * @arg @ref LL_DMAMUX_SYNC_NO_EVENT
1049 * @arg @ref LL_DMAMUX_SYNC_POL_RISING
1050 * @arg @ref LL_DMAMUX_SYNC_POL_FALLING
1051 * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
1052 */
1053 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1054 {
1055 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1056
1057 return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL));
1058 }
1059
1060 /**
1061 * @brief Enable the Event Generation on DMAMUX channel x.
1062 * @rmtoll CxCR EGE LL_DMAMUX_EnableEventGeneration
1063 * @param DMAMUXx DMAMUXx Instance
1064 * @param Channel This parameter can be one of the following values:
1065 * @arg @ref LL_DMAMUX_CHANNEL_0
1066 * @arg @ref LL_DMAMUX_CHANNEL_1
1067 * @arg @ref LL_DMAMUX_CHANNEL_2
1068 * @arg @ref LL_DMAMUX_CHANNEL_3
1069 * @arg @ref LL_DMAMUX_CHANNEL_4
1070 * @arg @ref LL_DMAMUX_CHANNEL_5
1071 * @arg @ref LL_DMAMUX_CHANNEL_6
1072 * @arg @ref LL_DMAMUX_CHANNEL_7
1073 * @arg @ref LL_DMAMUX_CHANNEL_8
1074 * @arg @ref LL_DMAMUX_CHANNEL_9
1075 * @arg @ref LL_DMAMUX_CHANNEL_10
1076 * @arg @ref LL_DMAMUX_CHANNEL_11
1077 * @arg @ref LL_DMAMUX_CHANNEL_12
1078 * @arg @ref LL_DMAMUX_CHANNEL_13
1079 * @arg @ref LL_DMAMUX_CHANNEL_14
1080 * @arg @ref LL_DMAMUX_CHANNEL_15
1081 * @retval None
1082 */
1083 __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1084 {
1085 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1086
1087 SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE);
1088 }
1089
1090 /**
1091 * @brief Disable the Event Generation on DMAMUX channel x.
1092 * @rmtoll CxCR EGE LL_DMAMUX_DisableEventGeneration
1093 * @param DMAMUXx DMAMUXx Instance
1094 * @param Channel This parameter can be one of the following values:
1095 * @arg @ref LL_DMAMUX_CHANNEL_0
1096 * @arg @ref LL_DMAMUX_CHANNEL_1
1097 * @arg @ref LL_DMAMUX_CHANNEL_2
1098 * @arg @ref LL_DMAMUX_CHANNEL_3
1099 * @arg @ref LL_DMAMUX_CHANNEL_4
1100 * @arg @ref LL_DMAMUX_CHANNEL_5
1101 * @arg @ref LL_DMAMUX_CHANNEL_6
1102 * @arg @ref LL_DMAMUX_CHANNEL_7
1103 * @arg @ref LL_DMAMUX_CHANNEL_8
1104 * @arg @ref LL_DMAMUX_CHANNEL_9
1105 * @arg @ref LL_DMAMUX_CHANNEL_10
1106 * @arg @ref LL_DMAMUX_CHANNEL_11
1107 * @arg @ref LL_DMAMUX_CHANNEL_12
1108 * @arg @ref LL_DMAMUX_CHANNEL_13
1109 * @arg @ref LL_DMAMUX_CHANNEL_14
1110 * @arg @ref LL_DMAMUX_CHANNEL_15
1111 * @retval None
1112 */
1113 __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1114 {
1115 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1116
1117 CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE);
1118 }
1119
1120 /**
1121 * @brief Check if the Event Generation on DMAMUX channel x is enabled or disabled.
1122 * @rmtoll CxCR EGE LL_DMAMUX_IsEnabledEventGeneration
1123 * @param DMAMUXx DMAMUXx Instance
1124 * @param Channel This parameter can be one of the following values:
1125 * @arg @ref LL_DMAMUX_CHANNEL_0
1126 * @arg @ref LL_DMAMUX_CHANNEL_1
1127 * @arg @ref LL_DMAMUX_CHANNEL_2
1128 * @arg @ref LL_DMAMUX_CHANNEL_3
1129 * @arg @ref LL_DMAMUX_CHANNEL_4
1130 * @arg @ref LL_DMAMUX_CHANNEL_5
1131 * @arg @ref LL_DMAMUX_CHANNEL_6
1132 * @arg @ref LL_DMAMUX_CHANNEL_7
1133 * @arg @ref LL_DMAMUX_CHANNEL_8
1134 * @arg @ref LL_DMAMUX_CHANNEL_9
1135 * @arg @ref LL_DMAMUX_CHANNEL_10
1136 * @arg @ref LL_DMAMUX_CHANNEL_11
1137 * @arg @ref LL_DMAMUX_CHANNEL_12
1138 * @arg @ref LL_DMAMUX_CHANNEL_13
1139 * @arg @ref LL_DMAMUX_CHANNEL_14
1140 * @arg @ref LL_DMAMUX_CHANNEL_15
1141 * @retval State of bit (1 or 0).
1142 */
1143 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1144 {
1145 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1146
1147 return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL);
1148 }
1149
1150 /**
1151 * @brief Enable the synchronization mode.
1152 * @rmtoll CxCR SE LL_DMAMUX_EnableSync
1153 * @param DMAMUXx DMAMUXx Instance
1154 * @param Channel This parameter can be one of the following values:
1155 * @arg @ref LL_DMAMUX_CHANNEL_0
1156 * @arg @ref LL_DMAMUX_CHANNEL_1
1157 * @arg @ref LL_DMAMUX_CHANNEL_2
1158 * @arg @ref LL_DMAMUX_CHANNEL_3
1159 * @arg @ref LL_DMAMUX_CHANNEL_4
1160 * @arg @ref LL_DMAMUX_CHANNEL_5
1161 * @arg @ref LL_DMAMUX_CHANNEL_6
1162 * @arg @ref LL_DMAMUX_CHANNEL_7
1163 * @arg @ref LL_DMAMUX_CHANNEL_8
1164 * @arg @ref LL_DMAMUX_CHANNEL_9
1165 * @arg @ref LL_DMAMUX_CHANNEL_10
1166 * @arg @ref LL_DMAMUX_CHANNEL_11
1167 * @arg @ref LL_DMAMUX_CHANNEL_12
1168 * @arg @ref LL_DMAMUX_CHANNEL_13
1169 * @arg @ref LL_DMAMUX_CHANNEL_14
1170 * @arg @ref LL_DMAMUX_CHANNEL_15
1171 * @retval None
1172 */
1173 __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1174 {
1175 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1176
1177 SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE);
1178 }
1179
1180 /**
1181 * @brief Disable the synchronization mode.
1182 * @rmtoll CxCR SE LL_DMAMUX_DisableSync
1183 * @param DMAMUXx DMAMUXx Instance
1184 * @param Channel This parameter can be one of the following values:
1185 * @arg @ref LL_DMAMUX_CHANNEL_0
1186 * @arg @ref LL_DMAMUX_CHANNEL_1
1187 * @arg @ref LL_DMAMUX_CHANNEL_2
1188 * @arg @ref LL_DMAMUX_CHANNEL_3
1189 * @arg @ref LL_DMAMUX_CHANNEL_4
1190 * @arg @ref LL_DMAMUX_CHANNEL_5
1191 * @arg @ref LL_DMAMUX_CHANNEL_6
1192 * @arg @ref LL_DMAMUX_CHANNEL_7
1193 * @arg @ref LL_DMAMUX_CHANNEL_8
1194 * @arg @ref LL_DMAMUX_CHANNEL_9
1195 * @arg @ref LL_DMAMUX_CHANNEL_10
1196 * @arg @ref LL_DMAMUX_CHANNEL_11
1197 * @arg @ref LL_DMAMUX_CHANNEL_12
1198 * @arg @ref LL_DMAMUX_CHANNEL_13
1199 * @arg @ref LL_DMAMUX_CHANNEL_14
1200 * @arg @ref LL_DMAMUX_CHANNEL_15
1201 * @retval None
1202 */
1203 __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1204 {
1205 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1206
1207 CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE);
1208 }
1209
1210 /**
1211 * @brief Check if the synchronization mode is enabled or disabled.
1212 * @rmtoll CxCR SE LL_DMAMUX_IsEnabledSync
1213 * @param DMAMUXx DMAMUXx Instance
1214 * @param Channel This parameter can be one of the following values:
1215 * @arg @ref LL_DMAMUX_CHANNEL_0
1216 * @arg @ref LL_DMAMUX_CHANNEL_1
1217 * @arg @ref LL_DMAMUX_CHANNEL_2
1218 * @arg @ref LL_DMAMUX_CHANNEL_3
1219 * @arg @ref LL_DMAMUX_CHANNEL_4
1220 * @arg @ref LL_DMAMUX_CHANNEL_5
1221 * @arg @ref LL_DMAMUX_CHANNEL_6
1222 * @arg @ref LL_DMAMUX_CHANNEL_7
1223 * @arg @ref LL_DMAMUX_CHANNEL_8
1224 * @arg @ref LL_DMAMUX_CHANNEL_9
1225 * @arg @ref LL_DMAMUX_CHANNEL_10
1226 * @arg @ref LL_DMAMUX_CHANNEL_11
1227 * @arg @ref LL_DMAMUX_CHANNEL_12
1228 * @arg @ref LL_DMAMUX_CHANNEL_13
1229 * @arg @ref LL_DMAMUX_CHANNEL_14
1230 * @arg @ref LL_DMAMUX_CHANNEL_15
1231 * @retval State of bit (1 or 0).
1232 */
1233 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1234 {
1235 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1236
1237 return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL);
1238 }
1239
1240 /**
1241 * @brief Set DMAMUX synchronization ID on DMAMUX Channel x.
1242 * @rmtoll CxCR SYNC_ID LL_DMAMUX_SetSyncID
1243 * @param DMAMUXx DMAMUXx Instance
1244 * @param Channel This parameter can be one of the following values:
1245 * @arg @ref LL_DMAMUX_CHANNEL_0
1246 * @arg @ref LL_DMAMUX_CHANNEL_1
1247 * @arg @ref LL_DMAMUX_CHANNEL_2
1248 * @arg @ref LL_DMAMUX_CHANNEL_3
1249 * @arg @ref LL_DMAMUX_CHANNEL_4
1250 * @arg @ref LL_DMAMUX_CHANNEL_5
1251 * @arg @ref LL_DMAMUX_CHANNEL_6
1252 * @arg @ref LL_DMAMUX_CHANNEL_7
1253 * @arg @ref LL_DMAMUX_CHANNEL_8
1254 * @arg @ref LL_DMAMUX_CHANNEL_9
1255 * @arg @ref LL_DMAMUX_CHANNEL_10
1256 * @arg @ref LL_DMAMUX_CHANNEL_11
1257 * @arg @ref LL_DMAMUX_CHANNEL_12
1258 * @arg @ref LL_DMAMUX_CHANNEL_13
1259 * @arg @ref LL_DMAMUX_CHANNEL_14
1260 * @arg @ref LL_DMAMUX_CHANNEL_15
1261 * @param SyncID This parameter can be one of the following values:
1262 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
1263 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
1264 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
1265 * @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT
1266 * @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT
1267 * @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT
1268 * @arg @ref LL_DMAMUX1_SYNC_EXTI0
1269 * @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO
1270 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT
1271 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT
1272 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT
1273 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT
1274 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT
1275 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT
1276 * @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP
1277 * @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP
1278 * @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT
1279 * @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT
1280 * @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP
1281 * @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP
1282 * @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT
1283 * @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP
1284 * @arg @ref LL_DMAMUX2_SYNC_EXTI0
1285 * @arg @ref LL_DMAMUX2_SYNC_EXTI2
1286 * @retval None
1287 */
1288 __STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
1289 {
1290 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1291
1292 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID, SyncID);
1293 }
1294
1295 /**
1296 * @brief Get DMAMUX synchronization ID on DMAMUX Channel x.
1297 * @rmtoll CxCR SYNC_ID LL_DMAMUX_GetSyncID
1298 * @param DMAMUXx DMAMUXx Instance
1299 * @param Channel This parameter can be one of the following values:
1300 * @arg @ref LL_DMAMUX_CHANNEL_0
1301 * @arg @ref LL_DMAMUX_CHANNEL_1
1302 * @arg @ref LL_DMAMUX_CHANNEL_2
1303 * @arg @ref LL_DMAMUX_CHANNEL_3
1304 * @arg @ref LL_DMAMUX_CHANNEL_4
1305 * @arg @ref LL_DMAMUX_CHANNEL_5
1306 * @arg @ref LL_DMAMUX_CHANNEL_6
1307 * @arg @ref LL_DMAMUX_CHANNEL_7
1308 * @arg @ref LL_DMAMUX_CHANNEL_8
1309 * @arg @ref LL_DMAMUX_CHANNEL_9
1310 * @arg @ref LL_DMAMUX_CHANNEL_10
1311 * @arg @ref LL_DMAMUX_CHANNEL_11
1312 * @arg @ref LL_DMAMUX_CHANNEL_12
1313 * @arg @ref LL_DMAMUX_CHANNEL_13
1314 * @arg @ref LL_DMAMUX_CHANNEL_14
1315 * @arg @ref LL_DMAMUX_CHANNEL_15
1316 * @retval Returned value can be one of the following values:
1317 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
1318 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
1319 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
1320 * @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT
1321 * @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT
1322 * @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT
1323 * @arg @ref LL_DMAMUX1_SYNC_EXTI0
1324 * @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO
1325 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT
1326 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT
1327 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT
1328 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT
1329 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT
1330 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT
1331 * @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP
1332 * @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP
1333 * @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT
1334 * @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT
1335 * @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP
1336 * @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP
1337 * @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT
1338 * @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP
1339 * @arg @ref LL_DMAMUX2_SYNC_EXTI0
1340 * @arg @ref LL_DMAMUX2_SYNC_EXTI2
1341 */
1342 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1343 {
1344 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1345
1346 return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID));
1347 }
1348
1349 /**
1350 * @brief Enable the Request Generator.
1351 * @rmtoll RGxCR GE LL_DMAMUX_EnableRequestGen
1352 * @param DMAMUXx DMAMUXx Instance
1353 * @param RequestGenChannel This parameter can be one of the following values:
1354 * @arg @ref LL_DMAMUX_REQ_GEN_0
1355 * @arg @ref LL_DMAMUX_REQ_GEN_1
1356 * @arg @ref LL_DMAMUX_REQ_GEN_2
1357 * @arg @ref LL_DMAMUX_REQ_GEN_3
1358 * @arg @ref LL_DMAMUX_REQ_GEN_4
1359 * @arg @ref LL_DMAMUX_REQ_GEN_5
1360 * @arg @ref LL_DMAMUX_REQ_GEN_6
1361 * @arg @ref LL_DMAMUX_REQ_GEN_7
1362 * @retval None
1363 */
1364 __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1365 {
1366 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1367
1368 SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE);
1369 }
1370
1371 /**
1372 * @brief Disable the Request Generator.
1373 * @rmtoll RGxCR GE LL_DMAMUX_DisableRequestGen
1374 * @param DMAMUXx DMAMUXx Instance
1375 * @param RequestGenChannel This parameter can be one of the following values:
1376 * @arg @ref LL_DMAMUX_REQ_GEN_0
1377 * @arg @ref LL_DMAMUX_REQ_GEN_1
1378 * @arg @ref LL_DMAMUX_REQ_GEN_2
1379 * @arg @ref LL_DMAMUX_REQ_GEN_3
1380 * @retval None
1381 */
1382 __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1383 {
1384 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1385
1386 CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE);
1387 }
1388
1389 /**
1390 * @brief Check if the Request Generator is enabled or disabled.
1391 * @rmtoll RGxCR GE LL_DMAMUX_IsEnabledRequestGen
1392 * @param DMAMUXx DMAMUXx Instance
1393 * @param RequestGenChannel This parameter can be one of the following values:
1394 * @arg @ref LL_DMAMUX_REQ_GEN_0
1395 * @arg @ref LL_DMAMUX_REQ_GEN_1
1396 * @arg @ref LL_DMAMUX_REQ_GEN_2
1397 * @arg @ref LL_DMAMUX_REQ_GEN_3
1398 * @arg @ref LL_DMAMUX_REQ_GEN_4
1399 * @arg @ref LL_DMAMUX_REQ_GEN_5
1400 * @arg @ref LL_DMAMUX_REQ_GEN_6
1401 * @arg @ref LL_DMAMUX_REQ_GEN_7
1402 * @retval State of bit (1 or 0).
1403 */
1404 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1405 {
1406 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1407
1408 return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL);
1409 }
1410
1411 /**
1412 * @brief Set the polarity of the signal on which the DMA request is generated.
1413 * @rmtoll RGxCR GPOL LL_DMAMUX_SetRequestGenPolarity
1414 * @param DMAMUXx DMAMUXx Instance
1415 * @param RequestGenChannel This parameter can be one of the following values:
1416 * @arg @ref LL_DMAMUX_REQ_GEN_0
1417 * @arg @ref LL_DMAMUX_REQ_GEN_1
1418 * @arg @ref LL_DMAMUX_REQ_GEN_2
1419 * @arg @ref LL_DMAMUX_REQ_GEN_3
1420 * @arg @ref LL_DMAMUX_REQ_GEN_4
1421 * @arg @ref LL_DMAMUX_REQ_GEN_5
1422 * @arg @ref LL_DMAMUX_REQ_GEN_6
1423 * @arg @ref LL_DMAMUX_REQ_GEN_7
1424 * @param Polarity This parameter can be one of the following values:
1425 * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
1426 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
1427 * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
1428 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
1429 * @retval None
1430 */
1431 __STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity)
1432 {
1433 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1434
1435 MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL, Polarity);
1436 }
1437
1438 /**
1439 * @brief Get the polarity of the signal on which the DMA request is generated.
1440 * @rmtoll RGxCR GPOL LL_DMAMUX_GetRequestGenPolarity
1441 * @param DMAMUXx DMAMUXx Instance
1442 * @param RequestGenChannel This parameter can be one of the following values:
1443 * @arg @ref LL_DMAMUX_REQ_GEN_0
1444 * @arg @ref LL_DMAMUX_REQ_GEN_1
1445 * @arg @ref LL_DMAMUX_REQ_GEN_2
1446 * @arg @ref LL_DMAMUX_REQ_GEN_3
1447 * @arg @ref LL_DMAMUX_REQ_GEN_4
1448 * @arg @ref LL_DMAMUX_REQ_GEN_5
1449 * @arg @ref LL_DMAMUX_REQ_GEN_6
1450 * @arg @ref LL_DMAMUX_REQ_GEN_7
1451 * @retval Returned value can be one of the following values:
1452 * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
1453 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
1454 * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
1455 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
1456 */
1457 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1458 {
1459 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1460
1461 return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL));
1462 }
1463
1464 /**
1465 * @brief Set the number of DMA request that will be autorized after a generation event.
1466 * @note This field can only be written when Generator is disabled.
1467 * @rmtoll RGxCR GNBREQ LL_DMAMUX_SetGenRequestNb
1468 * @param DMAMUXx DMAMUXx Instance
1469 * @param RequestGenChannel This parameter can be one of the following values:
1470 * @arg @ref LL_DMAMUX_REQ_GEN_0
1471 * @arg @ref LL_DMAMUX_REQ_GEN_1
1472 * @arg @ref LL_DMAMUX_REQ_GEN_2
1473 * @arg @ref LL_DMAMUX_REQ_GEN_3
1474 * @arg @ref LL_DMAMUX_REQ_GEN_4
1475 * @arg @ref LL_DMAMUX_REQ_GEN_5
1476 * @arg @ref LL_DMAMUX_REQ_GEN_6
1477 * @arg @ref LL_DMAMUX_REQ_GEN_7
1478 * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
1479 * @retval None
1480 */
1481 __STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb)
1482 {
1483 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1484
1485 MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos);
1486 }
1487
1488 /**
1489 * @brief Get the number of DMA request that will be autorized after a generation event.
1490 * @rmtoll RGxCR GNBREQ LL_DMAMUX_GetGenRequestNb
1491 * @param DMAMUXx DMAMUXx Instance
1492 * @param RequestGenChannel This parameter can be one of the following values:
1493 * @arg @ref LL_DMAMUX_REQ_GEN_0
1494 * @arg @ref LL_DMAMUX_REQ_GEN_1
1495 * @arg @ref LL_DMAMUX_REQ_GEN_2
1496 * @arg @ref LL_DMAMUX_REQ_GEN_3
1497 * @arg @ref LL_DMAMUX_REQ_GEN_4
1498 * @arg @ref LL_DMAMUX_REQ_GEN_5
1499 * @arg @ref LL_DMAMUX_REQ_GEN_6
1500 * @arg @ref LL_DMAMUX_REQ_GEN_7
1501 * @retval Between Min_Data = 1 and Max_Data = 32
1502 */
1503 __STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1504 {
1505 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1506
1507 return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U);
1508 }
1509
1510 /**
1511 * @brief Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.
1512 * @rmtoll RGxCR SIG_ID LL_DMAMUX_SetRequestSignalID
1513 * @param DMAMUXx DMAMUXx Instance
1514 * @param RequestGenChannel This parameter can be one of the following values:
1515 * @arg @ref LL_DMAMUX_REQ_GEN_0
1516 * @arg @ref LL_DMAMUX_REQ_GEN_1
1517 * @arg @ref LL_DMAMUX_REQ_GEN_2
1518 * @arg @ref LL_DMAMUX_REQ_GEN_3
1519 * @arg @ref LL_DMAMUX_REQ_GEN_4
1520 * @arg @ref LL_DMAMUX_REQ_GEN_5
1521 * @arg @ref LL_DMAMUX_REQ_GEN_6
1522 * @arg @ref LL_DMAMUX_REQ_GEN_7
1523 * @param RequestSignalID This parameter can be one of the following values:
1524 * @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
1525 * @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
1526 * @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
1527 * @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM1_OUT
1528 * @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM2_OUT
1529 * @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM3_OUT
1530 * @arg @ref LL_DMAMUX1_REQ_GEN_EXTI0
1531 * @arg @ref LL_DMAMUX1_REQ_GEN_TIM12_TRGO
1532 * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
1533 * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
1534 * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
1535 * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
1536 * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
1537 * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
1538 * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
1539 * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
1540 * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
1541 * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
1542 * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM2_OUT
1543 * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
1544 * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM3_OUT
1545 * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM4_WKUP (*)
1546 * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM5_WKUP (*)
1547 * @arg @ref LL_DMAMUX2_REQ_GEN_I2C4_WKUP
1548 * @arg @ref LL_DMAMUX2_REQ_GEN_SPI6_WKUP
1549 * @arg @ref LL_DMAMUX2_REQ_GEN_COMP1_OUT
1550 * @arg @ref LL_DMAMUX2_REQ_GEN_COMP2_OUT
1551 * @arg @ref LL_DMAMUX2_REQ_GEN_RTC_WKUP
1552 * @arg @ref LL_DMAMUX2_REQ_GEN_EXTI0
1553 * @arg @ref LL_DMAMUX2_REQ_GEN_EXTI2
1554 * @arg @ref LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
1555 * @arg @ref LL_DMAMUX2_REQ_GEN_SPI6_IT
1556 * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
1557 * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
1558 * @arg @ref LL_DMAMUX2_REQ_GEN_ADC3_IT (*)
1559 * @arg @ref LL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT (*)
1560 * @arg @ref LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
1561 * @arg @ref LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
1562 * @note (*) Availability depends on devices.
1563 * @retval None
1564 */
1565 __STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID)
1566 {
1567 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1568
1569 MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID);
1570 }
1571
1572 /**
1573 * @brief Get DMAMUX external Request Signal ID set on DMAMUX Channel x.
1574 * @rmtoll RGxCR SIG_ID LL_DMAMUX_GetRequestSignalID
1575 * @param DMAMUXx DMAMUXx Instance
1576 * @param RequestGenChannel This parameter can be one of the following values:
1577 * @arg @ref LL_DMAMUX_REQ_GEN_0
1578 * @arg @ref LL_DMAMUX_REQ_GEN_1
1579 * @arg @ref LL_DMAMUX_REQ_GEN_2
1580 * @arg @ref LL_DMAMUX_REQ_GEN_3
1581 * @arg @ref LL_DMAMUX_REQ_GEN_4
1582 * @arg @ref LL_DMAMUX_REQ_GEN_5
1583 * @arg @ref LL_DMAMUX_REQ_GEN_6
1584 * @arg @ref LL_DMAMUX_REQ_GEN_7
1585 * @retval Returned value can be one of the following values:
1586 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
1587 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
1588 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
1589 * @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT
1590 * @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT
1591 * @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT
1592 * @arg @ref LL_DMAMUX1_SYNC_EXTI0
1593 * @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO
1594 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT
1595 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT
1596 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT
1597 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT
1598 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT
1599 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT
1600 * @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP
1601 * @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP
1602 * @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT
1603 * @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT
1604 * @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP
1605 * @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP
1606 * @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT
1607 * @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP
1608 * @arg @ref LL_DMAMUX2_SYNC_EXTI0
1609 * @arg @ref LL_DMAMUX2_SYNC_EXTI2
1610 */
1611 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1612 {
1613 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1614
1615 return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID));
1616 }
1617
1618 /**
1619 * @}
1620 */
1621
1622 /** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management
1623 * @{
1624 */
1625
1626 /**
1627 * @brief Get Synchronization Event Overrun Flag Channel 0.
1628 * @rmtoll CSR SOF0 LL_DMAMUX_IsActiveFlag_SO0
1629 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1630 * @retval State of bit (1 or 0).
1631 */
1632 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
1633 {
1634 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1635
1636 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL);
1637 }
1638
1639 /**
1640 * @brief Get Synchronization Event Overrun Flag Channel 1.
1641 * @rmtoll CSR SOF1 LL_DMAMUX_IsActiveFlag_SO1
1642 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1643 * @retval State of bit (1 or 0).
1644 */
1645 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
1646 {
1647 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1648
1649 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL);
1650 }
1651
1652 /**
1653 * @brief Get Synchronization Event Overrun Flag Channel 2.
1654 * @rmtoll CSR SOF2 LL_DMAMUX_IsActiveFlag_SO2
1655 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1656 * @retval State of bit (1 or 0).
1657 */
1658 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
1659 {
1660 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1661
1662 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL);
1663 }
1664
1665 /**
1666 * @brief Get Synchronization Event Overrun Flag Channel 3.
1667 * @rmtoll CSR SOF3 LL_DMAMUX_IsActiveFlag_SO3
1668 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1669 * @retval State of bit (1 or 0).
1670 */
1671 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
1672 {
1673 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1674
1675 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL);
1676 }
1677
1678 /**
1679 * @brief Get Synchronization Event Overrun Flag Channel 4.
1680 * @rmtoll CSR SOF4 LL_DMAMUX_IsActiveFlag_SO4
1681 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1682 * @retval State of bit (1 or 0).
1683 */
1684 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
1685 {
1686 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1687
1688 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL);
1689 }
1690
1691 /**
1692 * @brief Get Synchronization Event Overrun Flag Channel 5.
1693 * @rmtoll CSR SOF5 LL_DMAMUX_IsActiveFlag_SO5
1694 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1695 * @retval State of bit (1 or 0).
1696 */
1697 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
1698 {
1699 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1700
1701 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL);
1702 }
1703
1704 /**
1705 * @brief Get Synchronization Event Overrun Flag Channel 6.
1706 * @rmtoll CSR SOF6 LL_DMAMUX_IsActiveFlag_SO6
1707 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1708 * @retval State of bit (1 or 0).
1709 */
1710 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
1711 {
1712 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1713
1714 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL);
1715 }
1716
1717 /**
1718 * @brief Get Synchronization Event Overrun Flag Channel 7.
1719 * @rmtoll CSR SOF7 LL_DMAMUX_IsActiveFlag_SO7
1720 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1721 * @retval State of bit (1 or 0).
1722 */
1723 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
1724 {
1725 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1726
1727 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL);
1728 }
1729
1730 /**
1731 * @brief Get Synchronization Event Overrun Flag Channel 8.
1732 * @rmtoll CSR SOF8 LL_DMAMUX_IsActiveFlag_SO8
1733 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1734 * @retval State of bit (1 or 0).
1735 */
1736 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
1737 {
1738 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1739
1740 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL);
1741 }
1742
1743 /**
1744 * @brief Get Synchronization Event Overrun Flag Channel 9.
1745 * @rmtoll CSR SOF9 LL_DMAMUX_IsActiveFlag_SO9
1746 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1747 * @retval State of bit (1 or 0).
1748 */
1749 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
1750 {
1751 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1752
1753 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL);
1754 }
1755
1756 /**
1757 * @brief Get Synchronization Event Overrun Flag Channel 10.
1758 * @rmtoll CSR SOF10 LL_DMAMUX_IsActiveFlag_SO10
1759 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1760 * @retval State of bit (1 or 0).
1761 */
1762 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
1763 {
1764 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1765
1766 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL);
1767 }
1768
1769 /**
1770 * @brief Get Synchronization Event Overrun Flag Channel 11.
1771 * @rmtoll CSR SOF11 LL_DMAMUX_IsActiveFlag_SO11
1772 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1773 * @retval State of bit (1 or 0).
1774 */
1775 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
1776 {
1777 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1778
1779 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL);
1780 }
1781
1782 /**
1783 * @brief Get Synchronization Event Overrun Flag Channel 12.
1784 * @rmtoll CSR SOF12 LL_DMAMUX_IsActiveFlag_SO12
1785 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1786 * @retval State of bit (1 or 0).
1787 */
1788 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
1789 {
1790 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1791
1792 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL);
1793 }
1794
1795 /**
1796 * @brief Get Synchronization Event Overrun Flag Channel 13.
1797 * @rmtoll CSR SOF13 LL_DMAMUX_IsActiveFlag_SO13
1798 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1799 * @retval State of bit (1 or 0).
1800 */
1801 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
1802 {
1803 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1804
1805 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL);
1806 }
1807
1808 /**
1809 * @brief Get Synchronization Event Overrun Flag Channel 14.
1810 * @rmtoll CSR SOF14 LL_DMAMUX_IsActiveFlag_SO14
1811 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1812 * @retval State of bit (1 or 0).
1813 */
1814 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
1815 {
1816 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1817
1818 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF14) == (DMAMUX_CSR_SOF14)) ? 1UL : 0UL);
1819 }
1820
1821 /**
1822 * @brief Get Synchronization Event Overrun Flag Channel 15.
1823 * @rmtoll CSR SOF15 LL_DMAMUX_IsActiveFlag_SO15
1824 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1825 * @retval State of bit (1 or 0).
1826 */
1827 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
1828 {
1829 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1830
1831 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF15) == (DMAMUX_CSR_SOF15)) ? 1UL : 0UL);
1832 }
1833
1834 /**
1835 * @brief Get Request Generator 0 Trigger Event Overrun Flag.
1836 * @rmtoll RGSR OF0 LL_DMAMUX_IsActiveFlag_RGO0
1837 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1838 * @retval State of bit (1 or 0).
1839 */
1840 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
1841 {
1842 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1843
1844 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL);
1845 }
1846
1847 /**
1848 * @brief Get Request Generator 1 Trigger Event Overrun Flag.
1849 * @rmtoll RGSR OF1 LL_DMAMUX_IsActiveFlag_RGO1
1850 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1851 * @retval State of bit (1 or 0).
1852 */
1853 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
1854 {
1855 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1856
1857 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL);
1858 }
1859
1860 /**
1861 * @brief Get Request Generator 2 Trigger Event Overrun Flag.
1862 * @rmtoll RGSR OF2 LL_DMAMUX_IsActiveFlag_RGO2
1863 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1864 * @retval State of bit (1 or 0).
1865 */
1866 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
1867 {
1868 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1869
1870 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL);
1871 }
1872
1873 /**
1874 * @brief Get Request Generator 3 Trigger Event Overrun Flag.
1875 * @rmtoll RGSR OF3 LL_DMAMUX_IsActiveFlag_RGO3
1876 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1877 * @retval State of bit (1 or 0).
1878 */
1879 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
1880 {
1881 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1882
1883 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL);
1884 }
1885
1886 /**
1887 * @brief Get Request Generator 4 Trigger Event Overrun Flag.
1888 * @rmtoll RGSR OF4 LL_DMAMUX_IsActiveFlag_RGO4
1889 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1890 * @retval State of bit (1 or 0).
1891 */
1892 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx)
1893 {
1894 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1895
1896 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF4) == (DMAMUX_RGSR_OF4)) ? 1UL : 0UL);
1897 }
1898
1899 /**
1900 * @brief Get Request Generator 5 Trigger Event Overrun Flag.
1901 * @rmtoll RGSR OF5 LL_DMAMUX_IsActiveFlag_RGO5
1902 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1903 * @retval State of bit (1 or 0).
1904 */
1905 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx)
1906 {
1907 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1908
1909 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF5) == (DMAMUX_RGSR_OF5)) ? 1UL : 0UL);
1910 }
1911
1912 /**
1913 * @brief Get Request Generator 6 Trigger Event Overrun Flag.
1914 * @rmtoll RGSR OF6 LL_DMAMUX_IsActiveFlag_RGO6
1915 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1916 * @retval State of bit (1 or 0).
1917 */
1918 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx)
1919 {
1920 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1921
1922 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF6) == (DMAMUX_RGSR_OF6)) ? 1UL : 0UL);
1923 }
1924
1925 /**
1926 * @brief Get Request Generator 7 Trigger Event Overrun Flag.
1927 * @rmtoll RGSR OF7 LL_DMAMUX_IsActiveFlag_RGO7
1928 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1929 * @retval State of bit (1 or 0).
1930 */
1931 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx)
1932 {
1933 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1934
1935 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF7) == (DMAMUX_RGSR_OF7)) ? 1UL : 0UL);
1936 }
1937
1938 /**
1939 * @brief Clear Synchronization Event Overrun Flag Channel 0.
1940 * @rmtoll CFR CSOF0 LL_DMAMUX_ClearFlag_SO0
1941 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1942 * @retval None
1943 */
1944 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
1945 {
1946 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1947
1948 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF0);
1949 }
1950
1951 /**
1952 * @brief Clear Synchronization Event Overrun Flag Channel 1.
1953 * @rmtoll CFR CSOF1 LL_DMAMUX_ClearFlag_SO1
1954 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1955 * @retval None
1956 */
1957 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
1958 {
1959 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1960
1961 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF1);
1962 }
1963
1964 /**
1965 * @brief Clear Synchronization Event Overrun Flag Channel 2.
1966 * @rmtoll CFR CSOF2 LL_DMAMUX_ClearFlag_SO2
1967 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1968 * @retval None
1969 */
1970 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
1971 {
1972 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1973
1974 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF2);
1975 }
1976
1977 /**
1978 * @brief Clear Synchronization Event Overrun Flag Channel 3.
1979 * @rmtoll CFR CSOF3 LL_DMAMUX_ClearFlag_SO3
1980 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1981 * @retval None
1982 */
1983 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
1984 {
1985 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1986
1987 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF3);
1988 }
1989
1990 /**
1991 * @brief Clear Synchronization Event Overrun Flag Channel 4.
1992 * @rmtoll CFR CSOF4 LL_DMAMUX_ClearFlag_SO4
1993 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1994 * @retval None
1995 */
1996 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
1997 {
1998 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1999
2000 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF4);
2001 }
2002
2003 /**
2004 * @brief Clear Synchronization Event Overrun Flag Channel 5.
2005 * @rmtoll CFR CSOF5 LL_DMAMUX_ClearFlag_SO5
2006 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2007 * @retval None
2008 */
2009 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
2010 {
2011 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2012
2013 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF5);
2014 }
2015
2016 /**
2017 * @brief Clear Synchronization Event Overrun Flag Channel 6.
2018 * @rmtoll CFR CSOF6 LL_DMAMUX_ClearFlag_SO6
2019 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2020 * @retval None
2021 */
2022 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
2023 {
2024 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2025
2026 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF6);
2027 }
2028
2029 /**
2030 * @brief Clear Synchronization Event Overrun Flag Channel 7.
2031 * @rmtoll CFR CSOF7 LL_DMAMUX_ClearFlag_SO7
2032 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2033 * @retval None
2034 */
2035 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
2036 {
2037 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2038
2039 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF7);
2040 }
2041
2042 /**
2043 * @brief Clear Synchronization Event Overrun Flag Channel 8.
2044 * @rmtoll CFR CSOF8 LL_DMAMUX_ClearFlag_SO8
2045 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2046 * @retval None
2047 */
2048 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
2049 {
2050 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2051
2052 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF8);
2053 }
2054
2055 /**
2056 * @brief Clear Synchronization Event Overrun Flag Channel 9.
2057 * @rmtoll CFR CSOF9 LL_DMAMUX_ClearFlag_SO9
2058 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2059 * @retval None
2060 */
2061 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
2062 {
2063 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2064
2065 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF9);
2066 }
2067
2068 /**
2069 * @brief Clear Synchronization Event Overrun Flag Channel 10.
2070 * @rmtoll CFR CSOF10 LL_DMAMUX_ClearFlag_SO10
2071 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2072 * @retval None
2073 */
2074 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
2075 {
2076 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2077
2078 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF10);
2079 }
2080
2081 /**
2082 * @brief Clear Synchronization Event Overrun Flag Channel 11.
2083 * @rmtoll CFR CSOF11 LL_DMAMUX_ClearFlag_SO11
2084 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2085 * @retval None
2086 */
2087 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
2088 {
2089 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2090
2091 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF11);
2092 }
2093
2094 /**
2095 * @brief Clear Synchronization Event Overrun Flag Channel 12.
2096 * @rmtoll CFR CSOF12 LL_DMAMUX_ClearFlag_SO12
2097 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2098 * @retval None
2099 */
2100 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
2101 {
2102 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2103
2104 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF12);
2105 }
2106
2107 /**
2108 * @brief Clear Synchronization Event Overrun Flag Channel 13.
2109 * @rmtoll CFR CSOF13 LL_DMAMUX_ClearFlag_SO13
2110 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2111 * @retval None
2112 */
2113 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
2114 {
2115 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2116
2117 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF13);
2118 }
2119
2120 /**
2121 * @brief Clear Synchronization Event Overrun Flag Channel 14.
2122 * @rmtoll CFR CSOF14 LL_DMAMUX_ClearFlag_SO14
2123 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2124 * @retval None
2125 */
2126 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
2127 {
2128 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2129
2130 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF14);
2131 }
2132
2133 /**
2134 * @brief Clear Synchronization Event Overrun Flag Channel 15.
2135 * @rmtoll CFR CSOF15 LL_DMAMUX_ClearFlag_SO15
2136 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2137 * @retval None
2138 */
2139 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
2140 {
2141 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2142
2143 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF15);
2144 }
2145
2146 /**
2147 * @brief Clear Request Generator 0 Trigger Event Overrun Flag.
2148 * @rmtoll RGCFR COF0 LL_DMAMUX_ClearFlag_RGO0
2149 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2150 * @retval None
2151 */
2152 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
2153 {
2154 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2155
2156 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF0);
2157 }
2158
2159 /**
2160 * @brief Clear Request Generator 1 Trigger Event Overrun Flag.
2161 * @rmtoll RGCFR COF1 LL_DMAMUX_ClearFlag_RGO1
2162 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2163 * @retval None
2164 */
2165 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
2166 {
2167 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2168
2169 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF1);
2170 }
2171
2172 /**
2173 * @brief Clear Request Generator 2 Trigger Event Overrun Flag.
2174 * @rmtoll RGCFR COF2 LL_DMAMUX_ClearFlag_RGO2
2175 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2176 * @retval None
2177 */
2178 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
2179 {
2180 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2181
2182 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF2);
2183 }
2184
2185 /**
2186 * @brief Clear Request Generator 3 Trigger Event Overrun Flag.
2187 * @rmtoll RGCFR COF3 LL_DMAMUX_ClearFlag_RGO3
2188 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2189 * @retval None
2190 */
2191 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
2192 {
2193 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2194
2195 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF3);
2196 }
2197
2198 /**
2199 * @brief Clear Request Generator 4 Trigger Event Overrun Flag.
2200 * @rmtoll RGCFR COF4 LL_DMAMUX_ClearFlag_RGO4
2201 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2202 * @retval None
2203 */
2204 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx)
2205 {
2206 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2207
2208 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF4);
2209 }
2210
2211 /**
2212 * @brief Clear Request Generator 5 Trigger Event Overrun Flag.
2213 * @rmtoll RGCFR COF5 LL_DMAMUX_ClearFlag_RGO5
2214 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2215 * @retval None
2216 */
2217 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx)
2218 {
2219 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2220
2221 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF5);
2222 }
2223
2224 /**
2225 * @brief Clear Request Generator 6 Trigger Event Overrun Flag.
2226 * @rmtoll RGCFR COF6 LL_DMAMUX_ClearFlag_RGO6
2227 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2228 * @retval None
2229 */
2230 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx)
2231 {
2232 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2233
2234 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF6);
2235 }
2236
2237 /**
2238 * @brief Clear Request Generator 7 Trigger Event Overrun Flag.
2239 * @rmtoll RGCFR COF7 LL_DMAMUX_ClearFlag_RGO7
2240 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2241 * @retval None
2242 */
2243 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx)
2244 {
2245 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2246
2247 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF7);
2248 }
2249
2250 /**
2251 * @}
2252 */
2253
2254 /** @defgroup DMAMUX_LL_EF_IT_Management IT_Management
2255 * @{
2256 */
2257
2258 /**
2259 * @brief Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
2260 * @rmtoll CxCR SOIE LL_DMAMUX_EnableIT_SO
2261 * @param DMAMUXx DMAMUXx Instance
2262 * @param Channel This parameter can be one of the following values:
2263 * @arg @ref LL_DMAMUX_CHANNEL_0
2264 * @arg @ref LL_DMAMUX_CHANNEL_1
2265 * @arg @ref LL_DMAMUX_CHANNEL_2
2266 * @arg @ref LL_DMAMUX_CHANNEL_3
2267 * @arg @ref LL_DMAMUX_CHANNEL_4
2268 * @arg @ref LL_DMAMUX_CHANNEL_5
2269 * @arg @ref LL_DMAMUX_CHANNEL_6
2270 * @arg @ref LL_DMAMUX_CHANNEL_7
2271 * @arg @ref LL_DMAMUX_CHANNEL_8
2272 * @arg @ref LL_DMAMUX_CHANNEL_9
2273 * @arg @ref LL_DMAMUX_CHANNEL_10
2274 * @arg @ref LL_DMAMUX_CHANNEL_11
2275 * @arg @ref LL_DMAMUX_CHANNEL_12
2276 * @arg @ref LL_DMAMUX_CHANNEL_13
2277 * @arg @ref LL_DMAMUX_CHANNEL_14
2278 * @arg @ref LL_DMAMUX_CHANNEL_15
2279 * @retval None
2280 */
2281 __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
2282 {
2283 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2284
2285 SET_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE);
2286 }
2287
2288 /**
2289 * @brief Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
2290 * @rmtoll CxCR SOIE LL_DMAMUX_DisableIT_SO
2291 * @param DMAMUXx DMAMUXx Instance
2292 * @param Channel This parameter can be one of the following values:
2293 * @arg @ref LL_DMAMUX_CHANNEL_0
2294 * @arg @ref LL_DMAMUX_CHANNEL_1
2295 * @arg @ref LL_DMAMUX_CHANNEL_2
2296 * @arg @ref LL_DMAMUX_CHANNEL_3
2297 * @arg @ref LL_DMAMUX_CHANNEL_4
2298 * @arg @ref LL_DMAMUX_CHANNEL_5
2299 * @arg @ref LL_DMAMUX_CHANNEL_6
2300 * @arg @ref LL_DMAMUX_CHANNEL_7
2301 * @arg @ref LL_DMAMUX_CHANNEL_8
2302 * @arg @ref LL_DMAMUX_CHANNEL_9
2303 * @arg @ref LL_DMAMUX_CHANNEL_10
2304 * @arg @ref LL_DMAMUX_CHANNEL_11
2305 * @arg @ref LL_DMAMUX_CHANNEL_12
2306 * @arg @ref LL_DMAMUX_CHANNEL_13
2307 * @arg @ref LL_DMAMUX_CHANNEL_14
2308 * @arg @ref LL_DMAMUX_CHANNEL_15
2309 * @retval None
2310 */
2311 __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
2312 {
2313 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2314
2315 CLEAR_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE);
2316 }
2317
2318 /**
2319 * @brief Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
2320 * @rmtoll CxCR SOIE LL_DMAMUX_IsEnabledIT_SO
2321 * @param DMAMUXx DMAMUXx Instance
2322 * @param Channel This parameter can be one of the following values:
2323 * @arg @ref LL_DMAMUX_CHANNEL_0
2324 * @arg @ref LL_DMAMUX_CHANNEL_1
2325 * @arg @ref LL_DMAMUX_CHANNEL_2
2326 * @arg @ref LL_DMAMUX_CHANNEL_3
2327 * @arg @ref LL_DMAMUX_CHANNEL_4
2328 * @arg @ref LL_DMAMUX_CHANNEL_5
2329 * @arg @ref LL_DMAMUX_CHANNEL_6
2330 * @arg @ref LL_DMAMUX_CHANNEL_7
2331 * @arg @ref LL_DMAMUX_CHANNEL_8
2332 * @arg @ref LL_DMAMUX_CHANNEL_9
2333 * @arg @ref LL_DMAMUX_CHANNEL_10
2334 * @arg @ref LL_DMAMUX_CHANNEL_11
2335 * @arg @ref LL_DMAMUX_CHANNEL_12
2336 * @arg @ref LL_DMAMUX_CHANNEL_13
2337 * @arg @ref LL_DMAMUX_CHANNEL_14
2338 * @arg @ref LL_DMAMUX_CHANNEL_15
2339 * @retval State of bit (1 or 0).
2340 */
2341 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
2342 {
2343 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2344
2345 return (READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SOIE));
2346 }
2347
2348 /**
2349 * @brief Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
2350 * @rmtoll RGxCR OIE LL_DMAMUX_EnableIT_RGO
2351 * @param DMAMUXx DMAMUXx Instance
2352 * @param RequestGenChannel This parameter can be one of the following values:
2353 * @arg @ref LL_DMAMUX_REQ_GEN_0
2354 * @arg @ref LL_DMAMUX_REQ_GEN_1
2355 * @arg @ref LL_DMAMUX_REQ_GEN_2
2356 * @arg @ref LL_DMAMUX_REQ_GEN_3
2357 * @arg @ref LL_DMAMUX_REQ_GEN_4
2358 * @arg @ref LL_DMAMUX_REQ_GEN_5
2359 * @arg @ref LL_DMAMUX_REQ_GEN_6
2360 * @arg @ref LL_DMAMUX_REQ_GEN_7
2361 * @retval None
2362 */
2363 __STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
2364 {
2365 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2366
2367 SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE);
2368 }
2369
2370 /**
2371 * @brief Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
2372 * @rmtoll RGxCR OIE LL_DMAMUX_DisableIT_RGO
2373 * @param DMAMUXx DMAMUXx Instance
2374 * @param RequestGenChannel This parameter can be one of the following values:
2375 * @arg @ref LL_DMAMUX_REQ_GEN_0
2376 * @arg @ref LL_DMAMUX_REQ_GEN_1
2377 * @arg @ref LL_DMAMUX_REQ_GEN_2
2378 * @arg @ref LL_DMAMUX_REQ_GEN_3
2379 * @arg @ref LL_DMAMUX_REQ_GEN_4
2380 * @arg @ref LL_DMAMUX_REQ_GEN_5
2381 * @arg @ref LL_DMAMUX_REQ_GEN_6
2382 * @arg @ref LL_DMAMUX_REQ_GEN_7
2383 * @retval None
2384 */
2385 __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
2386 {
2387 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2388
2389 CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE);
2390 }
2391
2392 /**
2393 * @brief Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
2394 * @rmtoll RGxCR OIE LL_DMAMUX_IsEnabledIT_RGO
2395 * @param DMAMUXx DMAMUXx Instance
2396 * @param RequestGenChannel This parameter can be one of the following values:
2397 * @arg @ref LL_DMAMUX_REQ_GEN_0
2398 * @arg @ref LL_DMAMUX_REQ_GEN_1
2399 * @arg @ref LL_DMAMUX_REQ_GEN_2
2400 * @arg @ref LL_DMAMUX_REQ_GEN_3
2401 * @arg @ref LL_DMAMUX_REQ_GEN_4
2402 * @arg @ref LL_DMAMUX_REQ_GEN_5
2403 * @arg @ref LL_DMAMUX_REQ_GEN_6
2404 * @arg @ref LL_DMAMUX_REQ_GEN_7
2405 * @retval State of bit (1 or 0).
2406 */
2407 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
2408 {
2409 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2410
2411 return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL);
2412 }
2413
2414 /**
2415 * @}
2416 */
2417
2418 /**
2419 * @}
2420 */
2421
2422 /**
2423 * @}
2424 */
2425
2426 #endif /* DMAMUX1 || DMAMUX2 */
2427
2428 /**
2429 * @}
2430 */
2431
2432 #ifdef __cplusplus
2433 }
2434 #endif
2435
2436 #endif /* __STM32H7xx_LL_DMAMUX_H */
2437
2438 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/