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Merge pull request #11270 from haslinghuis/rename_attr
[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_ll_fmc.h
blob124f5cdbc83c53f5e2b38783710e97269d7eba5e
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_fmc.h
4 * @author MCD Application Team
5 * @brief Header file of FMC HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_LL_FMC_H
22 #define STM32H7xx_LL_FMC_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx_hal_def.h"
30
31 /** @addtogroup STM32H7xx_HAL_Driver
32 * @{
33 */
34
35 /** @addtogroup FMC_LL
36 * @{
37 */
38
39 /** @addtogroup FMC_LL_Private_Macros
40 * @{
41 */
42
43 #define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \
44 ((__BANK__) == FMC_NORSRAM_BANK2) || \
45 ((__BANK__) == FMC_NORSRAM_BANK3) || \
46 ((__BANK__) == FMC_NORSRAM_BANK4))
47 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
48 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
49 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
50 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
51 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
52 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
53 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
54 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
55 #define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \
56 ((__SIZE__) == FMC_PAGE_SIZE_128) || \
57 ((__SIZE__) == FMC_PAGE_SIZE_256) || \
58 ((__SIZE__) == FMC_PAGE_SIZE_512) || \
59 ((__SIZE__) == FMC_PAGE_SIZE_1024))
60 #define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \
61 ((__FIFO__) == FMC_WRITE_FIFO_ENABLE))
62 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
63 ((__MODE__) == FMC_ACCESS_MODE_B) || \
64 ((__MODE__) == FMC_ACCESS_MODE_C) || \
65 ((__MODE__) == FMC_ACCESS_MODE_D))
66 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
67 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
68 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
69 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
70 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
71 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
72 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
73 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
74 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
75 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
76 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
77 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
78 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
79 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
80 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
81 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
82 ((__BURST__) == FMC_WRITE_BURST_ENABLE))
83 #define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
84 ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
85 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
86 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
87 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
88 #define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U)
89 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
90 #define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
91 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
92 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
93
94
95 #define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3)
96 #define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \
97 ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE))
98 #define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \
99 ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16))
100 #define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \
101 ((__STATE__) == FMC_NAND_ECC_ENABLE))
102
103 #define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
104 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
105 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
106 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
107 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
108 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
109 #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
110 #define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
111 #define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)
112 #define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U)
113 #define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U)
114 #define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U)
115 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
116
117
118 #define IS_FMC_SDMEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \
119 ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
120 ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_32))
121 #define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
122 ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
123 #define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \
124 ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \
125 ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3))
126 #define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \
127 ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE))
128 #define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \
129 ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \
130 ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2))
131 #define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) || \
132 ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) || \
133 ((__COMMAND__) == FMC_SDRAM_CMD_PALL) || \
134 ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
135 ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) || \
136 ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
137 ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE))
138 #define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \
139 ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \
140 ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2))
141 #define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
142 #define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
143 #define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U))
144 #define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
145 #define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U))
146 #define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
147 #define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
148 #define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0U) && ((__NUMBER__) <= 15U))
149 #define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191U)
150 #define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191U)
151 #define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE)
152 #define IS_FMC_SDRAM_BANK(__BANK__) (((__BANK__) == FMC_SDRAM_BANK1) || \
153 ((__BANK__) == FMC_SDRAM_BANK2))
154 #define IS_FMC_COLUMNBITS_NUMBER(__COLUMN__) (((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \
155 ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \
156 ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
157 ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_11))
158 #define IS_FMC_ROWBITS_NUMBER(__ROW__) (((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_11) || \
159 ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_12) || \
160 ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_13))
161 #define IS_FMC_INTERNALBANK_NUMBER(__NUMBER__) (((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
162 ((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_4))
163 #define IS_FMC_CAS_LATENCY(__LATENCY__) (((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_1) || \
164 ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_2) || \
165 ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_3))
166
167
168 /**
169 * @}
170 */
171
172 /* Exported typedef ----------------------------------------------------------*/
173
174 /** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types
175 * @{
176 */
177
178 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
179 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
180 #define FMC_NAND_TypeDef FMC_Bank3_TypeDef
181 #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
182
183 #define FMC_NORSRAM_DEVICE FMC_Bank1_R
184 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R
185 #define FMC_NAND_DEVICE FMC_Bank3_R
186 #define FMC_SDRAM_DEVICE FMC_Bank5_6_R
187
188 /**
189 * @brief FMC NORSRAM Configuration Structure definition
190 */
191 typedef struct
192 {
193 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
194 This parameter can be a value of @ref FMC_NORSRAM_Bank */
195
196 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
197 multiplexed on the data bus or not.
198 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
199
200 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
201 the corresponding memory device.
202 This parameter can be a value of @ref FMC_Memory_Type */
203
204 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
205 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
206
207 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
208 valid only with synchronous burst Flash memories.
209 This parameter can be a value of @ref FMC_Burst_Access_Mode */
210
211 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
212 the Flash memory in burst mode.
213 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
214
215 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
216 clock cycle before the wait state or during the wait state,
217 valid only when accessing memories in burst mode.
218 This parameter can be a value of @ref FMC_Wait_Timing */
219
220 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
221 This parameter can be a value of @ref FMC_Write_Operation */
222
223 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
224 signal, valid for Flash memory access in burst mode.
225 This parameter can be a value of @ref FMC_Wait_Signal */
226
227 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
228 This parameter can be a value of @ref FMC_Extended_Mode */
229
230 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
231 valid only with asynchronous Flash memories.
232 This parameter can be a value of @ref FMC_AsynchronousWait */
233
234 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
235 This parameter can be a value of @ref FMC_Write_Burst */
236
237 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
238 This parameter is only enabled through the FMC_BCR1 register, and don't care
239 through FMC_BCR2..4 registers.
240 This parameter can be a value of @ref FMC_Continous_Clock */
241
242 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
243 This parameter is only enabled through the FMC_BCR1 register, and don't care
244 through FMC_BCR2..4 registers.
245 This parameter can be a value of @ref FMC_Write_FIFO */
246
247 uint32_t PageSize; /*!< Specifies the memory page size.
248 This parameter can be a value of @ref FMC_Page_Size */
249 }FMC_NORSRAM_InitTypeDef;
250
251 /**
252 * @brief FMC NORSRAM Timing parameters structure definition
253 */
254 typedef struct
255 {
256 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
257 the duration of the address setup time.
258 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
259 @note This parameter is not used with synchronous NOR Flash memories. */
260
261 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
262 the duration of the address hold time.
263 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
264 @note This parameter is not used with synchronous NOR Flash memories. */
265
266 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
267 the duration of the data setup time.
268 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
269 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
270 NOR Flash memories. */
271
272 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
273 the duration of the bus turnaround.
274 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
275 @note This parameter is only used for multiplexed NOR Flash memories. */
276
277 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
278 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
279 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
280 accesses. */
281
282 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
283 to the memory before getting the first data.
284 The parameter value depends on the memory type as shown below:
285 - It must be set to 0 in case of a CRAM
286 - It is don't care in asynchronous NOR, SRAM or ROM accesses
287 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
288 with synchronous burst mode enable */
289
290 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
291 This parameter can be a value of @ref FMC_Access_Mode */
292 }FMC_NORSRAM_TimingTypeDef;
293
294 /**
295 * @brief FMC NAND Configuration Structure definition
296 */
297 typedef struct
298 {
299 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
300 This parameter can be a value of @ref FMC_NAND_Bank */
301
302 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
303 This parameter can be any value of @ref FMC_Wait_feature */
304
305 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
306 This parameter can be any value of @ref FMC_NAND_Data_Width */
307
308 uint32_t EccComputation; /*!< Enables or disables the ECC computation.
309 This parameter can be any value of @ref FMC_ECC */
310
311 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
312 This parameter can be any value of @ref FMC_ECC_Page_Size */
313
314 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
315 delay between CLE low and RE low.
316 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
317
318 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
319 delay between ALE low and RE low.
320 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
321 }FMC_NAND_InitTypeDef;
322
323 /**
324 * @brief FMC NAND Timing parameters structure definition
325 */
326 typedef struct
327 {
328 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
329 the command assertion for NAND-Flash read or write access
330 to common/Attribute or I/O memory space (depending on
331 the memory space timing to be configured).
332 This parameter can be a value between Min_Data = 0 and Max_Data = 254 */
333
334 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
335 command for NAND-Flash read or write access to
336 common/Attribute or I/O memory space (depending on the
337 memory space timing to be configured).
338 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
339
340 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
341 (and data for write access) after the command de-assertion
342 for NAND-Flash read or write access to common/Attribute
343 or I/O memory space (depending on the memory space timing
344 to be configured).
345 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
346
347 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
348 data bus is kept in HiZ after the start of a NAND-Flash
349 write access to common/Attribute or I/O memory space (depending
350 on the memory space timing to be configured).
351 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
352 }FMC_NAND_PCC_TimingTypeDef;
353
354
355 /**
356 * @brief FMC SDRAM Configuration Structure definition
357 */
358 typedef struct
359 {
360 uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
361 This parameter can be a value of @ref FMC_SDRAM_Bank */
362
363 uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
364 This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
365
366 uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
367 This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
368
369 uint32_t MemoryDataWidth; /*!< Defines the memory device width.
370 This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
371
372 uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
373 This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
374
375 uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
376 This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
377
378 uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
379 This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
380
381 uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
382 to disable the clock before changing frequency.
383 This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
384
385 uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
386 commands during the CAS latency and stores data in the Read FIFO.
387 This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
388
389 uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
390 This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
391 }FMC_SDRAM_InitTypeDef;
392
393 /**
394 * @brief FMC SDRAM Timing parameters structure definition
395 */
396 typedef struct
397 {
398 uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
399 an active or Refresh command in number of memory clock cycles.
400 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
401
402 uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
403 issuing the Activate command in number of memory clock cycles.
404 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
405
406 uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
407 cycles.
408 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
409
410 uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
411 and the delay between two consecutive Refresh commands in number of
412 memory clock cycles.
413 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
414
415 uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
416 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
417
418 uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
419 in number of memory clock cycles.
420 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
421
422 uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
423 command in number of memory clock cycles.
424 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
425 }FMC_SDRAM_TimingTypeDef;
426
427 /**
428 * @brief SDRAM command parameters structure definition
429 */
430 typedef struct
431 {
432 uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
433 This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
434
435 uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
436 This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
437
438 uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
439 in auto refresh mode.
440 This parameter can be a value between Min_Data = 1 and Max_Data = 15 */
441
442 uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */
443 }FMC_SDRAM_CommandTypeDef;
444 /**
445 * @}
446 */
447
448 /* Exported constants --------------------------------------------------------*/
449 /** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants
450 * @{
451 */
452
453 /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
454 * @{
455 */
456
457 /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
458 * @{
459 */
460 #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
461 #define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
462 #define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
463 #define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
464 /**
465 * @}
466 */
467
468 /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
469 * @{
470 */
471 #define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
472 #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
473 /**
474 * @}
475 */
476
477 /** @defgroup FMC_Memory_Type FMC Memory Type
478 * @{
479 */
480 #define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
481 #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
482 #define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
483 /**
484 * @}
485 */
486
487 /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
488 * @{
489 */
490 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
491 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
492 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
493 /**
494 * @}
495 */
496
497 /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
498 * @{
499 */
500 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
501 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
502 /**
503 * @}
504 */
505
506 /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
507 * @{
508 */
509 #define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
510 #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
511 /**
512 * @}
513 */
514
515 /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
516 * @{
517 */
518 #define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
519 #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
520 /**
521 * @}
522 */
523
524 /** @defgroup FMC_Wait_Timing FMC Wait Timing
525 * @{
526 */
527 #define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
528 #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
529 /**
530 * @}
531 */
532
533 /** @defgroup FMC_Write_Operation FMC Write Operation
534 * @{
535 */
536 #define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
537 #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
538 /**
539 * @}
540 */
541
542 /** @defgroup FMC_Wait_Signal FMC Wait Signal
543 * @{
544 */
545 #define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
546 #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
547 /**
548 * @}
549 */
550
551 /** @defgroup FMC_Extended_Mode FMC Extended Mode
552 * @{
553 */
554 #define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
555 #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
556 /**
557 * @}
558 */
559
560 /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
561 * @{
562 */
563 #define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
564 #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
565 /**
566 * @}
567 */
568
569 /** @defgroup FMC_Page_Size FMC Page Size
570 * @{
571 */
572 #define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000)
573 #define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCRx_CPSIZE_0)
574 #define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCRx_CPSIZE_1)
575 #define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCRx_CPSIZE_0 | FMC_BCRx_CPSIZE_1))
576 #define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCRx_CPSIZE_2)
577 /**
578 * @}
579 */
580
581 /** @defgroup FMC_Write_Burst FMC Write Burst
582 * @{
583 */
584 #define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
585 #define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
586 /**
587 * @}
588 */
589
590 /** @defgroup FMC_Continous_Clock FMC Continuous Clock
591 * @{
592 */
593 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
594 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
595 /**
596 * @}
597 */
598
599 /** @defgroup FMC_Write_FIFO FMC Write FIFO
600 * @{
601 */
602 #define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
603 #define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000)
604 /**
605 * @}
606 */
607
608 /** @defgroup FMC_Access_Mode FMC Access Mode
609 * @{
610 */
611 #define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
612 #define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
613 #define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
614 #define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
615 /**
616 * @}
617 */
618
619 /**
620 * @}
621 */
622
623
624 /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
625 * @{
626 */
627 /** @defgroup FMC_NAND_Bank FMC NAND Bank
628 * @{
629 */
630 #define FMC_NAND_BANK3 ((uint32_t)0x00000100)
631 /**
632 * @}
633 */
634
635 /** @defgroup FMC_Wait_feature FMC Wait feature
636 * @{
637 */
638 #define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
639 #define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
640 /**
641 * @}
642 */
643
644 /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
645 * @{
646 */
647 #define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
648 /**
649 * @}
650 */
651
652 /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
653 * @{
654 */
655 #define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
656 #define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
657 /**
658 * @}
659 */
660
661 /** @defgroup FMC_ECC FMC ECC
662 * @{
663 */
664 #define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
665 #define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
666 /**
667 * @}
668 */
669
670 /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
671 * @{
672 */
673 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
674 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
675 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
676 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
677 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
678 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
679 /**
680 * @}
681 */
682
683 /**
684 * @}
685 */
686
687 /** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
688 * @{
689 */
690 /** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
691 * @{
692 */
693 #define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
694 #define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
695 /**
696 * @}
697 */
698
699 /** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
700 * @{
701 */
702 #define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
703 #define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
704 #define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
705 #define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
706 /**
707 * @}
708 */
709
710 /** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
711 * @{
712 */
713 #define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
714 #define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
715 #define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
716 /**
717 * @}
718 */
719
720 /** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
721 * @{
722 */
723 #define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
724 #define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
725 #define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
726 /**
727 * @}
728 */
729
730 /** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
731 * @{
732 */
733 #define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
734 #define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
735 /**
736 * @}
737 */
738
739 /** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
740 * @{
741 */
742 #define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
743 #define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
744 #define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
745 /**
746 * @}
747 */
748
749 /** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
750 * @{
751 */
752 #define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
753 #define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
754 /**
755 * @}
756 */
757
758 /** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
759 * @{
760 */
761 #define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
762 #define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
763 #define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
764 /**
765 * @}
766 */
767
768 /** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
769 * @{
770 */
771 #define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
772 #define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
773 /**
774 * @}
775 */
776
777 /** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
778 * @{
779 */
780 #define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
781 #define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
782 #define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
783 /**
784 * @}
785 */
786
787 /** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
788 * @{
789 */
790 #define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
791 #define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)
792 #define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)
793 #define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)
794 #define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
795 #define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
796 #define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
797 /**
798 * @}
799 */
800
801 /** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
802 * @{
803 */
804 #define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
805 #define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
806 #define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
807 /**
808 * @}
809 */
810
811 /** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
812 * @{
813 */
814 #define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
815 #define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
816 #define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
817 /**
818 * @}
819 */
820
821 /**
822 * @}
823 */
824
825
826 /** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition
827 * @{
828 */
829 #define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
830 #define FMC_IT_LEVEL ((uint32_t)0x00000010)
831 #define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
832 #define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
833 /**
834 * @}
835 */
836
837 /** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition
838 * @{
839 */
840 #define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
841 #define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
842 #define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
843 #define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
844 #define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
845 #define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
846 #define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
847 /**
848 * @}
849 */
850
851 /**
852 * @}
853 */
854
855 /**
856 * @}
857 */
858
859 /* Private macro -------------------------------------------------------------*/
860 /** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros
861 * @{
862 */
863 /**
864 * @brief Enable the FMC Peripheral.
865 * @retval None
866 */
867 #define __FMC_ENABLE() (FMC_Bank1_R->BTCR[0] |= FMC_BCR1_FMCEN)
868
869 /**
870 * @brief Disable the FMC Peripheral.
871 * @retval None
872 */
873 #define __FMC_DISABLE() (FMC_Bank1_R->BTCR[0] &= ~FMC_BCR1_FMCEN)
874 /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
875 * @brief macros to handle NOR device enable/disable and read/write operations
876 * @{
877 */
878
879 /**
880 * @brief Enable the NORSRAM device access.
881 * @param __INSTANCE__ FMC_NORSRAM Instance
882 * @param __BANK__ FMC_NORSRAM Bank
883 * @retval None
884 */
885 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCRx_MBKEN)
886
887 /**
888 * @brief Disable the NORSRAM device access.
889 * @param __INSTANCE__ FMC_NORSRAM Instance
890 * @param __BANK__ FMC_NORSRAM Bank
891 * @retval None
892 */
893 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCRx_MBKEN)
894
895 /**
896 * @}
897 */
898
899 /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
900 * @brief macros to handle NAND device enable/disable
901 * @{
902 */
903
904 /**
905 * @brief Enable the NAND device access.
906 * @param __INSTANCE__ FMC_NAND Instance
907 * @retval None
908 */
909 #define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
910
911 /**
912 * @brief Disable the NAND device access.
913 * @param __INSTANCE__ FMC_NAND Instance
914 * @param __BANK__ FMC_NAND Bank
915 * @retval None
916 */
917 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN)
918
919 /**
920 * @}
921 */
922
923 /** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt
924 * @brief macros to handle NAND interrupts
925 * @{
926 */
927
928 /**
929 * @brief Enable the NAND device interrupt.
930 * @param __INSTANCE__ FMC_NAND instance
931 * @param __INTERRUPT__ FMC_NAND interrupt
932 * This parameter can be any combination of the following values:
933 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
934 * @arg FMC_IT_LEVEL: Interrupt level.
935 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
936 * @retval None
937 */
938 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__))
939
940 /**
941 * @brief Disable the NAND device interrupt.
942 * @param __INSTANCE__ FMC_NAND Instance
943 * @param __INTERRUPT__ FMC_NAND interrupt
944 * This parameter can be any combination of the following values:
945 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
946 * @arg FMC_IT_LEVEL: Interrupt level.
947 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
948 * @retval None
949 */
950 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
951
952 /**
953 * @brief Get flag status of the NAND device.
954 * @param __INSTANCE__ FMC_NAND Instance
955 * @param __BANK__ FMC_NAND Bank
956 * @param __FLAG__ FMC_NAND flag
957 * This parameter can be any combination of the following values:
958 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
959 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
960 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
961 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
962 * @retval The state of FLAG (SET or RESET).
963 */
964 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
965
966 /**
967 * @brief Clear flag status of the NAND device.
968 * @param __INSTANCE__ FMC_NAND Instance
969 * @param __FLAG__ FMC_NAND flag
970 * This parameter can be any combination of the following values:
971 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
972 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
973 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
974 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
975 * @retval None
976 */
977 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
978
979 /**
980 * @}
981 */
982
983
984 /** @defgroup FMC_LL_SDRAM_Interrupt FMC SDRAM Interrupt
985 * @brief macros to handle SDRAM interrupts
986 * @{
987 */
988
989 /**
990 * @brief Enable the SDRAM device interrupt.
991 * @param __INSTANCE__ FMC_SDRAM instance
992 * @param __INTERRUPT__ FMC_SDRAM interrupt
993 * This parameter can be any combination of the following values:
994 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
995 * @retval None
996 */
997 #define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))
998
999 /**
1000 * @brief Disable the SDRAM device interrupt.
1001 * @param __INSTANCE__ FMC_SDRAM instance
1002 * @param __INTERRUPT__ FMC_SDRAM interrupt
1003 * This parameter can be any combination of the following values:
1004 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
1005 * @retval None
1006 */
1007 #define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
1008
1009 /**
1010 * @brief Get flag status of the SDRAM device.
1011 * @param __INSTANCE__ FMC_SDRAM instance
1012 * @param __FLAG__ FMC_SDRAM flag
1013 * This parameter can be any combination of the following values:
1014 * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
1015 * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
1016 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
1017 * @retval The state of FLAG (SET or RESET).
1018 */
1019 #define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
1020
1021 /**
1022 * @brief Clear flag status of the SDRAM device.
1023 * @param __INSTANCE__ FMC_SDRAM instance
1024 * @param __FLAG__ FMC_SDRAM flag
1025 * This parameter can be any combination of the following values:
1026 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR
1027 * @retval None
1028 */
1029 #define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__))
1030
1031 /**
1032 * @}
1033 */
1034 /**
1035 * @}
1036 */
1037
1038 /**
1039 * @}
1040 */
1041
1042 /* Private functions ---------------------------------------------------------*/
1043 /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
1044 * @{
1045 */
1046
1047 /** @defgroup FMC_LL_NORSRAM NOR SRAM
1048 * @{
1049 */
1050 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
1051 * @{
1052 */
1053 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
1054 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
1055 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
1056 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
1057 /**
1058 * @}
1059 */
1060
1061 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
1062 * @{
1063 */
1064 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1065 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1066 /**
1067 * @}
1068 */
1069 /**
1070 * @}
1071 */
1072
1073 /** @defgroup FMC_LL_NAND NAND
1074 * @{
1075 */
1076 /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
1077 * @{
1078 */
1079 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
1080 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1081 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1082 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
1083 /**
1084 * @}
1085 */
1086
1087 /** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
1088 * @{
1089 */
1090 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1091 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1092 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
1093 /**
1094 * @}
1095 */
1096 /**
1097 * @}
1098 */
1099
1100
1101 /** @defgroup FMC_LL_SDRAM SDRAM
1102 * @{
1103 */
1104 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
1105 * @{
1106 */
1107 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
1108 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
1109 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1110 /**
1111 * @}
1112 */
1113
1114 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
1115 * @{
1116 */
1117 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1118 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1119 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
1120 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
1121 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
1122 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1123 /**
1124 * @}
1125 */
1126 /**
1127 * @}
1128 */
1129
1130 /**
1131 * @}
1132 */
1133
1134 /**
1135 * @}
1136 */
1137
1138 /**
1139 * @}
1140 */
1141
1142 #ifdef __cplusplus
1143 }
1144 #endif
1145
1146 #endif /* STM32H7xx_LL_FMC_H */
1147
1148 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/