lib/main/STM32H7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hsem.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32h7xx_ll_hsem.h
   4   * @author  MCD Application Team
   5   * @brief   Header file of HSEM LL module.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  10   * All rights reserved.</center></h2>
  11   *
  12   * This software component is licensed by ST under BSD 3-Clause license,
  13   * the "License"; You may not use this file except in compliance with the
  14   * License. You may obtain a copy of the License at:
  15   *                        opensource.org/licenses/BSD-3-Clause
  16   *
  17   ******************************************************************************
  18   */
  19
  20 /* Define to prevent recursive inclusion -------------------------------------*/
  21 #ifndef STM32H7xx_LL_HSEM_H
  22 #define STM32H7xx_LL_HSEM_H
  23
  24 #ifdef __cplusplus
  25 extern "C" {
  26 #endif
  27
  28 /* Includes ------------------------------------------------------------------*/
  29 #include "stm32h7xx.h"
  30
  31 /** @addtogroup STM32H7xx_LL_Driver
  32   * @{
  33   */
  34
  35 #if defined(HSEM)
  36
  37 /** @defgroup HSEM_LL HSEM
  38   * @{
  39   */
  40
  41 /* Private types -------------------------------------------------------------*/
  42 /* Private variables ---------------------------------------------------------*/
  43 /* Private constants ---------------------------------------------------------*/
  44 /* Private macros ------------------------------------------------------------*/
  45
  46 /* Exported types ------------------------------------------------------------*/
  47 /* Exported constants --------------------------------------------------------*/
  48
  49 /** @defgroup HSEM_LL_Exported_Constants HSEM Exported Constants
  50   * @{
  51   */
  52
  53 /** @defgroup HSEM_LL_EC_COREID COREID Defines
  54   * @{
  55   */
  56 #define LL_HSEM_COREID_NONE             0U
  57 #define LL_HSEM_COREID_CPU1             HSEM_CR_COREID_CPU1
  58 #if defined(DUAL_CORE)
  59 #define LL_HSEM_COREID_CPU2             HSEM_CR_COREID_CPU2
  60 #endif /* DUAL_CORE */
  61 #define LL_HSEM_COREID                  HSEM_CR_COREID_CURRENT
  62 /**
  63   * @}
  64   */
  65
  66 /** @defgroup HSEM_LL_EC_GET_FLAG Get Flags Defines
  67   * @brief    Flags defines which can be used with LL_HSEM_ReadReg function
  68   * @{
  69   */
  70
  71 #define LL_HSEM_SEMAPHORE_0                HSEM_C1IER_ISE0
  72 #define LL_HSEM_SEMAPHORE_1                HSEM_C1IER_ISE1
  73 #define LL_HSEM_SEMAPHORE_2                HSEM_C1IER_ISE2
  74 #define LL_HSEM_SEMAPHORE_3                HSEM_C1IER_ISE3
  75 #define LL_HSEM_SEMAPHORE_4                HSEM_C1IER_ISE4
  76 #define LL_HSEM_SEMAPHORE_5                HSEM_C1IER_ISE5
  77 #define LL_HSEM_SEMAPHORE_6                HSEM_C1IER_ISE6
  78 #define LL_HSEM_SEMAPHORE_7                HSEM_C1IER_ISE7
  79 #define LL_HSEM_SEMAPHORE_8                HSEM_C1IER_ISE8
  80 #define LL_HSEM_SEMAPHORE_9                HSEM_C1IER_ISE9
  81 #define LL_HSEM_SEMAPHORE_10               HSEM_C1IER_ISE10
  82 #define LL_HSEM_SEMAPHORE_11               HSEM_C1IER_ISE11
  83 #define LL_HSEM_SEMAPHORE_12               HSEM_C1IER_ISE12
  84 #define LL_HSEM_SEMAPHORE_13               HSEM_C1IER_ISE13
  85 #define LL_HSEM_SEMAPHORE_14               HSEM_C1IER_ISE14
  86 #define LL_HSEM_SEMAPHORE_15               HSEM_C1IER_ISE15
  87 #if (HSEM_SEMID_MAX == 15)
  88 #define LL_HSEM_SEMAPHORE_ALL              0x0000FFFFU
  89 #else /* HSEM_SEMID_MAX == 31 */
  90 #define LL_HSEM_SEMAPHORE_16               HSEM_C1IER_ISE16
  91 #define LL_HSEM_SEMAPHORE_17               HSEM_C1IER_ISE17
  92 #define LL_HSEM_SEMAPHORE_18               HSEM_C1IER_ISE18
  93 #define LL_HSEM_SEMAPHORE_19               HSEM_C1IER_ISE19
  94 #define LL_HSEM_SEMAPHORE_20               HSEM_C1IER_ISE20
  95 #define LL_HSEM_SEMAPHORE_21               HSEM_C1IER_ISE21
  96 #define LL_HSEM_SEMAPHORE_22               HSEM_C1IER_ISE22
  97 #define LL_HSEM_SEMAPHORE_23               HSEM_C1IER_ISE23
  98 #define LL_HSEM_SEMAPHORE_24               HSEM_C1IER_ISE24
  99 #define LL_HSEM_SEMAPHORE_25               HSEM_C1IER_ISE25
 100 #define LL_HSEM_SEMAPHORE_26               HSEM_C1IER_ISE26
 101 #define LL_HSEM_SEMAPHORE_27               HSEM_C1IER_ISE27
 102 #define LL_HSEM_SEMAPHORE_28               HSEM_C1IER_ISE28
 103 #define LL_HSEM_SEMAPHORE_29               HSEM_C1IER_ISE29
 104 #define LL_HSEM_SEMAPHORE_30               HSEM_C1IER_ISE30
 105 #define LL_HSEM_SEMAPHORE_31               HSEM_C1IER_ISE31
 106 #define LL_HSEM_SEMAPHORE_ALL              0xFFFFFFFFU
 107 #endif /* HSEM_SEMID_MAX == 15 */
 108 /**
 109   * @}
 110   */
 111
 112 /**
 113   * @}
 114   */
 115
 116 /* Exported macro ------------------------------------------------------------*/
 117 /** @defgroup HSEM_LL_Exported_Macros HSEM Exported Macros
 118   * @{
 119   */
 120
 121 /** @defgroup HSEM_LL_EM_WRITE_READ Common Write and read registers Macros
 122   * @{
 123   */
 124
 125 /**
 126   * @brief  Write a value in HSEM register
 127   * @param  __INSTANCE__ HSEM Instance
 128   * @param  __REG__ Register to be written
 129   * @param  __VALUE__ Value to be written in the register
 130   * @retval None
 131   */
 132 #define LL_HSEM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
 133
 134 /**
 135   * @brief  Read a value in HSEM register
 136   * @param  __INSTANCE__ HSEM Instance
 137   * @param  __REG__ Register to be read
 138   * @retval Register value
 139   */
 140 #define LL_HSEM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
 141 /**
 142   * @}
 143   */
 144
 145 /**
 146   * @}
 147   */
 148
 149 /* Exported functions --------------------------------------------------------*/
 150 /** @defgroup HSEM_LL_Exported_Functions HSEM Exported Functions
 151   * @{
 152   */
 153
 154 /** @defgroup HSEM_LL_EF_Data_Management Data_Management
 155   * @{
 156   */
 157
 158
 159 /**
 160   * @brief  Return 1 if the semaphore is locked, else return 0.
 161   * @rmtoll R            LOCK          LL_HSEM_IsSemaphoreLocked
 162   * @param  HSEMx HSEM Instance.
 163   * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
 164   * @retval State of bit (1 or 0).
 165   */
 166 __STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
 167 {
 168   return ((READ_BIT(HSEMx->R[Semaphore], HSEM_R_LOCK) == (HSEM_R_LOCK_Msk)) ? 1UL : 0UL);
 169 }
 170
 171 /**
 172   * @brief  Get core id.
 173   * @rmtoll R            COREID        LL_HSEM_GetCoreId
 174   * @param  HSEMx HSEM Instance.
 175   * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
 176   * @retval Returned value can be one of the following values:
 177   *         @arg @ref LL_HSEM_COREID_NONE
 178   *         @arg @ref LL_HSEM_COREID_CPU1
 179   *         @arg @ref LL_HSEM_COREID_CPU2
 180   */
 181 __STATIC_INLINE uint32_t LL_HSEM_GetCoreId(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
 182 {
 183   return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_COREID_Msk));
 184 }
 185
 186 /**
 187   * @brief  Get process id.
 188   * @rmtoll R            PROCID        LL_HSEM_GetProcessId
 189   * @param  HSEMx HSEM Instance.
 190   * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
 191   * @retval Process number. Value between Min_Data=0 and Max_Data=255
 192   */
 193 __STATIC_INLINE uint32_t LL_HSEM_GetProcessId(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
 194 {
 195   return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_PROCID_Msk));
 196 }
 197
 198 /**
 199   * @brief  Get the lock by writing in R register.
 200   * @note The R register has to be read to determined if the lock is taken.
 201   * @rmtoll R            LOCK          LL_HSEM_SetLock
 202   * @rmtoll R            COREID        LL_HSEM_SetLock
 203   * @rmtoll R            PROCID        LL_HSEM_SetLock
 204   * @param  HSEMx HSEM Instance.
 205   * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
 206   * @param  process Process id. Value between Min_Data=0 and Max_Data=255
 207   * @retval None
 208   */
 209 __STATIC_INLINE void LL_HSEM_SetLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
 210 {
 211   WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process));
 212 }
 213
 214 /**
 215   * @brief  Get the lock with 2-step lock.
 216   * @rmtoll R            LOCK          LL_HSEM_2StepLock
 217   * @rmtoll R            COREID        LL_HSEM_2StepLock
 218   * @rmtoll R            PROCID        LL_HSEM_2StepLock
 219   * @param  HSEMx HSEM Instance.
 220   * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
 221   * @param  process Process id. Value between Min_Data=0 and Max_Data=255
 222   * @retval 1 lock fail, 0 lock successful or already locked by same process and core
 223   */
 224 __STATIC_INLINE uint32_t LL_HSEM_2StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
 225 {
 226   WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process));
 227   return ((HSEMx->R[Semaphore] != (HSEM_R_LOCK | LL_HSEM_COREID | process)) ? 1UL : 0UL);
 228 }
 229
 230 /**
 231   * @brief  Get the lock with 1-step lock.
 232   * @rmtoll RLR          LOCK          LL_HSEM_1StepLock
 233   * @rmtoll RLR          COREID        LL_HSEM_1StepLock
 234   * @rmtoll RLR          PROCID        LL_HSEM_1StepLock
 235   * @param  HSEMx HSEM Instance.
 236   * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
 237   * @retval 1 lock fail, 0 lock successful or already locked by same core
 238   */
 239 __STATIC_INLINE uint32_t LL_HSEM_1StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
 240 {
 241   return ((HSEMx->RLR[Semaphore] != (HSEM_R_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL);
 242 }
 243
 244 /**
 245   * @brief  Release the lock of the semaphore.
 246   * @note In case of LL_HSEM_1StepLock usage to lock a semaphore, the process is 0.
 247   * @rmtoll R            LOCK          LL_HSEM_ReleaseLock
 248   * @param  HSEMx HSEM Instance.
 249   * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
 250   * @param  process Process number. Value between Min_Data=0 and Max_Data=255
 251   * @retval None
 252   */
 253 __STATIC_INLINE void LL_HSEM_ReleaseLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
 254 {
 255   WRITE_REG(HSEMx->R[Semaphore], (LL_HSEM_COREID | process));
 256 }
 257
 258 /**
 259   * @brief  Get the lock status of the semaphore.
 260   * @rmtoll R            LOCK          LL_HSEM_GetStatus
 261   * @param  HSEMx HSEM Instance.
 262   * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
 263   * @retval 0 semaphore is free, 1 semaphore is locked  */
 264 __STATIC_INLINE uint32_t LL_HSEM_GetStatus(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
 265 {
 266   return ((HSEMx->R[Semaphore] != 0U) ? 1UL : 0UL);
 267 }
 268
 269 /**
 270   * @brief  Set the key.
 271   * @rmtoll KEYR         KEY           LL_HSEM_SetKey
 272   * @param  HSEMx HSEM Instance.
 273   * @param  key Key value.
 274   * @retval None
 275   */
 276 __STATIC_INLINE void LL_HSEM_SetKey(HSEM_TypeDef *HSEMx, uint32_t key)
 277 {
 278   WRITE_REG(HSEMx->KEYR, key << HSEM_KEYR_KEY_Pos);
 279 }
 280
 281 /**
 282   * @brief  Get the key.
 283   * @rmtoll KEYR         KEY           LL_HSEM_GetKey
 284   * @param  HSEMx HSEM Instance.
 285   * @retval key to unlock all semaphore from the same core
 286   */
 287 __STATIC_INLINE uint32_t LL_HSEM_GetKey(HSEM_TypeDef *HSEMx)
 288 {
 289   return (uint32_t)(READ_BIT(HSEMx->KEYR, HSEM_KEYR_KEY) >> HSEM_KEYR_KEY_Pos);
 290 }
 291
 292 /**
 293   * @brief  Release all semaphore with the same core id.
 294   * @rmtoll CR           KEY           LL_HSEM_ResetAllLock
 295   * @param  HSEMx HSEM Instance.
 296   * @param  key Key value.
 297   * @param  core This parameter can be one of the following values:
 298   *         @arg @ref LL_HSEM_COREID_CPU1
 299   *         @arg @ref LL_HSEM_COREID_CPU2
 300   * @retval None
 301   */
 302 __STATIC_INLINE void LL_HSEM_ResetAllLock(HSEM_TypeDef *HSEMx, uint32_t key, uint32_t core)
 303 {
 304   WRITE_REG(HSEMx->CR, (key << HSEM_CR_KEY_Pos) | core);
 305 }
 306
 307 /**
 308   * @}
 309   */
 310
 311 /** @defgroup HSEM_LL_EF_IT_Management IT_Management
 312   * @{
 313   */
 314
 315 /**
 316   * @brief  Enable interrupt.
 317   * @rmtoll C1IER         ISEM          LL_HSEM_EnableIT_C1IER
 318   * @param  HSEMx HSEM Instance.
 319   * @param  SemaphoreMask This parameter can be a combination of the following values:
 320   *         @arg @ref LL_HSEM_SEMAPHORE_0
 321   *         @arg @ref LL_HSEM_SEMAPHORE_1
 322   *         @arg @ref LL_HSEM_SEMAPHORE_2
 323   *         @arg @ref LL_HSEM_SEMAPHORE_3
 324   *         @arg @ref LL_HSEM_SEMAPHORE_4
 325   *         @arg @ref LL_HSEM_SEMAPHORE_5
 326   *         @arg @ref LL_HSEM_SEMAPHORE_6
 327   *         @arg @ref LL_HSEM_SEMAPHORE_7
 328   *         @arg @ref LL_HSEM_SEMAPHORE_8
 329   *         @arg @ref LL_HSEM_SEMAPHORE_9
 330   *         @arg @ref LL_HSEM_SEMAPHORE_10
 331   *         @arg @ref LL_HSEM_SEMAPHORE_11
 332   *         @arg @ref LL_HSEM_SEMAPHORE_12
 333   *         @arg @ref LL_HSEM_SEMAPHORE_13
 334   *         @arg @ref LL_HSEM_SEMAPHORE_14
 335   *         @arg @ref LL_HSEM_SEMAPHORE_15
 336   *         @arg @ref LL_HSEM_SEMAPHORE_16
 337   *         @arg @ref LL_HSEM_SEMAPHORE_17
 338   *         @arg @ref LL_HSEM_SEMAPHORE_18
 339   *         @arg @ref LL_HSEM_SEMAPHORE_19
 340   *         @arg @ref LL_HSEM_SEMAPHORE_20
 341   *         @arg @ref LL_HSEM_SEMAPHORE_21
 342   *         @arg @ref LL_HSEM_SEMAPHORE_22
 343   *         @arg @ref LL_HSEM_SEMAPHORE_23
 344   *         @arg @ref LL_HSEM_SEMAPHORE_24
 345   *         @arg @ref LL_HSEM_SEMAPHORE_25
 346   *         @arg @ref LL_HSEM_SEMAPHORE_26
 347   *         @arg @ref LL_HSEM_SEMAPHORE_27
 348   *         @arg @ref LL_HSEM_SEMAPHORE_28
 349   *         @arg @ref LL_HSEM_SEMAPHORE_29
 350   *         @arg @ref LL_HSEM_SEMAPHORE_30
 351   *         @arg @ref LL_HSEM_SEMAPHORE_31
 352   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
 353   * @note   Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
 354   *         depends on devices.
 355   * @retval None
 356   */
 357 __STATIC_INLINE void LL_HSEM_EnableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
 358 {
 359   SET_BIT(HSEMx->C1IER, SemaphoreMask);
 360 }
 361
 362 /**
 363   * @brief  Disable interrupt.
 364   * @rmtoll C1IER          ISEM          LL_HSEM_DisableIT_C1IER
 365   * @param  HSEMx HSEM Instance.
 366   * @param  SemaphoreMask This parameter can be a combination of the following values:
 367   *         @arg @ref LL_HSEM_SEMAPHORE_0
 368   *         @arg @ref LL_HSEM_SEMAPHORE_1
 369   *         @arg @ref LL_HSEM_SEMAPHORE_2
 370   *         @arg @ref LL_HSEM_SEMAPHORE_3
 371   *         @arg @ref LL_HSEM_SEMAPHORE_4
 372   *         @arg @ref LL_HSEM_SEMAPHORE_5
 373   *         @arg @ref LL_HSEM_SEMAPHORE_6
 374   *         @arg @ref LL_HSEM_SEMAPHORE_7
 375   *         @arg @ref LL_HSEM_SEMAPHORE_8
 376   *         @arg @ref LL_HSEM_SEMAPHORE_9
 377   *         @arg @ref LL_HSEM_SEMAPHORE_10
 378   *         @arg @ref LL_HSEM_SEMAPHORE_11
 379   *         @arg @ref LL_HSEM_SEMAPHORE_12
 380   *         @arg @ref LL_HSEM_SEMAPHORE_13
 381   *         @arg @ref LL_HSEM_SEMAPHORE_14
 382   *         @arg @ref LL_HSEM_SEMAPHORE_15
 383   *         @arg @ref LL_HSEM_SEMAPHORE_16
 384   *         @arg @ref LL_HSEM_SEMAPHORE_17
 385   *         @arg @ref LL_HSEM_SEMAPHORE_18
 386   *         @arg @ref LL_HSEM_SEMAPHORE_19
 387   *         @arg @ref LL_HSEM_SEMAPHORE_20
 388   *         @arg @ref LL_HSEM_SEMAPHORE_21
 389   *         @arg @ref LL_HSEM_SEMAPHORE_22
 390   *         @arg @ref LL_HSEM_SEMAPHORE_23
 391   *         @arg @ref LL_HSEM_SEMAPHORE_24
 392   *         @arg @ref LL_HSEM_SEMAPHORE_25
 393   *         @arg @ref LL_HSEM_SEMAPHORE_26
 394   *         @arg @ref LL_HSEM_SEMAPHORE_27
 395   *         @arg @ref LL_HSEM_SEMAPHORE_28
 396   *         @arg @ref LL_HSEM_SEMAPHORE_29
 397   *         @arg @ref LL_HSEM_SEMAPHORE_30
 398   *         @arg @ref LL_HSEM_SEMAPHORE_31
 399   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
 400   * @note   Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
 401   *         depends on devices.
 402   * @retval None
 403   */
 404 __STATIC_INLINE void LL_HSEM_DisableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
 405 {
 406   CLEAR_BIT(HSEMx->C1IER, SemaphoreMask);
 407 }
 408
 409 /**
 410   * @brief  Check if interrupt is enabled.
 411   * @rmtoll C1IER          ISEM          LL_HSEM_IsEnabledIT_C1IER
 412   * @param  HSEMx HSEM Instance.
 413   * @param  SemaphoreMask This parameter can be a combination of the following values:
 414   *         @arg @ref LL_HSEM_SEMAPHORE_0
 415   *         @arg @ref LL_HSEM_SEMAPHORE_1
 416   *         @arg @ref LL_HSEM_SEMAPHORE_2
 417   *         @arg @ref LL_HSEM_SEMAPHORE_3
 418   *         @arg @ref LL_HSEM_SEMAPHORE_4
 419   *         @arg @ref LL_HSEM_SEMAPHORE_5
 420   *         @arg @ref LL_HSEM_SEMAPHORE_6
 421   *         @arg @ref LL_HSEM_SEMAPHORE_7
 422   *         @arg @ref LL_HSEM_SEMAPHORE_8
 423   *         @arg @ref LL_HSEM_SEMAPHORE_9
 424   *         @arg @ref LL_HSEM_SEMAPHORE_10
 425   *         @arg @ref LL_HSEM_SEMAPHORE_11
 426   *         @arg @ref LL_HSEM_SEMAPHORE_12
 427   *         @arg @ref LL_HSEM_SEMAPHORE_13
 428   *         @arg @ref LL_HSEM_SEMAPHORE_14
 429   *         @arg @ref LL_HSEM_SEMAPHORE_15
 430   *         @arg @ref LL_HSEM_SEMAPHORE_16
 431   *         @arg @ref LL_HSEM_SEMAPHORE_17
 432   *         @arg @ref LL_HSEM_SEMAPHORE_18
 433   *         @arg @ref LL_HSEM_SEMAPHORE_19
 434   *         @arg @ref LL_HSEM_SEMAPHORE_20
 435   *         @arg @ref LL_HSEM_SEMAPHORE_21
 436   *         @arg @ref LL_HSEM_SEMAPHORE_22
 437   *         @arg @ref LL_HSEM_SEMAPHORE_23
 438   *         @arg @ref LL_HSEM_SEMAPHORE_24
 439   *         @arg @ref LL_HSEM_SEMAPHORE_25
 440   *         @arg @ref LL_HSEM_SEMAPHORE_26
 441   *         @arg @ref LL_HSEM_SEMAPHORE_27
 442   *         @arg @ref LL_HSEM_SEMAPHORE_28
 443   *         @arg @ref LL_HSEM_SEMAPHORE_29
 444   *         @arg @ref LL_HSEM_SEMAPHORE_30
 445   *         @arg @ref LL_HSEM_SEMAPHORE_31
 446   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
 447   * @note   Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
 448   *         depends on devices.
 449   * @retval State of bit (1 or 0).
 450   */
 451 __STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
 452 {
 453   return ((READ_BIT(HSEMx->C1IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
 454 }
 455
 456 #if defined(DUAL_CORE)
 457 /**
 458   * @brief  Enable interrupt.
 459   * @rmtoll C2IER         ISEM          LL_HSEM_EnableIT_C2IER
 460   * @param  HSEMx HSEM Instance.
 461   * @param  SemaphoreMask This parameter can be a combination of the following values:
 462   *         @arg @ref LL_HSEM_SEMAPHORE_0
 463   *         @arg @ref LL_HSEM_SEMAPHORE_1
 464   *         @arg @ref LL_HSEM_SEMAPHORE_2
 465   *         @arg @ref LL_HSEM_SEMAPHORE_3
 466   *         @arg @ref LL_HSEM_SEMAPHORE_4
 467   *         @arg @ref LL_HSEM_SEMAPHORE_5
 468   *         @arg @ref LL_HSEM_SEMAPHORE_6
 469   *         @arg @ref LL_HSEM_SEMAPHORE_7
 470   *         @arg @ref LL_HSEM_SEMAPHORE_8
 471   *         @arg @ref LL_HSEM_SEMAPHORE_9
 472   *         @arg @ref LL_HSEM_SEMAPHORE_10
 473   *         @arg @ref LL_HSEM_SEMAPHORE_11
 474   *         @arg @ref LL_HSEM_SEMAPHORE_12
 475   *         @arg @ref LL_HSEM_SEMAPHORE_13
 476   *         @arg @ref LL_HSEM_SEMAPHORE_14
 477   *         @arg @ref LL_HSEM_SEMAPHORE_15
 478   *         @arg @ref LL_HSEM_SEMAPHORE_16
 479   *         @arg @ref LL_HSEM_SEMAPHORE_17
 480   *         @arg @ref LL_HSEM_SEMAPHORE_18
 481   *         @arg @ref LL_HSEM_SEMAPHORE_19
 482   *         @arg @ref LL_HSEM_SEMAPHORE_20
 483   *         @arg @ref LL_HSEM_SEMAPHORE_21
 484   *         @arg @ref LL_HSEM_SEMAPHORE_22
 485   *         @arg @ref LL_HSEM_SEMAPHORE_23
 486   *         @arg @ref LL_HSEM_SEMAPHORE_24
 487   *         @arg @ref LL_HSEM_SEMAPHORE_25
 488   *         @arg @ref LL_HSEM_SEMAPHORE_26
 489   *         @arg @ref LL_HSEM_SEMAPHORE_27
 490   *         @arg @ref LL_HSEM_SEMAPHORE_28
 491   *         @arg @ref LL_HSEM_SEMAPHORE_29
 492   *         @arg @ref LL_HSEM_SEMAPHORE_30
 493   *         @arg @ref LL_HSEM_SEMAPHORE_31
 494   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
 495   * @retval None
 496   */
 497 __STATIC_INLINE void LL_HSEM_EnableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
 498 {
 499   SET_BIT(HSEMx->C2IER, SemaphoreMask);
 500 }
 501
 502 /**
 503   * @brief  Disable interrupt.
 504   * @rmtoll C2IER          ISEM          LL_HSEM_DisableIT_C2IER
 505   * @param  HSEMx HSEM Instance.
 506   * @param  SemaphoreMask This parameter can be a combination of the following values:
 507   *         @arg @ref LL_HSEM_SEMAPHORE_0
 508   *         @arg @ref LL_HSEM_SEMAPHORE_1
 509   *         @arg @ref LL_HSEM_SEMAPHORE_2
 510   *         @arg @ref LL_HSEM_SEMAPHORE_3
 511   *         @arg @ref LL_HSEM_SEMAPHORE_4
 512   *         @arg @ref LL_HSEM_SEMAPHORE_5
 513   *         @arg @ref LL_HSEM_SEMAPHORE_6
 514   *         @arg @ref LL_HSEM_SEMAPHORE_7
 515   *         @arg @ref LL_HSEM_SEMAPHORE_8
 516   *         @arg @ref LL_HSEM_SEMAPHORE_9
 517   *         @arg @ref LL_HSEM_SEMAPHORE_10
 518   *         @arg @ref LL_HSEM_SEMAPHORE_11
 519   *         @arg @ref LL_HSEM_SEMAPHORE_12
 520   *         @arg @ref LL_HSEM_SEMAPHORE_13
 521   *         @arg @ref LL_HSEM_SEMAPHORE_14
 522   *         @arg @ref LL_HSEM_SEMAPHORE_15
 523   *         @arg @ref LL_HSEM_SEMAPHORE_16
 524   *         @arg @ref LL_HSEM_SEMAPHORE_17
 525   *         @arg @ref LL_HSEM_SEMAPHORE_18
 526   *         @arg @ref LL_HSEM_SEMAPHORE_19
 527   *         @arg @ref LL_HSEM_SEMAPHORE_20
 528   *         @arg @ref LL_HSEM_SEMAPHORE_21
 529   *         @arg @ref LL_HSEM_SEMAPHORE_22
 530   *         @arg @ref LL_HSEM_SEMAPHORE_23
 531   *         @arg @ref LL_HSEM_SEMAPHORE_24
 532   *         @arg @ref LL_HSEM_SEMAPHORE_25
 533   *         @arg @ref LL_HSEM_SEMAPHORE_26
 534   *         @arg @ref LL_HSEM_SEMAPHORE_27
 535   *         @arg @ref LL_HSEM_SEMAPHORE_28
 536   *         @arg @ref LL_HSEM_SEMAPHORE_29
 537   *         @arg @ref LL_HSEM_SEMAPHORE_30
 538   *         @arg @ref LL_HSEM_SEMAPHORE_31
 539   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
 540   * @retval None
 541   */
 542 __STATIC_INLINE void LL_HSEM_DisableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
 543 {
 544   CLEAR_BIT(HSEMx->C2IER, SemaphoreMask);
 545 }
 546
 547 /**
 548   * @brief  Check if interrupt is enabled.
 549   * @rmtoll C2IER          ISEM          LL_HSEM_IsEnabledIT_C2IER
 550   * @param  HSEMx HSEM Instance.
 551   * @param  SemaphoreMask This parameter can be a combination of the following values:
 552   *         @arg @ref LL_HSEM_SEMAPHORE_0
 553   *         @arg @ref LL_HSEM_SEMAPHORE_1
 554   *         @arg @ref LL_HSEM_SEMAPHORE_2
 555   *         @arg @ref LL_HSEM_SEMAPHORE_3
 556   *         @arg @ref LL_HSEM_SEMAPHORE_4
 557   *         @arg @ref LL_HSEM_SEMAPHORE_5
 558   *         @arg @ref LL_HSEM_SEMAPHORE_6
 559   *         @arg @ref LL_HSEM_SEMAPHORE_7
 560   *         @arg @ref LL_HSEM_SEMAPHORE_8
 561   *         @arg @ref LL_HSEM_SEMAPHORE_9
 562   *         @arg @ref LL_HSEM_SEMAPHORE_10
 563   *         @arg @ref LL_HSEM_SEMAPHORE_11
 564   *         @arg @ref LL_HSEM_SEMAPHORE_12
 565   *         @arg @ref LL_HSEM_SEMAPHORE_13
 566   *         @arg @ref LL_HSEM_SEMAPHORE_14
 567   *         @arg @ref LL_HSEM_SEMAPHORE_15
 568   *         @arg @ref LL_HSEM_SEMAPHORE_16
 569   *         @arg @ref LL_HSEM_SEMAPHORE_17
 570   *         @arg @ref LL_HSEM_SEMAPHORE_18
 571   *         @arg @ref LL_HSEM_SEMAPHORE_19
 572   *         @arg @ref LL_HSEM_SEMAPHORE_20
 573   *         @arg @ref LL_HSEM_SEMAPHORE_21
 574   *         @arg @ref LL_HSEM_SEMAPHORE_22
 575   *         @arg @ref LL_HSEM_SEMAPHORE_23
 576   *         @arg @ref LL_HSEM_SEMAPHORE_24
 577   *         @arg @ref LL_HSEM_SEMAPHORE_25
 578   *         @arg @ref LL_HSEM_SEMAPHORE_26
 579   *         @arg @ref LL_HSEM_SEMAPHORE_27
 580   *         @arg @ref LL_HSEM_SEMAPHORE_28
 581   *         @arg @ref LL_HSEM_SEMAPHORE_29
 582   *         @arg @ref LL_HSEM_SEMAPHORE_30
 583   *         @arg @ref LL_HSEM_SEMAPHORE_31
 584   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
 585   * @retval State of bit (1 or 0).
 586   */
 587 __STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
 588 {
 589   return ((READ_BIT(HSEMx->C2IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
 590 }
 591 #endif /* DUAL_CORE */
 592
 593 /**
 594   * @}
 595   */
 596
 597 /** @defgroup HSEM_LL_EF_FLAG_Management FLAG_Management
 598   * @{
 599   */
 600
 601 /**
 602   * @brief  Clear interrupt status.
 603   * @rmtoll C1ICR         ISEM          LL_HSEM_ClearFlag_C1ICR
 604   * @param  HSEMx HSEM Instance.
 605   * @param  SemaphoreMask This parameter can be a combination of the following values:
 606   *         @arg @ref LL_HSEM_SEMAPHORE_0
 607   *         @arg @ref LL_HSEM_SEMAPHORE_1
 608   *         @arg @ref LL_HSEM_SEMAPHORE_2
 609   *         @arg @ref LL_HSEM_SEMAPHORE_3
 610   *         @arg @ref LL_HSEM_SEMAPHORE_4
 611   *         @arg @ref LL_HSEM_SEMAPHORE_5
 612   *         @arg @ref LL_HSEM_SEMAPHORE_6
 613   *         @arg @ref LL_HSEM_SEMAPHORE_7
 614   *         @arg @ref LL_HSEM_SEMAPHORE_8
 615   *         @arg @ref LL_HSEM_SEMAPHORE_9
 616   *         @arg @ref LL_HSEM_SEMAPHORE_10
 617   *         @arg @ref LL_HSEM_SEMAPHORE_11
 618   *         @arg @ref LL_HSEM_SEMAPHORE_12
 619   *         @arg @ref LL_HSEM_SEMAPHORE_13
 620   *         @arg @ref LL_HSEM_SEMAPHORE_14
 621   *         @arg @ref LL_HSEM_SEMAPHORE_15
 622   *         @arg @ref LL_HSEM_SEMAPHORE_16
 623   *         @arg @ref LL_HSEM_SEMAPHORE_17
 624   *         @arg @ref LL_HSEM_SEMAPHORE_18
 625   *         @arg @ref LL_HSEM_SEMAPHORE_19
 626   *         @arg @ref LL_HSEM_SEMAPHORE_20
 627   *         @arg @ref LL_HSEM_SEMAPHORE_21
 628   *         @arg @ref LL_HSEM_SEMAPHORE_22
 629   *         @arg @ref LL_HSEM_SEMAPHORE_23
 630   *         @arg @ref LL_HSEM_SEMAPHORE_24
 631   *         @arg @ref LL_HSEM_SEMAPHORE_25
 632   *         @arg @ref LL_HSEM_SEMAPHORE_26
 633   *         @arg @ref LL_HSEM_SEMAPHORE_27
 634   *         @arg @ref LL_HSEM_SEMAPHORE_28
 635   *         @arg @ref LL_HSEM_SEMAPHORE_29
 636   *         @arg @ref LL_HSEM_SEMAPHORE_30
 637   *         @arg @ref LL_HSEM_SEMAPHORE_31
 638   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
 639   * @note   Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
 640   *         depends on devices.
 641   * @retval None
 642   */
 643 __STATIC_INLINE void LL_HSEM_ClearFlag_C1ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
 644 {
 645   WRITE_REG(HSEMx->C1ICR, SemaphoreMask);
 646 }
 647
 648 /**
 649   * @brief  Get interrupt status from ISR register.
 650   * @rmtoll C1ISR         ISEM          LL_HSEM_IsActiveFlag_C1ISR
 651   * @param  HSEMx HSEM Instance.
 652   * @param  SemaphoreMask This parameter can be a combination of the following values:
 653   *         @arg @ref LL_HSEM_SEMAPHORE_0
 654   *         @arg @ref LL_HSEM_SEMAPHORE_1
 655   *         @arg @ref LL_HSEM_SEMAPHORE_2
 656   *         @arg @ref LL_HSEM_SEMAPHORE_3
 657   *         @arg @ref LL_HSEM_SEMAPHORE_4
 658   *         @arg @ref LL_HSEM_SEMAPHORE_5
 659   *         @arg @ref LL_HSEM_SEMAPHORE_6
 660   *         @arg @ref LL_HSEM_SEMAPHORE_7
 661   *         @arg @ref LL_HSEM_SEMAPHORE_8
 662   *         @arg @ref LL_HSEM_SEMAPHORE_9
 663   *         @arg @ref LL_HSEM_SEMAPHORE_10
 664   *         @arg @ref LL_HSEM_SEMAPHORE_11
 665   *         @arg @ref LL_HSEM_SEMAPHORE_12
 666   *         @arg @ref LL_HSEM_SEMAPHORE_13
 667   *         @arg @ref LL_HSEM_SEMAPHORE_14
 668   *         @arg @ref LL_HSEM_SEMAPHORE_15
 669   *         @arg @ref LL_HSEM_SEMAPHORE_16
 670   *         @arg @ref LL_HSEM_SEMAPHORE_17
 671   *         @arg @ref LL_HSEM_SEMAPHORE_18
 672   *         @arg @ref LL_HSEM_SEMAPHORE_19
 673   *         @arg @ref LL_HSEM_SEMAPHORE_20
 674   *         @arg @ref LL_HSEM_SEMAPHORE_21
 675   *         @arg @ref LL_HSEM_SEMAPHORE_22
 676   *         @arg @ref LL_HSEM_SEMAPHORE_23
 677   *         @arg @ref LL_HSEM_SEMAPHORE_24
 678   *         @arg @ref LL_HSEM_SEMAPHORE_25
 679   *         @arg @ref LL_HSEM_SEMAPHORE_26
 680   *         @arg @ref LL_HSEM_SEMAPHORE_27
 681   *         @arg @ref LL_HSEM_SEMAPHORE_28
 682   *         @arg @ref LL_HSEM_SEMAPHORE_29
 683   *         @arg @ref LL_HSEM_SEMAPHORE_30
 684   *         @arg @ref LL_HSEM_SEMAPHORE_31
 685   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
 686   * @note   Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
 687   *         depends on devices.
 688   * @retval State of bit (1 or 0).
 689   */
 690 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
 691 {
 692   return ((READ_BIT(HSEMx->C1ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
 693 }
 694
 695 /**
 696   * @brief  Get interrupt status from MISR register.
 697   * @rmtoll C1MISR        ISEM          LL_HSEM_IsActiveFlag_C1MISR
 698   * @param  HSEMx HSEM Instance.
 699   * @param  SemaphoreMask This parameter can be a combination of the following values:
 700   *         @arg @ref LL_HSEM_SEMAPHORE_0
 701   *         @arg @ref LL_HSEM_SEMAPHORE_1
 702   *         @arg @ref LL_HSEM_SEMAPHORE_2
 703   *         @arg @ref LL_HSEM_SEMAPHORE_3
 704   *         @arg @ref LL_HSEM_SEMAPHORE_4
 705   *         @arg @ref LL_HSEM_SEMAPHORE_5
 706   *         @arg @ref LL_HSEM_SEMAPHORE_6
 707   *         @arg @ref LL_HSEM_SEMAPHORE_7
 708   *         @arg @ref LL_HSEM_SEMAPHORE_8
 709   *         @arg @ref LL_HSEM_SEMAPHORE_9
 710   *         @arg @ref LL_HSEM_SEMAPHORE_10
 711   *         @arg @ref LL_HSEM_SEMAPHORE_11
 712   *         @arg @ref LL_HSEM_SEMAPHORE_12
 713   *         @arg @ref LL_HSEM_SEMAPHORE_13
 714   *         @arg @ref LL_HSEM_SEMAPHORE_14
 715   *         @arg @ref LL_HSEM_SEMAPHORE_15
 716   *         @arg @ref LL_HSEM_SEMAPHORE_16
 717   *         @arg @ref LL_HSEM_SEMAPHORE_17
 718   *         @arg @ref LL_HSEM_SEMAPHORE_18
 719   *         @arg @ref LL_HSEM_SEMAPHORE_19
 720   *         @arg @ref LL_HSEM_SEMAPHORE_20
 721   *         @arg @ref LL_HSEM_SEMAPHORE_21
 722   *         @arg @ref LL_HSEM_SEMAPHORE_22
 723   *         @arg @ref LL_HSEM_SEMAPHORE_23
 724   *         @arg @ref LL_HSEM_SEMAPHORE_24
 725   *         @arg @ref LL_HSEM_SEMAPHORE_25
 726   *         @arg @ref LL_HSEM_SEMAPHORE_26
 727   *         @arg @ref LL_HSEM_SEMAPHORE_27
 728   *         @arg @ref LL_HSEM_SEMAPHORE_28
 729   *         @arg @ref LL_HSEM_SEMAPHORE_29
 730   *         @arg @ref LL_HSEM_SEMAPHORE_30
 731   *         @arg @ref LL_HSEM_SEMAPHORE_31
 732   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
 733   * @note   Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
 734   *         depends on devices.
 735   * @retval State of bit (1 or 0).
 736   */
 737 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
 738 {
 739   return ((READ_BIT(HSEMx->C1MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
 740 }
 741
 742 #if defined(DUAL_CORE)
 743 /**
 744   * @brief  Clear interrupt status.
 745   * @rmtoll C2ICR         ISEM          LL_HSEM_ClearFlag_C2ICR
 746   * @param  HSEMx HSEM Instance.
 747   * @param  SemaphoreMask This parameter can be a combination of the following values:
 748   *         @arg @ref LL_HSEM_SEMAPHORE_0
 749   *         @arg @ref LL_HSEM_SEMAPHORE_1
 750   *         @arg @ref LL_HSEM_SEMAPHORE_2
 751   *         @arg @ref LL_HSEM_SEMAPHORE_3
 752   *         @arg @ref LL_HSEM_SEMAPHORE_4
 753   *         @arg @ref LL_HSEM_SEMAPHORE_5
 754   *         @arg @ref LL_HSEM_SEMAPHORE_6
 755   *         @arg @ref LL_HSEM_SEMAPHORE_7
 756   *         @arg @ref LL_HSEM_SEMAPHORE_8
 757   *         @arg @ref LL_HSEM_SEMAPHORE_9
 758   *         @arg @ref LL_HSEM_SEMAPHORE_10
 759   *         @arg @ref LL_HSEM_SEMAPHORE_11
 760   *         @arg @ref LL_HSEM_SEMAPHORE_12
 761   *         @arg @ref LL_HSEM_SEMAPHORE_13
 762   *         @arg @ref LL_HSEM_SEMAPHORE_14
 763   *         @arg @ref LL_HSEM_SEMAPHORE_15
 764   *         @arg @ref LL_HSEM_SEMAPHORE_16
 765   *         @arg @ref LL_HSEM_SEMAPHORE_17
 766   *         @arg @ref LL_HSEM_SEMAPHORE_18
 767   *         @arg @ref LL_HSEM_SEMAPHORE_19
 768   *         @arg @ref LL_HSEM_SEMAPHORE_20
 769   *         @arg @ref LL_HSEM_SEMAPHORE_21
 770   *         @arg @ref LL_HSEM_SEMAPHORE_22
 771   *         @arg @ref LL_HSEM_SEMAPHORE_23
 772   *         @arg @ref LL_HSEM_SEMAPHORE_24
 773   *         @arg @ref LL_HSEM_SEMAPHORE_25
 774   *         @arg @ref LL_HSEM_SEMAPHORE_26
 775   *         @arg @ref LL_HSEM_SEMAPHORE_27
 776   *         @arg @ref LL_HSEM_SEMAPHORE_28
 777   *         @arg @ref LL_HSEM_SEMAPHORE_29
 778   *         @arg @ref LL_HSEM_SEMAPHORE_30
 779   *         @arg @ref LL_HSEM_SEMAPHORE_31
 780   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
 781   * @retval None
 782   */
 783 __STATIC_INLINE void LL_HSEM_ClearFlag_C2ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
 784 {
 785   WRITE_REG(HSEMx->C2ICR, SemaphoreMask);
 786 }
 787
 788 /**
 789   * @brief  Get interrupt status from ISR register.
 790   * @rmtoll C2ISR         ISEM          LL_HSEM_IsActiveFlag_C2ISR
 791   * @param  HSEMx HSEM Instance.
 792   * @param  SemaphoreMask This parameter can be a combination of the following values:
 793   *         @arg @ref LL_HSEM_SEMAPHORE_0
 794   *         @arg @ref LL_HSEM_SEMAPHORE_1
 795   *         @arg @ref LL_HSEM_SEMAPHORE_2
 796   *         @arg @ref LL_HSEM_SEMAPHORE_3
 797   *         @arg @ref LL_HSEM_SEMAPHORE_4
 798   *         @arg @ref LL_HSEM_SEMAPHORE_5
 799   *         @arg @ref LL_HSEM_SEMAPHORE_6
 800   *         @arg @ref LL_HSEM_SEMAPHORE_7
 801   *         @arg @ref LL_HSEM_SEMAPHORE_8
 802   *         @arg @ref LL_HSEM_SEMAPHORE_9
 803   *         @arg @ref LL_HSEM_SEMAPHORE_10
 804   *         @arg @ref LL_HSEM_SEMAPHORE_11
 805   *         @arg @ref LL_HSEM_SEMAPHORE_12
 806   *         @arg @ref LL_HSEM_SEMAPHORE_13
 807   *         @arg @ref LL_HSEM_SEMAPHORE_14
 808   *         @arg @ref LL_HSEM_SEMAPHORE_15
 809   *         @arg @ref LL_HSEM_SEMAPHORE_16
 810   *         @arg @ref LL_HSEM_SEMAPHORE_17
 811   *         @arg @ref LL_HSEM_SEMAPHORE_18
 812   *         @arg @ref LL_HSEM_SEMAPHORE_19
 813   *         @arg @ref LL_HSEM_SEMAPHORE_20
 814   *         @arg @ref LL_HSEM_SEMAPHORE_21
 815   *         @arg @ref LL_HSEM_SEMAPHORE_22
 816   *         @arg @ref LL_HSEM_SEMAPHORE_23
 817   *         @arg @ref LL_HSEM_SEMAPHORE_24
 818   *         @arg @ref LL_HSEM_SEMAPHORE_25
 819   *         @arg @ref LL_HSEM_SEMAPHORE_26
 820   *         @arg @ref LL_HSEM_SEMAPHORE_27
 821   *         @arg @ref LL_HSEM_SEMAPHORE_28
 822   *         @arg @ref LL_HSEM_SEMAPHORE_29
 823   *         @arg @ref LL_HSEM_SEMAPHORE_30
 824   *         @arg @ref LL_HSEM_SEMAPHORE_31
 825   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
 826   * @retval State of bit (1 or 0).
 827   */
 828 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
 829 {
 830   return ((READ_BIT(HSEMx->C2ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
 831 }
 832
 833 /**
 834   * @brief  Get interrupt status from MISR register.
 835   * @rmtoll C2MISR        ISEM          LL_HSEM_IsActiveFlag_C2MISR
 836   * @param  HSEMx HSEM Instance.
 837   * @param  SemaphoreMask This parameter can be a combination of the following values:
 838   *         @arg @ref LL_HSEM_SEMAPHORE_0
 839   *         @arg @ref LL_HSEM_SEMAPHORE_1
 840   *         @arg @ref LL_HSEM_SEMAPHORE_2
 841   *         @arg @ref LL_HSEM_SEMAPHORE_3
 842   *         @arg @ref LL_HSEM_SEMAPHORE_4
 843   *         @arg @ref LL_HSEM_SEMAPHORE_5
 844   *         @arg @ref LL_HSEM_SEMAPHORE_6
 845   *         @arg @ref LL_HSEM_SEMAPHORE_7
 846   *         @arg @ref LL_HSEM_SEMAPHORE_8
 847   *         @arg @ref LL_HSEM_SEMAPHORE_9
 848   *         @arg @ref LL_HSEM_SEMAPHORE_10
 849   *         @arg @ref LL_HSEM_SEMAPHORE_11
 850   *         @arg @ref LL_HSEM_SEMAPHORE_12
 851   *         @arg @ref LL_HSEM_SEMAPHORE_13
 852   *         @arg @ref LL_HSEM_SEMAPHORE_14
 853   *         @arg @ref LL_HSEM_SEMAPHORE_15
 854   *         @arg @ref LL_HSEM_SEMAPHORE_16
 855   *         @arg @ref LL_HSEM_SEMAPHORE_17
 856   *         @arg @ref LL_HSEM_SEMAPHORE_18
 857   *         @arg @ref LL_HSEM_SEMAPHORE_19
 858   *         @arg @ref LL_HSEM_SEMAPHORE_20
 859   *         @arg @ref LL_HSEM_SEMAPHORE_21
 860   *         @arg @ref LL_HSEM_SEMAPHORE_22
 861   *         @arg @ref LL_HSEM_SEMAPHORE_23
 862   *         @arg @ref LL_HSEM_SEMAPHORE_24
 863   *         @arg @ref LL_HSEM_SEMAPHORE_25
 864   *         @arg @ref LL_HSEM_SEMAPHORE_26
 865   *         @arg @ref LL_HSEM_SEMAPHORE_27
 866   *         @arg @ref LL_HSEM_SEMAPHORE_28
 867   *         @arg @ref LL_HSEM_SEMAPHORE_29
 868   *         @arg @ref LL_HSEM_SEMAPHORE_30
 869   *         @arg @ref LL_HSEM_SEMAPHORE_31
 870   *         @arg @ref LL_HSEM_SEMAPHORE_ALL
 871   * @retval State of bit (1 or 0).
 872   */
 873 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
 874 {
 875   return ((READ_BIT(HSEMx->C2MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
 876 }
 877 #endif /* DUAL_CORE */
 878 /**
 879   * @}
 880   */
 881
 882 /**
 883   * @}
 884   */
 885
 886 /**
 887   * @}
 888   */
 889
 890 #endif /* defined(HSEM) */
 891
 892 /**
 893   * @}
 894   */
 895
 896 #ifdef __cplusplus
 897 }
 898 #endif
 899
 900 #endif /* __STM32H7xx_LL_HSEM_H */
 901
 902 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/