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Merge pull request #11270 from haslinghuis/rename_attr
[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_ll_i2c.h
blobd91b7c2f7e1299b92adad421092022509e205977
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_i2c.h
4 * @author MCD Application Team
5 * @brief Header file of I2C LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_LL_I2C_H
22 #define STM32H7xx_LL_I2C_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx.h"
30
31 /** @addtogroup STM32H7xx_LL_Driver
32 * @{
33 */
34
35 #if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4) || defined (I2C5)
36
37 /** @defgroup I2C_LL I2C
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45 /** @defgroup I2C_LL_Private_Constants I2C Private Constants
46 * @{
47 */
48 /**
49 * @}
50 */
51
52 /* Private macros ------------------------------------------------------------*/
53 #if defined(USE_FULL_LL_DRIVER)
54 /** @defgroup I2C_LL_Private_Macros I2C Private Macros
55 * @{
56 */
57 /**
58 * @}
59 */
60 #endif /*USE_FULL_LL_DRIVER*/
61
62 /* Exported types ------------------------------------------------------------*/
63 #if defined(USE_FULL_LL_DRIVER)
64 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
65 * @{
66 */
67 typedef struct
68 {
69 uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
70 This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE.
71
72 This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
73
74 uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
75 This parameter must be set by referring to the STM32CubeMX Tool and
76 the helper macro @ref __LL_I2C_CONVERT_TIMINGS().
77
78 This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */
79
80 uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
81 This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION.
82
83 This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
84
85 uint32_t DigitalFilter; /*!< Configures the digital noise filter.
86 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
87
88 This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
89
90 uint32_t OwnAddress1; /*!< Specifies the device own address 1.
91 This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
92
93 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
94
95 uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
96 This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE.
97
98 This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
99
100 uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
101 This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1.
102
103 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
104 } LL_I2C_InitTypeDef;
105 /**
106 * @}
107 */
108 #endif /*USE_FULL_LL_DRIVER*/
109
110 /* Exported constants --------------------------------------------------------*/
111 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
112 * @{
113 */
114
115 /** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
116 * @brief Flags defines which can be used with LL_I2C_WriteReg function
117 * @{
118 */
119 #define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */
120 #define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */
121 #define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */
122 #define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */
123 #define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */
124 #define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */
125 #define LL_I2C_ICR_PECCF I2C_ICR_PECCF /*!< PEC error flag */
126 #define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /*!< Timeout detection flag */
127 #define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /*!< Alert flag */
128 /**
129 * @}
130 */
131
132 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
133 * @brief Flags defines which can be used with LL_I2C_ReadReg function
134 * @{
135 */
136 #define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register empty */
137 #define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status */
138 #define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not empty */
139 #define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mode) */
140 #define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received flag */
141 #define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag */
142 #define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master mode) */
143 #define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload */
144 #define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error */
145 #define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost */
146 #define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */
147 #define LL_I2C_ISR_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
148 #define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
149 #define LL_I2C_ISR_ALERT I2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */
150 #define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy */
151 /**
152 * @}
153 */
154
155 /** @defgroup I2C_LL_EC_IT IT Defines
156 * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
157 * @{
158 */
159 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable */
160 #define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable */
161 #define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */
162 #define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */
163 #define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt enable */
164 #define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrupt enable */
165 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable */
166 /**
167 * @}
168 */
169
170 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
171 * @{
172 */
173 #define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
174 #define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */
175 #define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode (Default address not acknowledge) */
176 #define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */
177 /**
178 * @}
179 */
180
181 /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
182 * @{
183 */
184 #define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */
185 #define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */
186 /**
187 * @}
188 */
189
190 /** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
191 * @{
192 */
193 #define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */
194 #define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/
195 /**
196 * @}
197 */
198
199 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
200 * @{
201 */
202 #define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */
203 #define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/
204 /**
205 * @}
206 */
207
208 /** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
209 * @{
210 */
211 #define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */
212 #define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */
213 #define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */
214 #define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */
215 #define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */
216 #define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */
217 #define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */
218 #define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done. All Address2 are acknowledged.*/
219 /**
220 * @}
221 */
222
223 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
224 * @{
225 */
226 #define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */
227 #define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/
228 /**
229 * @}
230 */
231
232 /** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
233 * @{
234 */
235 #define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */
236 #define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/
237 /**
238 * @}
239 */
240
241 /** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
242 * @{
243 */
244 #define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */
245 #define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */
246 /**
247 * @}
248 */
249
250 /** @defgroup I2C_LL_EC_MODE Transfer End Mode
251 * @{
252 */
253 #define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */
254 #define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode with no HW PEC comparison. */
255 #define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode with no HW PEC comparison. */
256 #define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
257 #define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
258 #define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode with HW PEC comparison. */
259 #define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
260 #define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Software end mode with HW PEC comparison. */
261 /**
262 * @}
263 */
264
265 /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
266 * @{
267 */
268 #define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */
269 #define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) /*!< Generate Stop condition (Size should be set to 0). */
270 #define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */
271 #define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Start for write request. */
272 #define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */
273 #define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 7Bit address. */
274 #define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */
275 #define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 10Bit address.*/
276 /**
277 * @}
278 */
279
280 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
281 * @{
282 */
283 #define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, slave enters receiver mode. */
284 #define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, slave enters transmitter mode.*/
285 /**
286 * @}
287 */
288
289 /** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
290 * @{
291 */
292 #define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
293 #define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
294 /**
295 * @}
296 */
297
298 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
299 * @{
300 */
301 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect SCL low level timeout. */
302 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/
303 /**
304 * @}
305 */
306
307 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
308 * @{
309 */
310 #define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */
311 #define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) enable bit */
312 #define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */
313 /**
314 * @}
315 */
316
317 /**
318 * @}
319 */
320
321 /* Exported macro ------------------------------------------------------------*/
322 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
323 * @{
324 */
325
326 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
327 * @{
328 */
329
330 /**
331 * @brief Write a value in I2C register
332 * @param __INSTANCE__ I2C Instance
333 * @param __REG__ Register to be written
334 * @param __VALUE__ Value to be written in the register
335 * @retval None
336 */
337 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
338
339 /**
340 * @brief Read a value in I2C register
341 * @param __INSTANCE__ I2C Instance
342 * @param __REG__ Register to be read
343 * @retval Register value
344 */
345 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
346 /**
347 * @}
348 */
349
350 /** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
351 * @{
352 */
353 /**
354 * @brief Configure the SDA setup, hold time and the SCL high, low period.
355 * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
356 * @param __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
357 * @param __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
358 * @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
359 * @param __CLOCK_LOW_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
360 * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
361 */
362 #define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \
363 ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \
364 (((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \
365 (((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \
366 (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \
367 (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
368 /**
369 * @}
370 */
371
372 /**
373 * @}
374 */
375
376 /* Exported functions --------------------------------------------------------*/
377 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
378 * @{
379 */
380
381 /** @defgroup I2C_LL_EF_Configuration Configuration
382 * @{
383 */
384
385 /**
386 * @brief Enable I2C peripheral (PE = 1).
387 * @rmtoll CR1 PE LL_I2C_Enable
388 * @param I2Cx I2C Instance.
389 * @retval None
390 */
391 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
392 {
393 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
394 }
395
396 /**
397 * @brief Disable I2C peripheral (PE = 0).
398 * @note When PE = 0, the I2C SCL and SDA lines are released.
399 * Internal state machines and status bits are put back to their reset value.
400 * When cleared, PE must be kept low for at least 3 APB clock cycles.
401 * @rmtoll CR1 PE LL_I2C_Disable
402 * @param I2Cx I2C Instance.
403 * @retval None
404 */
405 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
406 {
407 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
408 }
409
410 /**
411 * @brief Check if the I2C peripheral is enabled or disabled.
412 * @rmtoll CR1 PE LL_I2C_IsEnabled
413 * @param I2Cx I2C Instance.
414 * @retval State of bit (1 or 0).
415 */
416 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
417 {
418 return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
419 }
420
421 /**
422 * @brief Configure Noise Filters (Analog and Digital).
423 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
424 * The filters can only be programmed when the I2C is disabled (PE = 0).
425 * @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n
426 * CR1 DNF LL_I2C_ConfigFilters
427 * @param I2Cx I2C Instance.
428 * @param AnalogFilter This parameter can be one of the following values:
429 * @arg @ref LL_I2C_ANALOGFILTER_ENABLE
430 * @arg @ref LL_I2C_ANALOGFILTER_DISABLE
431 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
432 * This parameter is used to configure the digital noise filter on SDA and SCL input.
433 * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
434 * @retval None
435 */
436 __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
437 {
438 MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
439 }
440
441 /**
442 * @brief Configure Digital Noise Filter.
443 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
444 * This filter can only be programmed when the I2C is disabled (PE = 0).
445 * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter
446 * @param I2Cx I2C Instance.
447 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
448 * This parameter is used to configure the digital noise filter on SDA and SCL input.
449 * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
450 * @retval None
451 */
452 __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
453 {
454 MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
455 }
456
457 /**
458 * @brief Get the current Digital Noise Filter configuration.
459 * @rmtoll CR1 DNF LL_I2C_GetDigitalFilter
460 * @param I2Cx I2C Instance.
461 * @retval Value between Min_Data=0x0 and Max_Data=0xF
462 */
463 __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
464 {
465 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
466 }
467
468 /**
469 * @brief Enable Analog Noise Filter.
470 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
471 * @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter
472 * @param I2Cx I2C Instance.
473 * @retval None
474 */
475 __STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
476 {
477 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
478 }
479
480 /**
481 * @brief Disable Analog Noise Filter.
482 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
483 * @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter
484 * @param I2Cx I2C Instance.
485 * @retval None
486 */
487 __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
488 {
489 SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
490 }
491
492 /**
493 * @brief Check if Analog Noise Filter is enabled or disabled.
494 * @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
495 * @param I2Cx I2C Instance.
496 * @retval State of bit (1 or 0).
497 */
498 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
499 {
500 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
501 }
502
503 /**
504 * @brief Enable DMA transmission requests.
505 * @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
506 * @param I2Cx I2C Instance.
507 * @retval None
508 */
509 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
510 {
511 SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
512 }
513
514 /**
515 * @brief Disable DMA transmission requests.
516 * @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
517 * @param I2Cx I2C Instance.
518 * @retval None
519 */
520 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
521 {
522 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
523 }
524
525 /**
526 * @brief Check if DMA transmission requests are enabled or disabled.
527 * @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
528 * @param I2Cx I2C Instance.
529 * @retval State of bit (1 or 0).
530 */
531 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
532 {
533 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
534 }
535
536 /**
537 * @brief Enable DMA reception requests.
538 * @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
539 * @param I2Cx I2C Instance.
540 * @retval None
541 */
542 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
543 {
544 SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
545 }
546
547 /**
548 * @brief Disable DMA reception requests.
549 * @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
550 * @param I2Cx I2C Instance.
551 * @retval None
552 */
553 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
554 {
555 CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
556 }
557
558 /**
559 * @brief Check if DMA reception requests are enabled or disabled.
560 * @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
561 * @param I2Cx I2C Instance.
562 * @retval State of bit (1 or 0).
563 */
564 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
565 {
566 return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
567 }
568
569 /**
570 * @brief Get the data register address used for DMA transfer
571 * @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n
572 * RXDR RXDATA LL_I2C_DMA_GetRegAddr
573 * @param I2Cx I2C Instance
574 * @param Direction This parameter can be one of the following values:
575 * @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
576 * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
577 * @retval Address of data register
578 */
579 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
580 {
581 uint32_t data_reg_addr;
582
583 if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
584 {
585 /* return address of TXDR register */
586 data_reg_addr = (uint32_t) & (I2Cx->TXDR);
587 }
588 else
589 {
590 /* return address of RXDR register */
591 data_reg_addr = (uint32_t) & (I2Cx->RXDR);
592 }
593
594 return data_reg_addr;
595 }
596
597 /**
598 * @brief Enable Clock stretching.
599 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
600 * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
601 * @param I2Cx I2C Instance.
602 * @retval None
603 */
604 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
605 {
606 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
607 }
608
609 /**
610 * @brief Disable Clock stretching.
611 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
612 * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
613 * @param I2Cx I2C Instance.
614 * @retval None
615 */
616 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
617 {
618 SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
619 }
620
621 /**
622 * @brief Check if Clock stretching is enabled or disabled.
623 * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
624 * @param I2Cx I2C Instance.
625 * @retval State of bit (1 or 0).
626 */
627 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
628 {
629 return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
630 }
631
632 /**
633 * @brief Enable hardware byte control in slave mode.
634 * @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl
635 * @param I2Cx I2C Instance.
636 * @retval None
637 */
638 __STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
639 {
640 SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
641 }
642
643 /**
644 * @brief Disable hardware byte control in slave mode.
645 * @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl
646 * @param I2Cx I2C Instance.
647 * @retval None
648 */
649 __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
650 {
651 CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
652 }
653
654 /**
655 * @brief Check if hardware byte control in slave mode is enabled or disabled.
656 * @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl
657 * @param I2Cx I2C Instance.
658 * @retval State of bit (1 or 0).
659 */
660 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
661 {
662 return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
663 }
664
665 /**
666 * @brief Enable Wakeup from STOP.
667 * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
668 * WakeUpFromStop feature is supported by the I2Cx Instance.
669 * @note This bit can only be programmed when Digital Filter is disabled.
670 * @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop
671 * @param I2Cx I2C Instance.
672 * @retval None
673 */
674 __STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
675 {
676 SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
677 }
678
679 /**
680 * @brief Disable Wakeup from STOP.
681 * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
682 * WakeUpFromStop feature is supported by the I2Cx Instance.
683 * @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop
684 * @param I2Cx I2C Instance.
685 * @retval None
686 */
687 __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
688 {
689 CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
690 }
691
692 /**
693 * @brief Check if Wakeup from STOP is enabled or disabled.
694 * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
695 * WakeUpFromStop feature is supported by the I2Cx Instance.
696 * @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
697 * @param I2Cx I2C Instance.
698 * @retval State of bit (1 or 0).
699 */
700 __STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
701 {
702 return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
703 }
704
705 /**
706 * @brief Enable General Call.
707 * @note When enabled the Address 0x00 is ACKed.
708 * @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall
709 * @param I2Cx I2C Instance.
710 * @retval None
711 */
712 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
713 {
714 SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
715 }
716
717 /**
718 * @brief Disable General Call.
719 * @note When disabled the Address 0x00 is NACKed.
720 * @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall
721 * @param I2Cx I2C Instance.
722 * @retval None
723 */
724 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
725 {
726 CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
727 }
728
729 /**
730 * @brief Check if General Call is enabled or disabled.
731 * @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall
732 * @param I2Cx I2C Instance.
733 * @retval State of bit (1 or 0).
734 */
735 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
736 {
737 return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
738 }
739
740 /**
741 * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
742 * @note Changing this bit is not allowed, when the START bit is set.
743 * @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode
744 * @param I2Cx I2C Instance.
745 * @param AddressingMode This parameter can be one of the following values:
746 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
747 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
748 * @retval None
749 */
750 __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
751 {
752 MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
753 }
754
755 /**
756 * @brief Get the Master addressing mode.
757 * @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode
758 * @param I2Cx I2C Instance.
759 * @retval Returned value can be one of the following values:
760 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
761 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
762 */
763 __STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
764 {
765 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
766 }
767
768 /**
769 * @brief Set the Own Address1.
770 * @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n
771 * OAR1 OA1MODE LL_I2C_SetOwnAddress1
772 * @param I2Cx I2C Instance.
773 * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
774 * @param OwnAddrSize This parameter can be one of the following values:
775 * @arg @ref LL_I2C_OWNADDRESS1_7BIT
776 * @arg @ref LL_I2C_OWNADDRESS1_10BIT
777 * @retval None
778 */
779 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
780 {
781 MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
782 }
783
784 /**
785 * @brief Enable acknowledge on Own Address1 match address.
786 * @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1
787 * @param I2Cx I2C Instance.
788 * @retval None
789 */
790 __STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
791 {
792 SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
793 }
794
795 /**
796 * @brief Disable acknowledge on Own Address1 match address.
797 * @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1
798 * @param I2Cx I2C Instance.
799 * @retval None
800 */
801 __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
802 {
803 CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
804 }
805
806 /**
807 * @brief Check if Own Address1 acknowledge is enabled or disabled.
808 * @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
809 * @param I2Cx I2C Instance.
810 * @retval State of bit (1 or 0).
811 */
812 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
813 {
814 return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
815 }
816
817 /**
818 * @brief Set the 7bits Own Address2.
819 * @note This action has no effect if own address2 is enabled.
820 * @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n
821 * OAR2 OA2MSK LL_I2C_SetOwnAddress2
822 * @param I2Cx I2C Instance.
823 * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
824 * @param OwnAddrMask This parameter can be one of the following values:
825 * @arg @ref LL_I2C_OWNADDRESS2_NOMASK
826 * @arg @ref LL_I2C_OWNADDRESS2_MASK01
827 * @arg @ref LL_I2C_OWNADDRESS2_MASK02
828 * @arg @ref LL_I2C_OWNADDRESS2_MASK03
829 * @arg @ref LL_I2C_OWNADDRESS2_MASK04
830 * @arg @ref LL_I2C_OWNADDRESS2_MASK05
831 * @arg @ref LL_I2C_OWNADDRESS2_MASK06
832 * @arg @ref LL_I2C_OWNADDRESS2_MASK07
833 * @retval None
834 */
835 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
836 {
837 MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
838 }
839
840 /**
841 * @brief Enable acknowledge on Own Address2 match address.
842 * @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2
843 * @param I2Cx I2C Instance.
844 * @retval None
845 */
846 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
847 {
848 SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
849 }
850
851 /**
852 * @brief Disable acknowledge on Own Address2 match address.
853 * @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2
854 * @param I2Cx I2C Instance.
855 * @retval None
856 */
857 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
858 {
859 CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
860 }
861
862 /**
863 * @brief Check if Own Address1 acknowledge is enabled or disabled.
864 * @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
865 * @param I2Cx I2C Instance.
866 * @retval State of bit (1 or 0).
867 */
868 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
869 {
870 return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
871 }
872
873 /**
874 * @brief Configure the SDA setup, hold time and the SCL high, low period.
875 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
876 * @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming
877 * @param I2Cx I2C Instance.
878 * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
879 * @note This parameter is computed with the STM32CubeMX Tool.
880 * @retval None
881 */
882 __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
883 {
884 WRITE_REG(I2Cx->TIMINGR, Timing);
885 }
886
887 /**
888 * @brief Get the Timing Prescaler setting.
889 * @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler
890 * @param I2Cx I2C Instance.
891 * @retval Value between Min_Data=0x0 and Max_Data=0xF
892 */
893 __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
894 {
895 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
896 }
897
898 /**
899 * @brief Get the SCL low period setting.
900 * @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod
901 * @param I2Cx I2C Instance.
902 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
903 */
904 __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
905 {
906 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
907 }
908
909 /**
910 * @brief Get the SCL high period setting.
911 * @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod
912 * @param I2Cx I2C Instance.
913 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
914 */
915 __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
916 {
917 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
918 }
919
920 /**
921 * @brief Get the SDA hold time.
922 * @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime
923 * @param I2Cx I2C Instance.
924 * @retval Value between Min_Data=0x0 and Max_Data=0xF
925 */
926 __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
927 {
928 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
929 }
930
931 /**
932 * @brief Get the SDA setup time.
933 * @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime
934 * @param I2Cx I2C Instance.
935 * @retval Value between Min_Data=0x0 and Max_Data=0xF
936 */
937 __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
938 {
939 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
940 }
941
942 /**
943 * @brief Configure peripheral mode.
944 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
945 * SMBus feature is supported by the I2Cx Instance.
946 * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n
947 * CR1 SMBDEN LL_I2C_SetMode
948 * @param I2Cx I2C Instance.
949 * @param PeripheralMode This parameter can be one of the following values:
950 * @arg @ref LL_I2C_MODE_I2C
951 * @arg @ref LL_I2C_MODE_SMBUS_HOST
952 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
953 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
954 * @retval None
955 */
956 __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
957 {
958 MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
959 }
960
961 /**
962 * @brief Get peripheral mode.
963 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
964 * SMBus feature is supported by the I2Cx Instance.
965 * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n
966 * CR1 SMBDEN LL_I2C_GetMode
967 * @param I2Cx I2C Instance.
968 * @retval Returned value can be one of the following values:
969 * @arg @ref LL_I2C_MODE_I2C
970 * @arg @ref LL_I2C_MODE_SMBUS_HOST
971 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
972 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
973 */
974 __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
975 {
976 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
977 }
978
979 /**
980 * @brief Enable SMBus alert (Host or Device mode)
981 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
982 * SMBus feature is supported by the I2Cx Instance.
983 * @note SMBus Device mode:
984 * - SMBus Alert pin is drived low and
985 * Alert Response Address Header acknowledge is enabled.
986 * SMBus Host mode:
987 * - SMBus Alert pin management is supported.
988 * @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert
989 * @param I2Cx I2C Instance.
990 * @retval None
991 */
992 __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
993 {
994 SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
995 }
996
997 /**
998 * @brief Disable SMBus alert (Host or Device mode)
999 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1000 * SMBus feature is supported by the I2Cx Instance.
1001 * @note SMBus Device mode:
1002 * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
1003 * Alert Response Address Header acknowledge is disabled.
1004 * SMBus Host mode:
1005 * - SMBus Alert pin management is not supported.
1006 * @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert
1007 * @param I2Cx I2C Instance.
1008 * @retval None
1009 */
1010 __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
1011 {
1012 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
1013 }
1014
1015 /**
1016 * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
1017 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1018 * SMBus feature is supported by the I2Cx Instance.
1019 * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
1020 * @param I2Cx I2C Instance.
1021 * @retval State of bit (1 or 0).
1022 */
1023 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
1024 {
1025 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
1026 }
1027
1028 /**
1029 * @brief Enable SMBus Packet Error Calculation (PEC).
1030 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1031 * SMBus feature is supported by the I2Cx Instance.
1032 * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC
1033 * @param I2Cx I2C Instance.
1034 * @retval None
1035 */
1036 __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
1037 {
1038 SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
1039 }
1040
1041 /**
1042 * @brief Disable SMBus Packet Error Calculation (PEC).
1043 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1044 * SMBus feature is supported by the I2Cx Instance.
1045 * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC
1046 * @param I2Cx I2C Instance.
1047 * @retval None
1048 */
1049 __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
1050 {
1051 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
1052 }
1053
1054 /**
1055 * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
1056 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1057 * SMBus feature is supported by the I2Cx Instance.
1058 * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC
1059 * @param I2Cx I2C Instance.
1060 * @retval State of bit (1 or 0).
1061 */
1062 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
1063 {
1064 return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
1065 }
1066
1067 /**
1068 * @brief Configure the SMBus Clock Timeout.
1069 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1070 * SMBus feature is supported by the I2Cx Instance.
1071 * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
1072 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n
1073 * TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n
1074 * TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout
1075 * @param I2Cx I2C Instance.
1076 * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1077 * @param TimeoutAMode This parameter can be one of the following values:
1078 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1079 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1080 * @param TimeoutB
1081 * @retval None
1082 */
1083 __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
1084 uint32_t TimeoutB)
1085 {
1086 MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
1087 TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
1088 }
1089
1090 /**
1091 * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
1092 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1093 * SMBus feature is supported by the I2Cx Instance.
1094 * @note These bits can only be programmed when TimeoutA is disabled.
1095 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
1096 * @param I2Cx I2C Instance.
1097 * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1098 * @retval None
1099 */
1100 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
1101 {
1102 WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
1103 }
1104
1105 /**
1106 * @brief Get the SMBus Clock TimeoutA setting.
1107 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1108 * SMBus feature is supported by the I2Cx Instance.
1109 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
1110 * @param I2Cx I2C Instance.
1111 * @retval Value between Min_Data=0 and Max_Data=0xFFF
1112 */
1113 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
1114 {
1115 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
1116 }
1117
1118 /**
1119 * @brief Set the SMBus Clock TimeoutA mode.
1120 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1121 * SMBus feature is supported by the I2Cx Instance.
1122 * @note This bit can only be programmed when TimeoutA is disabled.
1123 * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
1124 * @param I2Cx I2C Instance.
1125 * @param TimeoutAMode This parameter can be one of the following values:
1126 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1127 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1128 * @retval None
1129 */
1130 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
1131 {
1132 WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
1133 }
1134
1135 /**
1136 * @brief Get the SMBus Clock TimeoutA mode.
1137 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1138 * SMBus feature is supported by the I2Cx Instance.
1139 * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
1140 * @param I2Cx I2C Instance.
1141 * @retval Returned value can be one of the following values:
1142 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1143 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1144 */
1145 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
1146 {
1147 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
1148 }
1149
1150 /**
1151 * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
1152 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1153 * SMBus feature is supported by the I2Cx Instance.
1154 * @note These bits can only be programmed when TimeoutB is disabled.
1155 * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
1156 * @param I2Cx I2C Instance.
1157 * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1158 * @retval None
1159 */
1160 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
1161 {
1162 WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
1163 }
1164
1165 /**
1166 * @brief Get the SMBus Extented Cumulative Clock TimeoutB setting.
1167 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1168 * SMBus feature is supported by the I2Cx Instance.
1169 * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
1170 * @param I2Cx I2C Instance.
1171 * @retval Value between Min_Data=0 and Max_Data=0xFFF
1172 */
1173 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
1174 {
1175 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
1176 }
1177
1178 /**
1179 * @brief Enable the SMBus Clock Timeout.
1180 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1181 * SMBus feature is supported by the I2Cx Instance.
1182 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n
1183 * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
1184 * @param I2Cx I2C Instance.
1185 * @param ClockTimeout This parameter can be one of the following values:
1186 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1187 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1188 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1189 * @retval None
1190 */
1191 __STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1192 {
1193 SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
1194 }
1195
1196 /**
1197 * @brief Disable the SMBus Clock Timeout.
1198 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1199 * SMBus feature is supported by the I2Cx Instance.
1200 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n
1201 * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
1202 * @param I2Cx I2C Instance.
1203 * @param ClockTimeout This parameter can be one of the following values:
1204 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1205 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1206 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1207 * @retval None
1208 */
1209 __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1210 {
1211 CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
1212 }
1213
1214 /**
1215 * @brief Check if the SMBus Clock Timeout is enabled or disabled.
1216 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1217 * SMBus feature is supported by the I2Cx Instance.
1218 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n
1219 * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
1220 * @param I2Cx I2C Instance.
1221 * @param ClockTimeout This parameter can be one of the following values:
1222 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1223 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1224 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1225 * @retval State of bit (1 or 0).
1226 */
1227 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1228 {
1229 return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout)) ? 1UL : 0UL);
1230 }
1231
1232 /**
1233 * @}
1234 */
1235
1236 /** @defgroup I2C_LL_EF_IT_Management IT_Management
1237 * @{
1238 */
1239
1240 /**
1241 * @brief Enable TXIS interrupt.
1242 * @rmtoll CR1 TXIE LL_I2C_EnableIT_TX
1243 * @param I2Cx I2C Instance.
1244 * @retval None
1245 */
1246 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
1247 {
1248 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
1249 }
1250
1251 /**
1252 * @brief Disable TXIS interrupt.
1253 * @rmtoll CR1 TXIE LL_I2C_DisableIT_TX
1254 * @param I2Cx I2C Instance.
1255 * @retval None
1256 */
1257 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
1258 {
1259 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
1260 }
1261
1262 /**
1263 * @brief Check if the TXIS Interrupt is enabled or disabled.
1264 * @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX
1265 * @param I2Cx I2C Instance.
1266 * @retval State of bit (1 or 0).
1267 */
1268 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
1269 {
1270 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
1271 }
1272
1273 /**
1274 * @brief Enable RXNE interrupt.
1275 * @rmtoll CR1 RXIE LL_I2C_EnableIT_RX
1276 * @param I2Cx I2C Instance.
1277 * @retval None
1278 */
1279 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
1280 {
1281 SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
1282 }
1283
1284 /**
1285 * @brief Disable RXNE interrupt.
1286 * @rmtoll CR1 RXIE LL_I2C_DisableIT_RX
1287 * @param I2Cx I2C Instance.
1288 * @retval None
1289 */
1290 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
1291 {
1292 CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
1293 }
1294
1295 /**
1296 * @brief Check if the RXNE Interrupt is enabled or disabled.
1297 * @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX
1298 * @param I2Cx I2C Instance.
1299 * @retval State of bit (1 or 0).
1300 */
1301 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
1302 {
1303 return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
1304 }
1305
1306 /**
1307 * @brief Enable Address match interrupt (slave mode only).
1308 * @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR
1309 * @param I2Cx I2C Instance.
1310 * @retval None
1311 */
1312 __STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
1313 {
1314 SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
1315 }
1316
1317 /**
1318 * @brief Disable Address match interrupt (slave mode only).
1319 * @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR
1320 * @param I2Cx I2C Instance.
1321 * @retval None
1322 */
1323 __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
1324 {
1325 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
1326 }
1327
1328 /**
1329 * @brief Check if Address match interrupt is enabled or disabled.
1330 * @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
1331 * @param I2Cx I2C Instance.
1332 * @retval State of bit (1 or 0).
1333 */
1334 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
1335 {
1336 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
1337 }
1338
1339 /**
1340 * @brief Enable Not acknowledge received interrupt.
1341 * @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK
1342 * @param I2Cx I2C Instance.
1343 * @retval None
1344 */
1345 __STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
1346 {
1347 SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
1348 }
1349
1350 /**
1351 * @brief Disable Not acknowledge received interrupt.
1352 * @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK
1353 * @param I2Cx I2C Instance.
1354 * @retval None
1355 */
1356 __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
1357 {
1358 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
1359 }
1360
1361 /**
1362 * @brief Check if Not acknowledge received interrupt is enabled or disabled.
1363 * @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK
1364 * @param I2Cx I2C Instance.
1365 * @retval State of bit (1 or 0).
1366 */
1367 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
1368 {
1369 return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
1370 }
1371
1372 /**
1373 * @brief Enable STOP detection interrupt.
1374 * @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP
1375 * @param I2Cx I2C Instance.
1376 * @retval None
1377 */
1378 __STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
1379 {
1380 SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
1381 }
1382
1383 /**
1384 * @brief Disable STOP detection interrupt.
1385 * @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP
1386 * @param I2Cx I2C Instance.
1387 * @retval None
1388 */
1389 __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
1390 {
1391 CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
1392 }
1393
1394 /**
1395 * @brief Check if STOP detection interrupt is enabled or disabled.
1396 * @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP
1397 * @param I2Cx I2C Instance.
1398 * @retval State of bit (1 or 0).
1399 */
1400 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
1401 {
1402 return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
1403 }
1404
1405 /**
1406 * @brief Enable Transfer Complete interrupt.
1407 * @note Any of these events will generate interrupt :
1408 * Transfer Complete (TC)
1409 * Transfer Complete Reload (TCR)
1410 * @rmtoll CR1 TCIE LL_I2C_EnableIT_TC
1411 * @param I2Cx I2C Instance.
1412 * @retval None
1413 */
1414 __STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
1415 {
1416 SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
1417 }
1418
1419 /**
1420 * @brief Disable Transfer Complete interrupt.
1421 * @note Any of these events will generate interrupt :
1422 * Transfer Complete (TC)
1423 * Transfer Complete Reload (TCR)
1424 * @rmtoll CR1 TCIE LL_I2C_DisableIT_TC
1425 * @param I2Cx I2C Instance.
1426 * @retval None
1427 */
1428 __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
1429 {
1430 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
1431 }
1432
1433 /**
1434 * @brief Check if Transfer Complete interrupt is enabled or disabled.
1435 * @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC
1436 * @param I2Cx I2C Instance.
1437 * @retval State of bit (1 or 0).
1438 */
1439 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
1440 {
1441 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
1442 }
1443
1444 /**
1445 * @brief Enable Error interrupts.
1446 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1447 * SMBus feature is supported by the I2Cx Instance.
1448 * @note Any of these errors will generate interrupt :
1449 * Arbitration Loss (ARLO)
1450 * Bus Error detection (BERR)
1451 * Overrun/Underrun (OVR)
1452 * SMBus Timeout detection (TIMEOUT)
1453 * SMBus PEC error detection (PECERR)
1454 * SMBus Alert pin event detection (ALERT)
1455 * @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR
1456 * @param I2Cx I2C Instance.
1457 * @retval None
1458 */
1459 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
1460 {
1461 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
1462 }
1463
1464 /**
1465 * @brief Disable Error interrupts.
1466 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1467 * SMBus feature is supported by the I2Cx Instance.
1468 * @note Any of these errors will generate interrupt :
1469 * Arbitration Loss (ARLO)
1470 * Bus Error detection (BERR)
1471 * Overrun/Underrun (OVR)
1472 * SMBus Timeout detection (TIMEOUT)
1473 * SMBus PEC error detection (PECERR)
1474 * SMBus Alert pin event detection (ALERT)
1475 * @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR
1476 * @param I2Cx I2C Instance.
1477 * @retval None
1478 */
1479 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
1480 {
1481 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
1482 }
1483
1484 /**
1485 * @brief Check if Error interrupts are enabled or disabled.
1486 * @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR
1487 * @param I2Cx I2C Instance.
1488 * @retval State of bit (1 or 0).
1489 */
1490 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
1491 {
1492 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
1493 }
1494
1495 /**
1496 * @}
1497 */
1498
1499 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
1500 * @{
1501 */
1502
1503 /**
1504 * @brief Indicate the status of Transmit data register empty flag.
1505 * @note RESET: When next data is written in Transmit data register.
1506 * SET: When Transmit data register is empty.
1507 * @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE
1508 * @param I2Cx I2C Instance.
1509 * @retval State of bit (1 or 0).
1510 */
1511 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
1512 {
1513 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
1514 }
1515
1516 /**
1517 * @brief Indicate the status of Transmit interrupt flag.
1518 * @note RESET: When next data is written in Transmit data register.
1519 * SET: When Transmit data register is empty.
1520 * @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS
1521 * @param I2Cx I2C Instance.
1522 * @retval State of bit (1 or 0).
1523 */
1524 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
1525 {
1526 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
1527 }
1528
1529 /**
1530 * @brief Indicate the status of Receive data register not empty flag.
1531 * @note RESET: When Receive data register is read.
1532 * SET: When the received data is copied in Receive data register.
1533 * @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE
1534 * @param I2Cx I2C Instance.
1535 * @retval State of bit (1 or 0).
1536 */
1537 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
1538 {
1539 return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
1540 }
1541
1542 /**
1543 * @brief Indicate the status of Address matched flag (slave mode).
1544 * @note RESET: Clear default value.
1545 * SET: When the received slave address matched with one of the enabled slave address.
1546 * @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR
1547 * @param I2Cx I2C Instance.
1548 * @retval State of bit (1 or 0).
1549 */
1550 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
1551 {
1552 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
1553 }
1554
1555 /**
1556 * @brief Indicate the status of Not Acknowledge received flag.
1557 * @note RESET: Clear default value.
1558 * SET: When a NACK is received after a byte transmission.
1559 * @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK
1560 * @param I2Cx I2C Instance.
1561 * @retval State of bit (1 or 0).
1562 */
1563 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
1564 {
1565 return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
1566 }
1567
1568 /**
1569 * @brief Indicate the status of Stop detection flag.
1570 * @note RESET: Clear default value.
1571 * SET: When a Stop condition is detected.
1572 * @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP
1573 * @param I2Cx I2C Instance.
1574 * @retval State of bit (1 or 0).
1575 */
1576 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
1577 {
1578 return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
1579 }
1580
1581 /**
1582 * @brief Indicate the status of Transfer complete flag (master mode).
1583 * @note RESET: Clear default value.
1584 * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
1585 * @rmtoll ISR TC LL_I2C_IsActiveFlag_TC
1586 * @param I2Cx I2C Instance.
1587 * @retval State of bit (1 or 0).
1588 */
1589 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
1590 {
1591 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
1592 }
1593
1594 /**
1595 * @brief Indicate the status of Transfer complete flag (master mode).
1596 * @note RESET: Clear default value.
1597 * SET: When RELOAD=1 and NBYTES date have been transferred.
1598 * @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR
1599 * @param I2Cx I2C Instance.
1600 * @retval State of bit (1 or 0).
1601 */
1602 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
1603 {
1604 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
1605 }
1606
1607 /**
1608 * @brief Indicate the status of Bus error flag.
1609 * @note RESET: Clear default value.
1610 * SET: When a misplaced Start or Stop condition is detected.
1611 * @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR
1612 * @param I2Cx I2C Instance.
1613 * @retval State of bit (1 or 0).
1614 */
1615 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
1616 {
1617 return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
1618 }
1619
1620 /**
1621 * @brief Indicate the status of Arbitration lost flag.
1622 * @note RESET: Clear default value.
1623 * SET: When arbitration lost.
1624 * @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO
1625 * @param I2Cx I2C Instance.
1626 * @retval State of bit (1 or 0).
1627 */
1628 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
1629 {
1630 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
1631 }
1632
1633 /**
1634 * @brief Indicate the status of Overrun/Underrun flag (slave mode).
1635 * @note RESET: Clear default value.
1636 * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
1637 * @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR
1638 * @param I2Cx I2C Instance.
1639 * @retval State of bit (1 or 0).
1640 */
1641 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
1642 {
1643 return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
1644 }
1645
1646 /**
1647 * @brief Indicate the status of SMBus PEC error flag in reception.
1648 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1649 * SMBus feature is supported by the I2Cx Instance.
1650 * @note RESET: Clear default value.
1651 * SET: When the received PEC does not match with the PEC register content.
1652 * @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
1653 * @param I2Cx I2C Instance.
1654 * @retval State of bit (1 or 0).
1655 */
1656 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
1657 {
1658 return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
1659 }
1660
1661 /**
1662 * @brief Indicate the status of SMBus Timeout detection flag.
1663 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1664 * SMBus feature is supported by the I2Cx Instance.
1665 * @note RESET: Clear default value.
1666 * SET: When a timeout or extended clock timeout occurs.
1667 * @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
1668 * @param I2Cx I2C Instance.
1669 * @retval State of bit (1 or 0).
1670 */
1671 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
1672 {
1673 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
1674 }
1675
1676 /**
1677 * @brief Indicate the status of SMBus alert flag.
1678 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1679 * SMBus feature is supported by the I2Cx Instance.
1680 * @note RESET: Clear default value.
1681 * SET: When SMBus host configuration, SMBus alert enabled and
1682 * a falling edge event occurs on SMBA pin.
1683 * @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
1684 * @param I2Cx I2C Instance.
1685 * @retval State of bit (1 or 0).
1686 */
1687 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
1688 {
1689 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
1690 }
1691
1692 /**
1693 * @brief Indicate the status of Bus Busy flag.
1694 * @note RESET: Clear default value.
1695 * SET: When a Start condition is detected.
1696 * @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY
1697 * @param I2Cx I2C Instance.
1698 * @retval State of bit (1 or 0).
1699 */
1700 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
1701 {
1702 return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
1703 }
1704
1705 /**
1706 * @brief Clear Address Matched flag.
1707 * @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR
1708 * @param I2Cx I2C Instance.
1709 * @retval None
1710 */
1711 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
1712 {
1713 SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
1714 }
1715
1716 /**
1717 * @brief Clear Not Acknowledge flag.
1718 * @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK
1719 * @param I2Cx I2C Instance.
1720 * @retval None
1721 */
1722 __STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
1723 {
1724 SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
1725 }
1726
1727 /**
1728 * @brief Clear Stop detection flag.
1729 * @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP
1730 * @param I2Cx I2C Instance.
1731 * @retval None
1732 */
1733 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
1734 {
1735 SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
1736 }
1737
1738 /**
1739 * @brief Clear Transmit data register empty flag (TXE).
1740 * @note This bit can be clear by software in order to flush the transmit data register (TXDR).
1741 * @rmtoll ISR TXE LL_I2C_ClearFlag_TXE
1742 * @param I2Cx I2C Instance.
1743 * @retval None
1744 */
1745 __STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
1746 {
1747 WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
1748 }
1749
1750 /**
1751 * @brief Clear Bus error flag.
1752 * @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR
1753 * @param I2Cx I2C Instance.
1754 * @retval None
1755 */
1756 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
1757 {
1758 SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
1759 }
1760
1761 /**
1762 * @brief Clear Arbitration lost flag.
1763 * @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO
1764 * @param I2Cx I2C Instance.
1765 * @retval None
1766 */
1767 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
1768 {
1769 SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
1770 }
1771
1772 /**
1773 * @brief Clear Overrun/Underrun flag.
1774 * @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR
1775 * @param I2Cx I2C Instance.
1776 * @retval None
1777 */
1778 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
1779 {
1780 SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
1781 }
1782
1783 /**
1784 * @brief Clear SMBus PEC error flag.
1785 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1786 * SMBus feature is supported by the I2Cx Instance.
1787 * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
1788 * @param I2Cx I2C Instance.
1789 * @retval None
1790 */
1791 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
1792 {
1793 SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
1794 }
1795
1796 /**
1797 * @brief Clear SMBus Timeout detection flag.
1798 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1799 * SMBus feature is supported by the I2Cx Instance.
1800 * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
1801 * @param I2Cx I2C Instance.
1802 * @retval None
1803 */
1804 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
1805 {
1806 SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
1807 }
1808
1809 /**
1810 * @brief Clear SMBus Alert flag.
1811 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1812 * SMBus feature is supported by the I2Cx Instance.
1813 * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
1814 * @param I2Cx I2C Instance.
1815 * @retval None
1816 */
1817 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
1818 {
1819 SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
1820 }
1821
1822 /**
1823 * @}
1824 */
1825
1826 /** @defgroup I2C_LL_EF_Data_Management Data_Management
1827 * @{
1828 */
1829
1830 /**
1831 * @brief Enable automatic STOP condition generation (master mode).
1832 * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
1833 * This bit has no effect in slave mode or when RELOAD bit is set.
1834 * @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode
1835 * @param I2Cx I2C Instance.
1836 * @retval None
1837 */
1838 __STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
1839 {
1840 SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
1841 }
1842
1843 /**
1844 * @brief Disable automatic STOP condition generation (master mode).
1845 * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
1846 * @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode
1847 * @param I2Cx I2C Instance.
1848 * @retval None
1849 */
1850 __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
1851 {
1852 CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
1853 }
1854
1855 /**
1856 * @brief Check if automatic STOP condition is enabled or disabled.
1857 * @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode
1858 * @param I2Cx I2C Instance.
1859 * @retval State of bit (1 or 0).
1860 */
1861 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
1862 {
1863 return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
1864 }
1865
1866 /**
1867 * @brief Enable reload mode (master mode).
1868 * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
1869 * @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode
1870 * @param I2Cx I2C Instance.
1871 * @retval None
1872 */
1873 __STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
1874 {
1875 SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
1876 }
1877
1878 /**
1879 * @brief Disable reload mode (master mode).
1880 * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
1881 * @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode
1882 * @param I2Cx I2C Instance.
1883 * @retval None
1884 */
1885 __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
1886 {
1887 CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
1888 }
1889
1890 /**
1891 * @brief Check if reload mode is enabled or disabled.
1892 * @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode
1893 * @param I2Cx I2C Instance.
1894 * @retval State of bit (1 or 0).
1895 */
1896 __STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
1897 {
1898 return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
1899 }
1900
1901 /**
1902 * @brief Configure the number of bytes for transfer.
1903 * @note Changing these bits when START bit is set is not allowed.
1904 * @rmtoll CR2 NBYTES LL_I2C_SetTransferSize
1905 * @param I2Cx I2C Instance.
1906 * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
1907 * @retval None
1908 */
1909 __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
1910 {
1911 MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
1912 }
1913
1914 /**
1915 * @brief Get the number of bytes configured for transfer.
1916 * @rmtoll CR2 NBYTES LL_I2C_GetTransferSize
1917 * @param I2Cx I2C Instance.
1918 * @retval Value between Min_Data=0x0 and Max_Data=0xFF
1919 */
1920 __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
1921 {
1922 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
1923 }
1924
1925 /**
1926 * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
1927 * @note Usage in Slave mode only.
1928 * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData
1929 * @param I2Cx I2C Instance.
1930 * @param TypeAcknowledge This parameter can be one of the following values:
1931 * @arg @ref LL_I2C_ACK
1932 * @arg @ref LL_I2C_NACK
1933 * @retval None
1934 */
1935 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
1936 {
1937 MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
1938 }
1939
1940 /**
1941 * @brief Generate a START or RESTART condition
1942 * @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
1943 * This action has no effect when RELOAD is set.
1944 * @rmtoll CR2 START LL_I2C_GenerateStartCondition
1945 * @param I2Cx I2C Instance.
1946 * @retval None
1947 */
1948 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
1949 {
1950 SET_BIT(I2Cx->CR2, I2C_CR2_START);
1951 }
1952
1953 /**
1954 * @brief Generate a STOP condition after the current byte transfer (master mode).
1955 * @rmtoll CR2 STOP LL_I2C_GenerateStopCondition
1956 * @param I2Cx I2C Instance.
1957 * @retval None
1958 */
1959 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
1960 {
1961 SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
1962 }
1963
1964 /**
1965 * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
1966 * @note The master sends the complete 10bit slave address read sequence :
1967 * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
1968 * @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead
1969 * @param I2Cx I2C Instance.
1970 * @retval None
1971 */
1972 __STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
1973 {
1974 CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
1975 }
1976
1977 /**
1978 * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode).
1979 * @note The master only sends the first 7 bits of 10bit address in Read direction.
1980 * @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead
1981 * @param I2Cx I2C Instance.
1982 * @retval None
1983 */
1984 __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
1985 {
1986 SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
1987 }
1988
1989 /**
1990 * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
1991 * @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead
1992 * @param I2Cx I2C Instance.
1993 * @retval State of bit (1 or 0).
1994 */
1995 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
1996 {
1997 return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
1998 }
1999
2000 /**
2001 * @brief Configure the transfer direction (master mode).
2002 * @note Changing these bits when START bit is set is not allowed.
2003 * @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest
2004 * @param I2Cx I2C Instance.
2005 * @param TransferRequest This parameter can be one of the following values:
2006 * @arg @ref LL_I2C_REQUEST_WRITE
2007 * @arg @ref LL_I2C_REQUEST_READ
2008 * @retval None
2009 */
2010 __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
2011 {
2012 MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
2013 }
2014
2015 /**
2016 * @brief Get the transfer direction requested (master mode).
2017 * @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest
2018 * @param I2Cx I2C Instance.
2019 * @retval Returned value can be one of the following values:
2020 * @arg @ref LL_I2C_REQUEST_WRITE
2021 * @arg @ref LL_I2C_REQUEST_READ
2022 */
2023 __STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
2024 {
2025 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
2026 }
2027
2028 /**
2029 * @brief Configure the slave address for transfer (master mode).
2030 * @note Changing these bits when START bit is set is not allowed.
2031 * @rmtoll CR2 SADD LL_I2C_SetSlaveAddr
2032 * @param I2Cx I2C Instance.
2033 * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
2034 * @retval None
2035 */
2036 __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
2037 {
2038 MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
2039 }
2040
2041 /**
2042 * @brief Get the slave address programmed for transfer.
2043 * @rmtoll CR2 SADD LL_I2C_GetSlaveAddr
2044 * @param I2Cx I2C Instance.
2045 * @retval Value between Min_Data=0x0 and Max_Data=0x3F
2046 */
2047 __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
2048 {
2049 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
2050 }
2051
2052 /**
2053 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
2054 * @rmtoll CR2 SADD LL_I2C_HandleTransfer\n
2055 * CR2 ADD10 LL_I2C_HandleTransfer\n
2056 * CR2 RD_WRN LL_I2C_HandleTransfer\n
2057 * CR2 START LL_I2C_HandleTransfer\n
2058 * CR2 STOP LL_I2C_HandleTransfer\n
2059 * CR2 RELOAD LL_I2C_HandleTransfer\n
2060 * CR2 NBYTES LL_I2C_HandleTransfer\n
2061 * CR2 AUTOEND LL_I2C_HandleTransfer\n
2062 * CR2 HEAD10R LL_I2C_HandleTransfer
2063 * @param I2Cx I2C Instance.
2064 * @param SlaveAddr Specifies the slave address to be programmed.
2065 * @param SlaveAddrSize This parameter can be one of the following values:
2066 * @arg @ref LL_I2C_ADDRSLAVE_7BIT
2067 * @arg @ref LL_I2C_ADDRSLAVE_10BIT
2068 * @param TransferSize Specifies the number of bytes to be programmed.
2069 * This parameter must be a value between Min_Data=0 and Max_Data=255.
2070 * @param EndMode This parameter can be one of the following values:
2071 * @arg @ref LL_I2C_MODE_RELOAD
2072 * @arg @ref LL_I2C_MODE_AUTOEND
2073 * @arg @ref LL_I2C_MODE_SOFTEND
2074 * @arg @ref LL_I2C_MODE_SMBUS_RELOAD
2075 * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
2076 * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
2077 * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
2078 * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
2079 * @param Request This parameter can be one of the following values:
2080 * @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
2081 * @arg @ref LL_I2C_GENERATE_STOP
2082 * @arg @ref LL_I2C_GENERATE_START_READ
2083 * @arg @ref LL_I2C_GENERATE_START_WRITE
2084 * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
2085 * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
2086 * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
2087 * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
2088 * @retval None
2089 */
2090 __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
2091 uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
2092 {
2093 MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
2094 I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
2095 SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
2096 }
2097
2098 /**
2099 * @brief Indicate the value of transfer direction (slave mode).
2100 * @note RESET: Write transfer, Slave enters in receiver mode.
2101 * SET: Read transfer, Slave enters in transmitter mode.
2102 * @rmtoll ISR DIR LL_I2C_GetTransferDirection
2103 * @param I2Cx I2C Instance.
2104 * @retval Returned value can be one of the following values:
2105 * @arg @ref LL_I2C_DIRECTION_WRITE
2106 * @arg @ref LL_I2C_DIRECTION_READ
2107 */
2108 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
2109 {
2110 return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
2111 }
2112
2113 /**
2114 * @brief Return the slave matched address.
2115 * @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode
2116 * @param I2Cx I2C Instance.
2117 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
2118 */
2119 __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
2120 {
2121 return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
2122 }
2123
2124 /**
2125 * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
2126 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2127 * SMBus feature is supported by the I2Cx Instance.
2128 * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
2129 * This bit has no effect when RELOAD bit is set.
2130 * This bit has no effect in device mode when SBC bit is not set.
2131 * @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
2132 * @param I2Cx I2C Instance.
2133 * @retval None
2134 */
2135 __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
2136 {
2137 SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
2138 }
2139
2140 /**
2141 * @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
2142 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2143 * SMBus feature is supported by the I2Cx Instance.
2144 * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
2145 * @param I2Cx I2C Instance.
2146 * @retval State of bit (1 or 0).
2147 */
2148 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
2149 {
2150 return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
2151 }
2152
2153 /**
2154 * @brief Get the SMBus Packet Error byte calculated.
2155 * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2156 * SMBus feature is supported by the I2Cx Instance.
2157 * @rmtoll PECR PEC LL_I2C_GetSMBusPEC
2158 * @param I2Cx I2C Instance.
2159 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
2160 */
2161 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
2162 {
2163 return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
2164 }
2165
2166 /**
2167 * @brief Read Receive Data register.
2168 * @rmtoll RXDR RXDATA LL_I2C_ReceiveData8
2169 * @param I2Cx I2C Instance.
2170 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
2171 */
2172 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
2173 {
2174 return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
2175 }
2176
2177 /**
2178 * @brief Write in Transmit Data Register .
2179 * @rmtoll TXDR TXDATA LL_I2C_TransmitData8
2180 * @param I2Cx I2C Instance.
2181 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
2182 * @retval None
2183 */
2184 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
2185 {
2186 WRITE_REG(I2Cx->TXDR, Data);
2187 }
2188
2189 /**
2190 * @}
2191 */
2192
2193 #if defined(USE_FULL_LL_DRIVER)
2194 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
2195 * @{
2196 */
2197
2198 ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
2199 ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx);
2200 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
2201
2202
2203 /**
2204 * @}
2205 */
2206 #endif /* USE_FULL_LL_DRIVER */
2207
2208 /**
2209 * @}
2210 */
2211
2212 /**
2213 * @}
2214 */
2215
2216 #endif /* I2C1 || I2C2 || I2C3 || I2C4 || I2C5 */
2217
2218 /**
2219 * @}
2220 */
2221
2222 #ifdef __cplusplus
2223 }
2224 #endif
2225
2226 #endif /* STM32H7xx_LL_I2C_H */
2227
2228 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/