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Merge pull request #11270 from haslinghuis/rename_attr
[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_ll_lptim.h
blob25290037678e7250b8669ebd7b3f0efd1e75f26a
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_lptim.h
4 * @author MCD Application Team
5 * @brief Header file of LPTIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_LL_LPTIM_H
22 #define STM32H7xx_LL_LPTIM_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx.h"
30
31 /** @addtogroup STM32H7xx_LL_Driver
32 * @{
33 */
34
35 #if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4) || defined (LPTIM5)
36
37 /** @defgroup LPTIM_LL LPTIM
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45
46 /* Private macros ------------------------------------------------------------*/
47 #if defined(USE_FULL_LL_DRIVER)
48 /** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
49 * @{
50 */
51 /**
52 * @}
53 */
54 #endif /*USE_FULL_LL_DRIVER*/
55
56 /* Exported types ------------------------------------------------------------*/
57 #if defined(USE_FULL_LL_DRIVER)
58 /** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
59 * @{
60 */
61
62 /**
63 * @brief LPTIM Init structure definition
64 */
65 typedef struct
66 {
67 uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
68 This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
69
70 This feature can be modified afterwards using unitary function @ref LL_LPTIM_SetClockSource().*/
71
72 uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
73 This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
74
75 This feature can be modified afterwards using using unitary function @ref LL_LPTIM_SetPrescaler().*/
76
77 uint32_t Waveform; /*!< Specifies the waveform shape.
78 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
79
80 This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
81
82 uint32_t Polarity; /*!< Specifies waveform polarity.
83 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY.
84
85 This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
86 } LL_LPTIM_InitTypeDef;
87
88 /**
89 * @}
90 */
91 #endif /* USE_FULL_LL_DRIVER */
92
93 /* Exported constants --------------------------------------------------------*/
94 /** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
95 * @{
96 */
97
98 /** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
99 * @brief Flags defines which can be used with LL_LPTIM_ReadReg function
100 * @{
101 */
102 #define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /*!< Compare match */
103 #define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */
104 #define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */
105 #define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */
106 #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */
107 #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */
108 #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */
109 /**
110 * @}
111 */
112
113 /** @defgroup LPTIM_LL_EC_IT IT Defines
114 * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
115 * @{
116 */
117 #define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match Interrupt Enable */
118 #define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match Interrupt Enable */
119 #define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger valid edge Interrupt Enable */
120 #define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK Interrupt Enable */
121 #define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK Interrupt Enable */
122 #define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Direction change to UP Interrupt Enable */
123 #define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Direction change to down Interrupt Enable */
124 /**
125 * @}
126 */
127
128 /** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
129 * @{
130 */
131 #define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
132 #define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
133 /**
134 * @}
135 */
136
137 /** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
138 * @{
139 */
140 #define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/
141 #define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
142 /**
143 * @}
144 */
145
146 /** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
147 * @{
148 */
149 #define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/
150 #define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
151 /**
152 * @}
153 */
154
155 /** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
156 * @{
157 */
158 #define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINOUS or SINGLE*/
159 #define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
160 /**
161 * @}
162 */
163
164 /** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
165 * @{
166 */
167 #define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
168 #define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
169 /**
170 * @}
171 */
172
173 /** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
174 * @{
175 */
176 #define LL_LPTIM_PRESCALER_DIV1 0x00000000U /*!<Prescaler division factor is set to 1*/
177 #define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 /*!<Prescaler division factor is set to 2*/
178 #define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 /*!<Prescaler division factor is set to 4*/
179 #define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
180 #define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 /*!<Prescaler division factor is set to 16*/
181 #define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
182 #define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
183 #define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /*!<Prescaler division factor is set to 128*/
184 /**
185 * @}
186 */
187
188 /** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
189 * @{
190 */
191 #define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/
192 #define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/
193 #define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/
194 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
195 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to RTC Tamper 2*/
196 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 3*/
197 #define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP1 output*/
198 #define LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL /*!<External input trigger is connected to COMP2 output*/
199 #define LL_LPTIM_TRIG_SOURCE_LPTIM2 0x00000000U /*!<External input trigger is connected to LPTIM2 output*/
200 #define LL_LPTIM_TRIG_SOURCE_LPTIM3 LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to LPTIM3 output*/
201 #define LL_LPTIM_TRIG_SOURCE_LPTIM4 LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to LPTIM4 output*/
202 #define LL_LPTIM_TRIG_SOURCE_LPTIM5 (LPTIM_CFGR_TRIGSEL_1|LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to LPTIM5 output*/
203 #define LL_LPTIM_TRIG_SOURCE_SAI1_FS_A LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to SAI1 FS A output*/
204 #define LL_LPTIM_TRIG_SOURCE_SAI1_FS_B (LPTIM_CFGR_TRIGSEL_2|LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to SAI1 FS B output*/
205 #define LL_LPTIM_TRIG_SOURCE_SAI2_FS_A LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to SAI2 FS A output*/
206 #define LL_LPTIM_TRIG_SOURCE_SAI2_FS_B (LPTIM_CFGR_TRIGSEL_2|LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to SAI2 FS B output*/
207 #define LL_LPTIM_TRIG_SOURCE_SAI4_FS_A (LPTIM_CFGR_TRIGSEL_1|LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to SAI4 FS A output*/
208 #define LL_LPTIM_TRIG_SOURCE_SAI4_FS_B LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to SAI4 FS B output*/
209 #define LL_LPTIM_TRIG_SOURCE_DFSDM2_BRK (LPTIM_CFGR_TRIGSEL_2|LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to DFSDM2_BRK[0] */
210 /**
211 * @}
212 */
213
214 /** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
215 * @{
216 */
217 #define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/
218 #define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
219 #define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
220 #define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
221 /**
222 * @}
223 */
224
225 /** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
226 * @{
227 */
228 #define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
229 #define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
230 #define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/
231 /**
232 * @}
233 */
234
235 /** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
236 * @{
237 */
238 #define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
239 #define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
240 /**
241 * @}
242 */
243
244 /** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
245 * @{
246 */
247 #define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/
248 #define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
249 #define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
250 #define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
251 /**
252 * @}
253 */
254
255 /** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
256 * @{
257 */
258 #define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
259 #define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
260 #define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
261 /**
262 * @}
263 */
264
265 /** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
266 * @{
267 */
268 #define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
269 #define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
270 #define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
271 /**
272 * @}
273 */
274
275 /** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
276 * @{
277 */
278 #define LL_LPTIM_INPUT1_SRC_GPIO 0x00000000U /*!< For LPTIM1 and LPTIM2 */
279 #define LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_CFGR2_IN1SEL_0 /*!< For LPTIM1 and LPTIM2 */
280 #define LL_LPTIM_INPUT1_SRC_COMP2 LPTIM_CFGR2_IN1SEL_1 /*!< For LPTIM2 */
281 #define LL_LPTIM_INPUT1_SRC_COMP1_COMP2 (LPTIM_CFGR2_IN1SEL_1 | LPTIM_CFGR2_IN1SEL_0) /*!< For LPTIM2 */
282 #define LL_LPTIM_INPUT1_SRC_SAI4_FS_A LPTIM_CFGR2_IN1SEL_0 /*!< For LPTIM3 */
283 #define LL_LPTIM_INPUT1_SRC_SAI4_FS_B LPTIM_CFGR2_IN1SEL_1 /*!< For LPTIM3 */
284 /**
285 * @}
286 */
287
288 /** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source
289 * @{
290 */
291 #define LL_LPTIM_INPUT2_SRC_GPIO 0x00000000U /*!< For LPTIM1 */
292 #define LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_CFGR2_IN2SEL_0 /*!< For LPTIM1 */
293 /**
294 * @}
295 */
296
297 /**
298 * @}
299 */
300
301 /* Exported macro ------------------------------------------------------------*/
302 /** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
303 * @{
304 */
305
306 /** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
307 * @{
308 */
309
310 /**
311 * @brief Write a value in LPTIM register
312 * @param __INSTANCE__ LPTIM Instance
313 * @param __REG__ Register to be written
314 * @param __VALUE__ Value to be written in the register
315 * @retval None
316 */
317 #define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
318
319 /**
320 * @brief Read a value in LPTIM register
321 * @param __INSTANCE__ LPTIM Instance
322 * @param __REG__ Register to be read
323 * @retval Register value
324 */
325 #define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
326 /**
327 * @}
328 */
329
330 /**
331 * @}
332 */
333
334 /* Exported functions --------------------------------------------------------*/
335 /** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
336 * @{
337 */
338
339 #if defined(USE_FULL_LL_DRIVER)
340 /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
341 * @{
342 */
343
344 ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
345 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
346 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
347 void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx);
348 /**
349 * @}
350 */
351 #endif /* USE_FULL_LL_DRIVER */
352
353 /** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
354 * @{
355 */
356
357 /**
358 * @brief Enable the LPTIM instance
359 * @note After setting the ENABLE bit, a delay of two counter clock is needed
360 * before the LPTIM instance is actually enabled.
361 * @rmtoll CR ENABLE LL_LPTIM_Enable
362 * @param LPTIMx Low-Power Timer instance
363 * @retval None
364 */
365 __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
366 {
367 SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
368 }
369
370 /**
371 * @brief Indicates whether the LPTIM instance is enabled.
372 * @rmtoll CR ENABLE LL_LPTIM_IsEnabled
373 * @param LPTIMx Low-Power Timer instance
374 * @retval State of bit (1 or 0).
375 */
376 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
377 {
378 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
379 }
380
381 /**
382 * @brief Starts the LPTIM counter in the desired mode.
383 * @note LPTIM instance must be enabled before starting the counter.
384 * @note It is possible to change on the fly from One Shot mode to
385 * Continuous mode.
386 * @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n
387 * CR SNGSTRT LL_LPTIM_StartCounter
388 * @param LPTIMx Low-Power Timer instance
389 * @param OperatingMode This parameter can be one of the following values:
390 * @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
391 * @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
392 * @retval None
393 */
394 __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
395 {
396 MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
397 }
398
399 /**
400 * @brief Enable reset after read.
401 * @note After calling this function any read access to LPTIM_CNT
402 * register will asynchronously reset the LPTIM_CNT register content.
403 * @rmtoll CR RSTARE LL_LPTIM_EnableResetAfterRead
404 * @param LPTIMx Low-Power Timer instance
405 * @retval None
406 */
407 __STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx)
408 {
409 SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
410 }
411
412 /**
413 * @brief Disable reset after read.
414 * @rmtoll CR RSTARE LL_LPTIM_DisableResetAfterRead
415 * @param LPTIMx Low-Power Timer instance
416 * @retval None
417 */
418 __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
419 {
420 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
421 }
422
423 /**
424 * @brief Indicate whether the reset after read feature is enabled.
425 * @rmtoll CR RSTARE LL_LPTIM_IsEnabledResetAfterRead
426 * @param LPTIMx Low-Power Timer instance
427 * @retval State of bit (1 or 0).
428 */
429 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef *LPTIMx)
430 {
431 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));
432 }
433
434 /**
435 * @brief Reset of the LPTIM_CNT counter register (synchronous).
436 * @note Due to the synchronous nature of this reset, it only takes
437 * place after a synchronization delay of 3 LPTIM core clock cycles
438 * (LPTIM core clock may be different from APB clock).
439 * @note COUNTRST is automatically cleared by hardware
440 * @rmtoll CR COUNTRST LL_LPTIM_ResetCounter\n
441 * @param LPTIMx Low-Power Timer instance
442 * @retval None
443 */
444 __STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx)
445 {
446 SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST);
447 }
448
449 /**
450 * @brief Set the LPTIM registers update mode (enable/disable register preload)
451 * @note This function must be called when the LPTIM instance is disabled.
452 * @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode
453 * @param LPTIMx Low-Power Timer instance
454 * @param UpdateMode This parameter can be one of the following values:
455 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
456 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
457 * @retval None
458 */
459 __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
460 {
461 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
462 }
463
464 /**
465 * @brief Get the LPTIM registers update mode
466 * @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode
467 * @param LPTIMx Low-Power Timer instance
468 * @retval Returned value can be one of the following values:
469 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
470 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
471 */
472 __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx)
473 {
474 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
475 }
476
477 /**
478 * @brief Set the auto reload value
479 * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
480 * @note After a write to the LPTIMx_ARR register a new write operation to the
481 * same register can only be performed when the previous write operation
482 * is completed. Any successive write before the ARROK flag is set, will
483 * lead to unpredictable results.
484 * @note autoreload value be strictly greater than the compare value.
485 * @rmtoll ARR ARR LL_LPTIM_SetAutoReload
486 * @param LPTIMx Low-Power Timer instance
487 * @param AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
488 * @retval None
489 */
490 __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
491 {
492 MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
493 }
494
495 /**
496 * @brief Get actual auto reload value
497 * @rmtoll ARR ARR LL_LPTIM_GetAutoReload
498 * @param LPTIMx Low-Power Timer instance
499 * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
500 */
501 __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx)
502 {
503 return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
504 }
505
506 /**
507 * @brief Set the compare value
508 * @note After a write to the LPTIMx_CMP register a new write operation to the
509 * same register can only be performed when the previous write operation
510 * is completed. Any successive write before the CMPOK flag is set, will
511 * lead to unpredictable results.
512 * @rmtoll CMP CMP LL_LPTIM_SetCompare
513 * @param LPTIMx Low-Power Timer instance
514 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
515 * @retval None
516 */
517 __STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
518 {
519 MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMP, CompareValue);
520 }
521
522 /**
523 * @brief Get actual compare value
524 * @rmtoll CMP CMP LL_LPTIM_GetCompare
525 * @param LPTIMx Low-Power Timer instance
526 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
527 */
528 __STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx)
529 {
530 return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP));
531 }
532
533 /**
534 * @brief Get actual counter value
535 * @note When the LPTIM instance is running with an asynchronous clock, reading
536 * the LPTIMx_CNT register may return unreliable values. So in this case
537 * it is necessary to perform two consecutive read accesses and verify
538 * that the two returned values are identical.
539 * @rmtoll CNT CNT LL_LPTIM_GetCounter
540 * @param LPTIMx Low-Power Timer instance
541 * @retval Counter value
542 */
543 __STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *LPTIMx)
544 {
545 return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
546 }
547
548 /**
549 * @brief Set the counter mode (selection of the LPTIM counter clock source).
550 * @note The counter mode can be set only when the LPTIM instance is disabled.
551 * @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode
552 * @param LPTIMx Low-Power Timer instance
553 * @param CounterMode This parameter can be one of the following values:
554 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
555 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
556 * @retval None
557 */
558 __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
559 {
560 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
561 }
562
563 /**
564 * @brief Get the counter mode
565 * @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode
566 * @param LPTIMx Low-Power Timer instance
567 * @retval Returned value can be one of the following values:
568 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
569 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
570 */
571 __STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *LPTIMx)
572 {
573 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
574 }
575
576 /**
577 * @brief Configure the LPTIM instance output (LPTIMx_OUT)
578 * @note This function must be called when the LPTIM instance is disabled.
579 * @note Regarding the LPTIM output polarity the change takes effect
580 * immediately, so the output default value will change immediately after
581 * the polarity is re-configured, even before the timer is enabled.
582 * @rmtoll CFGR WAVE LL_LPTIM_ConfigOutput\n
583 * CFGR WAVPOL LL_LPTIM_ConfigOutput
584 * @param LPTIMx Low-Power Timer instance
585 * @param Waveform This parameter can be one of the following values:
586 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
587 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
588 * @param Polarity This parameter can be one of the following values:
589 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
590 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
591 * @retval None
592 */
593 __STATIC_INLINE void LL_LPTIM_ConfigOutput(LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
594 {
595 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL, Waveform | Polarity);
596 }
597
598 /**
599 * @brief Set waveform shape
600 * @rmtoll CFGR WAVE LL_LPTIM_SetWaveform
601 * @param LPTIMx Low-Power Timer instance
602 * @param Waveform This parameter can be one of the following values:
603 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
604 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
605 * @retval None
606 */
607 __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
608 {
609 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
610 }
611
612 /**
613 * @brief Get actual waveform shape
614 * @rmtoll CFGR WAVE LL_LPTIM_GetWaveform
615 * @param LPTIMx Low-Power Timer instance
616 * @retval Returned value can be one of the following values:
617 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
618 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
619 */
620 __STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx)
621 {
622 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
623 }
624
625 /**
626 * @brief Set output polarity
627 * @rmtoll CFGR WAVPOL LL_LPTIM_SetPolarity
628 * @param LPTIMx Low-Power Timer instance
629 * @param Polarity This parameter can be one of the following values:
630 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
631 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
632 * @retval None
633 */
634 __STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
635 {
636 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity);
637 }
638
639 /**
640 * @brief Get actual output polarity
641 * @rmtoll CFGR WAVPOL LL_LPTIM_GetPolarity
642 * @param LPTIMx Low-Power Timer instance
643 * @retval Returned value can be one of the following values:
644 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
645 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
646 */
647 __STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(LPTIM_TypeDef *LPTIMx)
648 {
649 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL));
650 }
651
652 /**
653 * @brief Set actual prescaler division ratio.
654 * @note This function must be called when the LPTIM instance is disabled.
655 * @note When the LPTIM is configured to be clocked by an internal clock source
656 * and the LPTIM counter is configured to be updated by active edges
657 * detected on the LPTIM external Input1, the internal clock provided to
658 * the LPTIM must be not be prescaled.
659 * @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler
660 * @param LPTIMx Low-Power Timer instance
661 * @param Prescaler This parameter can be one of the following values:
662 * @arg @ref LL_LPTIM_PRESCALER_DIV1
663 * @arg @ref LL_LPTIM_PRESCALER_DIV2
664 * @arg @ref LL_LPTIM_PRESCALER_DIV4
665 * @arg @ref LL_LPTIM_PRESCALER_DIV8
666 * @arg @ref LL_LPTIM_PRESCALER_DIV16
667 * @arg @ref LL_LPTIM_PRESCALER_DIV32
668 * @arg @ref LL_LPTIM_PRESCALER_DIV64
669 * @arg @ref LL_LPTIM_PRESCALER_DIV128
670 * @retval None
671 */
672 __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
673 {
674 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
675 }
676
677 /**
678 * @brief Get actual prescaler division ratio.
679 * @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler
680 * @param LPTIMx Low-Power Timer instance
681 * @retval Returned value can be one of the following values:
682 * @arg @ref LL_LPTIM_PRESCALER_DIV1
683 * @arg @ref LL_LPTIM_PRESCALER_DIV2
684 * @arg @ref LL_LPTIM_PRESCALER_DIV4
685 * @arg @ref LL_LPTIM_PRESCALER_DIV8
686 * @arg @ref LL_LPTIM_PRESCALER_DIV16
687 * @arg @ref LL_LPTIM_PRESCALER_DIV32
688 * @arg @ref LL_LPTIM_PRESCALER_DIV64
689 * @arg @ref LL_LPTIM_PRESCALER_DIV128
690 */
691 __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx)
692 {
693 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
694 }
695
696 /**
697 * @brief Set LPTIM input 1 source (default GPIO).
698 * @rmtoll CFGR2 IN1SEL LL_LPTIM_SetInput1Src
699 * @param LPTIMx Low-Power Timer instance
700 * @param Src This parameter can be one of the following values:
701 * @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
702 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1
703 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP2
704 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1_COMP2
705 * @arg @ref LL_LPTIM_INPUT1_SRC_SAI4_FS_A
706 * @arg @ref LL_LPTIM_INPUT1_SRC_SAI4_FS_B
707 * @retval None
708 */
709 __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
710 {
711 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN1SEL, Src);
712 }
713
714 /**
715 * @brief Set LPTIM input 2 source (default GPIO).
716 * @rmtoll CFGR2 IN2SEL LL_LPTIM_SetInput2Src
717 * @param LPTIMx Low-Power Timer instance
718 * @param Src This parameter can be one of the following values:
719 * @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
720 * @arg @ref LL_LPTIM_INPUT2_SRC_COMP2
721 * @retval None
722 */
723 __STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
724 {
725 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN2SEL, Src);
726 }
727
728 /**
729 * @}
730 */
731
732 /** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
733 * @{
734 */
735
736 /**
737 * @brief Enable the timeout function
738 * @note This function must be called when the LPTIM instance is disabled.
739 * @note The first trigger event will start the timer, any successive trigger
740 * event will reset the counter and the timer will restart.
741 * @note The timeout value corresponds to the compare value; if no trigger
742 * occurs within the expected time frame, the MCU is waked-up by the
743 * compare match event.
744 * @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout
745 * @param LPTIMx Low-Power Timer instance
746 * @retval None
747 */
748 __STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
749 {
750 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
751 }
752
753 /**
754 * @brief Disable the timeout function
755 * @note This function must be called when the LPTIM instance is disabled.
756 * @note A trigger event arriving when the timer is already started will be
757 * ignored.
758 * @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout
759 * @param LPTIMx Low-Power Timer instance
760 * @retval None
761 */
762 __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
763 {
764 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
765 }
766
767 /**
768 * @brief Indicate whether the timeout function is enabled.
769 * @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
770 * @param LPTIMx Low-Power Timer instance
771 * @retval State of bit (1 or 0).
772 */
773 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
774 {
775 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
776 }
777
778 /**
779 * @brief Start the LPTIM counter
780 * @note This function must be called when the LPTIM instance is disabled.
781 * @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw
782 * @param LPTIMx Low-Power Timer instance
783 * @retval None
784 */
785 __STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
786 {
787 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
788 }
789
790 /**
791 * @brief Configure the external trigger used as a trigger event for the LPTIM.
792 * @note This function must be called when the LPTIM instance is disabled.
793 * @note An internal clock source must be present when a digital filter is
794 * required for the trigger.
795 * @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n
796 * CFGR TRGFLT LL_LPTIM_ConfigTrigger\n
797 * CFGR TRIGEN LL_LPTIM_ConfigTrigger
798 * @param LPTIMx Low-Power Timer instance
799 * @param Source This parameter can be one of the following values:
800 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
801 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
802 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
803 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
804 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
805 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
806 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
807 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
808 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM2 (*)
809 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM3 (*)
810 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM4 (*)
811 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM5 (*)
812 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1_FS_A (*)
813 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1_FS_B (*)
814 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_A (*)
815 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_B (*)
816 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI4_FS_A (*)
817 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI4_FS_B (*)
818 * @arg @ref LL_LPTIM_TRIG_SOURCE_DFSDM2_BRK (*)
819 *
820 * (*) Value not defined in all devices. \n
821 *
822 * @param Filter This parameter can be one of the following values:
823 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
824 * @arg @ref LL_LPTIM_TRIG_FILTER_2
825 * @arg @ref LL_LPTIM_TRIG_FILTER_4
826 * @arg @ref LL_LPTIM_TRIG_FILTER_8
827 * @param Polarity This parameter can be one of the following values:
828 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
829 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
830 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
831 * @retval None
832 */
833 __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
834 {
835 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
836 }
837
838 /**
839 * @brief Get actual external trigger source.
840 * @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource
841 * @param LPTIMx Low-Power Timer instance
842 * @retval Returned value can be one of the following values:
843 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
844 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
845 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
846 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
847 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
848 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
849 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
850 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
851 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM2 (*)
852 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM3 (*)
853 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM4 (*)
854 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM5 (*)
855 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1_FS_A (*)
856 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1_FS_B (*)
857 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_A (*)
858 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_B (*)
859 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI4_FS_A (*)
860 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI4_FS_B (*)
861 * @arg @ref LL_LPTIM_TRIG_SOURCE_DFSDM2_BRK (*)
862 *
863 * (*) Value not defined in all devices. \n
864 *
865 */
866 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx)
867 {
868 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
869 }
870
871 /**
872 * @brief Get actual external trigger filter.
873 * @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter
874 * @param LPTIMx Low-Power Timer instance
875 * @retval Returned value can be one of the following values:
876 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
877 * @arg @ref LL_LPTIM_TRIG_FILTER_2
878 * @arg @ref LL_LPTIM_TRIG_FILTER_4
879 * @arg @ref LL_LPTIM_TRIG_FILTER_8
880 */
881 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx)
882 {
883 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
884 }
885
886 /**
887 * @brief Get actual external trigger polarity.
888 * @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
889 * @param LPTIMx Low-Power Timer instance
890 * @retval Returned value can be one of the following values:
891 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
892 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
893 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
894 */
895 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx)
896 {
897 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
898 }
899
900 /**
901 * @}
902 */
903
904 /** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
905 * @{
906 */
907
908 /**
909 * @brief Set the source of the clock used by the LPTIM instance.
910 * @note This function must be called when the LPTIM instance is disabled.
911 * @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource
912 * @param LPTIMx Low-Power Timer instance
913 * @param ClockSource This parameter can be one of the following values:
914 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
915 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
916 * @retval None
917 */
918 __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
919 {
920 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
921 }
922
923 /**
924 * @brief Get actual LPTIM instance clock source.
925 * @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource
926 * @param LPTIMx Low-Power Timer instance
927 * @retval Returned value can be one of the following values:
928 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
929 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
930 */
931 __STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx)
932 {
933 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
934 }
935
936 /**
937 * @brief Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.
938 * @note This function must be called when the LPTIM instance is disabled.
939 * @note When both external clock signal edges are considered active ones,
940 * the LPTIM must also be clocked by an internal clock source with a
941 * frequency equal to at least four times the external clock frequency.
942 * @note An internal clock source must be present when a digital filter is
943 * required for external clock.
944 * @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n
945 * CFGR CKPOL LL_LPTIM_ConfigClock
946 * @param LPTIMx Low-Power Timer instance
947 * @param ClockFilter This parameter can be one of the following values:
948 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
949 * @arg @ref LL_LPTIM_CLK_FILTER_2
950 * @arg @ref LL_LPTIM_CLK_FILTER_4
951 * @arg @ref LL_LPTIM_CLK_FILTER_8
952 * @param ClockPolarity This parameter can be one of the following values:
953 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
954 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
955 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
956 * @retval None
957 */
958 __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
959 {
960 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
961 }
962
963 /**
964 * @brief Get actual clock polarity
965 * @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity
966 * @param LPTIMx Low-Power Timer instance
967 * @retval Returned value can be one of the following values:
968 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
969 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
970 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
971 */
972 __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx)
973 {
974 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
975 }
976
977 /**
978 * @brief Get actual clock digital filter
979 * @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter
980 * @param LPTIMx Low-Power Timer instance
981 * @retval Returned value can be one of the following values:
982 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
983 * @arg @ref LL_LPTIM_CLK_FILTER_2
984 * @arg @ref LL_LPTIM_CLK_FILTER_4
985 * @arg @ref LL_LPTIM_CLK_FILTER_8
986 */
987 __STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx)
988 {
989 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
990 }
991
992 /**
993 * @}
994 */
995
996 /** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
997 * @{
998 */
999
1000 /**
1001 * @brief Configure the encoder mode.
1002 * @note This function must be called when the LPTIM instance is disabled.
1003 * @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode
1004 * @param LPTIMx Low-Power Timer instance
1005 * @param EncoderMode This parameter can be one of the following values:
1006 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1007 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1008 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1009 * @retval None
1010 */
1011 __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
1012 {
1013 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
1014 }
1015
1016 /**
1017 * @brief Get actual encoder mode.
1018 * @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode
1019 * @param LPTIMx Low-Power Timer instance
1020 * @retval Returned value can be one of the following values:
1021 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1022 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1023 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1024 */
1025 __STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx)
1026 {
1027 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
1028 }
1029
1030 /**
1031 * @brief Enable the encoder mode
1032 * @note This function must be called when the LPTIM instance is disabled.
1033 * @note In this mode the LPTIM instance must be clocked by an internal clock
1034 * source. Also, the prescaler division ratio must be equal to 1.
1035 * @note LPTIM instance must be configured in continuous mode prior enabling
1036 * the encoder mode.
1037 * @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode
1038 * @param LPTIMx Low-Power Timer instance
1039 * @retval None
1040 */
1041 __STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
1042 {
1043 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1044 }
1045
1046 /**
1047 * @brief Disable the encoder mode
1048 * @note This function must be called when the LPTIM instance is disabled.
1049 * @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode
1050 * @param LPTIMx Low-Power Timer instance
1051 * @retval None
1052 */
1053 __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
1054 {
1055 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1056 }
1057
1058 /**
1059 * @brief Indicates whether the LPTIM operates in encoder mode.
1060 * @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode
1061 * @param LPTIMx Low-Power Timer instance
1062 * @retval State of bit (1 or 0).
1063 */
1064 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
1065 {
1066 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
1067 }
1068
1069 /**
1070 * @}
1071 */
1072
1073 /** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
1074 * @{
1075 */
1076
1077 /**
1078 * @brief Clear the compare match flag (CMPMCF)
1079 * @rmtoll ICR CMPMCF LL_LPTIM_ClearFLAG_CMPM
1080 * @param LPTIMx Low-Power Timer instance
1081 * @retval None
1082 */
1083 __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
1084 {
1085 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF);
1086 }
1087
1088 /**
1089 * @brief Inform application whether a compare match interrupt has occurred.
1090 * @rmtoll ISR CMPM LL_LPTIM_IsActiveFlag_CMPM
1091 * @param LPTIMx Low-Power Timer instance
1092 * @retval State of bit (1 or 0).
1093 */
1094 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
1095 {
1096 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL));
1097 }
1098
1099 /**
1100 * @brief Clear the autoreload match flag (ARRMCF)
1101 * @rmtoll ICR ARRMCF LL_LPTIM_ClearFLAG_ARRM
1102 * @param LPTIMx Low-Power Timer instance
1103 * @retval None
1104 */
1105 __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
1106 {
1107 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
1108 }
1109
1110 /**
1111 * @brief Inform application whether a autoreload match interrupt has occurred.
1112 * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
1113 * @param LPTIMx Low-Power Timer instance
1114 * @retval State of bit (1 or 0).
1115 */
1116 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
1117 {
1118 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
1119 }
1120
1121 /**
1122 * @brief Clear the external trigger valid edge flag(EXTTRIGCF).
1123 * @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
1124 * @param LPTIMx Low-Power Timer instance
1125 * @retval None
1126 */
1127 __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1128 {
1129 SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
1130 }
1131
1132 /**
1133 * @brief Inform application whether a valid edge on the selected external trigger input has occurred.
1134 * @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
1135 * @param LPTIMx Low-Power Timer instance
1136 * @retval State of bit (1 or 0).
1137 */
1138 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1139 {
1140 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
1141 }
1142
1143 /**
1144 * @brief Clear the compare register update interrupt flag (CMPOKCF).
1145 * @rmtoll ICR CMPOKCF LL_LPTIM_ClearFlag_CMPOK
1146 * @param LPTIMx Low-Power Timer instance
1147 * @retval None
1148 */
1149 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
1150 {
1151 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPOKCF);
1152 }
1153
1154 /**
1155 * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed. If so, a new one can be initiated.
1156 * @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK
1157 * @param LPTIMx Low-Power Timer instance
1158 * @retval State of bit (1 or 0).
1159 */
1160 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
1161 {
1162 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL));
1163 }
1164
1165 /**
1166 * @brief Clear the autoreload register update interrupt flag (ARROKCF).
1167 * @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
1168 * @param LPTIMx Low-Power Timer instance
1169 * @retval None
1170 */
1171 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
1172 {
1173 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
1174 }
1175
1176 /**
1177 * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed. If so, a new one can be initiated.
1178 * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
1179 * @param LPTIMx Low-Power Timer instance
1180 * @retval State of bit (1 or 0).
1181 */
1182 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
1183 {
1184 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
1185 }
1186
1187 /**
1188 * @brief Clear the counter direction change to up interrupt flag (UPCF).
1189 * @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP
1190 * @param LPTIMx Low-Power Timer instance
1191 * @retval None
1192 */
1193 __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
1194 {
1195 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
1196 }
1197
1198 /**
1199 * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).
1200 * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP
1201 * @param LPTIMx Low-Power Timer instance
1202 * @retval State of bit (1 or 0).
1203 */
1204 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
1205 {
1206 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
1207 }
1208
1209 /**
1210 * @brief Clear the counter direction change to down interrupt flag (DOWNCF).
1211 * @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
1212 * @param LPTIMx Low-Power Timer instance
1213 * @retval None
1214 */
1215 __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
1216 {
1217 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
1218 }
1219
1220 /**
1221 * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).
1222 * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
1223 * @param LPTIMx Low-Power Timer instance
1224 * @retval State of bit (1 or 0).
1225 */
1226 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
1227 {
1228 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
1229 }
1230
1231 /**
1232 * @}
1233 */
1234
1235 /** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
1236 * @{
1237 */
1238
1239 /**
1240 * @brief Enable compare match interrupt (CMPMIE).
1241 * @rmtoll IER CMPMIE LL_LPTIM_EnableIT_CMPM
1242 * @param LPTIMx Low-Power Timer instance
1243 * @retval None
1244 */
1245 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef *LPTIMx)
1246 {
1247 SET_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
1248 }
1249
1250 /**
1251 * @brief Disable compare match interrupt (CMPMIE).
1252 * @rmtoll IER CMPMIE LL_LPTIM_DisableIT_CMPM
1253 * @param LPTIMx Low-Power Timer instance
1254 * @retval None
1255 */
1256 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
1257 {
1258 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
1259 }
1260
1261 /**
1262 * @brief Indicates whether the compare match interrupt (CMPMIE) is enabled.
1263 * @rmtoll IER CMPMIE LL_LPTIM_IsEnabledIT_CMPM
1264 * @param LPTIMx Low-Power Timer instance
1265 * @retval State of bit (1 or 0).
1266 */
1267 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
1268 {
1269 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL));
1270 }
1271
1272 /**
1273 * @brief Enable autoreload match interrupt (ARRMIE).
1274 * @rmtoll IER ARRMIE LL_LPTIM_EnableIT_ARRM
1275 * @param LPTIMx Low-Power Timer instance
1276 * @retval None
1277 */
1278 __STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
1279 {
1280 SET_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
1281 }
1282
1283 /**
1284 * @brief Disable autoreload match interrupt (ARRMIE).
1285 * @rmtoll IER ARRMIE LL_LPTIM_DisableIT_ARRM
1286 * @param LPTIMx Low-Power Timer instance
1287 * @retval None
1288 */
1289 __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
1290 {
1291 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
1292 }
1293
1294 /**
1295 * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
1296 * @rmtoll IER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
1297 * @param LPTIMx Low-Power Timer instance
1298 * @retval State of bit (1 or 0).
1299 */
1300 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
1301 {
1302 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL));
1303 }
1304
1305 /**
1306 * @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
1307 * @rmtoll IER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
1308 * @param LPTIMx Low-Power Timer instance
1309 * @retval None
1310 */
1311 __STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1312 {
1313 SET_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
1314 }
1315
1316 /**
1317 * @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
1318 * @rmtoll IER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
1319 * @param LPTIMx Low-Power Timer instance
1320 * @retval None
1321 */
1322 __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1323 {
1324 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
1325 }
1326
1327 /**
1328 * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
1329 * @rmtoll IER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
1330 * @param LPTIMx Low-Power Timer instance
1331 * @retval State of bit (1 or 0).
1332 */
1333 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1334 {
1335 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL));
1336 }
1337
1338 /**
1339 * @brief Enable compare register write completed interrupt (CMPOKIE).
1340 * @rmtoll IER CMPOKIE LL_LPTIM_EnableIT_CMPOK
1341 * @param LPTIMx Low-Power Timer instance
1342 * @retval None
1343 */
1344 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1345 {
1346 SET_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
1347 }
1348
1349 /**
1350 * @brief Disable compare register write completed interrupt (CMPOKIE).
1351 * @rmtoll IER CMPOKIE LL_LPTIM_DisableIT_CMPOK
1352 * @param LPTIMx Low-Power Timer instance
1353 * @retval None
1354 */
1355 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1356 {
1357 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
1358 }
1359
1360 /**
1361 * @brief Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
1362 * @rmtoll IER CMPOKIE LL_LPTIM_IsEnabledIT_CMPOK
1363 * @param LPTIMx Low-Power Timer instance
1364 * @retval State of bit (1 or 0).
1365 */
1366 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1367 {
1368 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL));
1369 }
1370
1371 /**
1372 * @brief Enable autoreload register write completed interrupt (ARROKIE).
1373 * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK
1374 * @param LPTIMx Low-Power Timer instance
1375 * @retval None
1376 */
1377 __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
1378 {
1379 SET_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
1380 }
1381
1382 /**
1383 * @brief Disable autoreload register write completed interrupt (ARROKIE).
1384 * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK
1385 * @param LPTIMx Low-Power Timer instance
1386 * @retval None
1387 */
1388 __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
1389 {
1390 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
1391 }
1392
1393 /**
1394 * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
1395 * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
1396 * @param LPTIMx Low-Power Timer instance
1397 * @retval State of bit(1 or 0).
1398 */
1399 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
1400 {
1401 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL));
1402 }
1403
1404 /**
1405 * @brief Enable direction change to up interrupt (UPIE).
1406 * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP
1407 * @param LPTIMx Low-Power Timer instance
1408 * @retval None
1409 */
1410 __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
1411 {
1412 SET_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
1413 }
1414
1415 /**
1416 * @brief Disable direction change to up interrupt (UPIE).
1417 * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP
1418 * @param LPTIMx Low-Power Timer instance
1419 * @retval None
1420 */
1421 __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
1422 {
1423 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
1424 }
1425
1426 /**
1427 * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
1428 * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
1429 * @param LPTIMx Low-Power Timer instance
1430 * @retval State of bit(1 or 0).
1431 */
1432 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
1433 {
1434 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL));
1435 }
1436
1437 /**
1438 * @brief Enable direction change to down interrupt (DOWNIE).
1439 * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN
1440 * @param LPTIMx Low-Power Timer instance
1441 * @retval None
1442 */
1443 __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
1444 {
1445 SET_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
1446 }
1447
1448 /**
1449 * @brief Disable direction change to down interrupt (DOWNIE).
1450 * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN
1451 * @param LPTIMx Low-Power Timer instance
1452 * @retval None
1453 */
1454 __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
1455 {
1456 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
1457 }
1458
1459 /**
1460 * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
1461 * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
1462 * @param LPTIMx Low-Power Timer instance
1463 * @retval State of bit(1 or 0).
1464 */
1465 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
1466 {
1467 return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL);
1468 }
1469
1470 /**
1471 * @}
1472 */
1473
1474 /**
1475 * @}
1476 */
1477
1478 /**
1479 * @}
1480 */
1481
1482 #endif /* LPTIM1 || LPTIM2 || LPTIM3 || LPTIM4 || LPTIM5 */
1483
1484 /**
1485 * @}
1486 */
1487
1488 #ifdef __cplusplus
1489 }
1490 #endif
1491
1492 #endif /* STM32H7xx_LL_LPTIM_H */
1493
1494 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/