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Merge pull request #11270 from haslinghuis/rename_attr
[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_ll_lpuart.h
blob1471bdd16219dc6c816385d52c5f060c7d3e217b
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_lpuart.h
4 * @author MCD Application Team
5 * @brief Header file of LPUART LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_LL_LPUART_H
22 #define STM32H7xx_LL_LPUART_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx.h"
30
31 /** @addtogroup STM32H7xx_LL_Driver
32 * @{
33 */
34
35 #if defined (LPUART1)
36
37 /** @defgroup LPUART_LL LPUART
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /** @defgroup LPUART_LL_Private_Variables LPUART Private Variables
44 * @{
45 */
46 /* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */
47 static const uint16_t LPUART_PRESCALER_TAB[] =
48 {
49 (uint16_t)1,
50 (uint16_t)2,
51 (uint16_t)4,
52 (uint16_t)6,
53 (uint16_t)8,
54 (uint16_t)10,
55 (uint16_t)12,
56 (uint16_t)16,
57 (uint16_t)32,
58 (uint16_t)64,
59 (uint16_t)128,
60 (uint16_t)256
61 };
62 /**
63 * @}
64 */
65
66 /* Private constants ---------------------------------------------------------*/
67 /** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
68 * @{
69 */
70 /* Defines used in Baud Rate related macros and corresponding register setting computation */
71 #define LPUART_LPUARTDIV_FREQ_MUL 256U
72 #define LPUART_BRR_MASK 0x000FFFFFU
73 #define LPUART_BRR_MIN_VALUE 0x00000300U
74 /**
75 * @}
76 */
77
78
79 /* Private macros ------------------------------------------------------------*/
80 #if defined(USE_FULL_LL_DRIVER)
81 /** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
82 * @{
83 */
84 /**
85 * @}
86 */
87 #endif /*USE_FULL_LL_DRIVER*/
88
89 /* Exported types ------------------------------------------------------------*/
90 #if defined(USE_FULL_LL_DRIVER)
91 /** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
92 * @{
93 */
94
95 /**
96 * @brief LL LPUART Init Structure definition
97 */
98 typedef struct
99 {
100 uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate.
101 This parameter can be a value of @ref LPUART_LL_EC_PRESCALER.
102
103 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetPrescaler().*/
104
105 uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate.
106
107 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetBaudRate().*/
108
109 uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
110 This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
111
112 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetDataWidth().*/
113
114 uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
115 This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
116
117 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetStopBitsLength().*/
118
119 uint32_t Parity; /*!< Specifies the parity mode.
120 This parameter can be a value of @ref LPUART_LL_EC_PARITY.
121
122 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetParity().*/
123
124 uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
125 This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
126
127 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetTransferDirection().*/
128
129 uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
130 This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
131
132 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetHWFlowCtrl().*/
133
134 } LL_LPUART_InitTypeDef;
135
136 /**
137 * @}
138 */
139 #endif /* USE_FULL_LL_DRIVER */
140
141 /* Exported constants --------------------------------------------------------*/
142 /** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
143 * @{
144 */
145
146 /** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
147 * @brief Flags defines which can be used with LL_LPUART_WriteReg function
148 * @{
149 */
150 #define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */
151 #define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */
152 #define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected flag */
153 #define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */
154 #define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */
155 #define LL_LPUART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty Clear flag */
156 #define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */
157 #define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */
158 #define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */
159 #define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */
160 /**
161 * @}
162 */
163
164 /** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
165 * @brief Flags defines which can be used with LL_LPUART_ReadReg function
166 * @{
167 */
168 #define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */
169 #define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */
170 #define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
171 #define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
172 #define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
173 #define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
174 #define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
175 #define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/
176 #define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
177 #define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
178 #define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
179 #define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
180 #define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
181 #define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
182 #define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */
183 #define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
184 #define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */
185 #define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */
186 #define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */
187 #define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */
188 #define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */
189 /**
190 * @}
191 */
192
193 /** @defgroup LPUART_LL_EC_IT IT Defines
194 * @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions
195 * @{
196 */
197 #define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
198 #define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty interrupt enable */
199 #define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
200 #define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not full interrupt enable */
201 #define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
202 #define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */
203 #define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */
204 #define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */
205 #define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
206 #define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
207 #define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */
208 #define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */
209 #define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */
210 /**
211 * @}
212 */
213
214 /** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold
215 * @{
216 */
217 #define LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */
218 #define LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */
219 #define LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */
220 #define LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */
221 #define LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */
222 #define LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */
223 /**
224 * @}
225 */
226
227 /** @defgroup LPUART_LL_EC_DIRECTION Direction
228 * @{
229 */
230 #define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */
231 #define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
232 #define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
233 #define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
234 /**
235 * @}
236 */
237
238 /** @defgroup LPUART_LL_EC_PARITY Parity Control
239 * @{
240 */
241 #define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
242 #define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
243 #define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
244 /**
245 * @}
246 */
247
248 /** @defgroup LPUART_LL_EC_WAKEUP Wakeup
249 * @{
250 */
251 #define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */
252 #define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */
253 /**
254 * @}
255 */
256
257 /** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
258 * @{
259 */
260 #define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
261 #define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
262 #define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
263 /**
264 * @}
265 */
266
267 /** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler
268 * @{
269 */
270 #define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not devided */
271 #define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock devided by 2 */
272 #define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock devided by 4 */
273 #define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 6 */
274 #define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock devided by 8 */
275 #define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 10 */
276 #define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 12 */
277 #define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 16 */
278 #define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock devided by 32 */
279 #define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 64 */
280 #define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 128 */
281 #define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 256 */
282 /**
283 * @}
284 */
285
286 /** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
287 * @{
288 */
289 #define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
290 #define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
291 /**
292 * @}
293 */
294
295 /** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
296 * @{
297 */
298 #define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
299 #define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
300 /**
301 * @}
302 */
303
304 /** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
305 * @{
306 */
307 #define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */
308 #define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
309 /**
310 * @}
311 */
312
313 /** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
314 * @{
315 */
316 #define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */
317 #define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
318 /**
319 * @}
320 */
321
322 /** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
323 * @{
324 */
325 #define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
326 #define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
327 /**
328 * @}
329 */
330
331 /** @defgroup LPUART_LL_EC_BITORDER Bit Order
332 * @{
333 */
334 #define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */
335 #define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */
336 /**
337 * @}
338 */
339
340 /** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
341 * @{
342 */
343 #define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */
344 #define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
345 /**
346 * @}
347 */
348
349 /** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
350 * @{
351 */
352 #define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */
353 #define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
354 #define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
355 #define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
356 /**
357 * @}
358 */
359
360 /** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
361 * @{
362 */
363 #define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */
364 #define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */
365 #define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */
366 /**
367 * @}
368 */
369
370 /** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
371 * @{
372 */
373 #define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */
374 #define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */
375 /**
376 * @}
377 */
378
379 /** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
380 * @{
381 */
382 #define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
383 #define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
384 /**
385 * @}
386 */
387
388 /**
389 * @}
390 */
391
392 /* Exported macro ------------------------------------------------------------*/
393 /** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
394 * @{
395 */
396
397 /** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
398 * @{
399 */
400
401 /**
402 * @brief Write a value in LPUART register
403 * @param __INSTANCE__ LPUART Instance
404 * @param __REG__ Register to be written
405 * @param __VALUE__ Value to be written in the register
406 * @retval None
407 */
408 #define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
409
410 /**
411 * @brief Read a value in LPUART register
412 * @param __INSTANCE__ LPUART Instance
413 * @param __REG__ Register to be read
414 * @retval Register value
415 */
416 #define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
417 /**
418 * @}
419 */
420
421 /** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
422 * @{
423 */
424
425 /**
426 * @brief Compute LPUARTDIV value according to Peripheral Clock and
427 * expected Baud Rate (20-bit value of LPUARTDIV is returned)
428 * @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
429 * @param __PRESCALER__ This parameter can be one of the following values:
430 * @arg @ref LL_LPUART_PRESCALER_DIV1
431 * @arg @ref LL_LPUART_PRESCALER_DIV2
432 * @arg @ref LL_LPUART_PRESCALER_DIV4
433 * @arg @ref LL_LPUART_PRESCALER_DIV6
434 * @arg @ref LL_LPUART_PRESCALER_DIV8
435 * @arg @ref LL_LPUART_PRESCALER_DIV10
436 * @arg @ref LL_LPUART_PRESCALER_DIV12
437 * @arg @ref LL_LPUART_PRESCALER_DIV16
438 * @arg @ref LL_LPUART_PRESCALER_DIV32
439 * @arg @ref LL_LPUART_PRESCALER_DIV64
440 * @arg @ref LL_LPUART_PRESCALER_DIV128
441 * @arg @ref LL_LPUART_PRESCALER_DIV256
442 * @param __BAUDRATE__ Baud Rate value to achieve
443 * @retval LPUARTDIV value to be used for BRR register filling
444 */
445 #define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)])) * LPUART_LPUARTDIV_FREQ_MUL)\
446 + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
447
448 /**
449 * @}
450 */
451
452 /**
453 * @}
454 */
455
456 /* Exported functions --------------------------------------------------------*/
457 /** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
458 * @{
459 */
460
461 /** @defgroup LPUART_LL_EF_Configuration Configuration functions
462 * @{
463 */
464
465 /**
466 * @brief LPUART Enable
467 * @rmtoll CR1 UE LL_LPUART_Enable
468 * @param LPUARTx LPUART Instance
469 * @retval None
470 */
471 __STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
472 {
473 SET_BIT(LPUARTx->CR1, USART_CR1_UE);
474 }
475
476 /**
477 * @brief LPUART Disable
478 * @note When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
479 * and current operations are discarded. The configuration of the LPUART is kept, but all the status
480 * flags, in the LPUARTx_ISR are set to their default values.
481 * @note In order to go into low-power mode without generating errors on the line,
482 * the TE bit must be reset before and the software must wait
483 * for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
484 * The DMA requests are also reset when UE = 0 so the DMA channel must
485 * be disabled before resetting the UE bit.
486 * @rmtoll CR1 UE LL_LPUART_Disable
487 * @param LPUARTx LPUART Instance
488 * @retval None
489 */
490 __STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
491 {
492 CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
493 }
494
495 /**
496 * @brief Indicate if LPUART is enabled
497 * @rmtoll CR1 UE LL_LPUART_IsEnabled
498 * @param LPUARTx LPUART Instance
499 * @retval State of bit (1 or 0).
500 */
501 __STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx)
502 {
503 return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
504 }
505
506 /**
507 * @brief FIFO Mode Enable
508 * @rmtoll CR1 FIFOEN LL_LPUART_EnableFIFO
509 * @param LPUARTx LPUART Instance
510 * @retval None
511 */
512 __STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx)
513 {
514 SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
515 }
516
517 /**
518 * @brief FIFO Mode Disable
519 * @rmtoll CR1 FIFOEN LL_LPUART_DisableFIFO
520 * @param LPUARTx LPUART Instance
521 * @retval None
522 */
523 __STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx)
524 {
525 CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
526 }
527
528 /**
529 * @brief Indicate if FIFO Mode is enabled
530 * @rmtoll CR1 FIFOEN LL_LPUART_IsEnabledFIFO
531 * @param LPUARTx LPUART Instance
532 * @retval State of bit (1 or 0).
533 */
534 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(USART_TypeDef *LPUARTx)
535 {
536 return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
537 }
538
539 /**
540 * @brief Configure TX FIFO Threshold
541 * @rmtoll CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold
542 * @param LPUARTx LPUART Instance
543 * @param Threshold This parameter can be one of the following values:
544 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
545 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
546 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
547 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
548 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
549 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
550 * @retval None
551 */
552 __STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
553 {
554 MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
555 }
556
557 /**
558 * @brief Return TX FIFO Threshold Configuration
559 * @rmtoll CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold
560 * @param LPUARTx LPUART Instance
561 * @retval Returned value can be one of the following values:
562 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
563 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
564 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
565 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
566 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
567 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
568 */
569 __STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(USART_TypeDef *LPUARTx)
570 {
571 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
572 }
573
574 /**
575 * @brief Configure RX FIFO Threshold
576 * @rmtoll CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold
577 * @param LPUARTx LPUART Instance
578 * @param Threshold This parameter can be one of the following values:
579 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
580 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
581 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
582 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
583 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
584 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
585 * @retval None
586 */
587 __STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
588 {
589 MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
590 }
591
592 /**
593 * @brief Return RX FIFO Threshold Configuration
594 * @rmtoll CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold
595 * @param LPUARTx LPUART Instance
596 * @retval Returned value can be one of the following values:
597 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
598 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
599 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
600 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
601 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
602 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
603 */
604 __STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx)
605 {
606 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
607 }
608
609 /**
610 * @brief Configure TX and RX FIFOs Threshold
611 * @rmtoll CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold\n
612 * CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold
613 * @param LPUARTx LPUART Instance
614 * @param TXThreshold This parameter can be one of the following values:
615 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
616 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
617 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
618 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
619 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
620 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
621 * @param RXThreshold This parameter can be one of the following values:
622 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
623 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
624 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
625 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
626 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
627 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
628 * @retval None
629 */
630 __STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
631 {
632 MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | (RXThreshold << USART_CR3_RXFTCFG_Pos));
633 }
634
635 /**
636 * @brief LPUART enabled in STOP Mode
637 * @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
638 * LPUART clock selection is HSI or LSE in RCC.
639 * @rmtoll CR1 UESM LL_LPUART_EnableInStopMode
640 * @param LPUARTx LPUART Instance
641 * @retval None
642 */
643 __STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
644 {
645 SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
646 }
647
648 /**
649 * @brief LPUART disabled in STOP Mode
650 * @note When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
651 * @rmtoll CR1 UESM LL_LPUART_DisableInStopMode
652 * @param LPUARTx LPUART Instance
653 * @retval None
654 */
655 __STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
656 {
657 CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
658 }
659
660 /**
661 * @brief Indicate if LPUART is enabled in STOP Mode
662 * (able to wake up MCU from Stop mode or not)
663 * @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode
664 * @param LPUARTx LPUART Instance
665 * @retval State of bit (1 or 0).
666 */
667 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx)
668 {
669 return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
670 }
671
672 /**
673 * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
674 * @rmtoll CR1 RE LL_LPUART_EnableDirectionRx
675 * @param LPUARTx LPUART Instance
676 * @retval None
677 */
678 __STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
679 {
680 SET_BIT(LPUARTx->CR1, USART_CR1_RE);
681 }
682
683 /**
684 * @brief Receiver Disable
685 * @rmtoll CR1 RE LL_LPUART_DisableDirectionRx
686 * @param LPUARTx LPUART Instance
687 * @retval None
688 */
689 __STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
690 {
691 CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
692 }
693
694 /**
695 * @brief Transmitter Enable
696 * @rmtoll CR1 TE LL_LPUART_EnableDirectionTx
697 * @param LPUARTx LPUART Instance
698 * @retval None
699 */
700 __STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
701 {
702 SET_BIT(LPUARTx->CR1, USART_CR1_TE);
703 }
704
705 /**
706 * @brief Transmitter Disable
707 * @rmtoll CR1 TE LL_LPUART_DisableDirectionTx
708 * @param LPUARTx LPUART Instance
709 * @retval None
710 */
711 __STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
712 {
713 CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
714 }
715
716 /**
717 * @brief Configure simultaneously enabled/disabled states
718 * of Transmitter and Receiver
719 * @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n
720 * CR1 TE LL_LPUART_SetTransferDirection
721 * @param LPUARTx LPUART Instance
722 * @param TransferDirection This parameter can be one of the following values:
723 * @arg @ref LL_LPUART_DIRECTION_NONE
724 * @arg @ref LL_LPUART_DIRECTION_RX
725 * @arg @ref LL_LPUART_DIRECTION_TX
726 * @arg @ref LL_LPUART_DIRECTION_TX_RX
727 * @retval None
728 */
729 __STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
730 {
731 MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
732 }
733
734 /**
735 * @brief Return enabled/disabled states of Transmitter and Receiver
736 * @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n
737 * CR1 TE LL_LPUART_GetTransferDirection
738 * @param LPUARTx LPUART Instance
739 * @retval Returned value can be one of the following values:
740 * @arg @ref LL_LPUART_DIRECTION_NONE
741 * @arg @ref LL_LPUART_DIRECTION_RX
742 * @arg @ref LL_LPUART_DIRECTION_TX
743 * @arg @ref LL_LPUART_DIRECTION_TX_RX
744 */
745 __STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx)
746 {
747 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
748 }
749
750 /**
751 * @brief Configure Parity (enabled/disabled and parity mode if enabled)
752 * @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
753 * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
754 * (depending on data width) and parity is checked on the received data.
755 * @rmtoll CR1 PS LL_LPUART_SetParity\n
756 * CR1 PCE LL_LPUART_SetParity
757 * @param LPUARTx LPUART Instance
758 * @param Parity This parameter can be one of the following values:
759 * @arg @ref LL_LPUART_PARITY_NONE
760 * @arg @ref LL_LPUART_PARITY_EVEN
761 * @arg @ref LL_LPUART_PARITY_ODD
762 * @retval None
763 */
764 __STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
765 {
766 MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
767 }
768
769 /**
770 * @brief Return Parity configuration (enabled/disabled and parity mode if enabled)
771 * @rmtoll CR1 PS LL_LPUART_GetParity\n
772 * CR1 PCE LL_LPUART_GetParity
773 * @param LPUARTx LPUART Instance
774 * @retval Returned value can be one of the following values:
775 * @arg @ref LL_LPUART_PARITY_NONE
776 * @arg @ref LL_LPUART_PARITY_EVEN
777 * @arg @ref LL_LPUART_PARITY_ODD
778 */
779 __STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx)
780 {
781 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
782 }
783
784 /**
785 * @brief Set Receiver Wake Up method from Mute mode.
786 * @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod
787 * @param LPUARTx LPUART Instance
788 * @param Method This parameter can be one of the following values:
789 * @arg @ref LL_LPUART_WAKEUP_IDLELINE
790 * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
791 * @retval None
792 */
793 __STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
794 {
795 MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
796 }
797
798 /**
799 * @brief Return Receiver Wake Up method from Mute mode
800 * @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod
801 * @param LPUARTx LPUART Instance
802 * @retval Returned value can be one of the following values:
803 * @arg @ref LL_LPUART_WAKEUP_IDLELINE
804 * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
805 */
806 __STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx)
807 {
808 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
809 }
810
811 /**
812 * @brief Set Word length (nb of data bits, excluding start and stop bits)
813 * @rmtoll CR1 M LL_LPUART_SetDataWidth
814 * @param LPUARTx LPUART Instance
815 * @param DataWidth This parameter can be one of the following values:
816 * @arg @ref LL_LPUART_DATAWIDTH_7B
817 * @arg @ref LL_LPUART_DATAWIDTH_8B
818 * @arg @ref LL_LPUART_DATAWIDTH_9B
819 * @retval None
820 */
821 __STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
822 {
823 MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
824 }
825
826 /**
827 * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits)
828 * @rmtoll CR1 M LL_LPUART_GetDataWidth
829 * @param LPUARTx LPUART Instance
830 * @retval Returned value can be one of the following values:
831 * @arg @ref LL_LPUART_DATAWIDTH_7B
832 * @arg @ref LL_LPUART_DATAWIDTH_8B
833 * @arg @ref LL_LPUART_DATAWIDTH_9B
834 */
835 __STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx)
836 {
837 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
838 }
839
840 /**
841 * @brief Allow switch between Mute Mode and Active mode
842 * @rmtoll CR1 MME LL_LPUART_EnableMuteMode
843 * @param LPUARTx LPUART Instance
844 * @retval None
845 */
846 __STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
847 {
848 SET_BIT(LPUARTx->CR1, USART_CR1_MME);
849 }
850
851 /**
852 * @brief Prevent Mute Mode use. Set Receiver in active mode permanently.
853 * @rmtoll CR1 MME LL_LPUART_DisableMuteMode
854 * @param LPUARTx LPUART Instance
855 * @retval None
856 */
857 __STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
858 {
859 CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
860 }
861
862 /**
863 * @brief Indicate if switch between Mute Mode and Active mode is allowed
864 * @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode
865 * @param LPUARTx LPUART Instance
866 * @retval State of bit (1 or 0).
867 */
868 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx)
869 {
870 return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
871 }
872
873 /**
874 * @brief Configure Clock source prescaler for baudrate generator and oversampling
875 * @rmtoll PRESC PRESCALER LL_LPUART_SetPrescaler
876 * @param LPUARTx LPUART Instance
877 * @param PrescalerValue This parameter can be one of the following values:
878 * @arg @ref LL_LPUART_PRESCALER_DIV1
879 * @arg @ref LL_LPUART_PRESCALER_DIV2
880 * @arg @ref LL_LPUART_PRESCALER_DIV4
881 * @arg @ref LL_LPUART_PRESCALER_DIV6
882 * @arg @ref LL_LPUART_PRESCALER_DIV8
883 * @arg @ref LL_LPUART_PRESCALER_DIV10
884 * @arg @ref LL_LPUART_PRESCALER_DIV12
885 * @arg @ref LL_LPUART_PRESCALER_DIV16
886 * @arg @ref LL_LPUART_PRESCALER_DIV32
887 * @arg @ref LL_LPUART_PRESCALER_DIV64
888 * @arg @ref LL_LPUART_PRESCALER_DIV128
889 * @arg @ref LL_LPUART_PRESCALER_DIV256
890 * @retval None
891 */
892 __STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
893 {
894 MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
895 }
896
897 /**
898 * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling
899 * @rmtoll PRESC PRESCALER LL_LPUART_GetPrescaler
900 * @param LPUARTx LPUART Instance
901 * @retval Returned value can be one of the following values:
902 * @arg @ref LL_LPUART_PRESCALER_DIV1
903 * @arg @ref LL_LPUART_PRESCALER_DIV2
904 * @arg @ref LL_LPUART_PRESCALER_DIV4
905 * @arg @ref LL_LPUART_PRESCALER_DIV6
906 * @arg @ref LL_LPUART_PRESCALER_DIV8
907 * @arg @ref LL_LPUART_PRESCALER_DIV10
908 * @arg @ref LL_LPUART_PRESCALER_DIV12
909 * @arg @ref LL_LPUART_PRESCALER_DIV16
910 * @arg @ref LL_LPUART_PRESCALER_DIV32
911 * @arg @ref LL_LPUART_PRESCALER_DIV64
912 * @arg @ref LL_LPUART_PRESCALER_DIV128
913 * @arg @ref LL_LPUART_PRESCALER_DIV256
914 */
915 __STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(USART_TypeDef *LPUARTx)
916 {
917 return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER));
918 }
919
920 /**
921 * @brief Set the length of the stop bits
922 * @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength
923 * @param LPUARTx LPUART Instance
924 * @param StopBits This parameter can be one of the following values:
925 * @arg @ref LL_LPUART_STOPBITS_1
926 * @arg @ref LL_LPUART_STOPBITS_2
927 * @retval None
928 */
929 __STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
930 {
931 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
932 }
933
934 /**
935 * @brief Retrieve the length of the stop bits
936 * @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength
937 * @param LPUARTx LPUART Instance
938 * @retval Returned value can be one of the following values:
939 * @arg @ref LL_LPUART_STOPBITS_1
940 * @arg @ref LL_LPUART_STOPBITS_2
941 */
942 __STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx)
943 {
944 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
945 }
946
947 /**
948 * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
949 * @note Call of this function is equivalent to following function call sequence :
950 * - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
951 * - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
952 * - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
953 * @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n
954 * CR1 PCE LL_LPUART_ConfigCharacter\n
955 * CR1 M LL_LPUART_ConfigCharacter\n
956 * CR2 STOP LL_LPUART_ConfigCharacter
957 * @param LPUARTx LPUART Instance
958 * @param DataWidth This parameter can be one of the following values:
959 * @arg @ref LL_LPUART_DATAWIDTH_7B
960 * @arg @ref LL_LPUART_DATAWIDTH_8B
961 * @arg @ref LL_LPUART_DATAWIDTH_9B
962 * @param Parity This parameter can be one of the following values:
963 * @arg @ref LL_LPUART_PARITY_NONE
964 * @arg @ref LL_LPUART_PARITY_EVEN
965 * @arg @ref LL_LPUART_PARITY_ODD
966 * @param StopBits This parameter can be one of the following values:
967 * @arg @ref LL_LPUART_STOPBITS_1
968 * @arg @ref LL_LPUART_STOPBITS_2
969 * @retval None
970 */
971 __STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
972 uint32_t StopBits)
973 {
974 MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
975 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
976 }
977
978 /**
979 * @brief Configure TX/RX pins swapping setting.
980 * @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap
981 * @param LPUARTx LPUART Instance
982 * @param SwapConfig This parameter can be one of the following values:
983 * @arg @ref LL_LPUART_TXRX_STANDARD
984 * @arg @ref LL_LPUART_TXRX_SWAPPED
985 * @retval None
986 */
987 __STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
988 {
989 MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
990 }
991
992 /**
993 * @brief Retrieve TX/RX pins swapping configuration.
994 * @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap
995 * @param LPUARTx LPUART Instance
996 * @retval Returned value can be one of the following values:
997 * @arg @ref LL_LPUART_TXRX_STANDARD
998 * @arg @ref LL_LPUART_TXRX_SWAPPED
999 */
1000 __STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx)
1001 {
1002 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
1003 }
1004
1005 /**
1006 * @brief Configure RX pin active level logic
1007 * @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel
1008 * @param LPUARTx LPUART Instance
1009 * @param PinInvMethod This parameter can be one of the following values:
1010 * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
1011 * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
1012 * @retval None
1013 */
1014 __STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
1015 {
1016 MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
1017 }
1018
1019 /**
1020 * @brief Retrieve RX pin active level logic configuration
1021 * @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel
1022 * @param LPUARTx LPUART Instance
1023 * @retval Returned value can be one of the following values:
1024 * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
1025 * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
1026 */
1027 __STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx)
1028 {
1029 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
1030 }
1031
1032 /**
1033 * @brief Configure TX pin active level logic
1034 * @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel
1035 * @param LPUARTx LPUART Instance
1036 * @param PinInvMethod This parameter can be one of the following values:
1037 * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
1038 * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
1039 * @retval None
1040 */
1041 __STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
1042 {
1043 MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
1044 }
1045
1046 /**
1047 * @brief Retrieve TX pin active level logic configuration
1048 * @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel
1049 * @param LPUARTx LPUART Instance
1050 * @retval Returned value can be one of the following values:
1051 * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
1052 * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
1053 */
1054 __STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx)
1055 {
1056 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
1057 }
1058
1059 /**
1060 * @brief Configure Binary data logic.
1061 *
1062 * @note Allow to define how Logical data from the data register are send/received :
1063 * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
1064 * @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic
1065 * @param LPUARTx LPUART Instance
1066 * @param DataLogic This parameter can be one of the following values:
1067 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
1068 * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
1069 * @retval None
1070 */
1071 __STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
1072 {
1073 MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
1074 }
1075
1076 /**
1077 * @brief Retrieve Binary data configuration
1078 * @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic
1079 * @param LPUARTx LPUART Instance
1080 * @retval Returned value can be one of the following values:
1081 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
1082 * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
1083 */
1084 __STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx)
1085 {
1086 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
1087 }
1088
1089 /**
1090 * @brief Configure transfer bit order (either Less or Most Significant Bit First)
1091 * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
1092 * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
1093 * @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder
1094 * @param LPUARTx LPUART Instance
1095 * @param BitOrder This parameter can be one of the following values:
1096 * @arg @ref LL_LPUART_BITORDER_LSBFIRST
1097 * @arg @ref LL_LPUART_BITORDER_MSBFIRST
1098 * @retval None
1099 */
1100 __STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
1101 {
1102 MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
1103 }
1104
1105 /**
1106 * @brief Return transfer bit order (either Less or Most Significant Bit First)
1107 * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
1108 * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
1109 * @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder
1110 * @param LPUARTx LPUART Instance
1111 * @retval Returned value can be one of the following values:
1112 * @arg @ref LL_LPUART_BITORDER_LSBFIRST
1113 * @arg @ref LL_LPUART_BITORDER_MSBFIRST
1114 */
1115 __STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx)
1116 {
1117 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
1118 }
1119
1120 /**
1121 * @brief Set Address of the LPUART node.
1122 * @note This is used in multiprocessor communication during Mute mode or Stop mode,
1123 * for wake up with address mark detection.
1124 * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7.
1125 * (b7-b4 should be set to 0)
1126 * 8bits address node is used when 7-bit Address Detection is selected in ADDM7.
1127 * (This is used in multiprocessor communication during Mute mode or Stop mode,
1128 * for wake up with 7-bit address mark detection.
1129 * The MSB of the character sent by the transmitter should be equal to 1.
1130 * It may also be used for character detection during normal reception,
1131 * Mute mode inactive (for example, end of block detection in ModBus protocol).
1132 * In this case, the whole received character (8-bit) is compared to the ADD[7:0]
1133 * value and CMF flag is set on match)
1134 * @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n
1135 * CR2 ADDM7 LL_LPUART_ConfigNodeAddress
1136 * @param LPUARTx LPUART Instance
1137 * @param AddressLen This parameter can be one of the following values:
1138 * @arg @ref LL_LPUART_ADDRESS_DETECT_4B
1139 * @arg @ref LL_LPUART_ADDRESS_DETECT_7B
1140 * @param NodeAddress 4 or 7 bit Address of the LPUART node.
1141 * @retval None
1142 */
1143 __STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
1144 {
1145 MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
1146 (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
1147 }
1148
1149 /**
1150 * @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2.
1151 * @note If 4-bit Address Detection is selected in ADDM7,
1152 * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
1153 * If 7-bit Address Detection is selected in ADDM7,
1154 * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
1155 * @rmtoll CR2 ADD LL_LPUART_GetNodeAddress
1156 * @param LPUARTx LPUART Instance
1157 * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
1158 */
1159 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx)
1160 {
1161 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
1162 }
1163
1164 /**
1165 * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
1166 * @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen
1167 * @param LPUARTx LPUART Instance
1168 * @retval Returned value can be one of the following values:
1169 * @arg @ref LL_LPUART_ADDRESS_DETECT_4B
1170 * @arg @ref LL_LPUART_ADDRESS_DETECT_7B
1171 */
1172 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx)
1173 {
1174 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
1175 }
1176
1177 /**
1178 * @brief Enable RTS HW Flow Control
1179 * @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl
1180 * @param LPUARTx LPUART Instance
1181 * @retval None
1182 */
1183 __STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1184 {
1185 SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
1186 }
1187
1188 /**
1189 * @brief Disable RTS HW Flow Control
1190 * @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl
1191 * @param LPUARTx LPUART Instance
1192 * @retval None
1193 */
1194 __STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1195 {
1196 CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
1197 }
1198
1199 /**
1200 * @brief Enable CTS HW Flow Control
1201 * @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl
1202 * @param LPUARTx LPUART Instance
1203 * @retval None
1204 */
1205 __STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1206 {
1207 SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
1208 }
1209
1210 /**
1211 * @brief Disable CTS HW Flow Control
1212 * @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl
1213 * @param LPUARTx LPUART Instance
1214 * @retval None
1215 */
1216 __STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1217 {
1218 CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
1219 }
1220
1221 /**
1222 * @brief Configure HW Flow Control mode (both CTS and RTS)
1223 * @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n
1224 * CR3 CTSE LL_LPUART_SetHWFlowCtrl
1225 * @param LPUARTx LPUART Instance
1226 * @param HardwareFlowControl This parameter can be one of the following values:
1227 * @arg @ref LL_LPUART_HWCONTROL_NONE
1228 * @arg @ref LL_LPUART_HWCONTROL_RTS
1229 * @arg @ref LL_LPUART_HWCONTROL_CTS
1230 * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
1231 * @retval None
1232 */
1233 __STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
1234 {
1235 MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
1236 }
1237
1238 /**
1239 * @brief Return HW Flow Control configuration (both CTS and RTS)
1240 * @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n
1241 * CR3 CTSE LL_LPUART_GetHWFlowCtrl
1242 * @param LPUARTx LPUART Instance
1243 * @retval Returned value can be one of the following values:
1244 * @arg @ref LL_LPUART_HWCONTROL_NONE
1245 * @arg @ref LL_LPUART_HWCONTROL_RTS
1246 * @arg @ref LL_LPUART_HWCONTROL_CTS
1247 * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
1248 */
1249 __STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx)
1250 {
1251 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
1252 }
1253
1254 /**
1255 * @brief Enable Overrun detection
1256 * @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect
1257 * @param LPUARTx LPUART Instance
1258 * @retval None
1259 */
1260 __STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
1261 {
1262 CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
1263 }
1264
1265 /**
1266 * @brief Disable Overrun detection
1267 * @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect
1268 * @param LPUARTx LPUART Instance
1269 * @retval None
1270 */
1271 __STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
1272 {
1273 SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
1274 }
1275
1276 /**
1277 * @brief Indicate if Overrun detection is enabled
1278 * @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect
1279 * @param LPUARTx LPUART Instance
1280 * @retval State of bit (1 or 0).
1281 */
1282 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx)
1283 {
1284 return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
1285 }
1286
1287 /**
1288 * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
1289 * @rmtoll CR3 WUS LL_LPUART_SetWKUPType
1290 * @param LPUARTx LPUART Instance
1291 * @param Type This parameter can be one of the following values:
1292 * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
1293 * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
1294 * @arg @ref LL_LPUART_WAKEUP_ON_RXNE
1295 * @retval None
1296 */
1297 __STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)
1298 {
1299 MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
1300 }
1301
1302 /**
1303 * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
1304 * @rmtoll CR3 WUS LL_LPUART_GetWKUPType
1305 * @param LPUARTx LPUART Instance
1306 * @retval Returned value can be one of the following values:
1307 * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
1308 * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
1309 * @arg @ref LL_LPUART_WAKEUP_ON_RXNE
1310 */
1311 __STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx)
1312 {
1313 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
1314 }
1315
1316 /**
1317 * @brief Configure LPUART BRR register for achieving expected Baud Rate value.
1318 *
1319 * @note Compute and set LPUARTDIV value in BRR Register (full BRR content)
1320 * according to used Peripheral Clock and expected Baud Rate values
1321 * @note Peripheral clock and Baud Rate values provided as function parameters should be valid
1322 * (Baud rate value != 0).
1323 * @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
1324 * a care should be taken when generating high baud rates using high PeriphClk
1325 * values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
1326 * @rmtoll BRR BRR LL_LPUART_SetBaudRate
1327 * @param LPUARTx LPUART Instance
1328 * @param PeriphClk Peripheral Clock
1329 * @param PrescalerValue This parameter can be one of the following values:
1330 * @arg @ref LL_LPUART_PRESCALER_DIV1
1331 * @arg @ref LL_LPUART_PRESCALER_DIV2
1332 * @arg @ref LL_LPUART_PRESCALER_DIV4
1333 * @arg @ref LL_LPUART_PRESCALER_DIV6
1334 * @arg @ref LL_LPUART_PRESCALER_DIV8
1335 * @arg @ref LL_LPUART_PRESCALER_DIV10
1336 * @arg @ref LL_LPUART_PRESCALER_DIV12
1337 * @arg @ref LL_LPUART_PRESCALER_DIV16
1338 * @arg @ref LL_LPUART_PRESCALER_DIV32
1339 * @arg @ref LL_LPUART_PRESCALER_DIV64
1340 * @arg @ref LL_LPUART_PRESCALER_DIV128
1341 * @arg @ref LL_LPUART_PRESCALER_DIV256
1342 * @param BaudRate Baud Rate
1343 * @retval None
1344 */
1345 __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
1346 uint32_t BaudRate)
1347 {
1348 LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
1349 }
1350
1351 /**
1352 * @brief Return current Baud Rate value, according to LPUARTDIV present in BRR register
1353 * (full BRR content), and to used Peripheral Clock values
1354 * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
1355 * @rmtoll BRR BRR LL_LPUART_GetBaudRate
1356 * @param LPUARTx LPUART Instance
1357 * @param PeriphClk Peripheral Clock
1358 * @param PrescalerValue This parameter can be one of the following values:
1359 * @arg @ref LL_LPUART_PRESCALER_DIV1
1360 * @arg @ref LL_LPUART_PRESCALER_DIV2
1361 * @arg @ref LL_LPUART_PRESCALER_DIV4
1362 * @arg @ref LL_LPUART_PRESCALER_DIV6
1363 * @arg @ref LL_LPUART_PRESCALER_DIV8
1364 * @arg @ref LL_LPUART_PRESCALER_DIV10
1365 * @arg @ref LL_LPUART_PRESCALER_DIV12
1366 * @arg @ref LL_LPUART_PRESCALER_DIV16
1367 * @arg @ref LL_LPUART_PRESCALER_DIV32
1368 * @arg @ref LL_LPUART_PRESCALER_DIV64
1369 * @arg @ref LL_LPUART_PRESCALER_DIV128
1370 * @arg @ref LL_LPUART_PRESCALER_DIV256
1371 * @retval Baud Rate
1372 */
1373 __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue)
1374 {
1375 uint32_t lpuartdiv;
1376 uint32_t brrresult;
1377 uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
1378
1379 lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
1380
1381 if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
1382 {
1383 brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
1384 }
1385 else
1386 {
1387 brrresult = 0x0UL;
1388 }
1389
1390 return (brrresult);
1391 }
1392
1393 /**
1394 * @}
1395 */
1396
1397 /** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
1398 * @{
1399 */
1400
1401 /**
1402 * @brief Enable Single Wire Half-Duplex mode
1403 * @rmtoll CR3 HDSEL LL_LPUART_EnableHalfDuplex
1404 * @param LPUARTx LPUART Instance
1405 * @retval None
1406 */
1407 __STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
1408 {
1409 SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
1410 }
1411
1412 /**
1413 * @brief Disable Single Wire Half-Duplex mode
1414 * @rmtoll CR3 HDSEL LL_LPUART_DisableHalfDuplex
1415 * @param LPUARTx LPUART Instance
1416 * @retval None
1417 */
1418 __STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
1419 {
1420 CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
1421 }
1422
1423 /**
1424 * @brief Indicate if Single Wire Half-Duplex mode is enabled
1425 * @rmtoll CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex
1426 * @param LPUARTx LPUART Instance
1427 * @retval State of bit (1 or 0).
1428 */
1429 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx)
1430 {
1431 return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
1432 }
1433
1434 /**
1435 * @}
1436 */
1437
1438 /** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
1439 * @{
1440 */
1441
1442 /**
1443 * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
1444 * @rmtoll CR1 DEDT LL_LPUART_SetDEDeassertionTime
1445 * @param LPUARTx LPUART Instance
1446 * @param Time Value between Min_Data=0 and Max_Data=31
1447 * @retval None
1448 */
1449 __STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
1450 {
1451 MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
1452 }
1453
1454 /**
1455 * @brief Return DEDT (Driver Enable De-Assertion Time)
1456 * @rmtoll CR1 DEDT LL_LPUART_GetDEDeassertionTime
1457 * @param LPUARTx LPUART Instance
1458 * @retval Time value expressed on 5 bits ([4:0] bits) : c
1459 */
1460 __STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx)
1461 {
1462 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
1463 }
1464
1465 /**
1466 * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
1467 * @rmtoll CR1 DEAT LL_LPUART_SetDEAssertionTime
1468 * @param LPUARTx LPUART Instance
1469 * @param Time Value between Min_Data=0 and Max_Data=31
1470 * @retval None
1471 */
1472 __STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
1473 {
1474 MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
1475 }
1476
1477 /**
1478 * @brief Return DEAT (Driver Enable Assertion Time)
1479 * @rmtoll CR1 DEAT LL_LPUART_GetDEAssertionTime
1480 * @param LPUARTx LPUART Instance
1481 * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
1482 */
1483 __STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx)
1484 {
1485 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
1486 }
1487
1488 /**
1489 * @brief Enable Driver Enable (DE) Mode
1490 * @rmtoll CR3 DEM LL_LPUART_EnableDEMode
1491 * @param LPUARTx LPUART Instance
1492 * @retval None
1493 */
1494 __STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
1495 {
1496 SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
1497 }
1498
1499 /**
1500 * @brief Disable Driver Enable (DE) Mode
1501 * @rmtoll CR3 DEM LL_LPUART_DisableDEMode
1502 * @param LPUARTx LPUART Instance
1503 * @retval None
1504 */
1505 __STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
1506 {
1507 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
1508 }
1509
1510 /**
1511 * @brief Indicate if Driver Enable (DE) Mode is enabled
1512 * @rmtoll CR3 DEM LL_LPUART_IsEnabledDEMode
1513 * @param LPUARTx LPUART Instance
1514 * @retval State of bit (1 or 0).
1515 */
1516 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx)
1517 {
1518 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
1519 }
1520
1521 /**
1522 * @brief Select Driver Enable Polarity
1523 * @rmtoll CR3 DEP LL_LPUART_SetDESignalPolarity
1524 * @param LPUARTx LPUART Instance
1525 * @param Polarity This parameter can be one of the following values:
1526 * @arg @ref LL_LPUART_DE_POLARITY_HIGH
1527 * @arg @ref LL_LPUART_DE_POLARITY_LOW
1528 * @retval None
1529 */
1530 __STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
1531 {
1532 MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
1533 }
1534
1535 /**
1536 * @brief Return Driver Enable Polarity
1537 * @rmtoll CR3 DEP LL_LPUART_GetDESignalPolarity
1538 * @param LPUARTx LPUART Instance
1539 * @retval Returned value can be one of the following values:
1540 * @arg @ref LL_LPUART_DE_POLARITY_HIGH
1541 * @arg @ref LL_LPUART_DE_POLARITY_LOW
1542 */
1543 __STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx)
1544 {
1545 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
1546 }
1547
1548 /**
1549 * @}
1550 */
1551
1552 /** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
1553 * @{
1554 */
1555
1556 /**
1557 * @brief Check if the LPUART Parity Error Flag is set or not
1558 * @rmtoll ISR PE LL_LPUART_IsActiveFlag_PE
1559 * @param LPUARTx LPUART Instance
1560 * @retval State of bit (1 or 0).
1561 */
1562 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx)
1563 {
1564 return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
1565 }
1566
1567 /**
1568 * @brief Check if the LPUART Framing Error Flag is set or not
1569 * @rmtoll ISR FE LL_LPUART_IsActiveFlag_FE
1570 * @param LPUARTx LPUART Instance
1571 * @retval State of bit (1 or 0).
1572 */
1573 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx)
1574 {
1575 return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
1576 }
1577
1578 /**
1579 * @brief Check if the LPUART Noise error detected Flag is set or not
1580 * @rmtoll ISR NE LL_LPUART_IsActiveFlag_NE
1581 * @param LPUARTx LPUART Instance
1582 * @retval State of bit (1 or 0).
1583 */
1584 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx)
1585 {
1586 return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
1587 }
1588
1589 /**
1590 * @brief Check if the LPUART OverRun Error Flag is set or not
1591 * @rmtoll ISR ORE LL_LPUART_IsActiveFlag_ORE
1592 * @param LPUARTx LPUART Instance
1593 * @retval State of bit (1 or 0).
1594 */
1595 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx)
1596 {
1597 return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
1598 }
1599
1600 /**
1601 * @brief Check if the LPUART IDLE line detected Flag is set or not
1602 * @rmtoll ISR IDLE LL_LPUART_IsActiveFlag_IDLE
1603 * @param LPUARTx LPUART Instance
1604 * @retval State of bit (1 or 0).
1605 */
1606 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx)
1607 {
1608 return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
1609 }
1610
1611 /* Legacy define */
1612 #define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
1613
1614 /**
1615 * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not
1616 * @rmtoll ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
1617 * @param LPUARTx LPUART Instance
1618 * @retval State of bit (1 or 0).
1619 */
1620 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *LPUARTx)
1621 {
1622 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
1623 }
1624
1625 /**
1626 * @brief Check if the LPUART Transmission Complete Flag is set or not
1627 * @rmtoll ISR TC LL_LPUART_IsActiveFlag_TC
1628 * @param LPUARTx LPUART Instance
1629 * @retval State of bit (1 or 0).
1630 */
1631 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx)
1632 {
1633 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
1634 }
1635
1636 /* Legacy define */
1637 #define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF
1638
1639 /**
1640 * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not
1641 * @rmtoll ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF
1642 * @param LPUARTx LPUART Instance
1643 * @retval State of bit (1 or 0).
1644 */
1645 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *LPUARTx)
1646 {
1647 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
1648 }
1649
1650 /**
1651 * @brief Check if the LPUART CTS interrupt Flag is set or not
1652 * @rmtoll ISR CTSIF LL_LPUART_IsActiveFlag_nCTS
1653 * @param LPUARTx LPUART Instance
1654 * @retval State of bit (1 or 0).
1655 */
1656 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx)
1657 {
1658 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
1659 }
1660
1661 /**
1662 * @brief Check if the LPUART CTS Flag is set or not
1663 * @rmtoll ISR CTS LL_LPUART_IsActiveFlag_CTS
1664 * @param LPUARTx LPUART Instance
1665 * @retval State of bit (1 or 0).
1666 */
1667 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx)
1668 {
1669 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
1670 }
1671
1672 /**
1673 * @brief Check if the LPUART Busy Flag is set or not
1674 * @rmtoll ISR BUSY LL_LPUART_IsActiveFlag_BUSY
1675 * @param LPUARTx LPUART Instance
1676 * @retval State of bit (1 or 0).
1677 */
1678 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx)
1679 {
1680 return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
1681 }
1682
1683 /**
1684 * @brief Check if the LPUART Character Match Flag is set or not
1685 * @rmtoll ISR CMF LL_LPUART_IsActiveFlag_CM
1686 * @param LPUARTx LPUART Instance
1687 * @retval State of bit (1 or 0).
1688 */
1689 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx)
1690 {
1691 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
1692 }
1693
1694 /**
1695 * @brief Check if the LPUART Send Break Flag is set or not
1696 * @rmtoll ISR SBKF LL_LPUART_IsActiveFlag_SBK
1697 * @param LPUARTx LPUART Instance
1698 * @retval State of bit (1 or 0).
1699 */
1700 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx)
1701 {
1702 return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
1703 }
1704
1705 /**
1706 * @brief Check if the LPUART Receive Wake Up from mute mode Flag is set or not
1707 * @rmtoll ISR RWU LL_LPUART_IsActiveFlag_RWU
1708 * @param LPUARTx LPUART Instance
1709 * @retval State of bit (1 or 0).
1710 */
1711 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx)
1712 {
1713 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
1714 }
1715
1716 /**
1717 * @brief Check if the LPUART Wake Up from stop mode Flag is set or not
1718 * @rmtoll ISR WUF LL_LPUART_IsActiveFlag_WKUP
1719 * @param LPUARTx LPUART Instance
1720 * @retval State of bit (1 or 0).
1721 */
1722 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx)
1723 {
1724 return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
1725 }
1726
1727 /**
1728 * @brief Check if the LPUART Transmit Enable Acknowledge Flag is set or not
1729 * @rmtoll ISR TEACK LL_LPUART_IsActiveFlag_TEACK
1730 * @param LPUARTx LPUART Instance
1731 * @retval State of bit (1 or 0).
1732 */
1733 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx)
1734 {
1735 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
1736 }
1737
1738 /**
1739 * @brief Check if the LPUART Receive Enable Acknowledge Flag is set or not
1740 * @rmtoll ISR REACK LL_LPUART_IsActiveFlag_REACK
1741 * @param LPUARTx LPUART Instance
1742 * @retval State of bit (1 or 0).
1743 */
1744 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx)
1745 {
1746 return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
1747 }
1748
1749 /**
1750 * @brief Check if the LPUART TX FIFO Empty Flag is set or not
1751 * @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE
1752 * @param LPUARTx LPUART Instance
1753 * @retval State of bit (1 or 0).
1754 */
1755 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef *LPUARTx)
1756 {
1757 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
1758 }
1759
1760 /**
1761 * @brief Check if the LPUART RX FIFO Full Flag is set or not
1762 * @rmtoll ISR RXFF LL_LPUART_IsActiveFlag_RXFF
1763 * @param LPUARTx LPUART Instance
1764 * @retval State of bit (1 or 0).
1765 */
1766 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef *LPUARTx)
1767 {
1768 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
1769 }
1770
1771 /**
1772 * @brief Check if the LPUART TX FIFO Threshold Flag is set or not
1773 * @rmtoll ISR TXFT LL_LPUART_IsActiveFlag_TXFT
1774 * @param LPUARTx LPUART Instance
1775 * @retval State of bit (1 or 0).
1776 */
1777 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef *LPUARTx)
1778 {
1779 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
1780 }
1781
1782 /**
1783 * @brief Check if the LPUART RX FIFO Threshold Flag is set or not
1784 * @rmtoll ISR RXFT LL_LPUART_IsActiveFlag_RXFT
1785 * @param LPUARTx LPUART Instance
1786 * @retval State of bit (1 or 0).
1787 */
1788 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(USART_TypeDef *LPUARTx)
1789 {
1790 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
1791 }
1792
1793 /**
1794 * @brief Clear Parity Error Flag
1795 * @rmtoll ICR PECF LL_LPUART_ClearFlag_PE
1796 * @param LPUARTx LPUART Instance
1797 * @retval None
1798 */
1799 __STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
1800 {
1801 WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
1802 }
1803
1804 /**
1805 * @brief Clear Framing Error Flag
1806 * @rmtoll ICR FECF LL_LPUART_ClearFlag_FE
1807 * @param LPUARTx LPUART Instance
1808 * @retval None
1809 */
1810 __STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
1811 {
1812 WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
1813 }
1814
1815 /**
1816 * @brief Clear Noise detected Flag
1817 * @rmtoll ICR NECF LL_LPUART_ClearFlag_NE
1818 * @param LPUARTx LPUART Instance
1819 * @retval None
1820 */
1821 __STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
1822 {
1823 WRITE_REG(LPUARTx->ICR, USART_ICR_NECF);
1824 }
1825
1826 /**
1827 * @brief Clear OverRun Error Flag
1828 * @rmtoll ICR ORECF LL_LPUART_ClearFlag_ORE
1829 * @param LPUARTx LPUART Instance
1830 * @retval None
1831 */
1832 __STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
1833 {
1834 WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
1835 }
1836
1837 /**
1838 * @brief Clear IDLE line detected Flag
1839 * @rmtoll ICR IDLECF LL_LPUART_ClearFlag_IDLE
1840 * @param LPUARTx LPUART Instance
1841 * @retval None
1842 */
1843 __STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
1844 {
1845 WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
1846 }
1847
1848 /**
1849 * @brief Clear TX FIFO Empty Flag
1850 * @rmtoll ICR TXFECF LL_LPUART_ClearFlag_TXFE
1851 * @param LPUARTx LPUART Instance
1852 * @retval None
1853 */
1854 __STATIC_INLINE void LL_LPUART_ClearFlag_TXFE(USART_TypeDef *LPUARTx)
1855 {
1856 WRITE_REG(LPUARTx->ICR, USART_ICR_TXFECF);
1857 }
1858
1859 /**
1860 * @brief Clear Transmission Complete Flag
1861 * @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC
1862 * @param LPUARTx LPUART Instance
1863 * @retval None
1864 */
1865 __STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
1866 {
1867 WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
1868 }
1869
1870 /**
1871 * @brief Clear CTS Interrupt Flag
1872 * @rmtoll ICR CTSCF LL_LPUART_ClearFlag_nCTS
1873 * @param LPUARTx LPUART Instance
1874 * @retval None
1875 */
1876 __STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
1877 {
1878 WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
1879 }
1880
1881 /**
1882 * @brief Clear Character Match Flag
1883 * @rmtoll ICR CMCF LL_LPUART_ClearFlag_CM
1884 * @param LPUARTx LPUART Instance
1885 * @retval None
1886 */
1887 __STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
1888 {
1889 WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
1890 }
1891
1892 /**
1893 * @brief Clear Wake Up from stop mode Flag
1894 * @rmtoll ICR WUCF LL_LPUART_ClearFlag_WKUP
1895 * @param LPUARTx LPUART Instance
1896 * @retval None
1897 */
1898 __STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)
1899 {
1900 WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
1901 }
1902
1903 /**
1904 * @}
1905 */
1906
1907 /** @defgroup LPUART_LL_EF_IT_Management IT_Management
1908 * @{
1909 */
1910
1911 /**
1912 * @brief Enable IDLE Interrupt
1913 * @rmtoll CR1 IDLEIE LL_LPUART_EnableIT_IDLE
1914 * @param LPUARTx LPUART Instance
1915 * @retval None
1916 */
1917 __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
1918 {
1919 SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
1920 }
1921
1922 /* Legacy define */
1923 #define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE
1924
1925 /**
1926 * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt
1927 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE
1928 * @param LPUARTx LPUART Instance
1929 * @retval None
1930 */
1931 __STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
1932 {
1933 SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
1934 }
1935
1936 /**
1937 * @brief Enable Transmission Complete Interrupt
1938 * @rmtoll CR1 TCIE LL_LPUART_EnableIT_TC
1939 * @param LPUARTx LPUART Instance
1940 * @retval None
1941 */
1942 __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
1943 {
1944 SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
1945 }
1946
1947 /* Legacy define */
1948 #define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF
1949
1950 /**
1951 * @brief Enable TX Empty and TX FIFO Not Full Interrupt
1952 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF
1953 * @param LPUARTx LPUART Instance
1954 * @retval None
1955 */
1956 __STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
1957 {
1958 SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
1959 }
1960
1961 /**
1962 * @brief Enable Parity Error Interrupt
1963 * @rmtoll CR1 PEIE LL_LPUART_EnableIT_PE
1964 * @param LPUARTx LPUART Instance
1965 * @retval None
1966 */
1967 __STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
1968 {
1969 SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
1970 }
1971
1972 /**
1973 * @brief Enable Character Match Interrupt
1974 * @rmtoll CR1 CMIE LL_LPUART_EnableIT_CM
1975 * @param LPUARTx LPUART Instance
1976 * @retval None
1977 */
1978 __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
1979 {
1980 SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
1981 }
1982
1983 /**
1984 * @brief Enable TX FIFO Empty Interrupt
1985 * @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE
1986 * @param LPUARTx LPUART Instance
1987 * @retval None
1988 */
1989 __STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx)
1990 {
1991 SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
1992 }
1993
1994 /**
1995 * @brief Enable RX FIFO Full Interrupt
1996 * @rmtoll CR1 RXFFIE LL_LPUART_EnableIT_RXFF
1997 * @param LPUARTx LPUART Instance
1998 * @retval None
1999 */
2000 __STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx)
2001 {
2002 SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
2003 }
2004
2005 /**
2006 * @brief Enable Error Interrupt
2007 * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
2008 * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
2009 * - 0: Interrupt is inhibited
2010 * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
2011 * @rmtoll CR3 EIE LL_LPUART_EnableIT_ERROR
2012 * @param LPUARTx LPUART Instance
2013 * @retval None
2014 */
2015 __STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
2016 {
2017 SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
2018 }
2019
2020 /**
2021 * @brief Enable CTS Interrupt
2022 * @rmtoll CR3 CTSIE LL_LPUART_EnableIT_CTS
2023 * @param LPUARTx LPUART Instance
2024 * @retval None
2025 */
2026 __STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
2027 {
2028 SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
2029 }
2030
2031 /**
2032 * @brief Enable Wake Up from Stop Mode Interrupt
2033 * @rmtoll CR3 WUFIE LL_LPUART_EnableIT_WKUP
2034 * @param LPUARTx LPUART Instance
2035 * @retval None
2036 */
2037 __STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
2038 {
2039 SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
2040 }
2041
2042 /**
2043 * @brief Enable TX FIFO Threshold Interrupt
2044 * @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT
2045 * @param LPUARTx LPUART Instance
2046 * @retval None
2047 */
2048 __STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx)
2049 {
2050 SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
2051 }
2052
2053 /**
2054 * @brief Enable RX FIFO Threshold Interrupt
2055 * @rmtoll CR3 RXFTIE LL_LPUART_EnableIT_RXFT
2056 * @param LPUARTx LPUART Instance
2057 * @retval None
2058 */
2059 __STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx)
2060 {
2061 SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
2062 }
2063
2064 /**
2065 * @brief Disable IDLE Interrupt
2066 * @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE
2067 * @param LPUARTx LPUART Instance
2068 * @retval None
2069 */
2070 __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
2071 {
2072 CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
2073 }
2074
2075 /* Legacy define */
2076 #define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE
2077
2078 /**
2079 * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt
2080 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE
2081 * @param LPUARTx LPUART Instance
2082 * @retval None
2083 */
2084 __STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
2085 {
2086 CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
2087 }
2088
2089 /**
2090 * @brief Disable Transmission Complete Interrupt
2091 * @rmtoll CR1 TCIE LL_LPUART_DisableIT_TC
2092 * @param LPUARTx LPUART Instance
2093 * @retval None
2094 */
2095 __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
2096 {
2097 CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
2098 }
2099
2100 /* Legacy define */
2101 #define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF
2102
2103 /**
2104 * @brief Disable TX Empty and TX FIFO Not Full Interrupt
2105 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF
2106 * @param LPUARTx LPUART Instance
2107 * @retval None
2108 */
2109 __STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
2110 {
2111 CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
2112 }
2113
2114 /**
2115 * @brief Disable Parity Error Interrupt
2116 * @rmtoll CR1 PEIE LL_LPUART_DisableIT_PE
2117 * @param LPUARTx LPUART Instance
2118 * @retval None
2119 */
2120 __STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
2121 {
2122 CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
2123 }
2124
2125 /**
2126 * @brief Disable Character Match Interrupt
2127 * @rmtoll CR1 CMIE LL_LPUART_DisableIT_CM
2128 * @param LPUARTx LPUART Instance
2129 * @retval None
2130 */
2131 __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
2132 {
2133 CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
2134 }
2135
2136 /**
2137 * @brief Disable TX FIFO Empty Interrupt
2138 * @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE
2139 * @param LPUARTx LPUART Instance
2140 * @retval None
2141 */
2142 __STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx)
2143 {
2144 CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
2145 }
2146
2147 /**
2148 * @brief Disable RX FIFO Full Interrupt
2149 * @rmtoll CR1 RXFFIE LL_LPUART_DisableIT_RXFF
2150 * @param LPUARTx LPUART Instance
2151 * @retval None
2152 */
2153 __STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx)
2154 {
2155 CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
2156 }
2157
2158 /**
2159 * @brief Disable Error Interrupt
2160 * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
2161 * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
2162 * - 0: Interrupt is inhibited
2163 * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
2164 * @rmtoll CR3 EIE LL_LPUART_DisableIT_ERROR
2165 * @param LPUARTx LPUART Instance
2166 * @retval None
2167 */
2168 __STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
2169 {
2170 CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
2171 }
2172
2173 /**
2174 * @brief Disable CTS Interrupt
2175 * @rmtoll CR3 CTSIE LL_LPUART_DisableIT_CTS
2176 * @param LPUARTx LPUART Instance
2177 * @retval None
2178 */
2179 __STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
2180 {
2181 CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
2182 }
2183
2184 /**
2185 * @brief Disable Wake Up from Stop Mode Interrupt
2186 * @rmtoll CR3 WUFIE LL_LPUART_DisableIT_WKUP
2187 * @param LPUARTx LPUART Instance
2188 * @retval None
2189 */
2190 __STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
2191 {
2192 CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
2193 }
2194
2195 /**
2196 * @brief Disable TX FIFO Threshold Interrupt
2197 * @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT
2198 * @param LPUARTx LPUART Instance
2199 * @retval None
2200 */
2201 __STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx)
2202 {
2203 CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
2204 }
2205
2206 /**
2207 * @brief Disable RX FIFO Threshold Interrupt
2208 * @rmtoll CR3 RXFTIE LL_LPUART_DisableIT_RXFT
2209 * @param LPUARTx LPUART Instance
2210 * @retval None
2211 */
2212 __STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx)
2213 {
2214 CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
2215 }
2216
2217 /**
2218 * @brief Check if the LPUART IDLE Interrupt source is enabled or disabled.
2219 * @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE
2220 * @param LPUARTx LPUART Instance
2221 * @retval State of bit (1 or 0).
2222 */
2223 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx)
2224 {
2225 return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
2226 }
2227
2228 /* Legacy define */
2229 #define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE
2230
2231 /**
2232 * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
2233 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE
2234 * @param LPUARTx LPUART Instance
2235 * @retval State of bit (1 or 0).
2236 */
2237 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
2238 {
2239 return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
2240 }
2241
2242 /**
2243 * @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
2244 * @rmtoll CR1 TCIE LL_LPUART_IsEnabledIT_TC
2245 * @param LPUARTx LPUART Instance
2246 * @retval State of bit (1 or 0).
2247 */
2248 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx)
2249 {
2250 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
2251 }
2252
2253 /* Legacy define */
2254 #define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF
2255
2256 /**
2257 * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled
2258 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF
2259 * @param LPUARTx LPUART Instance
2260 * @retval State of bit (1 or 0).
2261 */
2262 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
2263 {
2264 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
2265 }
2266
2267 /**
2268 * @brief Check if the LPUART Parity Error Interrupt is enabled or disabled.
2269 * @rmtoll CR1 PEIE LL_LPUART_IsEnabledIT_PE
2270 * @param LPUARTx LPUART Instance
2271 * @retval State of bit (1 or 0).
2272 */
2273 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx)
2274 {
2275 return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
2276 }
2277
2278 /**
2279 * @brief Check if the LPUART Character Match Interrupt is enabled or disabled.
2280 * @rmtoll CR1 CMIE LL_LPUART_IsEnabledIT_CM
2281 * @param LPUARTx LPUART Instance
2282 * @retval State of bit (1 or 0).
2283 */
2284 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx)
2285 {
2286 return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
2287 }
2288
2289 /**
2290 * @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled
2291 * @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE
2292 * @param LPUARTx LPUART Instance
2293 * @retval State of bit (1 or 0).
2294 */
2295 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef *LPUARTx)
2296 {
2297 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
2298 }
2299
2300 /**
2301 * @brief Check if the LPUART RX FIFO Full Interrupt is enabled or disabled
2302 * @rmtoll CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF
2303 * @param LPUARTx LPUART Instance
2304 * @retval State of bit (1 or 0).
2305 */
2306 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef *LPUARTx)
2307 {
2308 return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
2309 }
2310
2311 /**
2312 * @brief Check if the LPUART Error Interrupt is enabled or disabled.
2313 * @rmtoll CR3 EIE LL_LPUART_IsEnabledIT_ERROR
2314 * @param LPUARTx LPUART Instance
2315 * @retval State of bit (1 or 0).
2316 */
2317 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx)
2318 {
2319 return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
2320 }
2321
2322 /**
2323 * @brief Check if the LPUART CTS Interrupt is enabled or disabled.
2324 * @rmtoll CR3 CTSIE LL_LPUART_IsEnabledIT_CTS
2325 * @param LPUARTx LPUART Instance
2326 * @retval State of bit (1 or 0).
2327 */
2328 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx)
2329 {
2330 return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
2331 }
2332
2333 /**
2334 * @brief Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
2335 * @rmtoll CR3 WUFIE LL_LPUART_IsEnabledIT_WKUP
2336 * @param LPUARTx LPUART Instance
2337 * @retval State of bit (1 or 0).
2338 */
2339 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx)
2340 {
2341 return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
2342 }
2343
2344 /**
2345 * @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled
2346 * @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT
2347 * @param LPUARTx LPUART Instance
2348 * @retval State of bit (1 or 0).
2349 */
2350 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef *LPUARTx)
2351 {
2352 return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
2353 }
2354
2355 /**
2356 * @brief Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled
2357 * @rmtoll CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT
2358 * @param LPUARTx LPUART Instance
2359 * @retval State of bit (1 or 0).
2360 */
2361 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(USART_TypeDef *LPUARTx)
2362 {
2363 return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
2364 }
2365
2366 /**
2367 * @}
2368 */
2369
2370 /** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
2371 * @{
2372 */
2373
2374 /**
2375 * @brief Enable DMA Mode for reception
2376 * @rmtoll CR3 DMAR LL_LPUART_EnableDMAReq_RX
2377 * @param LPUARTx LPUART Instance
2378 * @retval None
2379 */
2380 __STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
2381 {
2382 SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
2383 }
2384
2385 /**
2386 * @brief Disable DMA Mode for reception
2387 * @rmtoll CR3 DMAR LL_LPUART_DisableDMAReq_RX
2388 * @param LPUARTx LPUART Instance
2389 * @retval None
2390 */
2391 __STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
2392 {
2393 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
2394 }
2395
2396 /**
2397 * @brief Check if DMA Mode is enabled for reception
2398 * @rmtoll CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX
2399 * @param LPUARTx LPUART Instance
2400 * @retval State of bit (1 or 0).
2401 */
2402 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx)
2403 {
2404 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
2405 }
2406
2407 /**
2408 * @brief Enable DMA Mode for transmission
2409 * @rmtoll CR3 DMAT LL_LPUART_EnableDMAReq_TX
2410 * @param LPUARTx LPUART Instance
2411 * @retval None
2412 */
2413 __STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
2414 {
2415 SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
2416 }
2417
2418 /**
2419 * @brief Disable DMA Mode for transmission
2420 * @rmtoll CR3 DMAT LL_LPUART_DisableDMAReq_TX
2421 * @param LPUARTx LPUART Instance
2422 * @retval None
2423 */
2424 __STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
2425 {
2426 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
2427 }
2428
2429 /**
2430 * @brief Check if DMA Mode is enabled for transmission
2431 * @rmtoll CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX
2432 * @param LPUARTx LPUART Instance
2433 * @retval State of bit (1 or 0).
2434 */
2435 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx)
2436 {
2437 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
2438 }
2439
2440 /**
2441 * @brief Enable DMA Disabling on Reception Error
2442 * @rmtoll CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr
2443 * @param LPUARTx LPUART Instance
2444 * @retval None
2445 */
2446 __STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
2447 {
2448 SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
2449 }
2450
2451 /**
2452 * @brief Disable DMA Disabling on Reception Error
2453 * @rmtoll CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr
2454 * @param LPUARTx LPUART Instance
2455 * @retval None
2456 */
2457 __STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
2458 {
2459 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
2460 }
2461
2462 /**
2463 * @brief Indicate if DMA Disabling on Reception Error is disabled
2464 * @rmtoll CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr
2465 * @param LPUARTx LPUART Instance
2466 * @retval State of bit (1 or 0).
2467 */
2468 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx)
2469 {
2470 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
2471 }
2472
2473 /**
2474 * @brief Get the LPUART data register address used for DMA transfer
2475 * @rmtoll RDR RDR LL_LPUART_DMA_GetRegAddr\n
2476 * @rmtoll TDR TDR LL_LPUART_DMA_GetRegAddr
2477 * @param LPUARTx LPUART Instance
2478 * @param Direction This parameter can be one of the following values:
2479 * @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
2480 * @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
2481 * @retval Address of data register
2482 */
2483 __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction)
2484 {
2485 uint32_t data_reg_addr;
2486
2487 if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
2488 {
2489 /* return address of TDR register */
2490 data_reg_addr = (uint32_t) &(LPUARTx->TDR);
2491 }
2492 else
2493 {
2494 /* return address of RDR register */
2495 data_reg_addr = (uint32_t) &(LPUARTx->RDR);
2496 }
2497
2498 return data_reg_addr;
2499 }
2500
2501 /**
2502 * @}
2503 */
2504
2505 /** @defgroup LPUART_LL_EF_Data_Management Data_Management
2506 * @{
2507 */
2508
2509 /**
2510 * @brief Read Receiver Data register (Receive Data value, 8 bits)
2511 * @rmtoll RDR RDR LL_LPUART_ReceiveData8
2512 * @param LPUARTx LPUART Instance
2513 * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
2514 */
2515 __STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx)
2516 {
2517 return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
2518 }
2519
2520 /**
2521 * @brief Read Receiver Data register (Receive Data value, 9 bits)
2522 * @rmtoll RDR RDR LL_LPUART_ReceiveData9
2523 * @param LPUARTx LPUART Instance
2524 * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
2525 */
2526 __STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx)
2527 {
2528 return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
2529 }
2530
2531 /**
2532 * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
2533 * @rmtoll TDR TDR LL_LPUART_TransmitData8
2534 * @param LPUARTx LPUART Instance
2535 * @param Value between Min_Data=0x00 and Max_Data=0xFF
2536 * @retval None
2537 */
2538 __STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
2539 {
2540 LPUARTx->TDR = Value;
2541 }
2542
2543 /**
2544 * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
2545 * @rmtoll TDR TDR LL_LPUART_TransmitData9
2546 * @param LPUARTx LPUART Instance
2547 * @param Value between Min_Data=0x00 and Max_Data=0x1FF
2548 * @retval None
2549 */
2550 __STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
2551 {
2552 LPUARTx->TDR = Value & 0x1FFUL;
2553 }
2554
2555 /**
2556 * @}
2557 */
2558
2559 /** @defgroup LPUART_LL_EF_Execution Execution
2560 * @{
2561 */
2562
2563 /**
2564 * @brief Request Break sending
2565 * @rmtoll RQR SBKRQ LL_LPUART_RequestBreakSending
2566 * @param LPUARTx LPUART Instance
2567 * @retval None
2568 */
2569 __STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
2570 {
2571 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
2572 }
2573
2574 /**
2575 * @brief Put LPUART in mute mode and set the RWU flag
2576 * @rmtoll RQR MMRQ LL_LPUART_RequestEnterMuteMode
2577 * @param LPUARTx LPUART Instance
2578 * @retval None
2579 */
2580 __STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
2581 {
2582 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ);
2583 }
2584
2585 /**
2586 * @brief Request a Receive Data and FIFO flush
2587 * @note Allows to discard the received data without reading them, and avoid an overrun
2588 * condition.
2589 * @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush
2590 * @param LPUARTx LPUART Instance
2591 * @retval None
2592 */
2593 __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
2594 {
2595 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
2596 }
2597
2598 /**
2599 * @}
2600 */
2601
2602 #if defined(USE_FULL_LL_DRIVER)
2603 /** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
2604 * @{
2605 */
2606 ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx);
2607 ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct);
2608 void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
2609 /**
2610 * @}
2611 */
2612 #endif /* USE_FULL_LL_DRIVER */
2613
2614 /**
2615 * @}
2616 */
2617
2618 /**
2619 * @}
2620 */
2621
2622 #endif /* LPUART1 */
2623
2624 /**
2625 * @}
2626 */
2627
2628 #ifdef __cplusplus
2629 }
2630 #endif
2631
2632 #endif /* STM32H7xx_LL_LPUART_H */
2633
2634 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/