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Merge pull request #11270 from haslinghuis/rename_attr
[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_ll_pwr.h
blob98602e2296b3d1642ce4c00266480ee3f10e5335
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_LL_PWR_H
22 #define STM32H7xx_LL_PWR_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx.h"
30
31 /** @addtogroup STM32H7xx_LL_Driver
32 * @{
33 */
34
35 #if defined (PWR)
36
37 /** @defgroup PWR_LL PWR
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup PWR_LL_Private_Constants PWR Private Constants
45 * @{
46 */
47
48 /** @defgroup PWR_LL_WAKEUP_PIN_OFFSET Wake-Up Pins register offsets Defines
49 * @brief Flags defines which can be used with LL_PWR_WriteReg function
50 * @{
51 */
52 /* Wake-Up Pins PWR register offsets */
53 #define LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET 2UL
54 #define LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK 0x1FU
55 /**
56 * @}
57 */
58 /**
59 * @}
60 */
61 /* Private macros ------------------------------------------------------------*/
62 /* Exported types ------------------------------------------------------------*/
63 /* Exported constants --------------------------------------------------------*/
64 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
65 * @{
66 */
67
68 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
69 * @brief Flags defines which can be used with LL_PWR_WriteReg function
70 * @{
71 */
72 #define LL_PWR_FLAG_CPU_CSSF PWR_CPUCR_CSSF /*!< Clear flags for CPU */
73 #if defined (DUAL_CORE)
74 #define LL_PWR_FLAG_CPU2_CSSF PWR_CPU2CR_CSSF /*!< Clear flags for CPU2 */
75 #endif /* DUAL_CORE */
76 #define LL_PWR_FLAG_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6 /*!< Clear PC1 WKUP flag */
77 #if defined (PWR_WKUPCR_WKUPC5)
78 #define LL_PWR_FLAG_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5 /*!< Clear PI11 WKUP flag */
79 #endif /* defined (PWR_WKUPCR_WKUPC5) */
80 #define LL_PWR_FLAG_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4 /*!< Clear PC13 WKUP flag */
81 #if defined (PWR_WKUPCR_WKUPC3)
82 #define LL_PWR_FLAG_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3 /*!< Clear PI8 WKUP flag */
83 #endif /* defined (PWR_WKUPCR_WKUPC3) */
84 #define LL_PWR_FLAG_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2 /*!< Clear PA2 WKUP flag */
85 #define LL_PWR_FLAG_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1 /*!< Clear PA0 WKUP flag */
86 /**
87 * @}
88 */
89
90 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
91 * @brief Flags defines which can be used with LL_PWR_ReadReg function
92 * @{
93 */
94 #define LL_PWR_FLAG_AVDO PWR_CSR1_AVDO /*!< Analog voltage detector output on VDDA flag */
95 #define LL_PWR_FLAG_PVDO PWR_CSR1_PVDO /*!< Programmable voltage detect output flag */
96 #define LL_PWR_FLAG_ACTVOS PWR_CSR1_ACTVOS /*!< Current VOS applied for VCORE voltage scaling flag */
97 #define LL_PWR_FLAG_ACTVOSRDY PWR_CSR1_ACTVOSRDY /*!< Ready bit for current actual used VOS for VCORE voltage scaling flag */
98 #if defined (PWR_CSR1_MMCVDO)
99 #define LL_PWR_FLAG_MMCVDO PWR_CSR1_MMCVDO /*!< Voltage detector output on VDDMMC flag */
100 #endif /* PWR_CSR1_MMCVDO */
101
102 #define LL_PWR_FLAG_TEMPH PWR_CR2_TEMPH /*!< Temperature high threshold flag */
103 #define LL_PWR_FLAG_TEMPL PWR_CR2_TEMPL /*!< Temperature low threshold flag */
104 #define LL_PWR_FLAG_VBATH PWR_CR2_VBATH /*!< VBAT high threshold flag */
105 #define LL_PWR_FLAG_VBATL PWR_CR2_VBATL /*!< VBAT low threshold flag */
106 #define LL_PWR_FLAG_BRRDY PWR_CR2_BRRDY /*!< Backup Regulator ready flag */
107
108 #define LL_PWR_FLAG_USBRDY PWR_CR3_USB33RDY /*!< USB supply ready flag */
109 #define LL_PWR_FLAG_SMPSEXTRDY PWR_CR3_SMPSEXTRDY /*!< SMPS External supply ready flag */
110
111 #if defined (PWR_CPUCR_SBF_D2)
112 #define LL_PWR_FLAG_CPU_SBF_D2 PWR_CPUCR_SBF_D2 /*!< D2 domain DSTANDBY Flag */
113 #endif /* PWR_CPUCR_SBF_D2 */
114 #if defined (PWR_CPUCR_SBF_D1)
115 #define LL_PWR_FLAG_CPU_SBF_D1 PWR_CPUCR_SBF_D1 /*!< D1 domain DSTANDBY Flag */
116 #endif /* PWR_CPUCR_SBF_D1 */
117 #define LL_PWR_FLAG_CPU_SBF PWR_CPUCR_SBF /*!< System STANDBY Flag */
118 #define LL_PWR_FLAG_CPU_STOPF PWR_CPUCR_STOPF /*!< STOP Flag */
119 #if defined (DUAL_CORE)
120 #define LL_PWR_FLAG_CPU_HOLD2F PWR_CPUCR_HOLD2F /*!< CPU2 in hold wakeup flag */
121 #endif /* DUAL_CORE */
122
123 #if defined (DUAL_CORE)
124 #define LL_PWR_FLAG_CPU2_SBF_D2 PWR_CPU2CR_SBF_D2 /*!< D2 domain DSTANDBY Flag */
125 #define LL_PWR_FLAG_CPU2_SBF_D1 PWR_CPU2CR_SBF_D1 /*!< D1 domain DSTANDBY Flag */
126 #define LL_PWR_FLAG_CPU2_SBF PWR_CPU2CR_SBF /*!< System STANDBY Flag */
127 #define LL_PWR_FLAG_CPU2_STOPF PWR_CPU2CR_STOPF /*!< STOP Flag */
128 #define LL_PWR_FLAG_CPU2_HOLD1F PWR_CPU2CR_HOLD1F /*!< CPU1 in hold wakeup flag */
129 #endif /* DUAL_CORE */
130
131 #if defined (PWR_CPUCR_PDDS_D2)
132 #define LL_PWR_D3CR_VOSRDY PWR_D3CR_VOSRDY /*!< Voltage scaling ready flag */
133 #else
134 #define LL_PWR_SRDCR_VOSRDY PWR_SRDCR_VOSRDY /*!< Voltage scaling ready flag */
135 #endif /* PWR_CPUCR_PDDS_D2 */
136
137 #define LL_PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6 /*!< Wakeup flag on PC1 */
138 #if defined (PWR_WKUPFR_WKUPF5)
139 #define LL_PWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5 /*!< Wakeup flag on PI11 */
140 #endif /* defined (PWR_WKUPFR_WKUPF5) */
141 #define LL_PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4 /*!< Wakeup flag on PC13 */
142 #if defined (PWR_WKUPFR_WKUPF3)
143 #define LL_PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3 /*!< Wakeup flag on PI8 */
144 #endif /* defined (PWR_WKUPFR_WKUPF3) */
145 #define LL_PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2 /*!< Wakeup flag on PA2 */
146 #define LL_PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1 /*!< Wakeup flag on PA0 */
147 /**
148 * @}
149 */
150
151 /** @defgroup PWR_LL_EC_MODE_PWR Power mode
152 * @{
153 */
154 #if defined (PWR_CPUCR_PDDS_D2)
155 #define LL_PWR_CPU_MODE_D1STOP 0x00000000U /*!< Enter D1 domain to Stop mode when the CPU enters deepsleep */
156 #define LL_PWR_CPU_MODE_D1STANDBY PWR_CPUCR_PDDS_D1 /*!< Enter D1 domain to Standby mode when the CPU enters deepsleep */
157 #else
158 #define LL_PWR_CPU_MODE_CDSTOP 0x00000000U /*!< Enter CD domain to Stop mode when the CPU enters deepsleep */
159 #define LL_PWR_CPU_MODE_CDSTOP2 PWR_CPUCR_RETDS_CD /*!< Enter CD domain to Stop2 mode when the CPU enters deepsleep */
160 #endif /* PWR_CPUCR_PDDS_D2 */
161
162 #if defined (PWR_CPUCR_PDDS_D2)
163 #define LL_PWR_CPU_MODE_D2STOP 0x00000000U /*!< Enter D2 domain to Stop mode when the CPU enters deepsleep */
164 #define LL_PWR_CPU_MODE_D2STANDBY PWR_CPUCR_PDDS_D2 /*!< Enter D2 domain to Standby mode when the CPU enters deepsleep */
165 #endif /* PWR_CPUCR_PDDS_D2 */
166
167 #if defined (PWR_CPUCR_PDDS_D2)
168 #define LL_PWR_CPU_MODE_D3RUN PWR_CPUCR_RUN_D3 /*!< Keep system D3 domain in Run mode when the CPU enter deepsleep */
169 #define LL_PWR_CPU_MODE_D3STOP 0x00000000U /*!< Enter D3 domain to Stop mode when the CPU enters deepsleep */
170 #define LL_PWR_CPU_MODE_D3STANDBY PWR_CPUCR_PDDS_D3 /*!< Enter D3 domain to Standby mode when the CPU enters deepsleep */
171 #else
172 #define LL_PWR_CPU_MODE_SRDRUN PWR_CPUCR_RUN_SRD /*!< Keep system SRD domain in Run mode when the CPU enter deepsleep */
173 #define LL_PWR_CPU_MODE_SRDSTOP 0x00000000U /*!< Enter SRD domain to Stop mode when the CPU enters deepsleep */
174 #define LL_PWR_CPU_MODE_SRDSTANDBY PWR_CPUCR_PDDS_SRD /*!< Enter SRD domain to Standby mode when the CPU enters deepsleep */
175 #endif /* PWR_CPUCR_PDDS_D2 */
176
177 #if defined (DUAL_CORE)
178 #define LL_PWR_CPU2_MODE_D1STOP 0x00000000U /*!< Enter D1 domain to Stop mode when the CPU2 enters deepsleep */
179 #define LL_PWR_CPU2_MODE_D1STANDBY PWR_CPU2CR_PDDS_D1 /*!< Enter D1 domain to Standby mode when the CPU2 enters deepsleep */
180 #define LL_PWR_CPU2_MODE_D2STOP 0x00000000U /*!< Enter D2 domain to Stop mode when the CPU2 enters deepsleep */
181 #define LL_PWR_CPU2_MODE_D2STANDBY PWR_CPU2CR_PDDS_D2 /*!< Enter D2 domain to Standby mode when the CPU2 enters deepsleep */
182 #define LL_PWR_CPU2_MODE_D3RUN PWR_CPU2CR_RUN_D3 /*!< Keep system D3 domain in RUN mode when the CPU2 enter deepsleep */
183 #define LL_PWR_CPU2_MODE_D3STOP 0x00000000U /*!< Enter D3 domain to Stop mode when the CPU2 enters deepsleep */
184 #define LL_PWR_CPU2_MODE_D3STANDBY PWR_CPU2CR_PDDS_D3 /*!< Enter D3 domain to Standby mode when the CPU2 enter deepsleep */
185 #endif /* DUAL_CORE */
186 /**
187 * @}
188 */
189
190 /** @defgroup PWR_LL_EC_REGU_VOLTAGE Run mode Regulator Voltage Scaling
191 * @{
192 */
193 #if defined (PWR_CPUCR_PDDS_D2)
194 #define LL_PWR_REGU_VOLTAGE_SCALE3 PWR_D3CR_VOS_0 /*!< Select voltage scale 3 */
195 #define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_D3CR_VOS_1 /*!< Select voltage scale 2 */
196 #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 1 */
197 #if defined (SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */
198 #define LL_PWR_REGU_VOLTAGE_SCALE0 (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 0 */
199 #else
200 #define LL_PWR_REGU_VOLTAGE_SCALE0 0x00000000U /*!< Select voltage scale 0 */
201 #endif /* defined (SYSCFG_PWRCR_ODEN) */
202 #else
203 #define LL_PWR_REGU_VOLTAGE_SCALE3 0x00000000U /*!< Select voltage scale 3 */
204 #define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_D3CR_VOS_0 /*!< Select voltage scale 2 */
205 #define LL_PWR_REGU_VOLTAGE_SCALE1 PWR_D3CR_VOS_1 /*!< Select voltage scale 1 */
206 #define LL_PWR_REGU_VOLTAGE_SCALE0 (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 0 */
207 #endif /* PWR_CPUCR_PDDS_D2 */
208 /**
209 * @}
210 */
211
212 /** @defgroup PWR_LL_EC_STOP_MODE_REGU_VOLTAGE Stop mode Regulator Voltage Scaling
213 * @{
214 */
215 #define LL_PWR_REGU_VOLTAGE_SVOS_SCALE5 PWR_CR1_SVOS_0 /*!< Select voltage scale 5 when system enters STOP mode */
216 #define LL_PWR_REGU_VOLTAGE_SVOS_SCALE4 PWR_CR1_SVOS_1 /*!< Select voltage scale 4 when system enters STOP mode */
217 #define LL_PWR_REGU_VOLTAGE_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1) /*!< Select voltage scale 3 when system enters STOP mode */
218 /**
219 * @}
220 */
221
222 /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
223 * @{
224 */
225 #define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */
226 #define LL_PWR_REGU_DSMODE_LOW_POWER PWR_CR1_LPDS /*!< Voltage Regulator in low-power mode during deepsleep mode */
227 /**
228 * @}
229 */
230
231 /** @defgroup PWR_LL_EC_PVDLEVEL Power Digital Voltage Level Detector
232 * @{
233 */
234 #define LL_PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 /*!< Voltage threshold detected by PVD 1.95 V */
235 #define LL_PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 /*!< Voltage threshold detected by PVD 2.1 V */
236 #define LL_PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 /*!< Voltage threshold detected by PVD 2.25 V */
237 #define LL_PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 /*!< Voltage threshold detected by PVD 2.4 V */
238 #define LL_PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 /*!< Voltage threshold detected by PVD 2.55 V */
239 #define LL_PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 /*!< Voltage threshold detected by PVD 2.7 V */
240 #define LL_PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 /*!< Voltage threshold detected by PVD 2.85 V */
241 #define LL_PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 /*!< External voltage level on PVD_IN pin, compared to internal VREFINT level. */
242 /**
243 * @}
244 */
245
246 /** @defgroup PWR_LL_EC_AVDLEVEL Power Analog Voltage Level Detector
247 * @{
248 */
249 #define LL_PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0 /*!< Analog Voltage threshold detected by AVD 1.7 V */
250 #define LL_PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1 /*!< Analog Voltage threshold detected by AVD 2.1 V */
251 #define LL_PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2 /*!< Analog Voltage threshold detected by AVD 2.5 V */
252 #define LL_PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3 /*!< Analog Voltage threshold detected by AVD 2.8 V */
253
254 /**
255 * @}
256 */
257
258 /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR Battery Charge Resistor
259 * @{
260 */
261 #define LL_PWR_BATT_CHARG_RESISTOR_5K 0x00000000U /*!< Charge the Battery through a 5 kO resistor */
262 #define LL_PWR_BATT_CHARGRESISTOR_1_5K PWR_CR3_VBRS /*!< Charge the Battery through a 1.5 kO resistor */
263 /**
264 * @}
265 */
266
267 /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
268 * @{
269 */
270 #define LL_PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1 /*!< Wake-Up pin 1 : PA0 */
271 #define LL_PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2 /*!< Wake-Up pin 2 : PA2 */
272 #if defined (PWR_WKUPEPR_WKUPEN3)
273 #define LL_PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3 /*!< Wake-Up pin 3 : PI8 */
274 #endif /* defined (PWR_WKUPEPR_WKUPEN3) */
275 #define LL_PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4 /*!< Wake-Up pin 4 : PC13 */
276 #if defined (PWR_WKUPEPR_WKUPEN5)
277 #define LL_PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5 /*!< Wake-Up pin 5 : PI11 */
278 #endif /* defined (PWR_WKUPEPR_WKUPEN5) */
279 #define LL_PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6 /*!< Wake-Up pin 6 : PC1 */
280 /**
281 * @}
282 */
283
284 /** @defgroup PWR_LL_EC_WAKEUP_PIN_PULL Wakeup Pins pull configuration
285 * @{
286 */
287 #define LL_PWR_WAKEUP_PIN_NOPULL 0x00000000UL /*!< Configure Wake-Up pin in no pull */
288 #define LL_PWR_WAKEUP_PIN_PULLUP 0x00000001UL /*!< Configure Wake-Up pin in pull Up */
289 #define LL_PWR_WAKEUP_PIN_PULLDOWN 0x00000002UL /*!< Configure Wake-Up pin in pull Down */
290 /**
291 * @}
292 */
293
294 /** @defgroup PWR_LL_EC_SUPPLY_PWR Power supply source configuration
295 * @{
296 */
297 #define LL_PWR_LDO_SUPPLY PWR_CR3_LDOEN /*!< Core domains are suppplied from the LDO */
298 #if defined (SMPS)
299 #define LL_PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN /*!< Core domains are suppplied from the SMPS */
300 #define LL_PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains */
301 #define LL_PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains */
302 #define LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
303 #define LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
304 #define LL_PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains */
305 #define LL_PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains */
306 #endif /* SMPS */
307 #define LL_PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS /*!< The SMPS and the LDO are Bypassed. The Core domains are supplied from an external source */
308 /**
309 * @}
310 */
311
312 /**
313 * @}
314 */
315 /* Exported macro ------------------------------------------------------------*/
316 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
317 * @{
318 */
319
320 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
321 * @{
322 */
323
324 /**
325 * @brief Write a value in PWR register
326 * @param __REG__ Register to be written
327 * @param __VALUE__ Value to be written in the register
328 * @retval None
329 */
330 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
331
332 /**
333 * @brief Read a value in PWR register
334 * @param __REG__ Register to be read
335 * @retval Register value
336 */
337 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
338 /**
339 * @}
340 */
341
342 /**
343 * @}
344 */
345 /* Exported functions --------------------------------------------------------*/
346 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
347 * @{
348 */
349
350 /** @defgroup PWR_LL_EF_Configuration Configuration
351 * @{
352 */
353
354 /**
355 * @brief Set the voltage Regulator mode during deep sleep mode
356 * @rmtoll CR1 LPDS LL_PWR_SetRegulModeDS
357 * @param RegulMode This parameter can be one of the following values:
358 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
359 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
360 * @retval None
361 */
362 __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
363 {
364 MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, RegulMode);
365 }
366
367 /**
368 * @brief Get the voltage Regulator mode during deep sleep mode
369 * @rmtoll CR1 LPDS LL_PWR_GetRegulModeDS
370 * @retval Returned value can be one of the following values:
371 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
372 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
373 */
374 __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
375 {
376 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPDS));
377 }
378
379 /**
380 * @brief Enable Power Voltage Detector
381 * @rmtoll CR1 PVDEN LL_PWR_EnablePVD
382 * @retval None
383 */
384 __STATIC_INLINE void LL_PWR_EnablePVD(void)
385 {
386 SET_BIT(PWR->CR1, PWR_CR1_PVDEN);
387 }
388
389 /**
390 * @brief Disable Power Voltage Detector
391 * @rmtoll CR1 PVDEN LL_PWR_DisablePVD
392 * @retval None
393 */
394 __STATIC_INLINE void LL_PWR_DisablePVD(void)
395 {
396 CLEAR_BIT(PWR->CR1, PWR_CR1_PVDEN);
397 }
398
399 /**
400 * @brief Check if Power Voltage Detector is enabled
401 * @rmtoll CR1 PVDEN LL_PWR_IsEnabledPVD
402 * @retval State of bit (1 or 0).
403 */
404 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
405 {
406 return ((READ_BIT(PWR->CR1, PWR_CR1_PVDEN) == (PWR_CR1_PVDEN)) ? 1UL : 0UL);
407 }
408
409 /**
410 * @brief Configure the voltage threshold detected by the Power Voltage Detector
411 * @rmtoll CR1 PLS LL_PWR_SetPVDLevel
412 * @param PVDLevel This parameter can be one of the following values:
413 * @arg @ref LL_PWR_PVDLEVEL_0
414 * @arg @ref LL_PWR_PVDLEVEL_1
415 * @arg @ref LL_PWR_PVDLEVEL_2
416 * @arg @ref LL_PWR_PVDLEVEL_3
417 * @arg @ref LL_PWR_PVDLEVEL_4
418 * @arg @ref LL_PWR_PVDLEVEL_5
419 * @arg @ref LL_PWR_PVDLEVEL_6
420 * @arg @ref LL_PWR_PVDLEVEL_7
421 * @retval None
422 */
423 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
424 {
425 MODIFY_REG(PWR->CR1, PWR_CR1_PLS, PVDLevel);
426 }
427
428 /**
429 * @brief Get the voltage threshold detection
430 * @rmtoll CR1 PLS LL_PWR_GetPVDLevel
431 * @retval Returned value can be one of the following values:
432 * @arg @ref LL_PWR_PVDLEVEL_0
433 * @arg @ref LL_PWR_PVDLEVEL_1
434 * @arg @ref LL_PWR_PVDLEVEL_2
435 * @arg @ref LL_PWR_PVDLEVEL_3
436 * @arg @ref LL_PWR_PVDLEVEL_4
437 * @arg @ref LL_PWR_PVDLEVEL_5
438 * @arg @ref LL_PWR_PVDLEVEL_6
439 * @arg @ref LL_PWR_PVDLEVEL_7
440 */
441 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
442 {
443 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_PLS));
444 }
445
446 /**
447 * @brief Enable access to the backup domain
448 * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess
449 * @retval None
450 */
451 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
452 {
453 SET_BIT(PWR->CR1, PWR_CR1_DBP);
454 }
455
456 /**
457 * @brief Disable access to the backup domain
458 * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess
459 * @retval None
460 */
461 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
462 {
463 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
464 }
465
466 /**
467 * @brief Check if the backup domain is enabled
468 * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess
469 * @retval State of bit (1 or 0).
470 */
471 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
472 {
473 return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL);
474 }
475
476 /**
477 * @brief Enable the Flash Power Down in Stop Mode
478 * @rmtoll CR1 FLPS LL_PWR_EnableFlashPowerDown
479 * @retval None
480 */
481 __STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
482 {
483 SET_BIT(PWR->CR1, PWR_CR1_FLPS);
484 }
485
486 /**
487 * @brief Disable the Flash Power Down in Stop Mode
488 * @rmtoll CR1 FLPS LL_PWR_DisableFlashPowerDown
489 * @retval None
490 */
491 __STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
492 {
493 CLEAR_BIT(PWR->CR1, PWR_CR1_FLPS);
494 }
495
496 /**
497 * @brief Check if the Flash Power Down in Stop Mode is enabled
498 * @rmtoll CR1 FLPS LL_PWR_IsEnabledFlashPowerDown
499 * @retval State of bit (1 or 0).
500 */
501 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
502 {
503 return ((READ_BIT(PWR->CR1, PWR_CR1_FLPS) == (PWR_CR1_FLPS)) ? 1UL : 0UL);
504 }
505
506 #if defined (PWR_CR1_BOOSTE)
507 /**
508 * @brief Enable the Analog Voltage Booster (VDDA)
509 * @rmtoll CR1 BOOSTE LL_PWR_EnableAnalogBooster
510 * @retval None
511 */
512 __STATIC_INLINE void LL_PWR_EnableAnalogBooster(void)
513 {
514 SET_BIT(PWR->CR1, PWR_CR1_BOOSTE);
515 }
516
517 /**
518 * @brief Disable the Analog Voltage Booster (VDDA)
519 * @rmtoll CR1 BOOSTE LL_PWR_DisableAnalogBooster
520 * @retval None
521 */
522 __STATIC_INLINE void LL_PWR_DisableAnalogBooster(void)
523 {
524 CLEAR_BIT(PWR->CR1, PWR_CR1_BOOSTE);
525 }
526
527 /**
528 * @brief Check if the Analog Voltage Booster (VDDA) is enabled
529 * @rmtoll CR1 BOOSTE LL_PWR_IsEnabledAnalogBooster
530 * @retval State of bit (1 or 0).
531 */
532 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogBooster(void)
533 {
534 return ((READ_BIT(PWR->CR1, PWR_CR1_BOOSTE) == (PWR_CR1_BOOSTE)) ? 1UL : 0UL);
535 }
536 #endif /* PWR_CR1_BOOSTE */
537
538 #if defined (PWR_CR1_AVD_READY)
539 /**
540 * @brief Enable the Analog Voltage Ready to isolate the BOOST IP untill VDDA will be ready
541 * @rmtoll CR1 AVD_READY LL_PWR_EnableAnalogVoltageReady
542 * @retval None
543 */
544 __STATIC_INLINE void LL_PWR_EnableAnalogVoltageReady(void)
545 {
546 SET_BIT(PWR->CR1, PWR_CR1_AVD_READY);
547 }
548
549 /**
550 * @brief Disable the Analog Voltage Ready (VDDA)
551 * @rmtoll CR1 AVD_READY LL_PWR_DisableAnalogVoltageReady
552 * @retval None
553 */
554 __STATIC_INLINE void LL_PWR_DisableAnalogVoltageReady(void)
555 {
556 CLEAR_BIT(PWR->CR1, PWR_CR1_AVD_READY);
557 }
558
559 /**
560 * @brief Check if the Analog Voltage Booster (VDDA) is enabled
561 * @rmtoll CR1 AVD_READY LL_PWR_IsEnabledAnalogVoltageReady
562 * @retval State of bit (1 or 0).
563 */
564 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogVoltageReady(void)
565 {
566 return ((READ_BIT(PWR->CR1, PWR_CR1_AVD_READY) == (PWR_CR1_AVD_READY)) ? 1UL : 0UL);
567 }
568 #endif /* PWR_CR1_AVD_READY */
569
570 /**
571 * @brief Set the internal Regulator output voltage in STOP mode
572 * @rmtoll CR1 SVOS LL_PWR_SetStopModeRegulVoltageScaling
573 * @param VoltageScaling This parameter can be one of the following values:
574 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3
575 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4
576 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5
577 * @retval None
578 */
579 __STATIC_INLINE void LL_PWR_SetStopModeRegulVoltageScaling(uint32_t VoltageScaling)
580 {
581 MODIFY_REG(PWR->CR1, PWR_CR1_SVOS, VoltageScaling);
582 }
583
584 /**
585 * @brief Get the internal Regulator output voltage in STOP mode
586 * @rmtoll CR1 SVOS LL_PWR_GetStopModeRegulVoltageScaling
587 * @retval Returned value can be one of the following values:
588 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3
589 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4
590 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5
591 */
592 __STATIC_INLINE uint32_t LL_PWR_GetStopModeRegulVoltageScaling(void)
593 {
594 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_SVOS));
595 }
596
597 /**
598 * @brief Enable Analog Power Voltage Detector
599 * @rmtoll CR1 AVDEN LL_PWR_EnableAVD
600 * @retval None
601 */
602 __STATIC_INLINE void LL_PWR_EnableAVD(void)
603 {
604 SET_BIT(PWR->CR1, PWR_CR1_AVDEN);
605 }
606
607 /**
608 * @brief Disable Analog Power Voltage Detector
609 * @rmtoll CR1 AVDEN LL_PWR_DisableAVD
610 * @retval None
611 */
612 __STATIC_INLINE void LL_PWR_DisableAVD(void)
613 {
614 CLEAR_BIT(PWR->CR1, PWR_CR1_AVDEN);
615 }
616
617 /**
618 * @brief Check if Analog Power Voltage Detector is enabled
619 * @rmtoll CR1 AVDEN LL_PWR_IsEnabledAVD
620 * @retval State of bit (1 or 0).
621 */
622 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAVD(void)
623 {
624 return ((READ_BIT(PWR->CR1, PWR_CR1_AVDEN) == (PWR_CR1_AVDEN)) ? 1UL : 0UL);
625 }
626
627 /**
628 * @brief Configure the voltage threshold to be detected by the Analog Power Voltage Detector
629 * @rmtoll CR1 ALS LL_PWR_SetAVDLevel
630 * @param AVDLevel This parameter can be one of the following values:
631 * @arg @ref LL_PWR_AVDLEVEL_0
632 * @arg @ref LL_PWR_AVDLEVEL_1
633 * @arg @ref LL_PWR_AVDLEVEL_2
634 * @arg @ref LL_PWR_AVDLEVEL_3
635 * @retval None
636 */
637 __STATIC_INLINE void LL_PWR_SetAVDLevel(uint32_t AVDLevel)
638 {
639 MODIFY_REG(PWR->CR1, PWR_CR1_ALS, AVDLevel);
640 }
641
642 /**
643 * @brief Get the Analog Voltage threshold to be detected by the Analog Power Voltage Detector
644 * @rmtoll CR1 ALS LL_PWR_GetAVDLevel
645 * @retval Returned value can be one of the following values:
646 * @arg @ref LL_PWR_AVDLEVEL_0
647 * @arg @ref LL_PWR_AVDLEVEL_1
648 * @arg @ref LL_PWR_AVDLEVEL_2
649 * @arg @ref LL_PWR_AVDLEVEL_3
650 */
651 __STATIC_INLINE uint32_t LL_PWR_GetAVDLevel(void)
652 {
653 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_ALS));
654 }
655
656 #if defined (PWR_CR1_AXIRAM1SO)
657 /**
658 * @brief Enable the AXI RAM1 shut-off in DStop/DStop2 mode
659 * @rmtoll CR1 AXIRAM1SO LL_PWR_EnableAXIRAM1ShutOff
660 * @retval None
661 */
662 __STATIC_INLINE void LL_PWR_EnableAXIRAM1ShutOff(void)
663 {
664 SET_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO);
665 }
666
667 /**
668 * @brief Disable the AXI RAM1 shut-off in DStop/DStop2 mode
669 * @rmtoll CR1 AXIRAM1SO LL_PWR_DisableAXIRAM1ShutOff
670 * @retval None
671 */
672 __STATIC_INLINE void LL_PWR_DisableAXIRAM1ShutOff(void)
673 {
674 CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO);
675 }
676
677 /**
678 * @brief Check if the AXI RAM1 shut-off in DStop/DStop2 mode is enabled
679 * @rmtoll CR1 AXIRAM1SO LL_PWR_IsEnabledAXIRAM1ShutOff
680 * @retval State of bit (1 or 0).
681 */
682 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM1ShutOff(void)
683 {
684 return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO) == (PWR_CR1_AXIRAM1SO)) ? 1UL : 0UL);
685 }
686 #endif /* PWR_CR1_AXIRAM1SO */
687
688 #if defined (PWR_CR1_AXIRAM2SO)
689 /**
690 * @brief Enable the AXI RAM2 shut-off in DStop/DStop2 mode
691 * @rmtoll CR1 AXIRAM2SO LL_PWR_EnableAXIRAM2ShutOff
692 * @retval None
693 */
694 __STATIC_INLINE void LL_PWR_EnableAXIRAM2ShutOff(void)
695 {
696 SET_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO);
697 }
698
699 /**
700 * @brief Disable the AXI RAM2 shut-off in DStop/DStop2 mode
701 * @rmtoll CR1 AXIRAM2SO LL_PWR_DisableAXIRAM2ShutOff
702 * @retval None
703 */
704 __STATIC_INLINE void LL_PWR_DisableAXIRAM2ShutOff(void)
705 {
706 CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO);
707 }
708
709 /**
710 * @brief Check if the AXI RAM2 shut-off in DStop/DStop2 mode is enabled
711 * @rmtoll CR1 AXIRAM2SO LL_PWR_IsEnabledAXIRAM2ShutOff
712 * @retval State of bit (1 or 0).
713 */
714 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM2ShutOff(void)
715 {
716 return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO) == (PWR_CR1_AXIRAM2SO)) ? 1UL : 0UL);
717 }
718 #endif /* PWR_CR1_AXIRAM2SO */
719
720 #if defined (PWR_CR1_AXIRAM3SO)
721 /**
722 * @brief Enable the AXI RAM3 shut-off in DStop/DStop2 mode
723 * @rmtoll CR1 AXIRAM3SO LL_PWR_EnableAXIRAM3ShutOff
724 * @retval None
725 */
726 __STATIC_INLINE void LL_PWR_EnableAXIRAM3ShutOff(void)
727 {
728 SET_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO);
729 }
730
731 /**
732 * @brief Disable the AXI RAM3 shut-off in DStop/DStop2 mode
733 * @rmtoll CR1 AXIRAM3SO LL_PWR_DisableAXIRAM3ShutOff
734 * @retval None
735 */
736 __STATIC_INLINE void LL_PWR_DisableAXIRAM3ShutOff(void)
737 {
738 CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO);
739 }
740
741 /**
742 * @brief Check if the AXI RAM3 shut-off in DStop/DStop2 mode is enabled
743 * @rmtoll CR1 AXIRAM3SO LL_PWR_IsEnabledAXIRAM3ShutOff
744 * @retval State of bit (1 or 0).
745 */
746 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM3ShutOff(void)
747 {
748 return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO) == (PWR_CR1_AXIRAM3SO)) ? 1UL : 0UL);
749 }
750 #endif /* PWR_CR1_AXIRAM3SO */
751
752 #if defined (PWR_CR1_AHBRAM1SO)
753 /**
754 * @brief Enable the AHB RAM1 shut-off in DStop/DStop2 mode
755 * @rmtoll CR1 AHBRAM1SO LL_PWR_EnableAHBRAM1ShutOff
756 * @retval None
757 */
758 __STATIC_INLINE void LL_PWR_EnableAHBRAM1ShutOff(void)
759 {
760 SET_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO);
761 }
762
763 /**
764 * @brief Disable the AHB RAM1 shut-off in DStop/DStop2 mode
765 * @rmtoll CR1 AHBRAM1SO LL_PWR_DisableAHBRAM1ShutOff
766 * @retval None
767 */
768 __STATIC_INLINE void LL_PWR_DisableAHBRAM1ShutOff(void)
769 {
770 CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO);
771 }
772
773 /**
774 * @brief Check if the AHB RAM1 shut-off in DStop/DStop2 mode is enabled
775 * @rmtoll CR1 AHBRAM1SO LL_PWR_IsEnabledAHBRAM1ShutOff
776 * @retval State of bit (1 or 0).
777 */
778 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM1ShutOff(void)
779 {
780 return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO) == (PWR_CR1_AHBRAM1SO)) ? 1UL : 0UL);
781 }
782 #endif /* PWR_CR1_AHBRAM1SO */
783
784 #if defined (PWR_CR1_AHBRAM2SO)
785 /**
786 * @brief Enable the AHB RAM2 shut-off in DStop/DStop2 mode
787 * @rmtoll CR1 AHBRAM2SO LL_PWR_EnableAHBRAM2ShutOff
788 * @retval None
789 */
790 __STATIC_INLINE void LL_PWR_EnableAHBRAM2ShutOff(void)
791 {
792 SET_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO);
793 }
794
795 /**
796 * @brief Disable the AHB RAM2 shut-off in DStop/DStop2 mode
797 * @rmtoll CR1 AHBRAM2SO LL_PWR_DisableAHBRAM2ShutOff
798 * @retval None
799 */
800 __STATIC_INLINE void LL_PWR_DisableAHBRAM2ShutOff(void)
801 {
802 CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO);
803 }
804
805 /**
806 * @brief Check if the AHB RAM2 shut-off in DStop/DStop2 mode is enabled
807 * @rmtoll CR1 AHBRAM2SO LL_PWR_IsEnabledAHBRAM2ShutOff
808 * @retval State of bit (1 or 0).
809 */
810 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2ShutOff(void)
811 {
812 return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO) == (PWR_CR1_AHBRAM2SO)) ? 1UL : 0UL);
813 }
814 #endif /* PWR_CR1_AHBRAM2SO */
815
816 #if defined (PWR_CR1_ITCMSO)
817 /**
818 * @brief Enable the ITCM shut-off in DStop/DStop2 mode
819 * @rmtoll CR1 ITCMSO LL_PWR_EnableITCMSOShutOff
820 * @retval None
821 */
822 __STATIC_INLINE void LL_PWR_EnableITCMSOShutOff(void)
823 {
824 SET_BIT(PWR->CR1, PWR_CR1_ITCMSO);
825 }
826
827 /**
828 * @brief Disable the ITCM shut-off in DStop/DStop2 mode
829 * @rmtoll CR1 ITCMSO LL_PWR_DisableITCMSOShutOff
830 * @retval None
831 */
832 __STATIC_INLINE void LL_PWR_DisableITCMSOShutOff(void)
833 {
834 CLEAR_BIT(PWR->CR1, PWR_CR1_ITCMSO);
835 }
836
837 /**
838 * @brief Check if the ITCM shut-off in DStop/DStop2 mode is enabled
839 * @rmtoll CR1 ITCMSO LL_PWR_IsEnabledITCMShutOff
840 * @retval State of bit (1 or 0).
841 */
842 __STATIC_INLINE uint32_t LL_PWR_IsEnabledITCMShutOff(void)
843 {
844 return ((READ_BIT(PWR->CR1, PWR_CR1_ITCMSO) == (PWR_CR1_ITCMSO)) ? 1UL : 0UL);
845 }
846 #endif /* PWR_CR1_ITCMSO */
847
848 #if defined (PWR_CR1_HSITFSO)
849 /**
850 * @brief Enable the USB and FDCAN shut-off in DStop/DStop2 mode
851 * @rmtoll CR1 HSITFSO LL_PWR_EnableHSITFShutOff
852 * @retval None
853 */
854 __STATIC_INLINE void LL_PWR_EnableHSITFShutOff(void)
855 {
856 SET_BIT(PWR->CR1, PWR_CR1_HSITFSO);
857 }
858
859 /**
860 * @brief Disable the USB and FDCAN shut-off in DStop/DStop2 mode
861 * @rmtoll CR1 HSITFSO LL_PWR_DisableHSITFShutOff
862 * @retval None
863 */
864 __STATIC_INLINE void LL_PWR_DisableHSITFShutOff(void)
865 {
866 CLEAR_BIT(PWR->CR1, PWR_CR1_HSITFSO);
867 }
868
869 /**
870 * @brief Check if the USB and FDCAN shut-off in DStop/DStop2 mode is enabled
871 * @rmtoll CR1 HSITFSO LL_PWR_IsEnabledHSITFShutOff
872 * @retval State of bit (1 or 0).
873 */
874 __STATIC_INLINE uint32_t LL_PWR_IsEnabledHSITFShutOff(void)
875 {
876 return ((READ_BIT(PWR->CR1, PWR_CR1_HSITFSO) == (PWR_CR1_HSITFSO)) ? 1UL : 0UL);
877 }
878 #endif /* PWR_CR1_HSITFSO */
879
880 #if defined (PWR_CR1_SRDRAMSO)
881 /**
882 * @brief Enable the SRD AHB RAM shut-off in DStop/DStop2 mode
883 * @rmtoll CR1 SRDRAMSO LL_PWR_EnableSRDRAMShutOff
884 * @retval None
885 */
886 __STATIC_INLINE void LL_PWR_EnableSRDRAMShutOff(void)
887 {
888 SET_BIT(PWR->CR1, PWR_CR1_SRDRAMSO);
889 }
890
891 /**
892 * @brief Disable the SRD AHB RAM shut-off in DStop/DStop2 mode
893 * @rmtoll CR1 SRDRAMSO LL_PWR_DisableSRDRAMShutOff
894 * @retval None
895 */
896 __STATIC_INLINE void LL_PWR_DisableSRDRAMShutOff(void)
897 {
898 CLEAR_BIT(PWR->CR1, PWR_CR1_SRDRAMSO);
899 }
900
901 /**
902 * @brief Check if the SRD AHB RAM shut-off in DStop/DStop2 mode is enabled
903 * @rmtoll CR1 SRDRAMSO LL_PWR_IsEnabledSRDRAMShutOff
904 * @retval State of bit (1 or 0).
905 */
906 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRDRAMShutOff(void)
907 {
908 return ((READ_BIT(PWR->CR1, PWR_CR1_SRDRAMSO) == (PWR_CR1_SRDRAMSO)) ? 1UL : 0UL);
909 }
910 #endif /* PWR_CR1_SRDRAMSO */
911
912 /**
913 * @brief Enable Backup Regulator
914 * @rmtoll CR2 BREN LL_PWR_EnableBkUpRegulator
915 * @note When set, the Backup Regulator (used to maintain backup SRAM content in Standby and
916 * VBAT modes) is enabled. If BRE is reset, the backup Regulator is switched off. The backup
917 * SRAM can still be used but its content will be lost in the Standby and VBAT modes. Once set,
918 * the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that
919 * the data written into the RAM will be maintained in the Standby and VBAT modes.
920 * @retval None
921 */
922 __STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
923 {
924 SET_BIT(PWR->CR2, PWR_CR2_BREN);
925 }
926
927 /**
928 * @brief Disable Backup Regulator
929 * @rmtoll CR2 BREN LL_PWR_DisableBkUpRegulator
930 * @retval None
931 */
932 __STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
933 {
934 CLEAR_BIT(PWR->CR2, PWR_CR2_BREN);
935 }
936
937 /**
938 * @brief Check if the backup Regulator is enabled
939 * @rmtoll CR2 BREN LL_PWR_IsEnabledBkUpRegulator
940 * @retval State of bit (1 or 0).
941 */
942 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
943 {
944 return ((READ_BIT(PWR->CR2, PWR_CR2_BREN) == (PWR_CR2_BREN)) ? 1UL : 0UL);
945 }
946
947 /**
948 * @brief Enable VBAT and Temperature monitoring
949 * @rmtoll CR2 MONEN LL_PWR_EnableMonitoring
950 * @retval None
951 */
952 __STATIC_INLINE void LL_PWR_EnableMonitoring(void)
953 {
954 SET_BIT(PWR->CR2, PWR_CR2_MONEN);
955 }
956
957 /**
958 * @brief Disable VBAT and Temperature monitoring
959 * @rmtoll CR2 MONEN LL_PWR_DisableMonitoring
960 * @retval None
961 */
962 __STATIC_INLINE void LL_PWR_DisableMonitoring(void)
963 {
964 CLEAR_BIT(PWR->CR2, PWR_CR2_MONEN);
965 }
966
967 /**
968 * @brief Check if the VBAT and Temperature monitoring is enabled
969 * @rmtoll CR2 MONEN LL_PWR_IsEnabledMonitoring
970 * @retval State of bit (1 or 0).
971 */
972 __STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void)
973 {
974 return ((READ_BIT(PWR->CR2, PWR_CR2_MONEN) == (PWR_CR2_MONEN)) ? 1UL : 0UL);
975 }
976
977 #if defined (SMPS)
978 /**
979 * @brief Configure the PWR supply
980 * @rmtoll CR3 BYPASS LL_PWR_ConfigSupply
981 * @rmtoll CR3 LDOEN LL_PWR_ConfigSupply
982 * @rmtoll CR3 SMPSEN LL_PWR_ConfigSupply
983 * @rmtoll CR3 SMPSEXTHP LL_PWR_ConfigSupply
984 * @rmtoll CR3 SMPSLEVEL LL_PWR_ConfigSupply
985 * @param SupplySource This parameter can be one of the following values:
986 * @arg @ref LL_PWR_LDO_SUPPLY
987 * @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY
988 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO
989 * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_LDO
990 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
991 * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO
992 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT
993 * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT
994 * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
995 * @retval None
996 */
997 __STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource)
998 {
999 /* Set the power supply configuration */
1000 MODIFY_REG(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), SupplySource);
1001 }
1002 #else
1003 /**
1004 * @brief Configure the PWR supply
1005 * @rmtoll CR3 BYPASS LL_PWR_ConfigSupply
1006 * @rmtoll CR3 LDOEN LL_PWR_ConfigSupply
1007 * @rmtoll CR3 SCUEN LL_PWR_ConfigSupply
1008 * @param SupplySource This parameter can be one of the following values:
1009 * @arg @ref LL_PWR_LDO_SUPPLY
1010 * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
1011 * @retval None
1012 */
1013 __STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource)
1014 {
1015 /* Set the power supply configuration */
1016 MODIFY_REG(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), SupplySource);
1017 }
1018 #endif /* defined (SMPS) */
1019
1020 #if defined (SMPS)
1021 /**
1022 * @brief Get the PWR supply
1023 * @rmtoll CR3 BYPASS LL_PWR_GetSupply
1024 * @rmtoll CR3 LDOEN LL_PWR_GetSupply
1025 * @rmtoll CR3 SMPSEN LL_PWR_GetSupply
1026 * @rmtoll CR3 SMPSEXTHP LL_PWR_GetSupply
1027 * @rmtoll CR3 SMPSLEVEL LL_PWR_GetSupply
1028 * @retval Returned value can be one of the following values:
1029 * @arg @ref LL_PWR_LDO_SUPPLY
1030 * @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY
1031 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO
1032 * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_LDO
1033 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
1034 * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO
1035 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT
1036 * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT
1037 * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
1038 */
1039 __STATIC_INLINE uint32_t LL_PWR_GetSupply(void)
1040 {
1041 /* Get the power supply configuration */
1042 return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)));
1043 }
1044 #else
1045 /**
1046 * @brief Get the PWR supply
1047 * @rmtoll CR3 BYPASS LL_PWR_GetSupply
1048 * @rmtoll CR3 LDOEN LL_PWR_GetSupply
1049 * @rmtoll CR3 SCUEN LL_PWR_GetSupply
1050 * @retval Returned value can be one of the following values:
1051 * @arg @ref LL_PWR_LDO_SUPPLY
1052 * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
1053 */
1054 __STATIC_INLINE uint32_t LL_PWR_GetSupply(void)
1055 {
1056 /* Get the power supply configuration */
1057 return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)));
1058 }
1059 #endif /* defined (SMPS) */
1060
1061 /**
1062 * @brief Enable battery charging
1063 * @rmtoll CR3 VBE LL_PWR_EnableBatteryCharging
1064 * @retval None
1065 */
1066 __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
1067 {
1068 SET_BIT(PWR->CR3, PWR_CR3_VBE);
1069 }
1070
1071 /**
1072 * @brief Disable battery charging
1073 * @rmtoll CR3 VBE LL_PWR_DisableBatteryCharging
1074 * @retval None
1075 */
1076 __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
1077 {
1078 CLEAR_BIT(PWR->CR3, PWR_CR3_VBE);
1079 }
1080
1081 /**
1082 * @brief Check if battery charging is enabled
1083 * @rmtoll CR3 VBE LL_PWR_IsEnabledBatteryCharging
1084 * @retval State of bit (1 or 0).
1085 */
1086 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
1087 {
1088 return ((READ_BIT(PWR->CR3, PWR_CR3_VBE) == (PWR_CR3_VBE)) ? 1UL : 0UL);
1089 }
1090
1091 /**
1092 * @brief Set the Battery charge resistor impedance
1093 * @rmtoll CR3 VBRS LL_PWR_SetBattChargResistor
1094 * @param Resistor This parameter can be one of the following values:
1095 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
1096 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
1097 * @retval None
1098 */
1099 __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
1100 {
1101 MODIFY_REG(PWR->CR3, PWR_CR3_VBRS, Resistor);
1102 }
1103
1104 /**
1105 * @brief Get the Battery charge resistor impedance
1106 * @rmtoll CR3 VBRS LL_PWR_GetBattChargResistor
1107 * @retval Returned value can be one of the following values:
1108 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
1109 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
1110 */
1111 __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
1112 {
1113 return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_VBRS));
1114 }
1115
1116 /**
1117 * @brief Enable the USB regulator
1118 * @rmtoll CR3 USBREGEN LL_PWR_EnableUSBReg
1119 * @retval None
1120 */
1121 __STATIC_INLINE void LL_PWR_EnableUSBReg(void)
1122 {
1123 SET_BIT(PWR->CR3, PWR_CR3_USBREGEN);
1124 }
1125
1126 /**
1127 * @brief Disable the USB regulator
1128 * @rmtoll CR3 USBREGEN LL_PWR_DisableUSBReg
1129 * @retval None
1130 */
1131 __STATIC_INLINE void LL_PWR_DisableUSBReg(void)
1132 {
1133 CLEAR_BIT(PWR->CR3, PWR_CR3_USBREGEN);
1134 }
1135
1136 /**
1137 * @brief Check if the USB regulator is enabled
1138 * @rmtoll CR3 USBREGEN LL_PWR_IsEnabledUSBReg
1139 * @retval State of bit (1 or 0).
1140 */
1141 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBReg(void)
1142 {
1143 return ((READ_BIT(PWR->CR3, PWR_CR3_USBREGEN) == (PWR_CR3_USBREGEN)) ? 1UL : 0UL);
1144 }
1145
1146 /**
1147 * @brief Enable the USB voltage detector
1148 * @rmtoll CR3 USB33DEN LL_PWR_EnableUSBVoltageDetector
1149 * @retval None
1150 */
1151 __STATIC_INLINE void LL_PWR_EnableUSBVoltageDetector(void)
1152 {
1153 SET_BIT(PWR->CR3, PWR_CR3_USB33DEN);
1154 }
1155
1156 /**
1157 * @brief Disable the USB voltage detector
1158 * @rmtoll CR3 USB33DEN LL_PWR_DisableUSBVoltageDetector
1159 * @retval None
1160 */
1161 __STATIC_INLINE void LL_PWR_DisableUSBVoltageDetector(void)
1162 {
1163 CLEAR_BIT(PWR->CR3, PWR_CR3_USB33DEN);
1164 }
1165
1166 /**
1167 * @brief Check if the USB voltage detector is enabled
1168 * @rmtoll CR3 USB33DEN LL_PWR_IsEnabledUSBVoltageDetector
1169 * @retval State of bit (1 or 0).
1170 */
1171 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBVoltageDetector(void)
1172 {
1173 return ((READ_BIT(PWR->CR3, PWR_CR3_USB33DEN) == (PWR_CR3_USB33DEN)) ? 1UL : 0UL);
1174 }
1175
1176 #if defined (PWR_CPUCR_PDDS_D2)
1177 /**
1178 * @brief Set the D1 domain Power Down mode when the CPU enters deepsleep
1179 * @rmtoll CPUCR PDDS_D1 LL_PWR_CPU_SetD1PowerMode
1180 * @param PDMode This parameter can be one of the following values:
1181 * @arg @ref LL_PWR_CPU_MODE_D1STOP
1182 * @arg @ref LL_PWR_CPU_MODE_D1STANDBY
1183 * @retval None
1184 */
1185 __STATIC_INLINE void LL_PWR_CPU_SetD1PowerMode(uint32_t PDMode)
1186 {
1187 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D1, PDMode);
1188 }
1189 #else
1190 /**
1191 * @brief Set the CPU domain Power Down mode when the CPU enters deepsleep
1192 * @rmtoll CPUCR RETDS_CD LL_PWR_CPU_SetCDPowerMode
1193 * @param PDMode This parameter can be one of the following values:
1194 * @arg @ref LL_PWR_CPU_MODE_CDSTOP
1195 * @arg @ref LL_PWR_CPU_MODE_CDSTOP2
1196 * @retval None
1197 */
1198 __STATIC_INLINE void LL_PWR_CPU_SetCDPowerMode(uint32_t PDMode)
1199 {
1200 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_RETDS_CD, PDMode);
1201 }
1202 #endif /* PWR_CPUCR_PDDS_D2 */
1203
1204 #if defined (DUAL_CORE)
1205 /**
1206 * @brief Set the D1 domain Power Down mode when the CPU2 enters deepsleep
1207 * @rmtoll CPU2CR PDDS_D1 LL_PWR_CPU2_SetD1PowerMode
1208 * @param PDMode This parameter can be one of the following values:
1209 * @arg @ref LL_PWR_CPU2_MODE_D1STOP
1210 * @arg @ref LL_PWR_CPU2_MODE_D1STANDBY
1211 * @retval None
1212 */
1213 __STATIC_INLINE void LL_PWR_CPU2_SetD1PowerMode(uint32_t PDMode)
1214 {
1215 MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1, PDMode);
1216 }
1217 #endif /* DUAL_CORE */
1218
1219 #if defined (PWR_CPUCR_PDDS_D2)
1220 /**
1221 * @brief Get the D1 Domain Power Down mode when the CPU enters deepsleep
1222 * @rmtoll CPUCR PDDS_D1 LL_PWR_CPU_GetD1PowerMode
1223 * @retval Returned value can be one of the following values:
1224 * @arg @ref LL_PWR_CPU_MODE_D1STOP
1225 * @arg @ref LL_PWR_CPU_MODE_D1STANDBY
1226 */
1227 __STATIC_INLINE uint32_t LL_PWR_CPU_GetD1PowerMode(void)
1228 {
1229 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1));
1230 }
1231 #else
1232 /**
1233 * @brief Get the CD Domain Power Down mode when the CPU enters deepsleep
1234 * @rmtoll CPUCR RETDS_CD LL_PWR_CPU_GetCDPowerMode
1235 * @retval Returned value can be one of the following values:
1236 * @arg @ref LL_PWR_CPU_MODE_CDSTOP
1237 * @arg @ref LL_PWR_CPU_MODE_CDSTOP2
1238 */
1239 __STATIC_INLINE uint32_t LL_PWR_CPU_GetCDPowerMode(void)
1240 {
1241 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_RETDS_CD));
1242 }
1243 #endif /* PWR_CPUCR_PDDS_D2 */
1244
1245 #if defined (DUAL_CORE)
1246 /**
1247 * @brief Get the D1 Domain Power Down mode when the CPU2 enters deepsleep
1248 * @rmtoll CPU2CR PDDS_D1 LL_PWR_CPU2_GetD1PowerMode
1249 * @retval Returned value can be one of the following values:
1250 * @arg @ref LL_PWR_CPU2_MODE_D1STOP
1251 * @arg @ref LL_PWR_CPU2_MODE_D1STANDBY
1252 */
1253 __STATIC_INLINE uint32_t LL_PWR_CPU2_GetD1PowerMode(void)
1254 {
1255 return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1));
1256 }
1257 #endif /* DUAL_CORE */
1258
1259 #if defined (PWR_CPUCR_PDDS_D2)
1260 /**
1261 * @brief Set the D2 domain Power Down mode when the CPU enters deepsleep
1262 * @rmtoll CPUCR PDDS_D2 LL_PWR_CPU_SetD2PowerMode
1263 * @param PDMode This parameter can be one of the following values:
1264 * @arg @ref LL_PWR_CPU_MODE_D2STOP
1265 * @arg @ref LL_PWR_CPU_MODE_D2STANDBY
1266 * @retval None
1267 */
1268 __STATIC_INLINE void LL_PWR_CPU_SetD2PowerMode(uint32_t PDMode)
1269 {
1270 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D2, PDMode);
1271 }
1272 #endif /* PWR_CPUCR_PDDS_D2 */
1273
1274 #if defined (DUAL_CORE)
1275 /**
1276 * @brief Set the D2 domain Power Down mode when the CPU2 enters deepsleep
1277 * @rmtoll CPU2CR PDDS_D2 LL_PWR_CPU2_SetD2PowerMode
1278 * @param PDMode This parameter can be one of the following values:
1279 * @arg @ref LL_PWR_CPU2_MODE_D2STOP
1280 * @arg @ref LL_PWR_CPU2_MODE_D2STANDBY
1281 * @retval None
1282 */
1283 __STATIC_INLINE void LL_PWR_CPU2_SetD2PowerMode(uint32_t PDMode)
1284 {
1285 MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2, PDMode);
1286 }
1287 #endif /* DUAL_CORE */
1288
1289 #if defined (PWR_CPUCR_PDDS_D2)
1290 /**
1291 * @brief Get the D2 Domain Power Down mode when the CPU enters deepsleep
1292 * @rmtoll CPUCR PDDS_D2 LL_PWR_CPU_GetD2PowerMode
1293 * @retval Returned value can be one of the following values:
1294 * @arg @ref LL_PWR_CPU_MODE_D2STOP
1295 * @arg @ref LL_PWR_CPU_MODE_D2STANDBY
1296 */
1297 __STATIC_INLINE uint32_t LL_PWR_CPU_GetD2PowerMode(void)
1298 {
1299 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2));
1300 }
1301 #endif /* PWR_CPUCR_PDDS_D2 */
1302
1303 #if defined (DUAL_CORE)
1304 /**
1305 * @brief Get the D2 Domain Power Down mode when the CPU2 enters deepsleep
1306 * @rmtoll CPU2CR PDDS_D2 LL_PWR_CPU2_GetD2PowerMode
1307 * @retval Returned value can be one of the following values:
1308 * @arg @ref LL_PWR_CPU2_MODE_D2STOP
1309 * @arg @ref LL_PWR_CPU2_MODE_D2STANDBY
1310 */
1311 __STATIC_INLINE uint32_t LL_PWR_CPU2_GetD2PowerMode(void)
1312 {
1313 return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2));
1314 }
1315 #endif /* DUAL_CORE */
1316
1317 #if defined (PWR_CPUCR_PDDS_D2)
1318 /**
1319 * @brief Set the D3 domain Power Down mode when the CPU enters deepsleep
1320 * @rmtoll CPUCR PDDS_D3 LL_PWR_CPU_SetD3PowerMode
1321 * @param PDMode This parameter can be one of the following values:
1322 * @arg @ref LL_PWR_CPU_MODE_D3STOP
1323 * @arg @ref LL_PWR_CPU_MODE_D3STANDBY
1324 * @retval None
1325 */
1326 __STATIC_INLINE void LL_PWR_CPU_SetD3PowerMode(uint32_t PDMode)
1327 {
1328 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D3 , PDMode);
1329 }
1330 #else
1331 /**
1332 * @brief Set the SRD domain Power Down mode when the CPU enters deepsleep
1333 * @rmtoll CPUCR PDDS_SRD LL_PWR_CPU_SetSRDPowerMode
1334 * @param PDMode This parameter can be one of the following values:
1335 * @arg @ref LL_PWR_CPU_MODE_SRDSTOP
1336 * @arg @ref LL_PWR_CPU_MODE_SRDSTANDBY
1337 * @retval None
1338 */
1339 __STATIC_INLINE void LL_PWR_CPU_SetSRDPowerMode(uint32_t PDMode)
1340 {
1341 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_SRD , PDMode);
1342 }
1343 #endif /* PWR_CPUCR_PDDS_D2 */
1344
1345 #if defined (DUAL_CORE)
1346 /**
1347 * @brief Set the D3 domain Power Down mode when the CPU2 enters deepsleep
1348 * @rmtoll CPU2CR PDDS_D3 LL_PWR_CPU2_SetD3PowerMode
1349 * @param PDMode This parameter can be one of the following values:
1350 * @arg @ref LL_PWR_CPU2_MODE_D3STOP
1351 * @arg @ref LL_PWR_CPU2_MODE_D3STANDBY
1352 * @retval None
1353 */
1354 __STATIC_INLINE void LL_PWR_CPU2_SetD3PowerMode(uint32_t PDMode)
1355 {
1356 MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3, PDMode);
1357 }
1358 #endif /* DUAL_CORE */
1359
1360 #if defined (PWR_CPUCR_PDDS_D2)
1361 /**
1362 * @brief Get the D3 Domain Power Down mode when the CPU enters deepsleep
1363 * @rmtoll CPUCR PDDS_D3 LL_PWR_CPU_GetD3PowerMode
1364 * @retval Returned value can be one of the following values:
1365 * @arg @ref LL_PWR_CPU_MODE_D3STOP
1366 * @arg @ref LL_PWR_CPU_MODE_D3STANDBY
1367 */
1368 __STATIC_INLINE uint32_t LL_PWR_CPU_GetD3PowerMode(void)
1369 {
1370 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3));
1371 }
1372 #else
1373 /**
1374 * @brief Get the SRD Domain Power Down mode when the CPU enters deepsleep
1375 * @rmtoll CPUCR PDDS_SRD LL_PWR_CPU_GetSRDPowerMode
1376 * @retval Returned value can be one of the following values:
1377 * @arg @ref LL_PWR_CPU_MODE_SRDSTOP
1378 * @arg @ref LL_PWR_CPU_MODE_SRDSTANDBY
1379 */
1380 __STATIC_INLINE uint32_t LL_PWR_CPU_GetSRDPowerMode(void)
1381 {
1382 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_SRD));
1383 }
1384 #endif /* PWR_CPUCR_PDDS_D2 */
1385
1386 #if defined (DUAL_CORE)
1387 /**
1388 * @brief Get the D3 Domain Power Down mode when the CPU2 enters deepsleep
1389 * @rmtoll CPU2CR PDDS_D3 LL_PWR_CPU2_GetD3PowerMode
1390 * @retval Returned value can be one of the following values:
1391 * @arg @ref LL_PWR_CPU2_MODE_D3STOP
1392 * @arg @ref LL_PWR_CPU2_MODE_D3STANDBY
1393 */
1394 __STATIC_INLINE uint32_t LL_PWR_CPU2_GetD3PowerMode(void)
1395 {
1396 return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3));
1397 }
1398 #endif /* DUAL_CORE */
1399
1400 #if defined (DUAL_CORE)
1401 /**
1402 * @brief Hold the CPU1 and allocated peripherals when exiting from STOP mode
1403 * @rmtoll CPU2CR HOLD1 LL_PWR_HoldCPU1
1404 * @retval None
1405 */
1406 __STATIC_INLINE void LL_PWR_HoldCPU1(void)
1407 {
1408 SET_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1);
1409 }
1410
1411 /**
1412 * @brief Release the CPU1 and allocated peripherals
1413 * @rmtoll CPU2CR HOLD1 LL_PWR_ReleaseCPU1
1414 * @retval None
1415 */
1416 __STATIC_INLINE void LL_PWR_ReleaseCPU1(void)
1417 {
1418 CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1);
1419 }
1420
1421 /**
1422 * @brief Ckeck if the CPU1 and allocated peripherals are held
1423 * @rmtoll CPU2CR HOLD1 LL_PWR_IsCPU1Held
1424 * @retval State of bit (1 or 0).
1425 */
1426 __STATIC_INLINE uint32_t LL_PWR_IsCPU1Held(void)
1427 {
1428 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1) == (PWR_CPU2CR_HOLD1)) ? 1UL : 0UL);
1429 }
1430
1431 /**
1432 * @brief Hold the CPU2 and allocated peripherals when exiting from STOP mode
1433 * @rmtoll CPUCR HOLD2 LL_PWR_HoldCPU2
1434 * @retval None
1435 */
1436 __STATIC_INLINE void LL_PWR_HoldCPU2(void)
1437 {
1438 SET_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2);
1439 }
1440
1441 /**
1442 * @brief Release the CPU2 and allocated peripherals
1443 * @rmtoll CPUCR HOLD2 LL_PWR_ReleaseCPU2
1444 * @retval None
1445 */
1446 __STATIC_INLINE void LL_PWR_ReleaseCPU2(void)
1447 {
1448 CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2);
1449 }
1450
1451 /**
1452 * @brief Ckeck if the CPU2 and allocated peripherals are held
1453 * @rmtoll CPUCR HOLD2 LL_PWR_IsCPU2Held
1454 * @retval State of bit (1 or 0).
1455 */
1456 __STATIC_INLINE uint32_t LL_PWR_IsCPU2Held(void)
1457 {
1458 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2) == (PWR_CPUCR_HOLD2)) ? 1UL : 0UL);
1459 }
1460 #endif /* DUAL_CORE */
1461
1462 #if defined (PWR_CPUCR_PDDS_D2)
1463 /**
1464 * @brief D3 domain remains in Run mode regardless of CPU subsystem modes
1465 * @rmtoll CPUCR RUN_D3 LL_PWR_CPU_EnableD3RunInLowPowerMode
1466 * @retval None
1467 */
1468 __STATIC_INLINE void LL_PWR_CPU_EnableD3RunInLowPowerMode(void)
1469 {
1470 SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3);
1471 }
1472 #else
1473 /**
1474 * @brief SRD domain remains in Run mode regardless of CPU subsystem modes
1475 * @rmtoll CPUCR RUN_SRD LL_PWR_CPU_EnableSRDRunInLowPowerMode
1476 * @retval None
1477 */
1478 __STATIC_INLINE void LL_PWR_CPU_EnableSRDRunInLowPowerMode(void)
1479 {
1480 SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD);
1481 }
1482 #endif /* PWR_CPUCR_PDDS_D2 */
1483
1484 #if defined (DUAL_CORE)
1485 /**
1486 * @brief D3 domain remains in Run mode regardless of CPU2 subsystem modes
1487 * @rmtoll CPU2CR RUN_D3 LL_PWR_CPU2_EnableD3RunInLowPowerMode
1488 * @retval None
1489 */
1490 __STATIC_INLINE void LL_PWR_CPU2_EnableD3RunInLowPowerMode(void)
1491 {
1492 SET_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3);
1493 }
1494 #endif /* DUAL_CORE */
1495
1496 #if defined (PWR_CPUCR_PDDS_D2)
1497 /**
1498 * @brief D3 domain follows CPU subsystem modes
1499 * @rmtoll CPUCR RUN_D3 LL_PWR_CPU_DisableD3RunInLowPowerMode
1500 * @retval None
1501 */
1502 __STATIC_INLINE void LL_PWR_CPU_DisableD3RunInLowPowerMode(void)
1503 {
1504 CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3);
1505 }
1506 #else
1507 /**
1508 * @brief SRD domain follows CPU subsystem modes
1509 * @rmtoll CPUCR RUN_SRD LL_PWR_CPU_DisableSRDRunInLowPowerMode
1510 * @retval None
1511 */
1512 __STATIC_INLINE void LL_PWR_CPU_DisableSRDRunInLowPowerMode(void)
1513 {
1514 CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD);
1515 }
1516 #endif /* PWR_CPUCR_PDDS_D2 */
1517
1518 #if defined (DUAL_CORE)
1519 /**
1520 * @brief D3 domain follows CPU2 subsystem modes
1521 * @rmtoll CPU2CR RUN_D3 LL_PWR_CPU2_DisableD3RunInLowPowerMode
1522 * @retval None
1523 */
1524 __STATIC_INLINE void LL_PWR_CPU2_DisableD3RunInLowPowerMode(void)
1525 {
1526 CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3);
1527 }
1528 #endif /* DUAL_CORE */
1529
1530 #if defined (PWR_CPUCR_PDDS_D2)
1531 /**
1532 * @brief Check if D3 is kept in Run mode when CPU enters low power mode
1533 * @rmtoll CPUCR RUN_D3 LL_PWR_CPU_IsEnabledD3RunInLowPowerMode
1534 * @retval State of bit (1 or 0).
1535 */
1536 __STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledD3RunInLowPowerMode(void)
1537 {
1538 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3) == (PWR_CPUCR_RUN_D3)) ? 1UL : 0UL);
1539 }
1540 #else
1541 /**
1542 * @brief Check if SRD is kept in Run mode when CPU enters low power mode
1543 * @rmtoll CPUCR RUN_SRD LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode
1544 * @retval State of bit (1 or 0).
1545 */
1546 __STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode(void)
1547 {
1548 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD) == (PWR_CPUCR_RUN_SRD)) ? 1UL : 0UL);
1549 }
1550 #endif /* PWR_CPUCR_PDDS_D2 */
1551
1552 #if defined (DUAL_CORE)
1553 /**
1554 * @brief Check if D3 is kept in Run mode when CPU2 enters low power mode
1555 * @rmtoll CPU2CR RUN_D3 LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode
1556 * @retval State of bit (1 or 0).
1557 */
1558 __STATIC_INLINE uint32_t LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode(void)
1559 {
1560 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3) == (PWR_CPU2CR_RUN_D3)) ? 1UL : 0UL);
1561 }
1562 #endif /* DUAL_CORE */
1563
1564 /**
1565 * @brief Set the main internal Regulator output voltage
1566 * @rmtoll D3CR VOS LL_PWR_SetRegulVoltageScaling
1567 * @param VoltageScaling This parameter can be one of the following values:
1568 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0
1569 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
1570 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
1571 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
1572 * @note For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, VOS0
1573 * is applied when PWR_D3CR_VOS[1:0] = 0b11 and SYSCFG_PWRCR_ODEN = 0b1.
1574 * @retval None
1575 */
1576 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
1577 {
1578 #if defined (PWR_CPUCR_PDDS_D2)
1579 MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling);
1580 #else
1581 MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, VoltageScaling);
1582 #endif /* PWR_CPUCR_PDDS_D2 */
1583 }
1584
1585 /**
1586 * @brief Get the main internal Regulator output voltage
1587 * @rmtoll D3CR VOS LL_PWR_GetRegulVoltageScaling
1588 * @note For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, checking
1589 * VOS0 need the check of PWR_D3CR_VOS[1:0] field and SYSCFG_PWRCR_ODEN bit.
1590 * @retval Returned value can be one of the following values:
1591 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0
1592 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
1593 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
1594 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
1595 */
1596 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
1597 {
1598 #if defined (PWR_CPUCR_PDDS_D2)
1599 return (uint32_t)(READ_BIT(PWR->D3CR, PWR_D3CR_VOS));
1600 #else
1601 return (uint32_t)(READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS));
1602 #endif /* PWR_CPUCR_PDDS_D2 */
1603 }
1604
1605 /**
1606 * @brief Enable the WakeUp PINx functionality
1607 * @rmtoll WKUPEPR WKUPEN1 LL_PWR_EnableWakeUpPin\n
1608 * WKUPEPR WKUPEN2 LL_PWR_EnableWakeUpPin\n
1609 * WKUPEPR WKUPEN3 LL_PWR_EnableWakeUpPin\n
1610 * WKUPEPR WKUPEN4 LL_PWR_EnableWakeUpPin\n
1611 * WKUPEPR WKUPEN5 LL_PWR_EnableWakeUpPin\n
1612 * WKUPEPR WKUPEN6 LL_PWR_EnableWakeUpPin
1613 * @param WakeUpPin This parameter can be one of the following values:
1614 * @arg @ref LL_PWR_WAKEUP_PIN1
1615 * @arg @ref LL_PWR_WAKEUP_PIN2
1616 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
1617 * @arg @ref LL_PWR_WAKEUP_PIN4
1618 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
1619 * @arg @ref LL_PWR_WAKEUP_PIN6
1620 *
1621 * (*) value not defined in all devices.
1622 *
1623 * @retval None
1624 */
1625 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
1626 {
1627 SET_BIT(PWR->WKUPEPR, WakeUpPin);
1628 }
1629
1630 /**
1631 * @brief Disable the WakeUp PINx functionality
1632 * @rmtoll WKUPEPR WKUPEN1 LL_PWR_DisableWakeUpPin\n
1633 * WKUPEPR WKUPEN2 LL_PWR_DisableWakeUpPin\n
1634 * WKUPEPR WKUPEN3 LL_PWR_DisableWakeUpPin\n
1635 * WKUPEPR WKUPEN4 LL_PWR_DisableWakeUpPin\n
1636 * WKUPEPR WKUPEN5 LL_PWR_DisableWakeUpPin\n
1637 * WKUPEPR WKUPEN6 LL_PWR_DisableWakeUpPin
1638 * @param WakeUpPin This parameter can be one of the following values:
1639 * @arg @ref LL_PWR_WAKEUP_PIN1
1640 * @arg @ref LL_PWR_WAKEUP_PIN2
1641 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
1642 * @arg @ref LL_PWR_WAKEUP_PIN4
1643 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
1644 * @arg @ref LL_PWR_WAKEUP_PIN6
1645 *
1646 * (*) value not defined in all devices.
1647 *
1648 * @retval None
1649 */
1650 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
1651 {
1652 CLEAR_BIT(PWR->WKUPEPR, WakeUpPin);
1653 }
1654
1655 /**
1656 * @brief Check if the WakeUp PINx functionality is enabled
1657 * @rmtoll WKUPEPR WKUPEN1 LL_PWR_IsEnabledWakeUpPin\n
1658 * WKUPEPR WKUPEN2 LL_PWR_IsEnabledWakeUpPin\n
1659 * WKUPEPR WKUPEN3 LL_PWR_IsEnabledWakeUpPin\n
1660 * WKUPEPR WKUPEN4 LL_PWR_IsEnabledWakeUpPin\n
1661 * WKUPEPR WKUPEN5 LL_PWR_IsEnabledWakeUpPin\n
1662 * WKUPEPR WKUPEN6 LL_PWR_IsEnabledWakeUpPin
1663 * @param WakeUpPin This parameter can be one of the following values:
1664 * @arg @ref LL_PWR_WAKEUP_PIN1
1665 * @arg @ref LL_PWR_WAKEUP_PIN2
1666 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
1667 * @arg @ref LL_PWR_WAKEUP_PIN4
1668 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
1669 * @arg @ref LL_PWR_WAKEUP_PIN6
1670 *
1671 * (*) value not defined in all devices.
1672 *
1673 * @retval State of bit (1 or 0).
1674 */
1675 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
1676 {
1677 return ((READ_BIT(PWR->WKUPEPR, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
1678 }
1679
1680 /**
1681 * @brief Set the Wake-Up pin polarity low for the event detection
1682 * @rmtoll WKUPEPR WKUPP1 LL_PWR_SetWakeUpPinPolarityLow\n
1683 * WKUPEPR WKUPP2 LL_PWR_SetWakeUpPinPolarityLow\n
1684 * WKUPEPR WKUPP3 LL_PWR_SetWakeUpPinPolarityLow\n
1685 * WKUPEPR WKUPP4 LL_PWR_SetWakeUpPinPolarityLow\n
1686 * WKUPEPR WKUPP5 LL_PWR_SetWakeUpPinPolarityLow\n
1687 * WKUPEPR WKUPP6 LL_PWR_SetWakeUpPinPolarityLow
1688 * @param WakeUpPin This parameter can be one of the following values:
1689 * @arg @ref LL_PWR_WAKEUP_PIN1
1690 * @arg @ref LL_PWR_WAKEUP_PIN2
1691 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
1692 * @arg @ref LL_PWR_WAKEUP_PIN4
1693 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
1694 * @arg @ref LL_PWR_WAKEUP_PIN6
1695 *
1696 * (*) value not defined in all devices.
1697 *
1698 * @retval None
1699 */
1700 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
1701 {
1702 SET_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos));
1703 }
1704
1705 /**
1706 * @brief Set the Wake-Up pin polarity high for the event detection
1707 * @rmtoll WKUPEPR WKUPP1 LL_PWR_SetWakeUpPinPolarityHigh\n
1708 * WKUPEPR WKUPP2 LL_PWR_SetWakeUpPinPolarityHigh\n
1709 * WKUPEPR WKUPP3 LL_PWR_SetWakeUpPinPolarityHigh\n
1710 * WKUPEPR WKUPP4 LL_PWR_SetWakeUpPinPolarityHigh\n
1711 * WKUPEPR WKUPP5 LL_PWR_SetWakeUpPinPolarityHigh\n
1712 * WKUPEPR WKUPP6 LL_PWR_SetWakeUpPinPolarityHigh
1713 * @param WakeUpPin This parameter can be one of the following values:
1714 * @arg @ref LL_PWR_WAKEUP_PIN1
1715 * @arg @ref LL_PWR_WAKEUP_PIN2
1716 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
1717 * @arg @ref LL_PWR_WAKEUP_PIN4
1718 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
1719 * @arg @ref LL_PWR_WAKEUP_PIN6
1720 *
1721 * (*) value not defined in all devices.
1722 *
1723 * @retval None
1724 */
1725 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
1726 {
1727 CLEAR_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos));
1728 }
1729
1730 /**
1731 * @brief Get the Wake-Up pin polarity for the event detection
1732 * @rmtoll WKUPEPR WKUPP1 LL_PWR_IsWakeUpPinPolarityLow\n
1733 * WKUPEPR WKUPP2 LL_PWR_IsWakeUpPinPolarityLow\n
1734 * WKUPEPR WKUPP3 LL_PWR_IsWakeUpPinPolarityLow\n
1735 * WKUPEPR WKUPP4 LL_PWR_IsWakeUpPinPolarityLow\n
1736 * WKUPEPR WKUPP5 LL_PWR_IsWakeUpPinPolarityLow\n
1737 * WKUPEPR WKUPP6 LL_PWR_IsWakeUpPinPolarityLow
1738 * @param WakeUpPin This parameter can be one of the following values:
1739 * @arg @ref LL_PWR_WAKEUP_PIN1
1740 * @arg @ref LL_PWR_WAKEUP_PIN2
1741 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
1742 * @arg @ref LL_PWR_WAKEUP_PIN4
1743 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
1744 * @arg @ref LL_PWR_WAKEUP_PIN6
1745 *
1746 * (*) value not defined in all devices.
1747 *
1748 * @retval State of bit (1 or 0).
1749 */
1750 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
1751 {
1752 return ((READ_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) == (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) ? 1UL : 0UL);
1753 }
1754
1755 /**
1756 * @brief Set the Wake-Up pin Pull None
1757 * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullNone\n
1758 * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullNone\n
1759 * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullNone\n
1760 * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullNone\n
1761 * WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullNone\n
1762 * WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullNone
1763 * @param WakeUpPin This parameter can be one of the following values:
1764 * @arg @ref LL_PWR_WAKEUP_PIN1
1765 * @arg @ref LL_PWR_WAKEUP_PIN2
1766 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
1767 * @arg @ref LL_PWR_WAKEUP_PIN4
1768 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
1769 * @arg @ref LL_PWR_WAKEUP_PIN6
1770 *
1771 * (*) value not defined in all devices.
1772 *
1773 * @retval None
1774 */
1775 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin)
1776 {
1777 MODIFY_REG(PWR->WKUPEPR, \
1778 (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
1779 (LL_PWR_WAKEUP_PIN_NOPULL << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
1780 }
1781
1782 /**
1783 * @brief Set the Wake-Up pin Pull Up
1784 * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullUp\n
1785 * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullUp\n
1786 * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullUp\n
1787 * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullUp\n
1788 * WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullUp\n
1789 * WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullUp
1790 * @param WakeUpPin This parameter can be one of the following values:
1791 * @arg @ref LL_PWR_WAKEUP_PIN1
1792 * @arg @ref LL_PWR_WAKEUP_PIN2
1793 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
1794 * @arg @ref LL_PWR_WAKEUP_PIN4
1795 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
1796 * @arg @ref LL_PWR_WAKEUP_PIN6
1797 *
1798 * (*) value not defined in all devices.
1799 *
1800 * @retval None
1801 */
1802 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin)
1803 {
1804 MODIFY_REG(PWR->WKUPEPR, \
1805 (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
1806 (LL_PWR_WAKEUP_PIN_PULLUP << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
1807 }
1808
1809 /**
1810 * @brief Set the Wake-Up pin Pull Down
1811 * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullDown\n
1812 * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullDown\n
1813 * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullDown\n
1814 * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullDown\n
1815 * WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullDown\n
1816 * WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullDown
1817 * @param WakeUpPin This parameter can be one of the following values:
1818 * @arg @ref LL_PWR_WAKEUP_PIN1
1819 * @arg @ref LL_PWR_WAKEUP_PIN2
1820 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
1821 * @arg @ref LL_PWR_WAKEUP_PIN4
1822 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
1823 * @arg @ref LL_PWR_WAKEUP_PIN6
1824 *
1825 * (*) value not defined in all devices.
1826 *
1827 * @retval None
1828 */
1829 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin)
1830 {
1831 MODIFY_REG(PWR->WKUPEPR, \
1832 (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
1833 (LL_PWR_WAKEUP_PIN_PULLDOWN << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
1834 }
1835
1836 /**
1837 * @brief Get the Wake-Up pin pull
1838 * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_GetWakeUpPinPull\n
1839 * WKUPEPR WKUPPUPD2 LL_PWR_GetWakeUpPinPull\n
1840 * WKUPEPR WKUPPUPD3 LL_PWR_GetWakeUpPinPull\n
1841 * WKUPEPR WKUPPUPD4 LL_PWR_GetWakeUpPinPull\n
1842 * WKUPEPR WKUPPUPD5 LL_PWR_GetWakeUpPinPull\n
1843 * WKUPEPR WKUPPUPD6 LL_PWR_GetWakeUpPinPull
1844 * @param WakeUpPin This parameter can be one of the following values:
1845 * @arg @ref LL_PWR_WAKEUP_PIN1
1846 * @arg @ref LL_PWR_WAKEUP_PIN2
1847 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
1848 * @arg @ref LL_PWR_WAKEUP_PIN4
1849 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
1850 * @arg @ref LL_PWR_WAKEUP_PIN6
1851 *
1852 * (*) value not defined in all devices.
1853 *
1854 * @retval Returned value can be one of the following values:
1855 * @arg @ref LL_PWR_WAKEUP_PIN_NOPULL
1856 * @arg @ref LL_PWR_WAKEUP_PIN_PULLUP
1857 * @arg @ref LL_PWR_WAKEUP_PIN_PULLDOWN
1858 */
1859 __STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin)
1860 {
1861 uint32_t regValue = READ_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
1862
1863 return (uint32_t)(regValue >> ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK));
1864 }
1865
1866 /**
1867 * @}
1868 */
1869
1870 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
1871 * @{
1872 */
1873
1874 /**
1875 * @brief Indicate whether VDD voltage is below the selected PVD threshold
1876 * @rmtoll CSR1 PVDO LL_PWR_IsActiveFlag_PVDO
1877 * @retval State of bit (1 or 0).
1878 */
1879 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
1880 {
1881 return ((READ_BIT(PWR->CSR1, PWR_CSR1_PVDO) == (PWR_CSR1_PVDO)) ? 1UL : 0UL);
1882 }
1883
1884 /**
1885 * @brief Indicate whether the voltage level is ready for current actual used VOS
1886 * @rmtoll CSR1 ACTVOSRDY LL_PWR_IsActiveFlag_ACTVOS
1887 * @retval State of bit (1 or 0).
1888 */
1889 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS(void)
1890 {
1891 return ((READ_BIT(PWR->CSR1, PWR_CSR1_ACTVOSRDY) == (PWR_CSR1_ACTVOSRDY)) ? 1UL : 0UL);
1892 }
1893
1894 /**
1895 * @brief Indicate whether VDDA voltage is below the selected AVD threshold
1896 * @rmtoll CSR1 AVDO LL_PWR_IsActiveFlag_AVDO
1897 * @retval State of bit (1 or 0).
1898 */
1899 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_AVDO(void)
1900 {
1901 return ((READ_BIT(PWR->CSR1, PWR_CSR1_AVDO) == (PWR_CSR1_AVDO)) ? 1UL : 0UL);
1902 }
1903
1904 #if defined (PWR_CSR1_MMCVDO)
1905 /**
1906 * @brief Indicate whether VDDMMC voltage is below 1V2
1907 * @rmtoll CSR1 MMCVDO LL_PWR_IsActiveFlag_MMCVDO
1908 * @retval State of bit (1 or 0).
1909 */
1910 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_MMCVDO(void)
1911 {
1912 return ((READ_BIT(PWR->CSR1, PWR_CSR1_MMCVDO) == (PWR_CSR1_MMCVDO)) ? 1UL : 0UL);
1913 }
1914 #endif /* PWR_CSR1_MMCVDO */
1915
1916 /**
1917 * @brief Get Backup Regulator ready Flag
1918 * @rmtoll CR2 BRRDY LL_PWR_IsActiveFlag_BRR
1919 * @retval State of bit (1 or 0).
1920 */
1921 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
1922 {
1923 return ((READ_BIT(PWR->CR2, PWR_CR2_BRRDY) == (PWR_CR2_BRRDY)) ? 1UL : 0UL);
1924 }
1925
1926 /**
1927 * @brief Indicate whether the VBAT level is above or below low threshold
1928 * @rmtoll CR2 VBATL LL_PWR_IsActiveFlag_VBATL
1929 * @retval State of bit (1 or 0).
1930 */
1931 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATL(void)
1932 {
1933 return ((READ_BIT(PWR->CR2, PWR_CR2_VBATL) == (PWR_CR2_VBATL)) ? 1UL : 0UL);
1934 }
1935
1936 /**
1937 * @brief Indicate whether the VBAT level is above or below high threshold
1938 * @rmtoll CR2 VBATH LL_PWR_IsActiveFlag_VBATH
1939 * @retval State of bit (1 or 0).
1940 */
1941 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void)
1942 {
1943 return ((READ_BIT(PWR->CR2, PWR_CR2_VBATH) == (PWR_CR2_VBATH)) ? 1UL : 0UL);
1944 }
1945
1946 /**
1947 * @brief Indicate whether the CPU temperature level is above or below low threshold
1948 * @rmtoll CR2 TEMPL LL_PWR_IsActiveFlag_TEMPL
1949 * @retval State of bit (1 or 0).
1950 */
1951 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void)
1952 {
1953 return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPL) == (PWR_CR2_TEMPL)) ? 1UL : 0UL);
1954 }
1955
1956 /**
1957 * @brief Indicate whether the CPU temperature level is above or below high threshold
1958 * @rmtoll CR2 TEMPH LL_PWR_IsActiveFlag_TEMPH
1959 * @retval State of bit (1 or 0).
1960 */
1961 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void)
1962 {
1963 return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPH) == (PWR_CR2_TEMPH)) ? 1UL : 0UL);
1964 }
1965
1966 #if defined (SMPS)
1967 /**
1968 * @brief Indicate whether the SMPS external supply is ready or not
1969 * @rmtoll CR3 SMPSEXTRDY LL_PWR_IsActiveFlag_SMPSEXT
1970 * @retval State of bit (1 or 0).
1971 */
1972 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SMPSEXT(void)
1973 {
1974 return ((READ_BIT(PWR->CR3, PWR_CR3_SMPSEXTRDY) == (PWR_CR3_SMPSEXTRDY)) ? 1UL : 0UL);
1975 }
1976 #endif /* SMPS */
1977
1978 /**
1979 * @brief Indicate whether the USB supply is ready or not
1980 * @rmtoll CR3 USBRDY LL_PWR_IsActiveFlag_USB
1981 * @retval State of bit (1 or 0).
1982 */
1983 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_USB(void)
1984 {
1985 return ((READ_BIT(PWR->CR3, PWR_CR3_USB33RDY) == (PWR_CR3_USB33RDY)) ? 1UL : 0UL);
1986 }
1987
1988 #if defined (DUAL_CORE)
1989 /**
1990 * @brief Get HOLD2 Flag
1991 * @rmtoll CPUCR HOLD2F LL_PWR_IsActiveFlag_HOLD2
1992 * @retval State of bit (1 or 0).
1993 */
1994 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_HOLD2(void)
1995 {
1996 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2F) == (PWR_CPUCR_HOLD2F)) ? 1UL : 0UL);
1997 }
1998
1999 /**
2000 * @brief Get HOLD1 Flag
2001 * @rmtoll CPU2CR HOLD1F LL_PWR_IsActiveFlag_HOLD1
2002 * @retval State of bit (1 or 0).
2003 */
2004 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_HOLD1(void)
2005 {
2006 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1F) == (PWR_CPU2CR_HOLD1F)) ? 1UL : 0UL);
2007 }
2008 #endif /* DUAL_CORE */
2009
2010 /**
2011 * @brief Get CPU System Stop Flag
2012 * @rmtoll CPUCR STOPF LL_PWR_CPU_IsActiveFlag_STOP
2013 * @retval State of bit (1 or 0).
2014 */
2015 __STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_STOP(void)
2016 {
2017 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_STOPF) == (PWR_CPUCR_STOPF)) ? 1UL : 0UL);
2018 }
2019
2020 #if defined (DUAL_CORE)
2021 /**
2022 * @brief Get CPU2 System Stop Flag
2023 * @rmtoll CPU2CR STOPF LL_PWR_CPU2_IsActiveFlag_STOP
2024 * @retval State of bit (1 or 0).
2025 */
2026 __STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_STOP(void)
2027 {
2028 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_STOPF) == (PWR_CPU2CR_STOPF)) ? 1UL : 0UL);
2029 }
2030 #endif /* DUAL_CORE */
2031
2032 /**
2033 * @brief Get CPU System Standby Flag
2034 * @rmtoll CPUCR SBF LL_PWR_CPU_IsActiveFlag_SB
2035 * @retval State of bit (1 or 0).
2036 */
2037 __STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB(void)
2038 {
2039 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF) == (PWR_CPUCR_SBF)) ? 1UL : 0UL);
2040 }
2041
2042 #if defined (DUAL_CORE)
2043 /**
2044 * @brief Get CPU2 System Standby Flag
2045 * @rmtoll CPU2CR SBF LL_PWR_CPU2_IsActiveFlag_SB
2046 * @retval State of bit (1 or 0).
2047 */
2048 __STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB(void)
2049 {
2050 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF) == (PWR_CPU2CR_SBF)) ? 1UL : 0UL);
2051 }
2052 #endif /* DUAL_CORE */
2053
2054 #if defined (PWR_CPUCR_SBF_D1)
2055 /**
2056 * @brief Get CPU D1 Domain Standby Flag
2057 * @rmtoll CPUCR SBF_D1 LL_PWR_CPU_IsActiveFlag_SB_D1
2058 * @retval State of bit (1 or 0).
2059 */
2060 __STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D1(void)
2061 {
2062 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D1) == (PWR_CPUCR_SBF_D1)) ? 1UL : 0UL);
2063 }
2064 #endif /* PWR_CPUCR_SBF_D1 */
2065
2066 #if defined (DUAL_CORE)
2067 /**
2068 * @brief Get CPU2 D1 Domain Standby Flag
2069 * @rmtoll CPU2CR SBF_D1 LL_PWR_CPU2_IsActiveFlag_SB_D1
2070 * @retval State of bit (1 or 0).
2071 */
2072 __STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB_D1(void)
2073 {
2074 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D1) == (PWR_CPU2CR_SBF_D1)) ? 1UL : 0UL);
2075 }
2076 #endif /* DUAL_CORE */
2077
2078 #if defined (PWR_CPUCR_SBF_D2)
2079 /**
2080 * @brief Get CPU D2 Domain Standby Flag
2081 * @rmtoll CPUCR SBF_D2 LL_PWR_CPU_IsActiveFlag_SB_D2
2082 * @retval State of bit (1 or 0).
2083 */
2084 __STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D2(void)
2085 {
2086 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D2) == (PWR_CPUCR_SBF_D2)) ? 1UL : 0UL);
2087 }
2088 #endif /* PWR_CPUCR_SBF_D2 */
2089
2090 #if defined (DUAL_CORE)
2091 /**
2092 * @brief Get CPU2 D2 Domain Standby Flag
2093 * @rmtoll CPU2CR SBF_D2 LL_PWR_CPU2_IsActiveFlag_SB_D2
2094 * @retval State of bit (1 or 0).
2095 */
2096 __STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB_D2(void)
2097 {
2098 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D2) == (PWR_CPU2CR_SBF_D2)) ? 1UL : 0UL);
2099 }
2100 #endif /* DUAL_CORE */
2101
2102
2103 /**
2104 * @brief Indicate whether the Regulator is ready in the selected voltage range
2105 * or if its output voltage is still changing to the required voltage level
2106 * @rmtoll D3CR VOSRDY LL_PWR_IsActiveFlag_VOS
2107 * @retval State of bit (1 or 0).
2108 */
2109 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
2110 {
2111 #if defined (PWR_CPUCR_PDDS_D2)
2112 return ((READ_BIT(PWR->D3CR, PWR_D3CR_VOSRDY) == (PWR_D3CR_VOSRDY)) ? 1UL : 0UL);
2113 #else
2114 return ((READ_BIT(PWR->SRDCR, PWR_SRDCR_VOSRDY) == (PWR_SRDCR_VOSRDY)) ? 1UL : 0UL);
2115 #endif /* PWR_CPUCR_PDDS_D2 */
2116 }
2117
2118 /**
2119 * @brief Get Wake-up Flag 6
2120 * @rmtoll WKUPFR WKUPF6 LL_PWR_IsActiveFlag_WU6
2121 * @retval State of bit (1 or 0).
2122 */
2123 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
2124 {
2125 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF6) == (PWR_WKUPFR_WKUPF6)) ? 1UL : 0UL);
2126 }
2127
2128 #if defined (PWR_WKUPFR_WKUPF5)
2129 /**
2130 * @brief Get Wake-up Flag 5
2131 * @rmtoll WKUPFR WKUPF5 LL_PWR_IsActiveFlag_WU5
2132 * @retval State of bit (1 or 0).
2133 */
2134 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
2135 {
2136 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF5) == (PWR_WKUPFR_WKUPF5)) ? 1UL : 0UL);
2137 }
2138 #endif /* defined (PWR_WKUPFR_WKUPF5) */
2139
2140 /**
2141 * @brief Get Wake-up Flag 4
2142 * @rmtoll WKUPFR WKUPF4 LL_PWR_IsActiveFlag_WU4
2143 * @retval State of bit (1 or 0).
2144 */
2145 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
2146 {
2147 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF4) == (PWR_WKUPFR_WKUPF4)) ? 1UL : 0UL);
2148 }
2149
2150 #if defined (PWR_WKUPFR_WKUPF3)
2151 /**
2152 * @brief Get Wake-up Flag 3
2153 * @rmtoll WKUPFR WKUPF3 LL_PWR_IsActiveFlag_WU3
2154 * @retval State of bit (1 or 0).
2155 */
2156 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
2157 {
2158 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF3) == (PWR_WKUPFR_WKUPF3)) ? 1UL : 0UL);
2159 }
2160 #endif /* defined (PWR_WKUPFR_WKUPF3) */
2161
2162 /**
2163 * @brief Get Wake-up Flag 2
2164 * @rmtoll WKUPFR WKUPF2 LL_PWR_IsActiveFlag_WU2
2165 * @retval State of bit (1 or 0).
2166 */
2167 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
2168 {
2169 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF2) == (PWR_WKUPFR_WKUPF2)) ? 1UL : 0UL);
2170 }
2171
2172 /**
2173 * @brief Get Wake-up Flag 1
2174 * @rmtoll WKUPFR WKUPF1 LL_PWR_IsActiveFlag_WU1
2175 * @retval State of bit (1 or 0).
2176 */
2177 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
2178 {
2179 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) == (PWR_WKUPFR_WKUPF1)) ? 1UL : 0UL);
2180 }
2181
2182 /**
2183 * @brief Clear CPU STANDBY, STOP and HOLD flags
2184 * @rmtoll CPUCR CSSF LL_PWR_ClearFlag_CPU
2185 * @retval None
2186 */
2187 __STATIC_INLINE void LL_PWR_ClearFlag_CPU(void)
2188 {
2189 SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF);
2190 }
2191
2192 #if defined (DUAL_CORE)
2193 /**
2194 * @brief Clear CPU2 STANDBY, STOP and HOLD flags
2195 * @rmtoll CPU2CR CSSF LL_PWR_ClearFlag_CPU2
2196 * @retval None
2197 */
2198 __STATIC_INLINE void LL_PWR_ClearFlag_CPU2(void)
2199 {
2200 SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF);
2201 }
2202 #endif /* DUAL_CORE */
2203
2204 /**
2205 * @brief Clear Wake-up Flag 6
2206 * @rmtoll WKUPCR WKUPC6 LL_PWR_ClearFlag_WU6
2207 * @retval None
2208 */
2209 __STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)
2210 {
2211 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC6);
2212 }
2213
2214 #if defined (PWR_WKUPCR_WKUPC5)
2215 /**
2216 * @brief Clear Wake-up Flag 5
2217 * @rmtoll WKUPCR WKUPC5 LL_PWR_ClearFlag_WU5
2218 * @retval None
2219 */
2220 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
2221 {
2222 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC5);
2223 }
2224 #endif /* defined (PWR_WKUPCR_WKUPC5) */
2225
2226 /**
2227 * @brief Clear Wake-up Flag 4
2228 * @rmtoll WKUPCR WKUPC4 LL_PWR_ClearFlag_WU4
2229 * @retval None
2230 */
2231 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
2232 {
2233 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC4);
2234 }
2235
2236 #if defined (PWR_WKUPCR_WKUPC3)
2237 /**
2238 * @brief Clear Wake-up Flag 3
2239 * @rmtoll WKUPCR WKUPC3 LL_PWR_ClearFlag_WU3
2240 * @retval None
2241 */
2242 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
2243 {
2244 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC3);
2245 }
2246 #endif /* defined (PWR_WKUPCR_WKUPC3) */
2247
2248 /**
2249 * @brief Clear Wake-up Flag 2
2250 * @rmtoll WKUPCR WKUPC2 LL_PWR_ClearFlag_WU2
2251 * @retval None
2252 */
2253 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
2254 {
2255 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC2);
2256 }
2257
2258 /**
2259 * @brief Clear Wake-up Flag 1
2260 * @rmtoll WKUPCR WKUPC1 LL_PWR_ClearFlag_WU1
2261 * @retval None
2262 */
2263 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
2264 {
2265 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC1);
2266 }
2267
2268 #if defined (USE_FULL_LL_DRIVER)
2269 /** @defgroup PWR_LL_EF_Init De-initialization function
2270 * @{
2271 */
2272 ErrorStatus LL_PWR_DeInit(void);
2273 /**
2274 * @}
2275 */
2276 #endif /* defined (USE_FULL_LL_DRIVER) */
2277
2278
2279 /**
2280 * @}
2281 */
2282
2283 /**
2284 * @}
2285 */
2286
2287 /**
2288 * @}
2289 */
2290
2291 #endif /* defined (PWR) */
2292
2293 /**
2294 * @}
2295 */
2296
2297 #ifdef __cplusplus
2298 }
2299 #endif
2300
2301 #endif /* STM32H7xx_LL_PWR_H */
2302
2303 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/