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Merge pull request #11270 from haslinghuis/rename_attr
[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_ll_rcc.h
blobed63ebf55b5ae1b4f8d30ea07a7170676fb5f864
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_rcc.h
4 * @author MCD Application Team
5 * @version $VERSION$
6 * @date $DATE$
7 * @brief Header file of RCC LL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
12 * All rights reserved.</center></h2>
13 *
14 * This software component is licensed by ST under BSD 3-Clause license,
15 * the "License"; You may not use this file except in compliance with the
16 * License. You may obtain a copy of the License at:
17 * opensource.org/licenses/BSD-3-Clause
18 *
19 ******************************************************************************
20 */
21
22 /* Define to prevent recursive inclusion -------------------------------------*/
23 #ifndef STM32H7xx_LL_RCC_H
24 #define STM32H7xx_LL_RCC_H
25
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29
30 /* Includes ------------------------------------------------------------------*/
31 #include "stm32h7xx.h"
32 #include <math.h>
33
34 /** @addtogroup STM32H7xx_LL_Driver
35 * @{
36 */
37
38 #if defined(RCC)
39
40 /** @defgroup RCC_LL RCC
41 * @{
42 */
43
44 /* Private types -------------------------------------------------------------*/
45 /* Private variables ---------------------------------------------------------*/
46 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
47 * @{
48 */
49 extern const uint8_t LL_RCC_PrescTable[16];
50
51 /**
52 * @}
53 */
54 /* Private constants ---------------------------------------------------------*/
55 /* Private macros ------------------------------------------------------------*/
56 #if !defined(UNUSED)
57 #define UNUSED(x) ((void)(x))
58 #endif
59
60 /* 32 24 16 8 0
61 --------------------------------------------------------
62 | Mask | ClkSource | Bit | Register |
63 | | Config | Position | Offset |
64 --------------------------------------------------------*/
65
66 #if defined(RCC_VER_2_0)
67 /* Clock source register offset Vs CDCCIPR regsiter */
68 #define CDCCIP 0x0UL
69 #define CDCCIP1 0x4UL
70 #define CDCCIP2 0x8UL
71 #define SRDCCIP 0xCUL
72 #else
73 /* Clock source register offset Vs D1CCIPR regsiter */
74 #define D1CCIP 0x0UL
75 #define D2CCIP1 0x4UL
76 #define D2CCIP2 0x8UL
77 #define D3CCIP 0xCUL
78 #endif /* RCC_VER_2_0 */
79
80 #define LL_RCC_REG_SHIFT 0U
81 #define LL_RCC_POS_SHIFT 8U
82 #define LL_RCC_CONFIG_SHIFT 16U
83 #define LL_RCC_MASK_SHIFT 24U
84
85 #define LL_CLKSOURCE_SHIFT(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_POS_SHIFT ) & 0x1FUL)
86
87 #define LL_CLKSOURCE_MASK(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_MASK_SHIFT ) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
88
89 #define LL_CLKSOURCE_CONFIG(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_CONFIG_SHIFT) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
90
91 #define LL_CLKSOURCE_REG(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_REG_SHIFT ) & 0xFFUL)
92
93 #define LL_CLKSOURCE(__REG__, __MSK__, __POS__, __CLK__) ((uint32_t)((((__MSK__) >> (__POS__)) << LL_RCC_MASK_SHIFT) | \
94 (( __POS__ ) << LL_RCC_POS_SHIFT) | \
95 (( __REG__ ) << LL_RCC_REG_SHIFT) | \
96 (((__CLK__) >> (__POS__)) << LL_RCC_CONFIG_SHIFT)))
97
98 #if defined(USE_FULL_LL_DRIVER)
99 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
100 * @{
101 */
102 /**
103 * @}
104 */
105 #endif /*USE_FULL_LL_DRIVER*/
106 /* Exported types ------------------------------------------------------------*/
107 #if defined(USE_FULL_LL_DRIVER)
108 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
109 * @{
110 */
111
112 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
113 * @{
114 */
115
116 /**
117 * @brief RCC Clocks Frequency Structure
118 */
119 typedef struct
120 {
121 uint32_t SYSCLK_Frequency;
122 uint32_t CPUCLK_Frequency;
123 uint32_t HCLK_Frequency;
124 uint32_t PCLK1_Frequency;
125 uint32_t PCLK2_Frequency;
126 uint32_t PCLK3_Frequency;
127 uint32_t PCLK4_Frequency;
128 } LL_RCC_ClocksTypeDef;
129
130 /**
131 * @}
132 */
133
134 /**
135 * @brief PLL Clocks Frequency Structure
136 */
137 typedef struct
138 {
139 uint32_t PLL_P_Frequency;
140 uint32_t PLL_Q_Frequency;
141 uint32_t PLL_R_Frequency;
142 } LL_PLL_ClocksTypeDef;
143
144 /**
145 * @}
146 */
147
148 #endif /* USE_FULL_LL_DRIVER */
149
150 /* Exported constants --------------------------------------------------------*/
151 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
152 * @{
153 */
154
155 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
156 * @brief Defines used to adapt values of different oscillators
157 * @note These values could be modified in the user environment according to
158 * HW set-up.
159 * @{
160 */
161 #if !defined (HSE_VALUE)
162 #if defined(RCC_VER_X) || defined(RCC_VER_3_0)
163 #define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */
164 #else
165 #define HSE_VALUE 24000000U /*!< Value of the HSE oscillator in Hz */
166 #endif /* RCC_VER_X || RCC_VER_3_0 */
167 #endif /* HSE_VALUE */
168
169 #if !defined (HSI_VALUE)
170 #define HSI_VALUE 64000000U /*!< Value of the HSI oscillator in Hz */
171 #endif /* HSI_VALUE */
172
173 #if !defined (CSI_VALUE)
174 #define CSI_VALUE 4000000U /*!< Value of the CSI oscillator in Hz */
175 #endif /* CSI_VALUE */
176
177 #if !defined (LSE_VALUE)
178 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
179 #endif /* LSE_VALUE */
180
181 #if !defined (LSI_VALUE)
182 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
183 #endif /* LSI_VALUE */
184
185 #if !defined (EXTERNAL_CLOCK_VALUE)
186 #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
187 #endif /* EXTERNAL_CLOCK_VALUE */
188
189 #if !defined (HSI48_VALUE)
190 #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */
191 #endif /* HSI48_VALUE */
192
193 /**
194 * @}
195 */
196
197 /** @defgroup RCC_LL_EC_HSIDIV HSI oscillator divider
198 * @{
199 */
200 #define LL_RCC_HSI_DIV1 RCC_CR_HSIDIV_1
201 #define LL_RCC_HSI_DIV2 RCC_CR_HSIDIV_2
202 #define LL_RCC_HSI_DIV4 RCC_CR_HSIDIV_4
203 #define LL_RCC_HSI_DIV8 RCC_CR_HSIDIV_8
204 /**
205 * @}
206 */
207
208 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
209 * @{
210 */
211 #define LL_RCC_LSEDRIVE_LOW (uint32_t)(0x00000000U)
212 #define LL_RCC_LSEDRIVE_MEDIUMLOW (uint32_t)(RCC_BDCR_LSEDRV_0)
213 #define LL_RCC_LSEDRIVE_MEDIUMHIGH (uint32_t)(RCC_BDCR_LSEDRV_1)
214 #define LL_RCC_LSEDRIVE_HIGH (uint32_t)(RCC_BDCR_LSEDRV)
215 /**
216 * @}
217 */
218
219 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
220 * @{
221 */
222 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI
223 #define LL_RCC_SYS_CLKSOURCE_CSI RCC_CFGR_SW_CSI
224 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE
225 #define LL_RCC_SYS_CLKSOURCE_PLL1 RCC_CFGR_SW_PLL1
226 /**
227 * @}
228 */
229
230 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
231 * @{
232 */
233 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
234 #define LL_RCC_SYS_CLKSOURCE_STATUS_CSI RCC_CFGR_SWS_CSI /*!< CSI used as system clock */
235 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
236 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 RCC_CFGR_SWS_PLL1 /*!< PLL1 used as system clock */
237 /**
238 * @}
239 */
240
241 /** @defgroup RCC_LL_EC_SYSWAKEUP_CLKSOURCE System wakeup clock source
242 * @{
243 */
244 #define LL_RCC_SYSWAKEUP_CLKSOURCE_HSI (uint32_t)(0x00000000U)
245 #define LL_RCC_SYSWAKEUP_CLKSOURCE_CSI (uint32_t)(RCC_CFGR_STOPWUCK)
246 /**
247 * @}
248 */
249
250 /** @defgroup RCC_LL_EC_KERWAKEUP_CLKSOURCE Kernel wakeup clock source
251 * @{
252 */
253 #define LL_RCC_KERWAKEUP_CLKSOURCE_HSI (uint32_t)(0x00000000U)
254 #define LL_RCC_KERWAKEUP_CLKSOURCE_CSI (uint32_t)(RCC_CFGR_STOPKERWUCK)
255 /**
256 * @}
257 */
258
259 /** @defgroup RCC_LL_EC_SYSCLK_DIV System prescaler
260 * @{
261 */
262 #if defined(RCC_D1CFGR_D1CPRE_DIV1)
263 #define LL_RCC_SYSCLK_DIV_1 RCC_D1CFGR_D1CPRE_DIV1
264 #define LL_RCC_SYSCLK_DIV_2 RCC_D1CFGR_D1CPRE_DIV2
265 #define LL_RCC_SYSCLK_DIV_4 RCC_D1CFGR_D1CPRE_DIV4
266 #define LL_RCC_SYSCLK_DIV_8 RCC_D1CFGR_D1CPRE_DIV8
267 #define LL_RCC_SYSCLK_DIV_16 RCC_D1CFGR_D1CPRE_DIV16
268 #define LL_RCC_SYSCLK_DIV_64 RCC_D1CFGR_D1CPRE_DIV64
269 #define LL_RCC_SYSCLK_DIV_128 RCC_D1CFGR_D1CPRE_DIV128
270 #define LL_RCC_SYSCLK_DIV_256 RCC_D1CFGR_D1CPRE_DIV256
271 #define LL_RCC_SYSCLK_DIV_512 RCC_D1CFGR_D1CPRE_DIV512
272 #else
273 #define LL_RCC_SYSCLK_DIV_1 RCC_CDCFGR1_CDCPRE_DIV1
274 #define LL_RCC_SYSCLK_DIV_2 RCC_CDCFGR1_CDCPRE_DIV2
275 #define LL_RCC_SYSCLK_DIV_4 RCC_CDCFGR1_CDCPRE_DIV4
276 #define LL_RCC_SYSCLK_DIV_8 RCC_CDCFGR1_CDCPRE_DIV8
277 #define LL_RCC_SYSCLK_DIV_16 RCC_CDCFGR1_CDCPRE_DIV16
278 #define LL_RCC_SYSCLK_DIV_64 RCC_CDCFGR1_CDCPRE_DIV64
279 #define LL_RCC_SYSCLK_DIV_128 RCC_CDCFGR1_CDCPRE_DIV128
280 #define LL_RCC_SYSCLK_DIV_256 RCC_CDCFGR1_CDCPRE_DIV256
281 #define LL_RCC_SYSCLK_DIV_512 RCC_CDCFGR1_CDCPRE_DIV512
282 #endif /* RCC_D1CFGR_D1CPRE_DIV1 */
283 /**
284 * @}
285 */
286
287 /** @defgroup RCC_LL_EC_AHB_DIV AHB prescaler
288 * @{
289 */
290 #if defined(RCC_D1CFGR_HPRE_DIV1)
291 #define LL_RCC_AHB_DIV_1 RCC_D1CFGR_HPRE_DIV1
292 #define LL_RCC_AHB_DIV_2 RCC_D1CFGR_HPRE_DIV2
293 #define LL_RCC_AHB_DIV_4 RCC_D1CFGR_HPRE_DIV4
294 #define LL_RCC_AHB_DIV_8 RCC_D1CFGR_HPRE_DIV8
295 #define LL_RCC_AHB_DIV_16 RCC_D1CFGR_HPRE_DIV16
296 #define LL_RCC_AHB_DIV_64 RCC_D1CFGR_HPRE_DIV64
297 #define LL_RCC_AHB_DIV_128 RCC_D1CFGR_HPRE_DIV128
298 #define LL_RCC_AHB_DIV_256 RCC_D1CFGR_HPRE_DIV256
299 #define LL_RCC_AHB_DIV_512 RCC_D1CFGR_HPRE_DIV512
300 #else
301 #define LL_RCC_AHB_DIV_1 RCC_CDCFGR1_HPRE_DIV1
302 #define LL_RCC_AHB_DIV_2 RCC_CDCFGR1_HPRE_DIV2
303 #define LL_RCC_AHB_DIV_4 RCC_CDCFGR1_HPRE_DIV4
304 #define LL_RCC_AHB_DIV_8 RCC_CDCFGR1_HPRE_DIV8
305 #define LL_RCC_AHB_DIV_16 RCC_CDCFGR1_HPRE_DIV16
306 #define LL_RCC_AHB_DIV_64 RCC_CDCFGR1_HPRE_DIV64
307 #define LL_RCC_AHB_DIV_128 RCC_CDCFGR1_HPRE_DIV128
308 #define LL_RCC_AHB_DIV_256 RCC_CDCFGR1_HPRE_DIV256
309 #define LL_RCC_AHB_DIV_512 RCC_CDCFGR1_HPRE_DIV512
310 #endif /* RCC_D1CFGR_HPRE_DIV1 */
311 /**
312 * @}
313 */
314
315 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
316 * @{
317 */
318 #if defined(RCC_D2CFGR_D2PPRE1_DIV1)
319 #define LL_RCC_APB1_DIV_1 RCC_D2CFGR_D2PPRE1_DIV1
320 #define LL_RCC_APB1_DIV_2 RCC_D2CFGR_D2PPRE1_DIV2
321 #define LL_RCC_APB1_DIV_4 RCC_D2CFGR_D2PPRE1_DIV4
322 #define LL_RCC_APB1_DIV_8 RCC_D2CFGR_D2PPRE1_DIV8
323 #define LL_RCC_APB1_DIV_16 RCC_D2CFGR_D2PPRE1_DIV16
324 #else
325 #define LL_RCC_APB1_DIV_1 RCC_CDCFGR2_CDPPRE1_DIV1
326 #define LL_RCC_APB1_DIV_2 RCC_CDCFGR2_CDPPRE1_DIV2
327 #define LL_RCC_APB1_DIV_4 RCC_CDCFGR2_CDPPRE1_DIV4
328 #define LL_RCC_APB1_DIV_8 RCC_CDCFGR2_CDPPRE1_DIV8
329 #define LL_RCC_APB1_DIV_16 RCC_CDCFGR2_CDPPRE1_DIV16
330 #endif /* RCC_D2CFGR_D2PPRE1_DIV1 */
331 /**
332 * @}
333 */
334
335 /** @defgroup RCC_LL_EC_APB2_DIV APB low-speed prescaler (APB2)
336 * @{
337 */
338 #if defined(RCC_D2CFGR_D2PPRE2_DIV1)
339 #define LL_RCC_APB2_DIV_1 RCC_D2CFGR_D2PPRE2_DIV1
340 #define LL_RCC_APB2_DIV_2 RCC_D2CFGR_D2PPRE2_DIV2
341 #define LL_RCC_APB2_DIV_4 RCC_D2CFGR_D2PPRE2_DIV4
342 #define LL_RCC_APB2_DIV_8 RCC_D2CFGR_D2PPRE2_DIV8
343 #define LL_RCC_APB2_DIV_16 RCC_D2CFGR_D2PPRE2_DIV16
344 #else
345 #define LL_RCC_APB2_DIV_1 RCC_CDCFGR2_CDPPRE2_DIV1
346 #define LL_RCC_APB2_DIV_2 RCC_CDCFGR2_CDPPRE2_DIV2
347 #define LL_RCC_APB2_DIV_4 RCC_CDCFGR2_CDPPRE2_DIV4
348 #define LL_RCC_APB2_DIV_8 RCC_CDCFGR2_CDPPRE2_DIV8
349 #define LL_RCC_APB2_DIV_16 RCC_CDCFGR2_CDPPRE2_DIV16
350 #endif /* RCC_D2CFGR_D2PPRE2_DIV1 */
351 /**
352 * @}
353 */
354
355 /** @defgroup RCC_LL_EC_APB3_DIV APB low-speed prescaler (APB3)
356 * @{
357 */
358 #if defined(RCC_D1CFGR_D1PPRE_DIV1)
359 #define LL_RCC_APB3_DIV_1 RCC_D1CFGR_D1PPRE_DIV1
360 #define LL_RCC_APB3_DIV_2 RCC_D1CFGR_D1PPRE_DIV2
361 #define LL_RCC_APB3_DIV_4 RCC_D1CFGR_D1PPRE_DIV4
362 #define LL_RCC_APB3_DIV_8 RCC_D1CFGR_D1PPRE_DIV8
363 #define LL_RCC_APB3_DIV_16 RCC_D1CFGR_D1PPRE_DIV16
364 #else
365 #define LL_RCC_APB3_DIV_1 RCC_CDCFGR1_CDPPRE_DIV1
366 #define LL_RCC_APB3_DIV_2 RCC_CDCFGR1_CDPPRE_DIV2
367 #define LL_RCC_APB3_DIV_4 RCC_CDCFGR1_CDPPRE_DIV4
368 #define LL_RCC_APB3_DIV_8 RCC_CDCFGR1_CDPPRE_DIV8
369 #define LL_RCC_APB3_DIV_16 RCC_CDCFGR1_CDPPRE_DIV16
370 #endif /* RCC_D1CFGR_D1PPRE_DIV1 */
371 /**
372 * @}
373 */
374
375 /** @defgroup RCC_LL_EC_APB4_DIV APB low-speed prescaler (APB4)
376 * @{
377 */
378 #if defined(RCC_D3CFGR_D3PPRE_DIV1)
379 #define LL_RCC_APB4_DIV_1 RCC_D3CFGR_D3PPRE_DIV1
380 #define LL_RCC_APB4_DIV_2 RCC_D3CFGR_D3PPRE_DIV2
381 #define LL_RCC_APB4_DIV_4 RCC_D3CFGR_D3PPRE_DIV4
382 #define LL_RCC_APB4_DIV_8 RCC_D3CFGR_D3PPRE_DIV8
383 #define LL_RCC_APB4_DIV_16 RCC_D3CFGR_D3PPRE_DIV16
384 #else
385 #define LL_RCC_APB4_DIV_1 RCC_SRDCFGR_SRDPPRE_DIV1
386 #define LL_RCC_APB4_DIV_2 RCC_SRDCFGR_SRDPPRE_DIV2
387 #define LL_RCC_APB4_DIV_4 RCC_SRDCFGR_SRDPPRE_DIV4
388 #define LL_RCC_APB4_DIV_8 RCC_SRDCFGR_SRDPPRE_DIV8
389 #define LL_RCC_APB4_DIV_16 RCC_SRDCFGR_SRDPPRE_DIV16
390 #endif /* RCC_D3CFGR_D3PPRE_DIV1 */
391 /**
392 * @}
393 */
394
395 /** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection
396 * @{
397 */
398 #define LL_RCC_MCO1SOURCE_HSI (uint32_t)((RCC_CFGR_MCO1>>16U) | 0x00000000U)
399 #define LL_RCC_MCO1SOURCE_LSE (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_0)
400 #define LL_RCC_MCO1SOURCE_HSE (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1)
401 #define LL_RCC_MCO1SOURCE_PLL1QCLK (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0)
402 #define LL_RCC_MCO1SOURCE_HSI48 (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_2)
403 #define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | 0x00000000U)
404 #define LL_RCC_MCO2SOURCE_PLL2PCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_0)
405 #define LL_RCC_MCO2SOURCE_HSE (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1)
406 #define LL_RCC_MCO2SOURCE_PLL1PCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0)
407 #define LL_RCC_MCO2SOURCE_CSI (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2)
408 #define LL_RCC_MCO2SOURCE_LSI (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2|RCC_CFGR_MCO2_0)
409 /**
410 * @}
411 */
412
413 /** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler
414 * @{
415 */
416 #define LL_RCC_MCO1_DIV_1 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0)
417 #define LL_RCC_MCO1_DIV_2 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1)
418 #define LL_RCC_MCO1_DIV_3 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)
419 #define LL_RCC_MCO1_DIV_4 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2)
420 #define LL_RCC_MCO1_DIV_5 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
421 #define LL_RCC_MCO1_DIV_6 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
422 #define LL_RCC_MCO1_DIV_7 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
423 #define LL_RCC_MCO1_DIV_8 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_3)
424 #define LL_RCC_MCO1_DIV_9 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)
425 #define LL_RCC_MCO1_DIV_10 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
426 #define LL_RCC_MCO1_DIV_11 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
427 #define LL_RCC_MCO1_DIV_12 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
428 #define LL_RCC_MCO1_DIV_13 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
429 #define LL_RCC_MCO1_DIV_14 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
430 #define LL_RCC_MCO1_DIV_15 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE)
431 #define LL_RCC_MCO2_DIV_1 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0)
432 #define LL_RCC_MCO2_DIV_2 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1)
433 #define LL_RCC_MCO2_DIV_3 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1)
434 #define LL_RCC_MCO2_DIV_4 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2)
435 #define LL_RCC_MCO2_DIV_5 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2)
436 #define LL_RCC_MCO2_DIV_6 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)
437 #define LL_RCC_MCO2_DIV_7 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)
438 #define LL_RCC_MCO2_DIV_8 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_3)
439 #define LL_RCC_MCO2_DIV_9 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_3)
440 #define LL_RCC_MCO2_DIV_10 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3)
441 #define LL_RCC_MCO2_DIV_11 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3)
442 #define LL_RCC_MCO2_DIV_12 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
443 #define LL_RCC_MCO2_DIV_13 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
444 #define LL_RCC_MCO2_DIV_14 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
445 #define LL_RCC_MCO2_DIV_15 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE)
446
447 /**
448 * @}
449 */
450
451 /** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock
452 * @{
453 */
454 #define LL_RCC_RTC_NOCLOCK (uint32_t)(0x00000000U)
455 #define LL_RCC_RTC_HSE_DIV_2 (uint32_t)(RCC_CFGR_RTCPRE_1)
456 #define LL_RCC_RTC_HSE_DIV_3 (uint32_t)(RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
457 #define LL_RCC_RTC_HSE_DIV_4 (uint32_t)(RCC_CFGR_RTCPRE_2)
458 #define LL_RCC_RTC_HSE_DIV_5 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
459 #define LL_RCC_RTC_HSE_DIV_6 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
460 #define LL_RCC_RTC_HSE_DIV_7 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
461 #define LL_RCC_RTC_HSE_DIV_8 (uint32_t)(RCC_CFGR_RTCPRE_3)
462 #define LL_RCC_RTC_HSE_DIV_9 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
463 #define LL_RCC_RTC_HSE_DIV_10 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
464 #define LL_RCC_RTC_HSE_DIV_11 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
465 #define LL_RCC_RTC_HSE_DIV_12 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
466 #define LL_RCC_RTC_HSE_DIV_13 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
467 #define LL_RCC_RTC_HSE_DIV_14 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
468 #define LL_RCC_RTC_HSE_DIV_15 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
469 #define LL_RCC_RTC_HSE_DIV_16 (uint32_t)(RCC_CFGR_RTCPRE_4)
470 #define LL_RCC_RTC_HSE_DIV_17 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)
471 #define LL_RCC_RTC_HSE_DIV_18 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)
472 #define LL_RCC_RTC_HSE_DIV_19 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
473 #define LL_RCC_RTC_HSE_DIV_20 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)
474 #define LL_RCC_RTC_HSE_DIV_21 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
475 #define LL_RCC_RTC_HSE_DIV_22 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
476 #define LL_RCC_RTC_HSE_DIV_23 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
477 #define LL_RCC_RTC_HSE_DIV_24 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)
478 #define LL_RCC_RTC_HSE_DIV_25 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
479 #define LL_RCC_RTC_HSE_DIV_26 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
480 #define LL_RCC_RTC_HSE_DIV_27 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
481 #define LL_RCC_RTC_HSE_DIV_28 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
482 #define LL_RCC_RTC_HSE_DIV_29 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
483 #define LL_RCC_RTC_HSE_DIV_30 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
484 #define LL_RCC_RTC_HSE_DIV_31 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
485 #define LL_RCC_RTC_HSE_DIV_32 (uint32_t)(RCC_CFGR_RTCPRE_5)
486 #define LL_RCC_RTC_HSE_DIV_33 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_0)
487 #define LL_RCC_RTC_HSE_DIV_34 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1)
488 #define LL_RCC_RTC_HSE_DIV_35 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
489 #define LL_RCC_RTC_HSE_DIV_36 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2)
490 #define LL_RCC_RTC_HSE_DIV_37 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
491 #define LL_RCC_RTC_HSE_DIV_38 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
492 #define LL_RCC_RTC_HSE_DIV_39 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
493 #define LL_RCC_RTC_HSE_DIV_40 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3)
494 #define LL_RCC_RTC_HSE_DIV_41 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
495 #define LL_RCC_RTC_HSE_DIV_42 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
496 #define LL_RCC_RTC_HSE_DIV_43 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
497 #define LL_RCC_RTC_HSE_DIV_44 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
498 #define LL_RCC_RTC_HSE_DIV_45 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
499 #define LL_RCC_RTC_HSE_DIV_46 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
500 #define LL_RCC_RTC_HSE_DIV_47 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
501 #define LL_RCC_RTC_HSE_DIV_48 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4)
502 #define LL_RCC_RTC_HSE_DIV_49 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)
503 #define LL_RCC_RTC_HSE_DIV_50 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)
504 #define LL_RCC_RTC_HSE_DIV_51 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
505 #define LL_RCC_RTC_HSE_DIV_52 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)
506 #define LL_RCC_RTC_HSE_DIV_53 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
507 #define LL_RCC_RTC_HSE_DIV_54 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
508 #define LL_RCC_RTC_HSE_DIV_55 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
509 #define LL_RCC_RTC_HSE_DIV_56 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)
510 #define LL_RCC_RTC_HSE_DIV_57 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
511 #define LL_RCC_RTC_HSE_DIV_58 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
512 #define LL_RCC_RTC_HSE_DIV_59 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
513 #define LL_RCC_RTC_HSE_DIV_60 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
514 #define LL_RCC_RTC_HSE_DIV_61 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
515 #define LL_RCC_RTC_HSE_DIV_62 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
516 #define LL_RCC_RTC_HSE_DIV_63 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
517 /**
518 * @}
519 */
520
521 /** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection
522 * @{
523 */
524 #if defined(RCC_D2CCIP2R_USART16SEL)
525 #define LL_RCC_USART16_CLKSOURCE_PCLK2 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U)
526 #define LL_RCC_USART16_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0)
527 #define LL_RCC_USART16_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_1)
528 #define LL_RCC_USART16_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)
529 #define LL_RCC_USART16_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_2)
530 #define LL_RCC_USART16_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)
531 /* Aliases */
532 #define LL_RCC_USART16910_CLKSOURCE_PCLK2 LL_RCC_USART16_CLKSOURCE_PCLK2
533 #define LL_RCC_USART16910_CLKSOURCE_PLL2Q LL_RCC_USART16_CLKSOURCE_PLL2Q
534 #define LL_RCC_USART16910_CLKSOURCE_PLL3Q LL_RCC_USART16_CLKSOURCE_PLL3Q
535 #define LL_RCC_USART16910_CLKSOURCE_HSI LL_RCC_USART16_CLKSOURCE_HSI
536 #define LL_RCC_USART16910_CLKSOURCE_CSI LL_RCC_USART16_CLKSOURCE_CSI
537 #define LL_RCC_USART16910_CLKSOURCE_LSE LL_RCC_USART16_CLKSOURCE_LSE
538
539 #elif defined(RCC_D2CCIP2R_USART16910SEL)
540 #define LL_RCC_USART16910_CLKSOURCE_PCLK2 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, 0x00000000U)
541 #define LL_RCC_USART16910_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0)
542 #define LL_RCC_USART16910_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_1)
543 #define LL_RCC_USART16910_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_1)
544 #define LL_RCC_USART16910_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_2)
545 #define LL_RCC_USART16910_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_2)
546 /* Aliases */
547 #define LL_RCC_USART16_CLKSOURCE_PCLK2 LL_RCC_USART16910_CLKSOURCE_PCLK2
548 #define LL_RCC_USART16_CLKSOURCE_PLL2Q LL_RCC_USART16910_CLKSOURCE_PLL2Q
549 #define LL_RCC_USART16_CLKSOURCE_PLL3Q LL_RCC_USART16910_CLKSOURCE_PLL3Q
550 #define LL_RCC_USART16_CLKSOURCE_HSI LL_RCC_USART16910_CLKSOURCE_HSI
551 #define LL_RCC_USART16_CLKSOURCE_CSI LL_RCC_USART16910_CLKSOURCE_CSI
552 #define LL_RCC_USART16_CLKSOURCE_LSE LL_RCC_USART16910_CLKSOURCE_LSE
553
554 #else
555 #define LL_RCC_USART16910_CLKSOURCE_PCLK2 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U)
556 #define LL_RCC_USART16910_CLKSOURCE_PLL2Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0)
557 #define LL_RCC_USART16910_CLKSOURCE_PLL3Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_1)
558 #define LL_RCC_USART16910_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1)
559 #define LL_RCC_USART16910_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_2)
560 #define LL_RCC_USART16910_CLKSOURCE_LSE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2)
561 /* Aliases */
562 #define LL_RCC_USART16_CLKSOURCE_PCLK2 LL_RCC_USART16910_CLKSOURCE_PCLK2
563 #define LL_RCC_USART16_CLKSOURCE_PLL2Q LL_RCC_USART16910_CLKSOURCE_PLL2Q
564 #define LL_RCC_USART16_CLKSOURCE_PLL3Q LL_RCC_USART16910_CLKSOURCE_PLL3Q
565 #define LL_RCC_USART16_CLKSOURCE_HSI LL_RCC_USART16910_CLKSOURCE_HSI
566 #define LL_RCC_USART16_CLKSOURCE_CSI LL_RCC_USART16910_CLKSOURCE_CSI
567 #define LL_RCC_USART16_CLKSOURCE_LSE LL_RCC_USART16910_CLKSOURCE_LSE
568 #endif /* RCC_D2CCIP2R_USART16SEL */
569 #if defined(RCC_D2CCIP2R_USART28SEL)
570 #define LL_RCC_USART234578_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U)
571 #define LL_RCC_USART234578_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0)
572 #define LL_RCC_USART234578_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_1)
573 #define LL_RCC_USART234578_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
574 #define LL_RCC_USART234578_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_2)
575 #define LL_RCC_USART234578_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)
576 #else
577 #define LL_RCC_USART234578_CLKSOURCE_PCLK1 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U)
578 #define LL_RCC_USART234578_CLKSOURCE_PLL2Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0)
579 #define LL_RCC_USART234578_CLKSOURCE_PLL3Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_1)
580 #define LL_RCC_USART234578_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1)
581 #define LL_RCC_USART234578_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_2)
582 #define LL_RCC_USART234578_CLKSOURCE_LSE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2)
583 #endif /* RCC_D2CCIP2R_USART28SEL */
584 /**
585 * @}
586 */
587
588 /** @defgroup RCC_LL_EC_LPUARTx_CLKSOURCE Peripheral LPUART clock source selection
589 * @{
590 */
591 #if defined(RCC_D3CCIPR_LPUART1SEL)
592 #define LL_RCC_LPUART1_CLKSOURCE_PCLK4 (0x00000000U)
593 #define LL_RCC_LPUART1_CLKSOURCE_PLL2Q (RCC_D3CCIPR_LPUART1SEL_0)
594 #define LL_RCC_LPUART1_CLKSOURCE_PLL3Q (RCC_D3CCIPR_LPUART1SEL_1)
595 #define LL_RCC_LPUART1_CLKSOURCE_HSI (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1)
596 #define LL_RCC_LPUART1_CLKSOURCE_CSI (RCC_D3CCIPR_LPUART1SEL_2)
597 #define LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_2)
598 #else
599 #define LL_RCC_LPUART1_CLKSOURCE_PCLK4 (0x00000000U)
600 #define LL_RCC_LPUART1_CLKSOURCE_PLL2Q (RCC_SRDCCIPR_LPUART1SEL_0)
601 #define LL_RCC_LPUART1_CLKSOURCE_PLL3Q (RCC_SRDCCIPR_LPUART1SEL_1)
602 #define LL_RCC_LPUART1_CLKSOURCE_HSI (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1)
603 #define LL_RCC_LPUART1_CLKSOURCE_CSI (RCC_SRDCCIPR_LPUART1SEL_2)
604 #define LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_2)
605 #endif /* RCC_D3CCIPR_LPUART1SEL */
606 /**
607 * @}
608 */
609
610 /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection
611 * @{
612 */
613 #if defined (RCC_D2CCIP2R_I2C123SEL)
614 #define LL_RCC_I2C123_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U)
615 #define LL_RCC_I2C123_CLKSOURCE_PLL3R LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0)
616 #define LL_RCC_I2C123_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_1)
617 #define LL_RCC_I2C123_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)
618 /* Aliases */
619 #define LL_RCC_I2C1235_CLKSOURCE_PCLK1 LL_RCC_I2C123_CLKSOURCE_PCLK1
620 #define LL_RCC_I2C1235_CLKSOURCE_PLL3R LL_RCC_I2C123_CLKSOURCE_PLL3R
621 #define LL_RCC_I2C1235_CLKSOURCE_HSI LL_RCC_I2C123_CLKSOURCE_HSI
622 #define LL_RCC_I2C1235_CLKSOURCE_CSI LL_RCC_I2C123_CLKSOURCE_CSI
623
624 #elif defined (RCC_D2CCIP2R_I2C1235SEL)
625 #define LL_RCC_I2C1235_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, 0x00000000U)
626 #define LL_RCC_I2C1235_CLKSOURCE_PLL3R LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_0)
627 #define LL_RCC_I2C1235_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_1)
628 #define LL_RCC_I2C1235_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_0 | RCC_D2CCIP2R_I2C1235SEL_1)
629 /* Aliases */
630 #define LL_RCC_I2C123_CLKSOURCE_PCLK1 LL_RCC_I2C1235_CLKSOURCE_PCLK1
631 #define LL_RCC_I2C123_CLKSOURCE_PLL3R LL_RCC_I2C1235_CLKSOURCE_PLL3R
632 #define LL_RCC_I2C123_CLKSOURCE_HSI LL_RCC_I2C1235_CLKSOURCE_HSI
633 #define LL_RCC_I2C123_CLKSOURCE_CSI LL_RCC_I2C1235_CLKSOURCE_CSI
634
635 #else
636 #define LL_RCC_I2C123_CLKSOURCE_PCLK1 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U)
637 #define LL_RCC_I2C123_CLKSOURCE_PLL3R LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0)
638 #define LL_RCC_I2C123_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_1)
639 #define LL_RCC_I2C123_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1)
640 #endif /* RCC_D2CCIP2R_I2C123SEL */
641 #if defined (RCC_D3CCIPR_I2C4SEL)
642 #define LL_RCC_I2C4_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, 0x00000000U)
643 #define LL_RCC_I2C4_CLKSOURCE_PLL3R LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, RCC_D3CCIPR_I2C4SEL_0)
644 #define LL_RCC_I2C4_CLKSOURCE_HSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, RCC_D3CCIPR_I2C4SEL_1)
645 #define LL_RCC_I2C4_CLKSOURCE_CSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1)
646 #else
647 #define LL_RCC_I2C4_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, 0x00000000U)
648 #define LL_RCC_I2C4_CLKSOURCE_PLL3R LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, RCC_SRDCCIPR_I2C4SEL_0)
649 #define LL_RCC_I2C4_CLKSOURCE_HSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, RCC_SRDCCIPR_I2C4SEL_1)
650 #define LL_RCC_I2C4_CLKSOURCE_CSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1)
651 #endif /* RCC_D3CCIPR_I2C4SEL */
652 /**
653 * @}
654 */
655
656 /** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE Peripheral LPTIM clock source selection
657 * @{
658 */
659 #if defined(RCC_D2CCIP2R_LPTIM1SEL)
660 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, 0x00000000U)
661 #define LL_RCC_LPTIM1_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_0)
662 #define LL_RCC_LPTIM1_CLKSOURCE_PLL3R LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_1)
663 #define LL_RCC_LPTIM1_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1)
664 #define LL_RCC_LPTIM1_CLKSOURCE_LSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_2)
665 #define LL_RCC_LPTIM1_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2)
666 #else
667 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, 0x00000000U)
668 #define LL_RCC_LPTIM1_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_0)
669 #define LL_RCC_LPTIM1_CLKSOURCE_PLL3R LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_1)
670 #define LL_RCC_LPTIM1_CLKSOURCE_LSE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1)
671 #define LL_RCC_LPTIM1_CLKSOURCE_LSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_2)
672 #define LL_RCC_LPTIM1_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2)
673 #endif /* RCC_D2CCIP2R_LPTIM1SEL */
674 #if defined(RCC_D3CCIPR_LPTIM2SEL)
675 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, 0x00000000U)
676 #define LL_RCC_LPTIM2_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_0)
677 #define LL_RCC_LPTIM2_CLKSOURCE_PLL3R LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_1)
678 #define LL_RCC_LPTIM2_CLKSOURCE_LSE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1)
679 #define LL_RCC_LPTIM2_CLKSOURCE_LSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_2)
680 #define LL_RCC_LPTIM2_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2)
681 #else
682 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, 0x00000000U)
683 #define LL_RCC_LPTIM2_CLKSOURCE_PLL2P LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_0)
684 #define LL_RCC_LPTIM2_CLKSOURCE_PLL3R LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_1)
685 #define LL_RCC_LPTIM2_CLKSOURCE_LSE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1)
686 #define LL_RCC_LPTIM2_CLKSOURCE_LSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_2)
687 #define LL_RCC_LPTIM2_CLKSOURCE_CLKP LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2)
688 #endif /* RCC_D3CCIPR_LPTIM2SEL */
689 #if defined(RCC_D3CCIPR_LPTIM345SEL)
690 #define LL_RCC_LPTIM345_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, 0x00000000U)
691 #define LL_RCC_LPTIM345_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0)
692 #define LL_RCC_LPTIM345_CLKSOURCE_PLL3R LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_1)
693 #define LL_RCC_LPTIM345_CLKSOURCE_LSE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)
694 #define LL_RCC_LPTIM345_CLKSOURCE_LSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_2)
695 #define LL_RCC_LPTIM345_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)
696 #else
697 #define LL_RCC_LPTIM345_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, 0x00000000U)
698 #define LL_RCC_LPTIM345_CLKSOURCE_PLL2P LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0)
699 #define LL_RCC_LPTIM345_CLKSOURCE_PLL3R LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_1)
700 #define LL_RCC_LPTIM345_CLKSOURCE_LSE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1)
701 #define LL_RCC_LPTIM345_CLKSOURCE_LSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_2)
702 #define LL_RCC_LPTIM345_CLKSOURCE_CLKP LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2)
703 /* aliases*/
704 #define LL_RCC_LPTIM3_CLKSOURCE_PCLK4 LL_RCC_LPTIM345_CLKSOURCE_PCLK4
705 #define LL_RCC_LPTIM3_CLKSOURCE_PLL2P LL_RCC_LPTIM345_CLKSOURCE_PLL2P
706 #define LL_RCC_LPTIM3_CLKSOURCE_PLL3R LL_RCC_LPTIM345_CLKSOURCE_PLL3R
707 #define LL_RCC_LPTIM3_CLKSOURCE_LSE LL_RCC_LPTIM345_CLKSOURCE_LSE
708 #define LL_RCC_LPTIM3_CLKSOURCE_LSI LL_RCC_LPTIM345_CLKSOURCE_LSI
709 #define LL_RCC_LPTIM3_CLKSOURCE_CLKP LL_RCC_LPTIM345_CLKSOURCE_CLKP
710 #endif /* RCC_D3CCIPR_LPTIM345SEL */
711 /**
712 * @}
713 */
714
715 /** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection
716 * @{
717 */
718 #if defined(RCC_D2CCIP1R_SAI1SEL)
719 #define LL_RCC_SAI1_CLKSOURCE_PLL1Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, 0x00000000U)
720 #define LL_RCC_SAI1_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_0)
721 #define LL_RCC_SAI1_CLKSOURCE_PLL3P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_1)
722 #define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1)
723 #define LL_RCC_SAI1_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_2)
724 #else
725 #define LL_RCC_SAI1_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, 0x00000000U)
726 #define LL_RCC_SAI1_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_0)
727 #define LL_RCC_SAI1_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_1)
728 #define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1)
729 #define LL_RCC_SAI1_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_2)
730 #endif
731 #if defined(SAI3)
732 #define LL_RCC_SAI23_CLKSOURCE_PLL1Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U)
733 #define LL_RCC_SAI23_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0)
734 #define LL_RCC_SAI23_CLKSOURCE_PLL3P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_1)
735 #define LL_RCC_SAI23_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1)
736 #define LL_RCC_SAI23_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_2)
737 #endif /* SAI3 */
738 #if defined(RCC_CDCCIP1R_SAI2ASEL)
739 #define LL_RCC_SAI2A_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, 0x00000000U)
740 #define LL_RCC_SAI2A_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_0)
741 #define LL_RCC_SAI2A_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_1)
742 #define LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1)
743 #define LL_RCC_SAI2A_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_2)
744 #define LL_RCC_SAI2A_CLKSOURCE_SPDIF LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2)
745 #endif /* RCC_CDCCIP1R_SAI2ASEL */
746 #if defined(RCC_CDCCIP1R_SAI2BSEL)
747 #define LL_RCC_SAI2B_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, 0x00000000U)
748 #define LL_RCC_SAI2B_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_0)
749 #define LL_RCC_SAI2B_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_1)
750 #define LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1)
751 #define LL_RCC_SAI2B_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_2)
752 #define LL_RCC_SAI2B_CLKSOURCE_SPDIF LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2)
753 #endif /* RCC_CDCCIP1R_SAI2BSEL */
754 #if defined(SAI4_Block_A)
755 #define LL_RCC_SAI4A_CLKSOURCE_PLL1Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, 0x00000000U)
756 #define LL_RCC_SAI4A_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_0)
757 #define LL_RCC_SAI4A_CLKSOURCE_PLL3P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_1)
758 #define LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1)
759 #define LL_RCC_SAI4A_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_2)
760 #if defined(RCC_VER_3_0)
761 #define LL_RCC_SAI4A_CLKSOURCE_SPDIF LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_2 | RCC_D3CCIPR_SAI4ASEL_0)
762 #endif /* RCC_VER_3_0 */
763 #endif /* SAI4_Block_A */
764 #if defined(SAI4_Block_B)
765 #define LL_RCC_SAI4B_CLKSOURCE_PLL1Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, 0x00000000U)
766 #define LL_RCC_SAI4B_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_0)
767 #define LL_RCC_SAI4B_CLKSOURCE_PLL3P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_1)
768 #define LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1)
769 #define LL_RCC_SAI4B_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_2)
770 #if defined(RCC_VER_3_0)
771 #define LL_RCC_SAI4B_CLKSOURCE_SPDIF LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_2 | RCC_D3CCIPR_SAI4BSEL_0)
772 #endif /* RCC_VER_3_0 */
773 #endif /* SAI4_Block_B */
774 /**
775 * @}
776 */
777
778 /** @defgroup RCC_LL_EC_SDMMC_CLKSOURCE Peripheral SDMMC clock source selection
779 * @{
780 */
781 #if defined(RCC_D1CCIPR_SDMMCSEL)
782 #define LL_RCC_SDMMC_CLKSOURCE_PLL1Q (0x00000000U)
783 #define LL_RCC_SDMMC_CLKSOURCE_PLL2R (RCC_D1CCIPR_SDMMCSEL)
784 #else
785 #define LL_RCC_SDMMC_CLKSOURCE_PLL1Q (0x00000000U)
786 #define LL_RCC_SDMMC_CLKSOURCE_PLL2R (RCC_CDCCIPR_SDMMCSEL)
787 #endif /* RCC_D1CCIPR_SDMMCSEL */
788 /**
789 * @}
790 */
791
792 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
793 * @{
794 */
795 #if defined(RCC_D2CCIP2R_RNGSEL)
796 #define LL_RCC_RNG_CLKSOURCE_HSI48 (0x00000000U)
797 #define LL_RCC_RNG_CLKSOURCE_PLL1Q (RCC_D2CCIP2R_RNGSEL_0)
798 #define LL_RCC_RNG_CLKSOURCE_LSE (RCC_D2CCIP2R_RNGSEL_1)
799 #define LL_RCC_RNG_CLKSOURCE_LSI (RCC_D2CCIP2R_RNGSEL_1 | RCC_D2CCIP2R_RNGSEL_0)
800 #else
801 #define LL_RCC_RNG_CLKSOURCE_HSI48 (0x00000000U)
802 #define LL_RCC_RNG_CLKSOURCE_PLL1Q (RCC_CDCCIP2R_RNGSEL_0)
803 #define LL_RCC_RNG_CLKSOURCE_LSE (RCC_CDCCIP2R_RNGSEL_1)
804 #define LL_RCC_RNG_CLKSOURCE_LSI (RCC_CDCCIP2R_RNGSEL_1 | RCC_CDCCIP2R_RNGSEL_0)
805 #endif /* RCC_D2CCIP2R_RNGSEL */
806 /**
807 * @}
808 */
809
810 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
811 * @{
812 */
813 #if defined(RCC_D2CCIP2R_USBSEL)
814 #define LL_RCC_USB_CLKSOURCE_DISABLE (0x00000000U)
815 #define LL_RCC_USB_CLKSOURCE_PLL1Q (RCC_D2CCIP2R_USBSEL_0)
816 #define LL_RCC_USB_CLKSOURCE_PLL3Q (RCC_D2CCIP2R_USBSEL_1)
817 #define LL_RCC_USB_CLKSOURCE_HSI48 (RCC_D2CCIP2R_USBSEL_1 | RCC_D2CCIP2R_USBSEL_0)
818 #else
819 #define LL_RCC_USB_CLKSOURCE_DISABLE (0x00000000U)
820 #define LL_RCC_USB_CLKSOURCE_PLL1Q (RCC_CDCCIP2R_USBSEL_0)
821 #define LL_RCC_USB_CLKSOURCE_PLL3Q (RCC_CDCCIP2R_USBSEL_1)
822 #define LL_RCC_USB_CLKSOURCE_HSI48 (RCC_CDCCIP2R_USBSEL_1 | RCC_CDCCIP2R_USBSEL_0)
823 #endif /* RCC_D2CCIP2R_USBSEL */
824 /**
825 * @}
826 */
827
828 /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
829 * @{
830 */
831 #if defined(RCC_D2CCIP2R_CECSEL)
832 #define LL_RCC_CEC_CLKSOURCE_LSE (0x00000000U)
833 #define LL_RCC_CEC_CLKSOURCE_LSI (RCC_D2CCIP2R_CECSEL_0)
834 #define LL_RCC_CEC_CLKSOURCE_CSI_DIV122 (RCC_D2CCIP2R_CECSEL_1)
835 #else
836 #define LL_RCC_CEC_CLKSOURCE_LSE (0x00000000U)
837 #define LL_RCC_CEC_CLKSOURCE_LSI (RCC_CDCCIP2R_CECSEL_0)
838 #define LL_RCC_CEC_CLKSOURCE_CSI_DIV122 (RCC_CDCCIP2R_CECSEL_1)
839 #endif
840 /**
841 * @}
842 */
843
844 #if defined(DSI)
845 /** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection
846 * @{
847 */
848 #define LL_RCC_DSI_CLKSOURCE_PHY (0x00000000U)
849 #define LL_RCC_DSI_CLKSOURCE_PLL2Q (RCC_D1CCIPR_DSISEL)
850 /**
851 * @}
852 */
853 #endif /* DSI */
854
855 /** @defgroup RCC_LL_EC_DFSDM_CLKSOURCE Peripheral DFSDM clock source selection
856 * @{
857 */
858 #if defined(RCC_D2CCIP1R_DFSDM1SEL)
859 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 (0x00000000U)
860 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK (RCC_D2CCIP1R_DFSDM1SEL)
861 #else
862 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 (0x00000000U)
863 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK (RCC_CDCCIP1R_DFSDM1SEL)
864 #endif /* RCC_D2CCIP1R_DFSDM1SEL */
865 /**
866 * @}
867 */
868
869 #if defined(DFSDM2_BASE)
870 /** @defgroup RCC_LL_EC_DFSDM2_CLKSOURCE Peripheral DFSDM2 clock source selection
871 * @{
872 */
873 #define LL_RCC_DFSDM2_CLKSOURCE_PCLK4 (0x00000000U)
874 #define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (RCC_SRDCCIPR_DFSDM2SEL)
875 /**
876 * @}
877 */
878 #endif /* DFSDM2_BASE */
879
880 /** @defgroup RCC_LL_EC_FMC_CLKSOURCE Peripheral FMC clock source selection
881 * @{
882 */
883 #if defined(RCC_D1CCIPR_FMCSEL)
884 #define LL_RCC_FMC_CLKSOURCE_HCLK (0x00000000U)
885 #define LL_RCC_FMC_CLKSOURCE_PLL1Q (RCC_D1CCIPR_FMCSEL_0)
886 #define LL_RCC_FMC_CLKSOURCE_PLL2R (RCC_D1CCIPR_FMCSEL_1)
887 #define LL_RCC_FMC_CLKSOURCE_CLKP (RCC_D1CCIPR_FMCSEL_0 | RCC_D1CCIPR_FMCSEL_1)
888 #else
889 #define LL_RCC_FMC_CLKSOURCE_HCLK (0x00000000U)
890 #define LL_RCC_FMC_CLKSOURCE_PLL1Q (RCC_CDCCIPR_FMCSEL_0)
891 #define LL_RCC_FMC_CLKSOURCE_PLL2R (RCC_CDCCIPR_FMCSEL_1)
892 #define LL_RCC_FMC_CLKSOURCE_CLKP (RCC_CDCCIPR_FMCSEL_0 | RCC_CDCCIPR_FMCSEL_1)
893 #endif /* RCC_D1CCIPR_FMCSEL */
894 /**
895 * @}
896 */
897
898 #if defined(QUADSPI)
899 /** @defgroup RCC_LL_EC_QSPI_CLKSOURCE Peripheral QSPI clock source selection
900 * @{
901 */
902 #define LL_RCC_QSPI_CLKSOURCE_HCLK (0x00000000U)
903 #define LL_RCC_QSPI_CLKSOURCE_PLL1Q (RCC_D1CCIPR_QSPISEL_0)
904 #define LL_RCC_QSPI_CLKSOURCE_PLL2R (RCC_D1CCIPR_QSPISEL_1)
905 #define LL_RCC_QSPI_CLKSOURCE_CLKP (RCC_D1CCIPR_QSPISEL_0 | RCC_D1CCIPR_QSPISEL_1)
906 /**
907 * @}
908 */
909 #endif /* QUADSPI */
910
911
912 #if defined(OCTOSPI1) || defined(OCTOSPI2)
913 /** @defgroup RCC_LL_EC_OSPI_CLKSOURCE Peripheral OSPI clock source selection
914 * @{
915 */
916 #if defined(RCC_D1CCIPR_OCTOSPISEL)
917 #define LL_RCC_OSPI_CLKSOURCE_HCLK (0x00000000U)
918 #define LL_RCC_OSPI_CLKSOURCE_PLL1Q (RCC_D1CCIPR_OCTOSPISEL_0)
919 #define LL_RCC_OSPI_CLKSOURCE_PLL2R (RCC_D1CCIPR_OCTOSPISEL_1)
920 #define LL_RCC_OSPI_CLKSOURCE_CLKP (RCC_D1CCIPR_OCTOSPISEL_0 | RCC_D1CCIPR_OCTOSPISEL_1)
921 #else
922 #define LL_RCC_OSPI_CLKSOURCE_HCLK (0x00000000U)
923 #define LL_RCC_OSPI_CLKSOURCE_PLL1Q (RCC_CDCCIPR_OCTOSPISEL_0)
924 #define LL_RCC_OSPI_CLKSOURCE_PLL2R (RCC_CDCCIPR_OCTOSPISEL_1)
925 #define LL_RCC_OSPI_CLKSOURCE_CLKP (RCC_CDCCIPR_OCTOSPISEL_0 | RCC_CDCCIPR_OCTOSPISEL_1)
926 #endif /* RCC_D1CCIPR_OCTOSPISEL */
927 /**
928 * @}
929 */
930 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
931
932
933 /** @defgroup RCC_LL_EC_CLKP_CLKSOURCE Peripheral CLKP clock source selection
934 * @{
935 */
936 #if defined(RCC_D1CCIPR_CKPERSEL)
937 #define LL_RCC_CLKP_CLKSOURCE_HSI (0x00000000U)
938 #define LL_RCC_CLKP_CLKSOURCE_CSI (RCC_D1CCIPR_CKPERSEL_0)
939 #define LL_RCC_CLKP_CLKSOURCE_HSE (RCC_D1CCIPR_CKPERSEL_1)
940 #else
941 #define LL_RCC_CLKP_CLKSOURCE_HSI (0x00000000U)
942 #define LL_RCC_CLKP_CLKSOURCE_CSI (RCC_CDCCIPR_CKPERSEL_0)
943 #define LL_RCC_CLKP_CLKSOURCE_HSE (RCC_CDCCIPR_CKPERSEL_1)
944 #endif /* RCC_D1CCIPR_CKPERSEL */
945 /**
946 * @}
947 */
948
949 /** @defgroup RCC_LL_EC_SPIx_CLKSOURCE Peripheral SPI clock source selection
950 * @{
951 */
952 #if defined(RCC_D2CCIP1R_SPI123SEL)
953 #define LL_RCC_SPI123_CLKSOURCE_PLL1Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U)
954 #define LL_RCC_SPI123_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0)
955 #define LL_RCC_SPI123_CLKSOURCE_PLL3P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_1)
956 #define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)
957 #define LL_RCC_SPI123_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_2)
958 #else
959 #define LL_RCC_SPI123_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U)
960 #define LL_RCC_SPI123_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0)
961 #define LL_RCC_SPI123_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_1)
962 #define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1)
963 #define LL_RCC_SPI123_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_2)
964 #endif /* RCC_D2CCIP1R_SPI123SEL */
965 #if defined(RCC_D2CCIP1R_SPI45SEL)
966 #define LL_RCC_SPI45_CLKSOURCE_PCLK2 LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, 0x00000000U)
967 #define LL_RCC_SPI45_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_0)
968 #define LL_RCC_SPI45_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_1)
969 #define LL_RCC_SPI45_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)
970 #define LL_RCC_SPI45_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_2)
971 #define LL_RCC_SPI45_CLKSOURCE_HSE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)
972 #else
973 #define LL_RCC_SPI45_CLKSOURCE_PCLK2 LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, 0x00000000U)
974 #define LL_RCC_SPI45_CLKSOURCE_PLL2Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_0)
975 #define LL_RCC_SPI45_CLKSOURCE_PLL3Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_1)
976 #define LL_RCC_SPI45_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1)
977 #define LL_RCC_SPI45_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_2)
978 #define LL_RCC_SPI45_CLKSOURCE_HSE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2)
979 #endif /* (RCC_D2CCIP1R_SPI45SEL */
980 #if defined(RCC_D3CCIPR_SPI6SEL)
981 #define LL_RCC_SPI6_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, 0x00000000U)
982 #define LL_RCC_SPI6_CLKSOURCE_PLL2Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_0)
983 #define LL_RCC_SPI6_CLKSOURCE_PLL3Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_1)
984 #define LL_RCC_SPI6_CLKSOURCE_HSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1)
985 #define LL_RCC_SPI6_CLKSOURCE_CSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_2)
986 #define LL_RCC_SPI6_CLKSOURCE_HSE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2)
987 #else
988 #define LL_RCC_SPI6_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, 0x00000000U)
989 #define LL_RCC_SPI6_CLKSOURCE_PLL2Q LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_0)
990 #define LL_RCC_SPI6_CLKSOURCE_PLL3Q LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_1)
991 #define LL_RCC_SPI6_CLKSOURCE_HSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)
992 #define LL_RCC_SPI6_CLKSOURCE_CSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_2)
993 #define LL_RCC_SPI6_CLKSOURCE_HSE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)
994 #define LL_RCC_SPI6_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)
995 #endif /* RCC_D3CCIPR_SPI6SEL */
996 /**
997 * @}
998 */
999
1000 /** @defgroup RCC_LL_EC_SPDIF_CLKSOURCE Peripheral SPDIF clock source selection
1001 * @{
1002 */
1003 #if defined(RCC_D2CCIP1R_SPDIFSEL)
1004 #define LL_RCC_SPDIF_CLKSOURCE_PLL1Q (0x00000000U)
1005 #define LL_RCC_SPDIF_CLKSOURCE_PLL2R (RCC_D2CCIP1R_SPDIFSEL_0)
1006 #define LL_RCC_SPDIF_CLKSOURCE_PLL3R (RCC_D2CCIP1R_SPDIFSEL_1)
1007 #define LL_RCC_SPDIF_CLKSOURCE_HSI (RCC_D2CCIP1R_SPDIFSEL_0 | RCC_D2CCIP1R_SPDIFSEL_1)
1008 #else
1009 #define LL_RCC_SPDIF_CLKSOURCE_PLL1Q (0x00000000U)
1010 #define LL_RCC_SPDIF_CLKSOURCE_PLL2R (RCC_CDCCIP1R_SPDIFSEL_0)
1011 #define LL_RCC_SPDIF_CLKSOURCE_PLL3R (RCC_CDCCIP1R_SPDIFSEL_1)
1012 #define LL_RCC_SPDIF_CLKSOURCE_HSI (RCC_CDCCIP1R_SPDIFSEL_0 | RCC_CDCCIP1R_SPDIFSEL_1)
1013 #endif /* RCC_D2CCIP1R_SPDIFSEL */
1014 /**
1015 * @}
1016 */
1017
1018 #if defined(FDCAN1) || defined(FDCAN2)
1019 /** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN clock source selection
1020 * @{
1021 */
1022 #if defined(RCC_D2CCIP1R_FDCANSEL)
1023 #define LL_RCC_FDCAN_CLKSOURCE_HSE (0x00000000U)
1024 #define LL_RCC_FDCAN_CLKSOURCE_PLL1Q (RCC_D2CCIP1R_FDCANSEL_0)
1025 #define LL_RCC_FDCAN_CLKSOURCE_PLL2Q (RCC_D2CCIP1R_FDCANSEL_1)
1026 #else
1027 #define LL_RCC_FDCAN_CLKSOURCE_HSE (0x00000000U)
1028 #define LL_RCC_FDCAN_CLKSOURCE_PLL1Q (RCC_CDCCIP1R_FDCANSEL_0)
1029 #define LL_RCC_FDCAN_CLKSOURCE_PLL2Q (RCC_CDCCIP1R_FDCANSEL_1)
1030 #endif /* RCC_D2CCIP1R_FDCANSEL */
1031 /**
1032 * @}
1033 */
1034 #endif /*FDCAN1 || FDCAN2*/
1035
1036 /** @defgroup RCC_LL_EC_SWP_CLKSOURCE Peripheral SWP clock source selection
1037 * @{
1038 */
1039 #if defined(RCC_D2CCIP1R_SWPSEL)
1040 #define LL_RCC_SWP_CLKSOURCE_PCLK1 (0x00000000U)
1041 #define LL_RCC_SWP_CLKSOURCE_HSI (RCC_D2CCIP1R_SWPSEL)
1042 #else
1043 #define LL_RCC_SWP_CLKSOURCE_PCLK1 (0x00000000U)
1044 #define LL_RCC_SWP_CLKSOURCE_HSI (RCC_CDCCIP1R_SWPSEL)
1045 #endif /* RCC_D2CCIP1R_SWPSEL */
1046 /**
1047 * @}
1048 */
1049
1050 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
1051 * @{
1052 */
1053 #if defined(RCC_D3CCIPR_ADCSEL)
1054 #define LL_RCC_ADC_CLKSOURCE_PLL2P (0x00000000U)
1055 #define LL_RCC_ADC_CLKSOURCE_PLL3R (RCC_D3CCIPR_ADCSEL_0)
1056 #define LL_RCC_ADC_CLKSOURCE_CLKP (RCC_D3CCIPR_ADCSEL_1)
1057 #else
1058 #define LL_RCC_ADC_CLKSOURCE_PLL2P (0x00000000U)
1059 #define LL_RCC_ADC_CLKSOURCE_PLL3R (RCC_SRDCCIPR_ADCSEL_0)
1060 #define LL_RCC_ADC_CLKSOURCE_CLKP (RCC_SRDCCIPR_ADCSEL_1)
1061 #endif /* RCC_D3CCIPR_ADCSEL */
1062 /**
1063 * @}
1064 */
1065
1066 /** @defgroup RCC_LL_EC_USARTx Peripheral USART get clock source
1067 * @{
1068 */
1069 #if defined (RCC_D2CCIP2R_USART16SEL)
1070 #define LL_RCC_USART16_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U)
1071 #elif defined (RCC_D2CCIP2R_USART16910SEL)
1072 #define LL_RCC_USART16_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, 0x00000000U)
1073 /* alias*/
1074 #define LL_RCC_USART16910_CLKSOURCE LL_RCC_USART16_CLKSOURCE
1075 #else
1076 #define LL_RCC_USART16_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U)
1077 /* alias*/
1078 #define LL_RCC_USART16910_CLKSOURCE LL_RCC_USART16_CLKSOURCE
1079 #endif /* RCC_D2CCIP2R_USART16SEL */
1080 #if defined (RCC_D2CCIP2R_USART28SEL)
1081 #define LL_RCC_USART234578_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U)
1082 #else
1083 #define LL_RCC_USART234578_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U)
1084 #endif /* RCC_D2CCIP2R_USART28SEL */
1085 /**
1086 * @}
1087 */
1088
1089 /** @defgroup RCC_LL_EC_LPUARTx Peripheral LPUART get clock source
1090 * @{
1091 */
1092 #if defined(RCC_D3CCIPR_LPUART1SEL)
1093 #define LL_RCC_LPUART1_CLKSOURCE RCC_D3CCIPR_LPUART1SEL
1094 #else
1095 #define LL_RCC_LPUART1_CLKSOURCE RCC_SRDCCIPR_LPUART1SEL
1096 #endif /* RCC_D3CCIPR_LPUART1SEL */
1097 /**
1098 * @}
1099 */
1100
1101 /** @defgroup RCC_LL_EC_I2Cx Peripheral I2C get clock source
1102 * @{
1103 */
1104 #if defined(RCC_D2CCIP2R_I2C123SEL)
1105 #define LL_RCC_I2C123_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U)
1106 /* alias */
1107 #define LL_RCC_I2C1235_CLKSOURCE LL_RCC_I2C123_CLKSOURCE
1108 #elif defined(RCC_D2CCIP2R_I2C1235SEL)
1109 #define LL_RCC_I2C1235_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, 0x00000000U)
1110 /* alias */
1111 #define LL_RCC_I2C123_CLKSOURCE LL_RCC_I2C1235_CLKSOURCE
1112 #else
1113 #define LL_RCC_I2C123_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U)
1114 /* alias */
1115 #define LL_RCC_I2C1235_CLKSOURCE LL_RCC_I2C123_CLKSOURCE
1116 #endif /* RCC_D2CCIP2R_I2C123SEL */
1117 #if defined(RCC_D3CCIPR_I2C4SEL)
1118 #define LL_RCC_I2C4_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, 0x00000000U)
1119 #else
1120 #define LL_RCC_I2C4_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, 0x00000000U)
1121 #endif /* RCC_D3CCIPR_I2C4SEL */
1122 /**
1123 * @}
1124 */
1125
1126 /** @defgroup RCC_LL_EC_LPTIMx Peripheral LPTIM get clock source
1127 * @{
1128 */
1129 #if defined(RCC_D2CCIP2R_LPTIM1SEL)
1130 #define LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, 0x00000000U)
1131 #else
1132 #define LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, 0x00000000U)
1133 #endif /* RCC_D2CCIP2R_LPTIM1SEL) */
1134 #if defined(RCC_D3CCIPR_LPTIM2SEL)
1135 #define LL_RCC_LPTIM2_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, 0x00000000U)
1136 #else
1137 #define LL_RCC_LPTIM2_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, 0x00000000U)
1138 #endif /* RCC_D3CCIPR_LPTIM2SEL */
1139 #if defined(RCC_D3CCIPR_LPTIM345SEL)
1140 #define LL_RCC_LPTIM345_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, 0x00000000U)
1141 #else
1142 #define LL_RCC_LPTIM345_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, 0x00000000U)
1143 #define LL_RCC_LPTIM3_CLKSOURCE LL_RCC_LPTIM345_CLKSOURCE /* alias */
1144 #endif /* RCC_D3CCIPR_LPTIM345SEL */
1145 /**
1146 * @}
1147 */
1148
1149 /** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source
1150 * @{
1151 */
1152 #if defined(RCC_D2CCIP1R_SAI1SEL)
1153 #define LL_RCC_SAI1_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, 0x00000000U)
1154 #else
1155 #define LL_RCC_SAI1_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, 0x00000000U)
1156 #endif /* RCC_D2CCIP1R_SAI1SEL */
1157 #if defined(RCC_D2CCIP1R_SAI23SEL)
1158 #define LL_RCC_SAI23_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U)
1159 #endif /* RCC_D2CCIP1R_SAI23SEL */
1160 #if defined(RCC_CDCCIP1R_SAI2ASEL)
1161 #define LL_RCC_SAI2A_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, 0x00000000U)
1162 #endif /* RCC_CDCCIP1R_SAI2ASEL */
1163 #if defined(RCC_CDCCIP1R_SAI2BSEL)
1164 #define LL_RCC_SAI2B_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, 0x00000000U)
1165 #endif /* RCC_CDCCIP1R_SAI2BSEL */
1166 #if defined(RCC_D3CCIPR_SAI4ASEL)
1167 #define LL_RCC_SAI4A_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, 0x00000000U)
1168 #endif /* RCC_D3CCIPR_SAI4ASEL */
1169 #if defined(RCC_D3CCIPR_SAI4BSEL)
1170 #define LL_RCC_SAI4B_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, 0x00000000U)
1171 #endif /* RCC_D3CCIPR_SAI4BSEL */
1172 /**
1173 * @}
1174 */
1175
1176 /** @defgroup RCC_LL_EC_SDMMC Peripheral SDMMC get clock source
1177 * @{
1178 */
1179 #if defined(RCC_D1CCIPR_SDMMCSEL)
1180 #define LL_RCC_SDMMC_CLKSOURCE RCC_D1CCIPR_SDMMCSEL
1181 #else
1182 #define LL_RCC_SDMMC_CLKSOURCE RCC_CDCCIPR_SDMMCSEL
1183 #endif /* RCC_D1CCIPR_SDMMCSEL */
1184 /**
1185 * @}
1186 */
1187
1188 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
1189 * @{
1190 */
1191 #if (RCC_D2CCIP2R_RNGSEL)
1192 #define LL_RCC_RNG_CLKSOURCE RCC_D2CCIP2R_RNGSEL
1193 #else
1194 #define LL_RCC_RNG_CLKSOURCE RCC_CDCCIP2R_RNGSEL
1195 #endif /* RCC_D2CCIP2R_RNGSEL */
1196 /**
1197 * @}
1198 */
1199
1200 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
1201 * @{
1202 */
1203 #if (RCC_D2CCIP2R_USBSEL)
1204 #define LL_RCC_USB_CLKSOURCE RCC_D2CCIP2R_USBSEL
1205 #else
1206 #define LL_RCC_USB_CLKSOURCE RCC_CDCCIP2R_USBSEL
1207 #endif /* RCC_D2CCIP2R_USBSEL */
1208 /**
1209 * @}
1210 */
1211
1212 /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
1213 * @{
1214 */
1215 #if (RCC_D2CCIP2R_CECSEL)
1216 #define LL_RCC_CEC_CLKSOURCE RCC_D2CCIP2R_CECSEL
1217 #else
1218 #define LL_RCC_CEC_CLKSOURCE RCC_CDCCIP2R_CECSEL
1219 #endif /* RCC_D2CCIP2R_CECSEL */
1220 /**
1221 * @}
1222 */
1223
1224 #if defined(DSI)
1225 /** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source
1226 * @{
1227 */
1228 #define LL_RCC_DSI_CLKSOURCE RCC_D1CCIPR_DSISEL
1229 /**
1230 * @}
1231 */
1232 #endif /* DSI */
1233
1234 /** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source
1235 * @{
1236 */
1237 #if defined(RCC_D2CCIP1R_DFSDM1SEL)
1238 #define LL_RCC_DFSDM1_CLKSOURCE RCC_D2CCIP1R_DFSDM1SEL
1239 #else
1240 #define LL_RCC_DFSDM1_CLKSOURCE RCC_CDCCIP1R_DFSDM1SEL
1241 #endif /* RCC_D2CCIP1R_DFSDM1SEL */
1242 /**
1243 * @}
1244 */
1245
1246 #if defined(DFSDM2_BASE)
1247 /** @defgroup RCC_LL_EC_DFSDM2 Peripheral DFSDM2 get clock source
1248 * @{
1249 */
1250 #define LL_RCC_DFSDM2_CLKSOURCE RCC_SRDCCIPR_DFSDM2SEL
1251 /**
1252 * @}
1253 */
1254 #endif /* DFSDM2_BASE */
1255
1256
1257
1258 /** @defgroup RCC_LL_EC_FMC Peripheral FMC get clock source
1259 * @{
1260 */
1261 #if defined(RCC_D1CCIPR_FMCSEL)
1262 #define LL_RCC_FMC_CLKSOURCE RCC_D1CCIPR_FMCSEL
1263 #else
1264 #define LL_RCC_FMC_CLKSOURCE RCC_CDCCIPR_FMCSEL
1265 #endif
1266 /**
1267 * @}
1268 */
1269
1270 #if defined(QUADSPI)
1271 /** @defgroup RCC_LL_EC_QSPI Peripheral QSPI get clock source
1272 * @{
1273 */
1274 #define LL_RCC_QSPI_CLKSOURCE RCC_D1CCIPR_QSPISEL
1275 /**
1276 * @}
1277 */
1278 #endif /* QUADSPI */
1279
1280 #if defined(OCTOSPI1) || defined(OCTOSPI2)
1281 /** @defgroup RCC_LL_EC_OSPI Peripheral OSPI get clock source
1282 * @{
1283 */
1284 #if defined(RCC_CDCCIPR_OCTOSPISEL)
1285 #define LL_RCC_OSPI_CLKSOURCE RCC_CDCCIPR_OCTOSPISEL
1286 #else
1287 #define LL_RCC_OSPI_CLKSOURCE RCC_D1CCIPR_OCTOSPISEL
1288 #endif /* RCC_CDCCIPR_OCTOSPISEL */
1289 /**
1290 * @}
1291 */
1292 #endif /* OCTOSPI1 || OCTOSPI2 */
1293
1294 /** @defgroup RCC_LL_EC_CLKP Peripheral CLKP get clock source
1295 * @{
1296 */
1297 #if defined(RCC_D1CCIPR_CKPERSEL)
1298 #define LL_RCC_CLKP_CLKSOURCE RCC_D1CCIPR_CKPERSEL
1299 #else
1300 #define LL_RCC_CLKP_CLKSOURCE RCC_CDCCIPR_CKPERSEL
1301 #endif /* RCC_D1CCIPR_CKPERSEL */
1302 /**
1303 * @}
1304 */
1305
1306 /** @defgroup RCC_LL_EC_SPIx Peripheral SPI get clock source
1307 * @{
1308 */
1309 #if defined(RCC_D2CCIP1R_SPI123SEL)
1310 #define LL_RCC_SPI123_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U)
1311 #else
1312 #define LL_RCC_SPI123_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U)
1313 #endif /* RCC_D2CCIP1R_SPI123SEL */
1314 #if defined(RCC_D2CCIP1R_SPI45SEL)
1315 #define LL_RCC_SPI45_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, 0x00000000U)
1316 #else
1317 #define LL_RCC_SPI45_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, 0x00000000U)
1318 #endif /* RCC_D2CCIP1R_SPI45SEL */
1319 #if defined(RCC_D3CCIPR_SPI6SEL)
1320 #define LL_RCC_SPI6_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, 0x00000000U)
1321 #else
1322 #define LL_RCC_SPI6_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, 0x00000000U)
1323 #endif /* RCC_D3CCIPR_SPI6SEL */
1324 /**
1325 * @}
1326 */
1327
1328 /** @defgroup RCC_LL_EC_SPDIF Peripheral SPDIF get clock source
1329 * @{
1330 */
1331 #if defined(RCC_D2CCIP1R_SPDIFSEL)
1332 #define LL_RCC_SPDIF_CLKSOURCE RCC_D2CCIP1R_SPDIFSEL
1333 #else
1334 #define LL_RCC_SPDIF_CLKSOURCE RCC_CDCCIP1R_SPDIFSEL
1335 #endif /* RCC_D2CCIP1R_SPDIFSEL */
1336 /**
1337 * @}
1338 */
1339
1340 #if defined(FDCAN1) || defined(FDCAN2)
1341 /** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get clock source
1342 * @{
1343 */
1344 #if defined(RCC_D2CCIP1R_FDCANSEL)
1345 #define LL_RCC_FDCAN_CLKSOURCE RCC_D2CCIP1R_FDCANSEL
1346 #else
1347 #define LL_RCC_FDCAN_CLKSOURCE RCC_CDCCIP1R_FDCANSEL
1348 #endif
1349 /**
1350 * @}
1351 */
1352 #endif /*FDCAN1 || FDCAN2*/
1353
1354 /** @defgroup RCC_LL_EC_SWP Peripheral SWP get clock source
1355 * @{
1356 */
1357 #if defined(RCC_D2CCIP1R_SWPSEL)
1358 #define LL_RCC_SWP_CLKSOURCE RCC_D2CCIP1R_SWPSEL
1359 #else
1360 #define LL_RCC_SWP_CLKSOURCE RCC_CDCCIP1R_SWPSEL
1361 #endif /* RCC_D2CCIP1R_SWPSEL */
1362 /**
1363 * @}
1364 */
1365
1366 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
1367 * @{
1368 */
1369 #if defined(RCC_D3CCIPR_ADCSEL)
1370 #define LL_RCC_ADC_CLKSOURCE RCC_D3CCIPR_ADCSEL
1371 #else
1372 #define LL_RCC_ADC_CLKSOURCE RCC_SRDCCIPR_ADCSEL
1373 #endif /* RCC_D3CCIPR_ADCSEL */
1374 /**
1375 * @}
1376 */
1377
1378 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
1379 * @{
1380 */
1381 #define LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)(0x00000000U)
1382 #define LL_RCC_RTC_CLKSOURCE_LSE (uint32_t)(RCC_BDCR_RTCSEL_0)
1383 #define LL_RCC_RTC_CLKSOURCE_LSI (uint32_t)(RCC_BDCR_RTCSEL_1)
1384 #define LL_RCC_RTC_CLKSOURCE_HSE (uint32_t)(RCC_BDCR_RTCSEL_0 | RCC_BDCR_RTCSEL_1)
1385 /**
1386 * @}
1387 */
1388
1389 /** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection
1390 * @{
1391 */
1392 #define LL_RCC_TIM_PRESCALER_TWICE (uint32_t)(0x00000000U)
1393 #define LL_RCC_TIM_PRESCALER_FOUR_TIMES (uint32_t)(RCC_CFGR_TIMPRE)
1394 /**
1395 * @}
1396 */
1397
1398 #if defined(HRTIM1)
1399 /** @defgroup RCC_LL_EC_HRTIM_CLKSOURCE High Resolution Timers clock selection
1400 * @{
1401 */
1402 #define LL_RCC_HRTIM_CLKSOURCE_TIM (uint32_t)(0x00000000U) /* HRTIM Clock source is same as other timers */
1403 #define LL_RCC_HRTIM_CLKSOURCE_CPU (uint32_t)(RCC_CFGR_HRTIMSEL) /* HRTIM Clock source is the CPU clock */
1404 /**
1405 * @}
1406 */
1407 #endif /* HRTIM1 */
1408
1409 /** @defgroup RCC_LL_EC_PLLSOURCE All PLLs entry clock source
1410 * @{
1411 */
1412 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCKSELR_PLLSRC_HSI
1413 #define LL_RCC_PLLSOURCE_CSI RCC_PLLCKSELR_PLLSRC_CSI
1414 #define LL_RCC_PLLSOURCE_HSE RCC_PLLCKSELR_PLLSRC_HSE
1415 #define LL_RCC_PLLSOURCE_NONE RCC_PLLCKSELR_PLLSRC_NONE
1416 /**
1417 * @}
1418 */
1419
1420 /** @defgroup RCC_LL_EC_PLLINPUTRANGE All PLLs input range
1421 * @{
1422 */
1423 #define LL_RCC_PLLINPUTRANGE_1_2 (uint32_t)(0x00000000U)
1424 #define LL_RCC_PLLINPUTRANGE_2_4 (uint32_t)(0x00000001)
1425 #define LL_RCC_PLLINPUTRANGE_4_8 (uint32_t)(0x00000002)
1426 #define LL_RCC_PLLINPUTRANGE_8_16 (uint32_t)(0x00000003)
1427 /**
1428 * @}
1429 */
1430
1431 /** @defgroup RCC_LL_EC_PLLVCORANGE All PLLs VCO range
1432 * @{
1433 */
1434 #define LL_RCC_PLLVCORANGE_WIDE (uint32_t)(0x00000000U) /* VCO output range: 192 to 836 MHz OR 128 to 544 MHz (*) */
1435 #define LL_RCC_PLLVCORANGE_MEDIUM (uint32_t)(0x00000001) /* VCO output range: 150 to 420 MHz */
1436 /**
1437 * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
1438 * @}
1439 */
1440
1441 /**
1442 * @}
1443 */
1444
1445 /* Exported macro ------------------------------------------------------------*/
1446 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
1447 * @{
1448 */
1449
1450 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
1451 * @{
1452 */
1453
1454 /**
1455 * @brief Write a value in RCC register
1456 * @param __REG__ Register to be written
1457 * @param __VALUE__ Value to be written in the register
1458 * @retval None
1459 */
1460 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
1461
1462 /**
1463 * @brief Read a value in RCC register
1464 * @param __REG__ Register to be read
1465 * @retval Register value
1466 */
1467 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
1468 /**
1469 * @}
1470 */
1471
1472 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
1473 * @{
1474 */
1475
1476 /**
1477 * @brief Helper macro to calculate the SYSCLK frequency
1478 * @param __SYSINPUTCLKFREQ__ Frequency of the input of sys_ck (based on HSE/CSI/HSI/PLL1P)
1479 * @param __SYSPRESCALER__ This parameter can be one of the following values:
1480 * @arg @ref LL_RCC_SYSCLK_DIV_1
1481 * @arg @ref LL_RCC_SYSCLK_DIV_2
1482 * @arg @ref LL_RCC_SYSCLK_DIV_4
1483 * @arg @ref LL_RCC_SYSCLK_DIV_8
1484 * @arg @ref LL_RCC_SYSCLK_DIV_16
1485 * @arg @ref LL_RCC_SYSCLK_DIV_64
1486 * @arg @ref LL_RCC_SYSCLK_DIV_128
1487 * @arg @ref LL_RCC_SYSCLK_DIV_256
1488 * @arg @ref LL_RCC_SYSCLK_DIV_512
1489 * @retval SYSCLK clock frequency (in Hz)
1490 */
1491 #if defined(RCC_D1CFGR_D1CPRE)
1492 #define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU))
1493 #else
1494 #define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU))
1495 #endif /* RCC_D1CFGR_D1CPRE */
1496
1497 /**
1498 * @brief Helper macro to calculate the HCLK frequency
1499 * @param __SYSCLKFREQ__ SYSCLK frequency.
1500 * @param __HPRESCALER__ This parameter can be one of the following values:
1501 * @arg @ref LL_RCC_AHB_DIV_1
1502 * @arg @ref LL_RCC_AHB_DIV_2
1503 * @arg @ref LL_RCC_AHB_DIV_4
1504 * @arg @ref LL_RCC_AHB_DIV_8
1505 * @arg @ref LL_RCC_AHB_DIV_16
1506 * @arg @ref LL_RCC_AHB_DIV_64
1507 * @arg @ref LL_RCC_AHB_DIV_128
1508 * @arg @ref LL_RCC_AHB_DIV_256
1509 * @arg @ref LL_RCC_AHB_DIV_512
1510 * @retval HCLK clock frequency (in Hz)
1511 */
1512 #if defined(RCC_D1CFGR_HPRE)
1513 #define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU))
1514 #else
1515 #define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU))
1516 #endif /* RCC_D1CFGR_HPRE */
1517
1518 /**
1519 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
1520 * @param __HCLKFREQ__ HCLK frequency
1521 * @param __APB1PRESCALER__ This parameter can be one of the following values:
1522 * @arg @ref LL_RCC_APB1_DIV_1
1523 * @arg @ref LL_RCC_APB1_DIV_2
1524 * @arg @ref LL_RCC_APB1_DIV_4
1525 * @arg @ref LL_RCC_APB1_DIV_8
1526 * @arg @ref LL_RCC_APB1_DIV_16
1527 * @retval PCLK1 clock frequency (in Hz)
1528 */
1529 #if defined(RCC_D2CFGR_D2PPRE1)
1530 #define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU))
1531 #else
1532 #define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU))
1533 #endif /* RCC_D2CFGR_D2PPRE1 */
1534
1535 /**
1536 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
1537 * @param __HCLKFREQ__ HCLK frequency
1538 * @param __APB2PRESCALER__ This parameter can be one of the following values:
1539 * @arg @ref LL_RCC_APB2_DIV_1
1540 * @arg @ref LL_RCC_APB2_DIV_2
1541 * @arg @ref LL_RCC_APB2_DIV_4
1542 * @arg @ref LL_RCC_APB2_DIV_8
1543 * @arg @ref LL_RCC_APB2_DIV_16
1544 * @retval PCLK2 clock frequency (in Hz)
1545 */
1546 #if defined(RCC_D2CFGR_D2PPRE2)
1547 #define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU))
1548 #else
1549 #define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU))
1550 #endif /* RCC_D2CFGR_D2PPRE2 */
1551
1552 /**
1553 * @brief Helper macro to calculate the PCLK3 frequency (APB3)
1554 * @param __HCLKFREQ__ HCLK frequency
1555 * @param __APB3PRESCALER__ This parameter can be one of the following values:
1556 * @arg @ref LL_RCC_APB3_DIV_1
1557 * @arg @ref LL_RCC_APB3_DIV_2
1558 * @arg @ref LL_RCC_APB3_DIV_4
1559 * @arg @ref LL_RCC_APB3_DIV_8
1560 * @arg @ref LL_RCC_APB3_DIV_16
1561 * @retval PCLK1 clock frequency (in Hz)
1562 */
1563 #if defined(RCC_D1CFGR_D1PPRE)
1564 #define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_D1CFGR_D1PPRE) >> RCC_D1CFGR_D1PPRE_Pos]) & 0x1FU))
1565 #else
1566 #define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_CDCFGR1_CDPPRE) >> RCC_CDCFGR1_CDPPRE_Pos]) & 0x1FU))
1567 #endif /* RCC_D1CFGR_D1PPRE */
1568
1569 /**
1570 * @brief Helper macro to calculate the PCLK4 frequency (ABP4)
1571 * @param __HCLKFREQ__ HCLK frequency
1572 * @param __APB4PRESCALER__ This parameter can be one of the following values:
1573 * @arg @ref LL_RCC_APB4_DIV_1
1574 * @arg @ref LL_RCC_APB4_DIV_2
1575 * @arg @ref LL_RCC_APB4_DIV_4
1576 * @arg @ref LL_RCC_APB4_DIV_8
1577 * @arg @ref LL_RCC_APB4_DIV_16
1578 * @retval PCLK1 clock frequency (in Hz)
1579 */
1580 #if defined(RCC_D3CFGR_D3PPRE)
1581 #define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos]) & 0x1FU))
1582 #else
1583 #define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos]) & 0x1FU))
1584 #endif /* RCC_D3CFGR_D3PPRE */
1585
1586 /**
1587 * @}
1588 */
1589
1590 #if defined(USE_FULL_LL_DRIVER)
1591 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
1592 * @{
1593 */
1594 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
1595 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
1596 /**
1597 * @}
1598 */
1599 #endif /* USE_FULL_LL_DRIVER */
1600
1601 /**
1602 * @}
1603 */
1604
1605 /* Exported functions --------------------------------------------------------*/
1606 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
1607 * @{
1608 */
1609
1610 /** @defgroup RCC_LL_EF_HSE HSE
1611 * @{
1612 */
1613
1614 /**
1615 * @brief Enable the Clock Security System.
1616 * @note Once HSE Clock Security System is enabled it cannot be changed anymore unless
1617 * a reset occurs or system enter in standby mode.
1618 * @rmtoll CR CSSHSEON LL_RCC_HSE_EnableCSS
1619 * @retval None
1620 */
1621 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
1622 {
1623 SET_BIT(RCC->CR, RCC_CR_CSSHSEON);
1624 }
1625
1626 /**
1627 * @brief Enable HSE external oscillator (HSE Bypass)
1628 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
1629 * @retval None
1630 */
1631 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
1632 {
1633 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
1634 }
1635
1636 /**
1637 * @brief Disable HSE external oscillator (HSE Bypass)
1638 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
1639 * @retval None
1640 */
1641 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
1642 {
1643 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
1644 }
1645
1646 #if defined(RCC_CR_HSEEXT)
1647 /**
1648 * @brief Select the Analog HSE external clock type in Bypass mode
1649 * @rmtoll CR HSEEXT LL_RCC_HSE_SelectAnalogClock
1650 * @retval None
1651 */
1652 __STATIC_INLINE void LL_RCC_HSE_SelectAnalogClock(void)
1653 {
1654 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);
1655 }
1656
1657 /**
1658 * @brief Select the Digital HSE external clock type in Bypass mode
1659 * @rmtoll CR HSEEXT LL_RCC_HSE_SelectDigitalClock
1660 * @retval None
1661 */
1662 __STATIC_INLINE void LL_RCC_HSE_SelectDigitalClock(void)
1663 {
1664 SET_BIT(RCC->CR, RCC_CR_HSEEXT);
1665 }
1666 #endif /* RCC_CR_HSEEXT */
1667
1668 /**
1669 * @brief Enable HSE crystal oscillator (HSE ON)
1670 * @rmtoll CR HSEON LL_RCC_HSE_Enable
1671 * @retval None
1672 */
1673 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
1674 {
1675 SET_BIT(RCC->CR, RCC_CR_HSEON);
1676 }
1677
1678 /**
1679 * @brief Disable HSE crystal oscillator (HSE ON)
1680 * @rmtoll CR HSEON LL_RCC_HSE_Disable
1681 * @retval None
1682 */
1683 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
1684 {
1685 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
1686 }
1687
1688 /**
1689 * @brief Check if HSE oscillator Ready
1690 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
1691 * @retval State of bit (1 or 0).
1692 */
1693 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
1694 {
1695 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY))?1UL:0UL);
1696 }
1697
1698 /**
1699 * @}
1700 */
1701
1702 /** @defgroup RCC_LL_EF_HSI HSI
1703 * @{
1704 */
1705
1706 /**
1707 * @brief Enable HSI oscillator
1708 * @rmtoll CR HSION LL_RCC_HSI_Enable
1709 * @retval None
1710 */
1711 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
1712 {
1713 SET_BIT(RCC->CR, RCC_CR_HSION);
1714 }
1715
1716 /**
1717 * @brief Disable HSI oscillator
1718 * @rmtoll CR HSION LL_RCC_HSI_Disable
1719 * @retval None
1720 */
1721 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
1722 {
1723 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
1724 }
1725
1726 /**
1727 * @brief Check if HSI clock is ready
1728 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
1729 * @retval State of bit (1 or 0).
1730 */
1731 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
1732 {
1733 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY))?1UL:0UL);
1734 }
1735
1736 /**
1737 * @brief Check if HSI new divider applied and ready
1738 * @rmtoll CR HSIDIVF LL_RCC_HSI_IsDividerReady
1739 * @retval State of bit (1 or 0).
1740 */
1741 __STATIC_INLINE uint32_t LL_RCC_HSI_IsDividerReady(void)
1742 {
1743 return ((READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == (RCC_CR_HSIDIVF))?1UL:0UL);
1744 }
1745
1746 /**
1747 * @brief Set HSI divider
1748 * @rmtoll CR HSIDIV LL_RCC_HSI_SetDivider
1749 * @param Divider This parameter can be one of the following values:
1750 * @arg @ref LL_RCC_HSI_DIV1
1751 * @arg @ref LL_RCC_HSI_DIV2
1752 * @arg @ref LL_RCC_HSI_DIV4
1753 * @arg @ref LL_RCC_HSI_DIV8
1754 * @retval None.
1755 */
1756 __STATIC_INLINE void LL_RCC_HSI_SetDivider(uint32_t Divider)
1757 {
1758 MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, Divider);
1759 }
1760
1761 /**
1762 * @brief Get HSI divider
1763 * @rmtoll CR HSIDIV LL_RCC_HSI_GetDivider
1764 * @retval can be one of the following values:
1765 * @arg @ref LL_RCC_HSI_DIV1
1766 * @arg @ref LL_RCC_HSI_DIV2
1767 * @arg @ref LL_RCC_HSI_DIV4
1768 * @arg @ref LL_RCC_HSI_DIV8
1769 */
1770 __STATIC_INLINE uint32_t LL_RCC_HSI_GetDivider(void)
1771 {
1772 return (READ_BIT(RCC->CR, RCC_CR_HSIDIV));
1773 }
1774
1775 /**
1776 * @brief Enable HSI oscillator in Stop mode
1777 * @rmtoll CR HSIKERON LL_RCC_HSI_EnableStopMode
1778 * @retval None
1779 */
1780 __STATIC_INLINE void LL_RCC_HSI_EnableStopMode(void)
1781 {
1782 SET_BIT(RCC->CR, RCC_CR_HSIKERON);
1783 }
1784
1785 /**
1786 * @brief Disable HSI oscillator in Stop mode
1787 * @rmtoll CR HSION LL_RCC_HSI_DisableStopMode
1788 * @retval None
1789 */
1790 __STATIC_INLINE void LL_RCC_HSI_DisableStopMode(void)
1791 {
1792 CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
1793 }
1794
1795 /**
1796 * @brief Get HSI Calibration value
1797 * @note When HSITRIM is written, HSICAL is updated with the sum of
1798 * HSITRIM and the factory trim value
1799 * @rmtoll HSICFGR HSICAL LL_RCC_HSI_GetCalibration
1800 * @retval A value between 0 and 4095 (0xFFF)
1801 */
1802 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
1803 {
1804 return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSICAL) >> RCC_HSICFGR_HSICAL_Pos);
1805 }
1806
1807 /**
1808 * @brief Set HSI Calibration trimming
1809 * @note user-programmable trimming value that is added to the HSICAL
1810 * @note Default value is 64 (32 for Cut1.x), which, when added to the HSICAL value,
1811 * should trim the HSI to 64 MHz +/- 1 %
1812 * @rmtoll HSICFGR HSITRIM LL_RCC_HSI_SetCalibTrimming
1813 * @param Value can be a value between 0 and 127 (63 for Cut1.x)
1814 * @retval None
1815 */
1816 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
1817 {
1818 #if defined(RCC_VER_X)
1819 if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
1820 {
1821 /* STM32H7 Rev.Y */
1822 MODIFY_REG(RCC->HSICFGR, 0x3F000U, Value << 12U);
1823 }
1824 else
1825 {
1826 /* STM32H7 Rev.V */
1827 MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos);
1828 }
1829 #else
1830 MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos);
1831 #endif /* RCC_VER_X */
1832 }
1833
1834 /**
1835 * @brief Get HSI Calibration trimming
1836 * @rmtoll HSICFGR HSITRIM LL_RCC_HSI_GetCalibTrimming
1837 * @retval A value between 0 and 127 (63 for Cut1.x)
1838 */
1839 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
1840 {
1841 #if defined(RCC_VER_X)
1842 if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
1843 {
1844 /* STM32H7 Rev.Y */
1845 return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x3F000U) >> 12U);
1846 }
1847 else
1848 {
1849 /* STM32H7 Rev.V */
1850 return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
1851 }
1852 #else
1853 return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
1854 #endif /* RCC_VER_X */
1855 }
1856
1857 /**
1858 * @}
1859 */
1860
1861 /** @defgroup RCC_LL_EF_CSI CSI
1862 * @{
1863 */
1864
1865 /**
1866 * @brief Enable CSI oscillator
1867 * @rmtoll CR CSION LL_RCC_CSI_Enable
1868 * @retval None
1869 */
1870 __STATIC_INLINE void LL_RCC_CSI_Enable(void)
1871 {
1872 SET_BIT(RCC->CR, RCC_CR_CSION);
1873 }
1874
1875 /**
1876 * @brief Disable CSI oscillator
1877 * @rmtoll CR CSION LL_RCC_CSI_Disable
1878 * @retval None
1879 */
1880 __STATIC_INLINE void LL_RCC_CSI_Disable(void)
1881 {
1882 CLEAR_BIT(RCC->CR, RCC_CR_CSION);
1883 }
1884
1885 /**
1886 * @brief Check if CSI clock is ready
1887 * @rmtoll CR CSIRDY LL_RCC_CSI_IsReady
1888 * @retval State of bit (1 or 0).
1889 */
1890 __STATIC_INLINE uint32_t LL_RCC_CSI_IsReady(void)
1891 {
1892 return ((READ_BIT(RCC->CR, RCC_CR_CSIRDY) == (RCC_CR_CSIRDY))?1UL:0UL);
1893 }
1894
1895 /**
1896 * @brief Enable CSI oscillator in Stop mode
1897 * @rmtoll CR CSIKERON LL_RCC_CSI_EnableStopMode
1898 * @retval None
1899 */
1900 __STATIC_INLINE void LL_RCC_CSI_EnableStopMode(void)
1901 {
1902 SET_BIT(RCC->CR, RCC_CR_CSIKERON);
1903 }
1904
1905 /**
1906 * @brief Disable CSI oscillator in Stop mode
1907 * @rmtoll CR CSIKERON LL_RCC_CSI_DisableStopMode
1908 * @retval None
1909 */
1910 __STATIC_INLINE void LL_RCC_CSI_DisableStopMode(void)
1911 {
1912 CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON);
1913 }
1914
1915 /**
1916 * @brief Get CSI Calibration value
1917 * @note When CSITRIM is written, CSICAL is updated with the sum of
1918 * CSITRIM and the factory trim value
1919 * @rmtoll CSICFGR CSICAL LL_RCC_CSI_GetCalibration
1920 * @retval A value between 0 and 255 (0xFF)
1921 */
1922 __STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibration(void)
1923 {
1924 #if defined(RCC_VER_X)
1925 if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
1926 {
1927 /* STM32H7 Rev.Y */
1928 return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x3FC0000U) >> 18U);
1929 }
1930 else
1931 {
1932 /* STM32H7 Rev.V */
1933 return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos);
1934 }
1935 #else
1936 return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos);
1937 #endif /* RCC_VER_X */
1938 }
1939
1940 /**
1941 * @brief Set CSI Calibration trimming
1942 * @note user-programmable trimming value that is added to the CSICAL
1943 * @note Default value is 16, which, when added to the CSICAL value,
1944 * should trim the CSI to 4 MHz +/- 1 %
1945 * @rmtoll CSICFGR CSITRIM LL_RCC_CSI_SetCalibTrimming
1946 * @param Value can be a value between 0 and 31
1947 * @retval None
1948 */
1949 __STATIC_INLINE void LL_RCC_CSI_SetCalibTrimming(uint32_t Value)
1950 {
1951 #if defined(RCC_VER_X)
1952 if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
1953 {
1954 /* STM32H7 Rev.Y */
1955 MODIFY_REG(RCC->HSICFGR, 0x7C000000U, Value << 26U);
1956 }
1957 else
1958 {
1959 /* STM32H7 Rev.V */
1960 MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos);
1961 }
1962 #else
1963 MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos);
1964 #endif /* RCC_VER_X */
1965 }
1966
1967 /**
1968 * @brief Get CSI Calibration trimming
1969 * @rmtoll CSICFGR CSITRIM LL_RCC_CSI_GetCalibTrimming
1970 * @retval A value between 0 and 31
1971 */
1972 __STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibTrimming(void)
1973 {
1974 #if defined(RCC_VER_X)
1975 if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
1976 {
1977 /* STM32H7 Rev.Y */
1978 return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x7C000000U) >> 26U);
1979 }
1980 else
1981 {
1982 /* STM32H7 Rev.V */
1983 return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
1984 }
1985 #else
1986 return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
1987 #endif /* RCC_VER_X */
1988 }
1989
1990 /**
1991 * @}
1992 */
1993
1994 /** @defgroup RCC_LL_EF_HSI48 HSI48
1995 * @{
1996 */
1997
1998 /**
1999 * @brief Enable HSI48 oscillator
2000 * @rmtoll CR HSI48ON LL_RCC_HSI48_Enable
2001 * @retval None
2002 */
2003 __STATIC_INLINE void LL_RCC_HSI48_Enable(void)
2004 {
2005 SET_BIT(RCC->CR, RCC_CR_HSI48ON);
2006 }
2007
2008 /**
2009 * @brief Disable HSI48 oscillator
2010 * @rmtoll CR HSI48ON LL_RCC_HSI48_Disable
2011 * @retval None
2012 */
2013 __STATIC_INLINE void LL_RCC_HSI48_Disable(void)
2014 {
2015 CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
2016 }
2017
2018 /**
2019 * @brief Check if HSI48 clock is ready
2020 * @rmtoll CR HSI48RDY LL_RCC_HSI48_IsReady
2021 * @retval State of bit (1 or 0).
2022 */
2023 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
2024 {
2025 return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == (RCC_CR_HSI48RDY))?1UL:0UL);
2026 }
2027
2028 /**
2029 * @brief Get HSI48 Calibration value
2030 * @note When HSI48TRIM is written, HSI48CAL is updated with the sum of
2031 * HSI48TRIM and the factory trim value
2032 * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
2033 * @retval A value between 0 and 1023 (0x3FF)
2034 */
2035 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
2036 {
2037 return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
2038 }
2039 /**
2040 * @}
2041 */
2042
2043 #if defined(RCC_CR_D1CKRDY)
2044
2045 /** @defgroup RCC_LL_EF_D1CLK D1CKREADY
2046 * @{
2047 */
2048
2049 /**
2050 * @brief Check if D1 clock is ready
2051 * @rmtoll CR D1CKRDY LL_RCC_D1CK_IsReady
2052 * @retval State of bit (1 or 0).
2053 */
2054 __STATIC_INLINE uint32_t LL_RCC_D1CK_IsReady(void)
2055 {
2056 return ((READ_BIT(RCC->CR, RCC_CR_D1CKRDY) == (RCC_CR_D1CKRDY))?1UL:0UL);
2057 }
2058
2059 /**
2060 * @}
2061 */
2062 #else
2063
2064 /** @defgroup RCC_LL_EF_CPUCLK CPUCKREADY
2065 * @{
2066 */
2067
2068 /**
2069 * @brief Check if CPU clock is ready
2070 * @rmtoll CR CPUCKRDY LL_RCC_CPUCK_IsReady
2071 * @retval State of bit (1 or 0).
2072 */
2073 __STATIC_INLINE uint32_t LL_RCC_CPUCK_IsReady(void)
2074 {
2075 return ((READ_BIT(RCC->CR, RCC_CR_CPUCKRDY) == (RCC_CR_CPUCKRDY))?1UL:0UL);
2076 }
2077 /* alias */
2078 #define LL_RCC_D1CK_IsReady LL_RCC_CPUCK_IsReady
2079 /**
2080 * @}
2081 */
2082 #endif /* RCC_CR_D1CKRDY */
2083
2084 #if defined(RCC_CR_D2CKRDY)
2085
2086 /** @defgroup RCC_LL_EF_D2CLK D2CKREADY
2087 * @{
2088 */
2089
2090 /**
2091 * @brief Check if D2 clock is ready
2092 * @rmtoll CR D2CKRDY LL_RCC_D2CK_IsReady
2093 * @retval State of bit (1 or 0).
2094 */
2095 __STATIC_INLINE uint32_t LL_RCC_D2CK_IsReady(void)
2096 {
2097 return ((READ_BIT(RCC->CR, RCC_CR_D2CKRDY) == (RCC_CR_D2CKRDY))?1UL:0UL);
2098 }
2099 /**
2100 * @}
2101 */
2102 #else
2103
2104 /** @defgroup RCC_LL_EF_CDCLK CDCKREADY
2105 * @{
2106 */
2107
2108 /**
2109 * @brief Check if CD clock is ready
2110 * @rmtoll CR CDCKRDY LL_RCC_CDCK_IsReady
2111 * @retval State of bit (1 or 0).
2112 */
2113 __STATIC_INLINE uint32_t LL_RCC_CDCK_IsReady(void)
2114 {
2115 return ((READ_BIT(RCC->CR, RCC_CR_CDCKRDY) == (RCC_CR_CDCKRDY))?1UL:0UL);
2116 }
2117 #define LL_RCC_D2CK_IsReady LL_RCC_CDCK_IsReady
2118 /**
2119 * @}
2120 */
2121 #endif /* RCC_CR_D2CKRDY */
2122
2123 /** @defgroup RCC_LL_EF_SYSTEM_WIDE_RESET RESET
2124 * @{
2125 */
2126 #if defined(RCC_GCR_WW1RSC)
2127
2128 /**
2129 * @brief Enable system wide reset for Window Watch Dog 1
2130 * @rmtoll GCR WW1RSC LL_RCC_WWDG1_EnableSystemReset
2131 * @retval None.
2132 */
2133 __STATIC_INLINE void LL_RCC_WWDG1_EnableSystemReset(void)
2134 {
2135 SET_BIT(RCC->GCR, RCC_GCR_WW1RSC);
2136 }
2137
2138 /**
2139 * @brief Check if Window Watch Dog 1 reset is system wide
2140 * @rmtoll GCR WW1RSC LL_RCC_WWDG1_IsSystemReset
2141 * @retval State of bit (1 or 0).
2142 */
2143 __STATIC_INLINE uint32_t LL_RCC_WWDG1_IsSystemReset(void)
2144 {
2145 return ((READ_BIT(RCC->GCR, RCC_GCR_WW1RSC) == RCC_GCR_WW1RSC)?1UL:0UL);
2146 }
2147 #endif /* RCC_GCR_WW1RSC */
2148
2149 #if defined(DUAL_CORE)
2150 /**
2151 * @brief Enable system wide reset for Window Watch Dog 2
2152 * @rmtoll GCR WW1RSC LL_RCC_WWDG2_EnableSystemReset
2153 * @retval None.
2154 */
2155 __STATIC_INLINE void LL_RCC_WWDG2_EnableSystemReset(void)
2156 {
2157 SET_BIT(RCC->GCR, RCC_GCR_WW2RSC);
2158 }
2159
2160 /**
2161 * @brief Check if Window Watch Dog 2 reset is system wide
2162 * @rmtoll GCR WW2RSC LL_RCC_WWDG2_IsSystemReset
2163 * @retval State of bit (1 or 0).
2164 */
2165 __STATIC_INLINE uint32_t LL_RCC_WWDG2_IsSystemReset(void)
2166 {
2167 return ((READ_BIT(RCC->GCR, RCC_GCR_WW2RSC) == RCC_GCR_WW2RSC)?1UL:0UL);
2168 }
2169 #endif /*DUAL_CORE*/
2170 /**
2171 * @}
2172 */
2173
2174 #if defined(DUAL_CORE)
2175 /** @defgroup RCC_LL_EF_BOOT_CPU CPU
2176 * @{
2177 */
2178
2179 /**
2180 * @brief Force CM4 boot (if hold by option byte BCM4 = 0)
2181 * @rmtoll GCR BOOT_C2 LL_RCC_ForceCM4Boot
2182 * @retval None.
2183 */
2184 __STATIC_INLINE void LL_RCC_ForceCM4Boot(void)
2185 {
2186 SET_BIT(RCC->GCR, RCC_GCR_BOOT_C2);
2187 }
2188
2189 /**
2190 * @brief Check if CM4 boot is forced
2191 * @rmtoll GCR BOOT_C2 LL_RCC_IsCM4BootForced
2192 * @retval State of bit (1 or 0).
2193 */
2194 __STATIC_INLINE uint32_t LL_RCC_IsCM4BootForced(void)
2195 {
2196 return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C2) == RCC_GCR_BOOT_C2)?1UL:0UL);
2197 }
2198
2199 /**
2200 * @brief Force CM7 boot (if hold by option byte BCM7 = 0)
2201 * @rmtoll GCR BOOT_C1 LL_RCC_ForceCM7Boot
2202 * @retval None.
2203 */
2204 __STATIC_INLINE void LL_RCC_ForceCM7Boot(void)
2205 {
2206 SET_BIT(RCC->GCR, RCC_GCR_BOOT_C1);
2207 }
2208
2209 /**
2210 * @brief Check if CM7 boot is forced
2211 * @rmtoll GCR BOOT_C1 LL_RCC_IsCM7BootForced
2212 * @retval State of bit (1 or 0).
2213 */
2214 __STATIC_INLINE uint32_t LL_RCC_IsCM7BootForced(void)
2215 {
2216 return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C1) == RCC_GCR_BOOT_C1)?1UL:0UL);
2217 }
2218
2219 /**
2220 * @}
2221 */
2222 #endif /*DUAL_CORE*/
2223
2224 /** @defgroup RCC_LL_EF_LSE LSE
2225 * @{
2226 */
2227
2228 /**
2229 * @brief Enable the Clock Security System on LSE.
2230 * @note Once LSE Clock Security System is enabled it cannot be changed anymore unless
2231 * a clock failure is detected.
2232 * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
2233 * @retval None
2234 */
2235 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
2236 {
2237 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
2238 }
2239
2240 /**
2241 * @brief Check if LSE failure is detected by Clock Security System
2242 * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsFailureDetected
2243 * @retval State of bit (1 or 0).
2244 */
2245 __STATIC_INLINE uint32_t LL_RCC_LSE_IsFailureDetected(void)
2246 {
2247 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD))?1UL:0UL);
2248 }
2249
2250 /**
2251 * @brief Enable Low Speed External (LSE) crystal.
2252 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
2253 * @retval None
2254 */
2255 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
2256 {
2257 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
2258 }
2259
2260 /**
2261 * @brief Disable Low Speed External (LSE) crystal.
2262 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
2263 * @retval None
2264 */
2265 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
2266 {
2267 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
2268 }
2269
2270 /**
2271 * @brief Enable external clock source (LSE bypass).
2272 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
2273 * @retval None
2274 */
2275 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
2276 {
2277 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
2278 }
2279
2280 /**
2281 * @brief Disable external clock source (LSE bypass).
2282 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
2283 * @retval None
2284 */
2285 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
2286 {
2287 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
2288 }
2289
2290 #if defined(RCC_BDCR_LSEEXT)
2291 /**
2292 * @brief Enable Low-speed external DIGITAL clock type in Bypass mode (not to be used if RTC is active).
2293 * @note The external clock must be enabled with the LSEON bit, to be used by the device.
2294 * The LSEEXT bit can be written only if the LSE oscillator is disabled.
2295 * @rmtoll BDCR LSEEXT LL_RCC_LSE_SelectDigitalClock
2296 * @retval None
2297 */
2298 __STATIC_INLINE void LL_RCC_LSE_SelectDigitalClock(void)
2299 {
2300 SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);
2301 }
2302
2303 /**
2304 * @brief Enable Low-speed external ANALOG clock type in Bypass mode (default after Backup domain reset).
2305 * @note The external clock must be enabled with the LSEON bit, to be used by the device.
2306 * The LSEEXT bit can be written only if the LSE oscillator is disabled.
2307 * @rmtoll BDCR LSEEXT LL_RCC_LSE_SelectAnalogClock
2308 * @retval None
2309 */
2310 __STATIC_INLINE void LL_RCC_LSE_SelectAnalogClock(void)
2311 {
2312 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);
2313 }
2314 #endif /* RCC_BDCR_LSEEXT */
2315
2316 /**
2317 * @brief Set LSE oscillator drive capability
2318 * @note The oscillator is in Xtal mode when it is not in bypass mode.
2319 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
2320 * @param LSEDrive This parameter can be one of the following values:
2321 * @arg @ref LL_RCC_LSEDRIVE_LOW
2322 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
2323 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
2324 * @arg @ref LL_RCC_LSEDRIVE_HIGH
2325 * @retval None
2326 */
2327 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
2328 {
2329 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
2330 }
2331
2332 /**
2333 * @brief Get LSE oscillator drive capability
2334 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
2335 * @retval Returned value can be one of the following values:
2336 * @arg @ref LL_RCC_LSEDRIVE_LOW
2337 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
2338 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
2339 * @arg @ref LL_RCC_LSEDRIVE_HIGH
2340 */
2341 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
2342 {
2343 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
2344 }
2345
2346 /**
2347 * @brief Check if LSE oscillator Ready
2348 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
2349 * @retval State of bit (1 or 0).
2350 */
2351 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
2352 {
2353 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY))?1UL:0UL);
2354 }
2355
2356 /**
2357 * @}
2358 */
2359
2360 /** @defgroup RCC_LL_EF_LSI LSI
2361 * @{
2362 */
2363
2364 /**
2365 * @brief Enable LSI Oscillator
2366 * @rmtoll CSR LSION LL_RCC_LSI_Enable
2367 * @retval None
2368 */
2369 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
2370 {
2371 SET_BIT(RCC->CSR, RCC_CSR_LSION);
2372 }
2373
2374 /**
2375 * @brief Disable LSI Oscillator
2376 * @rmtoll CSR LSION LL_RCC_LSI_Disable
2377 * @retval None
2378 */
2379 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
2380 {
2381 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
2382 }
2383
2384 /**
2385 * @brief Check if LSI is Ready
2386 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
2387 * @retval State of bit (1 or 0).
2388 */
2389 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
2390 {
2391 return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY))?1UL:0UL);
2392 }
2393
2394 /**
2395 * @}
2396 */
2397
2398 /** @defgroup RCC_LL_EF_System System
2399 * @{
2400 */
2401
2402 /**
2403 * @brief Configure the system clock source
2404 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
2405 * @param Source This parameter can be one of the following values:
2406 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
2407 * @arg @ref LL_RCC_SYS_CLKSOURCE_CSI
2408 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
2409 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL1
2410 * @retval None
2411 */
2412 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
2413 {
2414 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
2415 }
2416
2417 /**
2418 * @brief Get the system clock source
2419 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
2420 * @retval Returned value can be one of the following values:
2421 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
2422 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_CSI
2423 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
2424 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL1
2425 */
2426 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
2427 {
2428 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
2429 }
2430
2431 /**
2432 * @brief Configure the system wakeup clock source
2433 * @rmtoll CFGR STOPWUCK LL_RCC_SetSysWakeUpClkSource
2434 * @param Source This parameter can be one of the following values:
2435 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
2436 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI
2437 * @retval None
2438 */
2439 __STATIC_INLINE void LL_RCC_SetSysWakeUpClkSource(uint32_t Source)
2440 {
2441 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Source);
2442 }
2443
2444 /**
2445 * @brief Get the system wakeup clock source
2446 * @rmtoll CFGR STOPWUCK LL_RCC_GetSysWakeUpClkSource
2447 * @retval Returned value can be one of the following values:
2448 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
2449 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI
2450 */
2451 __STATIC_INLINE uint32_t LL_RCC_GetSysWakeUpClkSource(void)
2452 {
2453 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
2454 }
2455
2456 /**
2457 * @brief Configure the kernel wakeup clock source
2458 * @rmtoll CFGR STOPKERWUCK LL_RCC_SetKerWakeUpClkSource
2459 * @param Source This parameter can be one of the following values:
2460 * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI
2461 * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI
2462 * @retval None
2463 */
2464 __STATIC_INLINE void LL_RCC_SetKerWakeUpClkSource(uint32_t Source)
2465 {
2466 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, Source);
2467 }
2468
2469 /**
2470 * @brief Get the kernel wakeup clock source
2471 * @rmtoll CFGR STOPKERWUCK LL_RCC_GetKerWakeUpClkSource
2472 * @retval Returned value can be one of the following values:
2473 * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI
2474 * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI
2475 */
2476 __STATIC_INLINE uint32_t LL_RCC_GetKerWakeUpClkSource(void)
2477 {
2478 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPKERWUCK));
2479 }
2480
2481 /**
2482 * @brief Set System prescaler
2483 * @rmtoll D1CFGR/CDCFGR1 D1CPRE/CDCPRE LL_RCC_SetSysPrescaler
2484 * @param Prescaler This parameter can be one of the following values:
2485 * @arg @ref LL_RCC_SYSCLK_DIV_1
2486 * @arg @ref LL_RCC_SYSCLK_DIV_2
2487 * @arg @ref LL_RCC_SYSCLK_DIV_4
2488 * @arg @ref LL_RCC_SYSCLK_DIV_8
2489 * @arg @ref LL_RCC_SYSCLK_DIV_16
2490 * @arg @ref LL_RCC_SYSCLK_DIV_64
2491 * @arg @ref LL_RCC_SYSCLK_DIV_128
2492 * @arg @ref LL_RCC_SYSCLK_DIV_256
2493 * @arg @ref LL_RCC_SYSCLK_DIV_512
2494 * @retval None
2495 */
2496 __STATIC_INLINE void LL_RCC_SetSysPrescaler(uint32_t Prescaler)
2497 {
2498 #if defined(RCC_D1CFGR_D1CPRE)
2499 MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, Prescaler);
2500 #else
2501 MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, Prescaler);
2502 #endif /* RCC_D1CFGR_D1CPRE */
2503 }
2504
2505 /**
2506 * @brief Set AHB prescaler
2507 * @rmtoll D1CFGR/CDCFGR1 HPRE LL_RCC_SetAHBPrescaler
2508 * @param Prescaler This parameter can be one of the following values:
2509 * @arg @ref LL_RCC_AHB_DIV_1
2510 * @arg @ref LL_RCC_AHB_DIV_2
2511 * @arg @ref LL_RCC_AHB_DIV_4
2512 * @arg @ref LL_RCC_AHB_DIV_8
2513 * @arg @ref LL_RCC_AHB_DIV_16
2514 * @arg @ref LL_RCC_AHB_DIV_64
2515 * @arg @ref LL_RCC_AHB_DIV_128
2516 * @arg @ref LL_RCC_AHB_DIV_256
2517 * @arg @ref LL_RCC_AHB_DIV_512
2518 * @retval None
2519 */
2520 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
2521 {
2522 #if defined(RCC_D1CFGR_HPRE)
2523 MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, Prescaler);
2524 #else
2525 MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, Prescaler);
2526 #endif /* RCC_D1CFGR_HPRE */
2527 }
2528
2529 /**
2530 * @brief Set APB1 prescaler
2531 * @rmtoll D2CFGR/CDCFGR2 D2PPRE1/CDPPRE1 LL_RCC_SetAPB1Prescaler
2532 * @param Prescaler This parameter can be one of the following values:
2533 * @arg @ref LL_RCC_APB1_DIV_1
2534 * @arg @ref LL_RCC_APB1_DIV_2
2535 * @arg @ref LL_RCC_APB1_DIV_4
2536 * @arg @ref LL_RCC_APB1_DIV_8
2537 * @arg @ref LL_RCC_APB1_DIV_16
2538 * @retval None
2539 */
2540 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
2541 {
2542 #if defined(RCC_D2CFGR_D2PPRE1)
2543 MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, Prescaler);
2544 #else
2545 MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, Prescaler);
2546 #endif /* RCC_D2CFGR_D2PPRE1 */
2547 }
2548
2549 /**
2550 * @brief Set APB2 prescaler
2551 * @rmtoll D2CFGR/CDCFGR2 D2PPRE2/CDPPRE2 LL_RCC_SetAPB2Prescaler
2552 * @param Prescaler This parameter can be one of the following values:
2553 * @arg @ref LL_RCC_APB2_DIV_1
2554 * @arg @ref LL_RCC_APB2_DIV_2
2555 * @arg @ref LL_RCC_APB2_DIV_4
2556 * @arg @ref LL_RCC_APB2_DIV_8
2557 * @arg @ref LL_RCC_APB2_DIV_16
2558 * @retval None
2559 */
2560 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
2561 {
2562 #if defined(RCC_D2CFGR_D2PPRE2)
2563 MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, Prescaler);
2564 #else
2565 MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, Prescaler);
2566 #endif /* RCC_D2CFGR_D2PPRE2 */
2567 }
2568
2569 /**
2570 * @brief Set APB3 prescaler
2571 * @rmtoll D1CFGR/CDCFGR1 D1PPRE/CDPPRE LL_RCC_SetAPB3Prescaler
2572 * @param Prescaler This parameter can be one of the following values:
2573 * @arg @ref LL_RCC_APB3_DIV_1
2574 * @arg @ref LL_RCC_APB3_DIV_2
2575 * @arg @ref LL_RCC_APB3_DIV_4
2576 * @arg @ref LL_RCC_APB3_DIV_8
2577 * @arg @ref LL_RCC_APB3_DIV_16
2578 * @retval None
2579 */
2580 __STATIC_INLINE void LL_RCC_SetAPB3Prescaler(uint32_t Prescaler)
2581 {
2582 #if defined(RCC_D1CFGR_D1PPRE)
2583 MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, Prescaler);
2584 #else
2585 MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, Prescaler);
2586 #endif /* RCC_D1CFGR_D1PPRE */
2587 }
2588
2589 /**
2590 * @brief Set APB4 prescaler
2591 * @rmtoll D3CFGR/SRDCFGR D3PPRE/SRDPPRE LL_RCC_SetAPB4Prescaler
2592 * @param Prescaler This parameter can be one of the following values:
2593 * @arg @ref LL_RCC_APB4_DIV_1
2594 * @arg @ref LL_RCC_APB4_DIV_2
2595 * @arg @ref LL_RCC_APB4_DIV_4
2596 * @arg @ref LL_RCC_APB4_DIV_8
2597 * @arg @ref LL_RCC_APB4_DIV_16
2598 * @retval None
2599 */
2600 __STATIC_INLINE void LL_RCC_SetAPB4Prescaler(uint32_t Prescaler)
2601 {
2602 #if defined(RCC_D3CFGR_D3PPRE)
2603 MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, Prescaler);
2604 #else
2605 MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, Prescaler);
2606 #endif /* RCC_D3CFGR_D3PPRE */
2607 }
2608
2609 /**
2610 * @brief Get System prescaler
2611 * @rmtoll D1CFGR/CDCFGR1 D1CPRE/CDCPRE LL_RCC_GetSysPrescaler
2612 * @retval Returned value can be one of the following values:
2613 * @arg @ref LL_RCC_SYSCLK_DIV_1
2614 * @arg @ref LL_RCC_SYSCLK_DIV_2
2615 * @arg @ref LL_RCC_SYSCLK_DIV_4
2616 * @arg @ref LL_RCC_SYSCLK_DIV_8
2617 * @arg @ref LL_RCC_SYSCLK_DIV_16
2618 * @arg @ref LL_RCC_SYSCLK_DIV_64
2619 * @arg @ref LL_RCC_SYSCLK_DIV_128
2620 * @arg @ref LL_RCC_SYSCLK_DIV_256
2621 * @arg @ref LL_RCC_SYSCLK_DIV_512
2622 */
2623 __STATIC_INLINE uint32_t LL_RCC_GetSysPrescaler(void)
2624 {
2625 #if defined(RCC_D1CFGR_D1CPRE)
2626 return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1CPRE));
2627 #else
2628 return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE));
2629 #endif /* RCC_D1CFGR_D1CPRE */
2630 }
2631
2632 /**
2633 * @brief Get AHB prescaler
2634 * @rmtoll D1CFGR/ CDCFGR1 HPRE LL_RCC_GetAHBPrescaler
2635 * @retval Returned value can be one of the following values:
2636 * @arg @ref LL_RCC_AHB_DIV_1
2637 * @arg @ref LL_RCC_AHB_DIV_2
2638 * @arg @ref LL_RCC_AHB_DIV_4
2639 * @arg @ref LL_RCC_AHB_DIV_8
2640 * @arg @ref LL_RCC_AHB_DIV_16
2641 * @arg @ref LL_RCC_AHB_DIV_64
2642 * @arg @ref LL_RCC_AHB_DIV_128
2643 * @arg @ref LL_RCC_AHB_DIV_256
2644 * @arg @ref LL_RCC_AHB_DIV_512
2645 */
2646 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
2647 {
2648 #if defined(RCC_D1CFGR_HPRE)
2649 return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_HPRE));
2650 #else
2651 return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_HPRE));
2652 #endif /* RCC_D1CFGR_HPRE */
2653 }
2654
2655 /**
2656 * @brief Get APB1 prescaler
2657 * @rmtoll D2CFGR/CDCFGR2 D2PPRE1/CDPPRE1 LL_RCC_GetAPB1Prescaler
2658 * @retval Returned value can be one of the following values:
2659 * @arg @ref LL_RCC_APB1_DIV_1
2660 * @arg @ref LL_RCC_APB1_DIV_2
2661 * @arg @ref LL_RCC_APB1_DIV_4
2662 * @arg @ref LL_RCC_APB1_DIV_8
2663 * @arg @ref LL_RCC_APB1_DIV_16
2664 */
2665 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
2666 {
2667 #if defined(RCC_D2CFGR_D2PPRE1)
2668 return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1));
2669 #else
2670 return (uint32_t)(READ_BIT(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1));
2671 #endif /* RCC_D2CFGR_D2PPRE1 */
2672 }
2673
2674 /**
2675 * @brief Get APB2 prescaler
2676 * @rmtoll D2CFGR/CDCFGR2 D2PPRE2/CDPPRE2 LL_RCC_GetAPB2Prescaler
2677 * @retval Returned value can be one of the following values:
2678 * @arg @ref LL_RCC_APB2_DIV_1
2679 * @arg @ref LL_RCC_APB2_DIV_2
2680 * @arg @ref LL_RCC_APB2_DIV_4
2681 * @arg @ref LL_RCC_APB2_DIV_8
2682 * @arg @ref LL_RCC_APB2_DIV_16
2683 */
2684 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
2685 {
2686 #if defined(RCC_D2CFGR_D2PPRE2)
2687 return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2));
2688 #else
2689 return (uint32_t)(READ_BIT(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2));
2690 #endif /* RCC_D2CFGR_D2PPRE2 */
2691 }
2692
2693 /**
2694 * @brief Get APB3 prescaler
2695 * @rmtoll D1CFGR/CDCFGR1 D1PPRE/CDPPRE LL_RCC_GetAPB3Prescaler
2696 * @retval Returned value can be one of the following values:
2697 * @arg @ref LL_RCC_APB3_DIV_1
2698 * @arg @ref LL_RCC_APB3_DIV_2
2699 * @arg @ref LL_RCC_APB3_DIV_4
2700 * @arg @ref LL_RCC_APB3_DIV_8
2701 * @arg @ref LL_RCC_APB3_DIV_16
2702 */
2703 __STATIC_INLINE uint32_t LL_RCC_GetAPB3Prescaler(void)
2704 {
2705 #if defined(RCC_D1CFGR_D1PPRE)
2706 return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1PPRE));
2707 #else
2708 return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE));
2709 #endif /* RCC_D1CFGR_D1PPRE */
2710 }
2711
2712 /**
2713 * @brief Get APB4 prescaler
2714 * @rmtoll D3CFGR/SRDCFGR D3PPRE/SRDPPRE LL_RCC_GetAPB4Prescaler
2715 * @retval Returned value can be one of the following values:
2716 * @arg @ref LL_RCC_APB4_DIV_1
2717 * @arg @ref LL_RCC_APB4_DIV_2
2718 * @arg @ref LL_RCC_APB4_DIV_4
2719 * @arg @ref LL_RCC_APB4_DIV_8
2720 * @arg @ref LL_RCC_APB4_DIV_16
2721 */
2722 __STATIC_INLINE uint32_t LL_RCC_GetAPB4Prescaler(void)
2723 {
2724 #if defined(RCC_D3CFGR_D3PPRE)
2725 return (uint32_t)(READ_BIT(RCC->D3CFGR, RCC_D3CFGR_D3PPRE));
2726 #else
2727 return (uint32_t)(READ_BIT(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE));
2728 #endif /* RCC_D3CFGR_D3PPRE */
2729 }
2730
2731 /**
2732 * @}
2733 */
2734
2735 /** @defgroup RCC_LL_EF_MCO MCO
2736 * @{
2737 */
2738
2739 /**
2740 * @brief Configure MCOx
2741 * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n
2742 * CFGR MCO1PRE LL_RCC_ConfigMCO\n
2743 * CFGR MCO2 LL_RCC_ConfigMCO\n
2744 * CFGR MCO2PRE LL_RCC_ConfigMCO
2745 * @param MCOxSource This parameter can be one of the following values:
2746 * @arg @ref LL_RCC_MCO1SOURCE_HSI
2747 * @arg @ref LL_RCC_MCO1SOURCE_LSE
2748 * @arg @ref LL_RCC_MCO1SOURCE_HSE
2749 * @arg @ref LL_RCC_MCO1SOURCE_PLL1QCLK
2750 * @arg @ref LL_RCC_MCO1SOURCE_HSI48
2751 * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
2752 * @arg @ref LL_RCC_MCO2SOURCE_PLL2PCLK
2753 * @arg @ref LL_RCC_MCO2SOURCE_HSE
2754 * @arg @ref LL_RCC_MCO2SOURCE_PLL1PCLK
2755 * @arg @ref LL_RCC_MCO2SOURCE_CSI
2756 * @arg @ref LL_RCC_MCO2SOURCE_LSI
2757 * @param MCOxPrescaler This parameter can be one of the following values:
2758 * @arg @ref LL_RCC_MCO1_DIV_1
2759 * @arg @ref LL_RCC_MCO1_DIV_2
2760 * @arg @ref LL_RCC_MCO1_DIV_3
2761 * @arg @ref LL_RCC_MCO1_DIV_4
2762 * @arg @ref LL_RCC_MCO1_DIV_5
2763 * @arg @ref LL_RCC_MCO1_DIV_6
2764 * @arg @ref LL_RCC_MCO1_DIV_7
2765 * @arg @ref LL_RCC_MCO1_DIV_8
2766 * @arg @ref LL_RCC_MCO1_DIV_9
2767 * @arg @ref LL_RCC_MCO1_DIV_10
2768 * @arg @ref LL_RCC_MCO1_DIV_11
2769 * @arg @ref LL_RCC_MCO1_DIV_12
2770 * @arg @ref LL_RCC_MCO1_DIV_13
2771 * @arg @ref LL_RCC_MCO1_DIV_14
2772 * @arg @ref LL_RCC_MCO1_DIV_15
2773 * @arg @ref LL_RCC_MCO2_DIV_1
2774 * @arg @ref LL_RCC_MCO2_DIV_2
2775 * @arg @ref LL_RCC_MCO2_DIV_3
2776 * @arg @ref LL_RCC_MCO2_DIV_4
2777 * @arg @ref LL_RCC_MCO2_DIV_5
2778 * @arg @ref LL_RCC_MCO2_DIV_6
2779 * @arg @ref LL_RCC_MCO2_DIV_7
2780 * @arg @ref LL_RCC_MCO2_DIV_8
2781 * @arg @ref LL_RCC_MCO2_DIV_9
2782 * @arg @ref LL_RCC_MCO2_DIV_10
2783 * @arg @ref LL_RCC_MCO2_DIV_11
2784 * @arg @ref LL_RCC_MCO2_DIV_12
2785 * @arg @ref LL_RCC_MCO2_DIV_13
2786 * @arg @ref LL_RCC_MCO2_DIV_14
2787 * @arg @ref LL_RCC_MCO2_DIV_15
2788 * @retval None
2789 */
2790 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
2791 {
2792 MODIFY_REG(RCC->CFGR, (MCOxSource << 16U) | (MCOxPrescaler << 16U), (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U));
2793 }
2794
2795 /**
2796 * @}
2797 */
2798
2799 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
2800 * @{
2801 */
2802
2803 /**
2804 * @brief Configure periph clock source
2805 * @rmtoll D2CCIP1R/CDCCIP1R * LL_RCC_SetClockSource\n
2806 * D2CCIP2R/CDCCIP2R * LL_RCC_SetClockSource\n
2807 * D3CCIPR/SRDCCIPR * LL_RCC_SetClockSource
2808 * @param ClkSource This parameter can be one of the following values:
2809 * @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
2810 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
2811 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
2812 * @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
2813 * @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
2814 * @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
2815 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
2816 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
2817 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
2818 * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
2819 * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
2820 * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
2821 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
2822 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
2823 * @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
2824 * @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
2825 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
2826 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
2827 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
2828 * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
2829 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2830 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
2831 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
2832 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2833 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2834 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
2835 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
2836 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
2837 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
2838 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
2839 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
2840 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
2841 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
2842 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
2843 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
2844 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
2845 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
2846 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
2847 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
2848 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
2849 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
2850 * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
2851 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
2852 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
2853 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
2854 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
2855 * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
2856 * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
2857 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
2858 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)
2859 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)
2860 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)
2861 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_SPDIF (*)
2862 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)
2863 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)
2864 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)
2865 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*)
2866 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*)
2867 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF (*)
2868 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*)
2869 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
2870 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
2871 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
2872 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
2873 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_SPDIF (*)
2874 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
2875 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
2876 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
2877 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
2878 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
2879 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
2880 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
2881 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
2882 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
2883 * @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
2884 * @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
2885 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
2886 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
2887 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
2888 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
2889 * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
2890 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
2891 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
2892 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
2893 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
2894 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
2895 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
2896 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
2897 * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
2898 *
2899 * (*) value not defined in all devices.
2900 * @retval None
2901 */
2902 __STATIC_INLINE void LL_RCC_SetClockSource(uint32_t ClkSource)
2903 {
2904 #if defined(RCC_D1CCIPR_FMCSEL)
2905 uint32_t * pReg = (uint32_t *)((uint32_t)&RCC->D1CCIPR + LL_CLKSOURCE_REG(ClkSource));
2906 #else
2907 uint32_t * pReg = (uint32_t *)((uint32_t)&RCC->CDCCIPR + LL_CLKSOURCE_REG(ClkSource));
2908 #endif /* */
2909 MODIFY_REG(*pReg, LL_CLKSOURCE_MASK(ClkSource), LL_CLKSOURCE_CONFIG(ClkSource));
2910 }
2911
2912 /**
2913 * @brief Configure USARTx clock source
2914 * @rmtoll D2CCIP2R / D2CCIP2R USART16SEL LL_RCC_SetUSARTClockSource\n
2915 * D2CCIP2R / D2CCIP2R USART28SEL LL_RCC_SetUSARTClockSource
2916 * @param ClkSource This parameter can be one of the following values:
2917 * @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
2918 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
2919 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
2920 * @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
2921 * @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
2922 * @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
2923 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
2924 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
2925 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
2926 * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
2927 * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
2928 * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
2929 * @retval None
2930 */
2931 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t ClkSource)
2932 {
2933 LL_RCC_SetClockSource(ClkSource);
2934 }
2935
2936 /**
2937 * @brief Configure LPUARTx clock source
2938 * @rmtoll D3CCIPR / SRDCCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
2939 * @param ClkSource This parameter can be one of the following values:
2940 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4
2941 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q
2942 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q
2943 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
2944 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI
2945 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
2946 * @retval None
2947 */
2948 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t ClkSource)
2949 {
2950 #if defined(RCC_D3CCIPR_LPUART1SEL)
2951 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, ClkSource);
2952 #else
2953 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, ClkSource);
2954 #endif /* RCC_D3CCIPR_LPUART1SEL */
2955 }
2956
2957 /**
2958 * @brief Configure I2Cx clock source
2959 * @rmtoll D2CCIP2R / CDCCIP2R I2C123SEL LL_RCC_SetI2CClockSource\n
2960 * D3CCIPR / SRDCCIPR I2C4SEL LL_RCC_SetI2CClockSource
2961 * @param ClkSource This parameter can be one of the following values:
2962 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
2963 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
2964 * @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
2965 * @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
2966 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
2967 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
2968 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
2969 * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
2970 * @retval None
2971 */
2972 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t ClkSource)
2973 {
2974 LL_RCC_SetClockSource(ClkSource);
2975 }
2976
2977 /**
2978 * @brief Configure LPTIMx clock source
2979 * @rmtoll D2CCIP2R / CDCCIP2R LPTIM1SEL LL_RCC_SetLPTIMClockSource
2980 * D3CCIPR / SRDCCIPR LPTIM2SEL LL_RCC_SetLPTIMClockSource\n
2981 * D3CCIPR / SRDCCIPR LPTIM345SEL LL_RCC_SetLPTIMClockSource
2982 * @param ClkSource This parameter can be one of the following values:
2983 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2984 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
2985 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
2986 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2987 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2988 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
2989 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
2990 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
2991 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
2992 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
2993 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
2994 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
2995 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
2996 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
2997 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
2998 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
2999 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
3000 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
3001 * @retval None
3002 */
3003 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t ClkSource)
3004 {
3005 LL_RCC_SetClockSource(ClkSource);
3006 }
3007
3008 /**
3009 * @brief Configure SAIx clock source
3010 * @rmtoll D2CCIP1R / CDCCIP1R SAI1SEL LL_RCC_SetSAIClockSource\n
3011 * D2CCIP1R / CDCCIP1R SAI23SEL LL_RCC_SetSAIClockSource
3012 * D3CCIPR / SRDCCIPR SAI4ASEL LL_RCC_SetSAI4xClockSource\n
3013 * D3CCIPR / SRDCCIPR SAI4BSEL LL_RCC_SetSAI4xClockSource
3014 * @param ClkSource This parameter can be one of the following values:
3015 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
3016 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
3017 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
3018 * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
3019 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
3020 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
3021 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
3022 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
3023 * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
3024 * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
3025 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
3026 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)
3027 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)
3028 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)
3029 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_SPDIF (*)
3030 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)
3031 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)
3032 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)
3033 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*)
3034 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*)
3035 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF (*)
3036 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*)
3037 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
3038 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
3039 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
3040 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
3041 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_SPDIF (*)
3042 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
3043 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
3044 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
3045 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
3046 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
3047 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
3048 *
3049 * (*) value not defined in all devices.
3050 * @retval None
3051 */
3052 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t ClkSource)
3053 {
3054 LL_RCC_SetClockSource(ClkSource);
3055 }
3056
3057 /**
3058 * @brief Configure SDMMCx clock source
3059 * @rmtoll D1CCIPR / CDCCIPR SDMMCSEL LL_RCC_SetSDMMCClockSource
3060 * @param ClkSource This parameter can be one of the following values:
3061 * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL1Q
3062 * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2R
3063 * @retval None
3064 */
3065 __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t ClkSource)
3066 {
3067 #if defined(RCC_D1CCIPR_SDMMCSEL)
3068 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, ClkSource);
3069 #else
3070 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, ClkSource);
3071 #endif /* RCC_D1CCIPR_SDMMCSEL */
3072 }
3073
3074 /**
3075 * @brief Configure RNGx clock source
3076 * @rmtoll D2CCIP2R / CDCCIP2R RNGSEL LL_RCC_SetRNGClockSource
3077 * @param ClkSource This parameter can be one of the following values:
3078 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
3079 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q
3080 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
3081 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
3082 * @retval None
3083 */
3084 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t ClkSource)
3085 {
3086 #if defined(RCC_D2CCIP2R_RNGSEL)
3087 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, ClkSource);
3088 #else
3089 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, ClkSource);
3090 #endif /* RCC_D2CCIP2R_RNGSEL */
3091 }
3092
3093 /**
3094 * @brief Configure USBx clock source
3095 * @rmtoll D2CCIP2R / CDCCIP2R USBSEL LL_RCC_SetUSBClockSource
3096 * @param ClkSource This parameter can be one of the following values:
3097 * @arg @ref LL_RCC_USB_CLKSOURCE_DISABLE
3098 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q
3099 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q
3100 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
3101 * @retval None
3102 */
3103 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t ClkSource)
3104 {
3105 #if defined(RCC_D2CCIP2R_USBSEL)
3106 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, ClkSource);
3107 #else
3108 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, ClkSource);
3109 #endif /* RCC_D2CCIP2R_USBSEL */
3110 }
3111
3112 /**
3113 * @brief Configure CECx clock source
3114 * @rmtoll D2CCIP2R / CDCCIP2R CECSEL LL_RCC_SetCECClockSource
3115 * @param ClkSource This parameter can be one of the following values:
3116 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
3117 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSI
3118 * @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122
3119 * @retval None
3120 */
3121 __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t ClkSource)
3122 {
3123 #if defined(RCC_D2CCIP2R_CECSEL)
3124 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, ClkSource);
3125 #else
3126 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL, ClkSource);
3127 #endif /* RCC_D2CCIP2R_CECSEL */
3128 }
3129
3130 #if defined(DSI)
3131 /**
3132 * @brief Configure DSIx clock source
3133 * @rmtoll D1CCIPR DSISEL LL_RCC_SetDSIClockSource
3134 * @param ClkSource This parameter can be one of the following values:
3135 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
3136 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL2Q
3137 * @retval None
3138 */
3139 __STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t ClkSource)
3140 {
3141 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, ClkSource);
3142 }
3143 #endif /* DSI */
3144
3145 /**
3146 * @brief Configure DFSDMx Kernel clock source
3147 * @rmtoll D2CCIP1R / CDCCIP1R DFSDM1SEL LL_RCC_SetDFSDMClockSource
3148 * @param ClkSource This parameter can be one of the following values:
3149 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
3150 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
3151 * @retval None
3152 */
3153 __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t ClkSource)
3154 {
3155 #if defined(RCC_D2CCIP1R_DFSDM1SEL)
3156 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, ClkSource);
3157 #else
3158 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, ClkSource);
3159 #endif /* RCC_D2CCIP1R_DFSDM1SEL */
3160 }
3161
3162 #if defined(DFSDM2_BASE)
3163 /**
3164 * @brief Configure DFSDMx Kernel clock source
3165 * @rmtoll SRDCCIPR DFSDM2SEL LL_RCC_SetDFSDM2ClockSource
3166 * @param ClkSource This parameter can be one of the following values:
3167 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK4
3168 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK
3169 * @retval None
3170 */
3171 __STATIC_INLINE void LL_RCC_SetDFSDM2ClockSource(uint32_t ClkSource)
3172 {
3173 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, ClkSource);
3174 }
3175 #endif /* DFSDM2_BASE */
3176
3177 /**
3178 * @brief Configure FMCx Kernel clock source
3179 * @rmtoll D1CCIPR / CDCCIPR FMCSEL LL_RCC_SetFMCClockSource
3180 * @param ClkSource This parameter can be one of the following values:
3181 * @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK
3182 * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q
3183 * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R
3184 * @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP
3185 * @retval None
3186 */
3187 __STATIC_INLINE void LL_RCC_SetFMCClockSource(uint32_t ClkSource)
3188 {
3189 #if defined(RCC_D1CCIPR_FMCSEL)
3190 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, ClkSource);
3191 #else
3192 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, ClkSource);
3193 #endif /* RCC_D1CCIPR_FMCSEL */
3194 }
3195
3196 #if defined(QUADSPI)
3197 /**
3198 * @brief Configure QSPIx Kernel clock source
3199 * @rmtoll D1CCIPR QSPISEL LL_RCC_SetQSPIClockSource
3200 * @param ClkSource This parameter can be one of the following values:
3201 * @arg @ref LL_RCC_QSPI_CLKSOURCE_HCLK
3202 * @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL1Q
3203 * @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL2R
3204 * @arg @ref LL_RCC_QSPI_CLKSOURCE_CLKP
3205 * @retval None
3206 */
3207 __STATIC_INLINE void LL_RCC_SetQSPIClockSource(uint32_t ClkSource)
3208 {
3209 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, ClkSource);
3210 }
3211 #endif /* QUADSPI */
3212
3213 #if defined(OCTOSPI1) || defined(OCTOSPI2)
3214 /**
3215 * @brief Configure OSPIx Kernel clock source
3216 * @rmtoll D1CCIPR OPISEL LL_RCC_SetOSPIClockSource
3217 * @param ClkSource This parameter can be one of the following values:
3218 * @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK
3219 * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q
3220 * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R
3221 * @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP
3222 * @retval None
3223 */
3224 __STATIC_INLINE void LL_RCC_SetOSPIClockSource(uint32_t ClkSource)
3225 {
3226 #if defined(RCC_D1CCIPR_OCTOSPISEL)
3227 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL, ClkSource);
3228 #else
3229 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, ClkSource);
3230 #endif /* RCC_D1CCIPR_OCTOSPISEL */
3231 }
3232 #endif /* OCTOSPI1 || OCTOSPI2 */
3233
3234 /**
3235 * @brief Configure CLKP Kernel clock source
3236 * @rmtoll D1CCIPR / CDCCIPR CKPERSEL LL_RCC_SetCLKPClockSource
3237 * @param ClkSource This parameter can be one of the following values:
3238 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI
3239 * @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI
3240 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE
3241 * @retval None
3242 */
3243 __STATIC_INLINE void LL_RCC_SetCLKPClockSource(uint32_t ClkSource)
3244 {
3245 #if defined(RCC_D1CCIPR_CKPERSEL)
3246 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, ClkSource);
3247 #else
3248 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, ClkSource);
3249 #endif /* RCC_D1CCIPR_CKPERSEL */
3250 }
3251
3252 /**
3253 * @brief Configure SPIx Kernel clock source
3254 * @rmtoll D2CCIP1R / CDCCIP1R SPI123SEL LL_RCC_SetSPIClockSource\n
3255 * D2CCIP1R / CDCCIP1R SPI45SEL LL_RCC_SetSPIClockSource\n
3256 * D3CCIPR / SRDCCIPR SPI6SEL LL_RCC_SetSPIClockSource
3257 * @param ClkSource This parameter can be one of the following values:
3258 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
3259 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
3260 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
3261 * @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
3262 * @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
3263 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
3264 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
3265 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
3266 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
3267 * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
3268 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
3269 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
3270 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
3271 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
3272 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
3273 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
3274 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
3275 * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
3276 *
3277 * (*) value not defined in all devices.
3278 * @retval None
3279 */
3280 __STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t ClkSource)
3281 {
3282 LL_RCC_SetClockSource(ClkSource);
3283 }
3284
3285 /**
3286 * @brief Configure SPDIFx Kernel clock source
3287 * @rmtoll D2CCIP1R / CDCCIP1R SPDIFSEL LL_RCC_SetSPDIFClockSource
3288 * @param ClkSource This parameter can be one of the following values:
3289 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL1Q
3290 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL2R
3291 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL3R
3292 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_HSI
3293 * @retval None
3294 */
3295 __STATIC_INLINE void LL_RCC_SetSPDIFClockSource(uint32_t ClkSource)
3296 {
3297 #if defined(RCC_D2CCIP1R_SPDIFSEL)
3298 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, ClkSource);
3299 #else
3300 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, ClkSource);
3301 #endif /* RCC_D2CCIP1R_SPDIFSEL */
3302 }
3303
3304 /**
3305 * @brief Configure FDCANx Kernel clock source
3306 * @rmtoll D2CCIP1R / CDCCIP1R FDCANSEL LL_RCC_SetFDCANClockSource
3307 * @param ClkSource This parameter can be one of the following values:
3308 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
3309 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q
3310 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q
3311 * @retval None
3312 */
3313 __STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t ClkSource)
3314 {
3315 #if defined(RCC_D2CCIP1R_FDCANSEL)
3316 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, ClkSource);
3317 #else
3318 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, ClkSource);
3319 #endif /* RCC_D2CCIP1R_FDCANSEL */
3320 }
3321
3322 /**
3323 * @brief Configure SWPx Kernel clock source
3324 * @rmtoll D2CCIP1R / CDCCIP1R SWPSEL LL_RCC_SetSWPClockSource
3325 * @param ClkSource This parameter can be one of the following values:
3326 * @arg @ref LL_RCC_SWP_CLKSOURCE_PCLK1
3327 * @arg @ref LL_RCC_SWP_CLKSOURCE_HSI
3328 * @retval None
3329 */
3330 __STATIC_INLINE void LL_RCC_SetSWPClockSource(uint32_t ClkSource)
3331 {
3332 #if defined(RCC_D2CCIP1R_SWPSEL)
3333 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, ClkSource);
3334 #else
3335 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, ClkSource);
3336 #endif /* RCC_D2CCIP1R_SWPSEL */
3337 }
3338
3339 /**
3340 * @brief Configure ADCx Kernel clock source
3341 * @rmtoll D3CCIPR / SRDCCIPR ADCSEL LL_RCC_SetADCClockSource
3342 * @param ClkSource This parameter can be one of the following values:
3343 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P
3344 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R
3345 * @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP
3346 * @retval None
3347 */
3348 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ClkSource)
3349 {
3350 #if defined(RCC_D3CCIPR_ADCSEL)
3351 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, ClkSource);
3352 #else
3353 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, ClkSource);
3354 #endif /* RCC_D3CCIPR_ADCSEL */
3355 }
3356
3357 /**
3358 * @brief Get periph clock source
3359 * @rmtoll D1CCIPR / CDCCIPR * LL_RCC_GetClockSource\n
3360 * D2CCIP1R / CDCCIP1R * LL_RCC_GetClockSource\n
3361 * D2CCIP2R / CDCCIP2R * LL_RCC_GetClockSource\n
3362 * D3CCIPR / SRDCCIPR * LL_RCC_GetClockSource
3363 * @param Periph This parameter can be one of the following values:
3364 * @arg @ref LL_RCC_USART16_CLKSOURCE
3365 * @arg @ref LL_RCC_USART234578_CLKSOURCE
3366 * @arg @ref LL_RCC_I2C123_CLKSOURCE
3367 * @arg @ref LL_RCC_I2C4_CLKSOURCE
3368 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
3369 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
3370 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE
3371 * @arg @ref LL_RCC_SAI1_CLKSOURCE
3372 * @arg @ref LL_RCC_SAI23_CLKSOURCE
3373 * @arg @ref LL_RCC_SAI4A_CLKSOURCE (*)
3374 * @arg @ref LL_RCC_SAI4B_CLKSOURCE (*)
3375 * @arg @ref LL_RCC_SAI2A_CLKSOURCE (*)
3376 * @arg @ref LL_RCC_SAI2B_CLKSOURCE (*)
3377 * @arg @ref LL_RCC_SPI123_CLKSOURCE (*)
3378 * @arg @ref LL_RCC_SPI45_CLKSOURCE (*)
3379 * @arg @ref LL_RCC_SPI6_CLKSOURCE (*)
3380 * @retval Returned value can be one of the following values:
3381 * @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
3382 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
3383 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
3384 * @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
3385 * @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
3386 * @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
3387 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
3388 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
3389 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
3390 * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
3391 * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
3392 * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
3393 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
3394 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
3395 * @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
3396 * @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
3397 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
3398 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
3399 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
3400 * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
3401 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
3402 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
3403 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
3404 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3405 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3406 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
3407 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
3408 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
3409 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
3410 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
3411 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
3412 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
3413 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
3414 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
3415 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
3416 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
3417 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
3418 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
3419 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
3420 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
3421 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
3422 * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
3423 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
3424 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
3425 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
3426 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
3427 * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
3428 * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
3429 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
3430 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)
3431 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)
3432 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)
3433 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP (*)
3434 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*)
3435 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
3436 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
3437 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
3438 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
3439 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)
3440 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)
3441 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)
3442 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*)
3443 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*)
3444 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
3445 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
3446 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
3447 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
3448 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
3449 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
3450 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
3451 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
3452 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
3453 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
3454 * @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
3455 * @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
3456 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
3457 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
3458 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
3459 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
3460 * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
3461 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
3462 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
3463 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
3464 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
3465 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
3466 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
3467 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
3468 * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
3469 *
3470 * (*) value not defined in all devices.
3471 * @retval None
3472 */
3473 __STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph)
3474 {
3475 #if defined(RCC_D1CCIPR_FMCSEL)
3476 const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->D1CCIPR) + LL_CLKSOURCE_REG(Periph)));
3477 #else
3478 const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->CDCCIPR) + LL_CLKSOURCE_REG(Periph)));
3479 #endif /* RCC_D1CCIPR_FMCSEL */
3480 return (uint32_t) (Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> LL_CLKSOURCE_SHIFT(Periph)) << LL_RCC_CONFIG_SHIFT) );
3481 }
3482
3483 /**
3484 * @brief Get USARTx clock source
3485 * @rmtoll D2CCIP2R / CDCCIP2R USART16SEL LL_RCC_GetUSARTClockSource\n
3486 * D2CCIP2R / CDCCIP2R USART28SEL LL_RCC_GetUSARTClockSource
3487 * @param Periph This parameter can be one of the following values:
3488 * @arg @ref LL_RCC_USART16_CLKSOURCE
3489 * @arg @ref LL_RCC_USART234578_CLKSOURCE
3490 * @retval Returned value can be one of the following values:
3491 * @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
3492 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
3493 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
3494 * @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
3495 * @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
3496 * @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
3497 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
3498 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
3499 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
3500 * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
3501 * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
3502 * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
3503 */
3504 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t Periph)
3505 {
3506 return LL_RCC_GetClockSource(Periph);
3507 }
3508
3509 /**
3510 * @brief Get LPUART clock source
3511 * @rmtoll D3CCIPR / SRDCCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
3512 * @param Periph This parameter can be one of the following values:
3513 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
3514 * @retval Returned value can be one of the following values:
3515 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4
3516 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q
3517 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q
3518 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
3519 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI
3520 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
3521 */
3522 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t Periph)
3523 {
3524 UNUSED(Periph);
3525 #if defined(RCC_D3CCIPR_LPUART1SEL)
3526 return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL));
3527 #else
3528 return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL));
3529 #endif /* RCC_D3CCIPR_LPUART1SEL */
3530 }
3531
3532 /**
3533 * @brief Get I2Cx clock source
3534 * @rmtoll D2CCIP2R / CDCCIP2R I2C123SEL LL_RCC_GetI2CClockSource\n
3535 * D3CCIPR / SRDCCIPR I2C4SEL LL_RCC_GetI2CClockSource
3536 * @param Periph This parameter can be one of the following values:
3537 * @arg @ref LL_RCC_I2C123_CLKSOURCE
3538 * @arg @ref LL_RCC_I2C4_CLKSOURCE
3539 * @retval Returned value can be one of the following values:
3540 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
3541 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
3542 * @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
3543 * @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
3544 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
3545 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
3546 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
3547 * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
3548 */
3549 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t Periph)
3550 {
3551 return LL_RCC_GetClockSource(Periph);
3552 }
3553
3554 /**
3555 * @brief Get LPTIM clock source
3556 * @rmtoll D2CCIP2R / CDCCIP2R LPTIM1SEL LL_RCC_GetLPTIMClockSource\n
3557 * D3CCIPR / SRDCCIPR LPTIM2SEL LL_RCC_GetLPTIMClockSource\n
3558 * D3CCIPR / SRDCCIPR LPTIM345SEL LL_RCC_GetLPTIMClockSource
3559 * @param Periph This parameter can be one of the following values:
3560 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
3561 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
3562 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE
3563 * @retval Returned value can be one of the following values:
3564 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
3565 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
3566 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
3567 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3568 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3569 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
3570 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
3571 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
3572 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
3573 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
3574 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
3575 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
3576 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
3577 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
3578 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
3579 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
3580 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
3581 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
3582 * @retval None
3583 */
3584 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t Periph)
3585 {
3586 return LL_RCC_GetClockSource(Periph);
3587 }
3588
3589 /**
3590 * @brief Get SAIx clock source
3591 * @rmtoll D2CCIP1R / CDCCIP1R SAI1SEL LL_RCC_GetSAIClockSource\n
3592 * D2CCIP1R / CDCCIP1R SAI23SEL LL_RCC_GetSAIClockSource
3593 * D3CCIPR / SRDCCIPR SAI4ASEL LL_RCC_GetSAIClockSource\n
3594 * D3CCIPR / SRDCCIPR SAI4BSEL LL_RCC_GetSAIClockSource
3595 * @param Periph This parameter can be one of the following values:
3596 * @arg @ref LL_RCC_SAI1_CLKSOURCE (*)
3597 * @arg @ref LL_RCC_SAI2A_CLKSOURCE (*)
3598 * @arg @ref LL_RCC_SAI2B_CLKSOURCE (*)
3599 * @arg @ref LL_RCC_SAI23_CLKSOURCE (*)
3600 * @arg @ref LL_RCC_SAI4A_CLKSOURCE (*)
3601 * @arg @ref LL_RCC_SAI4B_CLKSOURCE (*)
3602 * @retval Returned value can be one of the following values:
3603 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
3604 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
3605 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
3606 * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
3607 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
3608 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
3609 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
3610 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
3611 * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
3612 * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
3613 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)
3614 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)
3615 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)
3616 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*)
3617 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*)
3618 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF (*)
3619 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
3620 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
3621 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
3622 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
3623 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
3624 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
3625 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
3626 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)
3627 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)
3628 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)
3629 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP (*)
3630 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*)
3631 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
3632 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
3633 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
3634 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
3635 *
3636 * (*) value not defined in all devices.
3637 */
3638 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t Periph)
3639 {
3640 return LL_RCC_GetClockSource(Periph);
3641 }
3642
3643 /**
3644 * @brief Get SDMMC clock source
3645 * @rmtoll D1CCIPR / CDCCIPR SDMMCSEL LL_RCC_GetSDMMCClockSource
3646 * @param Periph This parameter can be one of the following values:
3647 * @arg @ref LL_RCC_SDMMC_CLKSOURCE
3648 * @retval Returned value can be one of the following values:
3649 * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL1Q
3650 * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2R
3651 */
3652 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t Periph)
3653 {
3654 UNUSED(Periph);
3655 #if defined(RCC_D1CCIPR_SDMMCSEL)
3656 return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL));
3657 #else
3658 return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL));
3659 #endif /* RCC_D1CCIPR_SDMMCSEL */
3660 }
3661
3662 /**
3663 * @brief Get RNG clock source
3664 * @rmtoll D2CCIP2R RNGSEL LL_RCC_GetRNGClockSource
3665 * @param Periph This parameter can be one of the following values:
3666 * @arg @ref LL_RCC_RNG_CLKSOURCE
3667 * @retval Returned value can be one of the following values:
3668 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
3669 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q
3670 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
3671 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
3672 */
3673 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t Periph)
3674 {
3675 UNUSED(Periph);
3676 #if defined(RCC_D2CCIP2R_RNGSEL)
3677 return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL));
3678 #else
3679 return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL));
3680 #endif /* RCC_D2CCIP2R_RNGSEL */
3681 }
3682
3683 /**
3684 * @brief Get USB clock source
3685 * @rmtoll D2CCIP2R / CDCCIP2R USBSEL LL_RCC_GetUSBClockSource
3686 * @param Periph This parameter can be one of the following values:
3687 * @arg @ref LL_RCC_USB_CLKSOURCE
3688 * @retval Returned value can be one of the following values:
3689 * @arg @ref LL_RCC_USB_CLKSOURCE_DISABLE
3690 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q
3691 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q
3692 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
3693 */
3694 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t Periph)
3695 {
3696 UNUSED(Periph);
3697 #if defined(RCC_D2CCIP2R_USBSEL)
3698 return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL));
3699 #else
3700 return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL));
3701 #endif /* RCC_D2CCIP2R_USBSEL */
3702 }
3703
3704 /**
3705 * @brief Get CEC clock source
3706 * @rmtoll D2CCIP2R / CDCCIP2R CECSEL LL_RCC_GetCECClockSource
3707 * @param Periph This parameter can be one of the following values:
3708 * @arg @ref LL_RCC_CEC_CLKSOURCE
3709 * @retval Returned value can be one of the following values:
3710 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
3711 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSI
3712 * @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122
3713 */
3714 __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t Periph)
3715 {
3716 UNUSED(Periph);
3717 #if defined(RCC_D2CCIP2R_CECSEL)
3718 return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL));
3719 #else
3720 return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL));
3721 #endif /* RCC_D2CCIP2R_CECSEL */
3722 }
3723
3724 #if defined(DSI)
3725 /**
3726 * @brief Get DSI clock source
3727 * @rmtoll D1CCIPR DSISEL LL_RCC_GetDSIClockSource
3728 * @param Periph This parameter can be one of the following values:
3729 * @arg @ref LL_RCC_DSI_CLKSOURCE
3730 * @retval Returned value can be one of the following values:
3731 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
3732 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL2Q
3733 */
3734 __STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t Periph)
3735 {
3736 UNUSED(Periph);
3737 return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL));
3738 }
3739 #endif /* DSI */
3740
3741 /**
3742 * @brief Get DFSDM Kernel clock source
3743 * @rmtoll D2CCIP1R / CDCCIP1R DFSDM1SEL LL_RCC_GetDFSDMClockSource
3744 * @param Periph This parameter can be one of the following values:
3745 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
3746 * @retval Returned value can be one of the following values:
3747 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
3748 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
3749 */
3750 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t Periph)
3751 {
3752 UNUSED(Periph);
3753 #if defined(RCC_D2CCIP1R_DFSDM1SEL)
3754 return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL));
3755 #else
3756 return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL));
3757 #endif /* RCC_D2CCIP1R_DFSDM1SEL */
3758 }
3759
3760 #if defined(DFSDM2_BASE)
3761 /**
3762 * @brief Get DFSDM2 Kernel clock source
3763 * @rmtoll SRDCCIPR DFSDM2SEL LL_RCC_GetDFSDM2ClockSource
3764 * @param Periph This parameter can be one of the following values:
3765 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE
3766 * @retval Returned value can be one of the following values:
3767 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK4
3768 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK
3769 */
3770 __STATIC_INLINE uint32_t LL_RCC_GetDFSDM2ClockSource(uint32_t Periph)
3771 {
3772 UNUSED(Periph);
3773 return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL));
3774 }
3775 #endif /* DFSDM2_BASE */
3776
3777 /**
3778 * @brief Get FMC Kernel clock source
3779 * @rmtoll D1CCIPR / D1CCIPR FMCSEL LL_RCC_GetFMCClockSource
3780 * @param Periph This parameter can be one of the following values:
3781 * @arg @ref LL_RCC_FMC_CLKSOURCE
3782 * @retval Returned value can be one of the following values:
3783 * @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK
3784 * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q
3785 * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R
3786 * @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP
3787 */
3788 __STATIC_INLINE uint32_t LL_RCC_GetFMCClockSource(uint32_t Periph)
3789 {
3790 UNUSED(Periph);
3791 #if defined(RCC_D1CCIPR_FMCSEL)
3792 return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL));
3793 #else
3794 return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL));
3795 #endif /* RCC_D1CCIPR_FMCSEL */
3796 }
3797
3798 #if defined(QUADSPI)
3799 /**
3800 * @brief Get QSPI Kernel clock source
3801 * @rmtoll D1CCIPR / CDCCIPR QSPISEL LL_RCC_GetQSPIClockSource
3802 * @param Periph This parameter can be one of the following values:
3803 * @arg @ref LL_RCC_QSPI_CLKSOURCE
3804 * @retval Returned value can be one of the following values:
3805 * @arg @ref LL_RCC_QSPI_CLKSOURCE_HCLK
3806 * @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL1Q
3807 * @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL2R
3808 * @arg @ref LL_RCC_QSPI_CLKSOURCE_CLKP
3809 */
3810 __STATIC_INLINE uint32_t LL_RCC_GetQSPIClockSource(uint32_t Periph)
3811 {
3812 UNUSED(Periph);
3813 return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL));
3814 }
3815 #endif /* QUADSPI */
3816
3817 #if defined(OCTOSPI1) || defined(OCTOSPI2)
3818 /**
3819 * @brief Get OSPI Kernel clock source
3820 * @rmtoll CDCCIPR OSPISEL LL_RCC_GetOSPIClockSource
3821 * @param Periph This parameter can be one of the following values:
3822 * @arg @ref LL_RCC_OSPI_CLKSOURCE
3823 * @retval Returned value can be one of the following values:
3824 * @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK
3825 * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q
3826 * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R
3827 * @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP
3828 */
3829 __STATIC_INLINE uint32_t LL_RCC_GetOSPIClockSource(uint32_t Periph)
3830 {
3831 UNUSED(Periph);
3832 #if defined(RCC_D1CCIPR_OCTOSPISEL)
3833 return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL));
3834 #else
3835 return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL));
3836 #endif /* RCC_D1CCIPR_OCTOSPISEL */
3837 }
3838 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
3839
3840 /**
3841 * @brief Get CLKP Kernel clock source
3842 * @rmtoll D1CCIPR / CDCCIPR CKPERSEL LL_RCC_GetCLKPClockSource
3843 * @param Periph This parameter can be one of the following values:
3844 * @arg @ref LL_RCC_CLKP_CLKSOURCE
3845 * @retval Returned value can be one of the following values:
3846 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI
3847 * @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI
3848 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE
3849 */
3850 __STATIC_INLINE uint32_t LL_RCC_GetCLKPClockSource(uint32_t Periph)
3851 {
3852 UNUSED(Periph);
3853 #if defined(RCC_D1CCIPR_CKPERSEL)
3854 return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL));
3855 #else
3856 return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL));
3857 #endif /* RCC_D1CCIPR_CKPERSEL */
3858 }
3859
3860 /**
3861 * @brief Get SPIx Kernel clock source
3862 * @rmtoll D2CCIP1R / CDCCIP1R SPI123SEL LL_RCC_GetSPIClockSource\n
3863 * D2CCIP1R / CDCCIP1R SPI45SEL LL_RCC_GetSPIClockSource\n
3864 * D3CCIPR / SRDCCIPR SPI6SEL LL_RCC_GetSPIClockSource
3865 * @param Periph This parameter can be one of the following values:
3866 * @arg @ref LL_RCC_SPI123_CLKSOURCE
3867 * @arg @ref LL_RCC_SPI45_CLKSOURCE
3868 * @arg @ref LL_RCC_SPI6_CLKSOURCE
3869 * @retval Returned value can be one of the following values:
3870 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
3871 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
3872 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
3873 * @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
3874 * @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
3875 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
3876 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
3877 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
3878 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
3879 * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
3880 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
3881 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
3882 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
3883 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
3884 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
3885 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
3886 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
3887 * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
3888 *
3889 * (*) value not defined in all stm32h7xx lines.
3890 */
3891 __STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t Periph)
3892 {
3893 return LL_RCC_GetClockSource(Periph);
3894 }
3895
3896 /**
3897 * @brief Get SPDIF Kernel clock source
3898 * @rmtoll D2CCIP1R / CDCCIP1R SPDIFSEL LL_RCC_GetSPDIFClockSource
3899 * @param Periph This parameter can be one of the following values:
3900 * @arg @ref LL_RCC_SPDIF_CLKSOURCE
3901 * @retval Returned value can be one of the following values:
3902 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL1Q
3903 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL2R
3904 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL3R
3905 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_HSI
3906 */
3907 __STATIC_INLINE uint32_t LL_RCC_GetSPDIFClockSource(uint32_t Periph)
3908 {
3909 UNUSED(Periph);
3910 #if defined(RCC_D2CCIP1R_SPDIFSEL)
3911 return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL));
3912 #else
3913 return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL));
3914 #endif /* RCC_D2CCIP1R_SPDIFSEL */
3915 }
3916
3917 /**
3918 * @brief Get FDCAN Kernel clock source
3919 * @rmtoll D2CCIP1R / CDCCIP1R FDCANSEL LL_RCC_GetFDCANClockSource
3920 * @param Periph This parameter can be one of the following values:
3921 * @arg @ref LL_RCC_FDCAN_CLKSOURCE
3922 * @retval Returned value can be one of the following values:
3923 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
3924 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q
3925 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q
3926 */
3927 __STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t Periph)
3928 {
3929 UNUSED(Periph);
3930 #if defined(RCC_D2CCIP1R_FDCANSEL)
3931 return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL));
3932 #else
3933 return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL));
3934 #endif /* RCC_D2CCIP1R_FDCANSEL */
3935 }
3936
3937 /**
3938 * @brief Get SWP Kernel clock source
3939 * @rmtoll D2CCIP1R / CDCCIP1R SWPSEL LL_RCC_GetSWPClockSource
3940 * @param Periph This parameter can be one of the following values:
3941 * @arg @ref LL_RCC_SWP_CLKSOURCE
3942 * @retval Returned value can be one of the following values:
3943 * @arg @ref LL_RCC_SWP_CLKSOURCE_PCLK1
3944 * @arg @ref LL_RCC_SWP_CLKSOURCE_HSI
3945 */
3946 __STATIC_INLINE uint32_t LL_RCC_GetSWPClockSource(uint32_t Periph)
3947 {
3948 UNUSED(Periph);
3949 #if defined(RCC_D2CCIP1R_SWPSEL)
3950 return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL));
3951 #else
3952 return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL));
3953 #endif /* RCC_D2CCIP1R_SWPSEL */
3954 }
3955
3956 /**
3957 * @brief Get ADC Kernel clock source
3958 * @rmtoll D3CCIPR / SRDCCIPR ADCSEL LL_RCC_GetADCClockSource
3959 * @param Periph This parameter can be one of the following values:
3960 * @arg @ref LL_RCC_ADC_CLKSOURCE
3961 * @retval Returned value can be one of the following values:
3962 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P
3963 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R
3964 * @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP
3965 */
3966 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t Periph)
3967 {
3968 UNUSED(Periph);
3969 #if defined (RCC_D3CCIPR_ADCSEL)
3970 return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL));
3971 #else
3972 return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL));
3973 #endif /* RCC_D3CCIPR_ADCSEL */
3974 }
3975
3976 /**
3977 * @}
3978 */
3979
3980 /** @defgroup RCC_LL_EF_RTC RTC
3981 * @{
3982 */
3983
3984 /**
3985 * @brief Set RTC Clock Source
3986 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
3987 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
3988 * set). The BDRST bit can be used to reset them.
3989 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
3990 * @param Source This parameter can be one of the following values:
3991 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
3992 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
3993 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
3994 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
3995 * @retval None
3996 */
3997 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
3998 {
3999 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
4000 }
4001
4002 /**
4003 * @brief Get RTC Clock Source
4004 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
4005 * @retval Returned value can be one of the following values:
4006 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
4007 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
4008 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
4009 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
4010 */
4011 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
4012 {
4013 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
4014 }
4015
4016 /**
4017 * @brief Enable RTC
4018 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
4019 * @retval None
4020 */
4021 __STATIC_INLINE void LL_RCC_EnableRTC(void)
4022 {
4023 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
4024 }
4025
4026 /**
4027 * @brief Disable RTC
4028 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
4029 * @retval None
4030 */
4031 __STATIC_INLINE void LL_RCC_DisableRTC(void)
4032 {
4033 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
4034 }
4035
4036 /**
4037 * @brief Check if RTC has been enabled or not
4038 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
4039 * @retval State of bit (1 or 0).
4040 */
4041 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
4042 {
4043 return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN))?1UL:0UL);
4044 }
4045
4046 /**
4047 * @brief Force the Backup domain reset
4048 * @rmtoll BDCR BDRST / VSWRST LL_RCC_ForceBackupDomainReset
4049 * @retval None
4050 */
4051 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
4052 {
4053 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
4054 }
4055
4056 /**
4057 * @brief Release the Backup domain reset
4058 * @rmtoll BDCR BDRST / VSWRST LL_RCC_ReleaseBackupDomainReset
4059 * @retval None
4060 */
4061 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
4062 {
4063 #if defined(RCC_BDCR_BDRST)
4064 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
4065 #else
4066 CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST);
4067 #endif /* RCC_BDCR_BDRST */
4068 }
4069
4070 /**
4071 * @brief Set HSE Prescalers for RTC Clock
4072 * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler
4073 * @param Prescaler This parameter can be one of the following values:
4074 * @arg @ref LL_RCC_RTC_NOCLOCK
4075 * @arg @ref LL_RCC_RTC_HSE_DIV_2
4076 * @arg @ref LL_RCC_RTC_HSE_DIV_3
4077 * @arg @ref LL_RCC_RTC_HSE_DIV_4
4078 * @arg @ref LL_RCC_RTC_HSE_DIV_5
4079 * @arg @ref LL_RCC_RTC_HSE_DIV_6
4080 * @arg @ref LL_RCC_RTC_HSE_DIV_7
4081 * @arg @ref LL_RCC_RTC_HSE_DIV_8
4082 * @arg @ref LL_RCC_RTC_HSE_DIV_9
4083 * @arg @ref LL_RCC_RTC_HSE_DIV_10
4084 * @arg @ref LL_RCC_RTC_HSE_DIV_11
4085 * @arg @ref LL_RCC_RTC_HSE_DIV_12
4086 * @arg @ref LL_RCC_RTC_HSE_DIV_13
4087 * @arg @ref LL_RCC_RTC_HSE_DIV_14
4088 * @arg @ref LL_RCC_RTC_HSE_DIV_15
4089 * @arg @ref LL_RCC_RTC_HSE_DIV_16
4090 * @arg @ref LL_RCC_RTC_HSE_DIV_17
4091 * @arg @ref LL_RCC_RTC_HSE_DIV_18
4092 * @arg @ref LL_RCC_RTC_HSE_DIV_19
4093 * @arg @ref LL_RCC_RTC_HSE_DIV_20
4094 * @arg @ref LL_RCC_RTC_HSE_DIV_21
4095 * @arg @ref LL_RCC_RTC_HSE_DIV_22
4096 * @arg @ref LL_RCC_RTC_HSE_DIV_23
4097 * @arg @ref LL_RCC_RTC_HSE_DIV_24
4098 * @arg @ref LL_RCC_RTC_HSE_DIV_25
4099 * @arg @ref LL_RCC_RTC_HSE_DIV_26
4100 * @arg @ref LL_RCC_RTC_HSE_DIV_27
4101 * @arg @ref LL_RCC_RTC_HSE_DIV_28
4102 * @arg @ref LL_RCC_RTC_HSE_DIV_29
4103 * @arg @ref LL_RCC_RTC_HSE_DIV_30
4104 * @arg @ref LL_RCC_RTC_HSE_DIV_31
4105 * @arg @ref LL_RCC_RTC_HSE_DIV_32
4106 * @arg @ref LL_RCC_RTC_HSE_DIV_33
4107 * @arg @ref LL_RCC_RTC_HSE_DIV_34
4108 * @arg @ref LL_RCC_RTC_HSE_DIV_35
4109 * @arg @ref LL_RCC_RTC_HSE_DIV_36
4110 * @arg @ref LL_RCC_RTC_HSE_DIV_37
4111 * @arg @ref LL_RCC_RTC_HSE_DIV_38
4112 * @arg @ref LL_RCC_RTC_HSE_DIV_39
4113 * @arg @ref LL_RCC_RTC_HSE_DIV_40
4114 * @arg @ref LL_RCC_RTC_HSE_DIV_41
4115 * @arg @ref LL_RCC_RTC_HSE_DIV_42
4116 * @arg @ref LL_RCC_RTC_HSE_DIV_43
4117 * @arg @ref LL_RCC_RTC_HSE_DIV_44
4118 * @arg @ref LL_RCC_RTC_HSE_DIV_45
4119 * @arg @ref LL_RCC_RTC_HSE_DIV_46
4120 * @arg @ref LL_RCC_RTC_HSE_DIV_47
4121 * @arg @ref LL_RCC_RTC_HSE_DIV_48
4122 * @arg @ref LL_RCC_RTC_HSE_DIV_49
4123 * @arg @ref LL_RCC_RTC_HSE_DIV_50
4124 * @arg @ref LL_RCC_RTC_HSE_DIV_51
4125 * @arg @ref LL_RCC_RTC_HSE_DIV_52
4126 * @arg @ref LL_RCC_RTC_HSE_DIV_53
4127 * @arg @ref LL_RCC_RTC_HSE_DIV_54
4128 * @arg @ref LL_RCC_RTC_HSE_DIV_55
4129 * @arg @ref LL_RCC_RTC_HSE_DIV_56
4130 * @arg @ref LL_RCC_RTC_HSE_DIV_57
4131 * @arg @ref LL_RCC_RTC_HSE_DIV_58
4132 * @arg @ref LL_RCC_RTC_HSE_DIV_59
4133 * @arg @ref LL_RCC_RTC_HSE_DIV_60
4134 * @arg @ref LL_RCC_RTC_HSE_DIV_61
4135 * @arg @ref LL_RCC_RTC_HSE_DIV_62
4136 * @arg @ref LL_RCC_RTC_HSE_DIV_63
4137 * @retval None
4138 */
4139 __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
4140 {
4141 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
4142 }
4143
4144 /**
4145 * @brief Get HSE Prescalers for RTC Clock
4146 * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler
4147 * @retval Returned value can be one of the following values:
4148 * @arg @ref LL_RCC_RTC_NOCLOCK
4149 * @arg @ref LL_RCC_RTC_HSE_DIV_2
4150 * @arg @ref LL_RCC_RTC_HSE_DIV_3
4151 * @arg @ref LL_RCC_RTC_HSE_DIV_4
4152 * @arg @ref LL_RCC_RTC_HSE_DIV_5
4153 * @arg @ref LL_RCC_RTC_HSE_DIV_6
4154 * @arg @ref LL_RCC_RTC_HSE_DIV_7
4155 * @arg @ref LL_RCC_RTC_HSE_DIV_8
4156 * @arg @ref LL_RCC_RTC_HSE_DIV_9
4157 * @arg @ref LL_RCC_RTC_HSE_DIV_10
4158 * @arg @ref LL_RCC_RTC_HSE_DIV_11
4159 * @arg @ref LL_RCC_RTC_HSE_DIV_12
4160 * @arg @ref LL_RCC_RTC_HSE_DIV_13
4161 * @arg @ref LL_RCC_RTC_HSE_DIV_14
4162 * @arg @ref LL_RCC_RTC_HSE_DIV_15
4163 * @arg @ref LL_RCC_RTC_HSE_DIV_16
4164 * @arg @ref LL_RCC_RTC_HSE_DIV_17
4165 * @arg @ref LL_RCC_RTC_HSE_DIV_18
4166 * @arg @ref LL_RCC_RTC_HSE_DIV_19
4167 * @arg @ref LL_RCC_RTC_HSE_DIV_20
4168 * @arg @ref LL_RCC_RTC_HSE_DIV_21
4169 * @arg @ref LL_RCC_RTC_HSE_DIV_22
4170 * @arg @ref LL_RCC_RTC_HSE_DIV_23
4171 * @arg @ref LL_RCC_RTC_HSE_DIV_24
4172 * @arg @ref LL_RCC_RTC_HSE_DIV_25
4173 * @arg @ref LL_RCC_RTC_HSE_DIV_26
4174 * @arg @ref LL_RCC_RTC_HSE_DIV_27
4175 * @arg @ref LL_RCC_RTC_HSE_DIV_28
4176 * @arg @ref LL_RCC_RTC_HSE_DIV_29
4177 * @arg @ref LL_RCC_RTC_HSE_DIV_30
4178 * @arg @ref LL_RCC_RTC_HSE_DIV_31
4179 * @arg @ref LL_RCC_RTC_HSE_DIV_32
4180 * @arg @ref LL_RCC_RTC_HSE_DIV_33
4181 * @arg @ref LL_RCC_RTC_HSE_DIV_34
4182 * @arg @ref LL_RCC_RTC_HSE_DIV_35
4183 * @arg @ref LL_RCC_RTC_HSE_DIV_36
4184 * @arg @ref LL_RCC_RTC_HSE_DIV_37
4185 * @arg @ref LL_RCC_RTC_HSE_DIV_38
4186 * @arg @ref LL_RCC_RTC_HSE_DIV_39
4187 * @arg @ref LL_RCC_RTC_HSE_DIV_40
4188 * @arg @ref LL_RCC_RTC_HSE_DIV_41
4189 * @arg @ref LL_RCC_RTC_HSE_DIV_42
4190 * @arg @ref LL_RCC_RTC_HSE_DIV_43
4191 * @arg @ref LL_RCC_RTC_HSE_DIV_44
4192 * @arg @ref LL_RCC_RTC_HSE_DIV_45
4193 * @arg @ref LL_RCC_RTC_HSE_DIV_46
4194 * @arg @ref LL_RCC_RTC_HSE_DIV_47
4195 * @arg @ref LL_RCC_RTC_HSE_DIV_48
4196 * @arg @ref LL_RCC_RTC_HSE_DIV_49
4197 * @arg @ref LL_RCC_RTC_HSE_DIV_50
4198 * @arg @ref LL_RCC_RTC_HSE_DIV_51
4199 * @arg @ref LL_RCC_RTC_HSE_DIV_52
4200 * @arg @ref LL_RCC_RTC_HSE_DIV_53
4201 * @arg @ref LL_RCC_RTC_HSE_DIV_54
4202 * @arg @ref LL_RCC_RTC_HSE_DIV_55
4203 * @arg @ref LL_RCC_RTC_HSE_DIV_56
4204 * @arg @ref LL_RCC_RTC_HSE_DIV_57
4205 * @arg @ref LL_RCC_RTC_HSE_DIV_58
4206 * @arg @ref LL_RCC_RTC_HSE_DIV_59
4207 * @arg @ref LL_RCC_RTC_HSE_DIV_60
4208 * @arg @ref LL_RCC_RTC_HSE_DIV_61
4209 * @arg @ref LL_RCC_RTC_HSE_DIV_62
4210 * @arg @ref LL_RCC_RTC_HSE_DIV_63
4211 */
4212 __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
4213 {
4214 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
4215 }
4216
4217 /**
4218 * @}
4219 */
4220
4221 /** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
4222 * @{
4223 */
4224
4225 /**
4226 * @brief Set Timers Clock Prescalers
4227 * @rmtoll CFGR TIMPRE LL_RCC_SetTIMPrescaler
4228 * @param Prescaler This parameter can be one of the following values:
4229 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE
4230 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
4231 * @retval None
4232 */
4233 __STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
4234 {
4235 MODIFY_REG(RCC->CFGR, RCC_CFGR_TIMPRE, Prescaler);
4236 }
4237
4238 /**
4239 * @brief Get Timers Clock Prescalers
4240 * @rmtoll CFGR TIMPRE LL_RCC_GetTIMPrescaler
4241 * @retval Returned value can be one of the following values:
4242 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE
4243 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
4244 */
4245 __STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
4246 {
4247 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_TIMPRE));
4248 }
4249
4250 /**
4251 * @}
4252 */
4253
4254 #if defined(HRTIM1)
4255 /** @defgroup RCC_LL_EF_HRTIM_SET_CLOCK_SOURCE HRTIM
4256 * @{
4257 */
4258
4259 /**
4260 * @brief Set High Resolution Timers Clock Source
4261 * @rmtoll CFGR HRTIMSEL LL_RCC_SetHRTIMClockSource
4262 * @param Prescaler This parameter can be one of the following values:
4263 * @arg @ref LL_RCC_HRTIM_CLKSOURCE_TIM
4264 * @arg @ref LL_RCC_HRTIM_CLKSOURCE_CPU
4265 * @retval None
4266 */
4267 __STATIC_INLINE void LL_RCC_SetHRTIMClockSource(uint32_t Prescaler)
4268 {
4269 MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, Prescaler);
4270 }
4271 #endif /* HRTIM1 */
4272
4273 #if defined(HRTIM1)
4274 /**
4275 * @brief Get High Resolution Timers Clock Source
4276 * @rmtoll CFGR HRTIMSEL LL_RCC_GetHRTIMClockSource
4277 * @retval Returned value can be one of the following values:
4278 * @arg @ref LL_RCC_HRTIM_CLKSOURCE_TIM
4279 * @arg @ref LL_RCC_HRTIM_CLKSOURCE_CPU
4280 */
4281 __STATIC_INLINE uint32_t LL_RCC_GetHRTIMClockSource(void)
4282 {
4283 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL));
4284 }
4285 /**
4286 * @}
4287 */
4288 #endif /* HRTIM1 */
4289
4290 /** @defgroup RCC_LL_EF_PLL PLL
4291 * @{
4292 */
4293
4294 /**
4295 * @brief Set the oscillator used as PLL clock source.
4296 * @note PLLSRC can be written only when All PLLs are disabled.
4297 * @rmtoll PLLCKSELR PLLSRC LL_RCC_PLL_SetSource
4298 * @param PLLSource parameter can be one of the following values:
4299 * @arg @ref LL_RCC_PLLSOURCE_HSI
4300 * @arg @ref LL_RCC_PLLSOURCE_CSI
4301 * @arg @ref LL_RCC_PLLSOURCE_HSE
4302 * @arg @ref LL_RCC_PLLSOURCE_NONE
4303 * @retval None
4304 */
4305 __STATIC_INLINE void LL_RCC_PLL_SetSource(uint32_t PLLSource)
4306 {
4307 MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, PLLSource);
4308 }
4309
4310 /**
4311 * @brief Get the oscillator used as PLL clock source.
4312 * @rmtoll PLLCKSELR PLLSRC LL_RCC_PLL_GetSource
4313 * @retval Returned value can be one of the following values:
4314 * @arg @ref LL_RCC_PLLSOURCE_HSI
4315 * @arg @ref LL_RCC_PLLSOURCE_CSI
4316 * @arg @ref LL_RCC_PLLSOURCE_HSE
4317 * @arg @ref LL_RCC_PLLSOURCE_NONE
4318 */
4319 __STATIC_INLINE uint32_t LL_RCC_PLL_GetSource(void)
4320 {
4321 return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC));
4322 }
4323
4324 /**
4325 * @brief Enable PLL1
4326 * @rmtoll CR PLL1ON LL_RCC_PLL1_Enable
4327 * @retval None
4328 */
4329 __STATIC_INLINE void LL_RCC_PLL1_Enable(void)
4330 {
4331 SET_BIT(RCC->CR, RCC_CR_PLL1ON);
4332 }
4333
4334 /**
4335 * @brief Disable PLL1
4336 * @note Cannot be disabled if the PLL1 clock is used as the system clock
4337 * @rmtoll CR PLL1ON LL_RCC_PLL1_Disable
4338 * @retval None
4339 */
4340 __STATIC_INLINE void LL_RCC_PLL1_Disable(void)
4341 {
4342 CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);
4343 }
4344
4345 /**
4346 * @brief Check if PLL1 Ready
4347 * @rmtoll CR PLL1RDY LL_RCC_PLL1_IsReady
4348 * @retval State of bit (1 or 0).
4349 */
4350 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void)
4351 {
4352 return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == (RCC_CR_PLL1RDY))?1UL:0UL);
4353 }
4354
4355 /**
4356 * @brief Enable PLL1P
4357 * @note This API shall be called only when PLL1 is disabled.
4358 * @rmtoll PLLCFGR DIVP1EN LL_RCC_PLL1P_Enable
4359 * @retval None
4360 */
4361 __STATIC_INLINE void LL_RCC_PLL1P_Enable(void)
4362 {
4363 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN);
4364 }
4365
4366 /**
4367 * @brief Enable PLL1Q
4368 * @note This API shall be called only when PLL1 is disabled.
4369 * @rmtoll PLLCFGR DIVQ1EN LL_RCC_PLL1Q_Enable
4370 * @retval None
4371 */
4372 __STATIC_INLINE void LL_RCC_PLL1Q_Enable(void)
4373 {
4374 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN);
4375 }
4376
4377 /**
4378 * @brief Enable PLL1R
4379 * @note This API shall be called only when PLL1 is disabled.
4380 * @rmtoll PLLCFGR DIVR1EN LL_RCC_PLL1R_Enable
4381 * @retval None
4382 */
4383 __STATIC_INLINE void LL_RCC_PLL1R_Enable(void)
4384 {
4385 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN);
4386 }
4387
4388 /**
4389 * @brief Enable PLL1 FRACN
4390 * @rmtoll PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable
4391 * @retval None
4392 */
4393 __STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void)
4394 {
4395 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN);
4396 }
4397
4398 /**
4399 * @brief Check if PLL1 P is enabled
4400 * @rmtoll PLLCFGR DIVP1EN LL_RCC_PLL1P_IsEnabled
4401 * @retval State of bit (1 or 0).
4402 */
4403 __STATIC_INLINE uint32_t LL_RCC_PLL1P_IsEnabled(void)
4404 {
4405 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN) == RCC_PLLCFGR_DIVP1EN)?1UL:0UL);
4406 }
4407
4408 /**
4409 * @brief Check if PLL1 Q is enabled
4410 * @rmtoll PLLCFGR DIVQ1EN LL_RCC_PLL1Q_IsEnabled
4411 * @retval State of bit (1 or 0).
4412 */
4413 __STATIC_INLINE uint32_t LL_RCC_PLL1Q_IsEnabled(void)
4414 {
4415 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN) == RCC_PLLCFGR_DIVQ1EN)?1UL:0UL);
4416 }
4417
4418 /**
4419 * @brief Check if PLL1 R is enabled
4420 * @rmtoll PLLCFGR DIVR1EN LL_RCC_PLL1R_IsEnabled
4421 * @retval State of bit (1 or 0).
4422 */
4423 __STATIC_INLINE uint32_t LL_RCC_PLL1R_IsEnabled(void)
4424 {
4425 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN) == RCC_PLLCFGR_DIVR1EN)?1UL:0UL);
4426 }
4427
4428 /**
4429 * @brief Check if PLL1 FRACN is enabled
4430 * @rmtoll PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_IsEnabled
4431 * @retval State of bit (1 or 0).
4432 */
4433 __STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void)
4434 {
4435 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) == RCC_PLLCFGR_PLL1FRACEN)?1UL:0UL);
4436 }
4437
4438 /**
4439 * @brief Disable PLL1P
4440 * @note This API shall be called only when PLL1 is disabled.
4441 * @rmtoll PLLCFGR DIVP1EN LL_RCC_PLL1P_Disable
4442 * @retval None
4443 */
4444 __STATIC_INLINE void LL_RCC_PLL1P_Disable(void)
4445 {
4446 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN);
4447 }
4448
4449 /**
4450 * @brief Disable PLL1Q
4451 * @note This API shall be called only when PLL1 is disabled.
4452 * @rmtoll PLLCFGR DIVQ1EN LL_RCC_PLL1Q_Disable
4453 * @retval None
4454 */
4455 __STATIC_INLINE void LL_RCC_PLL1Q_Disable(void)
4456 {
4457 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN);
4458 }
4459
4460 /**
4461 * @brief Disable PLL1R
4462 * @note This API shall be called only when PLL1 is disabled.
4463 * @rmtoll PLLCFGR DIVR1EN LL_RCC_PLL1R_Disable
4464 * @retval None
4465 */
4466 __STATIC_INLINE void LL_RCC_PLL1R_Disable(void)
4467 {
4468 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN);
4469 }
4470
4471 /**
4472 * @brief Disable PLL1 FRACN
4473 * @rmtoll PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable
4474 * @retval None
4475 */
4476 __STATIC_INLINE void LL_RCC_PLL1FRACN_Disable(void)
4477 {
4478 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN);
4479 }
4480
4481 /**
4482 * @brief Set PLL1 VCO OutputRange
4483 * @note This API shall be called only when PLL1 is disabled.
4484 * @rmtoll PLLCFGR PLL1VCOSEL LL_RCC_PLL1_SetVCOOuputRange
4485 * @param VCORange This parameter can be one of the following values:
4486 * @arg @ref LL_RCC_PLLVCORANGE_WIDE
4487 * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
4488 * @retval None
4489 */
4490 __STATIC_INLINE void LL_RCC_PLL1_SetVCOOutputRange(uint32_t VCORange)
4491 {
4492 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, VCORange << RCC_PLLCFGR_PLL1VCOSEL_Pos);
4493 }
4494
4495 /**
4496 * @brief Set PLL1 VCO Input Range
4497 * @note This API shall be called only when PLL1 is disabled.
4498 * @rmtoll PLLCFGR PLL1RGE LL_RCC_PLL1_SetVCOInputRange
4499 * @param InputRange This parameter can be one of the following values:
4500 * @arg @ref LL_RCC_PLLINPUTRANGE_1_2
4501 * @arg @ref LL_RCC_PLLINPUTRANGE_2_4
4502 * @arg @ref LL_RCC_PLLINPUTRANGE_4_8
4503 * @arg @ref LL_RCC_PLLINPUTRANGE_8_16
4504 * @retval None
4505 */
4506 __STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange)
4507 {
4508 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, InputRange << RCC_PLLCFGR_PLL1RGE_Pos);
4509 }
4510
4511 /**
4512 * @brief Get PLL1 N Coefficient
4513 * @rmtoll PLL1DIVR N1 LL_RCC_PLL1_GetN
4514 * @retval A value between 4 and 512
4515 */
4516 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void)
4517 {
4518 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_N1) >> RCC_PLL1DIVR_N1_Pos) + 1UL);
4519 }
4520
4521 /**
4522 * @brief Get PLL1 M Coefficient
4523 * @rmtoll PLLCKSELR DIVM1 LL_RCC_PLL1_GetM
4524 * @retval A value between 0 and 63
4525 */
4526 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetM(void)
4527 {
4528 return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos);
4529 }
4530
4531 /**
4532 * @brief Get PLL1 P Coefficient
4533 * @rmtoll PLL1DIVR P1 LL_RCC_PLL1_GetP
4534 * @retval A value between 2 and 128
4535 */
4536 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void)
4537 {
4538 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) + 1UL);
4539 }
4540
4541 /**
4542 * @brief Get PLL1 Q Coefficient
4543 * @rmtoll PLL1DIVR Q1 LL_RCC_PLL1_GetQ
4544 * @retval A value between 1 and 128
4545 */
4546 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ(void)
4547 {
4548 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) + 1UL);
4549 }
4550
4551 /**
4552 * @brief Get PLL1 R Coefficient
4553 * @rmtoll PLL1DIVR R1 LL_RCC_PLL1_GetR
4554 * @retval A value between 1 and 128
4555 */
4556 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetR(void)
4557 {
4558 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) + 1UL);
4559 }
4560
4561 /**
4562 * @brief Get PLL1 FRACN Coefficient
4563 * @rmtoll PLL1FRACR FRACN1 LL_RCC_PLL1_GetFRACN
4564 * @retval A value between 0 and 8191 (0x1FFF)
4565 */
4566 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void)
4567 {
4568 return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos);
4569 }
4570
4571 /**
4572 * @brief Set PLL1 N Coefficient
4573 * @note This API shall be called only when PLL1 is disabled.
4574 * @rmtoll PLL1DIVR N1 LL_RCC_PLL1_SetN
4575 * @param N parameter can be a value between 4 and 512
4576 */
4577 __STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t N)
4578 {
4579 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_N1, (N-1UL) << RCC_PLL1DIVR_N1_Pos);
4580 }
4581
4582 /**
4583 * @brief Set PLL1 M Coefficient
4584 * @note This API shall be called only when PLL1 is disabled.
4585 * @rmtoll PLLCKSELR DIVM1 LL_RCC_PLL1_SetM
4586 * @param M parameter can be a value between 0 and 63
4587 */
4588 __STATIC_INLINE void LL_RCC_PLL1_SetM(uint32_t M)
4589 {
4590 MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1, M << RCC_PLLCKSELR_DIVM1_Pos);
4591 }
4592
4593 /**
4594 * @brief Set PLL1 P Coefficient
4595 * @note This API shall be called only when PLL1 is disabled.
4596 * @rmtoll PLL1DIVR P1 LL_RCC_PLL1_SetP
4597 * @param P parameter can be a value between 2 and 128 (ODD division factor not supportted)
4598 */
4599 __STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t P)
4600 {
4601 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_P1, (P-1UL) << RCC_PLL1DIVR_P1_Pos);
4602 }
4603
4604 /**
4605 * @brief Set PLL1 Q Coefficient
4606 * @note This API shall be called only when PLL1 is disabled.
4607 * @rmtoll PLL1DIVR Q1 LL_RCC_PLL1_SetQ
4608 * @param Q parameter can be a value between 1 and 128
4609 */
4610 __STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t Q)
4611 {
4612 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1, (Q-1UL) << RCC_PLL1DIVR_Q1_Pos);
4613 }
4614
4615 /**
4616 * @brief Set PLL1 R Coefficient
4617 * @note This API shall be called only when PLL1 is disabled.
4618 * @rmtoll PLL1DIVR R1 LL_RCC_PLL1_SetR
4619 * @param R parameter can be a value between 1 and 128
4620 */
4621 __STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t R)
4622 {
4623 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_R1, (R-1UL) << RCC_PLL1DIVR_R1_Pos);
4624 }
4625
4626 /**
4627 * @brief Set PLL1 FRACN Coefficient
4628 * @rmtoll PLL1FRACR FRACN1 LL_RCC_PLL1_SetFRACN
4629 * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF)
4630 */
4631 __STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN)
4632 {
4633 MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, FRACN << RCC_PLL1FRACR_FRACN1_Pos);
4634 }
4635
4636 /**
4637 * @brief Enable PLL2
4638 * @rmtoll CR PLL2ON LL_RCC_PLL2_Enable
4639 * @retval None
4640 */
4641 __STATIC_INLINE void LL_RCC_PLL2_Enable(void)
4642 {
4643 SET_BIT(RCC->CR, RCC_CR_PLL2ON);
4644 }
4645
4646 /**
4647 * @brief Disable PLL2
4648 * @note Cannot be disabled if the PLL2 clock is used as the system clock
4649 * @rmtoll CR PLL2ON LL_RCC_PLL2_Disable
4650 * @retval None
4651 */
4652 __STATIC_INLINE void LL_RCC_PLL2_Disable(void)
4653 {
4654 CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
4655 }
4656
4657 /**
4658 * @brief Check if PLL2 Ready
4659 * @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady
4660 * @retval State of bit (1 or 0).
4661 */
4662 __STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void)
4663 {
4664 return ((READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY))?1UL:0UL);
4665 }
4666
4667 /**
4668 * @brief Enable PLL2P
4669 * @note This API shall be called only when PLL2 is disabled.
4670 * @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL2P_Enable
4671 * @retval None
4672 */
4673 __STATIC_INLINE void LL_RCC_PLL2P_Enable(void)
4674 {
4675 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN);
4676 }
4677
4678 /**
4679 * @brief Enable PLL2Q
4680 * @note This API shall be called only when PLL2 is disabled.
4681 * @rmtoll PLLCFGR DIVQ2EN LL_RCC_PLL2Q_Enable
4682 * @retval None
4683 */
4684 __STATIC_INLINE void LL_RCC_PLL2Q_Enable(void)
4685 {
4686 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN);
4687 }
4688
4689 /**
4690 * @brief Enable PLL2R
4691 * @note This API shall be called only when PLL2 is disabled.
4692 * @rmtoll PLLCFGR DIVR2EN LL_RCC_PLL2R_Enable
4693 * @retval None
4694 */
4695 __STATIC_INLINE void LL_RCC_PLL2R_Enable(void)
4696 {
4697 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN);
4698 }
4699
4700 /**
4701 * @brief Enable PLL2 FRACN
4702 * @rmtoll PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_Enable
4703 * @retval None
4704 */
4705 __STATIC_INLINE void LL_RCC_PLL2FRACN_Enable(void)
4706 {
4707 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN);
4708 }
4709
4710 /**
4711 * @brief Check if PLL2 P is enabled
4712 * @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL2P_IsEnabled
4713 * @retval State of bit (1 or 0).
4714 */
4715 __STATIC_INLINE uint32_t LL_RCC_PLL2P_IsEnabled(void)
4716 {
4717 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN) == RCC_PLLCFGR_DIVP2EN)?1UL:0UL);
4718 }
4719
4720 /**
4721 * @brief Check if PLL2 Q is enabled
4722 * @rmtoll PLLCFGR DIVQ2EN LL_RCC_PLL2Q_IsEnabled
4723 * @retval State of bit (1 or 0).
4724 */
4725 __STATIC_INLINE uint32_t LL_RCC_PLL2Q_IsEnabled(void)
4726 {
4727 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN) == RCC_PLLCFGR_DIVQ2EN)?1UL:0UL);
4728 }
4729
4730 /**
4731 * @brief Check if PLL2 R is enabled
4732 * @rmtoll PLLCFGR DIVR2EN LL_RCC_PLL2R_IsEnabled
4733 * @retval State of bit (1 or 0).
4734 */
4735 __STATIC_INLINE uint32_t LL_RCC_PLL2R_IsEnabled(void)
4736 {
4737 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN) == RCC_PLLCFGR_DIVR2EN)?1UL:0UL);
4738 }
4739
4740 /**
4741 * @brief Check if PLL2 FRACN is enabled
4742 * @rmtoll PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_IsEnabled
4743 * @retval State of bit (1 or 0).
4744 */
4745 __STATIC_INLINE uint32_t LL_RCC_PLL2FRACN_IsEnabled(void)
4746 {
4747 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) == RCC_PLLCFGR_PLL2FRACEN)?1UL:0UL);
4748 }
4749
4750 /**
4751 * @brief Disable PLL2P
4752 * @note This API shall be called only when PLL2 is disabled.
4753 * @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL2P_Disable
4754 * @retval None
4755 */
4756 __STATIC_INLINE void LL_RCC_PLL2P_Disable(void)
4757 {
4758 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN);
4759 }
4760
4761 /**
4762 * @brief Disable PLL2Q
4763 * @note This API shall be called only when PLL2 is disabled.
4764 * @rmtoll PLLCFGR DIVQ2EN LL_RCC_PLL2Q_Disable
4765 * @retval None
4766 */
4767 __STATIC_INLINE void LL_RCC_PLL2Q_Disable(void)
4768 {
4769 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN);
4770 }
4771
4772 /**
4773 * @brief Disable PLL2R
4774 * @note This API shall be called only when PLL2 is disabled.
4775 * @rmtoll PLLCFGR DIVR2EN LL_RCC_PLL2R_Disable
4776 * @retval None
4777 */
4778 __STATIC_INLINE void LL_RCC_PLL2R_Disable(void)
4779 {
4780 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN);
4781 }
4782
4783 /**
4784 * @brief Disable PLL2 FRACN
4785 * @rmtoll PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_Enable
4786 * @retval None
4787 */
4788 __STATIC_INLINE void LL_RCC_PLL2FRACN_Disable(void)
4789 {
4790 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN);
4791 }
4792
4793 /**
4794 * @brief Set PLL2 VCO OutputRange
4795 * @note This API shall be called only when PLL2 is disabled.
4796 * @rmtoll PLLCFGR PLL2VCOSEL LL_RCC_PLL2_SetVCOOuputRange
4797 * @param VCORange This parameter can be one of the following values:
4798 * @arg @ref LL_RCC_PLLVCORANGE_WIDE
4799 * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
4800 * @retval None
4801 */
4802 __STATIC_INLINE void LL_RCC_PLL2_SetVCOOutputRange(uint32_t VCORange)
4803 {
4804 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, VCORange << RCC_PLLCFGR_PLL2VCOSEL_Pos);
4805 }
4806
4807 /**
4808 * @brief Set PLL2 VCO Input Range
4809 * @note This API shall be called only when PLL2 is disabled.
4810 * @rmtoll PLLCFGR PLL2RGE LL_RCC_PLL2_SetVCOInputRange
4811 * @param InputRange This parameter can be one of the following values:
4812 * @arg @ref LL_RCC_PLLINPUTRANGE_1_2
4813 * @arg @ref LL_RCC_PLLINPUTRANGE_2_4
4814 * @arg @ref LL_RCC_PLLINPUTRANGE_4_8
4815 * @arg @ref LL_RCC_PLLINPUTRANGE_8_16
4816 * @retval None
4817 */
4818 __STATIC_INLINE void LL_RCC_PLL2_SetVCOInputRange(uint32_t InputRange)
4819 {
4820 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, InputRange << RCC_PLLCFGR_PLL2RGE_Pos);
4821 }
4822
4823 /**
4824 * @brief Get PLL2 N Coefficient
4825 * @rmtoll PLL2DIVR N2 LL_RCC_PLL2_GetN
4826 * @retval A value between 4 and 512
4827 */
4828 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetN(void)
4829 {
4830 return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos) + 1UL);
4831 }
4832
4833 /**
4834 * @brief Get PLL2 M Coefficient
4835 * @rmtoll PLLCKSELR DIVM2 LL_RCC_PLL2_GetM
4836 * @retval A value between 0 and 63
4837 */
4838 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetM(void)
4839 {
4840 return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2) >> RCC_PLLCKSELR_DIVM2_Pos);
4841 }
4842
4843 /**
4844 * @brief Get PLL2 P Coefficient
4845 * @rmtoll PLL2DIVR P2 LL_RCC_PLL2_GetP
4846 * @retval A value between 1 and 128
4847 */
4848 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetP(void)
4849 {
4850 return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos) + 1UL);
4851 }
4852
4853 /**
4854 * @brief Get PLL2 Q Coefficient
4855 * @rmtoll PLL2DIVR Q2 LL_RCC_PLL2_GetQ
4856 * @retval A value between 1 and 128
4857 */
4858 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetQ(void)
4859 {
4860 return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos) + 1UL);
4861 }
4862
4863 /**
4864 * @brief Get PLL2 R Coefficient
4865 * @rmtoll PLL2DIVR R2 LL_RCC_PLL2_GetR
4866 * @retval A value between 1 and 128
4867 */
4868 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetR(void)
4869 {
4870 return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos) + 1UL);
4871 }
4872
4873 /**
4874 * @brief Get PLL2 FRACN Coefficient
4875 * @rmtoll PLL2FRACR FRACN2 LL_RCC_PLL2_GetFRACN
4876 * @retval A value between 0 and 8191 (0x1FFF)
4877 */
4878 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void)
4879 {
4880 return (uint32_t)(READ_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2) >> RCC_PLL2FRACR_FRACN2_Pos);
4881 }
4882
4883 /**
4884 * @brief Set PLL2 N Coefficient
4885 * @note This API shall be called only when PLL2 is disabled.
4886 * @rmtoll PLL2DIVR N2 LL_RCC_PLL2_SetN
4887 * @param N parameter can be a value between 4 and 512
4888 */
4889 __STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t N)
4890 {
4891 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_N2, (N-1UL) << RCC_PLL2DIVR_N2_Pos);
4892 }
4893
4894 /**
4895 * @brief Set PLL2 M Coefficient
4896 * @note This API shall be called only when PLL2 is disabled.
4897 * @rmtoll PLLCKSELR DIVM2 LL_RCC_PLL2_SetM
4898 * @param M parameter can be a value between 0 and 63
4899 */
4900 __STATIC_INLINE void LL_RCC_PLL2_SetM(uint32_t M)
4901 {
4902 MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2, M << RCC_PLLCKSELR_DIVM2_Pos);
4903 }
4904
4905 /**
4906 * @brief Set PLL2 P Coefficient
4907 * @note This API shall be called only when PLL2 is disabled.
4908 * @rmtoll PLL2DIVR P2 LL_RCC_PLL2_SetP
4909 * @param P parameter can be a value between 1 and 128
4910 */
4911 __STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t P)
4912 {
4913 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_P2, (P-1UL) << RCC_PLL2DIVR_P2_Pos);
4914 }
4915
4916 /**
4917 * @brief Set PLL2 Q Coefficient
4918 * @note This API shall be called only when PLL2 is disabled.
4919 * @rmtoll PLL2DIVR Q2 LL_RCC_PLL2_SetQ
4920 * @param Q parameter can be a value between 1 and 128
4921 */
4922 __STATIC_INLINE void LL_RCC_PLL2_SetQ(uint32_t Q)
4923 {
4924 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2, (Q-1UL) << RCC_PLL2DIVR_Q2_Pos);
4925 }
4926
4927 /**
4928 * @brief Set PLL2 R Coefficient
4929 * @note This API shall be called only when PLL2 is disabled.
4930 * @rmtoll PLL2DIVR R2 LL_RCC_PLL2_SetR
4931 * @param R parameter can be a value between 1 and 128
4932 */
4933 __STATIC_INLINE void LL_RCC_PLL2_SetR(uint32_t R)
4934 {
4935 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_R2, (R-1UL) << RCC_PLL2DIVR_R2_Pos);
4936 }
4937
4938 /**
4939 * @brief Set PLL2 FRACN Coefficient
4940 * @rmtoll PLL2FRACR FRACN2 LL_RCC_PLL2_SetFRACN
4941 * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF)
4942 */
4943 __STATIC_INLINE void LL_RCC_PLL2_SetFRACN(uint32_t FRACN)
4944 {
4945 MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2, FRACN << RCC_PLL2FRACR_FRACN2_Pos);
4946 }
4947
4948 /**
4949 * @brief Enable PLL3
4950 * @rmtoll CR PLL3ON LL_RCC_PLL3_Enable
4951 * @retval None
4952 */
4953 __STATIC_INLINE void LL_RCC_PLL3_Enable(void)
4954 {
4955 SET_BIT(RCC->CR, RCC_CR_PLL3ON);
4956 }
4957
4958 /**
4959 * @brief Disable PLL3
4960 * @note Cannot be disabled if the PLL3 clock is used as the system clock
4961 * @rmtoll CR PLL3ON LL_RCC_PLL3_Disable
4962 * @retval None
4963 */
4964 __STATIC_INLINE void LL_RCC_PLL3_Disable(void)
4965 {
4966 CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
4967 }
4968
4969 /**
4970 * @brief Check if PLL3 Ready
4971 * @rmtoll CR PLL3RDY LL_RCC_PLL3_IsReady
4972 * @retval State of bit (1 or 0).
4973 */
4974 __STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void)
4975 {
4976 return ((READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY))?1UL:0UL);
4977 }
4978
4979 /**
4980 * @brief Enable PLL3P
4981 * @note This API shall be called only when PLL3 is disabled.
4982 * @rmtoll PLLCFGR DIVP3EN LL_RCC_PLL3P_Enable
4983 * @retval None
4984 */
4985 __STATIC_INLINE void LL_RCC_PLL3P_Enable(void)
4986 {
4987 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN);
4988 }
4989
4990 /**
4991 * @brief Enable PLL3Q
4992 * @note This API shall be called only when PLL3 is disabled.
4993 * @rmtoll PLLCFGR DIVQ3EN LL_RCC_PLL3Q_Enable
4994 * @retval None
4995 */
4996 __STATIC_INLINE void LL_RCC_PLL3Q_Enable(void)
4997 {
4998 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN);
4999 }
5000
5001 /**
5002 * @brief Enable PLL3R
5003 * @note This API shall be called only when PLL3 is disabled.
5004 * @rmtoll PLLCFGR DIVR3EN LL_RCC_PLL3R_Enable
5005 * @retval None
5006 */
5007 __STATIC_INLINE void LL_RCC_PLL3R_Enable(void)
5008 {
5009 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN);
5010 }
5011
5012 /**
5013 * @brief Enable PLL3 FRACN
5014 * @rmtoll PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_Enable
5015 * @retval None
5016 */
5017 __STATIC_INLINE void LL_RCC_PLL3FRACN_Enable(void)
5018 {
5019 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN);
5020 }
5021
5022 /**
5023 * @brief Check if PLL3 P is enabled
5024 * @rmtoll PLLCFGR DIVP3EN LL_RCC_PLL3P_IsEnabled
5025 * @retval State of bit (1 or 0).
5026 */
5027 __STATIC_INLINE uint32_t LL_RCC_PLL3P_IsEnabled(void)
5028 {
5029 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN) == RCC_PLLCFGR_DIVP3EN)?1UL:0UL);
5030 }
5031
5032 /**
5033 * @brief Check if PLL3 Q is enabled
5034 * @rmtoll PLLCFGR DIVQ3EN LL_RCC_PLL3Q_IsEnabled
5035 * @retval State of bit (1 or 0).
5036 */
5037 __STATIC_INLINE uint32_t LL_RCC_PLL3Q_IsEnabled(void)
5038 {
5039 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN) == RCC_PLLCFGR_DIVQ3EN)?1UL:0UL);
5040 }
5041
5042 /**
5043 * @brief Check if PLL3 R is enabled
5044 * @rmtoll PLLCFGR DIVR3EN LL_RCC_PLL3R_IsEnabled
5045 * @retval State of bit (1 or 0).
5046 */
5047 __STATIC_INLINE uint32_t LL_RCC_PLL3R_IsEnabled(void)
5048 {
5049 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN) == RCC_PLLCFGR_DIVR3EN)?1UL:0UL);
5050 }
5051
5052 /**
5053 * @brief Check if PLL3 FRACN is enabled
5054 * @rmtoll PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_IsEnabled
5055 * @retval State of bit (1 or 0).
5056 */
5057 __STATIC_INLINE uint32_t LL_RCC_PLL3FRACN_IsEnabled(void)
5058 {
5059 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) == RCC_PLLCFGR_PLL3FRACEN)?1UL:0UL);
5060 }
5061
5062 /**
5063 * @brief Disable PLL3P
5064 * @note This API shall be called only when PLL3 is disabled.
5065 * @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL3P_Disable
5066 * @retval None
5067 */
5068 __STATIC_INLINE void LL_RCC_PLL3P_Disable(void)
5069 {
5070 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN);
5071 }
5072
5073 /**
5074 * @brief Disable PLL3Q
5075 * @note This API shall be called only when PLL3 is disabled.
5076 * @rmtoll PLLCFGR DIVQ3EN LL_RCC_PLL3Q_Disable
5077 * @retval None
5078 */
5079 __STATIC_INLINE void LL_RCC_PLL3Q_Disable(void)
5080 {
5081 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN);
5082 }
5083
5084 /**
5085 * @brief Disable PLL3R
5086 * @note This API shall be called only when PLL3 is disabled.
5087 * @rmtoll PLLCFGR DIVR3EN LL_RCC_PLL3R_Disable
5088 * @retval None
5089 */
5090 __STATIC_INLINE void LL_RCC_PLL3R_Disable(void)
5091 {
5092 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN);
5093 }
5094
5095 /**
5096 * @brief Disable PLL3 FRACN
5097 * @rmtoll PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_Enable
5098 * @retval None
5099 */
5100 __STATIC_INLINE void LL_RCC_PLL3FRACN_Disable(void)
5101 {
5102 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN);
5103 }
5104
5105 /**
5106 * @brief Set PLL3 VCO OutputRange
5107 * @note This API shall be called only when PLL3 is disabled.
5108 * @rmtoll PLLCFGR PLL3VCOSEL LL_RCC_PLL3_SetVCOOuputRange
5109 * @param VCORange This parameter can be one of the following values:
5110 * @arg @ref LL_RCC_PLLVCORANGE_WIDE
5111 * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
5112 * @retval None
5113 */
5114 __STATIC_INLINE void LL_RCC_PLL3_SetVCOOutputRange(uint32_t VCORange)
5115 {
5116 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, VCORange << RCC_PLLCFGR_PLL3VCOSEL_Pos);
5117 }
5118
5119 /**
5120 * @brief Set PLL3 VCO Input Range
5121 * @note This API shall be called only when PLL3 is disabled.
5122 * @rmtoll PLLCFGR PLL3RGE LL_RCC_PLL3_SetVCOInputRange
5123 * @param InputRange This parameter can be one of the following values:
5124 * @arg @ref LL_RCC_PLLINPUTRANGE_1_2
5125 * @arg @ref LL_RCC_PLLINPUTRANGE_2_4
5126 * @arg @ref LL_RCC_PLLINPUTRANGE_4_8
5127 * @arg @ref LL_RCC_PLLINPUTRANGE_8_16
5128 * @retval None
5129 */
5130 __STATIC_INLINE void LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange)
5131 {
5132 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, InputRange << RCC_PLLCFGR_PLL3RGE_Pos);
5133 }
5134
5135 /**
5136 * @brief Get PLL3 N Coefficient
5137 * @rmtoll PLL3DIVR N3 LL_RCC_PLL3_GetN
5138 * @retval A value between 4 and 512
5139 */
5140 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetN(void)
5141 {
5142 return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos) + 1UL);
5143 }
5144
5145 /**
5146 * @brief Get PLL3 M Coefficient
5147 * @rmtoll PLLCKSELR DIVM3 LL_RCC_PLL3_GetM
5148 * @retval A value between 0 and 63
5149 */
5150 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetM(void)
5151 {
5152 return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3) >> RCC_PLLCKSELR_DIVM3_Pos);
5153 }
5154
5155 /**
5156 * @brief Get PLL3 P Coefficient
5157 * @rmtoll PLL3DIVR P3 LL_RCC_PLL3_GetP
5158 * @retval A value between 1 and 128
5159 */
5160 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetP(void)
5161 {
5162 return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos) + 1UL);
5163 }
5164
5165 /**
5166 * @brief Get PLL3 Q Coefficient
5167 * @rmtoll PLL3DIVR Q3 LL_RCC_PLL3_GetQ
5168 * @retval A value between 1 and 128
5169 */
5170 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetQ(void)
5171 {
5172 return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos) + 1UL);
5173 }
5174
5175 /**
5176 * @brief Get PLL3 R Coefficient
5177 * @rmtoll PLL3DIVR R3 LL_RCC_PLL3_GetR
5178 * @retval A value between 1 and 128
5179 */
5180 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetR(void)
5181 {
5182 return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos) + 1UL);
5183 }
5184
5185 /**
5186 * @brief Get PLL3 FRACN Coefficient
5187 * @rmtoll PLL3FRACR FRACN3 LL_RCC_PLL3_GetFRACN
5188 * @retval A value between 0 and 8191 (0x1FFF)
5189 */
5190 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void)
5191 {
5192 return (uint32_t)(READ_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3) >> RCC_PLL3FRACR_FRACN3_Pos);
5193 }
5194
5195 /**
5196 * @brief Set PLL3 N Coefficient
5197 * @note This API shall be called only when PLL3 is disabled.
5198 * @rmtoll PLL3DIVR N3 LL_RCC_PLL3_SetN
5199 * @param N parameter can be a value between 4 and 512
5200 */
5201 __STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t N)
5202 {
5203 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_N3, (N-1UL) << RCC_PLL3DIVR_N3_Pos);
5204 }
5205
5206 /**
5207 * @brief Set PLL3 M Coefficient
5208 * @note This API shall be called only when PLL3 is disabled.
5209 * @rmtoll PLLCKSELR DIVM3 LL_RCC_PLL3_SetM
5210 * @param M parameter can be a value between 0 and 63
5211 */
5212 __STATIC_INLINE void LL_RCC_PLL3_SetM(uint32_t M)
5213 {
5214 MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3, M << RCC_PLLCKSELR_DIVM3_Pos);
5215 }
5216
5217 /**
5218 * @brief Set PLL3 P Coefficient
5219 * @note This API shall be called only when PLL3 is disabled.
5220 * @rmtoll PLL3DIVR P3 LL_RCC_PLL3_SetP
5221 * @param P parameter can be a value between 1 and 128
5222 */
5223 __STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t P)
5224 {
5225 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_P3, (P-1UL) << RCC_PLL3DIVR_P3_Pos);
5226 }
5227
5228 /**
5229 * @brief Set PLL3 Q Coefficient
5230 * @note This API shall be called only when PLL3 is disabled.
5231 * @rmtoll PLL3DIVR Q3 LL_RCC_PLL3_SetQ
5232 * @param Q parameter can be a value between 1 and 128
5233 */
5234 __STATIC_INLINE void LL_RCC_PLL3_SetQ(uint32_t Q)
5235 {
5236 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3, (Q-1UL) << RCC_PLL3DIVR_Q3_Pos);
5237 }
5238
5239 /**
5240 * @brief Set PLL3 R Coefficient
5241 * @note This API shall be called only when PLL3 is disabled.
5242 * @rmtoll PLL3DIVR R3 LL_RCC_PLL3_SetR
5243 * @param R parameter can be a value between 1 and 128
5244 */
5245 __STATIC_INLINE void LL_RCC_PLL3_SetR(uint32_t R)
5246 {
5247 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_R3, (R-1UL) << RCC_PLL3DIVR_R3_Pos);
5248 }
5249
5250 /**
5251 * @brief Set PLL3 FRACN Coefficient
5252 * @rmtoll PLL3FRACR FRACN3 LL_RCC_PLL3_SetFRACN
5253 * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF)
5254 */
5255 __STATIC_INLINE void LL_RCC_PLL3_SetFRACN(uint32_t FRACN)
5256 {
5257 MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, FRACN << RCC_PLL3FRACR_FRACN3_Pos);
5258 }
5259
5260
5261 /**
5262 * @}
5263 */
5264
5265
5266 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
5267 * @{
5268 */
5269
5270 /**
5271 * @brief Clear LSI ready interrupt flag
5272 * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
5273 * @retval None
5274 */
5275 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
5276 {
5277 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
5278 }
5279
5280 /**
5281 * @brief Clear LSE ready interrupt flag
5282 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
5283 * @retval None
5284 */
5285 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
5286 {
5287 SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
5288 }
5289
5290 /**
5291 * @brief Clear HSI ready interrupt flag
5292 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
5293 * @retval None
5294 */
5295 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
5296 {
5297 SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
5298 }
5299
5300 /**
5301 * @brief Clear HSE ready interrupt flag
5302 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
5303 * @retval None
5304 */
5305 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
5306 {
5307 SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
5308 }
5309
5310 /**
5311 * @brief Clear CSI ready interrupt flag
5312 * @rmtoll CICR CSIRDYC LL_RCC_ClearFlag_CSIRDY
5313 * @retval None
5314 */
5315 __STATIC_INLINE void LL_RCC_ClearFlag_CSIRDY(void)
5316 {
5317 SET_BIT(RCC->CICR, RCC_CICR_CSIRDYC);
5318 }
5319
5320 /**
5321 * @brief Clear HSI48 ready interrupt flag
5322 * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
5323 * @retval None
5324 */
5325 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
5326 {
5327 SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
5328 }
5329
5330 /**
5331 * @brief Clear PLL1 ready interrupt flag
5332 * @rmtoll CICR PLL1RDYC LL_RCC_ClearFlag_PLL1RDY
5333 * @retval None
5334 */
5335 __STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void)
5336 {
5337 SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
5338 }
5339
5340 /**
5341 * @brief Clear PLL2 ready interrupt flag
5342 * @rmtoll CICR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY
5343 * @retval None
5344 */
5345 __STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void)
5346 {
5347 SET_BIT(RCC->CICR, RCC_CICR_PLL2RDYC);
5348 }
5349
5350 /**
5351 * @brief Clear PLL3 ready interrupt flag
5352 * @rmtoll CICR PLL3RDYC LL_RCC_ClearFlag_PLL3RDY
5353 * @retval None
5354 */
5355 __STATIC_INLINE void LL_RCC_ClearFlag_PLL3RDY(void)
5356 {
5357 SET_BIT(RCC->CICR, RCC_CICR_PLL3RDYC);
5358 }
5359
5360 /**
5361 * @brief Clear LSE Clock security system interrupt flag
5362 * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
5363 * @retval None
5364 */
5365 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
5366 {
5367 SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
5368 }
5369
5370 /**
5371 * @brief Clear HSE Clock security system interrupt flag
5372 * @rmtoll CICR HSECSSC LL_RCC_ClearFlag_HSECSS
5373 * @retval None
5374 */
5375 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
5376 {
5377 SET_BIT(RCC->CICR, RCC_CICR_HSECSSC);
5378 }
5379
5380 /**
5381 * @brief Check if LSI ready interrupt occurred or not
5382 * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
5383 * @retval State of bit (1 or 0).
5384 */
5385 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
5386 {
5387 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF))?1UL:0UL);
5388 }
5389
5390 /**
5391 * @brief Check if LSE ready interrupt occurred or not
5392 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
5393 * @retval State of bit (1 or 0).
5394 */
5395 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
5396 {
5397 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF))?1UL:0UL);
5398 }
5399
5400 /**
5401 * @brief Check if HSI ready interrupt occurred or not
5402 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
5403 * @retval State of bit (1 or 0).
5404 */
5405 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
5406 {
5407 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF))?1UL:0UL);
5408 }
5409
5410 /**
5411 * @brief Check if HSE ready interrupt occurred or not
5412 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
5413 * @retval State of bit (1 or 0).
5414 */
5415 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
5416 {
5417 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF))?1UL:0UL);
5418 }
5419
5420 /**
5421 * @brief Check if CSI ready interrupt occurred or not
5422 * @rmtoll CIFR CSIRDYF LL_RCC_IsActiveFlag_CSIRDY
5423 * @retval State of bit (1 or 0).
5424 */
5425 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CSIRDY(void)
5426 {
5427 return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSIRDYF) == (RCC_CIFR_CSIRDYF))?1UL:0UL);
5428 }
5429
5430 /**
5431 * @brief Check if HSI48 ready interrupt occurred or not
5432 * @rmtoll CIFR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
5433 * @retval State of bit (1 or 0).
5434 */
5435 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
5436 {
5437 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF))?1UL:0UL);
5438 }
5439
5440 /**
5441 * @brief Check if PLL1 ready interrupt occurred or not
5442 * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLL1RDY
5443 * @retval State of bit (1 or 0).
5444 */
5445 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void)
5446 {
5447 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF))?1UL:0UL);
5448 }
5449
5450 /**
5451 * @brief Check if PLL2 ready interrupt occurred or not
5452 * @rmtoll CIFR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY
5453 * @retval State of bit (1 or 0).
5454 */
5455 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void)
5456 {
5457 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == (RCC_CIFR_PLL2RDYF))?1UL:0UL);
5458 }
5459
5460 /**
5461 * @brief Check if PLL3 ready interrupt occurred or not
5462 * @rmtoll CIFR PLL3RDYF LL_RCC_IsActiveFlag_PLL3RDY
5463 * @retval State of bit (1 or 0).
5464 */
5465 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void)
5466 {
5467 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == (RCC_CIFR_PLL3RDYF))?1UL:0UL);
5468 }
5469
5470 /**
5471 * @brief Check if LSE Clock security system interrupt occurred or not
5472 * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
5473 * @retval State of bit (1 or 0).
5474 */
5475 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
5476 {
5477 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF))?1UL:0UL);
5478 }
5479
5480 /**
5481 * @brief Check if HSE Clock security system interrupt occurred or not
5482 * @rmtoll CIFR HSECSSF LL_RCC_IsActiveFlag_HSECSS
5483 * @retval State of bit (1 or 0).
5484 */
5485 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
5486 {
5487 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == (RCC_CIFR_HSECSSF))?1UL:0UL);
5488 }
5489
5490 /**
5491 * @brief Check if RCC flag Low Power D1 reset is set or not.
5492 * @rmtoll RSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST (*)\n
5493 * RSR LPWR1RSTF LL_RCC_IsActiveFlag_LPWRRST (**)
5494 *
5495 * (*) Only available for single core devices
5496 * (**) Only available for Dual core devices
5497 * @retval State of bit (1 or 0).
5498 */
5499 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
5500 {
5501 #if defined(DUAL_CORE)
5502 return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL);
5503 #else
5504 return ((READ_BIT(RCC->RSR, RCC_RSR_LPWRRSTF) == (RCC_RSR_LPWRRSTF))?1UL:0UL);
5505 #endif /*DUAL_CORE*/
5506 }
5507
5508 #if defined(DUAL_CORE)
5509 /**
5510 * @brief Check if RCC flag Low Power D2 reset is set or not.
5511 * @rmtoll RSR LPWR2RSTF LL_RCC_IsActiveFlag_LPWR2RST
5512 * @retval State of bit (1 or 0).
5513 */
5514 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWR2RST(void)
5515 {
5516 return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL);
5517 }
5518 #endif /*DUAL_CORE*/
5519
5520 /**
5521 * @brief Check if RCC flag Window Watchdog 1 reset is set or not.
5522 * @rmtoll RSR WWDG1RSTF LL_RCC_IsActiveFlag_WWDG1RST
5523 * @retval State of bit (1 or 0).
5524 */
5525 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG1RST(void)
5526 {
5527 return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL);
5528 }
5529
5530 #if defined(DUAL_CORE)
5531 /**
5532 * @brief Check if RCC flag Window Watchdog 2 reset is set or not.
5533 * @rmtoll RSR WWDG2RSTF LL_RCC_IsActiveFlag_WWDG2RST
5534 * @retval State of bit (1 or 0).
5535 */
5536 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG2RST(void)
5537 {
5538 return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL);
5539 }
5540 #endif /*DUAL_CORE*/
5541
5542 /**
5543 * @brief Check if RCC flag Independent Watchdog 1 reset is set or not.
5544 * @rmtoll RSR IWDG1RSTF LL_RCC_IsActiveFlag_IWDG1RST
5545 * @retval State of bit (1 or 0).
5546 */
5547 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG1RST(void)
5548 {
5549 return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL);
5550 }
5551
5552 #if defined(DUAL_CORE)
5553 /**
5554 * @brief Check if RCC flag Independent Watchdog 2 reset is set or not.
5555 * @rmtoll RSR IWDG2RSTF LL_RCC_IsActiveFlag_IWDG2RST
5556 * @retval State of bit (1 or 0).
5557 */
5558 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG2RST(void)
5559 {
5560 return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL);
5561 }
5562 #endif /*DUAL_CORE*/
5563
5564 /**
5565 * @brief Check if RCC flag Software reset is set or not.
5566 * @rmtoll RSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST (*)\n
5567 * RSR SFT1RSTF LL_RCC_IsActiveFlag_SFTRST (**)
5568 *
5569 * (*) Only available for single core devices
5570 * (**) Only available for Dual core devices
5571 * @retval State of bit (1 or 0).
5572 */
5573 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
5574 {
5575 #if defined(DUAL_CORE)
5576 return ((READ_BIT(RCC->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL);
5577 #else
5578 return ((READ_BIT(RCC->RSR, RCC_RSR_SFTRSTF) == (RCC_RSR_SFTRSTF))?1UL:0UL);
5579 #endif /*DUAL_CORE*/
5580 }
5581
5582 #if defined(DUAL_CORE)
5583 /**
5584 * @brief Check if RCC flag Software reset is set or not.
5585 * @rmtoll RSR SFT2RSTF LL_RCC_IsActiveFlag_SFT2RST
5586 * @retval State of bit (1 or 0).
5587 */
5588 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFT2RST(void)
5589 {
5590 return ((READ_BIT(RCC->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL);
5591 }
5592 #endif /*DUAL_CORE*/
5593
5594 /**
5595 * @brief Check if RCC flag POR/PDR reset is set or not.
5596 * @rmtoll RSR PORRSTF LL_RCC_IsActiveFlag_PORRST
5597 * @retval State of bit (1 or 0).
5598 */
5599 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
5600 {
5601 return ((READ_BIT(RCC->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL);
5602 }
5603
5604 /**
5605 * @brief Check if RCC flag Pin reset is set or not.
5606 * @rmtoll RSR PINRSTF LL_RCC_IsActiveFlag_PINRST
5607 * @retval State of bit (1 or 0).
5608 */
5609 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
5610 {
5611 return ((READ_BIT(RCC->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL);
5612 }
5613
5614 /**
5615 * @brief Check if RCC flag BOR reset is set or not.
5616 * @rmtoll RSR BORRSTF LL_RCC_IsActiveFlag_BORRST
5617 * @retval State of bit (1 or 0).
5618 */
5619 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
5620 {
5621 return ((READ_BIT(RCC->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL);
5622 }
5623
5624 #if defined(RCC_RSR_D1RSTF)
5625 /**
5626 * @brief Check if RCC flag D1 reset is set or not.
5627 * @rmtoll RSR D1RSTF LL_RCC_IsActiveFlag_D1RST
5628 * @retval State of bit (1 or 0).
5629 */
5630 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D1RST(void)
5631 {
5632 return ((READ_BIT(RCC->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL);
5633 }
5634 #endif /* RCC_RSR_D1RSTF */
5635
5636 #if defined(RCC_RSR_CDRSTF)
5637 /**
5638 * @brief Check if RCC flag CD reset is set or not.
5639 * @rmtoll RSR CDRSTF LL_RCC_IsActiveFlag_CDRST
5640 * @retval State of bit (1 or 0).
5641 */
5642 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CDRST(void)
5643 {
5644 return ((READ_BIT(RCC->RSR, RCC_RSR_CDRSTF) == (RCC_RSR_CDRSTF))?1UL:0UL);
5645 }
5646 #endif /* RCC_RSR_CDRSTF */
5647
5648 #if defined(RCC_RSR_D2RSTF)
5649 /**
5650 * @brief Check if RCC flag D2 reset is set or not.
5651 * @rmtoll RSR D2RSTF LL_RCC_IsActiveFlag_D2RST
5652 * @retval State of bit (1 or 0).
5653 */
5654 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D2RST(void)
5655 {
5656 return ((READ_BIT(RCC->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL);
5657 }
5658 #endif /* RCC_RSR_D2RSTF */
5659
5660 #if defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF)
5661 /**
5662 * @brief Check if RCC flag CPU reset is set or not.
5663 * @rmtoll RSR CPURSTF LL_RCC_IsActiveFlag_CPURST (*)\n
5664 * RSR C1RSTF LL_RCC_IsActiveFlag_CPURST (**)
5665 *
5666 * (*) Only available for single core devices
5667 * (**) Only available for Dual core devices
5668 * @retval State of bit (1 or 0).
5669 */
5670 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPURST(void)
5671 {
5672 #if defined(DUAL_CORE)
5673 return ((READ_BIT(RCC->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL);
5674 #else
5675 return ((READ_BIT(RCC->RSR, RCC_RSR_CPURSTF) == (RCC_RSR_CPURSTF))?1UL:0UL);
5676 #endif/*DUAL_CORE*/
5677 }
5678 #endif /* defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF) */
5679
5680 #if defined(DUAL_CORE)
5681 /**
5682 * @brief Check if RCC flag CPU2 reset is set or not.
5683 * @rmtoll RSR C2RSTF LL_RCC_IsActiveFlag_CPU2RST
5684 * @retval State of bit (1 or 0).
5685 */
5686 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPU2RST(void)
5687 {
5688 return ((READ_BIT(RCC->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL);
5689 }
5690 #endif /*DUAL_CORE*/
5691
5692 /**
5693 * @brief Set RMVF bit to clear all reset flags.
5694 * @rmtoll RSR RMVF LL_RCC_ClearResetFlags
5695 * @retval None
5696 */
5697 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
5698 {
5699 SET_BIT(RCC->RSR, RCC_RSR_RMVF);
5700 }
5701
5702 #if defined(DUAL_CORE)
5703 /**
5704 * @brief Check if RCC_C1 flag Low Power D1 reset is set or not.
5705 * @rmtoll RSR LPWR1RSTF LL_C1_RCC_IsActiveFlag_LPWRRST
5706 * @retval State of bit (1 or 0).
5707 */
5708 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWRRST(void)
5709 {
5710 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL);
5711 }
5712
5713 /**
5714 * @brief Check if RCC_C1 flag Low Power D2 reset is set or not.
5715 * @rmtoll RSR LPWR2RSTF LL_C1_RCC_IsActiveFlag_LPWR2RST
5716 * @retval State of bit (1 or 0).
5717 */
5718 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWR2RST(void)
5719 {
5720 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL);
5721 }
5722
5723 /**
5724 * @brief Check if RCC_C1 flag Window Watchdog 1 reset is set or not.
5725 * @rmtoll RSR WWDG1RSTF LL_C1_RCC_IsActiveFlag_WWDG1RST
5726 * @retval State of bit (1 or 0).
5727 */
5728 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG1RST(void)
5729 {
5730 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL);
5731 }
5732
5733 /**
5734 * @brief Check if RCC_C1 flag Window Watchdog 2 reset is set or not.
5735 * @rmtoll RSR WWDG2RSTF LL_C1_RCC_IsActiveFlag_WWDG2RST
5736 * @retval State of bit (1 or 0).
5737 */
5738 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG2RST(void)
5739 {
5740 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL);
5741 }
5742
5743 /**
5744 * @brief Check if RCC_C1 flag Independent Watchdog 1 reset is set or not.
5745 * @rmtoll RSR IWDG1RSTF LL_C1_RCC_IsActiveFlag_IWDG1RST
5746 * @retval State of bit (1 or 0).
5747 */
5748 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG1RST(void)
5749 {
5750 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL);
5751 }
5752
5753 /**
5754 * @brief Check if RCC_C1 flag Independent Watchdog 2 reset is set or not.
5755 * @rmtoll RSR IWDG2RSTF LL_C1_RCC_IsActiveFlag_IWDG2RST
5756 * @retval State of bit (1 or 0).
5757 */
5758 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG2RST(void)
5759 {
5760 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL);
5761 }
5762
5763 /**
5764 * @brief Check if RCC_C1 flag Software reset is set or not.
5765 * @rmtoll RSR SFT1RSTF LL_C1_RCC_IsActiveFlag_SFTRST
5766 * @retval State of bit (1 or 0).
5767 */
5768 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFTRST(void)
5769 {
5770 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL);
5771 }
5772
5773 /**
5774 * @brief Check if RCC_C1 flag Software reset is set or not.
5775 * @rmtoll RSR SFT2RSTF LL_C1_RCC_IsActiveFlag_SFT2RST
5776 * @retval State of bit (1 or 0).
5777 */
5778 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFT2RST(void)
5779 {
5780 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL);
5781 }
5782
5783 /**
5784 * @brief Check if RCC_C1 flag POR/PDR reset is set or not.
5785 * @rmtoll RSR PORRSTF LL_C1_RCC_IsActiveFlag_PORRST
5786 * @retval State of bit (1 or 0).
5787 */
5788 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PORRST(void)
5789 {
5790 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL);
5791 }
5792
5793 /**
5794 * @brief Check if RCC_C1 flag Pin reset is set or not.
5795 * @rmtoll RSR PINRSTF LL_C1_RCC_IsActiveFlag_PINRST
5796 * @retval State of bit (1 or 0).
5797 */
5798 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PINRST(void)
5799 {
5800 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL);
5801 }
5802
5803 /**
5804 * @brief Check if RCC_C1 flag BOR reset is set or not.
5805 * @rmtoll RSR BORRSTF LL_C1_RCC_IsActiveFlag_BORRST
5806 * @retval State of bit (1 or 0).
5807 */
5808 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_BORRST(void)
5809 {
5810 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL);
5811 }
5812
5813 /**
5814 * @brief Check if RCC_C1 flag D1 reset is set or not.
5815 * @rmtoll RSR D1RSTF LL_C1_RCC_IsActiveFlag_D1RST
5816 * @retval State of bit (1 or 0).
5817 */
5818 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D1RST(void)
5819 {
5820 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL);
5821 }
5822
5823 /**
5824 * @brief Check if RCC_C1 flag D2 reset is set or not.
5825 * @rmtoll RSR D2RSTF LL_C1_RCC_IsActiveFlag_D2RST
5826 * @retval State of bit (1 or 0).
5827 */
5828 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D2RST(void)
5829 {
5830 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL);
5831 }
5832
5833 /**
5834 * @brief Check if RCC_C1 flag CPU reset is set or not.
5835 * @rmtoll RSR C1RSTF LL_C1_RCC_IsActiveFlag_CPURST
5836 * @retval State of bit (1 or 0).
5837 */
5838 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPURST(void)
5839 {
5840 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL);
5841 }
5842
5843 /**
5844 * @brief Check if RCC_C1 flag CPU2 reset is set or not.
5845 * @rmtoll RSR C2RSTF LL_C1_RCC_IsActiveFlag_CPU2RST
5846 * @retval State of bit (1 or 0).
5847 */
5848 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPU2RST(void)
5849 {
5850 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL);
5851 }
5852
5853 /**
5854 * @brief Set RMVF bit to clear the reset flags.
5855 * @rmtoll RSR RMVF LL_C1_RCC_ClearResetFlags
5856 * @retval None
5857 */
5858 __STATIC_INLINE void LL_C1_RCC_ClearResetFlags(void)
5859 {
5860 SET_BIT(RCC_C1->RSR, RCC_RSR_RMVF);
5861 }
5862
5863 /**
5864 * @brief Check if RCC_C2 flag Low Power D1 reset is set or not.
5865 * @rmtoll RSR LPWR1RSTF LL_C2_RCC_IsActiveFlag_LPWRRST
5866 * @retval State of bit (1 or 0).
5867 */
5868 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWRRST(void)
5869 {
5870 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL);
5871 }
5872
5873 /**
5874 * @brief Check if RCC_C2 flag Low Power D2 reset is set or not.
5875 * @rmtoll RSR LPWR2RSTF LL_C2_RCC_IsActiveFlag_LPWR2RST
5876 * @retval State of bit (1 or 0).
5877 */
5878 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWR2RST(void)
5879 {
5880 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL);
5881 }
5882
5883 /**
5884 * @brief Check if RCC_C2 flag Window Watchdog 1 reset is set or not.
5885 * @rmtoll RSR WWDG1RSTF LL_C2_RCC_IsActiveFlag_WWDG1RST
5886 * @retval State of bit (1 or 0).
5887 */
5888 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG1RST(void)
5889 {
5890 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL);
5891 }
5892
5893 /**
5894 * @brief Check if RCC_C2 flag Window Watchdog 2 reset is set or not.
5895 * @rmtoll RSR WWDG2RSTF LL_C2_RCC_IsActiveFlag_WWDG2RST
5896 * @retval State of bit (1 or 0).
5897 */
5898 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG2RST(void)
5899 {
5900 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL);
5901 }
5902
5903 /**
5904 * @brief Check if RCC_C2 flag Independent Watchdog 1 reset is set or not.
5905 * @rmtoll RSR IWDG1RSTF LL_C2_RCC_IsActiveFlag_IWDG1RST
5906 * @retval State of bit (1 or 0).
5907 */
5908 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG1RST(void)
5909 {
5910 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL);
5911 }
5912
5913 /**
5914 * @brief Check if RCC_C2 flag Independent Watchdog 2 reset is set or not.
5915 * @rmtoll RSR IWDG2RSTF LL_C2_RCC_IsActiveFlag_IWDG2RST
5916 * @retval State of bit (1 or 0).
5917 */
5918 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG2RST(void)
5919 {
5920 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL);
5921 }
5922
5923 /**
5924 * @brief Check if RCC_C2 flag Software reset is set or not.
5925 * @rmtoll RSR SFT1RSTF LL_C2_RCC_IsActiveFlag_SFTRST
5926 * @retval State of bit (1 or 0).
5927 */
5928 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFTRST(void)
5929 {
5930 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL);
5931 }
5932
5933 /**
5934 * @brief Check if RCC_C2 flag Software reset is set or not.
5935 * @rmtoll RSR SFT2RSTF LL_C2_RCC_IsActiveFlag_SFT2RST
5936 * @retval State of bit (1 or 0).
5937 */
5938 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFT2RST(void)
5939 {
5940 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL);
5941 }
5942
5943 /**
5944 * @brief Check if RCC_C2 flag POR/PDR reset is set or not.
5945 * @rmtoll RSR PORRSTF LL_C2_RCC_IsActiveFlag_PORRST
5946 * @retval State of bit (1 or 0).
5947 */
5948 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PORRST(void)
5949 {
5950 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL);
5951 }
5952
5953 /**
5954 * @brief Check if RCC_C2 flag Pin reset is set or not.
5955 * @rmtoll RSR PINRSTF LL_C2_RCC_IsActiveFlag_PINRST
5956 * @retval State of bit (1 or 0).
5957 */
5958 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PINRST(void)
5959 {
5960 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL);
5961 }
5962
5963 /**
5964 * @brief Check if RCC_C2 flag BOR reset is set or not.
5965 * @rmtoll RSR BORRSTF LL_C2_RCC_IsActiveFlag_BORRST
5966 * @retval State of bit (1 or 0).
5967 */
5968 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_BORRST(void)
5969 {
5970 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL);
5971 }
5972
5973 /**
5974 * @brief Check if RCC_C2 flag D1 reset is set or not.
5975 * @rmtoll RSR D1RSTF LL_C2_RCC_IsActiveFlag_D1RST
5976 * @retval State of bit (1 or 0).
5977 */
5978 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D1RST(void)
5979 {
5980 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL);
5981 }
5982
5983 /**
5984 * @brief Check if RCC_C2 flag D2 reset is set or not.
5985 * @rmtoll RSR D2RSTF LL_C2_RCC_IsActiveFlag_D2RST
5986 * @retval State of bit (1 or 0).
5987 */
5988 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D2RST(void)
5989 {
5990 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL);
5991 }
5992
5993 /**
5994 * @brief Check if RCC_C2 flag CPU reset is set or not.
5995 * @rmtoll RSR C1RSTF LL_C2_RCC_IsActiveFlag_CPURST
5996 * @retval State of bit (1 or 0).
5997 */
5998 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPURST(void)
5999 {
6000 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL);
6001 }
6002
6003 /**
6004 * @brief Check if RCC_C2 flag CPU2 reset is set or not.
6005 * @rmtoll RSR C2RSTF LL_C2_RCC_IsActiveFlag_CPU2RST
6006 * @retval State of bit (1 or 0).
6007 */
6008 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPU2RST(void)
6009 {
6010 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL);
6011 }
6012
6013 /**
6014 * @brief Set RMVF bit to clear the reset flags.
6015 * @rmtoll RSR RMVF LL_C2_RCC_ClearResetFlags
6016 * @retval None
6017 */
6018 __STATIC_INLINE void LL_C2_RCC_ClearResetFlags(void)
6019 {
6020 SET_BIT(RCC_C2->RSR, RCC_RSR_RMVF);
6021 }
6022 #endif /*DUAL_CORE*/
6023
6024 /**
6025 * @}
6026 */
6027
6028 /** @defgroup RCC_LL_EF_IT_Management IT Management
6029 * @{
6030 */
6031
6032 /**
6033 * @brief Enable LSI ready interrupt
6034 * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
6035 * @retval None
6036 */
6037 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
6038 {
6039 SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
6040 }
6041
6042 /**
6043 * @brief Enable LSE ready interrupt
6044 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
6045 * @retval None
6046 */
6047 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
6048 {
6049 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
6050 }
6051
6052 /**
6053 * @brief Enable HSI ready interrupt
6054 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
6055 * @retval None
6056 */
6057 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
6058 {
6059 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
6060 }
6061
6062 /**
6063 * @brief Enable HSE ready interrupt
6064 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
6065 * @retval None
6066 */
6067 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
6068 {
6069 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
6070 }
6071
6072 /**
6073 * @brief Enable CSI ready interrupt
6074 * @rmtoll CIER CSIRDYIE LL_RCC_EnableIT_CSIRDY
6075 * @retval None
6076 */
6077 __STATIC_INLINE void LL_RCC_EnableIT_CSIRDY(void)
6078 {
6079 SET_BIT(RCC->CIER, RCC_CIER_CSIRDYIE);
6080 }
6081
6082 /**
6083 * @brief Enable HSI48 ready interrupt
6084 * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
6085 * @retval None
6086 */
6087 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
6088 {
6089 SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
6090 }
6091
6092 /**
6093 * @brief Enable PLL1 ready interrupt
6094 * @rmtoll CIER PLL1RDYIE LL_RCC_EnableIT_PLL1RDY
6095 * @retval None
6096 */
6097 __STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void)
6098 {
6099 SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
6100 }
6101
6102 /**
6103 * @brief Enable PLL2 ready interrupt
6104 * @rmtoll CIER PLL2RDYIE LL_RCC_EnableIT_PLL2RDY
6105 * @retval None
6106 */
6107 __STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void)
6108 {
6109 SET_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
6110 }
6111
6112 /**
6113 * @brief Enable PLL3 ready interrupt
6114 * @rmtoll CIER PLL3RDYIE LL_RCC_EnableIT_PLL3RDY
6115 * @retval None
6116 */
6117 __STATIC_INLINE void LL_RCC_EnableIT_PLL3RDY(void)
6118 {
6119 SET_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
6120 }
6121
6122 /**
6123 * @brief Enable LSECSS interrupt
6124 * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS
6125 * @retval None
6126 */
6127 __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
6128 {
6129 SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
6130 }
6131
6132 /**
6133 * @brief Disable LSI ready interrupt
6134 * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
6135 * @retval None
6136 */
6137 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
6138 {
6139 CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
6140 }
6141
6142 /**
6143 * @brief Disable LSE ready interrupt
6144 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
6145 * @retval None
6146 */
6147 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
6148 {
6149 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
6150 }
6151
6152 /**
6153 * @brief Disable HSI ready interrupt
6154 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
6155 * @retval None
6156 */
6157 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
6158 {
6159 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
6160 }
6161
6162 /**
6163 * @brief Disable HSE ready interrupt
6164 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
6165 * @retval None
6166 */
6167 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
6168 {
6169 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
6170 }
6171
6172 /**
6173 * @brief Disable CSI ready interrupt
6174 * @rmtoll CIER CSIRDYIE LL_RCC_DisableIT_CSIRDY
6175 * @retval None
6176 */
6177 __STATIC_INLINE void LL_RCC_DisableIT_CSIRDY(void)
6178 {
6179 CLEAR_BIT(RCC->CIER, RCC_CIER_CSIRDYIE);
6180 }
6181
6182 /**
6183 * @brief Disable HSI48 ready interrupt
6184 * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
6185 * @retval None
6186 */
6187 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
6188 {
6189 CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
6190 }
6191
6192 /**
6193 * @brief Disable PLL1 ready interrupt
6194 * @rmtoll CIER PLL1RDYIE LL_RCC_DisableIT_PLL1RDY
6195 * @retval None
6196 */
6197 __STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void)
6198 {
6199 CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
6200 }
6201
6202 /**
6203 * @brief Disable PLL2 ready interrupt
6204 * @rmtoll CIER PLL2RDYIE LL_RCC_DisableIT_PLL2RDY
6205 * @retval None
6206 */
6207 __STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void)
6208 {
6209 CLEAR_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
6210 }
6211
6212 /**
6213 * @brief Disable PLL3 ready interrupt
6214 * @rmtoll CIER PLL3RDYIE LL_RCC_DisableIT_PLL3RDY
6215 * @retval None
6216 */
6217 __STATIC_INLINE void LL_RCC_DisableIT_PLL3RDY(void)
6218 {
6219 CLEAR_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
6220 }
6221
6222 /**
6223 * @brief Disable LSECSS interrupt
6224 * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS
6225 * @retval None
6226 */
6227 __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
6228 {
6229 CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
6230 }
6231
6232 /**
6233 * @brief Checks if LSI ready interrupt source is enabled or disabled.
6234 * @rmtoll CIER LSIRDYIE LL_RCC_IsEnableIT_LSIRDY
6235 * @retval State of bit (1 or 0).
6236 */
6237 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSIRDY(void)
6238 {
6239 return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE)?1UL:0UL);
6240 }
6241
6242 /**
6243 * @brief Checks if LSE ready interrupt source is enabled or disabled.
6244 * @rmtoll CIER LSERDYIE LL_RCC_IsEnableIT_LSERDY
6245 * @retval State of bit (1 or 0).
6246 */
6247 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSERDY(void)
6248 {
6249 return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE)?1UL:0UL);
6250 }
6251
6252 /**
6253 * @brief Checks if HSI ready interrupt source is enabled or disabled.
6254 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnableIT_HSIRDY
6255 * @retval State of bit (1 or 0).
6256 */
6257 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSIRDY(void)
6258 {
6259 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE)?1UL:0UL);
6260 }
6261
6262 /**
6263 * @brief Checks if HSE ready interrupt source is enabled or disabled.
6264 * @rmtoll CIER HSERDYIE LL_RCC_IsEnableIT_HSERDY
6265 * @retval State of bit (1 or 0).
6266 */
6267 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSERDY(void)
6268 {
6269 return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE)?1UL:0UL);
6270 }
6271
6272 /**
6273 * @brief Checks if CSI ready interrupt source is enabled or disabled.
6274 * @rmtoll CIER CSIRDYIE LL_RCC_IsEnableIT_CSIRDY
6275 * @retval State of bit (1 or 0).
6276 */
6277 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_CSIRDY(void)
6278 {
6279 return ((READ_BIT(RCC->CIER, RCC_CIER_CSIRDYIE) == RCC_CIER_CSIRDYIE)?1UL:0UL);
6280 }
6281
6282 /**
6283 * @brief Checks if HSI48 ready interrupt source is enabled or disabled.
6284 * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnableIT_HSI48RDY
6285 * @retval State of bit (1 or 0).
6286 */
6287 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSI48RDY(void)
6288 {
6289 return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE)?1UL:0UL);
6290 }
6291
6292 /**
6293 * @brief Checks if PLL1 ready interrupt source is enabled or disabled.
6294 * @rmtoll CIER PLL1RDYIE LL_RCC_IsEnableIT_PLL1RDY
6295 * @retval State of bit (1 or 0).
6296 */
6297 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL1RDY(void)
6298 {
6299 return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE)?1UL:0UL);
6300 }
6301
6302 /**
6303 * @brief Checks if PLL2 ready interrupt source is enabled or disabled.
6304 * @rmtoll CIER PLL2RDYIE LL_RCC_IsEnableIT_PLL2RDY
6305 * @retval State of bit (1 or 0).
6306 */
6307 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL2RDY(void)
6308 {
6309 return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE)?1UL:0UL);
6310 }
6311
6312 /**
6313 * @brief Checks if PLL3 ready interrupt source is enabled or disabled.
6314 * @rmtoll CIER PLL3RDYIE LL_RCC_IsEnableIT_PLL3RDY
6315 * @retval State of bit (1 or 0).
6316 */
6317 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL3RDY(void)
6318 {
6319 return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE)?1UL:0UL);
6320 }
6321
6322 /**
6323 * @brief Checks if LSECSS interrupt source is enabled or disabled.
6324 * @rmtoll CIER LSECSSIE LL_RCC_IsEnableIT_LSECSS
6325 * @retval State of bit (1 or 0).
6326 */
6327 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSECSS(void)
6328 {
6329 return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE)?1UL:0UL);
6330 }
6331 /**
6332 * @}
6333 */
6334
6335 #if defined(USE_FULL_LL_DRIVER)
6336 /** @defgroup RCC_LL_EF_Init De-initialization function
6337 * @{
6338 */
6339 void LL_RCC_DeInit(void);
6340 /**
6341 * @}
6342 */
6343
6344 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
6345 * @{
6346 */
6347 uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR);
6348
6349 void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
6350 void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
6351 void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
6352 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
6353
6354 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
6355 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
6356 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
6357 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
6358 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
6359 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
6360 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
6361 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
6362 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
6363 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
6364 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
6365 #if defined(DFSDM2_BASE)
6366 uint32_t LL_RCC_GetDFSDM2ClockFreq(uint32_t DFSDMxSource);
6367 #endif /* DFSDM2_BASE */
6368 #if defined(DSI)
6369 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
6370 #endif /* DSI */
6371 uint32_t LL_RCC_GetSPDIFClockFreq(uint32_t SPDIFxSource);
6372 uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource);
6373 uint32_t LL_RCC_GetSWPClockFreq(uint32_t SWPxSource);
6374 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);
6375 uint32_t LL_RCC_GetFMCClockFreq(uint32_t FMCxSource);
6376 #if defined(QUADSPI)
6377 uint32_t LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource);
6378 #endif /* QUADSPI */
6379 #if defined(OCTOSPI1) || defined(OCTOSPI2)
6380 uint32_t LL_RCC_GetOSPIClockFreq(uint32_t OSPIxSource);
6381 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
6382 uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource);
6383
6384
6385 /**
6386 * @}
6387 */
6388 #endif /* USE_FULL_LL_DRIVER */
6389
6390 /**
6391 * @}
6392 */
6393
6394
6395 /**
6396 * @}
6397 */
6398 #endif /* defined(RCC) */
6399
6400 /**
6401 * @}
6402 */
6403
6404 #ifdef __cplusplus
6405 }
6406 #endif
6407
6408 #endif /* STM32H7xx_LL_RCC_H */
6409
6410 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/