lib/main/STM32H7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rng.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32h7xx_ll_rng.h
   4   * @author  MCD Application Team
   5   * @brief   Header file of RNG LL module.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  10   * All rights reserved.</center></h2>
  11   *
  12   * This software component is licensed by ST under BSD 3-Clause license,
  13   * the "License"; You may not use this file except in compliance with the
  14   * License. You may obtain a copy of the License at:
  15   *                        opensource.org/licenses/BSD-3-Clause
  16   *
  17   ******************************************************************************
  18   */
  19
  20 /* Define to prevent recursive inclusion -------------------------------------*/
  21 #ifndef STM32H7xx_LL_RNG_H
  22 #define STM32H7xx_LL_RNG_H
  23
  24 #ifdef __cplusplus
  25 extern "C" {
  26 #endif
  27
  28 /* Includes ------------------------------------------------------------------*/
  29 #include "stm32h7xx.h"
  30
  31 /** @addtogroup STM32H7xx_LL_Driver
  32   * @{
  33   */
  34
  35 #if defined (RNG)
  36
  37 /** @defgroup RNG_LL RNG
  38   * @{
  39   */
  40
  41 /* Private types -------------------------------------------------------------*/
  42 /* Private variables ---------------------------------------------------------*/
  43 /* Private constants ---------------------------------------------------------*/
  44 /* Private macros ------------------------------------------------------------*/
  45
  46 /* Exported types ------------------------------------------------------------*/
  47 #if defined(USE_FULL_LL_DRIVER)
  48 /** @defgroup RNG_LL_ES_Init_Struct RNG Exported Init structures
  49   * @{
  50   */
  51
  52
  53 /**
  54   * @brief LL RNG Init Structure Definition
  55   */
  56 typedef struct
  57 {
  58   uint32_t         ClockErrorDetection; /*!< Clock error detection.
  59                                       This parameter can be one value of @ref RNG_LL_CED.
  60
  61                                       This parameter can be modified using unitary functions @ref LL_RNG_EnableClkErrorDetect(). */
  62 } LL_RNG_InitTypeDef;
  63
  64 /**
  65   * @}
  66   */
  67 #endif /* USE_FULL_LL_DRIVER */
  68 /* Exported constants --------------------------------------------------------*/
  69 /** @defgroup RNG_LL_Exported_Constants RNG Exported Constants
  70   * @{
  71   */
  72
  73 /** @defgroup RNG_LL_CED Clock Error Detection
  74   * @{
  75   */
  76 #define LL_RNG_CED_ENABLE         0x00000000U              /*!< Clock error detection enabled  */
  77 #define LL_RNG_CED_DISABLE        RNG_CR_CED               /*!< Clock error detection disabled */
  78 /**
  79   * @}
  80   */
  81
  82 #if defined(RNG_CR_CONDRST)
  83 /** @defgroup RNG_LL_Clock_Divider_Factor  Value used to configure an internal
  84  *            programmable divider acting on the incoming RNG clock
  85   * @{
  86   */
  87 #define LL_RNG_CLKDIV_BY_1       (0x00000000UL)                                                           /*!< No clock division                             */
  88 #define LL_RNG_CLKDIV_BY_2       (RNG_CR_CLKDIV_0)                                                        /*!< 2 RNG clock cycles per internal RNG clock     */
  89 #define LL_RNG_CLKDIV_BY_4       (RNG_CR_CLKDIV_1)                                                        /*!< 4 RNG clock cycles per internal RNG clock     */
  90 #define LL_RNG_CLKDIV_BY_8       (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)                                      /*!< 8 RNG clock cycles per internal RNG clock     */
  91 #define LL_RNG_CLKDIV_BY_16      (RNG_CR_CLKDIV_2)                                                        /*!< 16 RNG clock cycles per internal RNG clock    */
  92 #define LL_RNG_CLKDIV_BY_32      (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)                                      /*!< 32 RNG clock cycles per internal RNG clock    */
  93 #define LL_RNG_CLKDIV_BY_64      (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)                                      /*!< 64 RNG clock cycles per internal RNG clock    */
  94 #define LL_RNG_CLKDIV_BY_128     (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)                    /*!< 128 RNG clock cycles per internal RNG clock   */
  95 #define LL_RNG_CLKDIV_BY_256     (RNG_CR_CLKDIV_3)                                                        /*!< 256 RNG clock cycles per internal RNG clock   */
  96 #define LL_RNG_CLKDIV_BY_512     (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0)                                      /*!< 512 RNG clock cycles per internal RNG clock   */
  97 #define LL_RNG_CLKDIV_BY_1024    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1)                                      /*!< 1024 RNG clock cycles per internal RNG clock  */
  98 #define LL_RNG_CLKDIV_BY_2048    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)                    /*!< 2048 RNG clock cycles per internal RNG clock  */
  99 #define LL_RNG_CLKDIV_BY_4096    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2)                                      /*!< 4096 RNG clock cycles per internal RNG clock  */
 100 #define LL_RNG_CLKDIV_BY_8192    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)                    /*!< 8192 RNG clock cycles per internal RNG clock  */
 101 #define LL_RNG_CLKDIV_BY_16384   (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)                    /*!< 16384 RNG clock cycles per internal RNG clock */
 102 #define LL_RNG_CLKDIV_BY_32768   (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)  /*!< 32768 RNG clock cycles per internal RNG clock */
 103 /**
 104   * @}
 105   */
 106
 107 /** @defgroup RNG_LL_NIST_Compliance  NIST Compliance configuration
 108   * @{
 109   */
 110 #define LL_RNG_NIST_COMPLIANT     (0x00000000UL) /*!< Default NIST compliant configuration*/
 111 #define LL_RNG_CUSTOM_NIST        (RNG_CR_NISTC) /*!< Custom NIST configuration */
 112
 113 /**
 114   * @}
 115   */
 116
 117 #endif/*RNG_CR_CONDRST*/
 118 /** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
 119   * @brief    Flags defines which can be used with LL_RNG_ReadReg function
 120   * @{
 121   */
 122 #define LL_RNG_SR_DRDY RNG_SR_DRDY    /*!< Register contains valid random data */
 123 #define LL_RNG_SR_CECS RNG_SR_CECS    /*!< Clock error current status */
 124 #define LL_RNG_SR_SECS RNG_SR_SECS    /*!< Seed error current status */
 125 #define LL_RNG_SR_CEIS RNG_SR_CEIS    /*!< Clock error interrupt status */
 126 #define LL_RNG_SR_SEIS RNG_SR_SEIS    /*!< Seed error interrupt status */
 127 /**
 128   * @}
 129   */
 130
 131 /** @defgroup RNG_LL_EC_IT IT Defines
 132   * @brief    IT defines which can be used with LL_RNG_ReadReg and  LL_RNG_WriteReg macros
 133   * @{
 134   */
 135 #define LL_RNG_CR_IE   RNG_CR_IE      /*!< RNG Interrupt enable */
 136 /**
 137   * @}
 138   */
 139
 140 /**
 141   * @}
 142   */
 143
 144 /* Exported macro ------------------------------------------------------------*/
 145 /** @defgroup RNG_LL_Exported_Macros RNG Exported Macros
 146   * @{
 147   */
 148
 149 /** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros
 150   * @{
 151   */
 152
 153 /**
 154   * @brief  Write a value in RNG register
 155   * @param  __INSTANCE__ RNG Instance
 156   * @param  __REG__ Register to be written
 157   * @param  __VALUE__ Value to be written in the register
 158   * @retval None
 159   */
 160 #define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
 161
 162 /**
 163   * @brief  Read a value in RNG register
 164   * @param  __INSTANCE__ RNG Instance
 165   * @param  __REG__ Register to be read
 166   * @retval Register value
 167   */
 168 #define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
 169 /**
 170   * @}
 171   */
 172
 173 /**
 174   * @}
 175   */
 176
 177
 178 /* Exported functions --------------------------------------------------------*/
 179 /** @defgroup RNG_LL_Exported_Functions RNG Exported Functions
 180   * @{
 181   */
 182 /** @defgroup RNG_LL_EF_Configuration RNG Configuration functions
 183   * @{
 184   */
 185
 186 /**
 187   * @brief  Enable Random Number Generation
 188   * @rmtoll CR           RNGEN         LL_RNG_Enable
 189   * @param  RNGx RNG Instance
 190   * @retval None
 191   */
 192 __STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx)
 193 {
 194   SET_BIT(RNGx->CR, RNG_CR_RNGEN);
 195 }
 196
 197 /**
 198   * @brief  Disable Random Number Generation
 199   * @rmtoll CR           RNGEN         LL_RNG_Disable
 200   * @param  RNGx RNG Instance
 201   * @retval None
 202   */
 203 __STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
 204 {
 205   CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN);
 206 }
 207
 208 /**
 209   * @brief  Check if Random Number Generator is enabled
 210   * @rmtoll CR           RNGEN         LL_RNG_IsEnabled
 211   * @param  RNGx RNG Instance
 212   * @retval State of bit (1 or 0).
 213   */
 214 __STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
 215 {
 216   return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL);
 217 }
 218
 219 /**
 220   * @brief  Enable Clock Error Detection
 221   * @rmtoll CR           CED           LL_RNG_EnableClkErrorDetect
 222   * @param  RNGx RNG Instance
 223   * @retval None
 224   */
 225 __STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx)
 226 {
 227   CLEAR_BIT(RNGx->CR, RNG_CR_CED);
 228 }
 229
 230 /**
 231   * @brief  Disable RNG Clock Error Detection
 232   * @rmtoll CR           CED         LL_RNG_DisableClkErrorDetect
 233   * @param  RNGx RNG Instance
 234   * @retval None
 235   */
 236 __STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx)
 237 {
 238   SET_BIT(RNGx->CR, RNG_CR_CED);
 239 }
 240
 241 /**
 242   * @brief  Check if RNG Clock Error Detection is enabled
 243   * @rmtoll CR           CED         LL_RNG_IsEnabledClkErrorDetect
 244   * @param  RNGx RNG Instance
 245   * @retval State of bit (1 or 0).
 246   */
 247 __STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(RNG_TypeDef *RNGx)
 248 {
 249   return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL);
 250 }
 251
 252 #if defined(RNG_CR_CONDRST)
 253 /**
 254   * @brief  Set RNG Conditioning Soft Reset bit
 255   * @rmtoll CR           CONDRST          LL_RNG_EnableCondReset
 256   * @param  RNGx RNG Instance
 257   * @retval None
 258   */
 259 __STATIC_INLINE void LL_RNG_EnableCondReset(RNG_TypeDef *RNGx)
 260 {
 261   SET_BIT(RNGx->CR, RNG_CR_CONDRST);
 262 }
 263
 264 /**
 265   * @brief  Reset RNG  Conditioning Soft Reset bit
 266   * @rmtoll CR           CONDRST         LL_RNG_DisableCondReset
 267   * @param  RNGx RNG Instance
 268   * @retval None
 269   */
 270 __STATIC_INLINE void LL_RNG_DisableCondReset(RNG_TypeDef *RNGx)
 271 {
 272   CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
 273 }
 274
 275 /**
 276   * @brief  Check if RNG Conditioning Soft Reset bit is set
 277   * @rmtoll CR           CONDRST         LL_RNG_IsEnabledCondReset
 278   * @param  RNGx RNG Instance
 279   * @retval State of bit (1 or 0).
 280   */
 281 __STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset(RNG_TypeDef *RNGx)
 282 {
 283   return ((READ_BIT(RNGx->CR, RNG_CR_CONDRST) == (RNG_CR_CONDRST)) ? 1UL : 0UL);
 284 }
 285
 286 /**
 287   * @brief  Enable RNG Config Lock
 288   * @rmtoll CR           CONFIGLOCK          LL_RNG_ConfigLock
 289   * @param  RNGx RNG Instance
 290   * @retval None
 291   */
 292 __STATIC_INLINE void LL_RNG_ConfigLock(RNG_TypeDef *RNGx)
 293 {
 294   SET_BIT(RNGx->CR, RNG_CR_CONFIGLOCK);
 295 }
 296
 297 /**
 298   * @brief  Check if RNG Config Lock is enabled
 299   * @rmtoll CR           CONFIGLOCK         LL_RNG_IsConfigLocked
 300   * @param  RNGx RNG Instance
 301   * @retval State of bit (1 or 0).
 302   */
 303 __STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(RNG_TypeDef *RNGx)
 304 {
 305   return ((READ_BIT(RNGx->CR, RNG_CR_CONFIGLOCK) == (RNG_CR_CONFIGLOCK)) ? 1UL : 0UL);
 306 }
 307
 308 /**
 309   * @brief  Enable NIST Compliance
 310   * @rmtoll CR           NISTC         LL_RNG_EnableNistCompliance
 311   * @param  RNGx RNG Instance
 312   * @retval None
 313   */
 314 __STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx)
 315 {
 316   CLEAR_BIT(RNGx->CR, RNG_CR_NISTC);
 317 }
 318
 319 /**
 320   * @brief  Disable NIST Compliance
 321   * @rmtoll CR           NISTC         LL_RNG_DisableNistCompliance
 322   * @param  RNGx RNG Instance
 323   * @retval None
 324   */
 325 __STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx)
 326 {
 327   SET_BIT(RNGx->CR, RNG_CR_NISTC);
 328 }
 329
 330 /**
 331   * @brief  Check if NIST Compliance is enabled
 332   * @rmtoll CR           NISTC         LL_RNG_IsEnabledNistCompliance
 333   * @param  RNGx RNG Instance
 334   * @retval State of bit (1 or 0).
 335   */
 336 __STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(RNG_TypeDef *RNGx)
 337 {
 338   return ((READ_BIT(RNGx->CR, RNG_CR_NISTC) != (RNG_CR_NISTC)) ? 1UL : 0UL);
 339 }
 340
 341 /**
 342   * @brief  Set RNG  Config1 Configuration field value
 343   * @rmtoll CR           RNG_CONFIG1         LL_RNG_SetConfig1
 344   * @param  RNGx RNG Instance
 345   * @param  Config1 Value between 0 and 0x3F
 346   * @retval None
 347   */
 348 __STATIC_INLINE void LL_RNG_SetConfig1(RNG_TypeDef *RNGx, uint32_t Config1)
 349 {
 350   MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG1, Config1 << RNG_CR_RNG_CONFIG1_Pos);
 351 }
 352
 353 /**
 354   * @brief  Get RNG  Config1 Configuration field value
 355   * @rmtoll CR           RNG_CONFIG1         LL_RNG_GetConfig1
 356   * @param  RNGx RNG Instance
 357   * @retval Returned Value expressed on 6 bits : Value between 0 and 0x3F
 358   */
 359 __STATIC_INLINE uint32_t LL_RNG_GetConfig1(RNG_TypeDef *RNGx)
 360 {
 361   return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos);
 362 }
 363
 364 /**
 365   * @brief  Set RNG  Config2 Configuration field value
 366   * @rmtoll CR           RNG_CONFIG2         LL_RNG_SetConfig2
 367   * @param  RNGx RNG Instance
 368   * @param  Config2 Value between 0 and 0x7
 369   * @retval None
 370   */
 371 __STATIC_INLINE void LL_RNG_SetConfig2(RNG_TypeDef *RNGx, uint32_t Config2)
 372 {
 373   MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG2, Config2 << RNG_CR_RNG_CONFIG2_Pos);
 374 }
 375
 376 /**
 377   * @brief  Get RNG  Config2 Configuration field value
 378   * @rmtoll CR           RNG_CONFIG2         LL_RNG_GetConfig2
 379   * @param  RNGx RNG Instance
 380   * @retval Returned Value expressed on 3 bits : Value between 0 and 0x7
 381   */
 382 __STATIC_INLINE uint32_t LL_RNG_GetConfig2(RNG_TypeDef *RNGx)
 383 {
 384   return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos);
 385 }
 386
 387 /**
 388   * @brief  Set RNG  Config3 Configuration field value
 389   * @rmtoll CR           RNG_CONFIG3         LL_RNG_SetConfig3
 390   * @param  RNGx RNG Instance
 391   * @param  Config3 Value between 0 and 0xF
 392   * @retval None
 393   */
 394 __STATIC_INLINE void LL_RNG_SetConfig3(RNG_TypeDef *RNGx, uint32_t Config3)
 395 {
 396   MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG3, Config3 << RNG_CR_RNG_CONFIG3_Pos);
 397 }
 398
 399 /**
 400   * @brief  Get RNG  Config3 Configuration field value
 401   * @rmtoll CR           RNG_CONFIG3         LL_RNG_GetConfig3
 402   * @param  RNGx RNG Instance
 403   * @retval Returned Value expressed on 4 bits : Value between 0 and 0xF
 404   */
 405 __STATIC_INLINE uint32_t LL_RNG_GetConfig3(RNG_TypeDef *RNGx)
 406 {
 407   return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos);
 408 }
 409
 410 /**
 411   * @brief  Set RNG  Clock divider factor
 412   * @rmtoll CR           CLKDIV         LL_RNG_SetClockDivider
 413   * @param  RNGx RNG Instance
 414   * @param  Divider can be one of the following values:
 415   *         @arg @ref LL_RNG_CLKDIV_BY_1
 416   *         @arg @ref LL_RNG_CLKDIV_BY_2
 417   *         @arg @ref LL_RNG_CLKDIV_BY_4
 418   *         @arg @ref LL_RNG_CLKDIV_BY_8
 419   *         @arg @ref LL_RNG_CLKDIV_BY_16
 420   *         @arg @ref LL_RNG_CLKDIV_BY_32
 421   *         @arg @ref LL_RNG_CLKDIV_BY_64
 422   *         @arg @ref LL_RNG_CLKDIV_BY_128
 423   *         @arg @ref LL_RNG_CLKDIV_BY_256
 424   *         @arg @ref LL_RNG_CLKDIV_BY_512
 425   *         @arg @ref LL_RNG_CLKDIV_BY_1024
 426   *         @arg @ref LL_RNG_CLKDIV_BY_2048
 427   *         @arg @ref LL_RNG_CLKDIV_BY_4096
 428   *         @arg @ref LL_RNG_CLKDIV_BY_8192
 429   *         @arg @ref LL_RNG_CLKDIV_BY_16384
 430   *         @arg @ref LL_RNG_CLKDIV_BY_32768
 431   * @retval None
 432   */
 433 __STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider)
 434 {
 435   MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV, Divider << RNG_CR_CLKDIV_Pos);
 436 }
 437
 438 /**
 439   * @brief  Get RNG  Clock divider factor
 440   * @rmtoll CR           CLKDIV         LL_RNG_GetClockDivider
 441   * @param  RNGx RNG Instance
 442   * @retval Returned value can be one of the following values:
 443   *         @arg @ref LL_RNG_CLKDIV_BY_1
 444   *         @arg @ref LL_RNG_CLKDIV_BY_2
 445   *         @arg @ref LL_RNG_CLKDIV_BY_4
 446   *         @arg @ref LL_RNG_CLKDIV_BY_8
 447   *         @arg @ref LL_RNG_CLKDIV_BY_16
 448   *         @arg @ref LL_RNG_CLKDIV_BY_32
 449   *         @arg @ref LL_RNG_CLKDIV_BY_64
 450   *         @arg @ref LL_RNG_CLKDIV_BY_128
 451   *         @arg @ref LL_RNG_CLKDIV_BY_256
 452   *         @arg @ref LL_RNG_CLKDIV_BY_512
 453   *         @arg @ref LL_RNG_CLKDIV_BY_1024
 454   *         @arg @ref LL_RNG_CLKDIV_BY_2048
 455   *         @arg @ref LL_RNG_CLKDIV_BY_4096
 456   *         @arg @ref LL_RNG_CLKDIV_BY_8192
 457   *         @arg @ref LL_RNG_CLKDIV_BY_16384
 458   *         @arg @ref LL_RNG_CLKDIV_BY_32768
 459   */
 460 __STATIC_INLINE uint32_t LL_RNG_GetClockDivider(RNG_TypeDef *RNGx)
 461 {
 462   return (uint32_t)READ_BIT(RNGx->CR, RNG_CR_CLKDIV);
 463 }
 464 #endif /* RNG_CR_CONDRST */
 465 /**
 466   * @}
 467   */
 468
 469 /** @defgroup RNG_LL_EF_FLAG_Management FLAG Management
 470   * @{
 471   */
 472
 473 /**
 474   * @brief  Indicate if the RNG Data ready Flag is set or not
 475   * @rmtoll SR           DRDY          LL_RNG_IsActiveFlag_DRDY
 476   * @param  RNGx RNG Instance
 477   * @retval State of bit (1 or 0).
 478   */
 479 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
 480 {
 481   return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL);
 482 }
 483
 484 /**
 485   * @brief  Indicate if the Clock Error Current Status Flag is set or not
 486   * @rmtoll SR           CECS          LL_RNG_IsActiveFlag_CECS
 487   * @param  RNGx RNG Instance
 488   * @retval State of bit (1 or 0).
 489   */
 490 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
 491 {
 492   return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL);
 493 }
 494
 495 /**
 496   * @brief  Indicate if the Seed Error Current Status Flag is set or not
 497   * @rmtoll SR           SECS          LL_RNG_IsActiveFlag_SECS
 498   * @param  RNGx RNG Instance
 499   * @retval State of bit (1 or 0).
 500   */
 501 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
 502 {
 503   return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL);
 504 }
 505
 506 /**
 507   * @brief  Indicate if the Clock Error Interrupt Status Flag is set or not
 508   * @rmtoll SR           CEIS          LL_RNG_IsActiveFlag_CEIS
 509   * @param  RNGx RNG Instance
 510   * @retval State of bit (1 or 0).
 511   */
 512 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
 513 {
 514   return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL);
 515 }
 516
 517 /**
 518   * @brief  Indicate if the Seed Error Interrupt Status Flag is set or not
 519   * @rmtoll SR           SEIS          LL_RNG_IsActiveFlag_SEIS
 520   * @param  RNGx RNG Instance
 521   * @retval State of bit (1 or 0).
 522   */
 523 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx)
 524 {
 525   return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL);
 526 }
 527
 528 /**
 529   * @brief  Clear Clock Error interrupt Status (CEIS) Flag
 530   * @rmtoll SR           CEIS          LL_RNG_ClearFlag_CEIS
 531   * @param  RNGx RNG Instance
 532   * @retval None
 533   */
 534 __STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx)
 535 {
 536   WRITE_REG(RNGx->SR, ~RNG_SR_CEIS);
 537 }
 538
 539 /**
 540   * @brief  Clear Seed Error interrupt Status (SEIS) Flag
 541   * @rmtoll SR           SEIS          LL_RNG_ClearFlag_SEIS
 542   * @param  RNGx RNG Instance
 543   * @retval None
 544   */
 545 __STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx)
 546 {
 547   WRITE_REG(RNGx->SR, ~RNG_SR_SEIS);
 548 }
 549
 550 /**
 551   * @}
 552   */
 553
 554 /** @defgroup RNG_LL_EF_IT_Management IT Management
 555   * @{
 556   */
 557
 558 /**
 559   * @brief  Enable Random Number Generator Interrupt
 560   *         (applies for either Seed error, Clock Error or Data ready interrupts)
 561   * @rmtoll CR           IE            LL_RNG_EnableIT
 562   * @param  RNGx RNG Instance
 563   * @retval None
 564   */
 565 __STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx)
 566 {
 567   SET_BIT(RNGx->CR, RNG_CR_IE);
 568 }
 569
 570 /**
 571   * @brief  Disable Random Number Generator Interrupt
 572   *         (applies for either Seed error, Clock Error or Data ready interrupts)
 573   * @rmtoll CR           IE            LL_RNG_DisableIT
 574   * @param  RNGx RNG Instance
 575   * @retval None
 576   */
 577 __STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
 578 {
 579   CLEAR_BIT(RNGx->CR, RNG_CR_IE);
 580 }
 581
 582 /**
 583   * @brief  Check if Random Number Generator Interrupt is enabled
 584   *         (applies for either Seed error, Clock Error or Data ready interrupts)
 585   * @rmtoll CR           IE            LL_RNG_IsEnabledIT
 586   * @param  RNGx RNG Instance
 587   * @retval State of bit (1 or 0).
 588   */
 589 __STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
 590 {
 591   return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL);
 592 }
 593
 594 /**
 595   * @}
 596   */
 597
 598 /** @defgroup RNG_LL_EF_Data_Management Data Management
 599   * @{
 600   */
 601
 602 /**
 603   * @brief  Return32-bit Random Number value
 604   * @rmtoll DR           RNDATA        LL_RNG_ReadRandData32
 605   * @param  RNGx RNG Instance
 606   * @retval Generated 32-bit random value
 607   */
 608 __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
 609 {
 610   return (uint32_t)(READ_REG(RNGx->DR));
 611 }
 612
 613 /**
 614   * @}
 615   */
 616
 617 #if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
 618 /** @defgroup RNG_LL_EF_Health_Test_Control Health Test Control
 619   * @{
 620   */
 621
 622 /**
 623   * @brief  Set RNG Health Test Control
 624   * @rmtoll HTCR       HTCFG       LL_RNG_SetHealthConfig
 625   * @param  RNGx RNG Instance
 626   * @param  HTCFG can be values of 32 bits
 627   * @retval None
 628   */
 629 __STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG)
 630 {
 631   WRITE_REG(RNGx->HTCR, HTCFG);
 632 }
 633
 634 /**
 635   * @brief  Get RNG Health Test Control
 636   * @rmtoll HTCR         HTCFG        LL_RNG_GetHealthConfig
 637   * @param  RNGx RNG Instance
 638   * @retval Return 32-bit RNG Health Test configuration
 639   */
 640 __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(RNG_TypeDef *RNGx)
 641 {
 642   return (uint32_t)READ_REG(RNGx->HTCR);
 643 }
 644
 645 /**
 646   * @}
 647   */
 648 #endif  /*End of RNG_VER_3_2, RNG_VER_3_1 or RNG_VER_3_0*/
 649 #if defined(USE_FULL_LL_DRIVER)
 650 /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
 651   * @{
 652   */
 653 ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct);
 654 void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct);
 655 ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
 656
 657 /**
 658   * @}
 659   */
 660 #endif /* USE_FULL_LL_DRIVER */
 661
 662 /**
 663   * @}
 664   */
 665
 666 /**
 667   * @}
 668   */
 669
 670 #endif /* RNG */
 671
 672 /**
 673   * @}
 674   */
 675
 676 #ifdef __cplusplus
 677 }
 678 #endif
 679
 680 #endif /* __STM32H7xx_LL_RNG_H */
 681
 682 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/