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Merge pull request #11270 from haslinghuis/rename_attr
[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_ll_sdmmc.h
blob8b91c6cbc3deb608ae3e849d079865a06c49cf1e
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_sdmmc.h
4 * @author MCD Application Team
5 * @brief Header file of SDMMC HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_LL_SDMMC_H
22 #define STM32H7xx_LL_SDMMC_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx_hal_def.h"
30
31 /** @addtogroup STM32H7xx_Driver
32 * @{
33 */
34
35 /** @addtogroup SDMMC_LL
36 * @{
37 */
38
39 /* Exported types ------------------------------------------------------------*/
40 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
41 * @{
42 */
43
44 /**
45 * @brief SDMMC Configuration Structure definition
46 */
47 typedef struct
48 {
49 uint32_t ClockEdge; /*!< Specifies the SDMMC_CCK clock transition on which Data and Command change.
50 This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
51
52 uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or
53 disabled when the bus is idle.
54 This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
55
56 uint32_t BusWide; /*!< Specifies the SDMMC bus width.
57 This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
58
59 uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
60 This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
61
62 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
63 This parameter can be a value between Min_Data = 0 and Max_Data = 1023 */
64
65 #if (USE_SD_TRANSCEIVER != 0U)
66 uint32_t TranceiverPresent; /*!< Specifies if there is a 1V8 Tranceiver/Switcher.
67 This parameter can be a value of @ref SDMMC_LL_TRANCEIVER_PRESENT */
68 #endif /* USE_SD_TRANSCEIVER */
69 }SDMMC_InitTypeDef;
70
71
72 /**
73 * @brief SDMMC Command Control structure
74 */
75 typedef struct
76 {
77 uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent
78 to a card as part of a command message. If a command
79 contains an argument, it must be loaded into this register
80 before writing the command to the command register. */
81
82 uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
83 Max_Data = 64 */
84
85 uint32_t Response; /*!< Specifies the SDMMC response type.
86 This parameter can be a value of @ref SDMMC_LL_Response_Type */
87
88 uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is
89 enabled or disabled.
90 This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
91
92 uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)
93 is enabled or disabled.
94 This parameter can be a value of @ref SDMMC_LL_CPSM_State */
95 }SDMMC_CmdInitTypeDef;
96
97
98 /**
99 * @brief SDMMC Data Control structure
100 */
101 typedef struct
102 {
103 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
104
105 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
106
107 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
108 This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
109
110 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
111 is a read or write.
112 This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
113
114 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
115 This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
116
117 uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
118 is enabled or disabled.
119 This parameter can be a value of @ref SDMMC_LL_DPSM_State */
120 }SDMMC_DataInitTypeDef;
121
122 /**
123 * @}
124 */
125
126 /* Exported constants --------------------------------------------------------*/
127 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
128 * @{
129 */
130 #define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
131 #define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /*!< Command response received (but CRC check failed) */
132 #define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /*!< Data block sent/received (CRC check failed) */
133 #define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /*!< Command response timeout */
134 #define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /*!< Data timeout */
135 #define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */
136 #define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */
137 #define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */
138 #define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the
139 number of transferred bytes does not match the block length */
140 #define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */
141 #define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */
142 #define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */
143 #define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock
144 command or if there was an attempt to access a locked card */
145 #define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */
146 #define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */
147 #define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */
148 #define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /*!< Internal card controller error */
149 #define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /*!< General or unknown error */
150 #define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /*!< The card could not sustain data reading in stream rmode */
151 #define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /*!< The card could not sustain data programming in stream mode */
152 #define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */
153 #define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */
154 #define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */
155 #define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out
156 of erase sequence command was received */
157 #define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */
158 #define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */
159 #define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */
160 #define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /*!< Error when command request is not applicable */
161 #define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /*!< the used parameter is not valid */
162 #define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /*!< Error when feature is not insupported */
163 #define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /*!< Error when transfer process is busy */
164 #define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */
165 #define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */
166
167 /**
168 * @brief SDMMC Commands Index
169 */
170 #define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */
171 #define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */
172 #define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
173 #define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */
174 #define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */
175 #define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
176 operating condition register (OCR) content in the response on the CMD line. */
177 #define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
178 #define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */
179 #define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
180 and asks the card whether card supports voltage. */
181 #define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
182 #define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */
183 #define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /*!< SD card Voltage switch to 1.8V mode. */
184 #define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */
185 #define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */
186 #define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */
187 #define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */
188 #define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands
189 (read, write, lock). Default block length is fixed to 512 Bytes. Not effective
190 for SDHS and SDXC. */
191 #define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
192 fixed 512 bytes in case of SDHC and SDXC. */
193 #define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by
194 STOP_TRANSMISSION command. */
195 #define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
196 #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */
197 #define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */
198 #define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
199 fixed 512 bytes in case of SDHC and SDXC. */
200 #define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
201 #define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */
202 #define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */
203 #define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */
204 #define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */
205 #define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */
206 #define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */
207 #define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */
208 #define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command
209 system set by switch function command (CMD6). */
210 #define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased.
211 Reserved for each command system set by switch function command (CMD6). */
212 #define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */
213 #define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */
214 #define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */
215 #define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
216 the SET_BLOCK_LEN command. */
217 #define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather
218 than a standard command. */
219 #define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card
220 for general purpose/application specific commands. */
221 #define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */
222
223 /**
224 * @brief Following commands are SD Card Specific commands.
225 * SDMMC_APP_CMD should be sent before sending these commands.
226 */
227 #define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
228 widths are given in SCR register. */
229 #define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */
230 #define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
231 32bit+CRC data block. */
232 #define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
233 send its operating condition register (OCR) content in the response on the CMD line. */
234 #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
235 #define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */
236 #define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */
237 #define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */
238
239 /**
240 * @brief Following commands are SD Card Specific security commands.
241 * SDMMC_CMD_APP_CMD should be sent before sending these commands.
242 */
243 #define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U)
244 #define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U)
245 #define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U)
246 #define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U)
247 #define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U)
248 #define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U)
249 #define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U)
250 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U)
251 #define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U)
252 #define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U)
253 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U)
254
255 /**
256 * @brief Masks for errors Card Status R1 (OCR Register)
257 */
258 #define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U)
259 #define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U)
260 #define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U)
261 #define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U)
262 #define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U)
263 #define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U)
264 #define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U)
265 #define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U)
266 #define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U)
267 #define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U)
268 #define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U)
269 #define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U)
270 #define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U)
271 #define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U)
272 #define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U)
273 #define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U)
274 #define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U)
275 #define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U)
276 #define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U)
277 #define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U)
278
279 /**
280 * @brief Masks for R6 Response
281 */
282 #define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U)
283 #define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U)
284 #define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U)
285
286 #define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U)
287 #define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U)
288 #define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U)
289 #define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU)
290 #define SD_SWITCH_1_8V_CAPACITY ((uint32_t)0x01000000U)
291 #define SDMMC_DDR50_SWITCH_PATTERN ((uint32_t)0x80FFFF04U)
292 #define SDMMC_SDR104_SWITCH_PATTERN ((uint32_t)0x80FF1F03U)
293 #define SDMMC_SDR50_SWITCH_PATTERN ((uint32_t)0x80FF1F02U)
294 #define SDMMC_SDR25_SWITCH_PATTERN ((uint32_t)0x80FFFF01U)
295
296 #define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU)
297
298 #define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU)
299
300 #define SDMMC_ALLZERO ((uint32_t)0x00000000U)
301
302 #define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U)
303 #define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U)
304 #define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U)
305
306 #define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU)
307
308 #define SDMMC_0TO7BITS ((uint32_t)0x000000FFU)
309 #define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U)
310 #define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U)
311 #define SDMMC_24TO31BITS ((uint32_t)0xFF000000U)
312 #define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU)
313
314 #define SDMMC_HALFFIFO ((uint32_t)0x00000008U)
315 #define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U)
316
317 /**
318 * @brief Command Class supported
319 */
320 #define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U)
321
322 #define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */
323 #define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */
324 #define SDMMC_STOPTRANSFERTIMEOUT ((uint32_t)100000000U) /* Timeout for STOP TRANSMISSION command */
325
326 /** @defgroup SDMMC_LL_Clock_Edge Clock Edge
327 * @{
328 */
329 #define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U)
330 #define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE
331
332 #define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \
333 ((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
334 /**
335 * @}
336 */
337
338 /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
339 * @{
340 */
341 #define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U)
342 #define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV
343
344 #define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \
345 ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
346 /**
347 * @}
348 */
349
350 /** @defgroup SDMMC_LL_Bus_Wide Bus Width
351 * @{
352 */
353 #define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U)
354 #define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0
355 #define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1
356
357 #define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \
358 ((WIDE) == SDMMC_BUS_WIDE_4B) || \
359 ((WIDE) == SDMMC_BUS_WIDE_8B))
360 /**
361 * @}
362 */
363
364 /** @defgroup SDMMC_LL_Speed_Mode
365 * @{
366 */
367 #define SDMMC_SPEED_MODE_AUTO ((uint32_t)0x00000000U)
368 #define SDMMC_SPEED_MODE_DEFAULT ((uint32_t)0x00000001U)
369 #define SDMMC_SPEED_MODE_HIGH ((uint32_t)0x00000002U)
370 #define SDMMC_SPEED_MODE_ULTRA ((uint32_t)0x00000003U)
371 #define SDMMC_SPEED_MODE_DDR ((uint32_t)0x00000004U)
372
373 #define IS_SDMMC_SPEED_MODE(MODE) (((MODE) == SDMMC_SPEED_MODE_AUTO) || \
374 ((MODE) == SDMMC_SPEED_MODE_DEFAULT) || \
375 ((MODE) == SDMMC_SPEED_MODE_HIGH) || \
376 ((MODE) == SDMMC_SPEED_MODE_ULTRA) || \
377 ((MODE) == SDMMC_SPEED_MODE_DDR))
378
379 /**
380 * @}
381 */
382
383 /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
384 * @{
385 */
386 #define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U)
387 #define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN
388
389 #define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \
390 ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
391 /**
392 * @}
393 */
394
395 /** @defgroup SDMMC_LL_Clock_Division Clock Division
396 * @{
397 */
398 /* SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV] */
399 #define IS_SDMMC_CLKDIV(DIV) ((DIV) < 0x400U)
400 /**
401 * @}
402 */
403
404 /** @defgroup SDMMC_LL_TRANSCEIVER_PRESENT Tranceiver Present
405 * @{
406 */
407 #define SDMMC_TRANSCEIVER_UNKNOWN ((uint32_t)0x00000000U)
408 #define SDMMC_TRANSCEIVER_NOT_PRESENT ((uint32_t)0x00000001U)
409 #define SDMMC_TRANSCEIVER_PRESENT ((uint32_t)0x00000002U)
410
411 /**
412 * @}
413 */
414
415 /** @defgroup SDMMC_LL_Command_Index Command Index
416 * @{
417 */
418 #define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40U)
419 /**
420 * @}
421 */
422
423 /** @defgroup SDMMC_LL_Response_Type Response Type
424 * @{
425 */
426 #define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U)
427 #define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0
428 #define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP
429
430 #define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \
431 ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \
432 ((RESPONSE) == SDMMC_RESPONSE_LONG))
433 /**
434 * @}
435 */
436
437 /** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
438 * @{
439 */
440 #define SDMMC_WAIT_NO ((uint32_t)0x00000000U)
441 #define SDMMC_WAIT_IT SDMMC_CMD_WAITINT
442 #define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND
443
444 #define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \
445 ((WAIT) == SDMMC_WAIT_IT) || \
446 ((WAIT) == SDMMC_WAIT_PEND))
447 /**
448 * @}
449 */
450
451 /** @defgroup SDMMC_LL_CPSM_State CPSM State
452 * @{
453 */
454 #define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U)
455 #define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN
456
457 #define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \
458 ((CPSM) == SDMMC_CPSM_ENABLE))
459 /**
460 * @}
461 */
462
463 /** @defgroup SDMMC_LL_Response_Registers Response Register
464 * @{
465 */
466 #define SDMMC_RESP1 ((uint32_t)0x00000000U)
467 #define SDMMC_RESP2 ((uint32_t)0x00000004U)
468 #define SDMMC_RESP3 ((uint32_t)0x00000008U)
469 #define SDMMC_RESP4 ((uint32_t)0x0000000CU)
470
471 #define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \
472 ((RESP) == SDMMC_RESP2) || \
473 ((RESP) == SDMMC_RESP3) || \
474 ((RESP) == SDMMC_RESP4))
475
476 /** @defgroup SDMMC_Internal_DMA_Mode SDMMC Internal DMA Mode
477 * @{
478 */
479 #define SDMMC_DISABLE_IDMA ((uint32_t)0x00000000)
480 #define SDMMC_ENABLE_IDMA_SINGLE_BUFF (SDMMC_IDMA_IDMAEN)
481 #define SDMMC_ENABLE_IDMA_DOUBLE_BUFF0 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE)
482 #define SDMMC_ENABLE_IDMA_DOUBLE_BUFF1 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE | SDMMC_IDMA_IDMABACT)
483
484 /**
485 * @}
486 */
487
488 /** @defgroup SDMMC_LL_Data_Length Data Lenght
489 * @{
490 */
491 #define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
492 /**
493 * @}
494 */
495
496 /** @defgroup SDMMC_LL_Data_Block_Size Data Block Size
497 * @{
498 */
499 #define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U)
500 #define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0
501 #define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1
502 #define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1)
503 #define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2
504 #define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2)
505 #define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
506 #define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
507 #define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3
508 #define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3)
509 #define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
510 #define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
511 #define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
512 #define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
513 #define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
514
515 #define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \
516 ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \
517 ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \
518 ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \
519 ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \
520 ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \
521 ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \
522 ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \
523 ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \
524 ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \
525 ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \
526 ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \
527 ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \
528 ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \
529 ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))
530 /**
531 * @}
532 */
533
534 /** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
535 * @{
536 */
537 #define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U)
538 #define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR
539
540 #define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \
541 ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
542 /**
543 * @}
544 */
545
546 /** @defgroup SDMMC_LL_Transfer_Type Transfer Type
547 * @{
548 */
549 #define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U)
550 #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE_1
551
552 #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \
553 ((MODE) == SDMMC_TRANSFER_MODE_STREAM))
554 /**
555 * @}
556 */
557
558 /** @defgroup SDMMC_LL_DPSM_State DPSM State
559 * @{
560 */
561 #define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U)
562 #define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN
563
564 #define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\
565 ((DPSM) == SDMMC_DPSM_ENABLE))
566 /**
567 * @}
568 */
569
570 /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
571 * @{
572 */
573 #define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U)
574 #define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD)
575
576 #define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \
577 ((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
578 /**
579 * @}
580 */
581
582 /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
583 * @{
584 */
585 #define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE
586 #define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE
587 #define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE
588 #define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE
589 #define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE
590 #define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE
591 #define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE
592 #define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE
593 #define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE
594 #define SDMMC_IT_DHOLD SDMMC_MASK_DHOLDIE
595 #define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE
596 #define SDMMC_IT_DABORT SDMMC_MASK_DABORTIE
597 #define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE
598 #define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE
599 #define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE
600 #define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE
601 #define SDMMC_IT_BUSYD0END SDMMC_MASK_BUSYD0ENDIE
602 #define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE
603 #define SDMMC_IT_ACKFAIL SDMMC_MASK_ACKFAILIE
604 #define SDMMC_IT_ACKTIMEOUT SDMMC_MASK_ACKTIMEOUTIE
605 #define SDMMC_IT_VSWEND SDMMC_MASK_VSWENDIE
606 #define SDMMC_IT_CKSTOP SDMMC_MASK_CKSTOPIE
607 #define SDMMC_IT_IDMABTC SDMMC_MASK_IDMABTCIE
608 /**
609 * @}
610 */
611
612 /** @defgroup SDMMC_LL_Flags Flags
613 * @{
614 */
615 #define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL
616 #define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL
617 #define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT
618 #define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT
619 #define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR
620 #define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR
621 #define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND
622 #define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT
623 #define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND
624 #define SDMMC_FLAG_DHOLD SDMMC_STA_DHOLD
625 #define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND
626 #define SDMMC_FLAG_DABORT SDMMC_STA_DABORT
627 #define SDMMC_FLAG_DPSMACT SDMMC_STA_DPSMACT
628 #define SDMMC_FLAG_CMDACT SDMMC_STA_CPSMACT
629 #define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE
630 #define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF
631 #define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF
632 #define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF
633 #define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE
634 #define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE
635 #define SDMMC_FLAG_BUSYD0 SDMMC_STA_BUSYD0
636 #define SDMMC_FLAG_BUSYD0END SDMMC_STA_BUSYD0END
637 #define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT
638 #define SDMMC_FLAG_ACKFAIL SDMMC_STA_ACKFAIL
639 #define SDMMC_FLAG_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT
640 #define SDMMC_FLAG_VSWEND SDMMC_STA_VSWEND
641 #define SDMMC_FLAG_CKSTOP SDMMC_STA_CKSTOP
642 #define SDMMC_FLAG_IDMATE SDMMC_STA_IDMATE
643 #define SDMMC_FLAG_IDMABTC SDMMC_STA_IDMABTC
644
645 #define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\
646 SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\
647 SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\
648 SDMMC_FLAG_DHOLD | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT |\
649 SDMMC_FLAG_BUSYD0END | SDMMC_FLAG_SDIOIT | SDMMC_FLAG_ACKFAIL |\
650 SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND | SDMMC_FLAG_CKSTOP |\
651 SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC))
652
653 #define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\
654 SDMMC_FLAG_CMDSENT | SDMMC_FLAG_BUSYD0END))
655
656 #define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\
657 SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DHOLD |\
658 SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT | SDMMC_FLAG_IDMATE |\
659 SDMMC_FLAG_IDMABTC))
660 /**
661 * @}
662 */
663
664 /**
665 * @}
666 */
667
668 /* Exported macro ------------------------------------------------------------*/
669 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
670 * @{
671 */
672
673 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
674 * @brief SDMMC_LL registers bit address in the alias region
675 * @{
676 */
677 /* ---------------------- SDMMC registers bit mask --------------------------- */
678 /* --- CLKCR Register ---*/
679 /* CLKCR register clear mask */
680 #define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\
681 SDMMC_CLKCR_WIDBUS |\
682 SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN |\
683 SDMMC_CLKCR_DDR | SDMMC_CLKCR_BUSSPEED |\
684 SDMMC_CLKCR_SELCLKRX))
685
686 /* --- DCTRL Register ---*/
687 /* SDMMC DCTRL Clear Mask */
688 #define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN | SDMMC_DCTRL_DTDIR |\
689 SDMMC_DCTRL_DTMODE | SDMMC_DCTRL_DBLOCKSIZE))
690
691 /* --- CMD Register ---*/
692 /* CMD Register clear mask */
693 #define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\
694 SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\
695 SDMMC_CMD_CPSMEN | SDMMC_CMD_CMDSUSPEND))
696
697 /* SDMMC Initialization Frequency (400KHz max) for Peripheral CLK 200MHz*/
698 #define SDMMC_INIT_CLK_DIV ((uint8_t)0xFA)
699
700 /* SDMMC Default Speed Frequency (25Mhz max) for Peripheral CLK 200MHz*/
701 #define SDMMC_NSpeed_CLK_DIV ((uint8_t)0x4)
702
703 /* SDMMC High Speed Frequency (50Mhz max) for Peripheral CLK 200MHz*/
704 #define SDMMC_HSpeed_CLK_DIV ((uint8_t)0x2)
705 /**
706 * @}
707 */
708
709 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
710 * @brief macros to handle interrupts and specific clock configurations
711 * @{
712 */
713
714 /**
715 * @brief Enable the SDMMC device interrupt.
716 * @param __INSTANCE__ Pointer to SDMMC register base
717 * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.
718 * This parameter can be one or a combination of the following values:
719 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
720 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
721 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
722 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
723 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
724 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
725 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
726 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
727 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
728 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
729 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
730 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
731 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
732 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
733 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
734 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
735 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
736 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
737 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
738 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
739 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
740 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
741 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
742 * @retval None
743 */
744 #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
745
746 /**
747 * @brief Disable the SDMMC device interrupt.
748 * @param __INSTANCE__ Pointer to SDMMC register base
749 * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.
750 * This parameter can be one or a combination of the following values:
751 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
752 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
753 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
754 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
755 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
756 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
757 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
758 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
759 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
760 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
761 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
762 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
763 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
764 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
765 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
766 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
767 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
768 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
769 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
770 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
771 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
772 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
773 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
774 * @retval None
775 */
776 #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
777
778 /**
779 * @brief Checks whether the specified SDMMC flag is set or not.
780 * @param __INSTANCE__ Pointer to SDMMC register base
781 * @param __FLAG__ specifies the flag to check.
782 * This parameter can be one of the following values:
783 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
784 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
785 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
786 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout
787 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
788 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
789 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
790 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
791 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
792 * @arg SDMMC_FLAG_DHOLD: Data transfer Hold
793 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
794 * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
795 * @arg SDMMC_FLAG_DPSMACT: Data path state machine active
796 * @arg SDMMC_FLAG_CPSMACT: Command path state machine active
797 * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
798 * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
799 * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
800 * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full
801 * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
802 * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
803 * @arg SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy)
804 * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
805 * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received
806 * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
807 * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
808 * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
809 * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
810 * @arg SDMMC_FLAG_IDMATE: IDMA transfer error
811 * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
812 * @retval The new state of SDMMC_FLAG (SET or RESET).
813 */
814 #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U)
815
816
817 /**
818 * @brief Clears the SDMMC pending flags.
819 * @param __INSTANCE__ Pointer to SDMMC register base
820 * @param __FLAG__ specifies the flag to clear.
821 * This parameter can be one or a combination of the following values:
822 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
823 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
824 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
825 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout
826 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
827 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
828 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
829 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
830 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
831 * @arg SDMMC_FLAG_DHOLD: Data transfer Hold
832 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
833 * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
834 * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
835 * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received
836 * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
837 * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
838 * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
839 * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
840 * @arg SDMMC_FLAG_IDMATE: IDMA transfer error
841 * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
842 * @retval None
843 */
844 #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
845
846 /**
847 * @brief Checks whether the specified SDMMC interrupt has occurred or not.
848 * @param __INSTANCE__ Pointer to SDMMC register base
849 * @param __INTERRUPT__ specifies the SDMMC interrupt source to check.
850 * This parameter can be one of the following values:
851 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
852 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
853 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
854 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
855 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
856 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
857 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
858 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
859 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
860 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
861 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
862 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
863 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
864 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
865 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
866 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
867 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
868 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
869 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
870 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
871 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
872 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
873 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
874 * @retval The new state of SDMMC_IT (SET or RESET).
875 */
876 #define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
877
878 /**
879 * @brief Clears the SDMMC's interrupt pending bits.
880 * @param __INSTANCE__ Pointer to SDMMC register base
881 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
882 * This parameter can be one or a combination of the following values:
883 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
884 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
885 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
886 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
887 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
888 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
889 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
890 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
891 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
892 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
893 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
894 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
895 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
896 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
897 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
898 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
899 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
900 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
901 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
902 * @retval None
903 */
904 #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
905
906 /**
907 * @brief Enable Start the SD I/O Read Wait operation.
908 * @param __INSTANCE__ Pointer to SDMMC register base
909 * @retval None
910 */
911 #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART)
912
913 /**
914 * @brief Disable Start the SD I/O Read Wait operations.
915 * @param __INSTANCE__ Pointer to SDMMC register base
916 * @retval None
917 */
918 #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)
919
920 /**
921 * @brief Enable Start the SD I/O Read Wait operation.
922 * @param __INSTANCE__ Pointer to SDMMC register base
923 * @retval None
924 */
925 #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP)
926
927 /**
928 * @brief Disable Stop the SD I/O Read Wait operations.
929 * @param __INSTANCE__ Pointer to SDMMC register base
930 * @retval None
931 */
932 #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)
933
934 /**
935 * @brief Enable the SD I/O Mode Operation.
936 * @param __INSTANCE__ Pointer to SDMMC register base
937 * @retval None
938 */
939 #define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN)
940
941 /**
942 * @brief Disable the SD I/O Mode Operation.
943 * @param __INSTANCE__ Pointer to SDMMC register base
944 * @retval None
945 */
946 #define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN)
947
948 /**
949 * @brief Enable the SD I/O Suspend command sending.
950 * @param __INSTANCE__ Pointer to SDMMC register base
951 * @retval None
952 */
953 #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSUSPEND)
954
955 /**
956 * @brief Disable the SD I/O Suspend command sending.
957 * @param __INSTANCE__ Pointer to SDMMC register base
958 * @retval None
959 */
960 #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSUSPEND)
961
962 /**
963 * @brief Enable the CMDTRANS mode.
964 * @param __INSTANCE__ Pointer to SDMMC register base
965 * @retval None
966 */
967 #define __SDMMC_CMDTRANS_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDTRANS)
968
969 /**
970 * @brief Disable the CMDTRANS mode.
971 * @param __INSTANCE__ Pointer to SDMMC register base
972 * @retval None
973 */
974 #define __SDMMC_CMDTRANS_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDTRANS)
975
976 /**
977 * @brief Enable the CMDSTOP mode.
978 * @param __INSTANCE__ Pointer to SDMMC register base
979 * @retval None
980 */
981 #define __SDMMC_CMDSTOP_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSTOP)
982
983 /**
984 * @brief Disable the CMDSTOP mode.
985 * @param __INSTANCE__ Pointer to SDMMC register base
986 * @retval None
987 */
988 #define __SDMMC_CMDSTOP_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSTOP)
989
990 /**
991 * @}
992 */
993
994 /**
995 * @}
996 */
997
998 /* Exported functions --------------------------------------------------------*/
999 /** @addtogroup SDMMC_LL_Exported_Functions
1000 * @{
1001 */
1002
1003 /* Initialization/de-initialization functions **********************************/
1004 /** @addtogroup HAL_SDMMC_LL_Group1
1005 * @{
1006 */
1007 HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);
1008 /**
1009 * @}
1010 */
1011
1012 /* I/O operation functions *****************************************************/
1013 /** @addtogroup HAL_SDMMC_LL_Group2
1014 * @{
1015 */
1016 uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);
1017 HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData);
1018 /**
1019 * @}
1020 */
1021
1022 /* Peripheral Control functions ************************************************/
1023 /** @addtogroup HAL_SDMMC_LL_Group3
1024 * @{
1025 */
1026 HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);
1027 HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx);
1028 HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);
1029 uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);
1030
1031 /* Command path state machine (CPSM) management functions */
1032 HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command);
1033 uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);
1034 uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
1035
1036 /* Data path state machine (DPSM) management functions */
1037 HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data);
1038 uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
1039 uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
1040
1041 /* SDMMC Cards mode management functions */
1042 HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
1043
1044 /* SDMMC Commands management functions */
1045 uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize);
1046 uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
1047 uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
1048 uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
1049 uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
1050 uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
1051 uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
1052 uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
1053 uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
1054 uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx, uint32_t EraseType);
1055 uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx);
1056 uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr);
1057 uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx);
1058 uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx);
1059 uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
1060 uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
1061 uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth);
1062 uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx);
1063 uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx);
1064 uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
1065 uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA);
1066 uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
1067 uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx);
1068 uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx);
1069 uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
1070 uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
1071 uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
1072
1073 /**
1074 * @}
1075 */
1076
1077
1078 /**
1079 * @}
1080 */
1081
1082 /**
1083 * @}
1084 */
1085
1086 /**
1087 * @}
1088 */
1089
1090 /**
1091 * @}
1092 */
1093
1094 /**
1095 * @}
1096 */
1097 #ifdef __cplusplus
1098 }
1099 #endif
1100
1101 #endif /* STM32H7xx_LL_SDMMC_H */
1102
1103 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/