lib/main/STM32H7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_swpmi.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32h7xx_ll_swpmi.h
   4   * @author  MCD Application Team
   5   * @brief   Header file of SWPMI LL module.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  10   * All rights reserved.</center></h2>
  11   *
  12   * This software component is licensed by ST under BSD 3-Clause license,
  13   * the "License"; You may not use this file except in compliance with the
  14   * License. You may obtain a copy of the License at:
  15   *                        opensource.org/licenses/BSD-3-Clause
  16   *
  17   ******************************************************************************
  18   */
  19
  20 /* Define to prevent recursive inclusion -------------------------------------*/
  21 #ifndef STM32H7xx_LL_SWPMI_H
  22 #define STM32H7xx_LL_SWPMI_H
  23
  24 #ifdef __cplusplus
  25 extern "C" {
  26 #endif
  27
  28 /* Includes ------------------------------------------------------------------*/
  29 #include "stm32h7xx.h"
  30
  31 /** @addtogroup STM32H7xx_LL_Driver
  32   * @{
  33   */
  34
  35
  36 /** @defgroup SWPMI_LL SWPMI
  37   * @{
  38   */
  39
  40 /* Private types -------------------------------------------------------------*/
  41 /* Private variables ---------------------------------------------------------*/
  42 /* Private constants ---------------------------------------------------------*/
  43 /* Private macros ------------------------------------------------------------*/
  44 #if defined(USE_FULL_LL_DRIVER)
  45 /** @defgroup SWPMI_LL_Private_Macros SWPMI Private Macros
  46   * @{
  47   */
  48 /**
  49   * @}
  50   */
  51 #endif /*USE_FULL_LL_DRIVER*/
  52
  53 /* Exported types ------------------------------------------------------------*/
  54 #if defined(USE_FULL_LL_DRIVER)
  55 /** @defgroup SWPMI_LL_ES_INIT SWPMI Exported Init structure
  56   * @{
  57   */
  58
  59 /**
  60   * @brief  SWPMI Init structures definition
  61   */
  62 typedef struct
  63 {
  64   uint32_t VoltageClass;           /*!< Specifies the SWP Voltage Class.
  65                                         This parameter can be a value of @ref SWPMI_LL_EC_VOLTAGE_CLASS
  66
  67                                         This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetVoltageClass. */
  68
  69   uint32_t BitRatePrescaler;       /*!< Specifies the SWPMI bitrate prescaler.
  70                                         This parameter must be a number between Min_Data=0 and Max_Data=255U.
  71
  72                                         The value can be calculated thanks to helper macro @ref __LL_SWPMI_CALC_BITRATE_PRESCALER
  73
  74                                         This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetBitRatePrescaler. */
  75
  76   uint32_t TxBufferingMode;        /*!< Specifies the transmission buffering mode.
  77                                         This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_TX
  78
  79                                         This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetTransmissionMode. */
  80
  81   uint32_t RxBufferingMode;        /*!< Specifies the reception buffering mode.
  82                                         This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_RX
  83
  84                                         This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetReceptionMode. */
  85 } LL_SWPMI_InitTypeDef;
  86
  87 /**
  88   * @}
  89   */
  90 #endif /* USE_FULL_LL_DRIVER */
  91
  92 /* Exported constants --------------------------------------------------------*/
  93 /** @defgroup SWPMI_LL_Exported_Constants SWPMI Exported Constants
  94   * @{
  95   */
  96
  97 /** @defgroup SWPMI_LL_EC_CLEAR_FLAG Clear Flags Defines
  98   * @brief    Flags defines which can be used with LL_SWPMI_WriteReg function
  99   * @{
 100   */
 101 #define LL_SWPMI_ICR_CRXBFF                SWPMI_ICR_CRXBFF  /*!< Clear receive buffer full flag     */
 102 #define LL_SWPMI_ICR_CTXBEF                SWPMI_ICR_CTXBEF  /*!< Clear transmit buffer empty flag   */
 103 #define LL_SWPMI_ICR_CRXBERF               SWPMI_ICR_CRXBERF /*!< Clear receive CRC error flag       */
 104 #define LL_SWPMI_ICR_CRXOVRF               SWPMI_ICR_CRXOVRF /*!< Clear receive overrun error flag   */
 105 #define LL_SWPMI_ICR_CTXUNRF               SWPMI_ICR_CTXUNRF /*!< Clear transmit underrun error flag */
 106 #define LL_SWPMI_ICR_CTCF                  SWPMI_ICR_CTCF    /*!< Clear transfer complete flag       */
 107 #define LL_SWPMI_ICR_CSRF                  SWPMI_ICR_CSRF    /*!< Clear slave resume flag            */
 108 /**
 109   * @}
 110   */
 111
 112 /** @defgroup SWPMI_LL_EC_GET_FLAG Get Flags Defines
 113   * @brief    Flags defines which can be used with LL_SWPMI_ReadReg function
 114   * @{
 115   */
 116 #define LL_SWPMI_ISR_RXBFF                 SWPMI_ISR_RXBFF   /*!< Receive buffer full flag           */
 117 #define LL_SWPMI_ISR_TXBEF                 SWPMI_ISR_TXBEF   /*!< Transmit buffer empty flag         */
 118 #define LL_SWPMI_ISR_RXBERF                SWPMI_ISR_RXBERF  /*!< Receive CRC error flag             */
 119 #define LL_SWPMI_ISR_RXOVRF                SWPMI_ISR_RXOVRF  /*!< Receive overrun error flag         */
 120 #define LL_SWPMI_ISR_TXUNRF                SWPMI_ISR_TXUNRF  /*!< Transmit underrun error flag       */
 121 #define LL_SWPMI_ISR_RXNE                  SWPMI_ISR_RXNE    /*!< Receive data register not empty    */
 122 #define LL_SWPMI_ISR_TXE                   SWPMI_ISR_TXE     /*!< Transmit data register empty       */
 123 #define LL_SWPMI_ISR_TCF                   SWPMI_ISR_TCF     /*!< Transfer complete flag             */
 124 #define LL_SWPMI_ISR_SRF                   SWPMI_ISR_SRF     /*!< Slave resume flag                  */
 125 #define LL_SWPMI_ISR_SUSP                  SWPMI_ISR_SUSP    /*!< SUSPEND flag                       */
 126 #define LL_SWPMI_ISR_DEACTF                SWPMI_ISR_DEACTF  /*!< DEACTIVATED flag                   */
 127 /**
 128   * @}
 129   */
 130
 131 /** @defgroup SWPMI_LL_EC_IT IT Defines
 132   * @brief    IT defines which can be used with LL_SWPMI_ReadReg and  LL_SWPMI_WriteReg functions
 133   * @{
 134   */
 135 #define LL_SWPMI_IER_SRIE                  SWPMI_IER_SRIE    /*!< Slave resume interrupt enable            */
 136 #define LL_SWPMI_IER_TCIE                  SWPMI_IER_TCIE    /*!< Transmit complete interrupt enable       */
 137 #define LL_SWPMI_IER_TIE                   SWPMI_IER_TIE     /*!< Transmit interrupt enable                */
 138 #define LL_SWPMI_IER_RIE                   SWPMI_IER_RIE     /*!< Receive interrupt enable                 */
 139 #define LL_SWPMI_IER_TXUNRIE               SWPMI_IER_TXUNRIE /*!< Transmit underrun error interrupt enable */
 140 #define LL_SWPMI_IER_RXOVRIE               SWPMI_IER_RXOVRIE /*!< Receive overrun error interrupt enable   */
 141 #define LL_SWPMI_IER_RXBERIE               SWPMI_IER_RXBERIE /*!< Receive CRC error interrupt enable       */
 142 #define LL_SWPMI_IER_TXBEIE                SWPMI_IER_TXBEIE  /*!< Transmit buffer empty interrupt enable   */
 143 #define LL_SWPMI_IER_RXBFIE                SWPMI_IER_RXBFIE  /*!< Receive buffer full interrupt enable     */
 144 /**
 145   * @}
 146   */
 147
 148 /** @defgroup SWPMI_LL_EC_SW_BUFFER_RX SW BUFFER RX
 149   * @{
 150   */
 151 #define LL_SWPMI_SW_BUFFER_RX_SINGLE ((uint32_t)0x00000000)  /*!< Single software buffer mode for reception */
 152 #define LL_SWPMI_SW_BUFFER_RX_MULTI  SWPMI_CR_RXMODE         /*!< Multi software buffermode for reception   */
 153 /**
 154   * @}
 155   */
 156
 157 /** @defgroup SWPMI_LL_EC_SW_BUFFER_TX SW BUFFER TX
 158   * @{
 159   */
 160 #define LL_SWPMI_SW_BUFFER_TX_SINGLE ((uint32_t)0x00000000)  /*!< Single software buffer mode for transmission */
 161 #define LL_SWPMI_SW_BUFFER_TX_MULTI  SWPMI_CR_TXMODE         /*!< Multi software buffermode for transmission   */
 162 /**
 163   * @}
 164   */
 165
 166 /** @defgroup SWPMI_LL_EC_VOLTAGE_CLASS VOLTAGE CLASS
 167   * @{
 168   */
 169 #define LL_SWPMI_VOLTAGE_CLASS_C     ((uint32_t)0x00000000)  /*!< SWPMI_IO uses directly VDD voltage to operate in class C          */
 170 #define LL_SWPMI_VOLTAGE_CLASS_B     SWPMI_OR_CLASS          /*!< SWPMI_IO uses an internal voltage regulator to operate in class B */
 171 /**
 172   * @}
 173   */
 174
 175 /** @defgroup SWPMI_LL_EC_DMA_REG_DATA DMA register data
 176   * @{
 177   */
 178 #define LL_SWPMI_DMA_REG_DATA_TRANSMIT     (uint32_t)0       /*!< Get address of data register used for transmission */
 179 #define LL_SWPMI_DMA_REG_DATA_RECEIVE      (uint32_t)1       /*!< Get address of data register used for reception    */
 180 /**
 181   * @}
 182   */
 183
 184 /**
 185   * @}
 186   */
 187
 188 /* Exported macro ------------------------------------------------------------*/
 189 /** @defgroup SWPMI_LL_Exported_Macros SWPMI Exported Macros
 190   * @{
 191   */
 192
 193 /** @defgroup SWPMI_LL_EM_WRITE_READ Common Write and read registers Macros
 194   * @{
 195   */
 196
 197 /**
 198   * @brief  Write a value in SWPMI register
 199   * @param  __INSTANCE__ SWPMI Instance
 200   * @param  __REG__ Register to be written
 201   * @param  __VALUE__ Value to be written in the register
 202   * @retval None
 203   */
 204 #define LL_SWPMI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
 205
 206 /**
 207   * @brief  Read a value in SWPMI register
 208   * @param  __INSTANCE__ SWPMI Instance
 209   * @param  __REG__ Register to be read
 210   * @retval Register value
 211   */
 212 #define LL_SWPMI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
 213 /**
 214   * @}
 215   */
 216
 217 /** @defgroup SWPMI_LL_EM_BitRate Bit rate calculation helper Macros
 218   * @{
 219   */
 220
 221 /**
 222   * @brief  Helper macro to calculate bit rate value to set in BRR register (@ref LL_SWPMI_SetBitRatePrescaler function)
 223   * @note ex: @ref __LL_SWPMI_CALC_BITRATE_PRESCALER(2000000, 80000000);
 224   * @param  __FSWP__ Within the following range: from 100 Kbit/s up to 2Mbit/s (in bit/s)
 225   * @param  __FSWPCLK__ PCLK or HSI frequency (in Hz)
 226   * @retval Bitrate prescaler (BRR register)
 227   */
 228 #define __LL_SWPMI_CALC_BITRATE_PRESCALER(__FSWP__, __FSWPCLK__)   ((uint32_t)(((__FSWPCLK__) / ((__FSWP__) * 4)) - 1))
 229
 230 /**
 231   * @}
 232   */
 233
 234 /**
 235   * @}
 236   */
 237
 238 /* Exported functions --------------------------------------------------------*/
 239 /** @defgroup SWPMI_LL_Exported_Functions SWPMI Exported Functions
 240   * @{
 241   */
 242
 243 /** @defgroup SWPMI_LL_EF_Configuration Configuration
 244   * @{
 245   */
 246
 247 /**
 248   * @brief  Set Reception buffering mode
 249   * @note   If Multi software buffer mode is chosen, RXDMA bits must also be set.
 250   * @rmtoll CR           RXMODE        LL_SWPMI_SetReceptionMode
 251   * @param  SWPMIx SWPMI Instance
 252   * @param  RxBufferingMode This parameter can be one of the following values:
 253   *         @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE
 254   *         @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI
 255   * @retval None
 256   */
 257 __STATIC_INLINE void LL_SWPMI_SetReceptionMode(SWPMI_TypeDef *SWPMIx, uint32_t RxBufferingMode)
 258 {
 259   MODIFY_REG(SWPMIx->CR, SWPMI_CR_RXMODE, RxBufferingMode);
 260 }
 261
 262 /**
 263   * @brief  Get Reception buffering mode
 264   * @rmtoll CR           RXMODE        LL_SWPMI_GetReceptionMode
 265   * @param  SWPMIx SWPMI Instance
 266   * @retval Returned value can be one of the following values:
 267   *         @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE
 268   *         @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI
 269   */
 270 __STATIC_INLINE uint32_t LL_SWPMI_GetReceptionMode(SWPMI_TypeDef *SWPMIx)
 271 {
 272   return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_RXMODE));
 273 }
 274
 275 /**
 276   * @brief  Set Transmission buffering mode
 277   * @note   If Multi software buffer mode is chosen, TXDMA bits must also be set.
 278   * @rmtoll CR           TXMODE        LL_SWPMI_SetTransmissionMode
 279   * @param  SWPMIx SWPMI Instance
 280   * @param  TxBufferingMode This parameter can be one of the following values:
 281   *         @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE
 282   *         @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI
 283   * @retval None
 284   */
 285 __STATIC_INLINE void LL_SWPMI_SetTransmissionMode(SWPMI_TypeDef *SWPMIx, uint32_t TxBufferingMode)
 286 {
 287   MODIFY_REG(SWPMIx->CR, SWPMI_CR_TXMODE, TxBufferingMode);
 288 }
 289
 290 /**
 291   * @brief  Get Transmission buffering mode
 292   * @rmtoll CR           TXMODE        LL_SWPMI_GetTransmissionMode
 293   * @param  SWPMIx SWPMI Instance
 294   * @retval Returned value can be one of the following values:
 295   *         @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE
 296   *         @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI
 297   */
 298 __STATIC_INLINE uint32_t LL_SWPMI_GetTransmissionMode(SWPMI_TypeDef *SWPMIx)
 299 {
 300   return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_TXMODE));
 301 }
 302
 303 /**
 304   * @brief  Enable loopback mode
 305   * @rmtoll CR           LPBK          LL_SWPMI_EnableLoopback
 306   * @param  SWPMIx SWPMI Instance
 307   * @retval None
 308   */
 309 __STATIC_INLINE void LL_SWPMI_EnableLoopback(SWPMI_TypeDef *SWPMIx)
 310 {
 311   SET_BIT(SWPMIx->CR, SWPMI_CR_LPBK);
 312 }
 313
 314 /**
 315   * @brief  Disable loopback mode
 316   * @rmtoll CR           LPBK          LL_SWPMI_DisableLoopback
 317   * @param  SWPMIx SWPMI Instance
 318   * @retval None
 319   */
 320 __STATIC_INLINE void LL_SWPMI_DisableLoopback(SWPMI_TypeDef *SWPMIx)
 321 {
 322   CLEAR_BIT(SWPMIx->CR, SWPMI_CR_LPBK);
 323 }
 324
 325 /**
 326   * @brief  Enable SWPMI transceiver
 327   * @note   SWPMI_IO pin is controlled by SWPMI
 328   * @rmtoll CR           SWPEN          LL_SWPMI_EnableTransceiver
 329   * @param  SWPMIx SWPMI Instance
 330   * @retval None
 331   */
 332 __STATIC_INLINE void LL_SWPMI_EnableTransceiver(SWPMI_TypeDef *SWPMIx)
 333 {
 334   SET_BIT(SWPMIx->CR, SWPMI_CR_SWPEN);
 335 }
 336
 337 /**
 338   * @brief  Disable SWPMI transceiver
 339   * @note   SWPMI_IO pin is controlled by GPIO controller
 340   * @rmtoll CR           SWPEN          LL_SWPMI_DisableTransceiver
 341   * @param  SWPMIx SWPMI Instance
 342   * @retval None
 343   */
 344 __STATIC_INLINE void LL_SWPMI_DisableTransceiver(SWPMI_TypeDef *SWPMIx)
 345 {
 346   CLEAR_BIT(SWPMIx->CR, SWPMI_CR_SWPEN);
 347 }
 348
 349 /**
 350   * @brief  Check if SWPMI transceiver is enabled
 351   * @rmtoll CR           SWPEN         LL_SWPMI_IsEnabledTransceiver
 352   * @param  SWPMIx SWPMI Instance
 353   * @retval State of bit (1 or 0).
 354   */
 355 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledTransceiver(SWPMI_TypeDef *SWPMIx)
 356 {
 357   return ((READ_BIT(SWPMIx->CR, SWPMI_CR_SWPEN) == (SWPMI_CR_SWPEN)) ? 1UL : 0UL);
 358 }
 359
 360 /**
 361   * @brief  Activate Single wire protocol bus (SUSPENDED or ACTIVATED state)
 362   * @note   SWP bus stays in the ACTIVATED state as long as there is a communication
 363   *         with the slave, either in transmission or in reception. The SWP bus switches back
 364   *         to the SUSPENDED state as soon as there is no more transmission or reception
 365   *         activity, after 7 idle bits.
 366   * @rmtoll CR           SWPACT        LL_SWPMI_Activate
 367   * @param  SWPMIx SWPMI Instance
 368   * @retval None
 369   */
 370 __STATIC_INLINE void LL_SWPMI_Activate(SWPMI_TypeDef *SWPMIx)
 371 {
 372   /* In order to activate SWP again, the software must clear DEACT bit*/
 373   CLEAR_BIT(SWPMIx->CR, SWPMI_CR_DEACT);
 374
 375   /* Set SWACT bit */
 376   SET_BIT(SWPMIx->CR, SWPMI_CR_SWPACT);
 377 }
 378
 379 /**
 380   * @brief  Check if Single wire protocol bus is in ACTIVATED state.
 381   * @rmtoll CR           SWPACT        LL_SWPMI_Activate
 382   * @param  SWPMIx SWPMI Instance
 383   * @retval State of bit (1 or 0).
 384   */
 385 __STATIC_INLINE uint32_t LL_SWPMI_IsActivated(SWPMI_TypeDef *SWPMIx)
 386 {
 387   return ((READ_BIT(SWPMIx->CR, SWPMI_CR_SWPACT) == (SWPMI_CR_SWPACT)) ? 1UL : 0UL);
 388 }
 389
 390 /**
 391   * @brief  Deactivate immediately Single wire protocol bus (immediate transition to
 392   *         DEACTIVATED state)
 393   * @rmtoll CR           SWPACT        LL_SWPMI_Deactivate
 394   * @param  SWPMIx SWPMI Instance
 395   * @retval None
 396   */
 397 __STATIC_INLINE void LL_SWPMI_Deactivate(SWPMI_TypeDef *SWPMIx)
 398 {
 399   CLEAR_BIT(SWPMIx->CR, SWPMI_CR_SWPACT);
 400 }
 401
 402 /**
 403   * @brief  Request a deactivation of Single wire protocol bus (request to go in DEACTIVATED
 404   *         state if no resume from slave)
 405   * @rmtoll CR           DEACT         LL_SWPMI_RequestDeactivation
 406   * @param  SWPMIx SWPMI Instance
 407   * @retval None
 408   */
 409 __STATIC_INLINE void LL_SWPMI_RequestDeactivation(SWPMI_TypeDef *SWPMIx)
 410 {
 411   SET_BIT(SWPMIx->CR, SWPMI_CR_DEACT);
 412 }
 413
 414 /**
 415   * @brief  Set Bitrate prescaler SWPMI_freq = SWPMI_clk / (((BitRate) + 1)  * 4)
 416   * @rmtoll BRR          BR            LL_SWPMI_SetBitRatePrescaler
 417   * @param  SWPMIx SWPMI Instance
 418   * @param  BitRatePrescaler A number between Min_Data=0 and Max_Data=255U
 419   * @retval None
 420   */
 421 __STATIC_INLINE void LL_SWPMI_SetBitRatePrescaler(SWPMI_TypeDef *SWPMIx, uint32_t BitRatePrescaler)
 422 {
 423   WRITE_REG(SWPMIx->BRR, BitRatePrescaler);
 424 }
 425
 426 /**
 427   * @brief  Get Bitrate prescaler
 428   * @rmtoll BRR          BR            LL_SWPMI_GetBitRatePrescaler
 429   * @param  SWPMIx SWPMI Instance
 430   * @retval A number between Min_Data=0 and Max_Data=255U
 431   */
 432 __STATIC_INLINE uint32_t LL_SWPMI_GetBitRatePrescaler(SWPMI_TypeDef *SWPMIx)
 433 {
 434   return (uint32_t)(READ_BIT(SWPMIx->BRR, SWPMI_BRR_BR));
 435 }
 436
 437 /**
 438   * @brief  Set SWP Voltage Class
 439   * @rmtoll OR           CLASS         LL_SWPMI_SetVoltageClass
 440   * @param  SWPMIx SWPMI Instance
 441   * @param  VoltageClass This parameter can be one of the following values:
 442   *         @arg @ref LL_SWPMI_VOLTAGE_CLASS_C
 443   *         @arg @ref LL_SWPMI_VOLTAGE_CLASS_B
 444   * @retval None
 445   */
 446 __STATIC_INLINE void LL_SWPMI_SetVoltageClass(SWPMI_TypeDef *SWPMIx, uint32_t VoltageClass)
 447 {
 448   MODIFY_REG(SWPMIx->OR, SWPMI_OR_CLASS, VoltageClass);
 449 }
 450
 451 /**
 452   * @brief  Get SWP Voltage Class
 453   * @rmtoll OR           CLASS         LL_SWPMI_GetVoltageClass
 454   * @param  SWPMIx SWPMI Instance
 455   * @retval Returned value can be one of the following values:
 456   *         @arg @ref LL_SWPMI_VOLTAGE_CLASS_C
 457   *         @arg @ref LL_SWPMI_VOLTAGE_CLASS_B
 458   */
 459 __STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass(SWPMI_TypeDef *SWPMIx)
 460 {
 461   return (uint32_t)(READ_BIT(SWPMIx->OR, SWPMI_OR_CLASS));
 462 }
 463
 464 /**
 465   * @}
 466   */
 467
 468 /** @defgroup SWPMI_LL_EF_FLAG_Management FLAG_Management
 469   * @{
 470   */
 471
 472 /**
 473   * @brief  Check if the last word of the frame under reception has arrived in SWPMI_RDR.
 474   * @rmtoll ISR          RXBFF         LL_SWPMI_IsActiveFlag_RXBF
 475   * @param  SWPMIx SWPMI Instance
 476   * @retval State of bit (1 or 0).
 477   */
 478 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(SWPMI_TypeDef *SWPMIx)
 479 {
 480   return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBFF) == (SWPMI_ISR_RXBFF)) ? 1UL : 0UL);
 481 }
 482
 483 /**
 484   * @brief  Check if Frame transmission buffer has been emptied
 485   * @rmtoll ISR          TXBEF         LL_SWPMI_IsActiveFlag_TXBE
 486   * @param  SWPMIx SWPMI Instance
 487   * @retval State of bit (1 or 0).
 488   */
 489 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(SWPMI_TypeDef *SWPMIx)
 490 {
 491   return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXBEF) == (SWPMI_ISR_TXBEF)) ? 1UL : 0UL);
 492 }
 493
 494 /**
 495   * @brief  Check if CRC error in reception has been detected
 496   * @rmtoll ISR          RXBERF        LL_SWPMI_IsActiveFlag_RXBER
 497   * @param  SWPMIx SWPMI Instance
 498   * @retval State of bit (1 or 0).
 499   */
 500 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(SWPMI_TypeDef *SWPMIx)
 501 {
 502   return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBERF) == (SWPMI_ISR_RXBERF)) ? 1UL : 0UL);
 503 }
 504
 505 /**
 506   * @brief  Check if Overrun in reception has been detected
 507   * @rmtoll ISR          RXOVRF        LL_SWPMI_IsActiveFlag_RXOVR
 508   * @param  SWPMIx SWPMI Instance
 509   * @retval State of bit (1 or 0).
 510   */
 511 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(SWPMI_TypeDef *SWPMIx)
 512 {
 513   return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXOVRF) == (SWPMI_ISR_RXOVRF)) ? 1UL : 0UL);
 514 }
 515
 516 /**
 517   * @brief  Check if underrun error in transmission has been detected
 518   * @rmtoll ISR          TXUNRF        LL_SWPMI_IsActiveFlag_TXUNR
 519   * @param  SWPMIx SWPMI Instance
 520   * @retval State of bit (1 or 0).
 521   */
 522 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(SWPMI_TypeDef *SWPMIx)
 523 {
 524   return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXUNRF) == (SWPMI_ISR_TXUNRF)) ? 1UL : 0UL);
 525 }
 526
 527 /**
 528   * @brief  Check if Receive data register not empty (it means that Received data is ready
 529   *         to be read in the SWPMI_RDR register)
 530   * @rmtoll ISR          RXNE          LL_SWPMI_IsActiveFlag_RXNE
 531   * @param  SWPMIx SWPMI Instance
 532   * @retval State of bit (1 or 0).
 533   */
 534 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(SWPMI_TypeDef *SWPMIx)
 535 {
 536   return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXNE) == (SWPMI_ISR_RXNE)) ? 1UL : 0UL);
 537 }
 538
 539 /**
 540   * @brief  Check if Transmit data register is empty (it means that Data written in transmit
 541   *         data register SWPMI_TDR has been transmitted and SWPMI_TDR can be written to again)
 542   * @rmtoll ISR          TXE           LL_SWPMI_IsActiveFlag_TXE
 543   * @param  SWPMIx SWPMI Instance
 544   * @retval State of bit (1 or 0).
 545   */
 546 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(SWPMI_TypeDef *SWPMIx)
 547 {
 548   return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXE) == (SWPMI_ISR_TXE)) ? 1UL : 0UL);
 549 }
 550
 551 /**
 552   * @brief  Check if Both transmission and reception are completed and SWP is switched to
 553   *         the SUSPENDED state
 554   * @rmtoll ISR          TCF           LL_SWPMI_IsActiveFlag_TC
 555   * @param  SWPMIx SWPMI Instance
 556   * @retval State of bit (1 or 0).
 557   */
 558 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(SWPMI_TypeDef *SWPMIx)
 559 {
 560   return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TCF) == (SWPMI_ISR_TCF)) ? 1UL : 0UL);
 561 }
 562
 563 /**
 564   * @brief  Check if a Resume by slave state has been detected during the SWP bus SUSPENDED
 565   *         state
 566   * @rmtoll ISR          SRF           LL_SWPMI_IsActiveFlag_SR
 567   * @param  SWPMIx SWPMI Instance
 568   * @retval State of bit (1 or 0).
 569   */
 570 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(SWPMI_TypeDef *SWPMIx)
 571 {
 572   return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_SRF) == (SWPMI_ISR_SRF)) ? 1UL : 0UL);
 573 }
 574
 575 /**
 576   * @brief  Check if SWP bus is in SUSPENDED or DEACTIVATED state
 577   * @rmtoll ISR          SUSP          LL_SWPMI_IsActiveFlag_SUSP
 578   * @param  SWPMIx SWPMI Instance
 579   * @retval State of bit (1 or 0).
 580   */
 581 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(SWPMI_TypeDef *SWPMIx)
 582 {
 583   return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_SUSP) == (SWPMI_ISR_SUSP)) ? 1UL : 0UL);
 584 }
 585
 586 /**
 587   * @brief  Check if SWP bus is in DEACTIVATED state
 588   * @rmtoll ISR          DEACTF        LL_SWPMI_IsActiveFlag_DEACT
 589   * @param  SWPMIx SWPMI Instance
 590   * @retval State of bit (1 or 0).
 591   */
 592 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT(SWPMI_TypeDef *SWPMIx)
 593 {
 594   return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_DEACTF) == (SWPMI_ISR_DEACTF)) ? 1UL : 0UL);
 595 }
 596
 597 /**
 598   * @brief  Check if SWPMI transceiver is ready
 599   * @rmtoll ISR          RDYF        LL_SWPMI_IsActiveFlag_RDYF
 600   * @param  SWPMIx SWPMI Instance
 601   * @retval State of bit (1 or 0).
 602   */
 603 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RDYF(SWPMI_TypeDef *SWPMIx)
 604 {
 605   return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RDYF) == (SWPMI_ISR_RDYF)) ? 1UL : 0UL);
 606 }
 607
 608 /**
 609   * @brief  Clear receive buffer full flag
 610   * @rmtoll ICR          CRXBFF        LL_SWPMI_ClearFlag_RXBF
 611   * @param  SWPMIx SWPMI Instance
 612   * @retval None
 613   */
 614 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXBF(SWPMI_TypeDef *SWPMIx)
 615 {
 616   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBFF);
 617 }
 618
 619 /**
 620   * @brief  Clear transmit buffer empty flag
 621   * @rmtoll ICR          CTXBEF        LL_SWPMI_ClearFlag_TXBE
 622   * @param  SWPMIx SWPMI Instance
 623   * @retval None
 624   */
 625 __STATIC_INLINE void LL_SWPMI_ClearFlag_TXBE(SWPMI_TypeDef *SWPMIx)
 626 {
 627   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXBEF);
 628 }
 629
 630 /**
 631   * @brief  Clear receive CRC error flag
 632   * @rmtoll ICR          CRXBERF       LL_SWPMI_ClearFlag_RXBER
 633   * @param  SWPMIx SWPMI Instance
 634   * @retval None
 635   */
 636 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXBER(SWPMI_TypeDef *SWPMIx)
 637 {
 638   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBERF);
 639 }
 640
 641 /**
 642   * @brief  Clear receive overrun error flag
 643   * @rmtoll ICR          CRXOVRF       LL_SWPMI_ClearFlag_RXOVR
 644   * @param  SWPMIx SWPMI Instance
 645   * @retval None
 646   */
 647 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXOVR(SWPMI_TypeDef *SWPMIx)
 648 {
 649   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXOVRF);
 650 }
 651
 652 /**
 653   * @brief  Clear transmit underrun error flag
 654   * @rmtoll ICR          CTXUNRF       LL_SWPMI_ClearFlag_TXUNR
 655   * @param  SWPMIx SWPMI Instance
 656   * @retval None
 657   */
 658 __STATIC_INLINE void LL_SWPMI_ClearFlag_TXUNR(SWPMI_TypeDef *SWPMIx)
 659 {
 660   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXUNRF);
 661 }
 662
 663 /**
 664   * @brief  Clear transfer complete flag
 665   * @rmtoll ICR          CTCF          LL_SWPMI_ClearFlag_TC
 666   * @param  SWPMIx SWPMI Instance
 667   * @retval None
 668   */
 669 __STATIC_INLINE void LL_SWPMI_ClearFlag_TC(SWPMI_TypeDef *SWPMIx)
 670 {
 671   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTCF);
 672 }
 673
 674 /**
 675   * @brief  Clear slave resume flag
 676   * @rmtoll ICR          CSRF          LL_SWPMI_ClearFlag_SR
 677   * @param  SWPMIx SWPMI Instance
 678   * @retval None
 679   */
 680 __STATIC_INLINE void LL_SWPMI_ClearFlag_SR(SWPMI_TypeDef *SWPMIx)
 681 {
 682   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CSRF);
 683 }
 684
 685 /**
 686   * @brief  Clear SWPMI transceiver ready flag
 687   * @rmtoll ISR          CRDYF        LL_SWPMI_ClearFlag_RDY
 688   * @param  SWPMIx SWPMI Instance
 689   * @retval None
 690   */
 691 __STATIC_INLINE void LL_SWPMI_ClearFlag_RDY(SWPMI_TypeDef *SWPMIx)
 692 {
 693   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRDYF);
 694 }
 695
 696 /**
 697   * @}
 698   */
 699
 700 /** @defgroup SWPMI_LL_EF_IT_Management IT_Management
 701   * @{
 702   */
 703
 704 /**
 705   * @brief  Enable SWPMI transceiver ready interrupt
 706   * @rmtoll IER          RDYIE         LL_SWPMI_EnableIT_RDY
 707   * @param  SWPMIx SWPMI Instance
 708   * @retval None
 709   */
 710 __STATIC_INLINE void LL_SWPMI_EnableIT_RDY(SWPMI_TypeDef *SWPMIx)
 711 {
 712   SET_BIT(SWPMIx->IER, SWPMI_IER_RDYIE);
 713 }
 714
 715 /**
 716   * @brief  Enable Slave resume interrupt
 717   * @rmtoll IER          SRIE          LL_SWPMI_EnableIT_SR
 718   * @param  SWPMIx SWPMI Instance
 719   * @retval None
 720   */
 721 __STATIC_INLINE void LL_SWPMI_EnableIT_SR(SWPMI_TypeDef *SWPMIx)
 722 {
 723   SET_BIT(SWPMIx->IER, SWPMI_IER_SRIE);
 724 }
 725
 726 /**
 727   * @brief  Enable Transmit complete interrupt
 728   * @rmtoll IER          TCIE          LL_SWPMI_EnableIT_TC
 729   * @param  SWPMIx SWPMI Instance
 730   * @retval None
 731   */
 732 __STATIC_INLINE void LL_SWPMI_EnableIT_TC(SWPMI_TypeDef *SWPMIx)
 733 {
 734   SET_BIT(SWPMIx->IER, SWPMI_IER_TCIE);
 735 }
 736
 737 /**
 738   * @brief  Enable Transmit interrupt
 739   * @rmtoll IER          TIE           LL_SWPMI_EnableIT_TX
 740   * @param  SWPMIx SWPMI Instance
 741   * @retval None
 742   */
 743 __STATIC_INLINE void LL_SWPMI_EnableIT_TX(SWPMI_TypeDef *SWPMIx)
 744 {
 745   SET_BIT(SWPMIx->IER, SWPMI_IER_TIE);
 746 }
 747
 748 /**
 749   * @brief  Enable Receive interrupt
 750   * @rmtoll IER          RIE           LL_SWPMI_EnableIT_RX
 751   * @param  SWPMIx SWPMI Instance
 752   * @retval None
 753   */
 754 __STATIC_INLINE void LL_SWPMI_EnableIT_RX(SWPMI_TypeDef *SWPMIx)
 755 {
 756   SET_BIT(SWPMIx->IER, SWPMI_IER_RIE);
 757 }
 758
 759 /**
 760   * @brief  Enable Transmit underrun error interrupt
 761   * @rmtoll IER          TXUNRIE       LL_SWPMI_EnableIT_TXUNR
 762   * @param  SWPMIx SWPMI Instance
 763   * @retval None
 764   */
 765 __STATIC_INLINE void LL_SWPMI_EnableIT_TXUNR(SWPMI_TypeDef *SWPMIx)
 766 {
 767   SET_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE);
 768 }
 769
 770 /**
 771   * @brief  Enable Receive overrun error interrupt
 772   * @rmtoll IER          RXOVRIE       LL_SWPMI_EnableIT_RXOVR
 773   * @param  SWPMIx SWPMI Instance
 774   * @retval None
 775   */
 776 __STATIC_INLINE void LL_SWPMI_EnableIT_RXOVR(SWPMI_TypeDef *SWPMIx)
 777 {
 778   SET_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE);
 779 }
 780
 781 /**
 782   * @brief  Enable Receive CRC error interrupt
 783   * @rmtoll IER          RXBERIE       LL_SWPMI_EnableIT_RXBER
 784   * @param  SWPMIx SWPMI Instance
 785   * @retval None
 786   */
 787 __STATIC_INLINE void LL_SWPMI_EnableIT_RXBER(SWPMI_TypeDef *SWPMIx)
 788 {
 789   SET_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE);
 790 }
 791
 792 /**
 793   * @brief  Enable Transmit buffer empty interrupt
 794   * @rmtoll IER          TXBEIE        LL_SWPMI_EnableIT_TXBE
 795   * @param  SWPMIx SWPMI Instance
 796   * @retval None
 797   */
 798 __STATIC_INLINE void LL_SWPMI_EnableIT_TXBE(SWPMI_TypeDef *SWPMIx)
 799 {
 800   SET_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE);
 801 }
 802
 803 /**
 804   * @brief  Enable Receive buffer full interrupt
 805   * @rmtoll IER          RXBFIE        LL_SWPMI_EnableIT_RXBF
 806   * @param  SWPMIx SWPMI Instance
 807   * @retval None
 808   */
 809 __STATIC_INLINE void LL_SWPMI_EnableIT_RXBF(SWPMI_TypeDef *SWPMIx)
 810 {
 811   SET_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE);
 812 }
 813
 814 /**
 815   * @brief  Disable SWPMI transceiver ready interrupt
 816   * @rmtoll IER          RDYIE         LL_SWPMI_DisableIT_RDY
 817   * @param  SWPMIx SWPMI Instance
 818   * @retval None
 819   */
 820 __STATIC_INLINE void LL_SWPMI_DisableIT_RDY(SWPMI_TypeDef *SWPMIx)
 821 {
 822   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RDYIE);
 823 }
 824
 825 /**
 826   * @brief  Disable Slave resume interrupt
 827   * @rmtoll IER          SRIE          LL_SWPMI_DisableIT_SR
 828   * @param  SWPMIx SWPMI Instance
 829   * @retval None
 830   */
 831 __STATIC_INLINE void LL_SWPMI_DisableIT_SR(SWPMI_TypeDef *SWPMIx)
 832 {
 833   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_SRIE);
 834 }
 835
 836 /**
 837   * @brief  Disable Transmit complete interrupt
 838   * @rmtoll IER          TCIE          LL_SWPMI_DisableIT_TC
 839   * @param  SWPMIx SWPMI Instance
 840   * @retval None
 841   */
 842 __STATIC_INLINE void LL_SWPMI_DisableIT_TC(SWPMI_TypeDef *SWPMIx)
 843 {
 844   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TCIE);
 845 }
 846
 847 /**
 848   * @brief  Disable Transmit interrupt
 849   * @rmtoll IER          TIE           LL_SWPMI_DisableIT_TX
 850   * @param  SWPMIx SWPMI Instance
 851   * @retval None
 852   */
 853 __STATIC_INLINE void LL_SWPMI_DisableIT_TX(SWPMI_TypeDef *SWPMIx)
 854 {
 855   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TIE);
 856 }
 857
 858 /**
 859   * @brief  Disable Receive interrupt
 860   * @rmtoll IER          RIE           LL_SWPMI_DisableIT_RX
 861   * @param  SWPMIx SWPMI Instance
 862   * @retval None
 863   */
 864 __STATIC_INLINE void LL_SWPMI_DisableIT_RX(SWPMI_TypeDef *SWPMIx)
 865 {
 866   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RIE);
 867 }
 868
 869 /**
 870   * @brief  Disable Transmit underrun error interrupt
 871   * @rmtoll IER          TXUNRIE       LL_SWPMI_DisableIT_TXUNR
 872   * @param  SWPMIx SWPMI Instance
 873   * @retval None
 874   */
 875 __STATIC_INLINE void LL_SWPMI_DisableIT_TXUNR(SWPMI_TypeDef *SWPMIx)
 876 {
 877   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE);
 878 }
 879
 880 /**
 881   * @brief  Disable Receive overrun error interrupt
 882   * @rmtoll IER          RXOVRIE       LL_SWPMI_DisableIT_RXOVR
 883   * @param  SWPMIx SWPMI Instance
 884   * @retval None
 885   */
 886 __STATIC_INLINE void LL_SWPMI_DisableIT_RXOVR(SWPMI_TypeDef *SWPMIx)
 887 {
 888   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE);
 889 }
 890
 891 /**
 892   * @brief  Disable Receive CRC error interrupt
 893   * @rmtoll IER          RXBERIE       LL_SWPMI_DisableIT_RXBER
 894   * @param  SWPMIx SWPMI Instance
 895   * @retval None
 896   */
 897 __STATIC_INLINE void LL_SWPMI_DisableIT_RXBER(SWPMI_TypeDef *SWPMIx)
 898 {
 899   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE);
 900 }
 901
 902 /**
 903   * @brief  Disable Transmit buffer empty interrupt
 904   * @rmtoll IER          TXBEIE        LL_SWPMI_DisableIT_TXBE
 905   * @param  SWPMIx SWPMI Instance
 906   * @retval None
 907   */
 908 __STATIC_INLINE void LL_SWPMI_DisableIT_TXBE(SWPMI_TypeDef *SWPMIx)
 909 {
 910   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE);
 911 }
 912
 913 /**
 914   * @brief  Disable Receive buffer full interrupt
 915   * @rmtoll IER          RXBFIE        LL_SWPMI_DisableIT_RXBF
 916   * @param  SWPMIx SWPMI Instance
 917   * @retval None
 918   */
 919 __STATIC_INLINE void LL_SWPMI_DisableIT_RXBF(SWPMI_TypeDef *SWPMIx)
 920 {
 921   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE);
 922 }
 923
 924 /**
 925   * @brief  Check if SWPMI transceiver ready interrupt is enabled
 926   * @rmtoll IER          RDYIE         LL_SWPMI_IsEnabledIT_RDY
 927   * @param  SWPMIx SWPMI Instance
 928   * @retval State of bit (1 or 0).
 929   */
 930 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RDY(SWPMI_TypeDef *SWPMIx)
 931 {
 932   return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RDYIE) == (SWPMI_IER_RDYIE)) ? 1UL : 0UL);
 933 }
 934
 935 /**
 936   * @brief  Check if Slave resume interrupt is enabled
 937   * @rmtoll IER          SRIE          LL_SWPMI_IsEnabledIT_SR
 938   * @param  SWPMIx SWPMI Instance
 939   * @retval State of bit (1 or 0).
 940   */
 941 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(SWPMI_TypeDef *SWPMIx)
 942 {
 943   return ((READ_BIT(SWPMIx->IER, SWPMI_IER_SRIE) == (SWPMI_IER_SRIE)) ? 1UL : 0UL);
 944 }
 945
 946 /**
 947   * @brief  Check if Transmit complete interrupt is enabled
 948   * @rmtoll IER          TCIE          LL_SWPMI_IsEnabledIT_TC
 949   * @param  SWPMIx SWPMI Instance
 950   * @retval State of bit (1 or 0).
 951   */
 952 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(SWPMI_TypeDef *SWPMIx)
 953 {
 954   return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TCIE) == (SWPMI_IER_TCIE)) ? 1UL : 0UL);
 955 }
 956
 957 /**
 958   * @brief  Check if Transmit interrupt is enabled
 959   * @rmtoll IER          TIE           LL_SWPMI_IsEnabledIT_TX
 960   * @param  SWPMIx SWPMI Instance
 961   * @retval State of bit (1 or 0).
 962   */
 963 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(SWPMI_TypeDef *SWPMIx)
 964 {
 965   return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TIE) == (SWPMI_IER_TIE)) ? 1UL : 0UL);
 966 }
 967
 968 /**
 969   * @brief  Check if Receive interrupt is enabled
 970   * @rmtoll IER          RIE           LL_SWPMI_IsEnabledIT_RX
 971   * @param  SWPMIx SWPMI Instance
 972   * @retval State of bit (1 or 0).
 973   */
 974 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(SWPMI_TypeDef *SWPMIx)
 975 {
 976   return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RIE) == (SWPMI_IER_RIE)) ? 1UL : 0UL);
 977 }
 978
 979 /**
 980   * @brief  Check if Transmit underrun error interrupt is enabled
 981   * @rmtoll IER          TXUNRIE       LL_SWPMI_IsEnabledIT_TXUNR
 982   * @param  SWPMIx SWPMI Instance
 983   * @retval State of bit (1 or 0).
 984   */
 985 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(SWPMI_TypeDef *SWPMIx)
 986 {
 987   return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE) == (SWPMI_IER_TXUNRIE)) ? 1UL : 0UL);
 988 }
 989
 990 /**
 991   * @brief  Check if Receive overrun error interrupt is enabled
 992   * @rmtoll IER          RXOVRIE       LL_SWPMI_IsEnabledIT_RXOVR
 993   * @param  SWPMIx SWPMI Instance
 994   * @retval State of bit (1 or 0).
 995   */
 996 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(SWPMI_TypeDef *SWPMIx)
 997 {
 998   return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE) == (SWPMI_IER_RXOVRIE)) ? 1UL : 0UL);
 999 }
1000
1001 /**
1002   * @brief  Check if Receive CRC error interrupt is enabled
1003   * @rmtoll IER          RXBERIE       LL_SWPMI_IsEnabledIT_RXBER
1004   * @param  SWPMIx SWPMI Instance
1005   * @retval State of bit (1 or 0).
1006   */
1007 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(SWPMI_TypeDef *SWPMIx)
1008 {
1009   return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE) == (SWPMI_IER_RXBERIE)) ? 1UL : 0UL);
1010 }
1011
1012 /**
1013   * @brief  Check if Transmit buffer empty interrupt is enabled
1014   * @rmtoll IER          TXBEIE        LL_SWPMI_IsEnabledIT_TXBE
1015   * @param  SWPMIx SWPMI Instance
1016   * @retval State of bit (1 or 0).
1017   */
1018 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(SWPMI_TypeDef *SWPMIx)
1019 {
1020   return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE) == (SWPMI_IER_TXBEIE)) ? 1UL : 0UL);
1021 }
1022
1023 /**
1024   * @brief  Check if Receive buffer full interrupt is enabled
1025   * @rmtoll IER          RXBFIE        LL_SWPMI_IsEnabledIT_RXBF
1026   * @param  SWPMIx SWPMI Instance
1027   * @retval State of bit (1 or 0).
1028   */
1029 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBF(SWPMI_TypeDef *SWPMIx)
1030 {
1031   return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE) == (SWPMI_IER_RXBFIE)) ? 1UL : 0UL);
1032 }
1033
1034 /**
1035   * @}
1036   */
1037
1038 /** @defgroup SWPMI_LL_EF_DMA_Management DMA_Management
1039   * @{
1040   */
1041
1042 /**
1043   * @brief  Enable DMA mode for reception
1044   * @rmtoll CR           RXDMA         LL_SWPMI_EnableDMAReq_RX
1045   * @param  SWPMIx SWPMI Instance
1046   * @retval None
1047   */
1048 __STATIC_INLINE void LL_SWPMI_EnableDMAReq_RX(SWPMI_TypeDef *SWPMIx)
1049 {
1050   SET_BIT(SWPMIx->CR, SWPMI_CR_RXDMA);
1051 }
1052
1053 /**
1054   * @brief  Disable DMA mode for reception
1055   * @rmtoll CR           RXDMA         LL_SWPMI_DisableDMAReq_RX
1056   * @param  SWPMIx SWPMI Instance
1057   * @retval None
1058   */
1059 __STATIC_INLINE void LL_SWPMI_DisableDMAReq_RX(SWPMI_TypeDef *SWPMIx)
1060 {
1061   CLEAR_BIT(SWPMIx->CR, SWPMI_CR_RXDMA);
1062 }
1063
1064 /**
1065   * @brief  Check if DMA mode for reception is enabled
1066   * @rmtoll CR           RXDMA         LL_SWPMI_IsEnabledDMAReq_RX
1067   * @param  SWPMIx SWPMI Instance
1068   * @retval State of bit (1 or 0).
1069   */
1070 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_RX(SWPMI_TypeDef *SWPMIx)
1071 {
1072   return ((READ_BIT(SWPMIx->CR, SWPMI_CR_RXDMA) == (SWPMI_CR_RXDMA)) ? 1UL : 0UL);
1073 }
1074
1075 /**
1076   * @brief  Enable DMA mode for transmission
1077   * @rmtoll CR           TXDMA         LL_SWPMI_EnableDMAReq_TX
1078   * @param  SWPMIx SWPMI Instance
1079   * @retval None
1080   */
1081 __STATIC_INLINE void LL_SWPMI_EnableDMAReq_TX(SWPMI_TypeDef *SWPMIx)
1082 {
1083   SET_BIT(SWPMIx->CR, SWPMI_CR_TXDMA);
1084 }
1085
1086 /**
1087   * @brief  Disable DMA mode for transmission
1088   * @rmtoll CR           TXDMA         LL_SWPMI_DisableDMAReq_TX
1089   * @param  SWPMIx SWPMI Instance
1090   * @retval None
1091   */
1092 __STATIC_INLINE void LL_SWPMI_DisableDMAReq_TX(SWPMI_TypeDef *SWPMIx)
1093 {
1094   CLEAR_BIT(SWPMIx->CR, SWPMI_CR_TXDMA);
1095 }
1096
1097 /**
1098   * @brief  Check if DMA mode for transmission is enabled
1099   * @rmtoll CR           TXDMA         LL_SWPMI_IsEnabledDMAReq_TX
1100   * @param  SWPMIx SWPMI Instance
1101   * @retval State of bit (1 or 0).
1102   */
1103 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(SWPMI_TypeDef *SWPMIx)
1104 {
1105   return ((READ_BIT(SWPMIx->CR, SWPMI_CR_TXDMA) == (SWPMI_CR_TXDMA)) ? 1UL : 0UL);
1106 }
1107
1108 /**
1109   * @brief  Get the data register address used for DMA transfer
1110   * @rmtoll TDR          TD            LL_SWPMI_DMA_GetRegAddr\n
1111   *         RDR          RD            LL_SWPMI_DMA_GetRegAddr
1112   * @param  SWPMIx SWPMI Instance
1113   * @param  Direction This parameter can be one of the following values:
1114   *         @arg @ref LL_SWPMI_DMA_REG_DATA_TRANSMIT
1115   *         @arg @ref LL_SWPMI_DMA_REG_DATA_RECEIVE
1116   * @retval Address of data register
1117   */
1118 __STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr(SWPMI_TypeDef *SWPMIx, uint32_t Direction)
1119 {
1120   uint32_t data_reg_addr;
1121
1122   if (Direction == LL_SWPMI_DMA_REG_DATA_TRANSMIT)
1123   {
1124     /* return address of TDR register */
1125     data_reg_addr = (uint32_t)&(SWPMIx->TDR);
1126   }
1127   else
1128   {
1129     /* return address of RDR register */
1130     data_reg_addr = (uint32_t)&(SWPMIx->RDR);
1131   }
1132
1133   return data_reg_addr;
1134 }
1135
1136 /**
1137   * @}
1138   */
1139
1140 /** @defgroup SWPMI_LL_EF_Data_Management Data_Management
1141   * @{
1142   */
1143
1144 /**
1145   * @brief  Retrieve number of data bytes present in payload of received frame
1146   * @rmtoll RFL          RFL           LL_SWPMI_GetReceiveFrameLength
1147   * @param  SWPMIx SWPMI Instance
1148   * @retval Value between Min_Data=0x00 and Max_Data=0x1F
1149   */
1150 __STATIC_INLINE uint32_t LL_SWPMI_GetReceiveFrameLength(SWPMI_TypeDef *SWPMIx)
1151 {
1152   return (uint32_t)(READ_BIT(SWPMIx->RFL, SWPMI_RFL_RFL));
1153 }
1154
1155 /**
1156   * @brief  Transmit Data Register
1157   * @rmtoll TDR          TD            LL_SWPMI_TransmitData32
1158   * @param  SWPMIx SWPMI Instance
1159   * @param  TxData Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1160   * @retval None
1161   */
1162 __STATIC_INLINE void LL_SWPMI_TransmitData32(SWPMI_TypeDef *SWPMIx, uint32_t TxData)
1163 {
1164   WRITE_REG(SWPMIx->TDR, TxData);
1165 }
1166
1167 /**
1168   * @brief  Receive Data Register
1169   * @rmtoll RDR          RD            LL_SWPMI_ReceiveData32
1170   * @param  SWPMIx SWPMI Instance
1171   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1172   */
1173 __STATIC_INLINE uint32_t LL_SWPMI_ReceiveData32(SWPMI_TypeDef *SWPMIx)
1174 {
1175   return (uint32_t)(READ_BIT(SWPMIx->RDR, SWPMI_RDR_RD));
1176 }
1177
1178 /**
1179   * @brief  Enable SWP Transceiver Bypass
1180   * @note   The external interface for SWPMI is SWPMI_IO
1181   *         (SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are not available on GPIOs)
1182   * @rmtoll OR           TBYP          LL_SWPMI_EnableTXBypass
1183   * @param  SWPMIx SWPMI Instance
1184   * @retval None
1185   */
1186 __STATIC_INLINE void LL_SWPMI_EnableTXBypass(SWPMI_TypeDef *SWPMIx)
1187 {
1188   CLEAR_BIT(SWPMIx->OR, SWPMI_OR_TBYP);
1189 }
1190
1191 /**
1192   * @brief  Disable SWP Transceiver Bypass
1193   * @note   SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are available as alternate
1194   *         function on GPIOs. This configuration is selected to connect an external transceiver
1195   * @note   In SWPMI_IO bypass mode, SWPEN bit in SWPMI_CR register must be kept cleared
1196   * @rmtoll OR           TBYP          LL_SWPMI_DisableTXBypass
1197   * @param  SWPMIx SWPMI Instance
1198   * @retval None
1199   */
1200 __STATIC_INLINE void LL_SWPMI_DisableTXBypass(SWPMI_TypeDef *SWPMIx)
1201 {
1202   SET_BIT(SWPMIx->OR, SWPMI_OR_TBYP);
1203 }
1204
1205 /**
1206   * @}
1207   */
1208
1209 #if defined(USE_FULL_LL_DRIVER)
1210 /** @defgroup SWPMI_LL_EF_Init Initialization and de-initialization functions
1211   * @{
1212   */
1213
1214 ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx);
1215 ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_InitStruct);
1216 void        LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct);
1217
1218 /**
1219   * @}
1220   */
1221 #endif /*USE_FULL_LL_DRIVER*/
1222
1223 /**
1224   * @}
1225   */
1226
1227 /**
1228   * @}
1229   */
1230
1231
1232 /**
1233   * @}
1234   */
1235
1236 #ifdef __cplusplus
1237 }
1238 #endif
1239
1240 #endif /* STM32H7xx_LL_SWPMI_H */
1241
1242 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/