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Merge pull request #11270 from haslinghuis/rename_attr
[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_ll_system.h
blobdf3fe3bd021a7aa516928c471b3e567beb85236e
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 @verbatim
7 ==============================================================================
8 ##### How to use this driver #####
9 ==============================================================================
10 [..]
11 The LL SYSTEM driver contains a set of generic APIs that can be
12 used by user:
13 (+) Some of the FLASH features need to be handled in the SYSTEM file.
14 (+) Access to DBGCMU registers
15 (+) Access to SYSCFG registers
16
17 @endverbatim
18 ******************************************************************************
19 * @attention
20 *
21 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
22 * All rights reserved.</center></h2>
23 *
24 * This software component is licensed by ST under BSD 3-Clause license,
25 * the "License"; You may not use this file except in compliance with the
26 * License. You may obtain a copy of the License at:
27 * opensource.org/licenses/BSD-3-Clause
28 *
29 ******************************************************************************
30 */
31
32 /* Define to prevent recursive inclusion -------------------------------------*/
33 #ifndef __STM32H7xx_LL_SYSTEM_H
34 #define __STM32H7xx_LL_SYSTEM_H
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /* Includes ------------------------------------------------------------------*/
41 #include "stm32h7xx.h"
42
43 /** @addtogroup STM32H7xx_LL_Driver
44 * @{
45 */
46
47 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
48
49 /** @defgroup SYSTEM_LL SYSTEM
50 * @{
51 */
52
53 /* Private types -------------------------------------------------------------*/
54 /* Private variables ---------------------------------------------------------*/
55
56 /* Private constants ---------------------------------------------------------*/
57 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
58 * @{
59 */
60 /** @defgroup SYSTEM_LL_EC_FLASH_BANK1_SECTORS SYSCFG Flash Bank1 sectors bits status
61 * @{
62 */
63 #define LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT 0x10000U
64 #define LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT 0x20000U
65 #define LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT 0x40000U
66 #define LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT 0x80000U
67 #define LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT 0x100000U
68 #define LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT 0x200000U
69 #define LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT 0x400000U
70 #define LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT 0x800000U
71 /**
72 * @}
73 */
74
75 /** @defgroup SYSTEM_LL_EC_FLASH_BANK2_SECTORS SYSCFG Flash Bank2 sectors bits status
76 * @{
77 */
78 #define LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT 0x10000U
79 #define LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT 0x20000U
80 #define LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT 0x40000U
81 #define LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT 0x80000U
82 #define LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT 0x100000U
83 #define LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT 0x200000U
84 #define LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT 0x400000U
85 #define LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT 0x800000U
86 /**
87 * @}
88 */
89 /**
90 * @}
91 */
92
93 /* Private macros ------------------------------------------------------------*/
94
95 /* Exported types ------------------------------------------------------------*/
96 /* Exported constants --------------------------------------------------------*/
97 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
98 * @{
99 */
100
101 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
102 * @{
103 */
104 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP /*!< Enable Fast Mode Plus for I2C1 */
105 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP /*!< Enable Fast Mode Plus for I2C2 */
106 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP /*!< Enable Fast Mode Plus for I2C3 */
107 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP /*!< Enable Fast Mode Plus for I2C4 */
108 #if defined(I2C5)
109 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 SYSCFG_PMCR_I2C5_FMP /*!< Enable Fast Mode Plus for I2C5 */
110 #endif /*I2C5*/
111 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
112 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
113 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
114 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
115 /**
116 * @}
117 */
118
119 /** @defgroup SYSTEM_LL_EC_ANALOG_SWITCH Analog Switch control
120 * @{
121 */
122 #if defined(SYSCFG_PMCR_BOOSTEN)
123 #define LL_SYSCFG_ANALOG_SWITCH_BOOSTEN SYSCFG_PMCR_BOOSTEN /*!< I/O analog switch voltage booster enable */
124 #endif /*SYSCFG_PMCR_BOOSTEN*/
125 #define LL_SYSCFG_ANALOG_SWITCH_PA0 SYSCFG_PMCR_PA0SO /*!< PA0 Switch Open */
126 #define LL_SYSCFG_ANALOG_SWITCH_PA1 SYSCFG_PMCR_PA1SO /*!< PA1 Switch Open */
127 #define LL_SYSCFG_ANALOG_SWITCH_PC2 SYSCFG_PMCR_PC2SO /*!< PC2 Switch Open */
128 #define LL_SYSCFG_ANALOG_SWITCH_PC3 SYSCFG_PMCR_PC3SO /*!< PC3 Switch Open */
129 /**
130 * @}
131 */
132
133 #if defined(SYSCFG_PMCR_EPIS_SEL)
134 /** @defgroup SYSTEM_LL_EC_EPIS Ethernet PHY Interface Selection
135 * @{
136 */
137 #define LL_SYSCFG_ETH_MII 0x00000000U /*!< ETH Media MII interface */
138 #define LL_SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL /*!< ETH Media RMII interface */
139 /**
140 * @}
141 */
142 #endif /* SYSCFG_PMCR_EPIS_SEL */
143
144 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
145 * @{
146 */
147 #define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */
148 #define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */
149 #define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */
150 #define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */
151 #define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */
152 #define LL_SYSCFG_EXTI_PORTF 5U /*!< EXTI PORT F */
153 #define LL_SYSCFG_EXTI_PORTG 6U /*!< EXTI PORT G */
154 #define LL_SYSCFG_EXTI_PORTH 7U /*!< EXTI PORT H */
155 #if defined(GPIOI)
156 #define LL_SYSCFG_EXTI_PORTI 8U /*!< EXTI PORT I */
157 #endif /*GPIOI*/
158 #define LL_SYSCFG_EXTI_PORTJ 9U /*!< EXTI PORT J */
159 #define LL_SYSCFG_EXTI_PORTK 10U /*!< EXTI PORT k */
160 /**
161 * @}
162 */
163
164 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
165 * @{
166 */
167 #define LL_SYSCFG_EXTI_LINE0 ((0x000FUL << 16U) | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */
168 #define LL_SYSCFG_EXTI_LINE1 ((0x00F0UL << 16U) | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */
169 #define LL_SYSCFG_EXTI_LINE2 ((0x0F00UL << 16U) | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */
170 #define LL_SYSCFG_EXTI_LINE3 ((0xF000UL << 16U) | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */
171 #define LL_SYSCFG_EXTI_LINE4 ((0x000FUL << 16U) | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */
172 #define LL_SYSCFG_EXTI_LINE5 ((0x00F0UL << 16U) | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */
173 #define LL_SYSCFG_EXTI_LINE6 ((0x0F00UL << 16U) | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */
174 #define LL_SYSCFG_EXTI_LINE7 ((0xF000UL << 16U) | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */
175 #define LL_SYSCFG_EXTI_LINE8 ((0x000FUL << 16U) | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */
176 #define LL_SYSCFG_EXTI_LINE9 ((0x00F0UL << 16U) | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */
177 #define LL_SYSCFG_EXTI_LINE10 ((0x0F00UL << 16U) | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */
178 #define LL_SYSCFG_EXTI_LINE11 ((0xF000UL << 16U) | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */
179 #define LL_SYSCFG_EXTI_LINE12 ((0x000FUL << 16U) | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */
180 #define LL_SYSCFG_EXTI_LINE13 ((0x00F0UL << 16U) | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */
181 #define LL_SYSCFG_EXTI_LINE14 ((0x0F00UL << 16U) | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */
182 #define LL_SYSCFG_EXTI_LINE15 ((0xF000UL << 16U) | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */
183 /**
184 * @}
185 */
186
187 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
188 * @{
189 */
190 #define LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC SYSCFG_CFGR_AXISRAML /*!< Enables and locks the AXIRAM double ECC error signal
191 with Break Input of TIM1/8/15/16/17 and HRTIM */
192
193 #define LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC SYSCFG_CFGR_ITCML /*!< Enables and locks the ITCM double ECC error signal
194 with Break Input of TIM1/8/15/16/17 and HRTIM */
195
196 #define LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC SYSCFG_CFGR_DTCML /*!< Enables and locks the DTCM double ECC error signal
197 with Break Input of TIM1/8/15/16/17 and HRTIM */
198
199 #define LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC SYSCFG_CFGR_SRAM1L /*!< Enables and locks the SRAM1 double ECC error signal
200 with Break Input of TIM1/8/15/16/17 and HRTIM */
201
202 #define LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC SYSCFG_CFGR_SRAM2L /*!< Enables and locks the SRAM2 double ECC error signal
203 with Break Input of TIM1/8/15/16/17 and HRTIM */
204
205 #if defined(SYSCFG_CFGR_SRAM3L)
206 #define LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC SYSCFG_CFGR_SRAM3L /*!< Enables and locks the SRAM3 double ECC error signal
207 with Break Input of TIM1/8/15/16/17 and HRTIM */
208 #endif /*SYSCFG_CFGR_SRAM3L*/
209
210 #define LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC SYSCFG_CFGR_SRAM4L /*!< Enables and locks the SRAM4 double ECC error signal
211 with Break Input of TIM1/8/15/16/17 and HRTIM */
212
213 #define LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC SYSCFG_CFGR_BKRAML /*!< Enables and locks the BKRAM double ECC error signal
214 with Break Input of TIM1/8/15/16/17 and HRTIM */
215
216 #define LL_SYSCFG_TIMBREAK_CM7_LOCKUP SYSCFG_CFGR_CM7L /*!< Enables and locks the Cortex-M7 LOCKUP signal
217 with Break Input of TIM1/8/15/16/17 and HRTIM */
218
219 #define LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC SYSCFG_CFGR_FLASHL /*!< Enables and locks the FLASH double ECC error signal
220 with Break Input of TIM1/8/15/16/17 and HRTIM */
221
222 #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR_PVDL /*!< Enables and locks the PVD connection
223 with TIM1/8/15/16/17 and HRTIM Break Input
224 and also the PVDE and PLS bits of the Power Control Interface */
225 #if defined(DUAL_CORE)
226 #define LL_SYSCFG_TIMBREAK_CM4_LOCKUP SYSCFG_CFGR_CM4L /*!< Enables and locks the Cortex-M4 LOCKUP signal
227 with Break Input of TIM1/8/15/16/17 and HRTIM */
228 #endif /* DUAL_CORE */
229 /**
230 * @}
231 */
232
233 /** @defgroup SYSTEM_LL_EC_CS SYSCFG I/O compensation cell Code selection
234 * @{
235 */
236 #define LL_SYSCFG_CELL_CODE 0U
237 #define LL_SYSCFG_REGISTER_CODE SYSCFG_CCCSR_CS
238 /**
239 * @}
240 */
241
242 /** @defgroup SYSTEM_LL_IWDG1_CONTROL_MODES SYSCFG IWDG1 control modes
243 * @{
244 */
245 #define LL_SYSCFG_IWDG1_SW_CONTROL_MODE 0U
246 #define LL_SYSCFG_IWDG1_HW_CONTROL_MODE SYSCFG_UR11_IWDG1M
247 /**
248 * @}
249 */
250
251 #if defined (DUAL_CORE)
252 /** @defgroup SYSTEM_LL_IWDG2_CONTROL_MODES SYSCFG IWDG2 control modes
253 * @{
254 */
255 #define LL_SYSCFG_IWDG2_SW_CONTROL_MODE 0U
256 #define LL_SYSCFG_IWDG2_HW_CONTROL_MODE SYSCFG_UR12_IWDG2M
257 /**
258 * @}
259 */
260 #endif /* DUAL_CORE */
261
262 /** @defgroup SYSTEM_LL_DTCM_RAM_SIZE SYSCFG DTCM RAM size configuration
263 * @{
264 */
265 #define LL_SYSCFG_DTCM_RAM_SIZE_2KB 0U
266 #define LL_SYSCFG_DTCM_RAM_SIZE_4KB 1U
267 #define LL_SYSCFG_DTCM_RAM_SIZE_8KB 2U
268 #define LL_SYSCFG_DTCM_RAM_SIZE_16KB 3U
269 /**
270 * @}
271 */
272 #ifdef SYSCFG_UR17_TCM_AXI_CFG
273 /** @defgroup SYSTEM_LL_PACKAGE SYSCFG device package
274 * @{
275 */
276 #define LL_SYSCFG_ITCM_AXI_64KB_320KB 0U
277 #define LL_SYSCFG_ITCM_AXI_128KB_256KB 1U
278 #define LL_SYSCFG_ITCM_AXI_192KB_192KB 2U
279 #define LL_SYSCFG_ITCM_AXI_256KB_128KB 3U
280 /**
281 * @}
282 */
283 #endif /* #ifdef SYSCFG_UR17_TCM_AXI_CFG */
284 #if defined(SYSCFG_PKGR_PKG)
285 /** @defgroup SYSTEM_LL_PACKAGE SYSCFG device package
286 * @{
287 */
288 #if (STM32H7_DEV_ID == 0x450UL)
289 #define LL_SYSCFG_LQFP100_PACKAGE 0U
290 #define LL_SYSCFG_TQFP144_PACKAGE 2U
291 #define LL_SYSCFG_TQFP176_UFBGA176_PACKAGE 5U
292 #define LL_SYSCFG_LQFP208_TFBGA240_PACKAGE 8U
293 #elif (STM32H7_DEV_ID == 0x483UL)
294 #define LL_SYSCFG_VFQFPN68_INDUS_PACKAGE 0U
295 #define LL_SYSCFG_TFBGA100_LQFP100_PACKAGE 1U
296 #define LL_SYSCFG_LQFP100_INDUS_PACKAGE 2U
297 #define LL_SYSCFG_TFBGA100_INDUS_PACKAGE 3U
298 #define LL_SYSCFG_WLCSP115_INDUS_PACKAGE 4U
299 #define LL_SYSCFG_LQFP144_PACKAGE 5U
300 #define LL_SYSCFG_UFBGA144_PACKAGE 6U
301 #define LL_SYSCFG_LQFP144_INDUS_PACKAGE 7U
302 #define LL_SYSCFG_UFBGA169_INDUS_PACKAGE 8U
303 #define LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE 9U
304 #define LL_SYSCFG_LQFP176_INDUS_PACKAGE 10U
305 #endif /* STM32H7_DEV_ID == 0x450UL */
306 /**
307 * @}
308 */
309 #endif /* SYSCFG_PKGR_PKG */
310
311 /** @defgroup SYSTEM_LL_SYSCFG_BOR SYSCFG Brownout Reset Threshold Level
312 * @{
313 */
314 #define LL_SYSCFG_BOR_OFF_RESET_LEVEL 0x00000000U
315 #define LL_SYSCFG_BOR_LOW_RESET_LEVEL SYSCFG_UR2_BORH_0
316 #define LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL SYSCFG_UR2_BORH_1
317 #define LL_SYSCFG_BOR_HIGH_RESET_LEVEL SYSCFG_UR2_BORH
318
319 /**
320 * @}
321 */
322
323 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
324 * @{
325 */
326 #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
327 #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
328 #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
329 #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
330 #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
331 /**
332 * @}
333 */
334
335 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
336 * @{
337 */
338 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1LFZ1_DBG_TIM2 /*!< TIM2 counter stopped when core is halted */
339 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1LFZ1_DBG_TIM3 /*!< TIM3 counter stopped when core is halted */
340 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1LFZ1_DBG_TIM4 /*!< TIM4 counter stopped when core is halted */
341 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1LFZ1_DBG_TIM5 /*!< TIM5 counter stopped when core is halted */
342 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1LFZ1_DBG_TIM6 /*!< TIM6 counter stopped when core is halted */
343 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1LFZ1_DBG_TIM7 /*!< TIM7 counter stopped when core is halted */
344 #define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1LFZ1_DBG_TIM12 /*!< TIM12 counter stopped when core is halted */
345 #define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1LFZ1_DBG_TIM13 /*!< TIM13 counter stopped when core is halted */
346 #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1LFZ1_DBG_TIM14 /*!< TIM14 counter stopped when core is halted */
347 #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1LFZ1_DBG_LPTIM1 /*!< LPTIM1 counter stopped when core is halted */
348 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1LFZ1_DBG_I2C1 /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
349 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1LFZ1_DBG_I2C2 /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
350 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1LFZ1_DBG_I2C3 /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
351 #if defined(I2C5)
352 #define LL_DBGMCU_APB1_GRP1_I2C5_STOP DBGMCU_APB1LFZ1_DBG_I2C5 /*!< I2C5 SMBUS timeout mode stopped when Core is halted */
353 #endif /*I2C5*/
354 /**
355 * @}
356 */
357
358
359 /** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
360 * @{
361 */
362 #if defined(DBGMCU_APB1HFZ1_DBG_FDCAN)
363 #define LL_DBGMCU_APB1_GRP2_FDCAN_STOP DBGMCU_APB1HFZ1_DBG_FDCAN /*!< FDCAN is frozen while the core is in debug mode */
364 #endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/
365 #if defined(TIM23)
366 #define LL_DBGMCU_APB1_GRP2_TIM23_STOP DBGMCU_APB1HFZ1_DBG_TIM23 /*!< TIM23 is frozen while the core is in debug mode */
367 #endif /*TIM23*/
368 #if defined(TIM24)
369 #define LL_DBGMCU_APB1_GRP2_TIM24_STOP DBGMCU_APB1HFZ1_DBG_TIM24 /*!< TIM24 is frozen while the core is in debug mode */
370 #endif /*TIM24*/
371 /**
372 * @}
373 */
374
375 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
376 * @{
377 */
378 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ1_DBG_TIM1 /*!< TIM1 counter stopped when core is halted */
379 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ1_DBG_TIM8 /*!< TIM8 counter stopped when core is halted */
380 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ1_DBG_TIM15 /*!< TIM15 counter stopped when core is halted */
381 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ1_DBG_TIM16 /*!< TIM16 counter stopped when core is halted */
382 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ1_DBG_TIM17 /*!< TIM17 counter stopped when core is halted */
383 #if defined(HRTIM1)
384 #define LL_DBGMCU_APB2_GRP1_HRTIM_STOP DBGMCU_APB2FZ1_DBG_HRTIM /*!< HRTIM counter stopped when core is halted */
385 #endif /*HRTIM1*/
386 /**
387 * @}
388 */
389
390 /** @defgroup SYSTEM_LL_EC_APB3_GRP1_STOP_IP DBGMCU APB3 GRP1 STOP IP
391 * @{
392 */
393 #define LL_DBGMCU_APB3_GRP1_WWDG1_STOP DBGMCU_APB3FZ1_DBG_WWDG1 /*!< WWDG1 is frozen while the core is in debug mode */
394 /**
395 * @}
396 */
397
398 /** @defgroup SYSTEM_LL_EC_APB4_GRP1_STOP_IP DBGMCU APB4 GRP1 STOP IP
399 * @{
400 */
401 #define LL_DBGMCU_APB4_GRP1_I2C4_STOP DBGMCU_APB4FZ1_DBG_I2C4 /*!< I2C4 is frozen while the core is in debug mode */
402 #define LL_DBGMCU_APB4_GRP1_LPTIM2_STOP DBGMCU_APB4FZ1_DBG_LPTIM2 /*!< LPTIM2 is frozen while the core is in debug mode */
403 #define LL_DBGMCU_APB4_GRP1_LPTIM3_STOP DBGMCU_APB4FZ1_DBG_LPTIM3 /*!< LPTIM3 is frozen while the core is in debug mode */
404 #define LL_DBGMCU_APB4_GRP1_LPTIM4_STOP DBGMCU_APB4FZ1_DBG_LPTIM4 /*!< LPTIM4 is frozen while the core is in debug mode */
405 #define LL_DBGMCU_APB4_GRP1_LPTIM5_STOP DBGMCU_APB4FZ1_DBG_LPTIM5 /*!< LPTIM5 is frozen while the core is in debug mode */
406 #define LL_DBGMCU_APB4_GRP1_RTC_STOP DBGMCU_APB4FZ1_DBG_RTC /*!< RTC is frozen while the core is in debug mode */
407 #define LL_DBGMCU_APB4_GRP1_IWDG1_STOP DBGMCU_APB4FZ1_DBG_IWDG1 /*!< IWDG1 is frozen while the core is in debug mode */
408 /**
409 * @}
410 */
411
412 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
413 * @{
414 */
415 #define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
416 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
417 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
418 #define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
419 #define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */
420 #define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */
421 #define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */
422 #define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */
423 /**
424 * @}
425 */
426
427 /**
428 * @}
429 */
430
431 /* Exported macro ------------------------------------------------------------*/
432
433 /* Exported functions --------------------------------------------------------*/
434 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
435 * @{
436 */
437
438 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
439 * @{
440 */
441
442 #if defined(SYSCFG_PMCR_EPIS_SEL)
443 /**
444 * @brief Select Ethernet PHY interface
445 * @rmtoll PMCR EPIS_SEL LL_SYSCFG_SetPHYInterface
446 * @param Interface This parameter can be one of the following values:
447 * @arg @ref LL_SYSCFG_ETH_MII
448 * @arg @ref LL_SYSCFG_ETH_RMII
449 * @retval None
450 */
451 __STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
452 {
453 MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, Interface);
454 }
455
456 /**
457 * @brief Get Ethernet PHY interface
458 * @rmtoll PMCR EPIS_SEL LL_SYSCFG_GetPHYInterface
459 * @retval Returned value can be one of the following values:
460 * @arg @ref LL_SYSCFG_ETH_MII
461 * @arg @ref LL_SYSCFG_ETH_RMII
462 */
463 __STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
464 {
465 return (uint32_t)(READ_BIT(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL));
466 }
467
468 #endif /* SYSCFG_PMCR_EPIS_SEL */
469 /**
470 * @brief Open an Analog Switch
471 * @rmtoll PMCR PA0SO LL_SYSCFG_OpenAnalogSwitch
472 * @rmtoll PMCR PA1SO LL_SYSCFG_OpenAnalogSwitch
473 * @rmtoll PMCR PC2SO LL_SYSCFG_OpenAnalogSwitch
474 * @rmtoll PMCR PC3SO LL_SYSCFG_OpenAnalogSwitch
475 * @param AnalogSwitch This parameter can be one of the following values:
476 * @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch
477 * @arg LL_SYSCFG_ANALOG_SWITCH_PA1: PA1 analog switch
478 * @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch
479 * @arg LL_SYSCFG_ANALOG_SWITCH_PC3: PC3 analog switch
480 * @retval None
481 */
482 __STATIC_INLINE void LL_SYSCFG_OpenAnalogSwitch(uint32_t AnalogSwitch)
483 {
484 SET_BIT(SYSCFG->PMCR, AnalogSwitch);
485 }
486
487 /**
488 * @brief Close an Analog Switch
489 * @rmtoll PMCR PA0SO LL_SYSCFG_CloseAnalogSwitch
490 * @rmtoll PMCR PA1SO LL_SYSCFG_CloseAnalogSwitch
491 * @rmtoll PMCR PC2SO LL_SYSCFG_CloseAnalogSwitch
492 * @rmtoll PMCR PC3SO LL_SYSCFG_CloseAnalogSwitch
493 * @param AnalogSwitch This parameter can be one of the following values:
494 * @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch
495 * @arg LL_SYSCFG_ANALOG_SWITCH_PA1: PA1 analog switch
496 * @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch
497 * @arg LL_SYSCFG_ANALOG_SWITCH_PC3: PC3 analog switch
498 * @retval None
499 */
500 __STATIC_INLINE void LL_SYSCFG_CloseAnalogSwitch(uint32_t AnalogSwitch)
501 {
502 CLEAR_BIT(SYSCFG->PMCR, AnalogSwitch);
503 }
504 #ifdef SYSCFG_PMCR_BOOSTEN
505 /**
506 * @brief Enable the Analog booster to reduce the total harmonic distortion
507 * of the analog switch when the supply voltage is lower than 2.7 V
508 * @rmtoll PMCR BOOSTEN LL_SYSCFG_EnableAnalogBooster
509 * @note Activating the booster allows to guaranty the analog switch AC performance
510 * when the supply voltage is below 2.7 V: in this case, the analog switch
511 * performance is the same on the full voltage range
512 * @retval None
513 */
514 __STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
515 {
516 SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
517 }
518
519 /**
520 * @brief Disable the Analog booster
521 * @rmtoll PMCR BOOSTEN LL_SYSCFG_DisableAnalogBooster
522 * @note Activating the booster allows to guaranty the analog switch AC performance
523 * when the supply voltage is below 2.7 V: in this case, the analog switch
524 * performance is the same on the full voltage range
525 * @retval None
526 */
527 __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
528 {
529 CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
530 }
531 #endif /*SYSCFG_PMCR_BOOSTEN*/
532 /**
533 * @brief Enable the I2C fast mode plus driving capability.
534 * @rmtoll SYSCFG_PMCR I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n
535 * SYSCFG_PMCR I2Cx_FMP LL_SYSCFG_EnableFastModePlus
536 * @param ConfigFastModePlus This parameter can be a combination of the following values:
537 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
538 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
539 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
540 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
541 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
542 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
543 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
544 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4(*)
545 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C5(*)
546 *
547 * (*) value not defined in all devices
548 * @retval None
549 */
550 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
551 {
552 SET_BIT(SYSCFG->PMCR, ConfigFastModePlus);
553 }
554
555 /**
556 * @brief Disable the I2C fast mode plus driving capability.
557 * @rmtoll SYSCFG_PMCR I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n
558 * SYSCFG_PMCR I2Cx_FMP LL_SYSCFG_DisableFastModePlus
559 * @param ConfigFastModePlus This parameter can be a combination of the following values:
560 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
561 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
562 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
563 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
564 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
565 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
566 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
567 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4
568 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 (*)
569 *
570 * (*) value not defined in all devices
571 * @retval None
572 */
573 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
574 {
575 CLEAR_BIT(SYSCFG->PMCR, ConfigFastModePlus);
576 }
577
578 /**
579 * @brief Configure source input for the EXTI external interrupt.
580 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
581 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
582 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
583 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
584 * @param Port This parameter can be one of the following values:
585 * @arg @ref LL_SYSCFG_EXTI_PORTA
586 * @arg @ref LL_SYSCFG_EXTI_PORTB
587 * @arg @ref LL_SYSCFG_EXTI_PORTC
588 * @arg @ref LL_SYSCFG_EXTI_PORTD
589 * @arg @ref LL_SYSCFG_EXTI_PORTE
590 * @arg @ref LL_SYSCFG_EXTI_PORTF
591 * @arg @ref LL_SYSCFG_EXTI_PORTG
592 * @arg @ref LL_SYSCFG_EXTI_PORTH
593 * @arg @ref LL_SYSCFG_EXTI_PORTI (*)
594 * @arg @ref LL_SYSCFG_EXTI_PORTJ
595 * @arg @ref LL_SYSCFG_EXTI_PORTK
596 *
597 * (*) value not defined in all devices
598 * @param Line This parameter can be one of the following values:
599 * @arg @ref LL_SYSCFG_EXTI_LINE0
600 * @arg @ref LL_SYSCFG_EXTI_LINE1
601 * @arg @ref LL_SYSCFG_EXTI_LINE2
602 * @arg @ref LL_SYSCFG_EXTI_LINE3
603 * @arg @ref LL_SYSCFG_EXTI_LINE4
604 * @arg @ref LL_SYSCFG_EXTI_LINE5
605 * @arg @ref LL_SYSCFG_EXTI_LINE6
606 * @arg @ref LL_SYSCFG_EXTI_LINE7
607 * @arg @ref LL_SYSCFG_EXTI_LINE8
608 * @arg @ref LL_SYSCFG_EXTI_LINE9
609 * @arg @ref LL_SYSCFG_EXTI_LINE10
610 * @arg @ref LL_SYSCFG_EXTI_LINE11
611 * @arg @ref LL_SYSCFG_EXTI_LINE12
612 * @arg @ref LL_SYSCFG_EXTI_LINE13
613 * @arg @ref LL_SYSCFG_EXTI_LINE14
614 * @arg @ref LL_SYSCFG_EXTI_LINE15
615 * @retval None
616 */
617 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
618 {
619 MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U), Port << ((POSITION_VAL(Line >> 16U)) & 31U));
620 }
621
622 /**
623 * @brief Get the configured defined for specific EXTI Line
624 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
625 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
626 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
627 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
628 * @param Line This parameter can be one of the following values:
629 * @arg @ref LL_SYSCFG_EXTI_LINE0
630 * @arg @ref LL_SYSCFG_EXTI_LINE1
631 * @arg @ref LL_SYSCFG_EXTI_LINE2
632 * @arg @ref LL_SYSCFG_EXTI_LINE3
633 * @arg @ref LL_SYSCFG_EXTI_LINE4
634 * @arg @ref LL_SYSCFG_EXTI_LINE5
635 * @arg @ref LL_SYSCFG_EXTI_LINE6
636 * @arg @ref LL_SYSCFG_EXTI_LINE7
637 * @arg @ref LL_SYSCFG_EXTI_LINE8
638 * @arg @ref LL_SYSCFG_EXTI_LINE9
639 * @arg @ref LL_SYSCFG_EXTI_LINE10
640 * @arg @ref LL_SYSCFG_EXTI_LINE11
641 * @arg @ref LL_SYSCFG_EXTI_LINE12
642 * @arg @ref LL_SYSCFG_EXTI_LINE13
643 * @arg @ref LL_SYSCFG_EXTI_LINE14
644 * @arg @ref LL_SYSCFG_EXTI_LINE15
645 * @retval Returned value can be one of the following values:
646 * @arg @ref LL_SYSCFG_EXTI_PORTA
647 * @arg @ref LL_SYSCFG_EXTI_PORTB
648 * @arg @ref LL_SYSCFG_EXTI_PORTC
649 * @arg @ref LL_SYSCFG_EXTI_PORTD
650 * @arg @ref LL_SYSCFG_EXTI_PORTE
651 * @arg @ref LL_SYSCFG_EXTI_PORTF
652 * @arg @ref LL_SYSCFG_EXTI_PORTG
653 * @arg @ref LL_SYSCFG_EXTI_PORTH
654 * @arg @ref LL_SYSCFG_EXTI_PORTI (*)
655 * @arg @ref LL_SYSCFG_EXTI_PORTJ
656 * @arg @ref LL_SYSCFG_EXTI_PORTK
657 * (*) value not defined in all devices
658 */
659 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
660 {
661 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U)) >> (POSITION_VAL(Line >> 16U) & 31U));
662 }
663
664 /**
665 * @brief Set connections to TIM1/8/15/16/17 and HRTIM Break inputs
666 * @note this feature is available on STM32H7 rev.B and above
667 * @rmtoll SYSCFG_CFGR AXISRAML LL_SYSCFG_SetTIMBreakInputs\n
668 * SYSCFG_CFGR ITCML LL_SYSCFG_SetTIMBreakInputs\n
669 * SYSCFG_CFGR DTCML LL_SYSCFG_SetTIMBreakInputs\n
670 * SYSCFG_CFGR SRAM1L LL_SYSCFG_SetTIMBreakInputs\n
671 * SYSCFG_CFGR SRAM2L LL_SYSCFG_SetTIMBreakInputs\n
672 * SYSCFG_CFGR SRAM3L LL_SYSCFG_SetTIMBreakInputs\n
673 * SYSCFG_CFGR SRAM4L LL_SYSCFG_SetTIMBreakInputs\n
674 * SYSCFG_CFGR BKRAML LL_SYSCFG_SetTIMBreakInputs\n
675 * SYSCFG_CFGR CM7L LL_SYSCFG_SetTIMBreakInputs\n
676 * SYSCFG_CFGR FLASHL LL_SYSCFG_SetTIMBreakInputs\n
677 * SYSCFG_CFGR PVDL LL_SYSCFG_SetTIMBreakInputs\n
678 * SYSCFG_CFGR_CM4L LL_SYSCFG_SetTIMBreakInputs
679 * @param Break This parameter can be a combination of the following values:
680 * @arg @ref LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC
681 * @arg @ref LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC
682 * @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC
683 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC
684 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC
685 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC (*)
686 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC
687 * @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC
688 * @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP
689 * @arg @ref LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC
690 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
691 * @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only)
692 * @retval None
693 * (*) value not defined in all devices
694 */
695 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
696 {
697 #if defined(DUAL_CORE)
698 MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
699 SYSCFG_CFGR_SRAM3L | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \
700 SYSCFG_CFGR_PVDL | SYSCFG_CFGR_CM4L, Break);
701 #elif defined(SYSCFG_CFGR_AXISRAML) && defined(SYSCFG_CFGR_SRAM3L)
702 MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
703 SYSCFG_CFGR_SRAM3L | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \
704 SYSCFG_CFGR_PVDL, Break);
705 #elif defined(SYSCFG_CFGR_AXISRAML)
706 MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
707 SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL,\
708 Break);
709 #else
710 MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML |\
711 SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \
712 SYSCFG_CFGR_PVDL, Break);
713 #endif /* DUAL_CORE */
714 }
715
716 /**
717 * @brief Get connections to TIM1/8/15/16/17 and HRTIM Break inputs
718 * @note this feature is available on STM32H7 rev.B and above
719 * @rmtoll SYSCFG_CFGR AXISRAML LL_SYSCFG_GetTIMBreakInputs\n
720 * SYSCFG_CFGR ITCML LL_SYSCFG_GetTIMBreakInputs\n
721 * SYSCFG_CFGR DTCML LL_SYSCFG_GetTIMBreakInputs\n
722 * SYSCFG_CFGR SRAM1L LL_SYSCFG_GetTIMBreakInputs\n
723 * SYSCFG_CFGR SRAM2L LL_SYSCFG_GetTIMBreakInputs\n
724 * SYSCFG_CFGR SRAM3L LL_SYSCFG_GetTIMBreakInputs\n
725 * SYSCFG_CFGR SRAM4L LL_SYSCFG_GetTIMBreakInputs\n
726 * SYSCFG_CFGR BKRAML LL_SYSCFG_GetTIMBreakInputs\n
727 * SYSCFG_CFGR CM7L LL_SYSCFG_GetTIMBreakInputs\n
728 * SYSCFG_CFGR FLASHL LL_SYSCFG_GetTIMBreakInputs\n
729 * SYSCFG_CFGR PVDL LL_SYSCFG_GetTIMBreakInputs\n
730 * SYSCFG_CFGR_CM4L LL_SYSCFG_GetTIMBreakInputs
731 * @retval Returned value can be can be a combination of the following values:
732 * @arg @ref LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC
733 * @arg @ref LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC
734 * @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC
735 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC
736 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC
737 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC (*)
738 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC
739 * @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC
740 * @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP
741 * @arg @ref LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC
742 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
743 * @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only)
744 * (*) value not defined in all devices
745 */
746 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
747 {
748 #if defined(DUAL_CORE)
749 return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \
750 SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \
751 SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \
752 SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL | SYSCFG_CFGR_CM4L));
753 #elif defined (SYSCFG_CFGR_AXISRAML) && defined(SYSCFG_CFGR_SRAM3L)
754 return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \
755 SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \
756 SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \
757 SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL ));
758 #elif defined (SYSCFG_CFGR_AXISRAML)
759 return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \
760 SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
761 SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \
762 SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL ));
763 #else
764 return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_CM7L | \
765 SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL ));
766 #endif /* DUAL_CORE */
767 }
768
769 /**
770 * @brief Enable the Compensation Cell
771 * @rmtoll CCCSR EN LL_SYSCFG_EnableCompensationCell
772 * @note The I/O compensation cell can be used only when the device supply
773 * voltage ranges from 2.4 to 3.6 V
774 * @retval None
775 */
776 __STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
777 {
778 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
779 }
780
781 /**
782 * @brief Disable the Compensation Cell
783 * @rmtoll CCCSR EN LL_SYSCFG_DisableCompensationCell
784 * @note The I/O compensation cell can be used only when the device supply
785 * voltage ranges from 2.4 to 3.6 V
786 * @retval None
787 */
788 __STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
789 {
790 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
791 }
792
793 /**
794 * @brief Check if the Compensation Cell is enabled
795 * @rmtoll CCCSR EN LL_SYSCFG_IsEnabledCompensationCell
796 * @retval State of bit (1 or 0).
797 */
798 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledCompensationCell(void)
799 {
800 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) == SYSCFG_CCCSR_EN) ? 1UL : 0UL);
801 }
802
803 /**
804 * @brief Get Compensation Cell ready Flag
805 * @rmtoll CCCSR READY LL_SYSCFG_IsActiveFlag_CMPCR
806 * @retval State of bit (1 or 0).
807 */
808 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
809 {
810 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_READY) == (SYSCFG_CCCSR_READY)) ? 1UL : 0UL);
811 }
812
813 /**
814 * @brief Enable the I/O speed optimization when the product voltage is low.
815 * @rmtoll CCCSR HSLV LL_SYSCFG_EnableIOSpeedOptimize
816 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
817 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
818 * might be destructive.
819 * @retval None
820 */
821 __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization(void)
822 {
823 #if defined(SYSCFG_CCCSR_HSLV)
824 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
825 #else
826 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0);
827 #endif /* SYSCFG_CCCSR_HSLV */
828 }
829
830 #if defined(SYSCFG_CCCSR_HSLV1)
831 /**
832 * @brief Enable the I/O speed optimization when the product voltage is low.
833 * @rmtoll CCCSR HSLV1 LL_SYSCFG_EnableIOSpeedOptimize
834 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
835 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
836 * might be destructive.
837 * @retval None
838 */
839 __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization1(void)
840 {
841 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1);
842 }
843
844 /**
845 * @brief Enable the I/O speed optimization when the product voltage is low.
846 * @rmtoll CCCSR HSLV2 LL_SYSCFG_EnableIOSpeedOptimize
847 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
848 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
849 * might be destructive.
850 * @retval None
851 */
852 __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization2(void)
853 {
854 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2);
855 }
856
857 /**
858 * @brief Enable the I/O speed optimization when the product voltage is low.
859 * @rmtoll CCCSR HSLV3 LL_SYSCFG_EnableIOSpeedOptimize
860 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
861 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
862 * might be destructive.
863 * @retval None
864 */
865 __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization3(void)
866 {
867 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3);
868 }
869 #endif /*SYSCFG_CCCSR_HSLV1*/
870
871
872 /**
873 * @brief To Disable optimize the I/O speed when the product voltage is low.
874 * @rmtoll CCCSR HSLV LL_SYSCFG_DisableIOSpeedOptimize
875 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
876 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
877 * might be destructive.
878 * @retval None
879 */
880 __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization(void)
881 {
882 #if defined(SYSCFG_CCCSR_HSLV)
883 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
884 #else
885 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0);
886 #endif /* SYSCFG_CCCSR_HSLV */
887 }
888
889 #if defined(SYSCFG_CCCSR_HSLV1)
890 /**
891 * @brief To Disable optimize the I/O speed when the product voltage is low.
892 * @rmtoll CCCSR HSLV1 LL_SYSCFG_DisableIOSpeedOptimize
893 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
894 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
895 * might be destructive.
896 * @retval None
897 */
898 __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization1(void)
899 {
900 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1);
901 }
902
903 /**
904 * @brief To Disable optimize the I/O speed when the product voltage is low.
905 * @rmtoll CCCSR HSLV2 LL_SYSCFG_DisableIOSpeedOptimize
906 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
907 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
908 * might be destructive.
909 * @retval None
910 */
911 __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization2(void)
912 {
913 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2);
914 }
915
916 /**
917 * @brief To Disable optimize the I/O speed when the product voltage is low.
918 * @rmtoll CCCSR HSLV3 LL_SYSCFG_DisableIOSpeedOptimize
919 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
920 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
921 * might be destructive.
922 * @retval None
923 */
924 __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization3(void)
925 {
926 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3);
927 }
928 #endif /*SYSCFG_CCCSR_HSLV1*/
929
930 /**
931 * @brief Check if the I/O speed optimization is enabled
932 * @rmtoll CCCSR HSLV LL_SYSCFG_IsEnabledIOSpeedOptimization
933 * @retval State of bit (1 or 0).
934 */
935 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization(void)
936 {
937 #if defined(SYSCFG_CCCSR_HSLV)
938 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV) == SYSCFG_CCCSR_HSLV) ? 1UL : 0UL);
939 #else
940 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0) == SYSCFG_CCCSR_HSLV0) ? 1UL : 0UL);
941 #endif /*SYSCFG_CCCSR_HSLV*/
942 }
943
944 #if defined(SYSCFG_CCCSR_HSLV1)
945 /**
946 * @brief Check if the I/O speed optimization is enabled
947 * @rmtoll CCCSR HSLV1 LL_SYSCFG_IsEnabledIOSpeedOptimization
948 * @retval State of bit (1 or 0).
949 */
950 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization1(void)
951 {
952 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1) == SYSCFG_CCCSR_HSLV1) ? 1UL : 0UL);
953 }
954
955 /**
956 * @brief Check if the I/O speed optimization is enabled
957 * @rmtoll CCCSR HSLV2 LL_SYSCFG_IsEnabledIOSpeedOptimization
958 * @retval State of bit (1 or 0).
959 */
960 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization2(void)
961 {
962 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2) == SYSCFG_CCCSR_HSLV2) ? 1UL : 0UL);
963 }
964
965 /**
966 * @brief Check if the I/O speed optimization is enabled
967 * @rmtoll CCCSR HSLV3 LL_SYSCFG_IsEnabledIOSpeedOptimization
968 * @retval State of bit (1 or 0).
969 */
970 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization3(void)
971 {
972 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3) == SYSCFG_CCCSR_HSLV3) ? 1UL : 0UL);
973 }
974 #endif /*SYSCFG_CCCSR_HSLV1*/
975
976 /**
977 * @brief Set the code selection for the I/O Compensation cell
978 * @rmtoll CCCSR CS LL_SYSCFG_SetCellCompensationCode
979 * @param CompCode: Selects the code to be applied for the I/O compensation cell
980 * This parameter can be one of the following values:
981 * @arg LL_SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
982 * @arg LL_SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
983 * @retval None
984 */
985 __STATIC_INLINE void LL_SYSCFG_SetCellCompensationCode(uint32_t CompCode)
986 {
987 SET_BIT(SYSCFG->CCCSR, CompCode);
988 }
989
990 /**
991 * @brief Get the code selected for the I/O Compensation cell
992 * @rmtoll CCCSR CS LL_SYSCFG_GetCellCompensationCode
993 * @retval Returned value can be one of the following values:
994 * @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
995 * @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR)
996 */
997 __STATIC_INLINE uint32_t LL_SYSCFG_GetCellCompensationCode(void)
998 {
999 return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS));
1000 }
1001
1002 #ifdef SYSCFG_CCCSR_CS_MMC
1003
1004 /**
1005 * @brief Get the code selected for the I/O Compensation cell on the VDDMMC power rail
1006 * @rmtoll CCCSR CS LL_SYSCFG_GetCellCompensationCode
1007 * @retval Returned value can be one of the following values:
1008 * @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
1009 * @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR)
1010 */
1011 __STATIC_INLINE uint32_t LL_SYSCFG_MMCGetCellCompensationCode(void)
1012 {
1013 return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS_MMC));
1014 }
1015 #endif /*SYSCFG_CCCSR_CS_MMC*/
1016
1017 /**
1018 * @brief Get I/O compensation cell value for PMOS transistors
1019 * @rmtoll CCVR PCV LL_SYSCFG_GetPMOSCompensationValue
1020 * @retval Returned value is the I/O compensation cell value for PMOS transistors
1021 */
1022 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationValue(void)
1023 {
1024 return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV));
1025 }
1026
1027 /**
1028 * @brief Get I/O compensation cell value for NMOS transistors
1029 * @rmtoll CCVR NCV LL_SYSCFG_GetNMOSCompensationValue
1030 * @retval Returned value is the I/O compensation cell value for NMOS transistors
1031 */
1032 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationValue(void)
1033 {
1034 return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV));
1035 }
1036
1037 /**
1038 * @brief Set I/O compensation cell code for PMOS transistors
1039 * @rmtoll CCCR PCC LL_SYSCFG_SetPMOSCompensationCode
1040 * @param PMOSCode PMOS compensation code
1041 * This code is applied to the I/O compensation cell when the CS bit of the
1042 * SYSCFG_CMPCR is set
1043 * @retval None
1044 */
1045 __STATIC_INLINE void LL_SYSCFG_SetPMOSCompensationCode(uint32_t PMOSCode)
1046 {
1047 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC, PMOSCode);
1048 }
1049
1050 /**
1051 * @brief Get I/O compensation cell code for PMOS transistors
1052 * @rmtoll CCCR PCC LL_SYSCFG_GetPMOSCompensationCode
1053 * @retval Returned value is the I/O compensation cell code for PMOS transistors
1054 */
1055 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationCode(void)
1056 {
1057 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC));
1058 }
1059
1060 #ifdef SYSCFG_CCCR_PCC_MMC
1061
1062 /**
1063 * @brief Set I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail
1064 * @rmtoll CCCR PCC LL_SYSCFG_SetPMOSCompensationCode
1065 * @param PMOSCode PMOS compensation code
1066 * This code is applied to the I/O compensation cell when the CS bit of the
1067 * SYSCFG_CMPCR is set
1068 * @retval None
1069 */
1070 __STATIC_INLINE void LL_SYSCFG_MMCSetPMOSCompensationCode(uint32_t PMOSCode)
1071 {
1072 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC, PMOSCode);
1073 }
1074
1075 /**
1076 * @brief Get I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail
1077 * @rmtoll CCCR PCC LL_SYSCFG_GetPMOSCompensationCode
1078 * @retval Returned value is the I/O compensation cell code for PMOS transistors
1079 */
1080 __STATIC_INLINE uint32_t LL_SYSCFG_MMCGetPMOSCompensationCode(void)
1081 {
1082 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC));
1083 }
1084 #endif /* SYSCFG_CCCR_PCC_MMC */
1085
1086 /**
1087 * @brief Set I/O compensation cell code for NMOS transistors
1088 * @rmtoll CCCR NCC LL_SYSCFG_SetNMOSCompensationCode
1089 * @param NMOSCode NMOS compensation code
1090 * This code is applied to the I/O compensation cell when the CS bit of the
1091 * SYSCFG_CMPCR is set
1092 * @retval None
1093 */
1094 __STATIC_INLINE void LL_SYSCFG_SetNMOSCompensationCode(uint32_t NMOSCode)
1095 {
1096 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC, NMOSCode);
1097 }
1098
1099 /**
1100 * @brief Get I/O compensation cell code for NMOS transistors
1101 * @rmtoll CCCR NCC LL_SYSCFG_GetNMOSCompensationCode
1102 * @retval Returned value is the I/O compensation cell code for NMOS transistors
1103 */
1104 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationCode(void)
1105 {
1106 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC));
1107 }
1108
1109 #ifdef SYSCFG_CCCR_NCC_MMC
1110
1111 /**
1112 * @brief Set I/O compensation cell code for NMOS transistors on the VDDMMC power rail.
1113 * @rmtoll CCCR NCC LL_SYSCFG_SetNMOSCompensationCode
1114 * @param NMOSCode: NMOS compensation code
1115 * This code is applied to the I/O compensation cell when the CS bit of the
1116 * SYSCFG_CMPCR is set
1117 * @retval None
1118 */
1119 __STATIC_INLINE void LL_SYSCFG_VDMMCSetNMOSCompensationCode(uint32_t NMOSCode)
1120 {
1121 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC, NMOSCode);
1122 }
1123
1124 /**
1125 * @brief Get I/O compensation cell code for NMOS transistors on the VDDMMC power rail.
1126 * @rmtoll CCCR NCC LL_SYSCFG_GetNMOSCompensationCode
1127 * @retval Returned value is the I/O compensation cell code for NMOS transistors
1128 */
1129 __STATIC_INLINE uint32_t LL_SYSCFG_VDMMCGetNMOSCompensationCode(void)
1130 {
1131 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC));
1132 }
1133 #endif /*SYSCFG_CCCR_NCC_MMC*/
1134
1135 #ifdef SYSCFG_PKGR_PKG
1136 /**
1137 * @brief Get the device package
1138 * @rmtoll PKGR PKG LL_SYSCFG_GetPackage
1139 * @retval Returned value can be one of the following values:
1140 * @arg @ref LL_SYSCFG_LQFP100_PACKAGE (*)
1141 * @arg @ref LL_SYSCFG_TQFP144_PACKAGE (*)
1142 * @arg @ref LL_SYSCFG_TQFP176_UFBGA176_PACKAGE (*)
1143 * @arg @ref LL_SYSCFG_LQFP208_TFBGA240_PACKAGE (*)
1144 * @arg @ref LL_SYSCFG_VFQFPN68_INDUS_PACKAGE (*)
1145 * @arg @ref LL_SYSCFG_TFBGA100_LQFP100_PACKAGE (*)
1146 * @arg @ref LL_SYSCFG_LQFP100_INDUS_PACKAGE (**)
1147 * @arg @ref LL_SYSCFG_TFBGA100_INDUS_PACKAGE (**)
1148 * @arg @ref LL_SYSCFG_WLCSP115_INDUS_PACKAGE (**)
1149 * @arg @ref LL_SYSCFG_LQFP144_PACKAGE (**)
1150 * @arg @ref LL_SYSCFG_UFBGA144_PACKAGE (**)
1151 * @arg @ref LL_SYSCFG_LQFP144_INDUS_PACKAGE (**)
1152 * @arg @ref LL_SYSCFG_UFBGA169_INDUS_PACKAGE (**)
1153 * @arg @ref LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE (**)
1154 * @arg @ref LL_SYSCFG_LQFP176_INDUS_PACKAGE (**)
1155 *
1156 * (*) : For stm32h74xxx and stm32h75xxx family lines.
1157 * (**): For stm32h72xxx and stm32h73xxx family lines.
1158 */
1159 __STATIC_INLINE uint32_t LL_SYSCFG_GetPackage(void)
1160 {
1161 return (uint32_t)(READ_BIT(SYSCFG->PKGR, SYSCFG_PKGR_PKG));
1162 }
1163 #endif /*SYSCFG_PKGR_PKG*/
1164
1165 #ifdef SYSCFG_UR0_RDP
1166 /**
1167 * @brief Get the Flash memory protection level
1168 * @rmtoll UR0 RDP LL_SYSCFG_GetFLashProtectionLevel
1169 * @retval Returned value can be one of the following values:
1170 * 0xAA : RDP level 0
1171 * 0xCC : RDP level 2
1172 * Any other value : RDP level 1
1173 */
1174 __STATIC_INLINE uint32_t LL_SYSCFG_GetFLashProtectionLevel(void)
1175 {
1176 return (uint32_t)(READ_BIT(SYSCFG->UR0, SYSCFG_UR0_RDP));
1177 }
1178 #ifdef SYSCFG_UR0_BKS
1179 /**
1180 * @brief Indicate if the Flash memory bank addresses are inverted or not
1181 * @rmtoll UR0 BKS LL_SYSCFG_IsFLashBankAddressesSwaped
1182 * @retval State of bit (1 or 0).
1183 */
1184 __STATIC_INLINE uint32_t LL_SYSCFG_IsFLashBankAddressesSwaped(void)
1185 {
1186 return ((READ_BIT(SYSCFG->UR0, SYSCFG_UR0_BKS) == 0U) ? 1UL : 0UL);
1187 }
1188 #endif /*SYSCFG_UR0_BKS*/
1189
1190 /**
1191 * @brief Get the BOR Threshold Reset Level
1192 * @rmtoll UR2 BORH LL_SYSCFG_GetBrownoutResetLevel
1193 * @retval Returned value can be one of the following values:
1194 * @arg @ref LL_SYSCFG_BOR_HIGH_RESET_LEVEL
1195 * @arg @ref LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL
1196 * @arg @ref LL_SYSCFG_BOR_LOW_RESET_LEVEL
1197 * @arg @ref LL_SYSCFG_BOR_OFF_RESET_LEVEL
1198 */
1199 __STATIC_INLINE uint32_t LL_SYSCFG_GetBrownoutResetLevel(void)
1200 {
1201 return (uint32_t)(READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BORH));
1202 }
1203 /**
1204 * @brief BootCM7 address 0 configuration
1205 * @rmtoll UR2 BOOT_ADD0 LL_SYSCFG_SetCM7BootAddress0
1206 * @param BootAddress :Specifies the CM7 Boot Address to be loaded in Address0
1207 * @retval None
1208 */
1209 __STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress0(uint16_t BootAddress)
1210 {
1211 /* Configure CM7 BOOT ADD0 */
1212 #if defined(DUAL_CORE)
1213 MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BCM7_ADD0_Pos));
1214 #else
1215 MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BOOT_ADD0_Pos));
1216 #endif /*DUAL_CORE*/
1217
1218 }
1219
1220 /**
1221 * @brief Get BootCM7 address 0
1222 * @rmtoll UR2 BOOT_ADD0 LL_SYSCFG_GetCM7BootAddress0
1223 * @retval Returned the CM7 Boot Address0
1224 */
1225 __STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress0(void)
1226 {
1227 /* Get CM7 BOOT ADD0 */
1228 #if defined(DUAL_CORE)
1229 return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0) >> SYSCFG_UR2_BCM7_ADD0_Pos);
1230 #else
1231 return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0) >> SYSCFG_UR2_BOOT_ADD0_Pos);
1232 #endif /*DUAL_CORE*/
1233 }
1234
1235 /**
1236 * @brief BootCM7 address 1 configuration
1237 * @rmtoll UR3 BOOT_ADD1 LL_SYSCFG_SetCM7BootAddress1
1238 * @param BootAddress :Specifies the CM7 Boot Address to be loaded in Address1
1239 * @retval None
1240 */
1241 __STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress1(uint16_t BootAddress)
1242 {
1243 /* Configure CM7 BOOT ADD1 */
1244 #if defined(DUAL_CORE)
1245 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, BootAddress);
1246 #else
1247 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, BootAddress);
1248 #endif /*DUAL_CORE*/
1249 }
1250
1251 /**
1252 * @brief Get BootCM7 address 1
1253 * @rmtoll UR3 BOOT_ADD1 LL_SYSCFG_GetCM7BootAddress1
1254 * @retval Returned the CM7 Boot Address0
1255 */
1256 __STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress1(void)
1257 {
1258 /* Get CM7 BOOT ADD0 */
1259 #if defined(DUAL_CORE)
1260 return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1));
1261 #else
1262 return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1));
1263 #endif /* DUAL_CORE */
1264 }
1265
1266 #if defined(DUAL_CORE)
1267 /**
1268 * @brief BootCM4 address 0 configuration
1269 * @rmtoll UR3 BCM4_ADD0 LL_SYSCFG_SetCM4BootAddress0
1270 * @param BootAddress :Specifies the CM4 Boot Address to be loaded in Address0
1271 * @retval None
1272 */
1273 __STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress0(uint16_t BootAddress)
1274 {
1275 /* Configure CM4 BOOT ADD0 */
1276 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((uint32_t)BootAddress << SYSCFG_UR3_BCM4_ADD0_Pos));
1277 }
1278
1279 /**
1280 * @brief Get BootCM4 address 0
1281 * @rmtoll UR3 BCM4_ADD0 LL_SYSCFG_GetCM4BootAddress0
1282 * @retval Returned the CM4 Boot Address0
1283 */
1284 __STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress0(void)
1285 {
1286 /* Get CM4 BOOT ADD0 */
1287 return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0) >> SYSCFG_UR3_BCM4_ADD0_Pos);
1288 }
1289
1290 /**
1291 * @brief BootCM4 address 1 configuration
1292 * @rmtoll UR4 BCM4_ADD1 LL_SYSCFG_SetCM4BootAddress1
1293 * @param BootAddress :Specifies the CM4 Boot Address to be loaded in Address1
1294 * @retval None
1295 */
1296 __STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress1(uint16_t BootAddress)
1297 {
1298 /* Configure CM4 BOOT ADD1 */
1299 MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, BootAddress);
1300 }
1301
1302 /**
1303 * @brief Get BootCM4 address 1
1304 * @rmtoll UR4 BCM4_ADD1 LL_SYSCFG_GetCM4BootAddress1
1305 * @retval Returned the CM4 Boot Address0
1306 */
1307 __STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress1(void)
1308 {
1309 /* Get CM4 BOOT ADD0 */
1310 return (uint16_t)(READ_BIT(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1));
1311 }
1312 #endif /*DUAL_CORE*/
1313
1314 /**
1315 * @brief Indicates if the flash protected area (Bank 1) is erased by a mass erase
1316 * @rmtoll UR4 MEPAD_BANK1 LL_SYSCFG_IsFlashB1ProtectedAreaErasable
1317 * @retval State of bit (1 or 0).
1318 */
1319 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1ProtectedAreaErasable(void)
1320 {
1321 return ((READ_BIT(SYSCFG->UR4, SYSCFG_UR4_MEPAD_BANK1) == SYSCFG_UR4_MEPAD_BANK1) ? 1UL : 0UL);
1322 }
1323
1324 /**
1325 * @brief Indicates if the flash secured area (Bank 1) is erased by a mass erase
1326 * @rmtoll UR5 MESAD_BANK1 LL_SYSCFG_IsFlashB1SecuredAreaErasable
1327 * @retval State of bit (1 or 0).
1328 */
1329 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1SecuredAreaErasable(void)
1330 {
1331 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_MESAD_BANK1) == SYSCFG_UR5_MESAD_BANK1) ? 1UL : 0UL);
1332 }
1333
1334 /**
1335 * @brief Indicates if the sector 0 of the Flash memory bank 1 is write protected
1336 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector0WriteProtected
1337 * @retval State of bit (1 or 0).
1338 */
1339 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector0WriteProtected(void)
1340 {
1341 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT)) ? 1UL : 0UL);
1342 }
1343
1344 /**
1345 * @brief Indicates if the sector 1 of the Flash memory bank 1 is write protected
1346 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector1WriteProtected
1347 * @retval State of bit (1 or 0).
1348 */
1349 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector1WriteProtected(void)
1350 {
1351 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT)) ? 1UL : 0UL);
1352 }
1353
1354 /**
1355 * @brief Indicates if the sector 2 of the Flash memory bank 1 is write protected
1356 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector2WriteProtected
1357 * @retval State of bit (1 or 0).
1358 */
1359 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector2WriteProtected(void)
1360 {
1361 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT)) ? 1UL : 0UL);
1362 }
1363
1364 /**
1365 * @brief Indicates if the sector 3 of the Flash memory bank 1 is write protected
1366 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector3WriteProtected
1367 * @retval State of bit (1 or 0).
1368 */
1369 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector3WriteProtected(void)
1370 {
1371 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT)) ? 1UL : 0UL);
1372 }
1373
1374 /**
1375 * @brief Indicates if the sector 4 of the Flash memory bank 1 is write protected
1376 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector4WriteProtected
1377 * @retval State of bit (1 or 0).
1378 */
1379 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector4WriteProtected(void)
1380 {
1381 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT)) ? 1UL : 0UL);
1382 }
1383
1384 /**
1385 * @brief Indicates if the sector 5 of the Flash memory bank 1 is write protected
1386 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector5WriteProtected
1387 * @retval State of bit (1 or 0).
1388 */
1389 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector5WriteProtected(void)
1390 {
1391 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT)) ? 1UL : 0UL);
1392 }
1393
1394 /**
1395 * @brief Indicates if the sector 6 of the Flash memory bank 1 is write protected
1396 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector6WriteProtected
1397 * @retval State of bit (1 or 0).
1398 */
1399 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector6WriteProtected(void)
1400 {
1401 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT)) ? 1UL : 0UL);
1402 }
1403
1404 /**
1405 * @brief Indicates if the sector 7 of the Flash memory bank 1 is write protected
1406 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector7WriteProtected
1407 * @retval State of bit (1 or 0).
1408 */
1409 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector7WriteProtected(void)
1410 {
1411 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT)) ? 1UL : 0UL);
1412 }
1413
1414 /**
1415 * @brief Get the protected area start address for Flash bank 1
1416 * @rmtoll UR6 PABEG_BANK1 LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress
1417 * @retval Returned the protected area start address for Flash bank 1
1418 */
1419 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress(void)
1420 {
1421 return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PABEG_BANK1));
1422 }
1423
1424 /**
1425 * @brief Get the protected area end address for Flash bank 1
1426 * @rmtoll UR6 PAEND_BANK1 LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress
1427 * @retval Returned the protected area end address for Flash bank 1
1428 */
1429 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress(void)
1430 {
1431 return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PAEND_BANK1));
1432 }
1433
1434 /**
1435 * @brief Get the secured area start address for Flash bank 1
1436 * @rmtoll UR7 SABEG_BANK1 LL_SYSCFG_GetFlashB1SecuredAreaStartAddress
1437 * @retval Returned the secured area start address for Flash bank 1
1438 */
1439 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaStartAddress(void)
1440 {
1441 return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SABEG_BANK1));
1442 }
1443
1444 /**
1445 * @brief Get the secured area end address for Flash bank 1
1446 * @rmtoll UR7 SAEND_BANK1 LL_SYSCFG_GetFlashB1SecuredAreaEndAddress
1447 * @retval Returned the secured area end address for Flash bank 1
1448 */
1449 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaEndAddress(void)
1450 {
1451 return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SAEND_BANK1));
1452 }
1453
1454 #ifdef SYSCFG_UR8_MEPAD_BANK2
1455 /**
1456 * @brief Indicates if the flash protected area (Bank 2) is erased by a mass erase
1457 * @rmtoll UR8 MEPAD_BANK2 LL_SYSCFG_IsFlashB2ProtectedAreaErasable
1458 * @retval State of bit (1 or 0).
1459 */
1460 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2ProtectedAreaErasable(void)
1461 {
1462 return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MEPAD_BANK2) == SYSCFG_UR8_MEPAD_BANK2) ? 1UL : 0UL);
1463 }
1464
1465 /**
1466 * @brief Indicates if the flash secured area (Bank 2) is erased by a mass erase
1467 * @rmtoll UR8 MESAD_BANK2 LL_SYSCFG_IsFlashB2SecuredAreaErasable
1468 * @retval State of bit (1 or 0).
1469 */
1470 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2SecuredAreaErasable(void)
1471 {
1472 return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MESAD_BANK2) == SYSCFG_UR8_MESAD_BANK2) ? 1UL : 0UL);
1473 }
1474 #endif /*SYSCFG_UR8_MEPAD_BANK2*/
1475
1476 #ifdef SYSCFG_UR9_WRPN_BANK2
1477 /**
1478 * @brief Indicates if the sector 0 of the Flash memory bank 2 is write protected
1479 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector0WriteProtected
1480 * @retval State of bit (1 or 0).
1481 */
1482 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector0WriteProtected(void)
1483 {
1484 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT)) ? 1UL : 0UL);
1485 }
1486
1487 /**
1488 * @brief Indicates if the sector 1 of the Flash memory bank 2 is write protected
1489 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector1WriteProtected
1490 * @retval State of bit (1 or 0).
1491 */
1492 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector1WriteProtected(void)
1493 {
1494 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT)) ? 1UL : 0UL);
1495 }
1496
1497 /**
1498 * @brief Indicates if the sector 2 of the Flash memory bank 2 is write protected
1499 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector2WriteProtected
1500 * @retval State of bit (1 or 0).
1501 */
1502 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector2WriteProtected(void)
1503 {
1504 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT)) ? 1UL : 0UL);
1505 }
1506
1507 /**
1508 * @brief Indicates if the sector 3 of the Flash memory bank 2 is write protected
1509 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector3WriteProtected
1510 * @retval State of bit (1 or 0).
1511 */
1512 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector3WriteProtected(void)
1513 {
1514 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT)) ? 1UL : 0UL);
1515 }
1516
1517 /**
1518 * @brief Indicates if the sector 4 of the Flash memory bank 2 is write protected
1519 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector4WriteProtected
1520 * @retval State of bit (1 or 0).
1521 */
1522 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector4WriteProtected(void)
1523 {
1524 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT)) ? 1UL : 0UL);
1525 }
1526
1527 /**
1528 * @brief Indicates if the sector 5 of the Flash memory bank 2 is write protected
1529 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector5WriteProtected
1530 * @retval State of bit (1 or 0).
1531 */
1532 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector5WriteProtected(void)
1533 {
1534 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT)) ? 1UL : 0UL);
1535 }
1536
1537 /**
1538 * @brief Indicates if the sector 6 of the Flash memory bank 2 is write protected
1539 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector6WriteProtected
1540 * @retval State of bit (1 or 0).
1541 */
1542 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector6WriteProtected(void)
1543 {
1544 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT)) ? 1UL : 0UL);
1545 }
1546
1547 /**
1548 * @brief Indicates if the sector 7 of the Flash memory bank 2 is write protected
1549 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector7WriteProtected
1550 * @retval State of bit (1 or 0).
1551 */
1552 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector7WriteProtected(void)
1553 {
1554 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT)) ? 1UL : 0UL);
1555 }
1556
1557 /**
1558 * @brief Get the protected area start address for Flash bank 2
1559 * @rmtoll UR9 PABEG_BANK2 LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress
1560 * @retval Returned the protected area start address for Flash bank 2
1561 */
1562 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress(void)
1563 {
1564 return (uint32_t)(READ_BIT(SYSCFG->UR9, SYSCFG_UR9_PABEG_BANK2));
1565 }
1566 #endif /*SYSCFG_UR9_WRPN_BANK2*/
1567
1568 #ifdef SYSCFG_UR10_PAEND_BANK2
1569 /**
1570 * @brief Get the protected area end address for Flash bank 2
1571 * @rmtoll UR10 PAEND_BANK2 LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress
1572 * @retval Returned the protected area end address for Flash bank 2
1573 */
1574 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress(void)
1575 {
1576 return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_PAEND_BANK2));
1577 }
1578
1579 /**
1580 * @brief Get the secured area start address for Flash bank 2
1581 * @rmtoll UR10 SABEG_BANK2 LL_SYSCFG_GetFlashB2SecuredAreaStartAddress
1582 * @retval Returned the secured area start address for Flash bank 2
1583 */
1584 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaStartAddress(void)
1585 {
1586 return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_SABEG_BANK2));
1587 }
1588 #endif /*SYSCFG_UR10_PAEND_BANK2*/
1589
1590 #ifdef SYSCFG_UR11_SAEND_BANK2
1591 /**
1592 * @brief Get the secured area end address for Flash bank 2
1593 * @rmtoll UR11 SAEND_BANK2 LL_SYSCFG_GetFlashB2SecuredAreaEndAddress
1594 * @retval Returned the secured area end address for Flash bank 2
1595 */
1596 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaEndAddress(void)
1597 {
1598 return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_SAEND_BANK2));
1599 }
1600 #endif /*SYSCFG_UR11_SAEND_BANK2*/
1601
1602 /**
1603 * @brief Get the Independent Watchdog 1 control mode (Software or Hardware)
1604 * @rmtoll UR11 IWDG1M LL_SYSCFG_GetIWDG1ControlMode
1605 * @retval Returned value can be one of the following values:
1606 * @arg @ref LL_SYSCFG_IWDG1_SW_CONTROL_MODE
1607 * @arg @ref LL_SYSCFG_IWDG1_HW_CONTROL_MODE
1608 */
1609 __STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG1ControlMode(void)
1610 {
1611 return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_IWDG1M));
1612 }
1613
1614 #if defined (DUAL_CORE)
1615 /**
1616 * @brief Get the Independent Watchdog 2 control mode (Software or Hardware)
1617 * @rmtoll UR12 IWDG2M LL_SYSCFG_GetIWDG2ControlMode
1618 * @retval Returned value can be one of the following values:
1619 * @arg @ref LL_SYSCFG_IWDG2_SW_CONTROL_MODE
1620 * @arg @ref LL_SYSCFG_IWDG2_HW_CONTROL_MODE
1621 */
1622 __STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG2ControlMode(void)
1623 {
1624 return (uint32_t)(READ_BIT(SYSCFG->UR12, SYSCFG_UR12_IWDG2M));
1625 }
1626 #endif /* DUAL_CORE */
1627
1628 /**
1629 * @brief Indicates the Secure mode status
1630 * @rmtoll UR12 SECURE LL_SYSCFG_IsSecureModeEnabled
1631 * @retval State of bit (1 or 0).
1632 */
1633 __STATIC_INLINE uint32_t LL_SYSCFG_IsSecureModeEnabled(void)
1634 {
1635 return ((READ_BIT(SYSCFG->UR12, SYSCFG_UR12_SECURE) == SYSCFG_UR12_SECURE) ? 1UL : 0UL);
1636 }
1637
1638 /**
1639 * @brief Indicates if a reset is generated when D1 domain enters DStandby mode
1640 * @rmtoll UR13 D1SBRST LL_SYSCFG_IsD1StandbyGenerateReset
1641 * @retval State of bit (1 or 0).
1642 */
1643 __STATIC_INLINE uint32_t LL_SYSCFG_IsD1StandbyGenerateReset(void)
1644 {
1645 return ((READ_BIT(SYSCFG->UR13, SYSCFG_UR13_D1SBRST) == 0U) ? 1UL : 0UL);
1646 }
1647
1648 /**
1649 * @brief Get the secured DTCM RAM size
1650 * @rmtoll UR13 SDRS LL_SYSCFG_GetSecuredDTCMSize
1651 * @retval Returned value can be one of the following values:
1652 * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_2KB
1653 * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_4KB
1654 * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_8KB
1655 * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_16KB
1656 */
1657 __STATIC_INLINE uint32_t LL_SYSCFG_GetSecuredDTCMSize(void)
1658 {
1659 return (uint32_t)(READ_BIT(SYSCFG->UR13, SYSCFG_UR13_SDRS));
1660 }
1661
1662 /**
1663 * @brief Indicates if a reset is generated when D1 domain enters DStop mode
1664 * @rmtoll UR14 D1STPRST LL_SYSCFG_IsD1StopGenerateReset
1665 * @retval State of bit (1 or 0).
1666 */
1667 __STATIC_INLINE uint32_t LL_SYSCFG_IsD1StopGenerateReset(void)
1668 {
1669 return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D1STPRST) == 0U) ? 1UL : 0UL);
1670 }
1671
1672 #if defined (DUAL_CORE)
1673 /**
1674 * @brief Indicates if a reset is generated when D2 domain enters DStandby mode
1675 * @rmtoll UR14 D2SBRST LL_SYSCFG_IsD2StandbyGenerateReset
1676 * @retval State of bit (1 or 0).
1677 */
1678 __STATIC_INLINE uint32_t LL_SYSCFG_IsD2StandbyGenerateReset(void)
1679 {
1680 return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D2SBRST) == 0U) ? 1UL : 0UL);
1681 }
1682
1683 /**
1684 * @brief Indicates if a reset is generated when D2 domain enters DStop mode
1685 * @rmtoll UR15 D2STPRST LL_SYSCFG_IsD2StopGenerateReset
1686 * @retval State of bit (1 or 0).
1687 */
1688 __STATIC_INLINE uint32_t LL_SYSCFG_IsD2StopGenerateReset(void)
1689 {
1690 return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_D2STPRST) == 0U) ? 1UL : 0UL);
1691 }
1692 #endif /* DUAL_CORE */
1693
1694 /**
1695 * @brief Indicates if the independent watchdog is frozen in Standby mode
1696 * @rmtoll UR15 FZIWDGSTB LL_SYSCFG_IsIWDGFrozenInStandbyMode
1697 * @retval State of bit (1 or 0).
1698 */
1699 __STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStandbyMode(void)
1700 {
1701 return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_FZIWDGSTB) == 0U) ? 1UL : 0UL);
1702 }
1703
1704 /**
1705 * @brief Indicates if the independent watchdog is frozen in Stop mode
1706 * @rmtoll UR16 FZIWDGSTP LL_SYSCFG_IsIWDGFrozenInStopMode
1707 * @retval State of bit (1 or 0).
1708 */
1709 __STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStopMode(void)
1710 {
1711 return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_FZIWDGSTP) == 0U) ? 1UL : 0UL);
1712 }
1713
1714 /**
1715 * @brief Indicates if the device private key is programmed
1716 * @rmtoll UR16 PKP LL_SYSCFG_IsPrivateKeyProgrammed
1717 * @retval State of bit (1 or 0).
1718 */
1719 __STATIC_INLINE uint32_t LL_SYSCFG_IsPrivateKeyProgrammed(void)
1720 {
1721 return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_PKP) == SYSCFG_UR16_PKP) ? 1UL : 0UL);
1722 }
1723
1724 /**
1725 * @brief Indicates if the Product is working on the full voltage range or not
1726 * @rmtoll UR17 IOHSLV LL_SYSCFG_IsActiveFlag_IOHSLV
1727 * @note When the IOHSLV option bit is set the Product is working below 2.7 V.
1728 * When the IOHSLV option bit is reset the Product is working on the
1729 * full voltage range.
1730 * @retval State of bit (1 or 0).
1731 */
1732 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_IOHSLV(void)
1733 {
1734 return ((READ_BIT(SYSCFG->UR17, SYSCFG_UR17_IOHSLV) == SYSCFG_UR17_IOHSLV) ? 1UL : 0UL);
1735 }
1736
1737 #ifdef SYSCFG_UR17_TCM_AXI_CFG
1738 /**
1739 * @brief Get the size of ITCM-RAM and AXI-SRAM
1740 * @rmtoll UR17 TCM_AXI_CFG LL_SYSCFG_Get_ITCM_AXI_RAM_Size
1741 * @retval Returned value can be one of the following values:
1742 * @arg @ref LL_SYSCFG_ITCM_AXI_64KB_320KB
1743 * @arg @ref LL_SYSCFG_ITCM_AXI_128KB_256KB
1744 * @arg @ref LL_SYSCFG_ITCM_AXI_192KB_192KB
1745 * @arg @ref LL_SYSCFG_ITCM_AXI_256KB_128KB
1746 */
1747 __STATIC_INLINE uint32_t LL_SYSCFG_Get_ITCM_AXI_RAM_Size(void)
1748 {
1749 return (uint32_t)(READ_BIT(SYSCFG->UR17, SYSCFG_UR17_TCM_AXI_CFG));
1750 }
1751 #endif /*SYSCFG_UR17_TCM_AXI_CFG*/
1752
1753 #ifdef SYSCFG_UR18_CPU_FREQ_BOOST
1754 /**
1755 * @brief Indicates if the CPU maximum frequency boost is enabled
1756 * @rmtoll UR18 CPU_FREQ_BOOST LL_SYSCFG_IsCpuFreqBoostEnabled
1757 * @retval State of bit (1 or 0).
1758 */
1759 __STATIC_INLINE uint32_t LL_SYSCFG_IsCpuFreqBoostEnabled(void)
1760 {
1761 return ((READ_BIT(SYSCFG->UR18, SYSCFG_UR18_CPU_FREQ_BOOST) == SYSCFG_UR18_CPU_FREQ_BOOST) ? 1UL : 0UL);
1762 }
1763 #endif /*SYSCFG_UR18_CPU_FREQ_BOOST*/
1764
1765 #endif /*SYSCFG_UR0_RDP*/
1766
1767 /**
1768 * @}
1769 */
1770
1771 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
1772 * @{
1773 */
1774
1775 /**
1776 * @brief Return the device identifier
1777 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
1778 * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
1779 */
1780 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
1781 {
1782 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
1783 }
1784
1785 /**
1786 * @brief Return the device revision identifier
1787 * @note This field indicates the revision of the device.
1788 For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001
1789 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
1790 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
1791 */
1792 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
1793 {
1794 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
1795 }
1796
1797 /**
1798 * @brief Enable D1 Domain/CDomain debug during SLEEP mode
1799 * @rmtoll DBGMCU_CR DBGSLEEP_D1/DBGSLEEP_CD LL_DBGMCU_EnableD1DebugInSleepMode
1800 * @retval None
1801 */
1802 __STATIC_INLINE void LL_DBGMCU_EnableD1DebugInSleepMode(void)
1803 {
1804 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
1805 }
1806
1807 /**
1808 * @brief Disable D1 Domain/CDomain debug during SLEEP mode
1809 * @rmtoll DBGMCU_CR DBGSLEEP_D1/DBGSLEEP_CD LL_DBGMCU_DisableD1DebugInSleepMode
1810 * @retval None
1811 */
1812 __STATIC_INLINE void LL_DBGMCU_DisableD1DebugInSleepMode(void)
1813 {
1814 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
1815 }
1816
1817 /**
1818 * @brief Enable D1 Domain/CDomain debug during STOP mode
1819 * @rmtoll DBGMCU_CR DBGSTOP_D1/DBGSLEEP_CD LL_DBGMCU_EnableD1DebugInStopMode
1820 * @retval None
1821 */
1822 __STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStopMode(void)
1823 {
1824 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
1825 }
1826
1827 /**
1828 * @brief Disable D1 Domain/CDomain debug during STOP mode
1829 * @rmtoll DBGMCU_CR DBGSTOP_D1/DBGSLEEP_CD LL_DBGMCU_DisableD1DebugInStopMode
1830 * @retval None
1831 */
1832 __STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStopMode(void)
1833 {
1834 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
1835 }
1836
1837 /**
1838 * @brief Enable D1 Domain/CDomain debug during STANDBY mode
1839 * @rmtoll DBGMCU_CR DBGSTBY_D1/DBGSLEEP_CD LL_DBGMCU_EnableD1DebugInStandbyMode
1840 * @retval None
1841 */
1842 __STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStandbyMode(void)
1843 {
1844 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
1845 }
1846
1847 /**
1848 * @brief Disable D1 Domain/CDomain debug during STANDBY mode
1849 * @rmtoll DBGMCU_CR DBGSTBY_D1/DBGSLEEP_CD LL_DBGMCU_DisableD1DebugInStandbyMode
1850 * @retval None
1851 */
1852 __STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStandbyMode(void)
1853 {
1854 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
1855 }
1856
1857 #if defined (DUAL_CORE)
1858 /**
1859 * @brief Enable D2 Domain debug during SLEEP mode
1860 * @rmtoll DBGMCU_CR DBGSLEEP_D2 LL_DBGMCU_EnableD2DebugInSleepMode
1861 * @retval None
1862 */
1863 __STATIC_INLINE void LL_DBGMCU_EnableD2DebugInSleepMode(void)
1864 {
1865 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
1866 }
1867
1868 /**
1869 * @brief Disable D2 Domain debug during SLEEP mode
1870 * @rmtoll DBGMCU_CR DBGSLEEP_D2 LL_DBGMCU_DisableD2DebugInSleepMode
1871 * @retval None
1872 */
1873 __STATIC_INLINE void LL_DBGMCU_DisableD2DebugInSleepMode(void)
1874 {
1875 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
1876 }
1877
1878 /**
1879 * @brief Enable D2 Domain debug during STOP mode
1880 * @rmtoll DBGMCU_CR DBGSTOP_D2 LL_DBGMCU_EnableD2DebugInStopMode
1881 * @retval None
1882 */
1883 __STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStopMode(void)
1884 {
1885 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
1886 }
1887
1888 /**
1889 * @brief Disable D2 Domain debug during STOP mode
1890 * @rmtoll DBGMCU_CR DBGSTOP_D2 LL_DBGMCU_DisableD2DebugInStopMode
1891 * @retval None
1892 */
1893 __STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStopMode(void)
1894 {
1895 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
1896 }
1897
1898 /**
1899 * @brief Enable D2 Domain debug during STANDBY mode
1900 * @rmtoll DBGMCU_CR DBGSTBY_D2 LL_DBGMCU_EnableD2DebugInStandbyMode
1901 * @retval None
1902 */
1903 __STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStandbyMode(void)
1904 {
1905 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
1906 }
1907
1908 /**
1909 * @brief Disable D2 Domain debug during STANDBY mode
1910 * @rmtoll DBGMCU_CR DBGSTBY_D2 LL_DBGMCU_DisableD2DebugInStandbyMode
1911 * @retval None
1912 */
1913 __STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStandbyMode(void)
1914 {
1915 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
1916 }
1917 #endif /* DUAL_CORE */
1918
1919
1920 /**
1921 * @brief Enable D3 Domain/SRDomain debug during STOP mode
1922 * @rmtoll DBGMCU_CR DBGSTOP_D3/DBGSTOP_SRD LL_DBGMCU_EnableD3DebugInStopMode
1923 * @retval None
1924 */
1925 __STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStopMode(void)
1926 {
1927 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
1928 }
1929
1930 /**
1931 * @brief Disable D3 Domain/SRDomain debug during STOP mode
1932 * @rmtoll DBGMCU_CR DBGSTOP_D3/DBGSTOP_SRD LL_DBGMCU_DisableD3DebugInStopMode
1933 * @retval None
1934 */
1935 __STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStopMode(void)
1936 {
1937 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
1938 }
1939
1940 /**
1941 * @brief Enable D3 Domain/SRDomain debug during STANDBY mode
1942 * @rmtoll DBGMCU_CR DBGSTBY_D3/DBGSTBY_SRD LL_DBGMCU_EnableD3DebugInStandbyMode
1943 * @retval None
1944 */
1945 __STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStandbyMode(void)
1946 {
1947 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
1948 }
1949
1950 /**
1951 * @brief Disable D3 Domain/SRDomain debug during STANDBY mode
1952 * @rmtoll DBGMCU_CR DBGSTBY_D3/DBGSTBY_SRD LL_DBGMCU_DisableD3DebugInStandbyMode
1953 * @retval None
1954 */
1955 __STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStandbyMode(void)
1956 {
1957 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
1958 }
1959
1960 /**
1961 * @brief Enable the trace port clock
1962 * @rmtoll DBGMCU_CR TRACECKEN LL_DBGMCU_EnableTracePortClock
1963 * @retval None
1964 */
1965 __STATIC_INLINE void LL_DBGMCU_EnableTracePortClock(void)
1966 {
1967 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN);
1968 }
1969
1970 /**
1971 * @brief Disable the trace port clock
1972 * @rmtoll DBGMCU_CR TRACECKEN LL_DBGMCU_DisableTracePortClock
1973 * @retval None
1974 */
1975 __STATIC_INLINE void LL_DBGMCU_DisableTracePortClock(void)
1976 {
1977 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN);
1978 }
1979
1980 /**
1981 * @brief Enable the Domain1/CDomain debug clock enable
1982 * @rmtoll DBGMCU_CR CKD1EN/CKCDEN LL_DBGMCU_EnableD1DebugClock
1983 * @retval None
1984 */
1985 __STATIC_INLINE void LL_DBGMCU_EnableD1DebugClock(void)
1986 {
1987 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN);
1988 }
1989
1990 /**
1991 * @brief Disable the Domain1/CDomain debug clock enable
1992 * @rmtoll DBGMCU_CR CKD1EN/CKCDEN LL_DBGMCU_DisableD1DebugClock
1993 * @retval None
1994 */
1995 __STATIC_INLINE void LL_DBGMCU_DisableD1DebugClock(void)
1996 {
1997 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN);
1998 }
1999
2000 /**
2001 * @brief Enable the Domain3/SRDomain debug clock enable
2002 * @rmtoll DBGMCU_CR CKD3EN/CKSRDEN LL_DBGMCU_EnableD3DebugClock
2003 * @retval None
2004 */
2005 __STATIC_INLINE void LL_DBGMCU_EnableD3DebugClock(void)
2006 {
2007 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN);
2008 }
2009
2010 /**
2011 * @brief Disable the Domain3/SRDomain debug clock enable
2012 * @rmtoll DBGMCU_CR CKD3EN/CKSRDEN LL_DBGMCU_DisableD3DebugClock
2013 * @retval None
2014 */
2015 __STATIC_INLINE void LL_DBGMCU_DisableD3DebugClock(void)
2016 {
2017 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN);
2018 }
2019
2020 #define LL_DBGMCU_TRGIO_INPUT_DIRECTION 0U
2021 #define LL_DBGMCU_TRGIO_OUTPUT_DIRECTION DBGMCU_CR_DBG_TRGOEN
2022 /**
2023 * @brief Set the direction of the bi-directional trigger pin TRGIO
2024 * @rmtoll DBGMCU_CR TRGOEN LL_DBGMCU_SetExternalTriggerPinDirection\n
2025 * @param PinDirection This parameter can be one of the following values:
2026 * @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION
2027 * @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION
2028 * @retval None
2029 */
2030 __STATIC_INLINE void LL_DBGMCU_SetExternalTriggerPinDirection(uint32_t PinDirection)
2031 {
2032 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN, PinDirection);
2033 }
2034
2035 /**
2036 * @brief Get the direction of the bi-directional trigger pin TRGIO
2037 * @rmtoll DBGMCU_CR TRGOEN LL_DBGMCU_GetExternalTriggerPinDirection\n
2038 * @retval Returned value can be one of the following values:
2039 * @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION
2040 * @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION
2041 */
2042 __STATIC_INLINE uint32_t LL_DBGMCU_GetExternalTriggerPinDirection(void)
2043 {
2044 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN));
2045 }
2046
2047 /**
2048 * @brief Freeze APB1 group1 peripherals
2049 * @rmtoll DBGMCU_APB1LFZ1 TIM2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2050 * DBGMCU_APB1LFZ1 TIM3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2051 * DBGMCU_APB1LFZ1 TIM4 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2052 * DBGMCU_APB1LFZ1 TIM5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2053 * DBGMCU_APB1LFZ1 TIM6 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2054 * DBGMCU_APB1LFZ1 TIM7 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2055 * DBGMCU_APB1LFZ1 TIM12 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2056 * DBGMCU_APB1LFZ1 TIM13 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2057 * DBGMCU_APB1LFZ1 TIM14 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2058 * DBGMCU_APB1LFZ1 LPTIM1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2059 * DBGMCU_APB1LFZ1 I2C1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2060 * DBGMCU_APB1LFZ1 I2C2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2061 * DBGMCU_APB1LFZ1 I2C3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2062 * DBGMCU_APB1LFZ1 I2C5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n (*)
2063 * @param Periphs This parameter can be a combination of the following values:
2064 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
2065 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
2066 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
2067 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
2068 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
2069 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
2070 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
2071 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
2072 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
2073 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
2074 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
2075 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
2076 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
2077 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C5_STOP (*)
2078 *
2079 * (*) value not defined in all devices
2080 * @retval None
2081 */
2082 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
2083 {
2084 SET_BIT(DBGMCU->APB1LFZ1, Periphs);
2085 }
2086
2087 /**
2088 * @brief Unfreeze APB1 peripherals (group1 peripherals)
2089 * @rmtoll DBGMCU_APB1LFZ1 TIM2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2090 * DBGMCU_APB1LFZ1 TIM3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2091 * DBGMCU_APB1LFZ1 TIM4 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2092 * DBGMCU_APB1LFZ1 TIM5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2093 * DBGMCU_APB1LFZ1 TIM6 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2094 * DBGMCU_APB1LFZ1 TIM7 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2095 * DBGMCU_APB1LFZ1 TIM12 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2096 * DBGMCU_APB1LFZ1 TIM13 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2097 * DBGMCU_APB1LFZ1 TIM14 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2098 * DBGMCU_APB1LFZ1 LPTIM1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2099 * DBGMCU_APB1LFZ1 I2C1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2100 * DBGMCU_APB1LFZ1 I2C2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2101 * DBGMCU_APB1LFZ1 I2C3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2102 * DBGMCU_APB1LFZ1 I2C5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2103 * @param Periphs This parameter can be a combination of the following values:
2104 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
2105 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
2106 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
2107 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
2108 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
2109 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
2110 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
2111 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
2112 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
2113 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
2114 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
2115 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
2116 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
2117 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C5_STOP (*)
2118 *
2119 * (*) value not defined in all devices
2120 * @retval None
2121 */
2122 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
2123 {
2124 CLEAR_BIT(DBGMCU->APB1LFZ1, Periphs);
2125 }
2126
2127 #ifdef DBGMCU_APB1HFZ1_DBG_FDCAN
2128 /**
2129 * @brief Freeze APB1 group2 peripherals
2130 * @rmtoll DBGMCU_APB1HFZ1 FDCAN LL_DBGMCU_APB1_GRP2_FreezePeriph\n
2131 * @param Periphs This parameter can be a combination of the following values:
2132 * @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP
2133 * @retval None
2134 */
2135 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
2136 {
2137 SET_BIT(DBGMCU->APB1HFZ1, Periphs);
2138 }
2139
2140 /**
2141 * @brief Unfreeze APB1 group2 peripherals
2142 * @rmtoll DBGMCU_APB1HFZ1 FDCAN LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
2143 * @param Periphs This parameter can be a combination of the following values:
2144 * @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP
2145 * @retval None
2146 */
2147 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
2148 {
2149 CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs);
2150 }
2151 #endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/
2152
2153 #if defined(TIM23) || defined(TIM24)
2154 /**
2155 * @brief Freeze APB1 group2 peripherals
2156 * @rmtoll DBGMCU_APB1HFZ1 TIM23 LL_DBGMCU_APB1_GRP2_FreezePeriph\n
2157 * DBGMCU_APB1HFZ1 TIM24 LL_DBGMCU_APB1_GRP2_FreezePeriph\n
2158 * @param Periphs This parameter can be a combination of the following values:
2159 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM23_STOP
2160 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM24_STOP
2161 * @retval None
2162 */
2163 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
2164 {
2165 SET_BIT(DBGMCU->APB1HFZ1, Periphs);
2166 }
2167
2168 /**
2169 * @brief Unfreeze APB1 group2 peripherals
2170 * @rmtoll DBGMCU_APB1HFZ1 TIM23 LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
2171 DBGMCU_APB1HFZ1 TIM24 LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
2172 * @param Periphs This parameter can be a combination of the following values:
2173 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM23_STOP
2174 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM24_STOP
2175 * @retval None
2176 */
2177 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
2178 {
2179 CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs);
2180 }
2181 #endif /* TIM23 || TIM24 */
2182
2183 /**
2184 * @brief Freeze APB2 peripherals
2185 * @rmtoll DBGMCU_APB2FZ1 TIM1 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2186 * DBGMCU_APB2FZ1 TIM8 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2187 * DBGMCU_APB2FZ1 TIM15 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2188 * DBGMCU_APB2FZ1 TIM16 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2189 * DBGMCU_APB2FZ1 TIM17 LL_DBGMCU_APB2_GRP1_FreezePeriph
2190 * DBGMCU_APB2FZ1 HRTIM LL_DBGMCU_APB2_GRP1_FreezePeriph
2191 * @param Periphs This parameter can be a combination of the following values:
2192 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
2193 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
2194 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
2195 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
2196 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
2197 * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP (*)
2198 *
2199 * (*) value not defined in all devices
2200 * @retval None
2201 */
2202 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
2203 {
2204 SET_BIT(DBGMCU->APB2FZ1, Periphs);
2205 }
2206
2207 /**
2208 * @brief Unfreeze APB2 peripherals
2209 * @rmtoll DBGMCU_APB2FZ1 TIM1 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2210 * DBGMCU_APB2FZ1 TIM8 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2211 * DBGMCU_APB2FZ1 TIM15 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2212 * DBGMCU_APB2FZ1 TIM16 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2213 * DBGMCU_APB2FZ1 TIM17 LL_DBGMCU_APB2_GRP1_FreezePeriph
2214 * DBGMCU_APB2FZ1 HRTIM LL_DBGMCU_APB2_GRP1_FreezePeriph
2215 * @param Periphs This parameter can be a combination of the following values:
2216 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
2217 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
2218 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
2219 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
2220 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
2221 * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP (*)
2222 *
2223 * (*) value not defined in all devices
2224 * @retval None
2225 */
2226 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
2227 {
2228 CLEAR_BIT(DBGMCU->APB2FZ1, Periphs);
2229 }
2230
2231 /**
2232 * @brief Freeze APB3 peripherals
2233 * @rmtoll DBGMCU_APB3FZ1 WWDG1 LL_DBGMCU_APB3_GRP1_FreezePeriph\n
2234 * @param Periphs This parameter can be a combination of the following values:
2235 * @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP
2236 * @retval None
2237 */
2238 __STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs)
2239 {
2240 SET_BIT(DBGMCU->APB3FZ1, Periphs);
2241 }
2242
2243 /**
2244 * @brief Unfreeze APB3 peripherals
2245 * @rmtoll DBGMCU_APB3FZ1 WWDG1 LL_DBGMCU_APB3_GRP1_UnFreezePeriph\n
2246 * @param Periphs This parameter can be a combination of the following values:
2247 * @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP
2248 * @retval None
2249 */
2250 __STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs)
2251 {
2252 CLEAR_BIT(DBGMCU->APB3FZ1, Periphs);
2253 }
2254
2255 /**
2256 * @brief Freeze APB4 peripherals
2257 * @rmtoll DBGMCU_APB4FZ1 I2C4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2258 * @rmtoll DBGMCU_APB4FZ1 LPTIM2 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2259 * @rmtoll DBGMCU_APB4FZ1 LPTIM3 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2260 * @rmtoll DBGMCU_APB4FZ1 LPTIM4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2261 * @rmtoll DBGMCU_APB4FZ1 LPTIM5 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2262 * @rmtoll DBGMCU_APB4FZ1 RTC LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2263 * @rmtoll DBGMCU_APB4FZ1 WDGLSD1 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2264 * @param Periphs This parameter can be a combination of the following values:
2265 * @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP
2266 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
2267 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
2268 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP (*)
2269 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP (*)
2270 * @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP
2271 * @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP
2272 *
2273 * (*) value not defined in all devices
2274 * @retval None
2275 */
2276 __STATIC_INLINE void LL_DBGMCU_APB4_GRP1_FreezePeriph(uint32_t Periphs)
2277 {
2278 SET_BIT(DBGMCU->APB4FZ1, Periphs);
2279 }
2280
2281 /**
2282 * @brief Unfreeze APB4 peripherals
2283 * @rmtoll DBGMCU_APB4FZ1 I2C4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2284 * @rmtoll DBGMCU_APB4FZ1 LPTIM2 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2285 * @rmtoll DBGMCU_APB4FZ1 LPTIM3 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2286 * @rmtoll DBGMCU_APB4FZ1 LPTIM4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2287 * @rmtoll DBGMCU_APB4FZ1 LPTIM5 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2288 * @rmtoll DBGMCU_APB4FZ1 RTC LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2289 * @rmtoll DBGMCU_APB4FZ1 WDGLSD1 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2290 * @param Periphs This parameter can be a combination of the following values:
2291 * @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP
2292 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
2293 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
2294 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP (*)
2295 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP (*)
2296 * @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP
2297 * @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP
2298 *
2299 * (*) value not defined in all devices
2300 * @retval None
2301 */
2302 __STATIC_INLINE void LL_DBGMCU_APB4_GRP1_UnFreezePeriph(uint32_t Periphs)
2303 {
2304 CLEAR_BIT(DBGMCU->APB4FZ1, Periphs);
2305 }
2306 /**
2307 * @}
2308 */
2309
2310 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
2311 * @{
2312 */
2313
2314 /**
2315 * @brief Set FLASH Latency
2316 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
2317 * @param Latency This parameter can be one of the following values:
2318 * @arg @ref LL_FLASH_LATENCY_0
2319 * @arg @ref LL_FLASH_LATENCY_1
2320 * @arg @ref LL_FLASH_LATENCY_2
2321 * @arg @ref LL_FLASH_LATENCY_3
2322 * @arg @ref LL_FLASH_LATENCY_4
2323 * @arg @ref LL_FLASH_LATENCY_5
2324 * @arg @ref LL_FLASH_LATENCY_6
2325 * @arg @ref LL_FLASH_LATENCY_7
2326 * @retval None
2327 */
2328 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
2329 {
2330 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
2331 }
2332
2333 /**
2334 * @brief Get FLASH Latency
2335 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
2336 * @retval Returned value can be one of the following values:
2337 * @arg @ref LL_FLASH_LATENCY_0
2338 * @arg @ref LL_FLASH_LATENCY_1
2339 * @arg @ref LL_FLASH_LATENCY_2
2340 * @arg @ref LL_FLASH_LATENCY_3
2341 * @arg @ref LL_FLASH_LATENCY_4
2342 * @arg @ref LL_FLASH_LATENCY_5
2343 * @arg @ref LL_FLASH_LATENCY_6
2344 * @arg @ref LL_FLASH_LATENCY_7
2345 */
2346 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
2347 {
2348 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
2349 }
2350
2351 /**
2352 * @}
2353 */
2354
2355 #if defined(DUAL_CORE)
2356 /** @defgroup SYSTEM_LL_EF_ART ART
2357 * @{
2358 */
2359
2360 /**
2361 * @brief Enable the Cortex-M4 ART cache.
2362 * @rmtoll ART_CTR EN LL_ART_Enable
2363 * @retval None
2364 */
2365 __STATIC_INLINE void LL_ART_Enable(void)
2366 {
2367 SET_BIT(ART->CTR, ART_CTR_EN);
2368 }
2369
2370 /**
2371 * @brief Disable the Cortex-M4 ART cache.
2372 * @rmtoll ART_CTR EN LL_ART_Disable
2373 * @retval None
2374 */
2375 __STATIC_INLINE void LL_ART_Disable(void)
2376 {
2377 CLEAR_BIT(ART->CTR, ART_CTR_EN);
2378 }
2379
2380 /**
2381 * @brief Check if the Cortex-M4 ART cache is enabled
2382 * @rmtoll ART_CTR EN LL_ART_IsEnabled
2383 * @retval State of bit (1 or 0).
2384 */
2385 __STATIC_INLINE uint32_t LL_ART_IsEnabled(void)
2386 {
2387 return ((READ_BIT(ART->CTR, ART_CTR_EN) == ART_CTR_EN) ? 1UL : 0UL);
2388 }
2389
2390 /**
2391 * @brief Set the Cortex-M4 ART cache Base Address.
2392 * @rmtoll ART_CTR PCACHEADDR LL_ART_SetBaseAddress
2393 * @param BaseAddress Specifies the Base address of 1 Mbyte address page (cacheable page)
2394 from which the ART accelerator loads code to the cache.
2395 * @retval None
2396 */
2397 __STATIC_INLINE void LL_ART_SetBaseAddress(uint32_t BaseAddress)
2398 {
2399 MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((BaseAddress) >> 12U) & 0x000FFF00UL));
2400 }
2401
2402 /**
2403 * @brief Get the Cortex-M4 ART cache Base Address.
2404 * @rmtoll ART_CTR PCACHEADDR LL_ART_GetBaseAddress
2405 * @retval the Base address of 1 Mbyte address page (cacheable page)
2406 from which the ART accelerator loads code to the cache
2407 */
2408 __STATIC_INLINE uint32_t LL_ART_GetBaseAddress(void)
2409 {
2410 return (uint32_t)(READ_BIT(ART->CTR, ART_CTR_PCACHEADDR) << 12U);
2411 }
2412 #endif /* DUAL_CORE */
2413
2414 /**
2415 * @}
2416 */
2417
2418 /**
2419 * @}
2420 */
2421
2422 /**
2423 * @}
2424 */
2425
2426 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
2427
2428 /**
2429 * @}
2430 */
2431
2432 #ifdef __cplusplus
2433 }
2434 #endif
2435
2436 #endif /* __STM32H7xx_LL_SYSTEM_H */
2437
2438 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/