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Merge pull request #11270 from haslinghuis/rename_attr
[betaflight.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_ll_tim.h
blob3bbdaa191209d48bd99f7a5f004ed7d7724589b5
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32H7xx_LL_TIM_H
22 #define __STM32H7xx_LL_TIM_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx.h"
30
31 /** @addtogroup STM32H7xx_LL_Driver
32 * @{
33 */
34
35 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM23) || defined (TIM24)
36
37 /** @defgroup TIM_LL TIM
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
44 * @{
45 */
46 static const uint8_t OFFSET_TAB_CCMRx[] =
47 {
48 0x00U, /* 0: TIMx_CH1 */
49 0x00U, /* 1: TIMx_CH1N */
50 0x00U, /* 2: TIMx_CH2 */
51 0x00U, /* 3: TIMx_CH2N */
52 0x04U, /* 4: TIMx_CH3 */
53 0x04U, /* 5: TIMx_CH3N */
54 0x04U, /* 6: TIMx_CH4 */
55 0x3CU, /* 7: TIMx_CH5 */
56 0x3CU /* 8: TIMx_CH6 */
57 };
58
59 static const uint8_t SHIFT_TAB_OCxx[] =
60 {
61 0U, /* 0: OC1M, OC1FE, OC1PE */
62 0U, /* 1: - NA */
63 8U, /* 2: OC2M, OC2FE, OC2PE */
64 0U, /* 3: - NA */
65 0U, /* 4: OC3M, OC3FE, OC3PE */
66 0U, /* 5: - NA */
67 8U, /* 6: OC4M, OC4FE, OC4PE */
68 0U, /* 7: OC5M, OC5FE, OC5PE */
69 8U /* 8: OC6M, OC6FE, OC6PE */
70 };
71
72 static const uint8_t SHIFT_TAB_ICxx[] =
73 {
74 0U, /* 0: CC1S, IC1PSC, IC1F */
75 0U, /* 1: - NA */
76 8U, /* 2: CC2S, IC2PSC, IC2F */
77 0U, /* 3: - NA */
78 0U, /* 4: CC3S, IC3PSC, IC3F */
79 0U, /* 5: - NA */
80 8U, /* 6: CC4S, IC4PSC, IC4F */
81 0U, /* 7: - NA */
82 0U /* 8: - NA */
83 };
84
85 static const uint8_t SHIFT_TAB_CCxP[] =
86 {
87 0U, /* 0: CC1P */
88 2U, /* 1: CC1NP */
89 4U, /* 2: CC2P */
90 6U, /* 3: CC2NP */
91 8U, /* 4: CC3P */
92 10U, /* 5: CC3NP */
93 12U, /* 6: CC4P */
94 16U, /* 7: CC5P */
95 20U /* 8: CC6P */
96 };
97
98 static const uint8_t SHIFT_TAB_OISx[] =
99 {
100 0U, /* 0: OIS1 */
101 1U, /* 1: OIS1N */
102 2U, /* 2: OIS2 */
103 3U, /* 3: OIS2N */
104 4U, /* 4: OIS3 */
105 5U, /* 5: OIS3N */
106 6U, /* 6: OIS4 */
107 8U, /* 7: OIS5 */
108 10U /* 8: OIS6 */
109 };
110 /**
111 * @}
112 */
113
114 /* Private constants ---------------------------------------------------------*/
115 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
116 * @{
117 */
118
119 #if defined(TIM_BREAK_INPUT_SUPPORT)
120 /* Defines used for the bit position in the register and perform offsets */
121 #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
122
123 /* Generic bit definitions for TIMx_AF1 register */
124 #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */
125 #define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */
126 #endif /* TIM_BREAK_INPUT_SUPPORT */
127
128
129 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
130 #define DT_DELAY_1 ((uint8_t)0x7F)
131 #define DT_DELAY_2 ((uint8_t)0x3F)
132 #define DT_DELAY_3 ((uint8_t)0x1F)
133 #define DT_DELAY_4 ((uint8_t)0x1F)
134
135 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
136 #define DT_RANGE_1 ((uint8_t)0x00)
137 #define DT_RANGE_2 ((uint8_t)0x80)
138 #define DT_RANGE_3 ((uint8_t)0xC0)
139 #define DT_RANGE_4 ((uint8_t)0xE0)
140
141
142 /**
143 * @}
144 */
145
146 /* Private macros ------------------------------------------------------------*/
147 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
148 * @{
149 */
150 /** @brief Convert channel id into channel index.
151 * @param __CHANNEL__ This parameter can be one of the following values:
152 * @arg @ref LL_TIM_CHANNEL_CH1
153 * @arg @ref LL_TIM_CHANNEL_CH1N
154 * @arg @ref LL_TIM_CHANNEL_CH2
155 * @arg @ref LL_TIM_CHANNEL_CH2N
156 * @arg @ref LL_TIM_CHANNEL_CH3
157 * @arg @ref LL_TIM_CHANNEL_CH3N
158 * @arg @ref LL_TIM_CHANNEL_CH4
159 * @arg @ref LL_TIM_CHANNEL_CH5
160 * @arg @ref LL_TIM_CHANNEL_CH6
161 * @retval none
162 */
163 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
164 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
165 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
166 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
167 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
168 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
169 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
170 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
171 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
172
173 /** @brief Calculate the deadtime sampling period(in ps).
174 * @param __TIMCLK__ timer input clock frequency (in Hz).
175 * @param __CKD__ This parameter can be one of the following values:
176 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
177 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
178 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
179 * @retval none
180 */
181 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
182 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
183 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
184 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
185 /**
186 * @}
187 */
188
189
190 /* Exported types ------------------------------------------------------------*/
191 #if defined(USE_FULL_LL_DRIVER)
192 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
193 * @{
194 */
195
196 /**
197 * @brief TIM Time Base configuration structure definition.
198 */
199 typedef struct
200 {
201 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
202 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
203
204 This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
205
206 uint32_t CounterMode; /*!< Specifies the counter mode.
207 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
208
209 This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
210
211 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
212 Auto-Reload Register at the next update event.
213 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
214 Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
215
216 This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
217
218 uint32_t ClockDivision; /*!< Specifies the clock division.
219 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
220
221 This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
222
223 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
224 reaches zero, an update event is generated and counting restarts
225 from the RCR value (N).
226 This means in PWM mode that (N+1) corresponds to:
227 - the number of PWM periods in edge-aligned mode
228 - the number of half PWM period in center-aligned mode
229 GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
230 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
231
232 This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
233 } LL_TIM_InitTypeDef;
234
235 /**
236 * @brief TIM Output Compare configuration structure definition.
237 */
238 typedef struct
239 {
240 uint32_t OCMode; /*!< Specifies the output mode.
241 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
242
243 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
244
245 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
246 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
247
248 This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
249
250 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
251 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
252
253 This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
254
255 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
256 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
257
258 This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
259
260 uint32_t OCPolarity; /*!< Specifies the output polarity.
261 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
262
263 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
264
265 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
266 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
267
268 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
269
270
271 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
272 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
273
274 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
275
276 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
277 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
278
279 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
280 } LL_TIM_OC_InitTypeDef;
281
282 /**
283 * @brief TIM Input Capture configuration structure definition.
284 */
285
286 typedef struct
287 {
288
289 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
290 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
291
292 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
293
294 uint32_t ICActiveInput; /*!< Specifies the input.
295 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
296
297 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
298
299 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
300 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
301
302 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
303
304 uint32_t ICFilter; /*!< Specifies the input capture filter.
305 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
306
307 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
308 } LL_TIM_IC_InitTypeDef;
309
310
311 /**
312 * @brief TIM Encoder interface configuration structure definition.
313 */
314 typedef struct
315 {
316 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
317 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
318
319 This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
320
321 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
322 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
323
324 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
325
326 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
327 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
328
329 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
330
331 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
332 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
333
334 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
335
336 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
337 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
338
339 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
340
341 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
342 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
343
344 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
345
346 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
347 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
348
349 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
350
351 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
352 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
353
354 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
355
356 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
357 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
358
359 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
360
361 } LL_TIM_ENCODER_InitTypeDef;
362
363 /**
364 * @brief TIM Hall sensor interface configuration structure definition.
365 */
366 typedef struct
367 {
368
369 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
370 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
371
372 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
373
374 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
375 Prescaler must be set to get a maximum counter period longer than the
376 time interval between 2 consecutive changes on the Hall inputs.
377 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
378
379 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
380
381 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
382 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
383
384 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
385
386 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
387 A positive pulse (TRGO event) is generated with a programmable delay every time
388 a change occurs on the Hall inputs.
389 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
390
391 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
392 } LL_TIM_HALLSENSOR_InitTypeDef;
393
394 /**
395 * @brief BDTR (Break and Dead Time) structure definition
396 */
397 typedef struct
398 {
399 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
400 This parameter can be a value of @ref TIM_LL_EC_OSSR
401
402 This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
403
404 @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
405
406 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
407 This parameter can be a value of @ref TIM_LL_EC_OSSI
408
409 This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
410
411 @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
412
413 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
414 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
415
416 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
417 has been written, their content is frozen until the next reset.*/
418
419 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
420 switching-on of the outputs.
421 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
422
423 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
424
425 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
426
427 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
428 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
429
430 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
431
432 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
433
434 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
435 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
436
437 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
438
439 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
440
441 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
442 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
443
444 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
445
446 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
447
448 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
449 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
450
451 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
452
453 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
454
455 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
456 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
457
458 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
459
460 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
461
462 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
463 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
464
465 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
466
467 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
468
469 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
470 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
471
472 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
473
474 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
475 } LL_TIM_BDTR_InitTypeDef;
476
477 /**
478 * @}
479 */
480 #endif /* USE_FULL_LL_DRIVER */
481
482 /* Exported constants --------------------------------------------------------*/
483 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
484 * @{
485 */
486
487 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
488 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
489 * @{
490 */
491 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
492 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
493 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
494 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
495 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
496 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
497 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
498 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
499 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
500 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
501 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
502 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
503 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
504 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
505 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
506 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
507 /**
508 * @}
509 */
510
511 #if defined(USE_FULL_LL_DRIVER)
512 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
513 * @{
514 */
515 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
516 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
517 /**
518 * @}
519 */
520
521 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
522 * @{
523 */
524 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
525 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
526 /**
527 * @}
528 */
529
530 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
531 * @{
532 */
533 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
534 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
535 /**
536 * @}
537 */
538 #endif /* USE_FULL_LL_DRIVER */
539
540 /** @defgroup TIM_LL_EC_IT IT Defines
541 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
542 * @{
543 */
544 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
545 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
546 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
547 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
548 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
549 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
550 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
551 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
552 /**
553 * @}
554 */
555
556 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
557 * @{
558 */
559 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
560 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
561 /**
562 * @}
563 */
564
565 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
566 * @{
567 */
568 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */
569 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */
570 /**
571 * @}
572 */
573
574 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
575 * @{
576 */
577 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
578 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
579 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
580 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
581 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
582 /**
583 * @}
584 */
585
586 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
587 * @{
588 */
589 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
590 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
591 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
592 /**
593 * @}
594 */
595
596 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
597 * @{
598 */
599 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
600 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
601 /**
602 * @}
603 */
604
605 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
606 * @{
607 */
608 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
609 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
610 /**
611 * @}
612 */
613
614 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
615 * @{
616 */
617 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
618 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
619 /**
620 * @}
621 */
622
623 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
624 * @{
625 */
626 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
627 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
628 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
629 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
630 /**
631 * @}
632 */
633
634 /** @defgroup TIM_LL_EC_CHANNEL Channel
635 * @{
636 */
637 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
638 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
639 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
640 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
641 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
642 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
643 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
644 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
645 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
646 /**
647 * @}
648 */
649
650 #if defined(USE_FULL_LL_DRIVER)
651 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
652 * @{
653 */
654 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
655 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
656 /**
657 * @}
658 */
659 #endif /* USE_FULL_LL_DRIVER */
660
661 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
662 * @{
663 */
664 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
665 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
666 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
667 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
668 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
669 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
670 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
671 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
672 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
673 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
674 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
675 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
676 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
677 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
678 /**
679 * @}
680 */
681
682 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
683 * @{
684 */
685 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
686 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
687 /**
688 * @}
689 */
690
691 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
692 * @{
693 */
694 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
695 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
696 /**
697 * @}
698 */
699
700 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
701 * @{
702 */
703 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
704 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
705 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
706 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
707 /**
708 * @}
709 */
710
711 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
712 * @{
713 */
714 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
715 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
716 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
717 /**
718 * @}
719 */
720
721 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
722 * @{
723 */
724 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
725 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
726 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
727 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
728 /**
729 * @}
730 */
731
732 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
733 * @{
734 */
735 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
736 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
737 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
738 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
739 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
740 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
741 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
742 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
743 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
744 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
745 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
746 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
747 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
748 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
749 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
750 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
751 /**
752 * @}
753 */
754
755 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
756 * @{
757 */
758 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
759 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
760 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
761 /**
762 * @}
763 */
764
765 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
766 * @{
767 */
768 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
769 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
770 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
771 /**
772 * @}
773 */
774
775 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
776 * @{
777 */
778 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
779 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
780 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
781 /**
782 * @}
783 */
784
785 /** @defgroup TIM_LL_EC_TRGO Trigger Output
786 * @{
787 */
788 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
789 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
790 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
791 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
792 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
793 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
794 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
795 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
796 /**
797 * @}
798 */
799
800 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
801 * @{
802 */
803 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
804 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
805 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
806 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
807 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
808 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
809 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
810 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
811 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
812 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
813 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
814 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
815 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
816 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
817 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
818 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
819 /**
820 * @}
821 */
822
823 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
824 * @{
825 */
826 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
827 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
828 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
829 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
830 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
831 /**
832 * @}
833 */
834
835 /** @defgroup TIM_LL_EC_TS Trigger Selection
836 * @{
837 */
838 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
839 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
840 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
841 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
842 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
843 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
844 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
845 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
846 #define LL_TIM_TS_ITR4 (TIM_SMCR_TS_3) /*!< Internal Trigger 4 (ITR4) is used as trigger input */
847 #define LL_TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) is used as trigger input */
848 #define LL_TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) is used as trigger input */
849 #define LL_TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) is used as trigger input */
850 #define LL_TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) is used as trigger input */
851 #define LL_TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 9 (ITR9) is used as trigger input */
852 #define LL_TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 10 (ITR10) is used as trigger input */
853 #define LL_TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) is used as trigger input */
854 #define LL_TIM_TS_ITR12 (TIM_SMCR_TS_4) /*!< Internal Trigger 12 (ITR12) is used as trigger input */
855 #define LL_TIM_TS_ITR13 (TIM_SMCR_TS_0 | TIM_SMCR_TS_4) /*!< Internal Trigger 13 (ITR13) is used as trigger input */
856 /**
857 * @}
858 */
859
860 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
861 * @{
862 */
863 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
864 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
865 /**
866 * @}
867 */
868
869 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
870 * @{
871 */
872 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
873 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
874 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
875 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
876 /**
877 * @}
878 */
879
880 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
881 * @{
882 */
883 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
884 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
885 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
886 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
887 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
888 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
889 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
890 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
891 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
892 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
893 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
894 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
895 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
896 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
897 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
898 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
899 /**
900 * @}
901 */
902
903 #define LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */
904 #define LL_TIM_TIM1_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 OUT */
905 #define LL_TIM_TIM1_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 OUT */
906 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */
907 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) /* !< TIM1_ETR is connected to ADC1 AWD2 */
908 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */
909 #define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to ADC3 AWD1 */
910 #define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */
911 #define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /* !< TIM1_ETR is connected to ADC3 AWD3 */
912
913 #define LL_TIM_TIM8_ETRSOURCE_GPIO 0x00000000U /* !< TIM8_ETR is connected to GPIO */
914 #define LL_TIM_TIM8_ETRSOURCE_COMP1 TIM8_AF1_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 OUT */
915 #define LL_TIM_TIM8_ETRSOURCE_COMP2 TIM8_AF1_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 OUT */
916 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD1 */
917 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 (TIM8_AF1_ETRSEL_2) /* !< TIM8_ETR is connected to ADC2 AWD2 */
918 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */
919 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /* !< TIM8_ETR is connected to ADC3 AWD1 */
920 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */
921 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 TIM8_AF1_ETRSEL_3 /* !< TIM8_ETR is connected to ADC3 AWD3 */
922
923 #define LL_TIM_TIM2_ETRSOURCE_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */
924 #define LL_TIM_TIM2_ETRSOURCE_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to COMP1 OUT */
925 #define LL_TIM_TIM2_ETRSOURCE_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM2_ETR is connected to COMP2 OUT */
926 #define LL_TIM_TIM2_ETRSOURCE_RCC_LSE (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to RCC LSE */
927 #define LL_TIM_TIM2_ETRSOURCE_SAI1_FSA TIM2_AF1_ETRSEL_2 /* !< TIM2_ETR is connected to SAI1 FS_A */
928 #define LL_TIM_TIM2_ETRSOURCE_SAI1_FSB (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to SAI1 FS_B */
929
930 #define LL_TIM_TIM3_ETRSOURCE_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */
931 #define LL_TIM_TIM3_ETRSOURCE_COMP1 TIM3_AF1_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 OUT */
932
933 #define LL_TIM_TIM5_ETRSOURCE_GPIO 0x00000000U /* !< TIM5_ETR is connected to GPIO */
934 #define LL_TIM_TIM5_ETRSOURCE_SAI2_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI2 FS_A */
935 #define LL_TIM_TIM5_ETRSOURCE_SAI2_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI2 FS_B */
936 #define LL_TIM_TIM5_ETRSOURCE_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI4 FS_A */
937 #define LL_TIM_TIM5_ETRSOURCE_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI4 FS_B */
938
939 #define LL_TIM_TIM23_ETRSOURCE_GPIO 0x00000000U /* !< TIM23_ETR is connected to GPIO */
940 #define LL_TIM_TIM23_ETRSOURCE_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM23_ETR is connected to COMP1 OUT */
941 #define LL_TIM_TIM23_ETRSOURCE_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM23_ETR is connected to COMP2 OUT */
942
943 #define LL_TIM_TIM24_ETRSOURCE_GPIO 0x00000000U /* !< TIM24_ETR is connected to GPIO */
944 #define LL_TIM_TIM24_ETRSOURCE_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM24_ETR is connected to SAI4 FS_A */
945 #define LL_TIM_TIM24_ETRSOURCE_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM24_ETR is connected to SAI4 FS_B */
946 #define LL_TIM_TIM24_ETRSOURCE_SAI1_FSA (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM24_ETR is connected to SAI1 FS_A */
947 #define LL_TIM_TIM24_ETRSOURCE_SAI1_FSB TIM2_AF1_ETRSEL_2 /* !< TIM24_ETR is connected to SAI1 FS_B */
948
949 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
950 * @{
951 */
952 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
953 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
954 /**
955 * @}
956 */
957
958 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
959 * @{
960 */
961 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
962 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
963 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
964 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
965 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
966 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
967 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
968 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
969 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
970 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
971 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
972 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
973 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
974 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
975 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
976 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
977 /**
978 * @}
979 */
980
981 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
982 * @{
983 */
984 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
985 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
986 /**
987 * @}
988 */
989
990 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
991 * @{
992 */
993 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
994 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
995 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
996 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
997 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
998 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
999 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1000 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1001 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1002 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1003 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1004 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1005 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1006 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1007 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1008 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1009 /**
1010 * @}
1011 */
1012
1013 /** @defgroup TIM_LL_EC_OSSI OSSI
1014 * @{
1015 */
1016 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1017 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1018 /**
1019 * @}
1020 */
1021
1022 /** @defgroup TIM_LL_EC_OSSR OSSR
1023 * @{
1024 */
1025 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1026 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1027 /**
1028 * @}
1029 */
1030
1031 #if defined(TIM_BREAK_INPUT_SUPPORT)
1032 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1033 * @{
1034 */
1035 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1036 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1037 /**
1038 * @}
1039 */
1040
1041 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1042 * @{
1043 */
1044 #define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE /*!< BKIN input from AF controller */
1045 #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E /*!< internal signal: COMP1 output */
1046 #define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E /*!< internal signal: COMP2 output */
1047 #define LL_TIM_BKIN_SOURCE_DF1BK TIM1_AF1_BKDF1BK0E /*!< internal signal: DFSDM1 break output */
1048 /**
1049 * @}
1050 */
1051
1052 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1053 * @{
1054 */
1055 #define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /*!< BRK BKIN input is active low */
1056 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1057 /**
1058 * @}
1059 */
1060 #endif /* TIM_BREAK_INPUT_SUPPORT */
1061
1062 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1063 * @{
1064 */
1065 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1066 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1067 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1068 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1069 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1070 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1071 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1072 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1073 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1074 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1075 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1076 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1077 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1078 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1079 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1080 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1081 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1082 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1083 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1084 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1085 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1086 #if defined(TIM_AF1_BKINE)&&defined(TIM_AF2_BKINE)
1087 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
1088 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
1089 #endif /* TIM_AF1_BKINE && TIM_AF2_BKINE */
1090 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_TISEL register is the DMA base address for DMA burst */
1091 /**
1092 * @}
1093 */
1094
1095 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1096 * @{
1097 */
1098 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1099 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1100 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1101 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1102 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1103 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1104 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1105 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1106 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1107 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1108 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1109 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1110 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1111 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1112 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1113 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1114 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1115 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1116 /**
1117 * @}
1118 */
1119
1120 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 Timer Input Ch1 Remap
1121 * @{
1122 */
1123 #define LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000U /* !< TIM1 input 1 is connected to GPIO */
1124 #define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM1 input 1 is connected to COMP1 OUT */
1125 /**
1126 * @}
1127 */
1128
1129 /** @defgroup TIM_LL_EC_TIM8_TI1_RMP TIM8 Timer Input Ch1 Remap
1130 * @{
1131 */
1132 #define LL_TIM_TIM8_TI1_RMP_GPIO 0x00000000U /* !< TIM8 input 1 is connected to GPIO */
1133 #define LL_TIM_TIM8_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_0 /* !< TIM8 input 1 is connected to COMP2 OUT */
1134 /**
1135 * @}
1136 */
1137
1138 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 Timer Input Ch4 Remap
1139 * @{
1140 */
1141 #define LL_TIM_TIM2_TI4_RMP_GPIO 0x00000000U /* !< TIM2 input 4 is connected to GPIO */
1142 #define LL_TIM_TIM2_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM2 input 4 is connected to COMP1 OUT */
1143 #define LL_TIM_TIM2_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM2 input 4 is connected to COMP2 OUT */
1144 #define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM2 input 4 is connected to COMP2 OUT OR COMP2 OUT */
1145 /**
1146 * @}
1147 */
1148
1149 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 Timer Input Ch1 Remap
1150 * @{
1151 */
1152 #define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000U /* !< TIM3 input 1 is connected to GPIO */
1153 #define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM3 input 1 is connected to COMP1 OUT */
1154 #define LL_TIM_TIM3_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /* !< TIM3 input 1 is connected to COMP2 OUT */
1155 #define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3 input 1 is connected to COMP1 OUT or COMP2 OUT */
1156 /**
1157 * @}
1158 */
1159
1160 /** @defgroup TIM_LL_EC_TIM5_TI1_RMP TIM5 Timer Input Ch1 Remap
1161 * @{
1162 */
1163 #define LL_TIM_TIM5_TI1_RMP_GPIO 0x00000000U /* !< TIM5 input 1 is connected to GPIO */
1164 #define LL_TIM_TIM5_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM5 input 1 is connected to CAN TMP */
1165 #define LL_TIM_TIM5_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM5 input 1 is connected to CAN RTP */
1166 /**
1167 * @}
1168 */
1169
1170 /** @defgroup TIM_LL_EC_TIM12_TI1_RMP TIM12 Timer Input Ch1 Remap
1171 * @{
1172 */
1173 #define LL_TIM_TIM12_TI1_RMP_GPIO 0x00000000U /* !< TIM12 input 1 is connected to GPIO */
1174 #define LL_TIM_TIM12_TI1_RMP_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM12 input 1 is connected to SPDIF FS */
1175 /**
1176 * @}
1177 */
1178
1179 /** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 Timer Input Ch1 Remap
1180 * @{
1181 */
1182 #define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000U /* !< TIM15 input 1 is connected to GPIO */
1183 #define LL_TIM_TIM15_TI1_RMP_TIM2_CH1 TIM_TISEL_TI1SEL_0 /* !< TIM15 input 1 is connected to TIM2 CH1 */
1184 #define LL_TIM_TIM15_TI1_RMP_TIM3_CH1 TIM_TISEL_TI1SEL_1 /* !< TIM15 input 1 is connected to TIM3 CH1 */
1185 #define LL_TIM_TIM15_TI1_RMP_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15 input 1 is connected to TIM4 CH1 */
1186 #define LL_TIM_TIM15_TI1_RMP_RCC_LSE (TIM_TISEL_TI1SEL_2) /* !< TIM15 input 1 is connected to RCC LSE */
1187 #define LL_TIM_TIM15_TI1_RMP_RCC_CSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM15 input 1 is connected to RCC CSI */
1188 #define LL_TIM_TIM15_TI1_RMP_RCC_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM15 input 1 is connected to RCC MCO2 */
1189 /**
1190 * @}
1191 */
1192
1193 /** @defgroup TIM_LL_EC_TIM15_TI2_RMP TIM15 Timer Input Ch2 Remap
1194 * @{
1195 */
1196 #define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000U /* !< TIM15 input 2 is connected to GPIO */
1197 #define LL_TIM_TIM15_TI2_RMP_TIM2_CH2 (TIM_TISEL_TI2SEL_0) /* !< TIM15 input 2 is connected to TIM2 CH2 */
1198 #define LL_TIM_TIM15_TI2_RMP_TIM3_CH2 (TIM_TISEL_TI2SEL_1) /* !< TIM15 input 2 is connected to TIM3 CH2 */
1199 #define LL_TIM_TIM15_TI2_RMP_TIM4_CH2 (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /* !< TIM15 input 2 is connected to TIM4 CH2 */
1200 /**
1201 * @}
1202 */
1203
1204 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 Timer Input Ch1 Remap
1205 * @{
1206 */
1207 #define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U /* !< TIM16 input 1 is connected to GPIO */
1208 #define LL_TIM_TIM16_TI1_RMP_RCC_LSI TIM_TISEL_TI1SEL_0 /* !< TIM16 input 1 is connected to RCC LSI */
1209 #define LL_TIM_TIM16_TI1_RMP_RCC_LSE TIM_TISEL_TI1SEL_1 /* !< TIM16 input 1 is connected to RCC LSE */
1210 #define LL_TIM_TIM16_TI1_RMP_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 input 1 is connected to WKUP_IT */
1211 /**
1212 * @}
1213 */
1214
1215 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap
1216 * @{
1217 */
1218 #define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000U /* !< TIM17 input 1 is connected to GPIO */
1219 #define LL_TIM_TIM17_TI1_RMP_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM17 input 1 is connected to SPDIF FS */
1220 #define LL_TIM_TIM17_TI1_RMP_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /* !< TIM17 input 1 is connected to RCC HSE 1Mhz */
1221 #define LL_TIM_TIM17_TI1_RMP_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 input 1 is connected to RCC MCO1 */
1222 /**
1223 * @}
1224 */
1225
1226 /** @defgroup TIM_LL_EC_TIM23_TI4_RMP TIM23 Timer Input Ch4 Remap
1227 * @{
1228 */
1229 #define LL_TIM_TIM23_TI4_RMP_GPIO 0x00000000U /* !< TIM23 input 4 is connected to GPIO */
1230 #define LL_TIM_TIM23_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM23 input 4 is connected to COMP1 OUT */
1231 #define LL_TIM_TIM23_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM23 input 4 is connected to COMP2 OUT */
1232 #define LL_TIM_TIM23_TI4_RMP_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM23 input 4 is connected to COMP1 OUT or COMP2 OUT */
1233 /**
1234 * @}
1235 */
1236
1237 /** @defgroup TIM_LL_EC_TIM24_TI1_RMP TIM24 Timer Input Ch1 Remap
1238 * @{
1239 */
1240 #define LL_TIM_TIM24_TI1_RMP_GPIO 0x00000000U /* !< TIM24 input 1 is connected to GPIO */
1241 #define LL_TIM_TIM24_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM24 input 1 is connected to CAN TMP */
1242 #define LL_TIM_TIM24_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM24 input 1 is connected to CAN RTP */
1243 #define LL_TIM_TIM24_TI1_RMP_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24 input 1 is connected to CAN SOC */
1244 /**
1245 * @}
1246 */
1247
1248 #if defined(TIM_BREAK_INPUT_SUPPORT)
1249 /** Legacy definitions for compatibility purpose
1250 @cond 0
1251 */
1252 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
1253 /**
1254 @endcond
1255 */
1256 #endif /* TIM_BREAK_INPUT_SUPPORT */
1257 /**
1258 * @}
1259 */
1260
1261 /* Exported macro ------------------------------------------------------------*/
1262 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1263 * @{
1264 */
1265
1266 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1267 * @{
1268 */
1269 /**
1270 * @brief Write a value in TIM register.
1271 * @param __INSTANCE__ TIM Instance
1272 * @param __REG__ Register to be written
1273 * @param __VALUE__ Value to be written in the register
1274 * @retval None
1275 */
1276 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1277
1278 /**
1279 * @brief Read a value in TIM register.
1280 * @param __INSTANCE__ TIM Instance
1281 * @param __REG__ Register to be read
1282 * @retval Register value
1283 */
1284 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1285 /**
1286 * @}
1287 */
1288
1289 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
1290 * @{
1291 */
1292
1293 /**
1294 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1295 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1296 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1297 * to TIMx_CNT register bit 31)
1298 * @param __CNT__ Counter value
1299 * @retval UIF status bit
1300 */
1301 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1302 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1303
1304 /**
1305 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1306 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1307 * @param __TIMCLK__ timer input clock frequency (in Hz)
1308 * @param __CKD__ This parameter can be one of the following values:
1309 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1310 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1311 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1312 * @param __DT__ deadtime duration (in ns)
1313 * @retval DTG[0:7]
1314 */
1315 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1316 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1317 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1318 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1319 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1320 0U)
1321
1322 /**
1323 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1324 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1325 * @param __TIMCLK__ timer input clock frequency (in Hz)
1326 * @param __CNTCLK__ counter clock frequency (in Hz)
1327 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1328 */
1329 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1330 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
1331
1332 /**
1333 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1334 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1335 * @param __TIMCLK__ timer input clock frequency (in Hz)
1336 * @param __PSC__ prescaler
1337 * @param __FREQ__ output signal frequency (in Hz)
1338 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1339 */
1340 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1341 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1342
1343 /**
1344 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
1345 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1346 * @param __TIMCLK__ timer input clock frequency (in Hz)
1347 * @param __PSC__ prescaler
1348 * @param __DELAY__ timer output compare active/inactive delay (in us)
1349 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1350 */
1351 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1352 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1353 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1354
1355 /**
1356 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
1357 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1358 * @param __TIMCLK__ timer input clock frequency (in Hz)
1359 * @param __PSC__ prescaler
1360 * @param __DELAY__ timer output compare active/inactive delay (in us)
1361 * @param __PULSE__ pulse duration (in us)
1362 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1363 */
1364 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1365 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1366 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1367
1368 /**
1369 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1370 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1371 * @param __ICPSC__ This parameter can be one of the following values:
1372 * @arg @ref LL_TIM_ICPSC_DIV1
1373 * @arg @ref LL_TIM_ICPSC_DIV2
1374 * @arg @ref LL_TIM_ICPSC_DIV4
1375 * @arg @ref LL_TIM_ICPSC_DIV8
1376 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1377 */
1378 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1379 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1380
1381
1382 /**
1383 * @}
1384 */
1385
1386
1387 /**
1388 * @}
1389 */
1390
1391 /* Exported functions --------------------------------------------------------*/
1392 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1393 * @{
1394 */
1395
1396 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1397 * @{
1398 */
1399 /**
1400 * @brief Enable timer counter.
1401 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1402 * @param TIMx Timer instance
1403 * @retval None
1404 */
1405 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1406 {
1407 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1408 }
1409
1410 /**
1411 * @brief Disable timer counter.
1412 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1413 * @param TIMx Timer instance
1414 * @retval None
1415 */
1416 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1417 {
1418 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1419 }
1420
1421 /**
1422 * @brief Indicates whether the timer counter is enabled.
1423 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1424 * @param TIMx Timer instance
1425 * @retval State of bit (1 or 0).
1426 */
1427 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
1428 {
1429 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1430 }
1431
1432 /**
1433 * @brief Enable update event generation.
1434 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1435 * @param TIMx Timer instance
1436 * @retval None
1437 */
1438 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1439 {
1440 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1441 }
1442
1443 /**
1444 * @brief Disable update event generation.
1445 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1446 * @param TIMx Timer instance
1447 * @retval None
1448 */
1449 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1450 {
1451 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1452 }
1453
1454 /**
1455 * @brief Indicates whether update event generation is enabled.
1456 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1457 * @param TIMx Timer instance
1458 * @retval Inverted state of bit (0 or 1).
1459 */
1460 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
1461 {
1462 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1463 }
1464
1465 /**
1466 * @brief Set update event source
1467 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1468 * generate an update interrupt or DMA request if enabled:
1469 * - Counter overflow/underflow
1470 * - Setting the UG bit
1471 * - Update generation through the slave mode controller
1472 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1473 * overflow/underflow generates an update interrupt or DMA request if enabled.
1474 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1475 * @param TIMx Timer instance
1476 * @param UpdateSource This parameter can be one of the following values:
1477 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1478 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1479 * @retval None
1480 */
1481 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1482 {
1483 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1484 }
1485
1486 /**
1487 * @brief Get actual event update source
1488 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1489 * @param TIMx Timer instance
1490 * @retval Returned value can be one of the following values:
1491 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1492 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1493 */
1494 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
1495 {
1496 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1497 }
1498
1499 /**
1500 * @brief Set one pulse mode (one shot v.s. repetitive).
1501 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1502 * @param TIMx Timer instance
1503 * @param OnePulseMode This parameter can be one of the following values:
1504 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1505 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1506 * @retval None
1507 */
1508 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1509 {
1510 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1511 }
1512
1513 /**
1514 * @brief Get actual one pulse mode.
1515 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1516 * @param TIMx Timer instance
1517 * @retval Returned value can be one of the following values:
1518 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1519 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1520 */
1521 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
1522 {
1523 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1524 }
1525
1526 /**
1527 * @brief Set the timer counter counting mode.
1528 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1529 * check whether or not the counter mode selection feature is supported
1530 * by a timer instance.
1531 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1532 * requires a timer reset to avoid unexpected direction
1533 * due to DIR bit readonly in center aligned mode.
1534 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1535 * CR1 CMS LL_TIM_SetCounterMode
1536 * @param TIMx Timer instance
1537 * @param CounterMode This parameter can be one of the following values:
1538 * @arg @ref LL_TIM_COUNTERMODE_UP
1539 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1540 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1541 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1542 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1543 * @retval None
1544 */
1545 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1546 {
1547 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1548 }
1549
1550 /**
1551 * @brief Get actual counter mode.
1552 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1553 * check whether or not the counter mode selection feature is supported
1554 * by a timer instance.
1555 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1556 * CR1 CMS LL_TIM_GetCounterMode
1557 * @param TIMx Timer instance
1558 * @retval Returned value can be one of the following values:
1559 * @arg @ref LL_TIM_COUNTERMODE_UP
1560 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1561 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1562 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1563 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1564 */
1565 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
1566 {
1567 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
1568 }
1569
1570 /**
1571 * @brief Enable auto-reload (ARR) preload.
1572 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1573 * @param TIMx Timer instance
1574 * @retval None
1575 */
1576 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1577 {
1578 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1579 }
1580
1581 /**
1582 * @brief Disable auto-reload (ARR) preload.
1583 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1584 * @param TIMx Timer instance
1585 * @retval None
1586 */
1587 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1588 {
1589 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1590 }
1591
1592 /**
1593 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1594 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1595 * @param TIMx Timer instance
1596 * @retval State of bit (1 or 0).
1597 */
1598 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
1599 {
1600 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1601 }
1602
1603 /**
1604 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
1605 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1606 * whether or not the clock division feature is supported by the timer
1607 * instance.
1608 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1609 * @param TIMx Timer instance
1610 * @param ClockDivision This parameter can be one of the following values:
1611 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1612 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1613 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1614 * @retval None
1615 */
1616 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1617 {
1618 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1619 }
1620
1621 /**
1622 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
1623 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1624 * whether or not the clock division feature is supported by the timer
1625 * instance.
1626 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1627 * @param TIMx Timer instance
1628 * @retval Returned value can be one of the following values:
1629 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1630 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1631 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1632 */
1633 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
1634 {
1635 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1636 }
1637
1638 /**
1639 * @brief Set the counter value.
1640 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1641 * whether or not a timer instance supports a 32 bits counter.
1642 * @rmtoll CNT CNT LL_TIM_SetCounter
1643 * @param TIMx Timer instance
1644 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1645 * @retval None
1646 */
1647 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1648 {
1649 WRITE_REG(TIMx->CNT, Counter);
1650 }
1651
1652 /**
1653 * @brief Get the counter value.
1654 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1655 * whether or not a timer instance supports a 32 bits counter.
1656 * @rmtoll CNT CNT LL_TIM_GetCounter
1657 * @param TIMx Timer instance
1658 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1659 */
1660 __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
1661 {
1662 return (uint32_t)(READ_REG(TIMx->CNT));
1663 }
1664
1665 /**
1666 * @brief Get the current direction of the counter
1667 * @rmtoll CR1 DIR LL_TIM_GetDirection
1668 * @param TIMx Timer instance
1669 * @retval Returned value can be one of the following values:
1670 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1671 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1672 */
1673 __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
1674 {
1675 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1676 }
1677
1678 /**
1679 * @brief Set the prescaler value.
1680 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1681 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1682 * prescaler ratio is taken into account at the next update event.
1683 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1684 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1685 * @param TIMx Timer instance
1686 * @param Prescaler between Min_Data=0 and Max_Data=65535
1687 * @retval None
1688 */
1689 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1690 {
1691 WRITE_REG(TIMx->PSC, Prescaler);
1692 }
1693
1694 /**
1695 * @brief Get the prescaler value.
1696 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1697 * @param TIMx Timer instance
1698 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1699 */
1700 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
1701 {
1702 return (uint32_t)(READ_REG(TIMx->PSC));
1703 }
1704
1705 /**
1706 * @brief Set the auto-reload value.
1707 * @note The counter is blocked while the auto-reload value is null.
1708 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1709 * whether or not a timer instance supports a 32 bits counter.
1710 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1711 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1712 * @param TIMx Timer instance
1713 * @param AutoReload between Min_Data=0 and Max_Data=65535
1714 * @retval None
1715 */
1716 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1717 {
1718 WRITE_REG(TIMx->ARR, AutoReload);
1719 }
1720
1721 /**
1722 * @brief Get the auto-reload value.
1723 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1724 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1725 * whether or not a timer instance supports a 32 bits counter.
1726 * @param TIMx Timer instance
1727 * @retval Auto-reload value
1728 */
1729 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
1730 {
1731 return (uint32_t)(READ_REG(TIMx->ARR));
1732 }
1733
1734 /**
1735 * @brief Set the repetition counter value.
1736 * @note For advanced timer instances RepetitionCounter can be up to 65535.
1737 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1738 * whether or not a timer instance supports a repetition counter.
1739 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1740 * @param TIMx Timer instance
1741 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
1742 * @retval None
1743 */
1744 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1745 {
1746 WRITE_REG(TIMx->RCR, RepetitionCounter);
1747 }
1748
1749 /**
1750 * @brief Get the repetition counter value.
1751 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1752 * whether or not a timer instance supports a repetition counter.
1753 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1754 * @param TIMx Timer instance
1755 * @retval Repetition counter value
1756 */
1757 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
1758 {
1759 return (uint32_t)(READ_REG(TIMx->RCR));
1760 }
1761
1762 /**
1763 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
1764 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
1765 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
1766 * @param TIMx Timer instance
1767 * @retval None
1768 */
1769 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
1770 {
1771 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1772 }
1773
1774 /**
1775 * @brief Disable update interrupt flag (UIF) remapping.
1776 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
1777 * @param TIMx Timer instance
1778 * @retval None
1779 */
1780 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
1781 {
1782 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1783 }
1784
1785 /**
1786 * @brief Indicate whether update interrupt flag (UIF) copy is set.
1787 * @param Counter Counter value
1788 * @retval State of bit (1 or 0).
1789 */
1790 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter)
1791 {
1792 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
1793 }
1794
1795 /**
1796 * @}
1797 */
1798
1799 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1800 * @{
1801 */
1802 /**
1803 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1804 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1805 * they are updated only when a commutation event (COM) occurs.
1806 * @note Only on channels that have a complementary output.
1807 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1808 * whether or not a timer instance is able to generate a commutation event.
1809 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1810 * @param TIMx Timer instance
1811 * @retval None
1812 */
1813 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1814 {
1815 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1816 }
1817
1818 /**
1819 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1820 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1821 * whether or not a timer instance is able to generate a commutation event.
1822 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1823 * @param TIMx Timer instance
1824 * @retval None
1825 */
1826 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1827 {
1828 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1829 }
1830
1831 /**
1832 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1833 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1834 * whether or not a timer instance is able to generate a commutation event.
1835 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1836 * @param TIMx Timer instance
1837 * @param CCUpdateSource This parameter can be one of the following values:
1838 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1839 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1840 * @retval None
1841 */
1842 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1843 {
1844 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1845 }
1846
1847 /**
1848 * @brief Set the trigger of the capture/compare DMA request.
1849 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1850 * @param TIMx Timer instance
1851 * @param DMAReqTrigger This parameter can be one of the following values:
1852 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1853 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1854 * @retval None
1855 */
1856 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1857 {
1858 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1859 }
1860
1861 /**
1862 * @brief Get actual trigger of the capture/compare DMA request.
1863 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1864 * @param TIMx Timer instance
1865 * @retval Returned value can be one of the following values:
1866 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1867 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1868 */
1869 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
1870 {
1871 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1872 }
1873
1874 /**
1875 * @brief Set the lock level to freeze the
1876 * configuration of several capture/compare parameters.
1877 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1878 * the lock mechanism is supported by a timer instance.
1879 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1880 * @param TIMx Timer instance
1881 * @param LockLevel This parameter can be one of the following values:
1882 * @arg @ref LL_TIM_LOCKLEVEL_OFF
1883 * @arg @ref LL_TIM_LOCKLEVEL_1
1884 * @arg @ref LL_TIM_LOCKLEVEL_2
1885 * @arg @ref LL_TIM_LOCKLEVEL_3
1886 * @retval None
1887 */
1888 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1889 {
1890 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1891 }
1892
1893 /**
1894 * @brief Enable capture/compare channels.
1895 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1896 * CCER CC1NE LL_TIM_CC_EnableChannel\n
1897 * CCER CC2E LL_TIM_CC_EnableChannel\n
1898 * CCER CC2NE LL_TIM_CC_EnableChannel\n
1899 * CCER CC3E LL_TIM_CC_EnableChannel\n
1900 * CCER CC3NE LL_TIM_CC_EnableChannel\n
1901 * CCER CC4E LL_TIM_CC_EnableChannel\n
1902 * CCER CC5E LL_TIM_CC_EnableChannel\n
1903 * CCER CC6E LL_TIM_CC_EnableChannel
1904 * @param TIMx Timer instance
1905 * @param Channels This parameter can be a combination of the following values:
1906 * @arg @ref LL_TIM_CHANNEL_CH1
1907 * @arg @ref LL_TIM_CHANNEL_CH1N
1908 * @arg @ref LL_TIM_CHANNEL_CH2
1909 * @arg @ref LL_TIM_CHANNEL_CH2N
1910 * @arg @ref LL_TIM_CHANNEL_CH3
1911 * @arg @ref LL_TIM_CHANNEL_CH3N
1912 * @arg @ref LL_TIM_CHANNEL_CH4
1913 * @arg @ref LL_TIM_CHANNEL_CH5
1914 * @arg @ref LL_TIM_CHANNEL_CH6
1915 * @retval None
1916 */
1917 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1918 {
1919 SET_BIT(TIMx->CCER, Channels);
1920 }
1921
1922 /**
1923 * @brief Disable capture/compare channels.
1924 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
1925 * CCER CC1NE LL_TIM_CC_DisableChannel\n
1926 * CCER CC2E LL_TIM_CC_DisableChannel\n
1927 * CCER CC2NE LL_TIM_CC_DisableChannel\n
1928 * CCER CC3E LL_TIM_CC_DisableChannel\n
1929 * CCER CC3NE LL_TIM_CC_DisableChannel\n
1930 * CCER CC4E LL_TIM_CC_DisableChannel\n
1931 * CCER CC5E LL_TIM_CC_DisableChannel\n
1932 * CCER CC6E LL_TIM_CC_DisableChannel
1933 * @param TIMx Timer instance
1934 * @param Channels This parameter can be a combination of the following values:
1935 * @arg @ref LL_TIM_CHANNEL_CH1
1936 * @arg @ref LL_TIM_CHANNEL_CH1N
1937 * @arg @ref LL_TIM_CHANNEL_CH2
1938 * @arg @ref LL_TIM_CHANNEL_CH2N
1939 * @arg @ref LL_TIM_CHANNEL_CH3
1940 * @arg @ref LL_TIM_CHANNEL_CH3N
1941 * @arg @ref LL_TIM_CHANNEL_CH4
1942 * @arg @ref LL_TIM_CHANNEL_CH5
1943 * @arg @ref LL_TIM_CHANNEL_CH6
1944 * @retval None
1945 */
1946 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1947 {
1948 CLEAR_BIT(TIMx->CCER, Channels);
1949 }
1950
1951 /**
1952 * @brief Indicate whether channel(s) is(are) enabled.
1953 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
1954 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
1955 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
1956 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
1957 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
1958 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
1959 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
1960 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
1961 * CCER CC6E LL_TIM_CC_IsEnabledChannel
1962 * @param TIMx Timer instance
1963 * @param Channels This parameter can be a combination of the following values:
1964 * @arg @ref LL_TIM_CHANNEL_CH1
1965 * @arg @ref LL_TIM_CHANNEL_CH1N
1966 * @arg @ref LL_TIM_CHANNEL_CH2
1967 * @arg @ref LL_TIM_CHANNEL_CH2N
1968 * @arg @ref LL_TIM_CHANNEL_CH3
1969 * @arg @ref LL_TIM_CHANNEL_CH3N
1970 * @arg @ref LL_TIM_CHANNEL_CH4
1971 * @arg @ref LL_TIM_CHANNEL_CH5
1972 * @arg @ref LL_TIM_CHANNEL_CH6
1973 * @retval State of bit (1 or 0).
1974 */
1975 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1976 {
1977 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
1978 }
1979
1980 /**
1981 * @}
1982 */
1983
1984 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
1985 * @{
1986 */
1987 /**
1988 * @brief Configure an output channel.
1989 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
1990 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
1991 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
1992 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
1993 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
1994 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
1995 * CCER CC1P LL_TIM_OC_ConfigOutput\n
1996 * CCER CC2P LL_TIM_OC_ConfigOutput\n
1997 * CCER CC3P LL_TIM_OC_ConfigOutput\n
1998 * CCER CC4P LL_TIM_OC_ConfigOutput\n
1999 * CCER CC5P LL_TIM_OC_ConfigOutput\n
2000 * CCER CC6P LL_TIM_OC_ConfigOutput\n
2001 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
2002 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
2003 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
2004 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
2005 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
2006 * CR2 OIS6 LL_TIM_OC_ConfigOutput
2007 * @param TIMx Timer instance
2008 * @param Channel This parameter can be one of the following values:
2009 * @arg @ref LL_TIM_CHANNEL_CH1
2010 * @arg @ref LL_TIM_CHANNEL_CH2
2011 * @arg @ref LL_TIM_CHANNEL_CH3
2012 * @arg @ref LL_TIM_CHANNEL_CH4
2013 * @arg @ref LL_TIM_CHANNEL_CH5
2014 * @arg @ref LL_TIM_CHANNEL_CH6
2015 * @param Configuration This parameter must be a combination of all the following values:
2016 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
2017 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
2018 * @retval None
2019 */
2020 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2021 {
2022 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2023 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2024 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2025 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2026 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2027 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2028 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2029 }
2030
2031 /**
2032 * @brief Define the behavior of the output reference signal OCxREF from which
2033 * OCx and OCxN (when relevant) are derived.
2034 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2035 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2036 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2037 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2038 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2039 * CCMR3 OC6M LL_TIM_OC_SetMode
2040 * @param TIMx Timer instance
2041 * @param Channel This parameter can be one of the following values:
2042 * @arg @ref LL_TIM_CHANNEL_CH1
2043 * @arg @ref LL_TIM_CHANNEL_CH2
2044 * @arg @ref LL_TIM_CHANNEL_CH3
2045 * @arg @ref LL_TIM_CHANNEL_CH4
2046 * @arg @ref LL_TIM_CHANNEL_CH5
2047 * @arg @ref LL_TIM_CHANNEL_CH6
2048 * @param Mode This parameter can be one of the following values:
2049 * @arg @ref LL_TIM_OCMODE_FROZEN
2050 * @arg @ref LL_TIM_OCMODE_ACTIVE
2051 * @arg @ref LL_TIM_OCMODE_INACTIVE
2052 * @arg @ref LL_TIM_OCMODE_TOGGLE
2053 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2054 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2055 * @arg @ref LL_TIM_OCMODE_PWM1
2056 * @arg @ref LL_TIM_OCMODE_PWM2
2057 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2058 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2059 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2060 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2061 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2062 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2063 * @retval None
2064 */
2065 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2066 {
2067 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2068 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2069 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2070 }
2071
2072 /**
2073 * @brief Get the output compare mode of an output channel.
2074 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2075 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2076 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2077 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2078 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2079 * CCMR3 OC6M LL_TIM_OC_GetMode
2080 * @param TIMx Timer instance
2081 * @param Channel This parameter can be one of the following values:
2082 * @arg @ref LL_TIM_CHANNEL_CH1
2083 * @arg @ref LL_TIM_CHANNEL_CH2
2084 * @arg @ref LL_TIM_CHANNEL_CH3
2085 * @arg @ref LL_TIM_CHANNEL_CH4
2086 * @arg @ref LL_TIM_CHANNEL_CH5
2087 * @arg @ref LL_TIM_CHANNEL_CH6
2088 * @retval Returned value can be one of the following values:
2089 * @arg @ref LL_TIM_OCMODE_FROZEN
2090 * @arg @ref LL_TIM_OCMODE_ACTIVE
2091 * @arg @ref LL_TIM_OCMODE_INACTIVE
2092 * @arg @ref LL_TIM_OCMODE_TOGGLE
2093 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2094 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2095 * @arg @ref LL_TIM_OCMODE_PWM1
2096 * @arg @ref LL_TIM_OCMODE_PWM2
2097 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2098 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2099 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2100 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2101 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2102 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2103 */
2104 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
2105 {
2106 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2107 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2108 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2109 }
2110
2111 /**
2112 * @brief Set the polarity of an output channel.
2113 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2114 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2115 * CCER CC2P LL_TIM_OC_SetPolarity\n
2116 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2117 * CCER CC3P LL_TIM_OC_SetPolarity\n
2118 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2119 * CCER CC4P LL_TIM_OC_SetPolarity\n
2120 * CCER CC5P LL_TIM_OC_SetPolarity\n
2121 * CCER CC6P LL_TIM_OC_SetPolarity
2122 * @param TIMx Timer instance
2123 * @param Channel This parameter can be one of the following values:
2124 * @arg @ref LL_TIM_CHANNEL_CH1
2125 * @arg @ref LL_TIM_CHANNEL_CH1N
2126 * @arg @ref LL_TIM_CHANNEL_CH2
2127 * @arg @ref LL_TIM_CHANNEL_CH2N
2128 * @arg @ref LL_TIM_CHANNEL_CH3
2129 * @arg @ref LL_TIM_CHANNEL_CH3N
2130 * @arg @ref LL_TIM_CHANNEL_CH4
2131 * @arg @ref LL_TIM_CHANNEL_CH5
2132 * @arg @ref LL_TIM_CHANNEL_CH6
2133 * @param Polarity This parameter can be one of the following values:
2134 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2135 * @arg @ref LL_TIM_OCPOLARITY_LOW
2136 * @retval None
2137 */
2138 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2139 {
2140 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2141 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2142 }
2143
2144 /**
2145 * @brief Get the polarity of an output channel.
2146 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2147 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2148 * CCER CC2P LL_TIM_OC_GetPolarity\n
2149 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2150 * CCER CC3P LL_TIM_OC_GetPolarity\n
2151 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2152 * CCER CC4P LL_TIM_OC_GetPolarity\n
2153 * CCER CC5P LL_TIM_OC_GetPolarity\n
2154 * CCER CC6P LL_TIM_OC_GetPolarity
2155 * @param TIMx Timer instance
2156 * @param Channel This parameter can be one of the following values:
2157 * @arg @ref LL_TIM_CHANNEL_CH1
2158 * @arg @ref LL_TIM_CHANNEL_CH1N
2159 * @arg @ref LL_TIM_CHANNEL_CH2
2160 * @arg @ref LL_TIM_CHANNEL_CH2N
2161 * @arg @ref LL_TIM_CHANNEL_CH3
2162 * @arg @ref LL_TIM_CHANNEL_CH3N
2163 * @arg @ref LL_TIM_CHANNEL_CH4
2164 * @arg @ref LL_TIM_CHANNEL_CH5
2165 * @arg @ref LL_TIM_CHANNEL_CH6
2166 * @retval Returned value can be one of the following values:
2167 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2168 * @arg @ref LL_TIM_OCPOLARITY_LOW
2169 */
2170 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
2171 {
2172 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2173 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2174 }
2175
2176 /**
2177 * @brief Set the IDLE state of an output channel
2178 * @note This function is significant only for the timer instances
2179 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2180 * can be used to check whether or not a timer instance provides
2181 * a break input.
2182 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2183 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2184 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2185 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2186 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2187 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2188 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2189 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2190 * CR2 OIS6 LL_TIM_OC_SetIdleState
2191 * @param TIMx Timer instance
2192 * @param Channel This parameter can be one of the following values:
2193 * @arg @ref LL_TIM_CHANNEL_CH1
2194 * @arg @ref LL_TIM_CHANNEL_CH1N
2195 * @arg @ref LL_TIM_CHANNEL_CH2
2196 * @arg @ref LL_TIM_CHANNEL_CH2N
2197 * @arg @ref LL_TIM_CHANNEL_CH3
2198 * @arg @ref LL_TIM_CHANNEL_CH3N
2199 * @arg @ref LL_TIM_CHANNEL_CH4
2200 * @arg @ref LL_TIM_CHANNEL_CH5
2201 * @arg @ref LL_TIM_CHANNEL_CH6
2202 * @param IdleState This parameter can be one of the following values:
2203 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2204 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2205 * @retval None
2206 */
2207 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2208 {
2209 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2210 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2211 }
2212
2213 /**
2214 * @brief Get the IDLE state of an output channel
2215 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2216 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2217 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2218 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2219 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2220 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2221 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2222 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2223 * CR2 OIS6 LL_TIM_OC_GetIdleState
2224 * @param TIMx Timer instance
2225 * @param Channel This parameter can be one of the following values:
2226 * @arg @ref LL_TIM_CHANNEL_CH1
2227 * @arg @ref LL_TIM_CHANNEL_CH1N
2228 * @arg @ref LL_TIM_CHANNEL_CH2
2229 * @arg @ref LL_TIM_CHANNEL_CH2N
2230 * @arg @ref LL_TIM_CHANNEL_CH3
2231 * @arg @ref LL_TIM_CHANNEL_CH3N
2232 * @arg @ref LL_TIM_CHANNEL_CH4
2233 * @arg @ref LL_TIM_CHANNEL_CH5
2234 * @arg @ref LL_TIM_CHANNEL_CH6
2235 * @retval Returned value can be one of the following values:
2236 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2237 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2238 */
2239 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
2240 {
2241 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2242 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2243 }
2244
2245 /**
2246 * @brief Enable fast mode for the output channel.
2247 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2248 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2249 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2250 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2251 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2252 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2253 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2254 * @param TIMx Timer instance
2255 * @param Channel This parameter can be one of the following values:
2256 * @arg @ref LL_TIM_CHANNEL_CH1
2257 * @arg @ref LL_TIM_CHANNEL_CH2
2258 * @arg @ref LL_TIM_CHANNEL_CH3
2259 * @arg @ref LL_TIM_CHANNEL_CH4
2260 * @arg @ref LL_TIM_CHANNEL_CH5
2261 * @arg @ref LL_TIM_CHANNEL_CH6
2262 * @retval None
2263 */
2264 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2265 {
2266 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2267 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2268 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2269
2270 }
2271
2272 /**
2273 * @brief Disable fast mode for the output channel.
2274 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2275 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2276 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2277 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2278 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2279 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2280 * @param TIMx Timer instance
2281 * @param Channel This parameter can be one of the following values:
2282 * @arg @ref LL_TIM_CHANNEL_CH1
2283 * @arg @ref LL_TIM_CHANNEL_CH2
2284 * @arg @ref LL_TIM_CHANNEL_CH3
2285 * @arg @ref LL_TIM_CHANNEL_CH4
2286 * @arg @ref LL_TIM_CHANNEL_CH5
2287 * @arg @ref LL_TIM_CHANNEL_CH6
2288 * @retval None
2289 */
2290 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2291 {
2292 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2293 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2294 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2295
2296 }
2297
2298 /**
2299 * @brief Indicates whether fast mode is enabled for the output channel.
2300 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2301 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2302 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2303 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2304 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2305 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2306 * @param TIMx Timer instance
2307 * @param Channel This parameter can be one of the following values:
2308 * @arg @ref LL_TIM_CHANNEL_CH1
2309 * @arg @ref LL_TIM_CHANNEL_CH2
2310 * @arg @ref LL_TIM_CHANNEL_CH3
2311 * @arg @ref LL_TIM_CHANNEL_CH4
2312 * @arg @ref LL_TIM_CHANNEL_CH5
2313 * @arg @ref LL_TIM_CHANNEL_CH6
2314 * @retval State of bit (1 or 0).
2315 */
2316 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
2317 {
2318 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2319 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2320 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2321 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2322 }
2323
2324 /**
2325 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2326 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2327 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2328 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2329 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2330 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2331 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2332 * @param TIMx Timer instance
2333 * @param Channel This parameter can be one of the following values:
2334 * @arg @ref LL_TIM_CHANNEL_CH1
2335 * @arg @ref LL_TIM_CHANNEL_CH2
2336 * @arg @ref LL_TIM_CHANNEL_CH3
2337 * @arg @ref LL_TIM_CHANNEL_CH4
2338 * @arg @ref LL_TIM_CHANNEL_CH5
2339 * @arg @ref LL_TIM_CHANNEL_CH6
2340 * @retval None
2341 */
2342 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2343 {
2344 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2345 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2346 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2347 }
2348
2349 /**
2350 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2351 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2352 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2353 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2354 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2355 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2356 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2357 * @param TIMx Timer instance
2358 * @param Channel This parameter can be one of the following values:
2359 * @arg @ref LL_TIM_CHANNEL_CH1
2360 * @arg @ref LL_TIM_CHANNEL_CH2
2361 * @arg @ref LL_TIM_CHANNEL_CH3
2362 * @arg @ref LL_TIM_CHANNEL_CH4
2363 * @arg @ref LL_TIM_CHANNEL_CH5
2364 * @arg @ref LL_TIM_CHANNEL_CH6
2365 * @retval None
2366 */
2367 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2368 {
2369 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2370 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2371 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2372 }
2373
2374 /**
2375 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2376 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2377 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2378 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2379 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2380 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2381 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2382 * @param TIMx Timer instance
2383 * @param Channel This parameter can be one of the following values:
2384 * @arg @ref LL_TIM_CHANNEL_CH1
2385 * @arg @ref LL_TIM_CHANNEL_CH2
2386 * @arg @ref LL_TIM_CHANNEL_CH3
2387 * @arg @ref LL_TIM_CHANNEL_CH4
2388 * @arg @ref LL_TIM_CHANNEL_CH5
2389 * @arg @ref LL_TIM_CHANNEL_CH6
2390 * @retval State of bit (1 or 0).
2391 */
2392 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
2393 {
2394 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2395 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2396 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2397 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2398 }
2399
2400 /**
2401 * @brief Enable clearing the output channel on an external event.
2402 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2403 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2404 * or not a timer instance can clear the OCxREF signal on an external event.
2405 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2406 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2407 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2408 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2409 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2410 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2411 * @param TIMx Timer instance
2412 * @param Channel This parameter can be one of the following values:
2413 * @arg @ref LL_TIM_CHANNEL_CH1
2414 * @arg @ref LL_TIM_CHANNEL_CH2
2415 * @arg @ref LL_TIM_CHANNEL_CH3
2416 * @arg @ref LL_TIM_CHANNEL_CH4
2417 * @arg @ref LL_TIM_CHANNEL_CH5
2418 * @arg @ref LL_TIM_CHANNEL_CH6
2419 * @retval None
2420 */
2421 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2422 {
2423 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2424 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2425 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2426 }
2427
2428 /**
2429 * @brief Disable clearing the output channel on an external event.
2430 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2431 * or not a timer instance can clear the OCxREF signal on an external event.
2432 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2433 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2434 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2435 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2436 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2437 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2438 * @param TIMx Timer instance
2439 * @param Channel This parameter can be one of the following values:
2440 * @arg @ref LL_TIM_CHANNEL_CH1
2441 * @arg @ref LL_TIM_CHANNEL_CH2
2442 * @arg @ref LL_TIM_CHANNEL_CH3
2443 * @arg @ref LL_TIM_CHANNEL_CH4
2444 * @arg @ref LL_TIM_CHANNEL_CH5
2445 * @arg @ref LL_TIM_CHANNEL_CH6
2446 * @retval None
2447 */
2448 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2449 {
2450 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2451 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2452 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2453 }
2454
2455 /**
2456 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2457 * @note This function enables clearing the output channel on an external event.
2458 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2459 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2460 * or not a timer instance can clear the OCxREF signal on an external event.
2461 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2462 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2463 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2464 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2465 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2466 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2467 * @param TIMx Timer instance
2468 * @param Channel This parameter can be one of the following values:
2469 * @arg @ref LL_TIM_CHANNEL_CH1
2470 * @arg @ref LL_TIM_CHANNEL_CH2
2471 * @arg @ref LL_TIM_CHANNEL_CH3
2472 * @arg @ref LL_TIM_CHANNEL_CH4
2473 * @arg @ref LL_TIM_CHANNEL_CH5
2474 * @arg @ref LL_TIM_CHANNEL_CH6
2475 * @retval State of bit (1 or 0).
2476 */
2477 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
2478 {
2479 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2480 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2481 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2482 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2483 }
2484
2485 /**
2486 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
2487 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2488 * dead-time insertion feature is supported by a timer instance.
2489 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2490 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2491 * @param TIMx Timer instance
2492 * @param DeadTime between Min_Data=0 and Max_Data=255
2493 * @retval None
2494 */
2495 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2496 {
2497 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2498 }
2499
2500 /**
2501 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2502 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2503 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2504 * whether or not a timer instance supports a 32 bits counter.
2505 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2506 * output channel 1 is supported by a timer instance.
2507 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2508 * @param TIMx Timer instance
2509 * @param CompareValue between Min_Data=0 and Max_Data=65535
2510 * @retval None
2511 */
2512 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2513 {
2514 WRITE_REG(TIMx->CCR1, CompareValue);
2515 }
2516
2517 /**
2518 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2519 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2520 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2521 * whether or not a timer instance supports a 32 bits counter.
2522 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2523 * output channel 2 is supported by a timer instance.
2524 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2525 * @param TIMx Timer instance
2526 * @param CompareValue between Min_Data=0 and Max_Data=65535
2527 * @retval None
2528 */
2529 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2530 {
2531 WRITE_REG(TIMx->CCR2, CompareValue);
2532 }
2533
2534 /**
2535 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2536 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2537 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2538 * whether or not a timer instance supports a 32 bits counter.
2539 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2540 * output channel is supported by a timer instance.
2541 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2542 * @param TIMx Timer instance
2543 * @param CompareValue between Min_Data=0 and Max_Data=65535
2544 * @retval None
2545 */
2546 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2547 {
2548 WRITE_REG(TIMx->CCR3, CompareValue);
2549 }
2550
2551 /**
2552 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2553 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2554 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2555 * whether or not a timer instance supports a 32 bits counter.
2556 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2557 * output channel 4 is supported by a timer instance.
2558 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2559 * @param TIMx Timer instance
2560 * @param CompareValue between Min_Data=0 and Max_Data=65535
2561 * @retval None
2562 */
2563 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2564 {
2565 WRITE_REG(TIMx->CCR4, CompareValue);
2566 }
2567
2568 /**
2569 * @brief Set compare value for output channel 5 (TIMx_CCR5).
2570 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2571 * output channel 5 is supported by a timer instance.
2572 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2573 * @param TIMx Timer instance
2574 * @param CompareValue between Min_Data=0 and Max_Data=65535
2575 * @retval None
2576 */
2577 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
2578 {
2579 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
2580 }
2581
2582 /**
2583 * @brief Set compare value for output channel 6 (TIMx_CCR6).
2584 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2585 * output channel 6 is supported by a timer instance.
2586 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2587 * @param TIMx Timer instance
2588 * @param CompareValue between Min_Data=0 and Max_Data=65535
2589 * @retval None
2590 */
2591 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
2592 {
2593 WRITE_REG(TIMx->CCR6, CompareValue);
2594 }
2595
2596 /**
2597 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2598 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2599 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2600 * whether or not a timer instance supports a 32 bits counter.
2601 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2602 * output channel 1 is supported by a timer instance.
2603 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2604 * @param TIMx Timer instance
2605 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2606 */
2607 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
2608 {
2609 return (uint32_t)(READ_REG(TIMx->CCR1));
2610 }
2611
2612 /**
2613 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2614 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2615 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2616 * whether or not a timer instance supports a 32 bits counter.
2617 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2618 * output channel 2 is supported by a timer instance.
2619 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2620 * @param TIMx Timer instance
2621 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2622 */
2623 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
2624 {
2625 return (uint32_t)(READ_REG(TIMx->CCR2));
2626 }
2627
2628 /**
2629 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2630 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2631 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2632 * whether or not a timer instance supports a 32 bits counter.
2633 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2634 * output channel 3 is supported by a timer instance.
2635 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2636 * @param TIMx Timer instance
2637 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2638 */
2639 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
2640 {
2641 return (uint32_t)(READ_REG(TIMx->CCR3));
2642 }
2643
2644 /**
2645 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2646 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2647 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2648 * whether or not a timer instance supports a 32 bits counter.
2649 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2650 * output channel 4 is supported by a timer instance.
2651 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2652 * @param TIMx Timer instance
2653 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2654 */
2655 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
2656 {
2657 return (uint32_t)(READ_REG(TIMx->CCR4));
2658 }
2659
2660 /**
2661 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
2662 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2663 * output channel 5 is supported by a timer instance.
2664 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2665 * @param TIMx Timer instance
2666 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2667 */
2668 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
2669 {
2670 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
2671 }
2672
2673 /**
2674 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
2675 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2676 * output channel 6 is supported by a timer instance.
2677 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2678 * @param TIMx Timer instance
2679 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2680 */
2681 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
2682 {
2683 return (uint32_t)(READ_REG(TIMx->CCR6));
2684 }
2685
2686 /**
2687 * @brief Select on which reference signal the OC5REF is combined to.
2688 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
2689 * whether or not a timer instance supports the combined 3-phase PWM mode.
2690 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2691 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2692 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2693 * @param TIMx Timer instance
2694 * @param GroupCH5 This parameter can be a combination of the following values:
2695 * @arg @ref LL_TIM_GROUPCH5_NONE
2696 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
2697 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
2698 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
2699 * @retval None
2700 */
2701 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
2702 {
2703 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
2704 }
2705
2706 /**
2707 * @}
2708 */
2709
2710 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2711 * @{
2712 */
2713 /**
2714 * @brief Configure input channel.
2715 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2716 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2717 * CCMR1 IC1F LL_TIM_IC_Config\n
2718 * CCMR1 CC2S LL_TIM_IC_Config\n
2719 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2720 * CCMR1 IC2F LL_TIM_IC_Config\n
2721 * CCMR2 CC3S LL_TIM_IC_Config\n
2722 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2723 * CCMR2 IC3F LL_TIM_IC_Config\n
2724 * CCMR2 CC4S LL_TIM_IC_Config\n
2725 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2726 * CCMR2 IC4F LL_TIM_IC_Config\n
2727 * CCER CC1P LL_TIM_IC_Config\n
2728 * CCER CC1NP LL_TIM_IC_Config\n
2729 * CCER CC2P LL_TIM_IC_Config\n
2730 * CCER CC2NP LL_TIM_IC_Config\n
2731 * CCER CC3P LL_TIM_IC_Config\n
2732 * CCER CC3NP LL_TIM_IC_Config\n
2733 * CCER CC4P LL_TIM_IC_Config\n
2734 * CCER CC4NP LL_TIM_IC_Config
2735 * @param TIMx Timer instance
2736 * @param Channel This parameter can be one of the following values:
2737 * @arg @ref LL_TIM_CHANNEL_CH1
2738 * @arg @ref LL_TIM_CHANNEL_CH2
2739 * @arg @ref LL_TIM_CHANNEL_CH3
2740 * @arg @ref LL_TIM_CHANNEL_CH4
2741 * @param Configuration This parameter must be a combination of all the following values:
2742 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2743 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2744 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2745 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2746 * @retval None
2747 */
2748 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2749 {
2750 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2751 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2752 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2753 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
2754 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2755 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2756 }
2757
2758 /**
2759 * @brief Set the active input.
2760 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2761 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2762 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2763 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2764 * @param TIMx Timer instance
2765 * @param Channel This parameter can be one of the following values:
2766 * @arg @ref LL_TIM_CHANNEL_CH1
2767 * @arg @ref LL_TIM_CHANNEL_CH2
2768 * @arg @ref LL_TIM_CHANNEL_CH3
2769 * @arg @ref LL_TIM_CHANNEL_CH4
2770 * @param ICActiveInput This parameter can be one of the following values:
2771 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2772 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2773 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2774 * @retval None
2775 */
2776 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2777 {
2778 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2779 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2780 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2781 }
2782
2783 /**
2784 * @brief Get the current active input.
2785 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2786 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2787 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2788 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2789 * @param TIMx Timer instance
2790 * @param Channel This parameter can be one of the following values:
2791 * @arg @ref LL_TIM_CHANNEL_CH1
2792 * @arg @ref LL_TIM_CHANNEL_CH2
2793 * @arg @ref LL_TIM_CHANNEL_CH3
2794 * @arg @ref LL_TIM_CHANNEL_CH4
2795 * @retval Returned value can be one of the following values:
2796 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2797 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2798 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2799 */
2800 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
2801 {
2802 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2803 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2804 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2805 }
2806
2807 /**
2808 * @brief Set the prescaler of input channel.
2809 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2810 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2811 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2812 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2813 * @param TIMx Timer instance
2814 * @param Channel This parameter can be one of the following values:
2815 * @arg @ref LL_TIM_CHANNEL_CH1
2816 * @arg @ref LL_TIM_CHANNEL_CH2
2817 * @arg @ref LL_TIM_CHANNEL_CH3
2818 * @arg @ref LL_TIM_CHANNEL_CH4
2819 * @param ICPrescaler This parameter can be one of the following values:
2820 * @arg @ref LL_TIM_ICPSC_DIV1
2821 * @arg @ref LL_TIM_ICPSC_DIV2
2822 * @arg @ref LL_TIM_ICPSC_DIV4
2823 * @arg @ref LL_TIM_ICPSC_DIV8
2824 * @retval None
2825 */
2826 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
2827 {
2828 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2829 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2830 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2831 }
2832
2833 /**
2834 * @brief Get the current prescaler value acting on an input channel.
2835 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
2836 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
2837 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
2838 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
2839 * @param TIMx Timer instance
2840 * @param Channel This parameter can be one of the following values:
2841 * @arg @ref LL_TIM_CHANNEL_CH1
2842 * @arg @ref LL_TIM_CHANNEL_CH2
2843 * @arg @ref LL_TIM_CHANNEL_CH3
2844 * @arg @ref LL_TIM_CHANNEL_CH4
2845 * @retval Returned value can be one of the following values:
2846 * @arg @ref LL_TIM_ICPSC_DIV1
2847 * @arg @ref LL_TIM_ICPSC_DIV2
2848 * @arg @ref LL_TIM_ICPSC_DIV4
2849 * @arg @ref LL_TIM_ICPSC_DIV8
2850 */
2851 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
2852 {
2853 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2854 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2855 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2856 }
2857
2858 /**
2859 * @brief Set the input filter duration.
2860 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
2861 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
2862 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
2863 * CCMR2 IC4F LL_TIM_IC_SetFilter
2864 * @param TIMx Timer instance
2865 * @param Channel This parameter can be one of the following values:
2866 * @arg @ref LL_TIM_CHANNEL_CH1
2867 * @arg @ref LL_TIM_CHANNEL_CH2
2868 * @arg @ref LL_TIM_CHANNEL_CH3
2869 * @arg @ref LL_TIM_CHANNEL_CH4
2870 * @param ICFilter This parameter can be one of the following values:
2871 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2872 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2873 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2874 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2875 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2876 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2877 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2878 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2879 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2880 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2881 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2882 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2883 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2884 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2885 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2886 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2887 * @retval None
2888 */
2889 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
2890 {
2891 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2892 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2893 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2894 }
2895
2896 /**
2897 * @brief Get the input filter duration.
2898 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
2899 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
2900 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
2901 * CCMR2 IC4F LL_TIM_IC_GetFilter
2902 * @param TIMx Timer instance
2903 * @param Channel This parameter can be one of the following values:
2904 * @arg @ref LL_TIM_CHANNEL_CH1
2905 * @arg @ref LL_TIM_CHANNEL_CH2
2906 * @arg @ref LL_TIM_CHANNEL_CH3
2907 * @arg @ref LL_TIM_CHANNEL_CH4
2908 * @retval Returned value can be one of the following values:
2909 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2910 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2911 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2912 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2913 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2914 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2915 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2916 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2917 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2918 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2919 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2920 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2921 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2922 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2923 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2924 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2925 */
2926 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
2927 {
2928 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2929 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2930 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2931 }
2932
2933 /**
2934 * @brief Set the input channel polarity.
2935 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
2936 * CCER CC1NP LL_TIM_IC_SetPolarity\n
2937 * CCER CC2P LL_TIM_IC_SetPolarity\n
2938 * CCER CC2NP LL_TIM_IC_SetPolarity\n
2939 * CCER CC3P LL_TIM_IC_SetPolarity\n
2940 * CCER CC3NP LL_TIM_IC_SetPolarity\n
2941 * CCER CC4P LL_TIM_IC_SetPolarity\n
2942 * CCER CC4NP LL_TIM_IC_SetPolarity
2943 * @param TIMx Timer instance
2944 * @param Channel This parameter can be one of the following values:
2945 * @arg @ref LL_TIM_CHANNEL_CH1
2946 * @arg @ref LL_TIM_CHANNEL_CH2
2947 * @arg @ref LL_TIM_CHANNEL_CH3
2948 * @arg @ref LL_TIM_CHANNEL_CH4
2949 * @param ICPolarity This parameter can be one of the following values:
2950 * @arg @ref LL_TIM_IC_POLARITY_RISING
2951 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2952 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2953 * @retval None
2954 */
2955 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
2956 {
2957 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2958 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2959 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
2960 }
2961
2962 /**
2963 * @brief Get the current input channel polarity.
2964 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
2965 * CCER CC1NP LL_TIM_IC_GetPolarity\n
2966 * CCER CC2P LL_TIM_IC_GetPolarity\n
2967 * CCER CC2NP LL_TIM_IC_GetPolarity\n
2968 * CCER CC3P LL_TIM_IC_GetPolarity\n
2969 * CCER CC3NP LL_TIM_IC_GetPolarity\n
2970 * CCER CC4P LL_TIM_IC_GetPolarity\n
2971 * CCER CC4NP LL_TIM_IC_GetPolarity
2972 * @param TIMx Timer instance
2973 * @param Channel This parameter can be one of the following values:
2974 * @arg @ref LL_TIM_CHANNEL_CH1
2975 * @arg @ref LL_TIM_CHANNEL_CH2
2976 * @arg @ref LL_TIM_CHANNEL_CH3
2977 * @arg @ref LL_TIM_CHANNEL_CH4
2978 * @retval Returned value can be one of the following values:
2979 * @arg @ref LL_TIM_IC_POLARITY_RISING
2980 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2981 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2982 */
2983 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
2984 {
2985 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2986 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
2987 SHIFT_TAB_CCxP[iChannel]);
2988 }
2989
2990 /**
2991 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
2992 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2993 * a timer instance provides an XOR input.
2994 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
2995 * @param TIMx Timer instance
2996 * @retval None
2997 */
2998 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
2999 {
3000 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
3001 }
3002
3003 /**
3004 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3005 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3006 * a timer instance provides an XOR input.
3007 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3008 * @param TIMx Timer instance
3009 * @retval None
3010 */
3011 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3012 {
3013 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3014 }
3015
3016 /**
3017 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3018 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3019 * a timer instance provides an XOR input.
3020 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3021 * @param TIMx Timer instance
3022 * @retval State of bit (1 or 0).
3023 */
3024 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
3025 {
3026 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3027 }
3028
3029 /**
3030 * @brief Get captured value for input channel 1.
3031 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3032 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3033 * whether or not a timer instance supports a 32 bits counter.
3034 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3035 * input channel 1 is supported by a timer instance.
3036 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3037 * @param TIMx Timer instance
3038 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3039 */
3040 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
3041 {
3042 return (uint32_t)(READ_REG(TIMx->CCR1));
3043 }
3044
3045 /**
3046 * @brief Get captured value for input channel 2.
3047 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3048 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3049 * whether or not a timer instance supports a 32 bits counter.
3050 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3051 * input channel 2 is supported by a timer instance.
3052 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3053 * @param TIMx Timer instance
3054 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3055 */
3056 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
3057 {
3058 return (uint32_t)(READ_REG(TIMx->CCR2));
3059 }
3060
3061 /**
3062 * @brief Get captured value for input channel 3.
3063 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3064 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3065 * whether or not a timer instance supports a 32 bits counter.
3066 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3067 * input channel 3 is supported by a timer instance.
3068 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3069 * @param TIMx Timer instance
3070 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3071 */
3072 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
3073 {
3074 return (uint32_t)(READ_REG(TIMx->CCR3));
3075 }
3076
3077 /**
3078 * @brief Get captured value for input channel 4.
3079 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3080 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3081 * whether or not a timer instance supports a 32 bits counter.
3082 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3083 * input channel 4 is supported by a timer instance.
3084 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3085 * @param TIMx Timer instance
3086 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3087 */
3088 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
3089 {
3090 return (uint32_t)(READ_REG(TIMx->CCR4));
3091 }
3092
3093 /**
3094 * @}
3095 */
3096
3097 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3098 * @{
3099 */
3100 /**
3101 * @brief Enable external clock mode 2.
3102 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3103 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3104 * whether or not a timer instance supports external clock mode2.
3105 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3106 * @param TIMx Timer instance
3107 * @retval None
3108 */
3109 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3110 {
3111 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3112 }
3113
3114 /**
3115 * @brief Disable external clock mode 2.
3116 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3117 * whether or not a timer instance supports external clock mode2.
3118 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3119 * @param TIMx Timer instance
3120 * @retval None
3121 */
3122 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3123 {
3124 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3125 }
3126
3127 /**
3128 * @brief Indicate whether external clock mode 2 is enabled.
3129 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3130 * whether or not a timer instance supports external clock mode2.
3131 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3132 * @param TIMx Timer instance
3133 * @retval State of bit (1 or 0).
3134 */
3135 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
3136 {
3137 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3138 }
3139
3140 /**
3141 * @brief Set the clock source of the counter clock.
3142 * @note when selected clock source is external clock mode 1, the timer input
3143 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3144 * function. This timer input must be configured by calling
3145 * the @ref LL_TIM_IC_Config() function.
3146 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3147 * whether or not a timer instance supports external clock mode1.
3148 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3149 * whether or not a timer instance supports external clock mode2.
3150 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3151 * SMCR ECE LL_TIM_SetClockSource
3152 * @param TIMx Timer instance
3153 * @param ClockSource This parameter can be one of the following values:
3154 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3155 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3156 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3157 * @retval None
3158 */
3159 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3160 {
3161 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3162 }
3163
3164 /**
3165 * @brief Set the encoder interface mode.
3166 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3167 * whether or not a timer instance supports the encoder mode.
3168 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3169 * @param TIMx Timer instance
3170 * @param EncoderMode This parameter can be one of the following values:
3171 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3172 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3173 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3174 * @retval None
3175 */
3176 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3177 {
3178 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3179 }
3180
3181 /**
3182 * @}
3183 */
3184
3185 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3186 * @{
3187 */
3188 /**
3189 * @brief Set the trigger output (TRGO) used for timer synchronization .
3190 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3191 * whether or not a timer instance can operate as a master timer.
3192 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3193 * @param TIMx Timer instance
3194 * @param TimerSynchronization This parameter can be one of the following values:
3195 * @arg @ref LL_TIM_TRGO_RESET
3196 * @arg @ref LL_TIM_TRGO_ENABLE
3197 * @arg @ref LL_TIM_TRGO_UPDATE
3198 * @arg @ref LL_TIM_TRGO_CC1IF
3199 * @arg @ref LL_TIM_TRGO_OC1REF
3200 * @arg @ref LL_TIM_TRGO_OC2REF
3201 * @arg @ref LL_TIM_TRGO_OC3REF
3202 * @arg @ref LL_TIM_TRGO_OC4REF
3203 * @retval None
3204 */
3205 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3206 {
3207 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3208 }
3209
3210 /**
3211 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3212 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3213 * whether or not a timer instance can be used for ADC synchronization.
3214 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3215 * @param TIMx Timer Instance
3216 * @param ADCSynchronization This parameter can be one of the following values:
3217 * @arg @ref LL_TIM_TRGO2_RESET
3218 * @arg @ref LL_TIM_TRGO2_ENABLE
3219 * @arg @ref LL_TIM_TRGO2_UPDATE
3220 * @arg @ref LL_TIM_TRGO2_CC1F
3221 * @arg @ref LL_TIM_TRGO2_OC1
3222 * @arg @ref LL_TIM_TRGO2_OC2
3223 * @arg @ref LL_TIM_TRGO2_OC3
3224 * @arg @ref LL_TIM_TRGO2_OC4
3225 * @arg @ref LL_TIM_TRGO2_OC5
3226 * @arg @ref LL_TIM_TRGO2_OC6
3227 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3228 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3229 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3230 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3231 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3232 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3233 * @retval None
3234 */
3235 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3236 {
3237 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3238 }
3239
3240 /**
3241 * @brief Set the synchronization mode of a slave timer.
3242 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3243 * a timer instance can operate as a slave timer.
3244 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3245 * @param TIMx Timer instance
3246 * @param SlaveMode This parameter can be one of the following values:
3247 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3248 * @arg @ref LL_TIM_SLAVEMODE_RESET
3249 * @arg @ref LL_TIM_SLAVEMODE_GATED
3250 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3251 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3252 * @retval None
3253 */
3254 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3255 {
3256 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3257 }
3258
3259 /**
3260 * @brief Set the selects the trigger input to be used to synchronize the counter.
3261 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3262 * a timer instance can operate as a slave timer.
3263 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3264 * @param TIMx Timer instance
3265 * @param TriggerInput This parameter can be one of the following values:
3266 * @arg @ref LL_TIM_TS_ITR0
3267 * @arg @ref LL_TIM_TS_ITR1
3268 * @arg @ref LL_TIM_TS_ITR2
3269 * @arg @ref LL_TIM_TS_ITR3
3270 * @arg @ref LL_TIM_TS_TI1F_ED
3271 * @arg @ref LL_TIM_TS_TI1FP1
3272 * @arg @ref LL_TIM_TS_TI2FP2
3273 * @arg @ref LL_TIM_TS_ETRF
3274 * @arg @ref LL_TIM_TS_ITR4
3275 * @arg @ref LL_TIM_TS_ITR5
3276 * @arg @ref LL_TIM_TS_ITR6
3277 * @arg @ref LL_TIM_TS_ITR7
3278 * @arg @ref LL_TIM_TS_ITR8 (*)
3279 * @arg @ref LL_TIM_TS_ITR9 (*)
3280 * @arg @ref LL_TIM_TS_ITR10 (*)
3281 * @arg @ref LL_TIM_TS_ITR11 (*)
3282 * @arg @ref LL_TIM_TS_ITR12 (*)
3283 * @arg @ref LL_TIM_TS_ITR13 (*)
3284 *
3285 * (*) Value not defined in all devices.
3286 * @retval None
3287 */
3288 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3289 {
3290 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3291 }
3292
3293 /**
3294 * @brief Enable the Master/Slave mode.
3295 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3296 * a timer instance can operate as a slave timer.
3297 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3298 * @param TIMx Timer instance
3299 * @retval None
3300 */
3301 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3302 {
3303 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3304 }
3305
3306 /**
3307 * @brief Disable the Master/Slave mode.
3308 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3309 * a timer instance can operate as a slave timer.
3310 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3311 * @param TIMx Timer instance
3312 * @retval None
3313 */
3314 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3315 {
3316 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3317 }
3318
3319 /**
3320 * @brief Indicates whether the Master/Slave mode is enabled.
3321 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3322 * a timer instance can operate as a slave timer.
3323 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3324 * @param TIMx Timer instance
3325 * @retval State of bit (1 or 0).
3326 */
3327 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
3328 {
3329 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
3330 }
3331
3332 /**
3333 * @brief Configure the external trigger (ETR) input.
3334 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3335 * a timer instance provides an external trigger input.
3336 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3337 * SMCR ETPS LL_TIM_ConfigETR\n
3338 * SMCR ETF LL_TIM_ConfigETR
3339 * @param TIMx Timer instance
3340 * @param ETRPolarity This parameter can be one of the following values:
3341 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3342 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3343 * @param ETRPrescaler This parameter can be one of the following values:
3344 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3345 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3346 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3347 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3348 * @param ETRFilter This parameter can be one of the following values:
3349 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
3350 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3351 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3352 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3353 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3354 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3355 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3356 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3357 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3358 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3359 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3360 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3361 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3362 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3363 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3364 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3365 * @retval None
3366 */
3367 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3368 uint32_t ETRFilter)
3369 {
3370 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
3371 }
3372
3373 /**
3374 * @brief Select the external trigger (ETR) input source.
3375 * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
3376 * not a timer instance supports ETR source selection.
3377 * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
3378 * @param TIMx Timer instance
3379 * @param ETRSource This parameter can be one of the following values:
3380 * For TIM1, the parameter is one of the following values:
3381 * @arg LL_TIM_TIM1_ETRSOURCE_GPIO: TIM1_ETR is connected to GPIO
3382 * @arg LL_TIM_TIM1_ETRSOURCE_COMP1: TIM1_ETR is connected to COMP1 output
3383 * @arg LL_TIM_TIM1_ETRSOURCE_COMP2: TIM1_ETR is connected to COMP2 output
3384 * @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
3385 * @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
3386 * @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
3387 * @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1
3388 * @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2
3389 * @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3
3390 *
3391 * For TIM2, the parameter is one of the following values:
3392 * @arg LL_TIM_TIM2_ETRSOURCE_GPIO: TIM2_ETR is connected to GPIO
3393 * @arg LL_TIM_TIM2_ETRSOURCE_COMP1: TIM2_ETR is connected to COMP1 output
3394 * @arg LL_TIM_TIM2_ETRSOURCE_COMP2: TIM2_ETR is connected to COMP2 output
3395 * @arg LL_TIM_TIM2_ETRSOURCE_LSE: TIM2_ETR is connected to LSE
3396 * @arg LL_TIM_TIM2_ETRSOURCE_SAI1_FSA: TIM2_ETR is connected to SAI1 FS_A
3397 * @arg LL_TIM_TIM2_ETRSOURCE_SAI1_FSB: TIM2_ETR is connected to SAI1 FS_B
3398 *
3399 * For TIM3, the parameter is one of the following values:
3400 * @arg LL_TIM_TIM3_ETRSOURCE_GPIO: TIM3_ETR is connected to GPIO
3401 * @arg LL_TIM_TIM3_ETRSOURCE_COMP1: TIM3_ETR is connected to COMP1 output
3402 *
3403 * For TIM5, the parameter is one of the following values:
3404 * @arg LL_TIM_TIM5_ETRSOURCE_GPIO: TIM5_ETR is connected to GPIO
3405 * @arg LL_TIM_TIM5_ETRSOURCE_SAI2_FSA: TIM5_ETR is connected to SAI2 FS_A (*)
3406 * @arg LL_TIM_TIM5_ETRSOURCE_SAI2_FSB: TIM5_ETR is connected to SAI2 FS_B (*)
3407 * @arg LL_TIM_TIM5_ETRSOURCE_SAI4_FSA: TIM5_ETR is connected to SAI2 FS_A (*)
3408 * @arg LL_TIM_TIM5_ETRSOURCE_SAI4_FSB: TIM5_ETR is connected to SAI2 FS_B (*)
3409 *
3410 * For TIM8, the parameter is one of the following values:
3411 * @arg LL_TIM_TIM8_ETRSOURCE_GPIO: TIM8_ETR is connected to GPIO
3412 * @arg LL_TIM_TIM8_ETRSOURCE_COMP1: TIM8_ETR is connected to COMP1 output
3413 * @arg LL_TIM_TIM8_ETRSOURCE_COMP2: TIM8_ETR is connected to COMP2 output
3414 * @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
3415 * @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
3416 * @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3
3417 * @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
3418 * @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
3419 * @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
3420 *
3421 * For TIM23, the parameter is one of the following values: (*)
3422 * @arg LL_TIM_TIM23_ETRSOURCE_GPIO TIM23_ETR is connected to GPIO
3423 * @arg LL_TIM_TIM23_ETRSOURCE_COMP1 TIM23_ETR is connected to COMP1 output
3424 * @arg LL_TIM_TIM23_ETRSOURCE_COMP2 TIM23_ETR is connected to COMP2 output
3425 *
3426 * For TIM24, the parameter is one of the following values: (*)
3427 * @arg LL_TIM_TIM24_ETRSOURCE_GPIO TIM24_ETR is connected to GPIO
3428 * @arg LL_TIM_TIM24_ETRSOURCE_SAI4_FSA TIM24_ETR is connected to SAI4 FS_A
3429 * @arg LL_TIM_TIM24_ETRSOURCE_SAI4_FSB TIM24_ETR is connected to SAI4 FS_B
3430 * @arg LL_TIM_TIM24_ETRSOURCE_SAI1_FSA TIM24_ETR is connected to SAI1 FS_A
3431 * @arg LL_TIM_TIM24_ETRSOURCE_SAI1_FSB TIM24_ETR is connected to SAI1 FS_B
3432 *
3433 * (*) Value not defined in all devices.
3434 * @retval None
3435 */
3436 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
3437 {
3438
3439 MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
3440 }
3441
3442 /**
3443 * @}
3444 */
3445
3446 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
3447 * @{
3448 */
3449 /**
3450 * @brief Enable the break function.
3451 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3452 * a timer instance provides a break input.
3453 * @rmtoll BDTR BKE LL_TIM_EnableBRK
3454 * @param TIMx Timer instance
3455 * @retval None
3456 */
3457 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
3458 {
3459 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3460 }
3461
3462 /**
3463 * @brief Disable the break function.
3464 * @rmtoll BDTR BKE LL_TIM_DisableBRK
3465 * @param TIMx Timer instance
3466 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3467 * a timer instance provides a break input.
3468 * @retval None
3469 */
3470 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
3471 {
3472 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3473 }
3474
3475 /**
3476 * @brief Configure the break input.
3477 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3478 * a timer instance provides a break input.
3479 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
3480 * BDTR BKF LL_TIM_ConfigBRK
3481 * @param TIMx Timer instance
3482 * @param BreakPolarity This parameter can be one of the following values:
3483 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
3484 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3485 * @param BreakFilter This parameter can be one of the following values:
3486 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
3487 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
3488 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
3489 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
3490 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
3491 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
3492 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
3493 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
3494 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
3495 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
3496 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
3497 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
3498 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
3499 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
3500 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
3501 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
3502 * @retval None
3503 */
3504 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,
3505 uint32_t BreakFilter)
3506 {
3507 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
3508 }
3509
3510 /**
3511 * @brief Enable the break 2 function.
3512 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3513 * a timer instance provides a second break input.
3514 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
3515 * @param TIMx Timer instance
3516 * @retval None
3517 */
3518 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
3519 {
3520 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3521 }
3522
3523 /**
3524 * @brief Disable the break 2 function.
3525 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3526 * a timer instance provides a second break input.
3527 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
3528 * @param TIMx Timer instance
3529 * @retval None
3530 */
3531 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
3532 {
3533 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3534 }
3535
3536 /**
3537 * @brief Configure the break 2 input.
3538 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3539 * a timer instance provides a second break input.
3540 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
3541 * BDTR BK2F LL_TIM_ConfigBRK2
3542 * @param TIMx Timer instance
3543 * @param Break2Polarity This parameter can be one of the following values:
3544 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
3545 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
3546 * @param Break2Filter This parameter can be one of the following values:
3547 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
3548 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
3549 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
3550 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
3551 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
3552 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
3553 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
3554 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
3555 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
3556 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
3557 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
3558 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
3559 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
3560 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
3561 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
3562 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
3563 * @retval None
3564 */
3565 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
3566 {
3567 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
3568 }
3569
3570 /**
3571 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
3572 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3573 * a timer instance provides a break input.
3574 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
3575 * BDTR OSSR LL_TIM_SetOffStates
3576 * @param TIMx Timer instance
3577 * @param OffStateIdle This parameter can be one of the following values:
3578 * @arg @ref LL_TIM_OSSI_DISABLE
3579 * @arg @ref LL_TIM_OSSI_ENABLE
3580 * @param OffStateRun This parameter can be one of the following values:
3581 * @arg @ref LL_TIM_OSSR_DISABLE
3582 * @arg @ref LL_TIM_OSSR_ENABLE
3583 * @retval None
3584 */
3585 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
3586 {
3587 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
3588 }
3589
3590 /**
3591 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
3592 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3593 * a timer instance provides a break input.
3594 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
3595 * @param TIMx Timer instance
3596 * @retval None
3597 */
3598 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
3599 {
3600 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3601 }
3602
3603 /**
3604 * @brief Disable automatic output (MOE can be set only by software).
3605 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3606 * a timer instance provides a break input.
3607 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
3608 * @param TIMx Timer instance
3609 * @retval None
3610 */
3611 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
3612 {
3613 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3614 }
3615
3616 /**
3617 * @brief Indicate whether automatic output is enabled.
3618 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3619 * a timer instance provides a break input.
3620 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
3621 * @param TIMx Timer instance
3622 * @retval State of bit (1 or 0).
3623 */
3624 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
3625 {
3626 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
3627 }
3628
3629 /**
3630 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
3631 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3632 * software and is reset in case of break or break2 event
3633 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3634 * a timer instance provides a break input.
3635 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
3636 * @param TIMx Timer instance
3637 * @retval None
3638 */
3639 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
3640 {
3641 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3642 }
3643
3644 /**
3645 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
3646 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3647 * software and is reset in case of break or break2 event.
3648 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3649 * a timer instance provides a break input.
3650 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
3651 * @param TIMx Timer instance
3652 * @retval None
3653 */
3654 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
3655 {
3656 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3657 }
3658
3659 /**
3660 * @brief Indicates whether outputs are enabled.
3661 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3662 * a timer instance provides a break input.
3663 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
3664 * @param TIMx Timer instance
3665 * @retval State of bit (1 or 0).
3666 */
3667 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
3668 {
3669 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
3670 }
3671
3672 #if defined(TIM_BREAK_INPUT_SUPPORT)
3673 /**
3674 * @brief Enable the signals connected to the designated timer break input.
3675 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3676 * or not a timer instance allows for break input selection.
3677 * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
3678 * AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n
3679 * AF1 BKCMP2E LL_TIM_EnableBreakInputSource\n
3680 * AF1 BKDF1BK0E LL_TIM_EnableBreakInputSource\n
3681 * AF2 BK2INE LL_TIM_EnableBreakInputSource\n
3682 * AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n
3683 * AF2 BK2CMP2E LL_TIM_EnableBreakInputSource\n
3684 * AF2 BK2DF1BK1E LL_TIM_EnableBreakInputSource
3685 * @param TIMx Timer instance
3686 * @param BreakInput This parameter can be one of the following values:
3687 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3688 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3689 * @param Source This parameter can be one of the following values:
3690 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3691 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3692 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3693 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
3694 * @retval None
3695 */
3696 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3697 {
3698 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3699 SET_BIT(*pReg, Source);
3700 }
3701
3702 /**
3703 * @brief Disable the signals connected to the designated timer break input.
3704 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3705 * or not a timer instance allows for break input selection.
3706 * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
3707 * AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n
3708 * AF1 BKCMP2E LL_TIM_DisableBreakInputSource\n
3709 * AF1 BKDF1BK0E LL_TIM_DisableBreakInputSource\n
3710 * AF2 BK2INE LL_TIM_DisableBreakInputSource\n
3711 * AF2 BK2CMP1E LL_TIM_DisableBreakInputSource\n
3712 * AF2 BK2CMP2E LL_TIM_DisableBreakInputSource\n
3713 * AF2 BK2DF1BK1E LL_TIM_DisableBreakInputSource
3714 * @param TIMx Timer instance
3715 * @param BreakInput This parameter can be one of the following values:
3716 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3717 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3718 * @param Source This parameter can be one of the following values:
3719 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3720 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3721 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3722 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
3723 * @retval None
3724 */
3725 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3726 {
3727 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3728 CLEAR_BIT(*pReg, Source);
3729 }
3730
3731 /**
3732 * @brief Set the polarity of the break signal for the timer break input.
3733 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3734 * or not a timer instance allows for break input selection.
3735 * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
3736 * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
3737 * AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
3738 * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
3739 * AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
3740 * AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity
3741 * @param TIMx Timer instance
3742 * @param BreakInput This parameter can be one of the following values:
3743 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3744 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3745 * @param Source This parameter can be one of the following values:
3746 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3747 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3748 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3749 * @param Polarity This parameter can be one of the following values:
3750 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
3751 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
3752 * @retval None
3753 */
3754 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
3755 uint32_t Polarity)
3756 {
3757 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3758 MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
3759 }
3760 #endif /* TIM_BREAK_INPUT_SUPPORT */
3761 /**
3762 * @}
3763 */
3764
3765 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
3766 * @{
3767 */
3768 /**
3769 * @brief Configures the timer DMA burst feature.
3770 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
3771 * not a timer instance supports the DMA burst mode.
3772 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
3773 * DCR DBA LL_TIM_ConfigDMABurst
3774 * @param TIMx Timer instance
3775 * @param DMABurstBaseAddress This parameter can be one of the following values:
3776 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
3777 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
3778 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
3779 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
3780 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
3781 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
3782 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
3783 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
3784 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
3785 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
3786 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
3787 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
3788 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
3789 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
3790 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
3791 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
3792 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
3793 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
3794 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
3795 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
3796 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
3797 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
3798 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
3799 * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
3800 *
3801 * @param DMABurstLength This parameter can be one of the following values:
3802 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
3803 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
3804 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
3805 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
3806 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
3807 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
3808 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
3809 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
3810 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
3811 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
3812 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
3813 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
3814 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
3815 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
3816 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
3817 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
3818 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
3819 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
3820 * @retval None
3821 */
3822 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
3823 {
3824 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
3825 }
3826
3827 /**
3828 * @}
3829 */
3830
3831 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
3832 * @{
3833 */
3834 /**
3835 * @brief Remap TIM inputs (input channel, internal/external triggers).
3836 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
3837 * a some timer inputs can be remapped.
3838 * TIM1: one of the following values:
3839 * @arg LL_TIM_TIM1_TI1_RMP_GPIO: TIM1 TI1 is connected to GPIO
3840 * @arg LL_TIM_TIM1_TI1_RMP_COMP1: TIM1 TI1 is connected to COMP1 output
3841 *
3842 * TIM2: one of the following values:
3843 * @arg LL_TIM_TIM2_TI4_RMP_GPIO: TIM2 TI4 is connected to GPIO
3844 * @arg LL_TIM_TIM2_TI4_RMP_COMP1: TIM2 TI4 is connected to COMP1 output
3845 * @arg LL_TIM_TIM2_TI4_RMP_COMP2: TIM2 TI4 is connected to COMP2 output
3846 * @arg LL_TIM_TIM2_TI4_RMP_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
3847 *
3848 * TIM3: one of the following values:
3849 * @arg LL_TIM_TIM3_TI1_RMP_GPIO: TIM3 TI1 is connected to GPIO
3850 * @arg LL_TIM_TIM3_TI1_RMP_COMP1: TIM3 TI1 is connected to COMP1 output
3851 * @arg LL_TIM_TIM3_TI1_RMP_COMP2: TIM3 TI1 is connected to COMP2 output
3852 * @arg LL_TIM_TIM3_TI1_RMP_COMP1_COMP2: TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output
3853 *
3854 * TIM5: one of the following values:
3855 * @arg LL_TIM_TIM5_TI1_RMP_GPIO: TIM5 TI1 is connected to GPIO
3856 * @arg LL_TIM_TIM5_TI1_RMP_CAN_TMP: TIM5 TI1 is connected to CAN TMP
3857 * @arg LL_TIM_TIM5_TI1_RMP_CAN_RTP: TIM5 TI1 is connected to CAN RTP
3858 *
3859 * TIM8: one of the following values:
3860 * @arg LL_TIM_TIM8_TI1_RMP_GPIO: TIM8 TI1 is connected to GPIO
3861 * @arg LL_TIM_TIM8_TI1_RMP_COMP2: TIM8 TI1 is connected to COMP2 output
3862 *
3863 * TIM12: one of the following values: (*)
3864 * @arg LL_TIM_TIM12_TI1_RMP_GPIO: TIM12 TI1 is connected to GPIO
3865 * @arg LL_TIM_TIM12_TI1_RMP_SPDIF_FS: TIM12 TI1 is connected to SPDIF FS
3866 *
3867 * TIM15: one of the following values:
3868 * @arg LL_TIM_TIM15_TI1_RMP_GPIO: TIM15 TI1 is connected to GPIO
3869 * @arg LL_TIM_TIM15_TI1_RMP_TIM2: TIM15 TI1 is connected to TIM2 CH1
3870 * @arg LL_TIM_TIM15_TI1_RMP_TIM3: TIM15 TI1 is connected to TIM3 CH1
3871 * @arg LL_TIM_TIM15_TI1_RMP_TIM4: TIM15 TI1 is connected to TIM4 CH1
3872 * @arg LL_TIM_TIM15_TI1_RMP_LSE: TIM15 TI1 is connected to LSE
3873 * @arg LL_TIM_TIM15_TI1_RMP_CSI: TIM15 TI1 is connected to CSI
3874 * @arg LL_TIM_TIM15_TI1_RMP_MCO2: TIM15 TI1 is connected to MCO2
3875 * @arg LL_TIM_TIM15_TI2_RMP_GPIO: TIM15 TI2 is connected to GPIO
3876 * @arg LL_TIM_TIM15_TI2_RMP_TIM2: TIM15 TI2 is connected to TIM2 CH2
3877 * @arg LL_TIM_TIM15_TI2_RMP_TIM3: TIM15 TI2 is connected to TIM3 CH2
3878 * @arg LL_TIM_TIM15_TI2_RMP_TIM4: TIM15 TI2 is connected to TIM4 CH2
3879 *
3880 * TIM16: one of the following values:
3881 * @arg LL_TIM_TIM16_TI1_RMP_GPIO: TIM16 TI1 is connected to GPIO
3882 * @arg LL_TIM_TIM16_TI1_RMP_LSI: TIM16 TI1 is connected to LSI
3883 * @arg LL_TIM_TIM16_TI1_RMP_LSE: TIM16 TI1 is connected to LSE
3884 * @arg LL_TIM_TIM16_TI1_RMP_RTC: TIM16 TI1 is connected to RTC wakeup interrupt
3885 *
3886 * TIM17: one of the following values:
3887 * @arg LL_TIM_TIM17_TI1_RMP_GPIO: TIM17 TI1 is connected to GPIO
3888 * @arg LL_TIM_TIM17_TI1_RMP_SPDIF_FS: TIM17 TI1 is connected to SPDIF FS (*)
3889 * @arg LL_TIM_TIM17_TI1_RMP_HSE_1MHZ: TIM17 TI1 is connected to HSE 1MHz
3890 * @arg LL_TIM_TIM17_TI1_RMP_MCO1: TIM17 TI1 is connected to MCO1
3891 *
3892 * TIM23: one of the following values: (*)
3893 * @arg LL_TIM_TIM23_TI4_RMP_GPIO TIM23_TI4 is connected to GPIO
3894 * @arg LL_TIM_TIM23_TI4_RMP_COMP1 TIM23_TI4 is connected to COMP1 output
3895 * @arg LL_TIM_TIM23_TI4_RMP_COMP2 TIM23_TI4 is connected to COMP2 output
3896 * @arg LL_TIM_TIM23_TI4_RMP_COMP1_COMP2 TIM23_TI4 is connected to COMP2 output
3897 *
3898 * TIM24: one of the following values: (*)
3899 * @arg LL_TIM_TIM24_TI1_RMP_GPIO TIM24_TI1 is connected to GPIO
3900 * @arg LL_TIM_TIM24_TI1_RMP_CAN_TMP TIM24_TI1 is connected to CAN_TMP
3901 * @arg LL_TIM_TIM24_TI1_RMP_CAN_RTP TIM24_TI1 is connected to CAN_RTP
3902 * @arg LL_TIM_TIM24_TI1_RMP_CAN_SOC TIM24_TI1 is connected to CAN_SOC
3903 *
3904 * (*) Value not defined in all devices. \n
3905 * @retval None
3906 */
3907 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
3908 {
3909 MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
3910 }
3911
3912 /**
3913 * @}
3914 */
3915
3916 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
3917 * @{
3918 */
3919 /**
3920 * @brief Clear the update interrupt flag (UIF).
3921 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
3922 * @param TIMx Timer instance
3923 * @retval None
3924 */
3925 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
3926 {
3927 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
3928 }
3929
3930 /**
3931 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
3932 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
3933 * @param TIMx Timer instance
3934 * @retval State of bit (1 or 0).
3935 */
3936 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
3937 {
3938 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
3939 }
3940
3941 /**
3942 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
3943 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
3944 * @param TIMx Timer instance
3945 * @retval None
3946 */
3947 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
3948 {
3949 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
3950 }
3951
3952 /**
3953 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
3954 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
3955 * @param TIMx Timer instance
3956 * @retval State of bit (1 or 0).
3957 */
3958 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
3959 {
3960 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
3961 }
3962
3963 /**
3964 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
3965 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
3966 * @param TIMx Timer instance
3967 * @retval None
3968 */
3969 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
3970 {
3971 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
3972 }
3973
3974 /**
3975 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
3976 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
3977 * @param TIMx Timer instance
3978 * @retval State of bit (1 or 0).
3979 */
3980 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
3981 {
3982 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
3983 }
3984
3985 /**
3986 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
3987 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
3988 * @param TIMx Timer instance
3989 * @retval None
3990 */
3991 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
3992 {
3993 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
3994 }
3995
3996 /**
3997 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
3998 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
3999 * @param TIMx Timer instance
4000 * @retval State of bit (1 or 0).
4001 */
4002 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
4003 {
4004 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
4005 }
4006
4007 /**
4008 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
4009 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
4010 * @param TIMx Timer instance
4011 * @retval None
4012 */
4013 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
4014 {
4015 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
4016 }
4017
4018 /**
4019 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
4020 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
4021 * @param TIMx Timer instance
4022 * @retval State of bit (1 or 0).
4023 */
4024 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
4025 {
4026 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
4027 }
4028
4029 /**
4030 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
4031 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
4032 * @param TIMx Timer instance
4033 * @retval None
4034 */
4035 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
4036 {
4037 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
4038 }
4039
4040 /**
4041 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
4042 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
4043 * @param TIMx Timer instance
4044 * @retval State of bit (1 or 0).
4045 */
4046 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
4047 {
4048 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
4049 }
4050
4051 /**
4052 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
4053 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
4054 * @param TIMx Timer instance
4055 * @retval None
4056 */
4057 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
4058 {
4059 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
4060 }
4061
4062 /**
4063 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
4064 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
4065 * @param TIMx Timer instance
4066 * @retval State of bit (1 or 0).
4067 */
4068 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
4069 {
4070 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
4071 }
4072
4073 /**
4074 * @brief Clear the commutation interrupt flag (COMIF).
4075 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
4076 * @param TIMx Timer instance
4077 * @retval None
4078 */
4079 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
4080 {
4081 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
4082 }
4083
4084 /**
4085 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
4086 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
4087 * @param TIMx Timer instance
4088 * @retval State of bit (1 or 0).
4089 */
4090 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
4091 {
4092 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
4093 }
4094
4095 /**
4096 * @brief Clear the trigger interrupt flag (TIF).
4097 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
4098 * @param TIMx Timer instance
4099 * @retval None
4100 */
4101 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
4102 {
4103 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
4104 }
4105
4106 /**
4107 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
4108 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
4109 * @param TIMx Timer instance
4110 * @retval State of bit (1 or 0).
4111 */
4112 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
4113 {
4114 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
4115 }
4116
4117 /**
4118 * @brief Clear the break interrupt flag (BIF).
4119 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
4120 * @param TIMx Timer instance
4121 * @retval None
4122 */
4123 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
4124 {
4125 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
4126 }
4127
4128 /**
4129 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
4130 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
4131 * @param TIMx Timer instance
4132 * @retval State of bit (1 or 0).
4133 */
4134 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
4135 {
4136 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
4137 }
4138
4139 /**
4140 * @brief Clear the break 2 interrupt flag (B2IF).
4141 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
4142 * @param TIMx Timer instance
4143 * @retval None
4144 */
4145 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
4146 {
4147 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
4148 }
4149
4150 /**
4151 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
4152 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
4153 * @param TIMx Timer instance
4154 * @retval State of bit (1 or 0).
4155 */
4156 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
4157 {
4158 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
4159 }
4160
4161 /**
4162 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
4163 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
4164 * @param TIMx Timer instance
4165 * @retval None
4166 */
4167 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
4168 {
4169 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
4170 }
4171
4172 /**
4173 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
4174 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
4175 * @param TIMx Timer instance
4176 * @retval State of bit (1 or 0).
4177 */
4178 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
4179 {
4180 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
4181 }
4182
4183 /**
4184 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
4185 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
4186 * @param TIMx Timer instance
4187 * @retval None
4188 */
4189 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
4190 {
4191 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
4192 }
4193
4194 /**
4195 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
4196 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
4197 * @param TIMx Timer instance
4198 * @retval State of bit (1 or 0).
4199 */
4200 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
4201 {
4202 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
4203 }
4204
4205 /**
4206 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
4207 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
4208 * @param TIMx Timer instance
4209 * @retval None
4210 */
4211 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
4212 {
4213 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
4214 }
4215
4216 /**
4217 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
4218 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
4219 * @param TIMx Timer instance
4220 * @retval State of bit (1 or 0).
4221 */
4222 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
4223 {
4224 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
4225 }
4226
4227 /**
4228 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
4229 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
4230 * @param TIMx Timer instance
4231 * @retval None
4232 */
4233 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
4234 {
4235 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
4236 }
4237
4238 /**
4239 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
4240 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
4241 * @param TIMx Timer instance
4242 * @retval State of bit (1 or 0).
4243 */
4244 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
4245 {
4246 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
4247 }
4248
4249 /**
4250 * @brief Clear the system break interrupt flag (SBIF).
4251 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
4252 * @param TIMx Timer instance
4253 * @retval None
4254 */
4255 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
4256 {
4257 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
4258 }
4259
4260 /**
4261 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
4262 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
4263 * @param TIMx Timer instance
4264 * @retval State of bit (1 or 0).
4265 */
4266 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)
4267 {
4268 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
4269 }
4270
4271 /**
4272 * @}
4273 */
4274
4275 /** @defgroup TIM_LL_EF_IT_Management IT-Management
4276 * @{
4277 */
4278 /**
4279 * @brief Enable update interrupt (UIE).
4280 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
4281 * @param TIMx Timer instance
4282 * @retval None
4283 */
4284 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
4285 {
4286 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
4287 }
4288
4289 /**
4290 * @brief Disable update interrupt (UIE).
4291 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
4292 * @param TIMx Timer instance
4293 * @retval None
4294 */
4295 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
4296 {
4297 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
4298 }
4299
4300 /**
4301 * @brief Indicates whether the update interrupt (UIE) is enabled.
4302 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
4303 * @param TIMx Timer instance
4304 * @retval State of bit (1 or 0).
4305 */
4306 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
4307 {
4308 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
4309 }
4310
4311 /**
4312 * @brief Enable capture/compare 1 interrupt (CC1IE).
4313 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
4314 * @param TIMx Timer instance
4315 * @retval None
4316 */
4317 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
4318 {
4319 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4320 }
4321
4322 /**
4323 * @brief Disable capture/compare 1 interrupt (CC1IE).
4324 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
4325 * @param TIMx Timer instance
4326 * @retval None
4327 */
4328 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
4329 {
4330 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4331 }
4332
4333 /**
4334 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
4335 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
4336 * @param TIMx Timer instance
4337 * @retval State of bit (1 or 0).
4338 */
4339 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
4340 {
4341 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
4342 }
4343
4344 /**
4345 * @brief Enable capture/compare 2 interrupt (CC2IE).
4346 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
4347 * @param TIMx Timer instance
4348 * @retval None
4349 */
4350 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
4351 {
4352 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4353 }
4354
4355 /**
4356 * @brief Disable capture/compare 2 interrupt (CC2IE).
4357 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
4358 * @param TIMx Timer instance
4359 * @retval None
4360 */
4361 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
4362 {
4363 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4364 }
4365
4366 /**
4367 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
4368 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
4369 * @param TIMx Timer instance
4370 * @retval State of bit (1 or 0).
4371 */
4372 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
4373 {
4374 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
4375 }
4376
4377 /**
4378 * @brief Enable capture/compare 3 interrupt (CC3IE).
4379 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
4380 * @param TIMx Timer instance
4381 * @retval None
4382 */
4383 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
4384 {
4385 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4386 }
4387
4388 /**
4389 * @brief Disable capture/compare 3 interrupt (CC3IE).
4390 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
4391 * @param TIMx Timer instance
4392 * @retval None
4393 */
4394 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
4395 {
4396 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4397 }
4398
4399 /**
4400 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
4401 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
4402 * @param TIMx Timer instance
4403 * @retval State of bit (1 or 0).
4404 */
4405 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
4406 {
4407 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
4408 }
4409
4410 /**
4411 * @brief Enable capture/compare 4 interrupt (CC4IE).
4412 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
4413 * @param TIMx Timer instance
4414 * @retval None
4415 */
4416 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
4417 {
4418 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4419 }
4420
4421 /**
4422 * @brief Disable capture/compare 4 interrupt (CC4IE).
4423 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
4424 * @param TIMx Timer instance
4425 * @retval None
4426 */
4427 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
4428 {
4429 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4430 }
4431
4432 /**
4433 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
4434 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
4435 * @param TIMx Timer instance
4436 * @retval State of bit (1 or 0).
4437 */
4438 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
4439 {
4440 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
4441 }
4442
4443 /**
4444 * @brief Enable commutation interrupt (COMIE).
4445 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
4446 * @param TIMx Timer instance
4447 * @retval None
4448 */
4449 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
4450 {
4451 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
4452 }
4453
4454 /**
4455 * @brief Disable commutation interrupt (COMIE).
4456 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
4457 * @param TIMx Timer instance
4458 * @retval None
4459 */
4460 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
4461 {
4462 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
4463 }
4464
4465 /**
4466 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
4467 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
4468 * @param TIMx Timer instance
4469 * @retval State of bit (1 or 0).
4470 */
4471 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
4472 {
4473 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
4474 }
4475
4476 /**
4477 * @brief Enable trigger interrupt (TIE).
4478 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
4479 * @param TIMx Timer instance
4480 * @retval None
4481 */
4482 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
4483 {
4484 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
4485 }
4486
4487 /**
4488 * @brief Disable trigger interrupt (TIE).
4489 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
4490 * @param TIMx Timer instance
4491 * @retval None
4492 */
4493 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
4494 {
4495 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
4496 }
4497
4498 /**
4499 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
4500 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
4501 * @param TIMx Timer instance
4502 * @retval State of bit (1 or 0).
4503 */
4504 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
4505 {
4506 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
4507 }
4508
4509 /**
4510 * @brief Enable break interrupt (BIE).
4511 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
4512 * @param TIMx Timer instance
4513 * @retval None
4514 */
4515 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
4516 {
4517 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
4518 }
4519
4520 /**
4521 * @brief Disable break interrupt (BIE).
4522 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
4523 * @param TIMx Timer instance
4524 * @retval None
4525 */
4526 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
4527 {
4528 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
4529 }
4530
4531 /**
4532 * @brief Indicates whether the break interrupt (BIE) is enabled.
4533 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
4534 * @param TIMx Timer instance
4535 * @retval State of bit (1 or 0).
4536 */
4537 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
4538 {
4539 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
4540 }
4541
4542 /**
4543 * @}
4544 */
4545
4546 /** @defgroup TIM_LL_EF_DMA_Management DMA-Management
4547 * @{
4548 */
4549 /**
4550 * @brief Enable update DMA request (UDE).
4551 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
4552 * @param TIMx Timer instance
4553 * @retval None
4554 */
4555 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4556 {
4557 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
4558 }
4559
4560 /**
4561 * @brief Disable update DMA request (UDE).
4562 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
4563 * @param TIMx Timer instance
4564 * @retval None
4565 */
4566 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4567 {
4568 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
4569 }
4570
4571 /**
4572 * @brief Indicates whether the update DMA request (UDE) is enabled.
4573 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
4574 * @param TIMx Timer instance
4575 * @retval State of bit (1 or 0).
4576 */
4577 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
4578 {
4579 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
4580 }
4581
4582 /**
4583 * @brief Enable capture/compare 1 DMA request (CC1DE).
4584 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
4585 * @param TIMx Timer instance
4586 * @retval None
4587 */
4588 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
4589 {
4590 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4591 }
4592
4593 /**
4594 * @brief Disable capture/compare 1 DMA request (CC1DE).
4595 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
4596 * @param TIMx Timer instance
4597 * @retval None
4598 */
4599 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
4600 {
4601 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4602 }
4603
4604 /**
4605 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
4606 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
4607 * @param TIMx Timer instance
4608 * @retval State of bit (1 or 0).
4609 */
4610 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
4611 {
4612 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
4613 }
4614
4615 /**
4616 * @brief Enable capture/compare 2 DMA request (CC2DE).
4617 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
4618 * @param TIMx Timer instance
4619 * @retval None
4620 */
4621 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
4622 {
4623 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4624 }
4625
4626 /**
4627 * @brief Disable capture/compare 2 DMA request (CC2DE).
4628 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
4629 * @param TIMx Timer instance
4630 * @retval None
4631 */
4632 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
4633 {
4634 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4635 }
4636
4637 /**
4638 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
4639 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
4640 * @param TIMx Timer instance
4641 * @retval State of bit (1 or 0).
4642 */
4643 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
4644 {
4645 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
4646 }
4647
4648 /**
4649 * @brief Enable capture/compare 3 DMA request (CC3DE).
4650 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
4651 * @param TIMx Timer instance
4652 * @retval None
4653 */
4654 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
4655 {
4656 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4657 }
4658
4659 /**
4660 * @brief Disable capture/compare 3 DMA request (CC3DE).
4661 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
4662 * @param TIMx Timer instance
4663 * @retval None
4664 */
4665 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
4666 {
4667 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4668 }
4669
4670 /**
4671 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
4672 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
4673 * @param TIMx Timer instance
4674 * @retval State of bit (1 or 0).
4675 */
4676 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
4677 {
4678 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
4679 }
4680
4681 /**
4682 * @brief Enable capture/compare 4 DMA request (CC4DE).
4683 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
4684 * @param TIMx Timer instance
4685 * @retval None
4686 */
4687 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
4688 {
4689 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4690 }
4691
4692 /**
4693 * @brief Disable capture/compare 4 DMA request (CC4DE).
4694 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
4695 * @param TIMx Timer instance
4696 * @retval None
4697 */
4698 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
4699 {
4700 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4701 }
4702
4703 /**
4704 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
4705 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
4706 * @param TIMx Timer instance
4707 * @retval State of bit (1 or 0).
4708 */
4709 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
4710 {
4711 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
4712 }
4713
4714 /**
4715 * @brief Enable commutation DMA request (COMDE).
4716 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
4717 * @param TIMx Timer instance
4718 * @retval None
4719 */
4720 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
4721 {
4722 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
4723 }
4724
4725 /**
4726 * @brief Disable commutation DMA request (COMDE).
4727 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
4728 * @param TIMx Timer instance
4729 * @retval None
4730 */
4731 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
4732 {
4733 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
4734 }
4735
4736 /**
4737 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
4738 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
4739 * @param TIMx Timer instance
4740 * @retval State of bit (1 or 0).
4741 */
4742 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
4743 {
4744 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
4745 }
4746
4747 /**
4748 * @brief Enable trigger interrupt (TDE).
4749 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
4750 * @param TIMx Timer instance
4751 * @retval None
4752 */
4753 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
4754 {
4755 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
4756 }
4757
4758 /**
4759 * @brief Disable trigger interrupt (TDE).
4760 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
4761 * @param TIMx Timer instance
4762 * @retval None
4763 */
4764 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
4765 {
4766 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
4767 }
4768
4769 /**
4770 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
4771 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
4772 * @param TIMx Timer instance
4773 * @retval State of bit (1 or 0).
4774 */
4775 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
4776 {
4777 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
4778 }
4779
4780 /**
4781 * @}
4782 */
4783
4784 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
4785 * @{
4786 */
4787 /**
4788 * @brief Generate an update event.
4789 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
4790 * @param TIMx Timer instance
4791 * @retval None
4792 */
4793 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
4794 {
4795 SET_BIT(TIMx->EGR, TIM_EGR_UG);
4796 }
4797
4798 /**
4799 * @brief Generate Capture/Compare 1 event.
4800 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
4801 * @param TIMx Timer instance
4802 * @retval None
4803 */
4804 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
4805 {
4806 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
4807 }
4808
4809 /**
4810 * @brief Generate Capture/Compare 2 event.
4811 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
4812 * @param TIMx Timer instance
4813 * @retval None
4814 */
4815 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
4816 {
4817 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
4818 }
4819
4820 /**
4821 * @brief Generate Capture/Compare 3 event.
4822 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
4823 * @param TIMx Timer instance
4824 * @retval None
4825 */
4826 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
4827 {
4828 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
4829 }
4830
4831 /**
4832 * @brief Generate Capture/Compare 4 event.
4833 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
4834 * @param TIMx Timer instance
4835 * @retval None
4836 */
4837 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
4838 {
4839 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
4840 }
4841
4842 /**
4843 * @brief Generate commutation event.
4844 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
4845 * @param TIMx Timer instance
4846 * @retval None
4847 */
4848 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
4849 {
4850 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
4851 }
4852
4853 /**
4854 * @brief Generate trigger event.
4855 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
4856 * @param TIMx Timer instance
4857 * @retval None
4858 */
4859 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
4860 {
4861 SET_BIT(TIMx->EGR, TIM_EGR_TG);
4862 }
4863
4864 /**
4865 * @brief Generate break event.
4866 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
4867 * @param TIMx Timer instance
4868 * @retval None
4869 */
4870 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
4871 {
4872 SET_BIT(TIMx->EGR, TIM_EGR_BG);
4873 }
4874
4875 /**
4876 * @brief Generate break 2 event.
4877 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
4878 * @param TIMx Timer instance
4879 * @retval None
4880 */
4881 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
4882 {
4883 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
4884 }
4885
4886 /**
4887 * @}
4888 */
4889
4890 #if defined(USE_FULL_LL_DRIVER)
4891 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
4892 * @{
4893 */
4894
4895 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
4896 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
4897 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
4898 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4899 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4900 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
4901 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
4902 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4903 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4904 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4905 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4906 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4907 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4908 /**
4909 * @}
4910 */
4911 #endif /* USE_FULL_LL_DRIVER */
4912
4913 /**
4914 * @}
4915 */
4916
4917 /**
4918 * @}
4919 */
4920
4921 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 ||TIM14 || TIM15 || TIM16 || TIM17 || TIM23 || TIM24 */
4922
4923 /**
4924 * @}
4925 */
4926
4927 #ifdef __cplusplus
4928 }
4929 #endif
4930
4931 #endif /* __STM32H7xx_LL_TIM_H */
4932 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/