2 ******************************************************************************
3 * @file stm32h7xx_ll_wwdg.h
4 * @author MCD Application Team
5 * @brief Header file of WWDG LL module.
6 ******************************************************************************
9 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
17 ******************************************************************************
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_LL_WWDG_H
22 #define STM32H7xx_LL_WWDG_H
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx.h"
31 /** @addtogroup STM32H7xx_LL_Driver
35 #if defined (WWDG1) || defined (WWDG2)
37 /** @defgroup WWDG_LL WWDG
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /* Private macros ------------------------------------------------------------*/
45 /* Exported types ------------------------------------------------------------*/
46 /* Exported constants --------------------------------------------------------*/
47 /** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
51 /** @defgroup WWDG_LL_EC_IT IT Defines
52 * @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
55 #define LL_WWDG_CFR_EWI WWDG_CFR_EWI
60 /** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
63 #define LL_WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
64 #define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
65 #define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
66 #define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
67 #define LL_WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2 /*!< WWDG counter clock = (PCLK1/4096)/16 */
68 #define LL_WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/32 */
69 #define LL_WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/64 */
70 #define LL_WWDG_PRESCALER_128 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/128 */
79 /* Exported macro ------------------------------------------------------------*/
80 /** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
83 /** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
87 * @brief Write a value in WWDG register
88 * @param __INSTANCE__ WWDG Instance
89 * @param __REG__ Register to be written
90 * @param __VALUE__ Value to be written in the register
93 #define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
96 * @brief Read a value in WWDG register
97 * @param __INSTANCE__ WWDG Instance
98 * @param __REG__ Register to be read
99 * @retval Register value
101 #define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
110 /* Exported functions --------------------------------------------------------*/
111 /** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
115 /** @defgroup WWDG_LL_EF_Configuration Configuration
119 * @brief Enable Window Watchdog. The watchdog is always disabled after a reset.
120 * @note It is enabled by setting the WDGA bit in the WWDG_CR register,
121 * then it cannot be disabled again except by a reset.
122 * This bit is set by software and only cleared by hardware after a reset.
123 * When WDGA = 1, the watchdog can generate a reset.
124 * @rmtoll CR WDGA LL_WWDG_Enable
125 * @param WWDGx WWDG Instance
128 __STATIC_INLINE
void LL_WWDG_Enable(WWDG_TypeDef
*WWDGx
)
130 SET_BIT(WWDGx
->CR
, WWDG_CR_WDGA
);
134 * @brief Checks if Window Watchdog is enabled
135 * @rmtoll CR WDGA LL_WWDG_IsEnabled
136 * @param WWDGx WWDG Instance
137 * @retval State of bit (1 or 0).
139 __STATIC_INLINE
uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef
*WWDGx
)
141 return ((READ_BIT(WWDGx
->CR
, WWDG_CR_WDGA
) == (WWDG_CR_WDGA
)) ? 1UL : 0UL);
145 * @brief Set the Watchdog counter value to provided value (7-bits T[6:0])
146 * @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
147 * This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
148 * A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
149 * Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
150 * @rmtoll CR T LL_WWDG_SetCounter
151 * @param WWDGx WWDG Instance
152 * @param Counter 0..0x7F (7 bit counter value)
155 __STATIC_INLINE
void LL_WWDG_SetCounter(WWDG_TypeDef
*WWDGx
, uint32_t Counter
)
157 MODIFY_REG(WWDGx
->CR
, WWDG_CR_T
, Counter
);
161 * @brief Return current Watchdog Counter Value (7 bits counter value)
162 * @rmtoll CR T LL_WWDG_GetCounter
163 * @param WWDGx WWDG Instance
164 * @retval 7 bit Watchdog Counter value
166 __STATIC_INLINE
uint32_t LL_WWDG_GetCounter(WWDG_TypeDef
*WWDGx
)
168 return (READ_BIT(WWDGx
->CR
, WWDG_CR_T
));
172 * @brief Set the time base of the prescaler (WDGTB).
173 * @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
174 * is decremented every (4096 x 2expWDGTB) PCLK cycles
175 * @rmtoll CFR WDGTB LL_WWDG_SetPrescaler
176 * @param WWDGx WWDG Instance
177 * @param Prescaler This parameter can be one of the following values:
178 * @arg @ref LL_WWDG_PRESCALER_1
179 * @arg @ref LL_WWDG_PRESCALER_2
180 * @arg @ref LL_WWDG_PRESCALER_4
181 * @arg @ref LL_WWDG_PRESCALER_8
182 * @arg @ref LL_WWDG_PRESCALER_16
183 * @arg @ref LL_WWDG_PRESCALER_32
184 * @arg @ref LL_WWDG_PRESCALER_64
185 * @arg @ref LL_WWDG_PRESCALER_128
188 __STATIC_INLINE
void LL_WWDG_SetPrescaler(WWDG_TypeDef
*WWDGx
, uint32_t Prescaler
)
190 MODIFY_REG(WWDGx
->CFR
, WWDG_CFR_WDGTB
, Prescaler
);
194 * @brief Return current Watchdog Prescaler Value
195 * @rmtoll CFR WDGTB LL_WWDG_GetPrescaler
196 * @param WWDGx WWDG Instance
197 * @retval Returned value can be one of the following values:
198 * @arg @ref LL_WWDG_PRESCALER_1
199 * @arg @ref LL_WWDG_PRESCALER_2
200 * @arg @ref LL_WWDG_PRESCALER_4
201 * @arg @ref LL_WWDG_PRESCALER_8
202 * @arg @ref LL_WWDG_PRESCALER_16
203 * @arg @ref LL_WWDG_PRESCALER_32
204 * @arg @ref LL_WWDG_PRESCALER_64
205 * @arg @ref LL_WWDG_PRESCALER_128
207 __STATIC_INLINE
uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef
*WWDGx
)
209 return (READ_BIT(WWDGx
->CFR
, WWDG_CFR_WDGTB
));
213 * @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
214 * @note This window value defines when write in the WWDG_CR register
215 * to program Watchdog counter is allowed.
216 * Watchdog counter value update must occur only when the counter value
217 * is lower than the Watchdog window register value.
218 * Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
219 * (in the control register) is refreshed before the downcounter has reached
220 * the watchdog window register value.
221 * Physically is possible to set the Window lower then 0x40 but it is not recommended.
222 * To generate an immediate reset, it is possible to set the Counter lower than 0x40.
223 * @rmtoll CFR W LL_WWDG_SetWindow
224 * @param WWDGx WWDG Instance
225 * @param Window 0x00..0x7F (7 bit Window value)
228 __STATIC_INLINE
void LL_WWDG_SetWindow(WWDG_TypeDef
*WWDGx
, uint32_t Window
)
230 MODIFY_REG(WWDGx
->CFR
, WWDG_CFR_W
, Window
);
234 * @brief Return current Watchdog Window Value (7 bits value)
235 * @rmtoll CFR W LL_WWDG_GetWindow
236 * @param WWDGx WWDG Instance
237 * @retval 7 bit Watchdog Window value
239 __STATIC_INLINE
uint32_t LL_WWDG_GetWindow(WWDG_TypeDef
*WWDGx
)
241 return (READ_BIT(WWDGx
->CFR
, WWDG_CFR_W
));
248 /** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
252 * @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
253 * @note This bit is set by hardware when the counter has reached the value 0x40.
254 * It must be cleared by software by writing 0.
255 * A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
256 * @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP
257 * @param WWDGx WWDG Instance
258 * @retval State of bit (1 or 0).
260 __STATIC_INLINE
uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef
*WWDGx
)
262 return ((READ_BIT(WWDGx
->SR
, WWDG_SR_EWIF
) == (WWDG_SR_EWIF
)) ? 1UL : 0UL);
266 * @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF)
267 * @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP
268 * @param WWDGx WWDG Instance
271 __STATIC_INLINE
void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef
*WWDGx
)
273 WRITE_REG(WWDGx
->SR
, ~WWDG_SR_EWIF
);
280 /** @defgroup WWDG_LL_EF_IT_Management IT_Management
284 * @brief Enable the Early Wakeup Interrupt.
285 * @note When set, an interrupt occurs whenever the counter reaches value 0x40.
286 * This interrupt is only cleared by hardware after a reset
287 * @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP
288 * @param WWDGx WWDG Instance
291 __STATIC_INLINE
void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef
*WWDGx
)
293 SET_BIT(WWDGx
->CFR
, WWDG_CFR_EWI
);
297 * @brief Check if Early Wakeup Interrupt is enabled
298 * @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP
299 * @param WWDGx WWDG Instance
300 * @retval State of bit (1 or 0).
302 __STATIC_INLINE
uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef
*WWDGx
)
304 return ((READ_BIT(WWDGx
->CFR
, WWDG_CFR_EWI
) == (WWDG_CFR_EWI
)) ? 1UL : 0UL);
319 #endif /* WWDG1 || WWDG2 */
329 #endif /* STM32H7xx_LL_WWDG_H */
331 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/