src/main/drivers/timer_hal.c

   1 /*
   2  * This file is part of Cleanflight and Betaflight.
   3  *
   4  * Cleanflight and Betaflight are free software. You can redistribute
   5  * this software and/or modify this software under the terms of the
   6  * GNU General Public License as published by the Free Software
   7  * Foundation, either version 3 of the License, or (at your option)
   8  * any later version.
   9  *
  10  * Cleanflight and Betaflight are distributed in the hope that they
  11  * will be useful, but WITHOUT ANY WARRANTY; without even the implied
  12  * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  13  * See the GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this software.
  17  *
  18  * If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include <stdbool.h>
  22 #include <stdint.h>
  23 #include <string.h>
  24 #include <math.h>
  25
  26 #include "platform.h"
  27
  28 #ifdef USE_TIMER
  29
  30 #include "build/atomic.h"
  31
  32 #include "common/utils.h"
  33
  34 #include "drivers/nvic.h"
  35
  36 #include "drivers/io.h"
  37 #include "drivers/dma.h"
  38
  39 #include "rcc.h"
  40
  41 #include "timer.h"
  42 #include "timer_impl.h"
  43
  44 #define TIM_N(n) (1 << (n))
  45
  46 /*
  47     Groups that allow running different period (ex 50Hz servos + 400Hz throttle + etc):
  48     TIM1 2 channels
  49     TIM2 4 channels
  50     TIM3 4 channels
  51     TIM4 4 channels
  52 */
  53
  54 /// TODO: HAL in a lot af calls lookupTimerIndex is used. Instead of passing the timer instance the index should be passed.
  55 #define USED_TIMER_COUNT BITCOUNT(USED_TIMERS)
  56
  57 #define TIM_IT_CCx(ch) (TIM_IT_CC1 << ((ch) / 4))
  58
  59 typedef struct timerConfig_s {
  60     // per-timer
  61     timerOvrHandlerRec_t *updateCallback;
  62
  63     // per-channel
  64     timerCCHandlerRec_t *edgeCallback[CC_CHANNELS_PER_TIMER];
  65     timerOvrHandlerRec_t *overflowCallback[CC_CHANNELS_PER_TIMER];
  66
  67     // state
  68     timerOvrHandlerRec_t *overflowCallbackActive; // null-terminated linkded list of active overflow callbacks
  69     uint32_t forcedOverflowTimerValue;
  70 } timerConfig_t;
  71 timerConfig_t timerConfig[USED_TIMER_COUNT + 1];
  72
  73 typedef struct {
  74     channelType_t type;
  75 } timerChannelInfo_t;
  76 timerChannelInfo_t timerChannelInfo[TIMER_CHANNEL_COUNT];
  77
  78 typedef struct {
  79     uint8_t priority;
  80 } timerInfo_t;
  81 timerInfo_t timerInfo[USED_TIMER_COUNT + 1];
  82
  83 typedef struct {
  84     TIM_HandleTypeDef Handle;
  85 } timerHandle_t;
  86 timerHandle_t timerHandle[USED_TIMER_COUNT + 1];
  87
  88 // return index of timer in timer table. Lowest timer has index 0
  89 #define TIMER_INDEX(i) BITCOUNT((TIM_N(i) - 1) & USED_TIMERS)
  90
  91 static uint8_t lookupTimerIndex(const TIM_TypeDef *tim)
  92 {
  93 #define _CASE_SHF 10           // amount we can safely shift timer address to the right. gcc will throw error if some timers overlap
  94 #define _CASE_(tim, index) case ((unsigned)tim >> _CASE_SHF): return index; break
  95 #define _CASE(i) _CASE_(TIM##i##_BASE, TIMER_INDEX(i))
  96
  97 // let gcc do the work, switch should be quite optimized
  98     switch ((unsigned)tim >> _CASE_SHF) {
  99 #if USED_TIMERS & TIM_N(1)
 100         _CASE(1);
 101 #endif
 102 #if USED_TIMERS & TIM_N(2)
 103         _CASE(2);
 104 #endif
 105 #if USED_TIMERS & TIM_N(3)
 106         _CASE(3);
 107 #endif
 108 #if USED_TIMERS & TIM_N(4)
 109         _CASE(4);
 110 #endif
 111 #if USED_TIMERS & TIM_N(5)
 112         _CASE(5);
 113 #endif
 114 #if USED_TIMERS & TIM_N(6)
 115         _CASE(6);
 116 #endif
 117 #if USED_TIMERS & TIM_N(7)
 118         _CASE(7);
 119 #endif
 120 #if USED_TIMERS & TIM_N(8)
 121         _CASE(8);
 122 #endif
 123 #if USED_TIMERS & TIM_N(9)
 124         _CASE(9);
 125 #endif
 126 #if USED_TIMERS & TIM_N(10)
 127         _CASE(10);
 128 #endif
 129 #if USED_TIMERS & TIM_N(11)
 130         _CASE(11);
 131 #endif
 132 #if USED_TIMERS & TIM_N(12)
 133         _CASE(12);
 134 #endif
 135 #if USED_TIMERS & TIM_N(13)
 136         _CASE(13);
 137 #endif
 138 #if USED_TIMERS & TIM_N(14)
 139         _CASE(14);
 140 #endif
 141 #if USED_TIMERS & TIM_N(15)
 142         _CASE(15);
 143 #endif
 144 #if USED_TIMERS & TIM_N(16)
 145         _CASE(16);
 146 #endif
 147 #if USED_TIMERS & TIM_N(17)
 148         _CASE(17);
 149 #endif
 150 #if USED_TIMERS & TIM_N(20)
 151         _CASE(20);
 152 #endif
 153     default:  return ~1;  // make sure final index is out of range
 154     }
 155 #undef _CASE
 156 #undef _CASE_
 157 }
 158
 159 TIM_TypeDef * const usedTimers[USED_TIMER_COUNT] = {
 160 #define _DEF(i) TIM##i
 161
 162 #if USED_TIMERS & TIM_N(1)
 163     _DEF(1),
 164 #endif
 165 #if USED_TIMERS & TIM_N(2)
 166     _DEF(2),
 167 #endif
 168 #if USED_TIMERS & TIM_N(3)
 169     _DEF(3),
 170 #endif
 171 #if USED_TIMERS & TIM_N(4)
 172     _DEF(4),
 173 #endif
 174 #if USED_TIMERS & TIM_N(5)
 175     _DEF(5),
 176 #endif
 177 #if USED_TIMERS & TIM_N(6)
 178     _DEF(6),
 179 #endif
 180 #if USED_TIMERS & TIM_N(7)
 181     _DEF(7),
 182 #endif
 183 #if USED_TIMERS & TIM_N(8)
 184     _DEF(8),
 185 #endif
 186 #if !(defined(STM32H7) || defined(STM32G4))
 187 #if USED_TIMERS & TIM_N(9)
 188     _DEF(9),
 189 #endif
 190 #if USED_TIMERS & TIM_N(10)
 191     _DEF(10),
 192 #endif
 193 #if USED_TIMERS & TIM_N(11)
 194     _DEF(11),
 195 #endif
 196 #endif
 197 #if !defined(STM32G4)
 198 #if USED_TIMERS & TIM_N(12)
 199     _DEF(12),
 200 #endif
 201 #if USED_TIMERS & TIM_N(13)
 202     _DEF(13),
 203 #endif
 204 #if USED_TIMERS & TIM_N(14)
 205     _DEF(14),
 206 #endif
 207 #endif
 208 #if USED_TIMERS & TIM_N(15)
 209     _DEF(15),
 210 #endif
 211 #if USED_TIMERS & TIM_N(16)
 212     _DEF(16),
 213 #endif
 214 #if USED_TIMERS & TIM_N(17)
 215     _DEF(17),
 216 #endif
 217 #if defined(STM32G4)
 218 #if USED_TIMERS & TIM_N(20)
 219     _DEF(20),
 220 #endif
 221 #endif
 222 #undef _DEF
 223 };
 224
 225 // Map timer index to timer number (Straight copy of usedTimers array)
 226 const int8_t timerNumbers[USED_TIMER_COUNT] = {
 227 #define _DEF(i) i
 228
 229 #if USED_TIMERS & TIM_N(1)
 230     _DEF(1),
 231 #endif
 232 #if USED_TIMERS & TIM_N(2)
 233     _DEF(2),
 234 #endif
 235 #if USED_TIMERS & TIM_N(3)
 236     _DEF(3),
 237 #endif
 238 #if USED_TIMERS & TIM_N(4)
 239     _DEF(4),
 240 #endif
 241 #if USED_TIMERS & TIM_N(5)
 242     _DEF(5),
 243 #endif
 244 #if USED_TIMERS & TIM_N(6)
 245     _DEF(6),
 246 #endif
 247 #if USED_TIMERS & TIM_N(7)
 248     _DEF(7),
 249 #endif
 250 #if USED_TIMERS & TIM_N(8)
 251     _DEF(8),
 252 #endif
 253 #if USED_TIMERS & TIM_N(9)
 254     _DEF(9),
 255 #endif
 256 #if USED_TIMERS & TIM_N(10)
 257     _DEF(10),
 258 #endif
 259 #if USED_TIMERS & TIM_N(11)
 260     _DEF(11),
 261 #endif
 262 #if USED_TIMERS & TIM_N(12)
 263     _DEF(12),
 264 #endif
 265 #if USED_TIMERS & TIM_N(13)
 266     _DEF(13),
 267 #endif
 268 #if USED_TIMERS & TIM_N(14)
 269     _DEF(14),
 270 #endif
 271 #if USED_TIMERS & TIM_N(15)
 272     _DEF(15),
 273 #endif
 274 #if USED_TIMERS & TIM_N(16)
 275     _DEF(16),
 276 #endif
 277 #if USED_TIMERS & TIM_N(17)
 278     _DEF(17),
 279 #endif
 280 #if USED_TIMERS & TIM_N(20)
 281     _DEF(20),
 282 #endif
 283 #undef _DEF
 284 };
 285
 286 int8_t timerGetNumberByIndex(uint8_t index)
 287 {
 288     if (index < USED_TIMER_COUNT) {
 289         return timerNumbers[index];
 290     } else {
 291         return 0;
 292     }
 293 }
 294
 295 int8_t timerGetTIMNumber(const TIM_TypeDef *tim)
 296 {
 297     uint8_t index = lookupTimerIndex(tim);
 298
 299     return timerGetNumberByIndex(index);
 300 }
 301
 302 static inline uint8_t lookupChannelIndex(const uint16_t channel)
 303 {
 304     return channel >> 2;
 305 }
 306
 307 uint8_t timerLookupChannelIndex(const uint16_t channel)
 308 {
 309     return lookupChannelIndex(channel);
 310 }
 311
 312 rccPeriphTag_t timerRCC(TIM_TypeDef *tim)
 313 {
 314     for (int i = 0; i < HARDWARE_TIMER_DEFINITION_COUNT; i++) {
 315         if (timerDefinitions[i].TIMx == tim) {
 316             return timerDefinitions[i].rcc;
 317         }
 318     }
 319     return 0;
 320 }
 321
 322 uint8_t timerInputIrq(TIM_TypeDef *tim)
 323 {
 324     for (int i = 0; i < HARDWARE_TIMER_DEFINITION_COUNT; i++) {
 325         if (timerDefinitions[i].TIMx == tim) {
 326             return timerDefinitions[i].inputIrq;
 327         }
 328     }
 329     return 0;
 330 }
 331
 332 void timerNVICConfigure(uint8_t irq)
 333 {
 334     HAL_NVIC_SetPriority(irq, NVIC_PRIORITY_BASE(NVIC_PRIO_TIMER), NVIC_PRIORITY_SUB(NVIC_PRIO_TIMER));
 335     HAL_NVIC_EnableIRQ(irq);
 336 }
 337
 338 TIM_HandleTypeDef* timerFindTimerHandle(TIM_TypeDef *tim)
 339 {
 340     uint8_t timerIndex = lookupTimerIndex(tim);
 341     if (timerIndex >= USED_TIMER_COUNT)
 342         return NULL;
 343
 344     return &timerHandle[timerIndex].Handle;
 345 }
 346
 347 void timerReconfigureTimeBase(TIM_TypeDef *tim, uint16_t period, uint32_t hz)
 348 {
 349     TIM_HandleTypeDef* handle = timerFindTimerHandle(tim);
 350     if (handle == NULL) return;
 351
 352     handle->Init.Period = (period - 1) & 0xffff; // AKA TIMx_ARR
 353     handle->Init.Prescaler = (timerClock(tim) / hz) - 1;
 354
 355     TIM_Base_SetConfig(handle->Instance, &handle->Init);
 356 }
 357
 358 void configTimeBase(TIM_TypeDef *tim, uint16_t period, uint32_t hz)
 359 {
 360     TIM_HandleTypeDef* handle = timerFindTimerHandle(tim);
 361     if (handle == NULL) return;
 362
 363     if (handle->Instance == tim) {
 364         // already configured
 365         return;
 366     }
 367
 368     handle->Instance = tim;
 369
 370     handle->Init.Period = (period - 1) & 0xffff; // AKA TIMx_ARR
 371     handle->Init.Prescaler = (timerClock(tim) / hz) - 1;
 372
 373     handle->Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
 374     handle->Init.CounterMode = TIM_COUNTERMODE_UP;
 375     handle->Init.RepetitionCounter = 0x0000;
 376
 377     HAL_TIM_Base_Init(handle);
 378     if (tim == TIM1 || tim == TIM2 || tim == TIM3 || tim == TIM4 || tim == TIM5 || tim == TIM8
 379 #if !(defined(STM32H7) || defined(STM32G4))
 380         || tim == TIM9
 381 #endif
 382       ) {
 383         TIM_ClockConfigTypeDef sClockSourceConfig;
 384         memset(&sClockSourceConfig, 0, sizeof(sClockSourceConfig));
 385         sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
 386         if (HAL_TIM_ConfigClockSource(handle, &sClockSourceConfig) != HAL_OK) {
 387             return;
 388         }
 389     }
 390     if (tim == TIM1 || tim == TIM2 || tim == TIM3 || tim == TIM4 || tim == TIM5 || tim == TIM8) {
 391         TIM_MasterConfigTypeDef sMasterConfig;
 392         memset(&sMasterConfig, 0, sizeof(sMasterConfig));
 393         sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
 394         if (HAL_TIMEx_MasterConfigSynchronization(handle, &sMasterConfig) != HAL_OK) {
 395             return;
 396         }
 397     }
 398 }
 399
 400 // old interface for PWM inputs. It should be replaced
 401 void timerConfigure(const timerHardware_t *timerHardwarePtr, uint16_t period, uint32_t hz)
 402 {
 403     uint8_t timerIndex = lookupTimerIndex(timerHardwarePtr->tim);
 404     if (timerIndex >= USED_TIMER_COUNT) {
 405         return;
 406     }
 407
 408     configTimeBase(timerHardwarePtr->tim, period, hz);
 409     HAL_TIM_Base_Start(&timerHandle[timerIndex].Handle);
 410
 411     uint8_t irq = timerInputIrq(timerHardwarePtr->tim);
 412     timerNVICConfigure(irq);
 413     // HACK - enable second IRQ on timers that need it
 414     switch (irq) {
 415
 416     case TIM1_CC_IRQn:
 417 #if defined(STM32F7)
 418         timerNVICConfigure(TIM1_UP_TIM10_IRQn);
 419 #elif defined(STM32H7)
 420         timerNVICConfigure(TIM1_UP_IRQn);
 421 #elif defined(STM32G4)
 422         timerNVICConfigure(TIM1_UP_TIM16_IRQn);
 423 #else
 424         // Empty
 425 #endif
 426         break;
 427     case TIM8_CC_IRQn:
 428 #if defined(STM32G4)
 429         timerNVICConfigure(TIM8_UP_IRQn);
 430 #else
 431         timerNVICConfigure(TIM8_UP_TIM13_IRQn);
 432 #endif
 433         break;
 434
 435     }
 436 }
 437
 438 // allocate and configure timer channel. Timer priority is set to highest priority of its channels
 439 void timerChInit(const timerHardware_t *timHw, channelType_t type, int irqPriority, uint8_t irq)
 440 {
 441     uint8_t timerIndex = lookupTimerIndex(timHw->tim);
 442     if (timerIndex >= USED_TIMER_COUNT) {
 443         return;
 444     }
 445     unsigned channel = timHw - TIMER_HARDWARE;
 446     if (channel >= TIMER_CHANNEL_COUNT)
 447         return;
 448
 449     timerChannelInfo[channel].type = type;
 450     unsigned timer = lookupTimerIndex(timHw->tim);
 451     if (timer >= USED_TIMER_COUNT)
 452         return;
 453     if (irqPriority < timerInfo[timer].priority) {
 454         // it would be better to set priority in the end, but current startup sequence is not ready
 455         configTimeBase(usedTimers[timer], 0, 1);
 456         HAL_TIM_Base_Start(&timerHandle[timerIndex].Handle);
 457
 458         HAL_NVIC_SetPriority(irq, NVIC_PRIORITY_BASE(irqPriority), NVIC_PRIORITY_SUB(irqPriority));
 459         HAL_NVIC_EnableIRQ(irq);
 460
 461         timerInfo[timer].priority = irqPriority;
 462     }
 463 }
 464
 465 void timerChCCHandlerInit(timerCCHandlerRec_t *self, timerCCHandlerCallback *fn)
 466 {
 467     self->fn = fn;
 468 }
 469
 470 void timerChOvrHandlerInit(timerOvrHandlerRec_t *self, timerOvrHandlerCallback *fn)
 471 {
 472     self->fn = fn;
 473     self->next = NULL;
 474 }
 475
 476 // update overflow callback list
 477 // some synchronization mechanism is neccesary to avoid disturbing other channels (BASEPRI used now)
 478 static void timerChConfig_UpdateOverflow(timerConfig_t *cfg, const TIM_TypeDef *tim)
 479 {
 480     uint8_t timerIndex = lookupTimerIndex(tim);
 481     if (timerIndex >= USED_TIMER_COUNT) {
 482         return;
 483     }
 484
 485     timerOvrHandlerRec_t **chain = &cfg->overflowCallbackActive;
 486     ATOMIC_BLOCK(NVIC_PRIO_TIMER) {
 487
 488         if (cfg->updateCallback) {
 489             *chain = cfg->updateCallback;
 490             chain = &cfg->updateCallback->next;
 491         }
 492
 493         for (int i = 0; i < CC_CHANNELS_PER_TIMER; i++)
 494             if (cfg->overflowCallback[i]) {
 495                 *chain = cfg->overflowCallback[i];
 496                 chain = &cfg->overflowCallback[i]->next;
 497             }
 498         *chain = NULL;
 499     }
 500     // enable or disable IRQ
 501     if (cfg->overflowCallbackActive)
 502         __HAL_TIM_ENABLE_IT(&timerHandle[timerIndex].Handle, TIM_IT_UPDATE);
 503     else
 504         __HAL_TIM_DISABLE_IT(&timerHandle[timerIndex].Handle, TIM_IT_UPDATE);
 505 }
 506
 507 // config edge and overflow callback for channel. Try to avoid overflowCallback, it is a bit expensive
 508 void timerChConfigCallbacks(const timerHardware_t *timHw, timerCCHandlerRec_t *edgeCallback, timerOvrHandlerRec_t *overflowCallback)
 509 {
 510     uint8_t timerIndex = lookupTimerIndex(timHw->tim);
 511     if (timerIndex >= USED_TIMER_COUNT) {
 512         return;
 513     }
 514     uint8_t channelIndex = lookupChannelIndex(timHw->channel);
 515     if (edgeCallback == NULL)   // disable irq before changing callback to NULL
 516         __HAL_TIM_DISABLE_IT(&timerHandle[timerIndex].Handle, TIM_IT_CCx(timHw->channel));
 517     // setup callback info
 518     timerConfig[timerIndex].edgeCallback[channelIndex] = edgeCallback;
 519     timerConfig[timerIndex].overflowCallback[channelIndex] = overflowCallback;
 520     // enable channel IRQ
 521     if (edgeCallback)
 522         __HAL_TIM_ENABLE_IT(&timerHandle[timerIndex].Handle, TIM_IT_CCx(timHw->channel));
 523
 524     timerChConfig_UpdateOverflow(&timerConfig[timerIndex], timHw->tim);
 525 }
 526
 527 void timerConfigUpdateCallback(const TIM_TypeDef *tim, timerOvrHandlerRec_t *updateCallback)
 528 {
 529     uint8_t timerIndex = lookupTimerIndex(tim);
 530     if (timerIndex >= USED_TIMER_COUNT) {
 531         return;
 532     }
 533     timerConfig[timerIndex].updateCallback = updateCallback;
 534     timerChConfig_UpdateOverflow(&timerConfig[timerIndex], tim);
 535 }
 536
 537 // configure callbacks for pair of channels (1+2 or 3+4).
 538 // Hi(2,4) and Lo(1,3) callbacks are specified, it is not important which timHw channel is used.
 539 // This is intended for dual capture mode (each channel handles one transition)
 540 void timerChConfigCallbacksDual(const timerHardware_t *timHw, timerCCHandlerRec_t *edgeCallbackLo, timerCCHandlerRec_t *edgeCallbackHi, timerOvrHandlerRec_t *overflowCallback)
 541 {
 542     uint8_t timerIndex = lookupTimerIndex(timHw->tim);
 543     if (timerIndex >= USED_TIMER_COUNT) {
 544         return;
 545     }
 546     uint16_t chLo = timHw->channel & ~TIM_CHANNEL_2;   // lower channel
 547     uint16_t chHi = timHw->channel | TIM_CHANNEL_2;    // upper channel
 548     uint8_t channelIndex = lookupChannelIndex(chLo);   // get index of lower channel
 549
 550     if (edgeCallbackLo == NULL)   // disable irq before changing setting callback to NULL
 551         __HAL_TIM_DISABLE_IT(&timerHandle[timerIndex].Handle, TIM_IT_CCx(chLo));
 552     if (edgeCallbackHi == NULL)   // disable irq before changing setting callback to NULL
 553         __HAL_TIM_DISABLE_IT(&timerHandle[timerIndex].Handle, TIM_IT_CCx(chHi));
 554
 555     // setup callback info
 556     timerConfig[timerIndex].edgeCallback[channelIndex] = edgeCallbackLo;
 557     timerConfig[timerIndex].edgeCallback[channelIndex + 1] = edgeCallbackHi;
 558     timerConfig[timerIndex].overflowCallback[channelIndex] = overflowCallback;
 559     timerConfig[timerIndex].overflowCallback[channelIndex + 1] = NULL;
 560
 561     // enable channel IRQs
 562     if (edgeCallbackLo) {
 563         __HAL_TIM_CLEAR_FLAG(&timerHandle[timerIndex].Handle, TIM_IT_CCx(chLo));
 564         __HAL_TIM_ENABLE_IT(&timerHandle[timerIndex].Handle, TIM_IT_CCx(chLo));
 565     }
 566     if (edgeCallbackHi) {
 567         __HAL_TIM_CLEAR_FLAG(&timerHandle[timerIndex].Handle, TIM_IT_CCx(chHi));
 568         __HAL_TIM_ENABLE_IT(&timerHandle[timerIndex].Handle, TIM_IT_CCx(chHi));
 569     }
 570
 571     timerChConfig_UpdateOverflow(&timerConfig[timerIndex], timHw->tim);
 572 }
 573
 574 // enable/disable IRQ for low channel in dual configuration
 575 //void timerChITConfigDualLo(const timerHardware_t *timHw, FunctionalState newState) {
 576 //    TIM_ITConfig(timHw->tim, TIM_IT_CCx(timHw->channel&~TIM_Channel_2), newState);
 577 //}
 578 // enable/disable IRQ for low channel in dual configuration
 579 void timerChITConfigDualLo(const timerHardware_t *timHw, FunctionalState newState)
 580 {
 581     uint8_t timerIndex = lookupTimerIndex(timHw->tim);
 582     if (timerIndex >= USED_TIMER_COUNT) {
 583         return;
 584     }
 585
 586     if (newState)
 587         __HAL_TIM_ENABLE_IT(&timerHandle[timerIndex].Handle, TIM_IT_CCx(timHw->channel & ~TIM_CHANNEL_2));
 588     else
 589         __HAL_TIM_DISABLE_IT(&timerHandle[timerIndex].Handle, TIM_IT_CCx(timHw->channel & ~TIM_CHANNEL_2));
 590 }
 591
 592 //// enable or disable IRQ
 593 //void timerChITConfig(const timerHardware_t *timHw, FunctionalState newState)
 594 //{
 595 //    TIM_ITConfig(timHw->tim, TIM_IT_CCx(timHw->channel), newState);
 596 //}
 597 // enable or disable IRQ
 598 void timerChITConfig(const timerHardware_t *timHw, FunctionalState newState)
 599 {
 600     uint8_t timerIndex = lookupTimerIndex(timHw->tim);
 601     if (timerIndex >= USED_TIMER_COUNT) {
 602         return;
 603     }
 604
 605     if (newState)
 606         __HAL_TIM_ENABLE_IT(&timerHandle[timerIndex].Handle, TIM_IT_CCx(timHw->channel));
 607     else
 608         __HAL_TIM_DISABLE_IT(&timerHandle[timerIndex].Handle, TIM_IT_CCx(timHw->channel));
 609 }
 610
 611 // clear Compare/Capture flag for channel
 612 //void timerChClearCCFlag(const timerHardware_t *timHw)
 613 //{
 614 //    TIM_ClearFlag(timHw->tim, TIM_IT_CCx(timHw->channel));
 615 //}
 616 // clear Compare/Capture flag for channel
 617 void timerChClearCCFlag(const timerHardware_t *timHw)
 618 {
 619     uint8_t timerIndex = lookupTimerIndex(timHw->tim);
 620     if (timerIndex >= USED_TIMER_COUNT) {
 621         return;
 622     }
 623
 624     __HAL_TIM_CLEAR_FLAG(&timerHandle[timerIndex].Handle, TIM_IT_CCx(timHw->channel));
 625 }
 626
 627 // configure timer channel GPIO mode
 628 void timerChConfigGPIO(const timerHardware_t* timHw, ioConfig_t mode)
 629 {
 630     IOInit(IOGetByTag(timHw->tag), OWNER_TIMER, 0);
 631     IOConfigGPIO(IOGetByTag(timHw->tag), mode);
 632 }
 633
 634 // calculate input filter constant
 635 // TODO - we should probably setup DTS to higher value to allow reasonable input filtering
 636 //   - notice that prescaler[0] does use DTS for sampling - the sequence won't be monotonous anymore
 637 static unsigned getFilter(unsigned ticks)
 638 {
 639     static const unsigned ftab[16] = {
 640         1*1,                 // fDTS !
 641         1*2, 1*4, 1*8,       // fCK_INT
 642         2*6, 2*8,            // fDTS/2
 643         4*6, 4*8,
 644         8*6, 8*8,
 645         16*5, 16*6, 16*8,
 646         32*5, 32*6, 32*8
 647     };
 648     for (unsigned i = 1; i < ARRAYLEN(ftab); i++)
 649         if (ftab[i] > ticks)
 650             return i - 1;
 651     return 0x0f;
 652 }
 653
 654 // Configure input captupre
 655 void timerChConfigIC(const timerHardware_t *timHw, bool polarityRising, unsigned inputFilterTicks)
 656 {
 657     unsigned timer = lookupTimerIndex(timHw->tim);
 658     if (timer >= USED_TIMER_COUNT)
 659         return;
 660
 661     TIM_IC_InitTypeDef TIM_ICInitStructure;
 662
 663     TIM_ICInitStructure.ICPolarity = polarityRising ? TIM_ICPOLARITY_RISING : TIM_ICPOLARITY_FALLING;
 664     TIM_ICInitStructure.ICSelection = TIM_ICSELECTION_DIRECTTI;
 665     TIM_ICInitStructure.ICPrescaler = TIM_ICPSC_DIV1;
 666     TIM_ICInitStructure.ICFilter = getFilter(inputFilterTicks);
 667     HAL_TIM_IC_ConfigChannel(&timerHandle[timer].Handle, &TIM_ICInitStructure, timHw->channel);
 668 }
 669
 670 // configure dual channel input channel for capture
 671 // polarity is for Low channel (capture order is always Lo - Hi)
 672 void timerChConfigICDual(const timerHardware_t *timHw, bool polarityRising, unsigned inputFilterTicks)
 673 {
 674     unsigned timer = lookupTimerIndex(timHw->tim);
 675     if (timer >= USED_TIMER_COUNT)
 676         return;
 677
 678     TIM_IC_InitTypeDef TIM_ICInitStructure;
 679     bool directRising = (timHw->channel & TIM_CHANNEL_2) ? !polarityRising : polarityRising;
 680
 681     // configure direct channel
 682     TIM_ICInitStructure.ICPolarity = directRising ? TIM_ICPOLARITY_RISING : TIM_ICPOLARITY_FALLING;
 683     TIM_ICInitStructure.ICSelection = TIM_ICSELECTION_DIRECTTI;
 684     TIM_ICInitStructure.ICPrescaler = TIM_ICPSC_DIV1;
 685     TIM_ICInitStructure.ICFilter = getFilter(inputFilterTicks);
 686     HAL_TIM_IC_ConfigChannel(&timerHandle[timer].Handle, &TIM_ICInitStructure, timHw->channel);
 687
 688     // configure indirect channel
 689     TIM_ICInitStructure.ICPolarity = directRising ? TIM_ICPOLARITY_FALLING : TIM_ICPOLARITY_RISING;
 690     TIM_ICInitStructure.ICSelection = TIM_ICSELECTION_INDIRECTTI;
 691     HAL_TIM_IC_ConfigChannel(&timerHandle[timer].Handle, &TIM_ICInitStructure, timHw->channel ^ TIM_CHANNEL_2);
 692 }
 693
 694 void timerChICPolarity(const timerHardware_t *timHw, bool polarityRising)
 695 {
 696     timCCER_t tmpccer = timHw->tim->CCER;
 697     tmpccer &= ~(TIM_CCER_CC1P << timHw->channel);
 698     tmpccer |= polarityRising ? (TIM_ICPOLARITY_RISING << timHw->channel) : (TIM_ICPOLARITY_FALLING << timHw->channel);
 699     timHw->tim->CCER = tmpccer;
 700 }
 701
 702 volatile timCCR_t* timerChCCRHi(const timerHardware_t *timHw)
 703 {
 704     return (volatile timCCR_t*)((volatile char*)&timHw->tim->CCR1 + (timHw->channel | TIM_CHANNEL_2));
 705 }
 706
 707 volatile timCCR_t* timerChCCRLo(const timerHardware_t *timHw)
 708 {
 709     return (volatile timCCR_t*)((volatile char*)&timHw->tim->CCR1 + (timHw->channel & ~TIM_CHANNEL_2));
 710 }
 711
 712 volatile timCCR_t* timerChCCR(const timerHardware_t *timHw)
 713 {
 714     return (volatile timCCR_t*)((volatile char*)&timHw->tim->CCR1 + timHw->channel);
 715 }
 716
 717 void timerChConfigOC(const timerHardware_t* timHw, bool outEnable, bool stateHigh)
 718 {
 719     unsigned timer = lookupTimerIndex(timHw->tim);
 720     if (timer >= USED_TIMER_COUNT)
 721         return;
 722
 723     TIM_OC_InitTypeDef TIM_OCInitStructure;
 724
 725     TIM_OCInitStructure.OCMode = TIM_OCMODE_INACTIVE;
 726     TIM_OCInitStructure.Pulse = 0x00000000;
 727     TIM_OCInitStructure.OCPolarity = stateHigh ? TIM_OCPOLARITY_HIGH : TIM_OCPOLARITY_LOW;
 728     TIM_OCInitStructure.OCNPolarity = TIM_OCPOLARITY_HIGH;
 729     TIM_OCInitStructure.OCIdleState = TIM_OCIDLESTATE_RESET;
 730     TIM_OCInitStructure.OCNIdleState = TIM_OCNIDLESTATE_RESET;
 731
 732     HAL_TIM_OC_ConfigChannel(&timerHandle[timer].Handle, &TIM_OCInitStructure, timHw->channel);
 733
 734     if (outEnable) {
 735         TIM_OCInitStructure.OCMode = TIM_OCMODE_INACTIVE;
 736         HAL_TIM_OC_ConfigChannel(&timerHandle[timer].Handle, &TIM_OCInitStructure, timHw->channel);
 737         HAL_TIM_OC_Start(&timerHandle[timer].Handle, timHw->channel);
 738     } else {
 739         TIM_OCInitStructure.OCMode = TIM_OCMODE_TIMING;
 740         HAL_TIM_OC_ConfigChannel(&timerHandle[timer].Handle, &TIM_OCInitStructure, timHw->channel);
 741         HAL_TIM_OC_Start_IT(&timerHandle[timer].Handle, timHw->channel);
 742     }
 743 }
 744
 745 static void timCCxHandler(TIM_TypeDef *tim, timerConfig_t *timerConfig)
 746 {
 747     uint16_t capture;
 748     unsigned tim_status;
 749     tim_status = tim->SR & tim->DIER;
 750 #if 1
 751     while (tim_status) {
 752         // flags will be cleared by reading CCR in dual capture, make sure we call handler correctly
 753         // currrent order is highest bit first. Code should not rely on specific order (it will introduce race conditions anyway)
 754         unsigned bit = __builtin_clz(tim_status);
 755         unsigned mask = ~(0x80000000 >> bit);
 756         tim->SR = mask;
 757         tim_status &= mask;
 758         switch (bit) {
 759         case __builtin_clz(TIM_IT_UPDATE): {
 760
 761             if (timerConfig->forcedOverflowTimerValue != 0) {
 762                 capture = timerConfig->forcedOverflowTimerValue - 1;
 763                 timerConfig->forcedOverflowTimerValue = 0;
 764             } else {
 765                 capture = tim->ARR;
 766             }
 767
 768             timerOvrHandlerRec_t *cb = timerConfig->overflowCallbackActive;
 769             while (cb) {
 770                 cb->fn(cb, capture);
 771                 cb = cb->next;
 772             }
 773             break;
 774         }
 775         case __builtin_clz(TIM_IT_CC1):
 776             timerConfig->edgeCallback[0]->fn(timerConfig->edgeCallback[0], tim->CCR1);
 777             break;
 778         case __builtin_clz(TIM_IT_CC2):
 779             timerConfig->edgeCallback[1]->fn(timerConfig->edgeCallback[1], tim->CCR2);
 780             break;
 781         case __builtin_clz(TIM_IT_CC3):
 782             timerConfig->edgeCallback[2]->fn(timerConfig->edgeCallback[2], tim->CCR3);
 783             break;
 784         case __builtin_clz(TIM_IT_CC4):
 785             timerConfig->edgeCallback[3]->fn(timerConfig->edgeCallback[3], tim->CCR4);
 786             break;
 787         }
 788     }
 789 #else
 790     if (tim_status & (int)TIM_IT_Update) {
 791         tim->SR = ~TIM_IT_Update;
 792         capture = tim->ARR;
 793         timerOvrHandlerRec_t *cb = timerConfig->overflowCallbackActive;
 794         while (cb) {
 795             cb->fn(cb, capture);
 796             cb = cb->next;
 797         }
 798     }
 799     if (tim_status & (int)TIM_IT_CC1) {
 800         tim->SR = ~TIM_IT_CC1;
 801         timerConfig->edgeCallback[0]->fn(timerConfig->edgeCallback[0], tim->CCR1);
 802     }
 803     if (tim_status & (int)TIM_IT_CC2) {
 804         tim->SR = ~TIM_IT_CC2;
 805         timerConfig->edgeCallback[1]->fn(timerConfig->edgeCallback[1], tim->CCR2);
 806     }
 807     if (tim_status & (int)TIM_IT_CC3) {
 808         tim->SR = ~TIM_IT_CC3;
 809         timerConfig->edgeCallback[2]->fn(timerConfig->edgeCallback[2], tim->CCR3);
 810     }
 811     if (tim_status & (int)TIM_IT_CC4) {
 812         tim->SR = ~TIM_IT_CC4;
 813         timerConfig->edgeCallback[3]->fn(timerConfig->edgeCallback[3], tim->CCR4);
 814     }
 815 #endif
 816 }
 817
 818 static inline void timUpdateHandler(TIM_TypeDef *tim, timerConfig_t *timerConfig)
 819 {
 820     uint16_t capture;
 821     unsigned tim_status;
 822     tim_status = tim->SR & tim->DIER;
 823     while (tim_status) {
 824         // flags will be cleared by reading CCR in dual capture, make sure we call handler correctly
 825         // currrent order is highest bit first. Code should not rely on specific order (it will introduce race conditions anyway)
 826         unsigned bit = __builtin_clz(tim_status);
 827         unsigned mask = ~(0x80000000 >> bit);
 828         tim->SR = mask;
 829         tim_status &= mask;
 830         switch (bit) {
 831         case __builtin_clz(TIM_IT_UPDATE): {
 832
 833             if (timerConfig->forcedOverflowTimerValue != 0) {
 834                 capture = timerConfig->forcedOverflowTimerValue - 1;
 835                 timerConfig->forcedOverflowTimerValue = 0;
 836             } else {
 837                 capture = tim->ARR;
 838             }
 839
 840             timerOvrHandlerRec_t *cb = timerConfig->overflowCallbackActive;
 841             while (cb) {
 842                 cb->fn(cb, capture);
 843                 cb = cb->next;
 844             }
 845             break;
 846         }
 847         }
 848     }
 849 }
 850
 851 // handler for shared interrupts when both timers need to check status bits
 852 #define _TIM_IRQ_HANDLER2(name, i, j)                                   \
 853     void name(void)                                                     \
 854     {                                                                   \
 855         timCCxHandler(TIM ## i, &timerConfig[TIMER_INDEX(i)]);          \
 856         timCCxHandler(TIM ## j, &timerConfig[TIMER_INDEX(j)]);          \
 857     } struct dummy
 858
 859 #define _TIM_IRQ_HANDLER(name, i)                                       \
 860     void name(void)                                                     \
 861     {                                                                   \
 862         timCCxHandler(TIM ## i, &timerConfig[TIMER_INDEX(i)]);          \
 863     } struct dummy
 864
 865 #define _TIM_IRQ_HANDLER_UPDATE_ONLY(name, i)                           \
 866     void name(void)                                                     \
 867     {                                                                   \
 868         timUpdateHandler(TIM ## i, &timerConfig[TIMER_INDEX(i)]);       \
 869     } struct dummy
 870
 871 #if USED_TIMERS & TIM_N(1)
 872 _TIM_IRQ_HANDLER(TIM1_CC_IRQHandler, 1);
 873 #  if defined(STM32H7)
 874 _TIM_IRQ_HANDLER(TIM1_UP_IRQHandler, 1);
 875 #  elif defined(STM32G4)
 876 #    if USED_TIMERS & TIM_N(16)
 877 _TIM_IRQ_HANDLER2(TIM1_UP_TIM16_IRQHandler, 1, 16);  // both timers are in use
 878 #    else
 879 _TIM_IRQ_HANDLER(TIM1_UP_TIM16_IRQHandler, 1);       // timer16 is not used timers are in use
 880 #    endif
 881 #  else
 882 #    if USED_TIMERS & TIM_N(10)
 883 _TIM_IRQ_HANDLER2(TIM1_UP_TIM10_IRQHandler, 1, 10);  // both timers are in use
 884 #    else
 885 _TIM_IRQ_HANDLER(TIM1_UP_TIM10_IRQHandler, 1);     // timer10 is not used
 886 #    endif
 887 #  endif
 888 #endif
 889
 890 #if USED_TIMERS & TIM_N(2)
 891 _TIM_IRQ_HANDLER(TIM2_IRQHandler, 2);
 892 #endif
 893 #if USED_TIMERS & TIM_N(3)
 894 _TIM_IRQ_HANDLER(TIM3_IRQHandler, 3);
 895 #endif
 896 #if USED_TIMERS & TIM_N(4)
 897 _TIM_IRQ_HANDLER(TIM4_IRQHandler, 4);
 898 #endif
 899 #if USED_TIMERS & TIM_N(5)
 900 _TIM_IRQ_HANDLER(TIM5_IRQHandler, 5);
 901 #endif
 902
 903 #if USED_TIMERS & TIM_N(6)
 904 #  if !(defined(USE_PID_AUDIO) && (defined(STM32H7) || defined(STM32F7)))
 905 _TIM_IRQ_HANDLER_UPDATE_ONLY(TIM6_DAC_IRQHandler, 6);
 906 #  endif
 907 #endif
 908 #if USED_TIMERS & TIM_N(7)
 909 // The USB VCP_HAL driver conflicts with TIM7, see TIMx_IRQHandler in usbd_cdc_interface.h
 910 #  if !(defined(USE_VCP) && (defined(STM32F4) || defined(STM32G4) || defined(STM32H7) || defined(STM32F7)))
 911 #    if defined(STM32G4)
 912 _TIM_IRQ_HANDLER_UPDATE_ONLY(TIM7_DAC_IRQHandler, 7);
 913 #    else
 914 _TIM_IRQ_HANDLER_UPDATE_ONLY(TIM7_IRQHandler, 7);
 915 #    endif
 916 #  endif
 917 #endif
 918
 919 #if USED_TIMERS & TIM_N(8)
 920 _TIM_IRQ_HANDLER(TIM8_CC_IRQHandler, 8);
 921 #  if defined(STM32G4)
 922 _TIM_IRQ_HANDLER(TIM8_UP_IRQHandler, 8);
 923 #  endif
 924
 925 #  if USED_TIMERS & TIM_N(13)
 926 _TIM_IRQ_HANDLER2(TIM8_UP_TIM13_IRQHandler, 8, 13);  // both timers are in use
 927 #  else
 928 _TIM_IRQ_HANDLER(TIM8_UP_TIM13_IRQHandler, 8);     // timer13 is not used
 929 #  endif
 930 #endif
 931
 932 #if USED_TIMERS & TIM_N(9)
 933 _TIM_IRQ_HANDLER(TIM1_BRK_TIM9_IRQHandler, 9);
 934 #endif
 935 #  if USED_TIMERS & TIM_N(11)
 936 _TIM_IRQ_HANDLER(TIM1_TRG_COM_TIM11_IRQHandler, 11);
 937 #  endif
 938 #if USED_TIMERS & TIM_N(12)
 939 _TIM_IRQ_HANDLER(TIM8_BRK_TIM12_IRQHandler, 12);
 940 #endif
 941 #if defined(STM32H7) && (USED_TIMERS & TIM_N(14))
 942 _TIM_IRQ_HANDLER(TIM8_TRG_COM_TIM14_IRQHandler, 14);
 943 #endif
 944 #if USED_TIMERS & TIM_N(15)
 945 #  if defined(STM32H7)
 946 _TIM_IRQ_HANDLER(TIM15_IRQHandler, 15);
 947 #  else
 948 _TIM_IRQ_HANDLER(TIM1_BRK_TIM15_IRQHandler, 15);
 949 #  endif
 950 #endif
 951 #if defined(STM32H7) && (USED_TIMERS & TIM_N(16))
 952 _TIM_IRQ_HANDLER(TIM16_IRQHandler, 16);
 953 #endif
 954 #if USED_TIMERS & TIM_N(17)
 955 #  if defined(STM32H7)
 956 _TIM_IRQ_HANDLER(TIM17_IRQHandler, 17);
 957 #  else
 958 _TIM_IRQ_HANDLER(TIM1_TRG_COM_TIM17_IRQHandler, 17);
 959 #  endif
 960 #endif
 961 #if USED_TIMERS & TIM_N(20)
 962 _TIM_IRQ_HANDLER(TIM20_CC_IRQHandler, 20);
 963 #endif
 964
 965 void timerInit(void)
 966 {
 967     memset(timerConfig, 0, sizeof(timerConfig));
 968
 969 #if USED_TIMERS & TIM_N(1)
 970     __HAL_RCC_TIM1_CLK_ENABLE();
 971 #endif
 972 #if USED_TIMERS & TIM_N(2)
 973     __HAL_RCC_TIM2_CLK_ENABLE();
 974 #endif
 975 #if USED_TIMERS & TIM_N(3)
 976     __HAL_RCC_TIM3_CLK_ENABLE();
 977 #endif
 978 #if USED_TIMERS & TIM_N(4)
 979     __HAL_RCC_TIM4_CLK_ENABLE();
 980 #endif
 981 #if USED_TIMERS & TIM_N(5)
 982     __HAL_RCC_TIM5_CLK_ENABLE();
 983 #endif
 984 #if USED_TIMERS & TIM_N(6)
 985     __HAL_RCC_TIM6_CLK_ENABLE();
 986 #endif
 987 #if USED_TIMERS & TIM_N(7)
 988     __HAL_RCC_TIM7_CLK_ENABLE();
 989 #endif
 990 #if USED_TIMERS & TIM_N(8)
 991     __HAL_RCC_TIM8_CLK_ENABLE();
 992 #endif
 993 #if !defined(STM32H7)
 994 #if USED_TIMERS & TIM_N(9)
 995     __HAL_RCC_TIM9_CLK_ENABLE();
 996 #endif
 997 #if USED_TIMERS & TIM_N(10)
 998     __HAL_RCC_TIM10_CLK_ENABLE();
 999 #endif
1000 #if USED_TIMERS & TIM_N(11)
1001     __HAL_RCC_TIM11_CLK_ENABLE();
1002 #endif
1003 #endif
1004 #if USED_TIMERS & TIM_N(12)
1005     __HAL_RCC_TIM12_CLK_ENABLE();
1006 #endif
1007 #if USED_TIMERS & TIM_N(13)
1008     __HAL_RCC_TIM13_CLK_ENABLE();
1009 #endif
1010 #if USED_TIMERS & TIM_N(14)
1011     __HAL_RCC_TIM14_CLK_ENABLE();
1012 #endif
1013 #if USED_TIMERS & TIM_N(15)
1014     __HAL_RCC_TIM15_CLK_ENABLE();
1015 #endif
1016 #if USED_TIMERS & TIM_N(16)
1017     __HAL_RCC_TIM16_CLK_ENABLE();
1018 #endif
1019 #if USED_TIMERS & TIM_N(17)
1020     __HAL_RCC_TIM17_CLK_ENABLE();
1021 #endif
1022 #if USED_TIMERS & TIM_N(20)
1023     __HAL_RCC_TIM20_CLK_ENABLE();
1024 #endif
1025
1026     /* enable the timer peripherals */
1027     for (int i = 0; i < TIMER_CHANNEL_COUNT; i++) {
1028         RCC_ClockCmd(timerRCC(TIMER_HARDWARE[i].tim), ENABLE);
1029     }
1030
1031 #if defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
1032     for (unsigned timerIndex = 0; timerIndex < TIMER_CHANNEL_COUNT; timerIndex++) {
1033         const timerHardware_t *timerHardwarePtr = &TIMER_HARDWARE[timerIndex];
1034         if (timerHardwarePtr->usageFlags == TIM_USE_NONE) {
1035             continue;
1036         }
1037         // XXX IOConfigGPIOAF in timerInit should eventually go away.
1038         IOConfigGPIOAF(IOGetByTag(timerHardwarePtr->tag), IOCFG_AF_PP, timerHardwarePtr->alternateFunction);
1039     }
1040 #endif
1041
1042     /* enable the timer peripherals */
1043     for (unsigned i = 0; i < TIMER_CHANNEL_COUNT; i++) {
1044         RCC_ClockCmd(timerRCC(TIMER_HARDWARE[i].tim), ENABLE);
1045     }
1046
1047     // initialize timer channel structures
1048     for (unsigned i = 0; i < TIMER_CHANNEL_COUNT; i++) {
1049         timerChannelInfo[i].type = TYPE_FREE;
1050     }
1051
1052     for (unsigned i = 0; i < USED_TIMER_COUNT; i++) {
1053         timerInfo[i].priority = ~0;
1054     }
1055 }
1056
1057 // finish configuring timers after allocation phase
1058 // start timers
1059 // TODO - Work in progress - initialization routine must be modified/verified to start correctly without timers
1060 void timerStart(void)
1061 {
1062 #if 0
1063     for (unsigned timer = 0; timer < USED_TIMER_COUNT; timer++) {
1064         int priority = -1;
1065         int irq = -1;
1066         for (unsigned hwc = 0; hwc < TIMER_CHANNEL_COUNT; hwc++) {
1067             if ((timerChannelInfo[hwc].type != TYPE_FREE) && (TIMER_HARDWARE[hwc].tim == usedTimers[timer])) {
1068                 // TODO - move IRQ to timer info
1069                 irq = TIMER_HARDWARE[hwc].irq;
1070             }
1071         }
1072         // TODO - aggregate required timer paramaters
1073         configTimeBase(usedTimers[timer], 0, 1);
1074         TIM_Cmd(usedTimers[timer], ENABLE);
1075         if (priority >= 0) {  // maybe none of the channels was configured
1076             NVIC_InitTypeDef NVIC_InitStructure;
1077
1078             NVIC_InitStructure.NVIC_IRQChannel = irq;
1079             NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = NVIC_SPLIT_PRIORITY_BASE(priority);
1080             NVIC_InitStructure.NVIC_IRQChannelSubPriority = NVIC_SPLIT_PRIORITY_SUB(priority);
1081             NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
1082             NVIC_Init(&NVIC_InitStructure);
1083         }
1084     }
1085 #endif
1086 }
1087
1088 /**
1089  * Force an overflow for a given timer.
1090  * Saves the current value of the counter in the relevant timerConfig's forcedOverflowTimerValue variable.
1091  * @param TIM_Typedef *tim The timer to overflow
1092  * @return void
1093  **/
1094 void timerForceOverflow(TIM_TypeDef *tim)
1095 {
1096     uint8_t timerIndex = lookupTimerIndex((const TIM_TypeDef *)tim);
1097
1098     ATOMIC_BLOCK(NVIC_PRIO_TIMER) {
1099         // Save the current count so that PPM reading will work on the same timer that was forced to overflow
1100         timerConfig[timerIndex].forcedOverflowTimerValue = tim->CNT + 1;
1101
1102         // Force an overflow by setting the UG bit
1103         tim->EGR |= TIM_EGR_UG;
1104     }
1105 }
1106
1107 // DMA_Handle_index
1108 uint16_t timerDmaIndex(uint8_t channel)
1109 {
1110     switch (channel) {
1111     case TIM_CHANNEL_1:
1112         return TIM_DMA_ID_CC1;
1113     case TIM_CHANNEL_2:
1114         return TIM_DMA_ID_CC2;
1115     case TIM_CHANNEL_3:
1116         return TIM_DMA_ID_CC3;
1117     case TIM_CHANNEL_4:
1118         return TIM_DMA_ID_CC4;
1119     }
1120     return 0;
1121 }
1122
1123 // TIM_DMA_sources
1124 uint16_t timerDmaSource(uint8_t channel)
1125 {
1126     switch (channel) {
1127     case TIM_CHANNEL_1:
1128         return TIM_DMA_CC1;
1129     case TIM_CHANNEL_2:
1130         return TIM_DMA_CC2;
1131     case TIM_CHANNEL_3:
1132         return TIM_DMA_CC3;
1133     case TIM_CHANNEL_4:
1134         return TIM_DMA_CC4;
1135     }
1136     return 0;
1137 }
1138
1139 uint16_t timerGetPrescalerByDesiredMhz(TIM_TypeDef *tim, uint16_t mhz)
1140 {
1141     return timerGetPrescalerByDesiredHertz(tim, MHZ_TO_HZ(mhz));
1142 }
1143
1144 uint16_t timerGetPeriodByPrescaler(TIM_TypeDef *tim, uint16_t prescaler, uint32_t hz)
1145 {
1146     return (uint16_t)((timerClock(tim) / (prescaler + 1)) / hz);
1147 }
1148
1149 uint16_t timerGetPrescalerByDesiredHertz(TIM_TypeDef *tim, uint32_t hz)
1150 {
1151     // protection here for desired hertz > SystemCoreClock???
1152     if (hz > timerClock(tim)) {
1153         return 0;
1154     }
1155     return (uint16_t)((timerClock(tim) + hz / 2) / hz) - 1;
1156 }
1157
1158 HAL_StatusTypeDef TIM_DMACmd(TIM_HandleTypeDef *htim, uint32_t Channel, FunctionalState NewState)
1159 {
1160     switch (Channel) {
1161     case TIM_CHANNEL_1: {
1162         if (NewState != DISABLE) {
1163             /* Enable the TIM Capture/Compare 1 DMA request */
1164             __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1165         } else {
1166             /* Disable the TIM Capture/Compare 1 DMA request */
1167             __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1168         }
1169     }
1170         break;
1171
1172     case TIM_CHANNEL_2: {
1173         if (NewState != DISABLE) {
1174             /* Enable the TIM Capture/Compare 2 DMA request */
1175             __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1176         } else {
1177             /* Disable the TIM Capture/Compare 2 DMA request */
1178             __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1179         }
1180     }
1181         break;
1182
1183     case TIM_CHANNEL_3: {
1184         if (NewState != DISABLE) {
1185             /* Enable the TIM Capture/Compare 3 DMA request */
1186             __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1187         } else {
1188             /* Disable the TIM Capture/Compare 3 DMA request */
1189             __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1190         }
1191     }
1192         break;
1193
1194     case TIM_CHANNEL_4: {
1195         if (NewState != DISABLE) {
1196             /* Enable the TIM Capture/Compare 4 DMA request */
1197             __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1198         } else {
1199             /* Disable the TIM Capture/Compare 4 DMA request */
1200             __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1201         }
1202     }
1203         break;
1204
1205     default:
1206         break;
1207     }
1208     /* Change the htim state */
1209     htim->State = HAL_TIM_STATE_READY;
1210     /* Return function status */
1211     return HAL_OK;
1212 }
1213
1214 HAL_StatusTypeDef DMA_SetCurrDataCounter(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1215 {
1216     if ((htim->State == HAL_TIM_STATE_BUSY)) {
1217         return HAL_BUSY;
1218     } else if ((htim->State == HAL_TIM_STATE_READY)) {
1219         if (((uint32_t) pData == 0) && (Length > 0)) {
1220             return HAL_ERROR;
1221         } else {
1222             htim->State = HAL_TIM_STATE_BUSY;
1223         }
1224     }
1225     switch (Channel) {
1226     case TIM_CHANNEL_1: {
1227         /* Set the DMA Period elapsed callback */
1228         htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
1229
1230         /* Set the DMA error callback */
1231         htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError;
1232
1233         /* Enable the DMA Stream */
1234         HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t) pData, (uint32_t) & htim->Instance->CCR1, Length);
1235     }
1236         break;
1237
1238     case TIM_CHANNEL_2: {
1239         /* Set the DMA Period elapsed callback */
1240         htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
1241
1242         /* Set the DMA error callback */
1243         htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;
1244
1245         /* Enable the DMA Stream */
1246         HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t) pData, (uint32_t) & htim->Instance->CCR2, Length);
1247     }
1248         break;
1249
1250     case TIM_CHANNEL_3: {
1251         /* Set the DMA Period elapsed callback */
1252         htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
1253
1254         /* Set the DMA error callback */
1255         htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError;
1256
1257         /* Enable the DMA Stream */
1258         HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t) pData, (uint32_t) & htim->Instance->CCR3, Length);
1259     }
1260         break;
1261
1262     case TIM_CHANNEL_4: {
1263         /* Set the DMA Period elapsed callback */
1264         htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
1265
1266         /* Set the DMA error callback */
1267         htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError;
1268
1269         /* Enable the DMA Stream */
1270         HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t) pData, (uint32_t) & htim->Instance->CCR4, Length);
1271     }
1272         break;
1273
1274     default:
1275         break;
1276     }
1277     /* Return function status */
1278     return HAL_OK;
1279 }
1280 #endif