src/main/drivers/timer_stm32h7xx.c

   1 /*
   2  * This file is part of Cleanflight and Betaflight.
   3  *
   4  * Cleanflight and Betaflight are free software. You can redistribute
   5  * this software and/or modify this software under the terms of the
   6  * GNU General Public License as published by the Free Software
   7  * Foundation, either version 3 of the License, or (at your option)
   8  * any later version.
   9  *
  10  * Cleanflight and Betaflight are distributed in the hope that they
  11  * will be useful, but WITHOUT ANY WARRANTY; without even the implied
  12  * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  13  * See the GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this software.
  17  *
  18  * If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "platform.h"
  22
  23 #ifdef USE_TIMER
  24
  25 #include "common/utils.h"
  26
  27 #include "drivers/dma.h"
  28 #include "drivers/io.h"
  29 #include "drivers/timer_def.h"
  30
  31 #include "stm32h7xx.h"
  32 #include "rcc.h"
  33 #include "timer.h"
  34
  35 const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = {
  36     { .TIMx = TIM1,  .rcc = RCC_APB2(TIM1),   .inputIrq = TIM1_CC_IRQn},
  37     { .TIMx = TIM2,  .rcc = RCC_APB1L(TIM2),  .inputIrq = TIM2_IRQn},
  38     { .TIMx = TIM3,  .rcc = RCC_APB1L(TIM3),  .inputIrq = TIM3_IRQn},
  39     { .TIMx = TIM4,  .rcc = RCC_APB1L(TIM4),  .inputIrq = TIM4_IRQn},
  40     { .TIMx = TIM5,  .rcc = RCC_APB1L(TIM5),  .inputIrq = TIM5_IRQn},
  41     { .TIMx = TIM6,  .rcc = RCC_APB1L(TIM6),  .inputIrq = TIM6_DAC_IRQn},
  42     { .TIMx = TIM7,  .rcc = RCC_APB1L(TIM7),  .inputIrq = TIM7_IRQn},
  43     { .TIMx = TIM8,  .rcc = RCC_APB2(TIM8),   .inputIrq = TIM8_CC_IRQn},
  44     { .TIMx = TIM12, .rcc = RCC_APB1L(TIM12), .inputIrq = TIM8_BRK_TIM12_IRQn},
  45     { .TIMx = TIM13, .rcc = RCC_APB1L(TIM13), .inputIrq = TIM8_UP_TIM13_IRQn},
  46     { .TIMx = TIM14, .rcc = RCC_APB1L(TIM14), .inputIrq = TIM8_TRG_COM_TIM14_IRQn},
  47     { .TIMx = TIM15, .rcc = RCC_APB2(TIM15),  .inputIrq = TIM15_IRQn},
  48     { .TIMx = TIM16, .rcc = RCC_APB2(TIM16),  .inputIrq = TIM16_IRQn},
  49     { .TIMx = TIM17, .rcc = RCC_APB2(TIM17),  .inputIrq = TIM17_IRQn},
  50 };
  51
  52 #if defined(USE_TIMER_MGMT)
  53 const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = {
  54 // Auto-generated from 'timer_def.h'
  55 // Port A
  56     DEF_TIM(TIM2, CH1, PA0, TIM_USE_ANY, 0, 0, 0),
  57     DEF_TIM(TIM2, CH2, PA1, TIM_USE_ANY, 0, 0, 0),
  58     DEF_TIM(TIM2, CH3, PA2, TIM_USE_ANY, 0, 0, 0),
  59     DEF_TIM(TIM2, CH4, PA3, TIM_USE_ANY, 0, 0, 0),
  60     DEF_TIM(TIM2, CH1, PA5, TIM_USE_ANY, 0, 0, 0),
  61     DEF_TIM(TIM1, CH1N, PA7, TIM_USE_ANY, 0, 0, 0),
  62     DEF_TIM(TIM1, CH1, PA8, TIM_USE_ANY, 0, 0, 0),
  63     DEF_TIM(TIM1, CH2, PA9, TIM_USE_ANY, 0, 0, 0),
  64     DEF_TIM(TIM1, CH3, PA10, TIM_USE_ANY, 0, 0, 0),
  65     DEF_TIM(TIM1, CH4, PA11, TIM_USE_ANY, 0, 0, 0),
  66     DEF_TIM(TIM2, CH1, PA15, TIM_USE_ANY, 0, 0, 0),
  67
  68     DEF_TIM(TIM5, CH1, PA0, TIM_USE_ANY, 0, 0, 0),
  69     DEF_TIM(TIM5, CH2, PA1, TIM_USE_ANY, 0, 0, 0),
  70     DEF_TIM(TIM5, CH3, PA2, TIM_USE_ANY, 0, 0, 0),
  71     DEF_TIM(TIM5, CH4, PA3, TIM_USE_ANY, 0, 0, 0),
  72     DEF_TIM(TIM3, CH1, PA6, TIM_USE_ANY, 0, 0, 0),
  73     DEF_TIM(TIM3, CH2, PA7, TIM_USE_ANY, 0, 0, 0),
  74
  75     DEF_TIM(TIM8, CH1N, PA5, TIM_USE_ANY, 0, 0, 0),
  76     DEF_TIM(TIM8, CH1N, PA7, TIM_USE_ANY, 0, 0, 0),
  77
  78     DEF_TIM(TIM13, CH1, PA6, TIM_USE_ANY, 0, 0, 0),
  79     DEF_TIM(TIM14, CH1, PA7, TIM_USE_ANY, 0, 0, 0),
  80
  81     DEF_TIM(TIM15, CH1N, PA1, TIM_USE_ANY, 0, 0, 0),
  82     DEF_TIM(TIM15, CH1, PA2, TIM_USE_ANY, 0, 0, 0),
  83     DEF_TIM(TIM15, CH2, PA3, TIM_USE_ANY, 0, 0, 0),
  84
  85 // Port B
  86     DEF_TIM(TIM1, CH2N, PB0, TIM_USE_ANY, 0, 0, 0),
  87     DEF_TIM(TIM1, CH3N, PB1, TIM_USE_ANY, 0, 0, 0),
  88     DEF_TIM(TIM2, CH2, PB3, TIM_USE_ANY, 0, 0, 0),
  89     DEF_TIM(TIM16, CH1N, PB6, TIM_USE_ANY, 0, 0, 0),
  90     DEF_TIM(TIM17, CH1N, PB7, TIM_USE_ANY, 0, 0, 0),
  91     DEF_TIM(TIM16, CH1, PB8, TIM_USE_ANY, 0, 0, 0),
  92     DEF_TIM(TIM17, CH1, PB9, TIM_USE_ANY, 0, 0, 0),
  93     DEF_TIM(TIM2, CH3, PB10, TIM_USE_ANY, 0, 0, 0),
  94     DEF_TIM(TIM2, CH4, PB11, TIM_USE_ANY, 0, 0, 0),
  95     DEF_TIM(TIM1, CH1N, PB13, TIM_USE_ANY, 0, 0, 0),
  96     DEF_TIM(TIM1, CH2N, PB14, TIM_USE_ANY, 0, 0, 0),
  97     DEF_TIM(TIM1, CH3N, PB15, TIM_USE_ANY, 0, 0, 0),
  98
  99     DEF_TIM(TIM3, CH3, PB0, TIM_USE_ANY, 0, 0, 0),
 100     DEF_TIM(TIM3, CH4, PB1, TIM_USE_ANY, 0, 0, 0),
 101     DEF_TIM(TIM3, CH1, PB4, TIM_USE_ANY, 0, 0, 0),
 102     DEF_TIM(TIM3, CH2, PB5, TIM_USE_ANY, 0, 0, 0),
 103     DEF_TIM(TIM4, CH1, PB6, TIM_USE_ANY, 0, 0, 0),
 104     DEF_TIM(TIM4, CH2, PB7, TIM_USE_ANY, 0, 0, 0),
 105     DEF_TIM(TIM4, CH3, PB8, TIM_USE_ANY, 0, 0, 0),
 106     DEF_TIM(TIM4, CH4, PB9, TIM_USE_ANY, 0, 0, 0),
 107
 108     DEF_TIM(TIM12, CH1, PB14, TIM_USE_ANY, 0, 0, 0),
 109     DEF_TIM(TIM12, CH2, PB15, TIM_USE_ANY, 0, 0, 0),
 110
 111 // Port C
 112     DEF_TIM(TIM3, CH1, PC6, TIM_USE_ANY, 0, 0, 0),
 113     DEF_TIM(TIM3, CH2, PC7, TIM_USE_ANY, 0, 0, 0),
 114     DEF_TIM(TIM3, CH3, PC8, TIM_USE_ANY, 0, 0, 0),
 115     DEF_TIM(TIM3, CH4, PC9, TIM_USE_ANY, 0, 0, 0),
 116
 117     DEF_TIM(TIM8, CH1, PC6, TIM_USE_ANY, 0, 0, 0),
 118     DEF_TIM(TIM8, CH2, PC7, TIM_USE_ANY, 0, 0, 0),
 119     DEF_TIM(TIM8, CH3, PC8, TIM_USE_ANY, 0, 0, 0),
 120     DEF_TIM(TIM8, CH4, PC9, TIM_USE_ANY, 0, 0, 0),
 121
 122 // Port D
 123     DEF_TIM(TIM4, CH1, PD12, TIM_USE_ANY, 0, 0, 0),
 124     DEF_TIM(TIM4, CH2, PD13, TIM_USE_ANY, 0, 0, 0),
 125     DEF_TIM(TIM4, CH3, PD14, TIM_USE_ANY, 0, 0, 0),
 126     DEF_TIM(TIM4, CH4, PD15, TIM_USE_ANY, 0, 0, 0),
 127
 128 // Port E
 129     DEF_TIM(TIM1, CH1N, PE8, TIM_USE_ANY, 0, 0, 0),
 130     DEF_TIM(TIM1, CH1, PE9, TIM_USE_ANY, 0, 0, 0),
 131     DEF_TIM(TIM1, CH2N, PE10, TIM_USE_ANY, 0, 0, 0),
 132     DEF_TIM(TIM1, CH2, PE11, TIM_USE_ANY, 0, 0, 0),
 133     DEF_TIM(TIM1, CH3N, PE12, TIM_USE_ANY, 0, 0, 0),
 134     DEF_TIM(TIM1, CH3, PE13, TIM_USE_ANY, 0, 0, 0),
 135     DEF_TIM(TIM1, CH4, PE14, TIM_USE_ANY, 0, 0, 0),
 136
 137     DEF_TIM(TIM15, CH1N, PE4, TIM_USE_ANY, 0, 0, 0),
 138     DEF_TIM(TIM15, CH1, PE5, TIM_USE_ANY, 0, 0, 0),
 139     DEF_TIM(TIM15, CH2, PE6, TIM_USE_ANY, 0, 0, 0),
 140
 141 // Port F
 142     DEF_TIM(TIM16, CH1, PF6, TIM_USE_ANY, 0, 0, 0),
 143     DEF_TIM(TIM17, CH1, PF7, TIM_USE_ANY, 0, 0, 0),
 144     DEF_TIM(TIM16, CH1N, PF8, TIM_USE_ANY, 0, 0, 0),
 145     DEF_TIM(TIM17, CH1N, PF9, TIM_USE_ANY, 0, 0, 0),
 146
 147     DEF_TIM(TIM13, CH1N, PF8, TIM_USE_ANY, 0, 0, 0),
 148     DEF_TIM(TIM14, CH1N, PF9, TIM_USE_ANY, 0, 0, 0),
 149
 150 // Port H
 151 // Port H is not available for LPQFP-100 or 144 and TFBGA-100 package
 152 //    DEF_TIM(TIM12, CH1, PH6, TIM_USE_ANY, 0, 0, 0),
 153 //    DEF_TIM(TIM12, CH2, PH9, TIM_USE_ANY, 0, 0, 0),
 154 //    DEF_TIM(TIM5, CH1, PH10, TIM_USE_ANY, 0, 0, 0),
 155 //    DEF_TIM(TIM5, CH2, PH11, TIM_USE_ANY, 0, 0, 0),
 156 //    DEF_TIM(TIM5, CH3, PH12, TIM_USE_ANY, 0, 0, 0),
 157 //    DEF_TIM(TIM8, CH1N, PH13, TIM_USE_ANY, 0, 0, 0),
 158 //    DEF_TIM(TIM8, CH2N, PH14, TIM_USE_ANY, 0, 0, 0),
 159 //    DEF_TIM(TIM8, CH3N, PH15, TIM_USE_ANY, 0, 0, 0),
 160 };
 161 #endif
 162
 163
 164 uint32_t timerClock(TIM_TypeDef *tim)
 165 {
 166     int timpre;
 167     uint32_t pclk;
 168     uint32_t ppre;
 169
 170     // Implement the table:
 171     // RM0433 (Rev 6) Table 52.
 172     // RM0455 (Rev 3) Table 55.
 173     // "Ratio between clock timer and pclk"
 174     // (Tables are the same, just D2 or CD difference)
 175
 176 #if defined(STM32H743xx) || defined(STM32H750xx) || defined(STM32H723xx) || defined(STM32H725xx) || defined(STM32H730xx)
 177 #define PERIPH_PRESCALER(bus) ((RCC->D2CFGR & RCC_D2CFGR_D2PPRE ## bus) >> RCC_D2CFGR_D2PPRE ## bus ## _Pos)
 178 #elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ)
 179 #define PERIPH_PRESCALER(bus) ((RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE ## bus) >> RCC_CDCFGR2_CDPPRE ## bus ## _Pos)
 180 #else
 181 #error Unknown MCU type
 182 #endif
 183
 184     if (tim == TIM1 || tim == TIM8 || tim == TIM15 || tim == TIM16 || tim == TIM17) {
 185         // Timers on APB2
 186         pclk = HAL_RCC_GetPCLK2Freq();
 187         ppre = PERIPH_PRESCALER(2);
 188     } else {
 189         // Timers on APB1
 190         pclk = HAL_RCC_GetPCLK1Freq();
 191         ppre = PERIPH_PRESCALER(1);
 192     }
 193
 194     timpre = (RCC->CFGR & RCC_CFGR_TIMPRE) ? 1 : 0;
 195
 196     int index = (timpre << 3) | ppre;
 197
 198     static uint8_t periphToKernel[16] = { // The multiplier table
 199         1, 1, 1, 1, 2, 2, 2, 2, // TIMPRE = 0
 200         1, 1, 1, 1, 2, 4, 4, 4  // TIMPRE = 1
 201     };
 202
 203     return pclk * periphToKernel[index];
 204
 205 #undef PERIPH_PRESCALER
 206 }
 207 #endif