src/main/startup/startup_stm32f446xx.s

   1 /**
   2   ******************************************************************************
   3   * @file      startup_stm32f40_41xxx.s
   4   * @author    MCD Application Team
   5   * @version   V1.6.1
   6   * @date      21-October-2015
   7   * @brief     STM32F40xxx/41xxx Devices vector table for Atollic TrueSTUDIO toolchain.
   8   *            Same as startup_stm32f40_41xxx.s and maintained for legacy purpose
   9   *            This module performs:
  10   *                - Set the initial SP
  11   *                - Set the initial PC == Reset_Handler,
  12   *                - Set the vector table entries with the exceptions ISR address
  13   *                - Configure the clock system and the external SRAM mounted on
  14   *                  STM324xG-EVAL board to be used as data memory (optional,
  15   *                  to be enabled by user)
  16   *                - Branches to main in the C library (which eventually
  17   *                  calls main()).
  18   *            After Reset the Cortex-M4 processor is in Thread mode,
  19   *            priority is Privileged, and the Stack is set to Main.
  20   ******************************************************************************
  21   * @attention
  22   *
  23   * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
  24   *
  25   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
  26   * You may not use this file except in compliance with the License.
  27   * You may obtain a copy of the License at:
  28   *
  29   *        http://www.st.com/software_license_agreement_liberty_v2
  30   *
  31   * Unless required by applicable law or agreed to in writing, software
  32   * distributed under the License is distributed on an "AS IS" BASIS,
  33   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  34   * See the License for the specific language governing permissions and
  35   * limitations under the License.
  36   *
  37   ******************************************************************************
  38   */
  39
  40   .syntax unified
  41   .cpu cortex-m4
  42   .fpu softvfp
  43   .thumb
  44
  45 .global  g_pfnVectors
  46 .global  Default_Handler
  47
  48 /* start address for the initialization values of the .data section.
  49 defined in linker script */
  50 .word  _sidata
  51 /* start address for the .data section. defined in linker script */
  52 .word  _sdata
  53 /* end address for the .data section. defined in linker script */
  54 .word  _edata
  55 /* start address for the .bss section. defined in linker script */
  56 .word  _sbss
  57 /* end address for the .bss section. defined in linker script */
  58 .word  _ebss
  59 /* stack used for SystemInit_ExtMemCtl; always internal RAM used */
  60
  61 /**
  62  * @brief  This is the code that gets called when the processor first
  63  *          starts execution following a reset event. Only the absolutely
  64  *          necessary set is performed, after which the application
  65  *          supplied main() routine is called.
  66  * @param  None
  67  * @retval : None
  68 */
  69
  70   .section  .text.Reset_Handler
  71   .weak  Reset_Handler
  72   .type  Reset_Handler, %function
  73 Reset_Handler:
  74   // Defined in C code
  75   bl persistentObjectInit
  76   bl checkForBootLoaderRequest
  77
  78 /* Copy the data segment initializers from flash to SRAM */
  79   movs  r1, #0
  80   b  LoopCopyDataInit
  81
  82 CopyDataInit:
  83   ldr  r3, =_sidata
  84   ldr  r3, [r3, r1]
  85   str  r3, [r0, r1]
  86   adds  r1, r1, #4
  87
  88 LoopCopyDataInit:
  89   ldr  r0, =_sdata
  90   ldr  r3, =_edata
  91   adds  r2, r0, r1
  92   cmp  r2, r3
  93   bcc  CopyDataInit
  94   ldr  r2, =_sbss
  95   b  LoopFillZerobss
  96 /* Zero fill the bss segment. */
  97 FillZerobss:
  98   movs  r3, #0
  99   str  r3, [r2], #4
 100
 101 LoopFillZerobss:
 102   ldr  r3, = _ebss
 103   cmp  r2, r3
 104   bcc  FillZerobss
 105
 106 /* Mark the heap and stack */
 107   ldr   r2, =_heap_stack_begin
 108   b     LoopMarkHeapStack
 109
 110 MarkHeapStack:
 111   movs  r3, 0xa5a5a5a5
 112   str   r3, [r2], #4
 113
 114 LoopMarkHeapStack:
 115   ldr   r3, = _heap_stack_end
 116   cmp   r2, r3
 117   bcc   MarkHeapStack
 118
 119 /*FPU settings*/
 120  ldr     r0, =0xE000ED88           /* Enable CP10,CP11 */
 121  ldr     r1,[r0]
 122  orr     r1,r1,#(0xF << 20)
 123  str     r1,[r0]
 124
 125 /* Call the clock system intitialization function.*/
 126   bl  SystemInit
 127
 128 /* Call the application's entry point.*/
 129   bl  main
 130   bx  lr
 131
 132 LoopForever:
 133   b LoopForever
 134
 135 Reboot_Loader:                // mj666
 136
 137   // Reboot to ROM            // mj666
 138   ldr     r0, =0x1FFF0000     // mj666
 139   ldr     sp,[r0, #0]         // mj666
 140   ldr     r0,[r0, #4]         // mj666
 141   bx      r0                  // mj666
 142 .size  Reset_Handler, .-Reset_Handler
 143
 144 /**
 145  * @brief  This is the code that gets called when the processor receives an
 146  *         unexpected interrupt.  This simply enters an infinite loop, preserving
 147  *         the system state for examination by a debugger.
 148  * @param  None
 149  * @retval None
 150 */
 151     .section  .text.Default_Handler,"ax",%progbits
 152 Default_Handler:
 153 Infinite_Loop:
 154   b  Infinite_Loop
 155   .size  Default_Handler, .-Default_Handler
 156 /******************************************************************************
 157 *
 158 * The minimal vector table for a Cortex M4. Note that the proper constructs
 159 * must be placed on this to ensure that it ends up at physical address
 160 * 0x0000.0000.
 161 *
 162 *******************************************************************************/
 163   .section  .isr_vector,"a",%progbits
 164   .type  g_pfnVectors, %object
 165   .size  g_pfnVectors, .-g_pfnVectors
 166
 167
 168 g_pfnVectors:
 169   .word  _estack
 170   .word  Reset_Handler
 171   .word  NMI_Handler
 172   .word  HardFault_Handler
 173   .word  MemManage_Handler
 174   .word  BusFault_Handler
 175   .word  UsageFault_Handler
 176   .word  0
 177   .word  0
 178   .word  0
 179   .word  0
 180   .word  SVC_Handler
 181   .word  DebugMon_Handler
 182   .word  0
 183   .word  PendSV_Handler
 184   .word  SysTick_Handler
 185
 186   /* External Interrupts */
 187   .word     WWDG_IRQHandler                   /* Window WatchDog              */
 188   .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */
 189   .word     TAMP_STAMP_IRQHandler             /* Tamper and TimeStamps through the EXTI line */
 190   .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */
 191   .word     FLASH_IRQHandler                  /* FLASH                        */
 192   .word     RCC_IRQHandler                    /* RCC                          */
 193   .word     EXTI0_IRQHandler                  /* EXTI Line0                   */
 194   .word     EXTI1_IRQHandler                  /* EXTI Line1                   */
 195   .word     EXTI2_IRQHandler                  /* EXTI Line2                   */
 196   .word     EXTI3_IRQHandler                  /* EXTI Line3                   */
 197   .word     EXTI4_IRQHandler                  /* EXTI Line4                   */
 198   .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */
 199   .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */
 200   .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */
 201   .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */
 202   .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */
 203   .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */
 204   .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */
 205   .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */
 206   .word     0                /* CAN1 TX                      */
 207   .word     0               /* CAN1 RX0                     */
 208   .word     0               /* CAN1 RX1                     */
 209   .word     0               /* CAN1 SCE                     */
 210   .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */
 211   .word     TIM1_BRK_TIM9_IRQHandler          /* TIM1 Break and TIM9          */
 212   .word     TIM1_UP_TIM10_IRQHandler          /* TIM1 Update and TIM10        */
 213   .word     TIM1_TRG_COM_TIM11_IRQHandler     /* TIM1 Trigger and Commutation and TIM11 */
 214   .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */
 215   .word     TIM2_IRQHandler                   /* TIM2                         */
 216   .word     TIM3_IRQHandler                   /* TIM3                         */
 217   .word     TIM4_IRQHandler                   /* TIM4                         */
 218   .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */
 219   .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */
 220   .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */
 221   .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */
 222   .word     SPI1_IRQHandler                   /* SPI1                         */
 223   .word     SPI2_IRQHandler                   /* SPI2                         */
 224   .word     USART1_IRQHandler                 /* USART1                       */
 225   .word     USART2_IRQHandler                 /* USART2                       */
 226   .word     0                 /* USART3                       */
 227   .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */
 228   .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */
 229   .word     OTG_FS_WKUP_IRQHandler            /* USB OTG FS Wakeup through EXTI line */
 230   .word     0         /* TIM8 Break and TIM12         */
 231   .word     0          /* TIM8 Update and TIM13        */
 232   .word     0     /* TIM8 Trigger and Commutation and TIM14 */
 233   .word     0                /* TIM8 Capture Compare         */
 234   .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */
 235   .word     0                   /* FSMC                         */
 236   .word     SDIO_IRQHandler                   /* SDIO                         */
 237   .word     TIM5_IRQHandler                   /* TIM5                         */
 238   .word     SPI3_IRQHandler                   /* SPI3                         */
 239   .word     0                  /* UART4                        */
 240   .word     0                  /* UART5                        */
 241   .word     0               /* TIM6 and DAC1&2 underrun errors */
 242   .word     0                   /* TIM7                         */
 243   .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */
 244   .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */
 245   .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */
 246   .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */
 247   .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */
 248   .word     0                    /* Ethernet                     */
 249   .word     0               /* Ethernet Wakeup through EXTI line */
 250   .word     0                /* CAN2 TX                      */
 251   .word     0               /* CAN2 RX0                     */
 252   .word     0               /* CAN2 RX1                     */
 253   .word     0               /* CAN2 SCE                     */
 254   .word     OTG_FS_IRQHandler                 /* USB OTG FS                   */
 255   .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */
 256   .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */
 257   .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */
 258   .word     USART6_IRQHandler                 /* USART6                       */
 259   .word     I2C3_EV_IRQHandler                /* I2C3 event                   */
 260   .word     I2C3_ER_IRQHandler                /* I2C3 error                   */
 261   .word     0         /* USB OTG HS End Point 1 Out   */
 262   .word     0          /* USB OTG HS End Point 1 In    */
 263   .word     0            /* USB OTG HS Wakeup through EXTI */
 264   .word     0                 /* USB OTG HS                   */
 265   .word     0                   /* DCMI                         */
 266   .word     0                   /* CRYP crypto                  */
 267   .word     0               /* Hash and Rng                 */
 268   .word     FPU_IRQHandler                    /* FPU                          */
 269   .word     0                                 /* Reserved                     */
 270   .word     0                                 /* Reserved                     */
 271   .word     SPI4_IRQHandler                   /* SPI4                         */
 272   .word     SPI5_IRQHandler                   /* SPI5                         */
 273 /*******************************************************************************
 274 *
 275 * Provide weak aliases for each Exception handler to the Default_Handler.
 276 * As they are weak aliases, any function with the same name will override
 277 * this definition.
 278 *
 279 *******************************************************************************/
 280    .weak      NMI_Handler
 281    .thumb_set NMI_Handler,Default_Handler
 282
 283    .weak      HardFault_Handler
 284    .thumb_set HardFault_Handler,Default_Handler
 285
 286    .weak      MemManage_Handler
 287    .thumb_set MemManage_Handler,Default_Handler
 288
 289    .weak      BusFault_Handler
 290    .thumb_set BusFault_Handler,Default_Handler
 291
 292    .weak      UsageFault_Handler
 293    .thumb_set UsageFault_Handler,Default_Handler
 294
 295    .weak      SVC_Handler
 296    .thumb_set SVC_Handler,Default_Handler
 297
 298    .weak      DebugMon_Handler
 299    .thumb_set DebugMon_Handler,Default_Handler
 300
 301    .weak      PendSV_Handler
 302    .thumb_set PendSV_Handler,Default_Handler
 303
 304    .weak      SysTick_Handler
 305    .thumb_set SysTick_Handler,Default_Handler
 306
 307    .weak      WWDG_IRQHandler
 308    .thumb_set WWDG_IRQHandler,Default_Handler
 309
 310    .weak      PVD_IRQHandler
 311    .thumb_set PVD_IRQHandler,Default_Handler
 312
 313    .weak      TAMP_STAMP_IRQHandler
 314    .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
 315
 316    .weak      RTC_WKUP_IRQHandler
 317    .thumb_set RTC_WKUP_IRQHandler,Default_Handler
 318
 319    .weak      FLASH_IRQHandler
 320    .thumb_set FLASH_IRQHandler,Default_Handler
 321
 322    .weak      RCC_IRQHandler
 323    .thumb_set RCC_IRQHandler,Default_Handler
 324
 325    .weak      EXTI0_IRQHandler
 326    .thumb_set EXTI0_IRQHandler,Default_Handler
 327
 328    .weak      EXTI1_IRQHandler
 329    .thumb_set EXTI1_IRQHandler,Default_Handler
 330
 331    .weak      EXTI2_IRQHandler
 332    .thumb_set EXTI2_IRQHandler,Default_Handler
 333
 334    .weak      EXTI3_IRQHandler
 335    .thumb_set EXTI3_IRQHandler,Default_Handler
 336
 337    .weak      EXTI4_IRQHandler
 338    .thumb_set EXTI4_IRQHandler,Default_Handler
 339
 340    .weak      DMA1_Stream0_IRQHandler
 341    .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
 342
 343    .weak      DMA1_Stream1_IRQHandler
 344    .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
 345
 346    .weak      DMA1_Stream2_IRQHandler
 347    .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
 348
 349    .weak      DMA1_Stream3_IRQHandler
 350    .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
 351
 352    .weak      DMA1_Stream4_IRQHandler
 353    .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
 354
 355    .weak      DMA1_Stream5_IRQHandler
 356    .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
 357
 358    .weak      DMA1_Stream6_IRQHandler
 359    .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
 360
 361    .weak      ADC_IRQHandler
 362    .thumb_set ADC_IRQHandler,Default_Handler
 363
 364    .weak      EXTI9_5_IRQHandler
 365    .thumb_set EXTI9_5_IRQHandler,Default_Handler
 366
 367    .weak      TIM1_BRK_TIM9_IRQHandler
 368    .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
 369
 370    .weak      TIM1_UP_TIM10_IRQHandler
 371    .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
 372
 373    .weak      TIM1_TRG_COM_TIM11_IRQHandler
 374    .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
 375
 376    .weak      TIM1_CC_IRQHandler
 377    .thumb_set TIM1_CC_IRQHandler,Default_Handler
 378
 379    .weak      TIM2_IRQHandler
 380    .thumb_set TIM2_IRQHandler,Default_Handler
 381
 382    .weak      TIM3_IRQHandler
 383    .thumb_set TIM3_IRQHandler,Default_Handler
 384
 385    .weak      TIM4_IRQHandler
 386    .thumb_set TIM4_IRQHandler,Default_Handler
 387
 388    .weak      I2C1_EV_IRQHandler
 389    .thumb_set I2C1_EV_IRQHandler,Default_Handler
 390
 391    .weak      I2C1_ER_IRQHandler
 392    .thumb_set I2C1_ER_IRQHandler,Default_Handler
 393
 394    .weak      I2C2_EV_IRQHandler
 395    .thumb_set I2C2_EV_IRQHandler,Default_Handler
 396
 397    .weak      I2C2_ER_IRQHandler
 398    .thumb_set I2C2_ER_IRQHandler,Default_Handler
 399
 400    .weak      SPI1_IRQHandler
 401    .thumb_set SPI1_IRQHandler,Default_Handler
 402
 403    .weak      SPI2_IRQHandler
 404    .thumb_set SPI2_IRQHandler,Default_Handler
 405
 406    .weak      USART1_IRQHandler
 407    .thumb_set USART1_IRQHandler,Default_Handler
 408
 409    .weak      USART2_IRQHandler
 410    .thumb_set USART2_IRQHandler,Default_Handler
 411
 412    .weak      EXTI15_10_IRQHandler
 413    .thumb_set EXTI15_10_IRQHandler,Default_Handler
 414
 415    .weak      RTC_Alarm_IRQHandler
 416    .thumb_set RTC_Alarm_IRQHandler,Default_Handler
 417
 418    .weak      OTG_FS_WKUP_IRQHandler
 419    .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
 420
 421    .weak      DMA1_Stream7_IRQHandler
 422    .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
 423
 424    .weak      SDIO_IRQHandler
 425    .thumb_set SDIO_IRQHandler,Default_Handler
 426
 427    .weak      TIM5_IRQHandler
 428    .thumb_set TIM5_IRQHandler,Default_Handler
 429
 430    .weak      SPI3_IRQHandler
 431    .thumb_set SPI3_IRQHandler,Default_Handler
 432
 433    .weak      DMA2_Stream0_IRQHandler
 434    .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
 435
 436    .weak      DMA2_Stream1_IRQHandler
 437    .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
 438
 439    .weak      DMA2_Stream2_IRQHandler
 440    .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
 441
 442    .weak      DMA2_Stream3_IRQHandler
 443    .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
 444
 445    .weak      DMA2_Stream4_IRQHandler
 446    .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
 447
 448    .weak      OTG_FS_IRQHandler
 449    .thumb_set OTG_FS_IRQHandler,Default_Handler
 450
 451    .weak      DMA2_Stream5_IRQHandler
 452    .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
 453
 454    .weak      DMA2_Stream6_IRQHandler
 455    .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
 456
 457    .weak      DMA2_Stream7_IRQHandler
 458    .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
 459
 460    .weak      USART6_IRQHandler
 461    .thumb_set USART6_IRQHandler,Default_Handler
 462
 463    .weak      I2C3_EV_IRQHandler
 464    .thumb_set I2C3_EV_IRQHandler,Default_Handler
 465
 466    .weak      I2C3_ER_IRQHandler
 467    .thumb_set I2C3_ER_IRQHandler,Default_Handler
 468
 469    .weak      FPU_IRQHandler
 470    .thumb_set FPU_IRQHandler,Default_Handler
 471
 472    .weak      SPI4_IRQHandler
 473    .thumb_set SPI4_IRQHandler,Default_Handler
 474
 475    .weak      SPI5_IRQHandler
 476    .thumb_set SPI5_IRQHandler,Default_Handler
 477
 478 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/