src/platform/APM32/startup/system_apm32f4xx.c

   1 /**
   2  *
   3  * @file        system_apm32f4xx.c
   4  *
   5  * @brief       CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   6  *
   7  * @version     V1.0.0
   8  *
   9  * @date        2023-07-31
  10  *
  11  * @attention
  12  *
  13  *  Copyright (C) 2023 Geehy Semiconductor
  14  *
  15  *  You may not use this file except in compliance with the
  16  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  17  *
  18  *  The program is only for reference, which is distributed in the hope
  19  *  that it will be useful and instructional for customers to develop
  20  *  their software. Unless required by applicable law or agreed to in
  21  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  22  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
  23  *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
  24  *  and limitations under the License.
  25  */
  26
  27 /** @addtogroup CMSIS
  28   * @{
  29   */
  30
  31 /** @addtogroup apm32f4xx_system
  32   * @{
  33   */
  34
  35 /** @addtogroup APM32F4xx_System_Private_Includes
  36   * @{
  37   */
  38
  39 #include "apm32f4xx.h"
  40 #include "system_apm32f4xx.h"
  41 #include "platform.h"
  42 #include "drivers/system.h"
  43 #include "drivers/persistent.h"
  44
  45 #include <string.h>
  46
  47 /* Value of the external oscillator in Hz */
  48 #if !defined  (HSE_VALUE)
  49   #define HSE_VALUE    ((uint32_t)8000000U)
  50 #endif /* HSE_VALUE */
  51
  52 /* Value of the internal oscillator in Hz */
  53 #if !defined  (HSI_VALUE)
  54   #define HSI_VALUE    ((uint32_t)16000000U)
  55 #endif /* HSI_VALUE */
  56
  57 /**
  58   * @}
  59   */
  60
  61 /** @addtogroup APM32F4xx_System_Private_TypesDefinitions
  62   * @{
  63   */
  64
  65 /**
  66   * @}
  67   */
  68
  69 /** @addtogroup APM32F4xx_System_Private_Defines
  70   * @{
  71   */
  72 /* Uncomment the following line if you need to relocate your vector table in internal SRAM */
  73 /* #define VECT_TAB_SRAM */
  74
  75 /* Vector table base offset field. This value must be a multiple of 0x200 */
  76 #define VECT_TAB_OFFSET  0x00
  77
  78 /**
  79   * @}
  80   */
  81
  82 /** @addtogroup APM32F4xx_System_Private_Macros
  83   * @{
  84   */
  85 #define PLLI2S_TARGET_FREQ_MHZ (27 * 4)
  86 #define PLLI2S_R               2
  87
  88 /**
  89   * @}
  90   */
  91
  92 /** @addtogroup APM32F4xx_System_Private_Variables
  93   * @{
  94   */
  95 uint32_t SystemCoreClock = 16000000;
  96 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
  97 const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
  98
  99 uint32_t pll_src, pll_input, pll_m, pll_p, pll_n, pll_q;
 100
 101 typedef struct pllConfig_s {
 102   uint16_t mhz; // target SYSCLK
 103   uint16_t n;
 104   uint16_t p;
 105   uint16_t q;
 106 } pllConfig_t;
 107
 108 // PLL parameters for PLL input = 1MHz.
 109 // For PLL input = 2MHz, divide n by 2; see SystemInitPLLParameters below.
 110
 111 static const pllConfig_t overclockLevels[] = {
 112   { 168, 336, 2,  7 },  // 168 MHz
 113   { 192, 384, 2,  8 },  // 192 MHz
 114   { 216, 432, 2,  9 },  // 216 MHz
 115   { 240, 480, 2,  10 }  // 240 MHz
 116 };
 117
 118 /**
 119   * @}
 120   */
 121
 122 /** @addtogroup APM32F4xx_System_Private_FunctionPrototypes
 123   * @{
 124   */
 125
 126 /**
 127   * @}
 128   */
 129
 130 /** @addtogroup APM32F4xx_System_Private_Functions
 131   * @{
 132   */
 133
 134 static void SystemInitPLLParameters(void);
 135 void DAL_SysClkConfig(void);
 136 void DAL_ErrorHandler(void);
 137
 138 /**
 139  * @brief     Setup the microcontroller system
 140  *
 141  * @param     None
 142  *
 143  * @retval    None
 144  */
 145 void SystemInit(void)
 146 {
 147     initialiseMemorySections();
 148
 149     /* FPU settings */
 150 #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
 151       SCB->CPACR |= ((3UL << 10U * 2U)|(3UL << 11U * 2U));  /* set CP10 and CP11 Full Access */
 152 #endif
 153
 154     /* Reset the RCM clock configuration to the default reset state */
 155     /* Set HSIEN bit */
 156     RCM->CTRL |= (uint32_t)0x00000001;
 157
 158     /* Reset CFG register */
 159     RCM->CFG = 0x00000000;
 160
 161     /* Reset HSEEN, CSSEN and PLL1EN bits */
 162     RCM->CTRL &= (uint32_t)0xFEF6FFFF;
 163
 164     /* Reset PLL1CFG register */
 165     RCM->PLL1CFG = 0x24003010;
 166
 167     /* Reset HSEBCFG bit */
 168     RCM->CTRL &= (uint32_t)0xFFFBFFFF;
 169
 170     /* Disable all interrupts */
 171     RCM->INT = 0x00000000;
 172
 173     /* Configure the Vector Table location add offset address */
 174     extern uint8_t isr_vector_table_flash_base;
 175     extern uint8_t isr_vector_table_base;
 176     extern uint8_t isr_vector_table_end;
 177
 178     if (&isr_vector_table_base != &isr_vector_table_flash_base) {
 179         memcpy(&isr_vector_table_base, &isr_vector_table_flash_base, (size_t) (&isr_vector_table_end - &isr_vector_table_base));
 180     }
 181
 182     SCB->VTOR = (uint32_t)&isr_vector_table_base;
 183 }
 184
 185 /**
 186    * @brief Update SystemCoreClock variable according to clock register values
 187  *          The SystemCoreClock variable contains the core clock (HCLK)
 188   *
 189   * @param  None
 190   * @retval None
 191   */
 192 void SystemCoreClockUpdate(void)
 193 {
 194     uint32_t sysClock = 0, pllvco = 0, pllc, pllClock, pllb;
 195
 196     uint32_t hse_value = persistentObjectRead(PERSISTENT_OBJECT_HSE_VALUE);
 197
 198     /* Get SYSCLK source */
 199     sysClock = RCM->CFG & RCM_CFG_SCLKSWSTS;
 200
 201     switch (sysClock)
 202     {
 203         case 0x00:  /* HSI used as system clock source */
 204             SystemCoreClock = HSI_VALUE;
 205             break;
 206
 207         case 0x04:  /* HSE used as system clock source */
 208             SystemCoreClock = hse_value;
 209             break;
 210
 211         case 0x08:  /* PLL used as system clock source */
 212             pllClock = (RCM->PLL1CFG & RCM_PLL1CFG_PLL1CLKS) >> 22;
 213             pllb = RCM->PLL1CFG & RCM_PLL1CFG_PLLB;
 214
 215             if (pllClock != 0)
 216             {
 217                 /* HSE used as PLL clock source */
 218                 pllvco = (hse_value / pllb) * ((RCM->PLL1CFG & RCM_PLL1CFG_PLL1A) >> 6);
 219             }
 220             else
 221             {
 222                 /* HSI used as PLL clock source */
 223                 pllvco = (HSI_VALUE / pllb) * ((RCM->PLL1CFG & RCM_PLL1CFG_PLL1A) >> 6);
 224             }
 225
 226             pllc = (((RCM->PLL1CFG & RCM_PLL1CFG_PLL1C) >> 16) + 1 ) * 2;
 227             SystemCoreClock = pllvco / pllc;
 228             break;
 229
 230         default:
 231             SystemCoreClock = HSI_VALUE;
 232             break;
 233     }
 234
 235     /* Compute HCLK frequency --------------------------------------------------*/
 236     /* Get HCLK prescaler */
 237     sysClock = AHBPrescTable[((RCM->CFG & RCM_CFG_AHBPSC) >> 4)];
 238     /* HCLK frequency */
 239     SystemCoreClock >>= sysClock;
 240 }
 241
 242 /**
 243  * @brief   System clock configuration
 244  *
 245  * @param   None
 246  *
 247  * @retval  None
 248  */
 249 void DAL_SysClkConfig(void)
 250 {
 251     RCM_ClkInitTypeDef RCM_ClkInitStruct = {0U};
 252     RCM_OscInitTypeDef RCM_OscInitStruct = {0U};
 253     RCM_PeriphCLKInitTypeDef PeriphClk_InitStruct = {0U};
 254
 255     uint32_t hse_value = persistentObjectRead(PERSISTENT_OBJECT_HSE_VALUE);
 256     uint32_t hse_mhz = hse_value / 1000000;
 257
 258     if (hse_value == 0) {
 259         pll_src = RCM_PLLSOURCE_HSI;
 260
 261         // HSI is fixed at 16MHz
 262         pll_m = 8;
 263         pll_input = 2;
 264     }
 265     else {
 266         // HSE frequency is given
 267         pll_src = RCM_PLLSOURCE_HSE;
 268
 269         pll_m = hse_mhz /  2;
 270         if (pll_m * 2 != hse_mhz) {
 271             pll_m = hse_mhz;
 272         }
 273         pll_input = hse_mhz / pll_m;
 274     }
 275
 276     SystemInitPLLParameters();
 277
 278     /* Enable PMU clock */
 279     __DAL_RCM_PMU_CLK_ENABLE();
 280
 281     /* Configure the voltage scaling value */
 282     __DAL_PMU_VOLTAGESCALING_CONFIG(PMU_REGULATOR_VOLTAGE_SCALE1);
 283
 284     /* Enable HSE Oscillator and activate PLL with HSE as source */
 285     RCM_OscInitStruct.OscillatorType    = RCM_OSCILLATORTYPE_HSI | RCM_OSCILLATORTYPE_HSE | RCM_OSCILLATORTYPE_LSI;
 286     RCM_OscInitStruct.HSEState          = RCM_HSE_ON;
 287     RCM_OscInitStruct.HSIState          = RCM_HSI_ON;
 288     RCM_OscInitStruct.LSIState          = RCM_LSI_ON;
 289     RCM_OscInitStruct.PLL.PLLState      = RCM_PLL_ON;
 290     RCM_OscInitStruct.PLL.PLLSource     = pll_src;
 291     RCM_OscInitStruct.PLL.PLLB          = pll_m;
 292     RCM_OscInitStruct.PLL.PLL1A         = pll_n;
 293     RCM_OscInitStruct.PLL.PLL1C         = pll_p;
 294     RCM_OscInitStruct.PLL.PLLD          = pll_q;
 295     RCM_OscInitStruct.HSICalibrationValue = 0x10;
 296     if(DAL_RCM_OscConfig(&RCM_OscInitStruct) != DAL_OK)
 297     {
 298         DAL_ErrorHandler();
 299     }
 300
 301     /* Configure clock */
 302     RCM_ClkInitStruct.ClockType         = (RCM_CLOCKTYPE_SYSCLK | RCM_CLOCKTYPE_HCLK | RCM_CLOCKTYPE_PCLK1 | RCM_CLOCKTYPE_PCLK2);
 303     RCM_ClkInitStruct.SYSCLKSource      = RCM_SYSCLKSOURCE_PLLCLK;
 304     RCM_ClkInitStruct.AHBCLKDivider     = RCM_SYSCLK_DIV1;
 305     RCM_ClkInitStruct.APB1CLKDivider    = RCM_HCLK_DIV4;
 306     RCM_ClkInitStruct.APB2CLKDivider    = RCM_HCLK_DIV2;
 307     if(DAL_RCM_ClockConfig(&RCM_ClkInitStruct, FLASH_LATENCY_5) != DAL_OK)
 308     {
 309         DAL_ErrorHandler();
 310     }
 311
 312     /* I2S clock */
 313     // Configure PLLI2S for 27MHz operation
 314     // Use pll_input (1 or 2) to derive multiplier N for
 315     // 108MHz (27 * 4) PLLI2SCLK with R divider fixed at 2.
 316     // 108MHz will further be prescaled by 4 by mcoInit.
 317
 318     uint32_t plli2s_n = (PLLI2S_TARGET_FREQ_MHZ * PLLI2S_R) / pll_input;
 319
 320     PeriphClk_InitStruct.PeriphClockSelection   = RCM_PERIPHCLK_I2S;
 321     PeriphClk_InitStruct.PLLI2S.PLL2A           = plli2s_n;
 322     PeriphClk_InitStruct.PLLI2S.PLL2C           = PLLI2S_R;
 323     if (DAL_RCMEx_PeriphCLKConfig(&PeriphClk_InitStruct) != DAL_OK)
 324     {
 325         DAL_ErrorHandler();
 326     }
 327 }
 328
 329 /**
 330  * @brief     Error handler
 331  *
 332  * @param     None
 333  *
 334  * @retval    None
 335  */
 336 void DAL_ErrorHandler(void)
 337 {
 338     /* When the function is needed, this function
 339        could be implemented in the user file
 340     */
 341     while(1)
 342     {
 343     }
 344 }
 345
 346 LOCAL_UNUSED_FUNCTION static void AssertFailedHandler(uint8_t *file, uint32_t line)
 347 {
 348     /* When the function is needed, this function
 349        could be implemented in the user file
 350     */
 351     UNUSED(file);
 352     UNUSED(line);
 353     while(1)
 354     {
 355     }
 356 }
 357
 358 /**
 359  * @brief     Get the SYSCLK source
 360  *
 361  * @param     None
 362  *
 363  * @retval    The SYSCLK source
 364  *           - 0x00: HSI used as system clock source
 365  *           - 0x01: HSE used as system clock source
 366  *           - 0x02: PLL used as system clock source
 367  */
 368 int SystemSYSCLKSource(void)
 369 {
 370     return (int)((RCM->CFG & RCM_CFG_SCLKSWSTS) >> 2);
 371 }
 372
 373 /**
 374  * @brief     Get the PLL source
 375  *
 376  * @param     None
 377  *
 378  * @retval    The PLL source
 379  *           - 0x00: HSI used as PLL clock source
 380  *           - 0x01: HSE used as PLL clock source
 381  */
 382 int SystemPLLSource(void)
 383 {
 384     return (int)((RCM->PLL1CFG & RCM_PLL1CFG_PLL1CLKS) >> 22);
 385 }
 386
 387 /**
 388  * @brief Reboot the system if necessary after changing the overclock level
 389  *
 390  * @param overclockLevel
 391  *
 392  * @retval None
 393  */
 394 void OverclockRebootIfNecessary(uint32_t overclockLevel)
 395 {
 396     if (overclockLevel >= ARRAYLEN(overclockLevels)) {
 397         return;
 398     }
 399
 400     const pllConfig_t * const pll = overclockLevels + overclockLevel;
 401
 402     // Reboot to adjust overclock frequency
 403     if (SystemCoreClock != pll->mhz * 1000000U) {
 404         persistentObjectWrite(PERSISTENT_OBJECT_OVERCLOCK_LEVEL, overclockLevel);
 405         __disable_irq();
 406         NVIC_SystemReset();
 407     }
 408 }
 409
 410 /**
 411  * @brief Set the HSE value
 412  *
 413  * @param frequency
 414  *
 415  * @retval None
 416  */
 417 void systemClockSetHSEValue(uint32_t frequency)
 418 {
 419     uint32_t hse_value = persistentObjectRead(PERSISTENT_OBJECT_HSE_VALUE);
 420
 421     if (hse_value != frequency) {
 422         persistentObjectWrite(PERSISTENT_OBJECT_HSE_VALUE, frequency);
 423         __disable_irq();
 424         NVIC_SystemReset();
 425     }
 426 }
 427
 428 /**
 429  * @brief    Initialize the PLL parameters
 430  *
 431  * @param    None
 432  *
 433  * @retval   None
 434  *
 435  */
 436 static void SystemInitPLLParameters(void)
 437 {
 438     /* PLL setting for overclocking */
 439
 440     uint32_t currentOverclockLevel = persistentObjectRead(PERSISTENT_OBJECT_OVERCLOCK_LEVEL);
 441
 442     if (currentOverclockLevel >= ARRAYLEN(overclockLevels)) {
 443       return;
 444     }
 445
 446     const pllConfig_t * const pll = overclockLevels + currentOverclockLevel;
 447
 448     pll_n = pll->n / pll_input;
 449     pll_p = pll->p;
 450     pll_q = pll->q;
 451 }
 452
 453 /**
 454   * @}
 455   */
 456
 457 /**
 458   * @}
 459   */
 460
 461 /**
 462   * @}
 463   */