src/platform/AT32/system_at32f43x.c

   1 /*
   2  * This file is part of Betaflight.
   3  *
   4  * Betaflight is free software. You can redistribute this software
   5  * and/or modify this software under the terms of the GNU General
   6  * Public License as published by the Free Software Foundation,
   7  * either version 3 of the License, or (at your option) any later
   8  * version.
   9  *
  10  * Betaflight is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  13  *
  14  * See the GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public
  17  * License along with this software.
  18  *
  19  * If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <stdbool.h>
  23 #include <stdint.h>
  24
  25 #include "platform.h"
  26
  27 #include "drivers/exti.h"
  28 #include "drivers/nvic.h"
  29 #include "drivers/system.h"
  30 #include "drivers/persistent.h"
  31 #include "at32f435_437_clock.h"
  32
  33 // See RM_AT32F435_437_EN_V2.05.pdf reference manual table 5-6 for more info.
  34 #if 256 < TARGET_FLASH_SIZE
  35 #define USD_EOPB0_SRAM_CONFIG_MASK 0x7
  36 #else
  37 #define USD_EOPB0_SRAM_CONFIG_MASK 0x3
  38 #endif
  39
  40 static flash_usd_eopb0_type get_sram_config(void)
  41 {
  42     extern uint32_t _SRAM_SIZE; // Defined in linker file
  43     switch ((uint32_t)&_SRAM_SIZE) {
  44 #if 256 == TARGET_FLASH_SIZE
  45     case 448:
  46         return FLASH_EOPB0_SRAM_448K;
  47     case 512:
  48         return FLASH_EOPB0_SRAM_512K;
  49     case 384:
  50     default:
  51         return FLASH_EOPB0_SRAM_384K;
  52 #elif 448 == TARGET_FLASH_SIZE
  53     case 256:
  54         return FLASH_EOPB0_SRAM_256K;
  55     case 320:
  56         return FLASH_EOPB0_SRAM_320K;
  57     case 384:
  58         return FLASH_EOPB0_SRAM_384K;
  59     case 448:
  60         return FLASH_EOPB0_SRAM_448K;
  61     case 512:
  62         return FLASH_EOPB0_SRAM_512K;
  63     case 192:
  64     default:
  65         return FLASH_EOPB0_SRAM_192K;
  66 #elif 1024 <= TARGET_FLASH_SIZE
  67     case 128:
  68         return FLASH_EOPB0_SRAM_128K;
  69     case 256:
  70         return FLASH_EOPB0_SRAM_256K;
  71     case 320:
  72         return FLASH_EOPB0_SRAM_320K;
  73     case 384:
  74         return FLASH_EOPB0_SRAM_384K;
  75     case 448:
  76         return FLASH_EOPB0_SRAM_448K;
  77     case 512:
  78         return FLASH_EOPB0_SRAM_512K;
  79     case 192:
  80     default:
  81         return FLASH_EOPB0_SRAM_192K;
  82 #endif
  83     }
  84 }
  85
  86 static void init_sram_config(void)
  87 {
  88     // Make sure the SRAM config is correct
  89     const flash_usd_eopb0_type sram_cfg = get_sram_config();
  90     if (((USD->eopb0) & USD_EOPB0_SRAM_CONFIG_MASK) != sram_cfg) {
  91         flash_unlock();
  92         flash_user_system_data_erase();
  93         flash_eopb0_config(sram_cfg);
  94         systemReset();
  95     }
  96 }
  97
  98 void systemReset(void)
  99 {
 100     __disable_irq();
 101     NVIC_SystemReset();
 102 }
 103
 104 void systemResetToBootloader(bootloaderRequestType_e requestType)
 105 {
 106     switch (requestType) {
 107     case BOOTLOADER_REQUEST_ROM:
 108     default:
 109         persistentObjectWrite(PERSISTENT_OBJECT_RESET_REASON, RESET_BOOTLOADER_REQUEST_ROM);
 110
 111         break;
 112     }
 113
 114     __disable_irq();
 115     NVIC_SystemReset();
 116 }
 117
 118 typedef void resetHandler_t(void);
 119
 120 typedef struct isrVector_s {
 121     __I uint32_t    stackEnd;
 122     resetHandler_t *resetHandler;
 123 } isrVector_t;
 124
 125 static void checkForBootLoaderRequest(void)
 126 {
 127     volatile uint32_t bootloaderRequest = persistentObjectRead(PERSISTENT_OBJECT_RESET_REASON);
 128
 129     if (bootloaderRequest != RESET_BOOTLOADER_REQUEST_ROM) {
 130         return;
 131     }
 132     persistentObjectWrite(PERSISTENT_OBJECT_RESET_REASON, RESET_NONE);
 133
 134     extern isrVector_t system_isr_vector_table_base;
 135
 136     __set_MSP(system_isr_vector_table_base.stackEnd);
 137     system_isr_vector_table_base.resetHandler();
 138     while (1);
 139 }
 140
 141 void enableGPIOPowerUsageAndNoiseReductions(void)
 142 {
 143     //enable all needed periph
 144     crm_periph_clock_enable(
 145             CRM_GPIOA_PERIPH_CLOCK    |
 146             CRM_GPIOB_PERIPH_CLOCK    |
 147             CRM_GPIOC_PERIPH_CLOCK    |
 148             CRM_GPIOD_PERIPH_CLOCK    |
 149             CRM_GPIOE_PERIPH_CLOCK    |
 150             CRM_DMA1_PERIPH_CLOCK     |
 151             CRM_DMA2_PERIPH_CLOCK     |
 152             0,TRUE);
 153 }
 154
 155 bool isMPUSoftReset(void)
 156 {
 157     if (cachedRccCsrValue & CRM_SW_RESET_FLAG)
 158         return true;
 159     else
 160         return false;
 161 }
 162
 163 void systemInit(void)
 164 {
 165     init_sram_config();
 166
 167     persistentObjectInit();
 168
 169     checkForBootLoaderRequest();
 170
 171     system_clock_config();//config system clock to 288mhz usb 48mhz
 172
 173     // Configure NVIC preempt/priority groups
 174     nvic_priority_group_config(NVIC_PRIORITY_GROUPING);
 175
 176     // cache RCC->CSR value to use it in isMPUSoftReset() and others
 177     cachedRccCsrValue = CRM->ctrlsts;
 178
 179     // Although VTOR is already loaded with a possible vector table in RAM,
 180     // removing the call to NVIC_SetVectorTable causes USB not to become active,
 181     extern uint8_t isr_vector_table_base;
 182     nvic_vector_table_set((uint32_t)&isr_vector_table_base, 0x0);
 183
 184     crm_periph_clock_enable(CRM_OTGFS2_PERIPH_CLOCK|CRM_OTGFS1_PERIPH_CLOCK,FALSE);
 185
 186     CRM->ctrlsts_bit.rstfc = TRUE;
 187
 188     enableGPIOPowerUsageAndNoiseReductions();
 189
 190     // Init cycle counter
 191     cycleCounterInit();
 192
 193     // SysTick
 194     SysTick_Config(system_core_clock / 1000);
 195 }