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Merge pull request #11494 from haslinghuis/dshot_gpio
[betaflight.git] / lib / main / STM32F4 / Drivers / STM32F4xx_HAL_Driver / Inc / stm32f4xx_ll_adc.h
blob2cfeb23d1ab75fa22fdfede4e8a308fc22a0dda7
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_adc.h
4 * @author MCD Application Team
5 * @version V1.7.1
6 * @date 14-April-2017
7 * @brief Header file of ADC LL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_LL_ADC_H
40 #define __STM32F4xx_LL_ADC_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f4xx.h"
48
49 /** @addtogroup STM32F4xx_LL_Driver
50 * @{
51 */
52
53 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
54
55 /** @defgroup ADC_LL ADC
56 * @{
57 */
58
59 /* Private types -------------------------------------------------------------*/
60 /* Private variables ---------------------------------------------------------*/
61
62 /* Private constants ---------------------------------------------------------*/
63 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
64 * @{
65 */
66
67 /* Internal mask for ADC group regular sequencer: */
68 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
69 /* - sequencer register offset */
70 /* - sequencer rank bits position into the selected register */
71
72 /* Internal register offset for ADC group regular sequencer configuration */
73 /* (offset placed into a spare area of literal definition) */
74 #define ADC_SQR1_REGOFFSET 0x00000000U
75 #define ADC_SQR2_REGOFFSET 0x00000100U
76 #define ADC_SQR3_REGOFFSET 0x00000200U
77 #define ADC_SQR4_REGOFFSET 0x00000300U
78
79 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
80 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
81
82 /* Definition of ADC group regular sequencer bits information to be inserted */
83 /* into ADC group regular sequencer ranks literals definition. */
84 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
85 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
86 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
87 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
88 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
89 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
90 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
91 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
92 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
93 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
94 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
95 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
96 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
97 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
98 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
99 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
100
101 /* Internal mask for ADC group injected sequencer: */
102 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
103 /* - data register offset */
104 /* - offset register offset */
105 /* - sequencer rank bits position into the selected register */
106
107 /* Internal register offset for ADC group injected data register */
108 /* (offset placed into a spare area of literal definition) */
109 #define ADC_JDR1_REGOFFSET 0x00000000U
110 #define ADC_JDR2_REGOFFSET 0x00000100U
111 #define ADC_JDR3_REGOFFSET 0x00000200U
112 #define ADC_JDR4_REGOFFSET 0x00000300U
113
114 /* Internal register offset for ADC group injected offset configuration */
115 /* (offset placed into a spare area of literal definition) */
116 #define ADC_JOFR1_REGOFFSET 0x00000000U
117 #define ADC_JOFR2_REGOFFSET 0x00001000U
118 #define ADC_JOFR3_REGOFFSET 0x00002000U
119 #define ADC_JOFR4_REGOFFSET 0x00003000U
120
121 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
122 #define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)
123 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
124
125 /* Internal mask for ADC group regular trigger: */
126 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
127 /* - regular trigger source */
128 /* - regular trigger edge */
129 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
130
131 /* Mask containing trigger source masks for each of possible */
132 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
133 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
134 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4U * 0U)) | \
135 ((ADC_CR2_EXTSEL) >> (4U * 1U)) | \
136 ((ADC_CR2_EXTSEL) >> (4U * 2U)) | \
137 ((ADC_CR2_EXTSEL) >> (4U * 3U)))
138
139 /* Mask containing trigger edge masks for each of possible */
140 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
141 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
142 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4U * 0U)) | \
143 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \
144 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \
145 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U)))
146
147 /* Definition of ADC group regular trigger bits information. */
148 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */
149 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (28U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */
150
151
152
153 /* Internal mask for ADC group injected trigger: */
154 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
155 /* - injected trigger source */
156 /* - injected trigger edge */
157 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
158
159 /* Mask containing trigger source masks for each of possible */
160 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
161 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
162 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4U * 0U)) | \
163 ((ADC_CR2_JEXTSEL) >> (4U * 1U)) | \
164 ((ADC_CR2_JEXTSEL) >> (4U * 2U)) | \
165 ((ADC_CR2_JEXTSEL) >> (4U * 3U)))
166
167 /* Mask containing trigger edge masks for each of possible */
168 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
169 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
170 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4U * 0U)) | \
171 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \
172 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \
173 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U)))
174
175 /* Definition of ADC group injected trigger bits information. */
176 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */
177 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */
178
179 /* Internal mask for ADC channel: */
180 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
181 /* - channel identifier defined by number */
182 /* - channel differentiation between external channels (connected to */
183 /* GPIO pins) and internal channels (connected to internal paths) */
184 /* - channel sampling time defined by SMPRx register offset */
185 /* and SMPx bits positions into SMPRx register */
186 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)
187 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
188 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
189 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
190 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
191
192 /* Channel differentiation between external and internal channels */
193 #define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000U /* Marker of internal channel */
194 #define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000U /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
195 #define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */
196 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)
197
198 /* Internal register offset for ADC channel sampling time configuration */
199 /* (offset placed into a spare area of literal definition) */
200 #define ADC_SMPR1_REGOFFSET 0x00000000U
201 #define ADC_SMPR2_REGOFFSET 0x02000000U
202 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
203
204 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000U
205 #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
206
207 /* Definition of channels ID number information to be inserted into */
208 /* channels literals definition. */
209 #define ADC_CHANNEL_0_NUMBER 0x00000000U
210 #define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)
211 #define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )
212 #define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
213 #define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )
214 #define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
215 #define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
216 #define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
217 #define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 )
218 #define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)
219 #define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 )
220 #define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
221 #define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 )
222 #define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
223 #define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
224 #define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
225 #define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 )
226 #define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)
227 #define ADC_CHANNEL_18_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1 )
228
229 /* Definition of channels sampling time information to be inserted into */
230 /* channels literals definition. */
231 #define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
232 #define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
233 #define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
234 #define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
235 #define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
236 #define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
237 #define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
238 #define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
239 #define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
240 #define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
241 #define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
242 #define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
243 #define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
244 #define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
245 #define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
246 #define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
247 #define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
248 #define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
249 #define ADC_CHANNEL_18_SMP (ADC_SMPR1_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP18) */
250
251 /* Internal mask for ADC analog watchdog: */
252 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
253 /* (concatenation of multiple bits used in different analog watchdogs, */
254 /* (feature of several watchdogs not available on all STM32 families)). */
255 /* - analog watchdog 1: monitored channel defined by number, */
256 /* selection of ADC group (ADC groups regular and-or injected). */
257
258 /* Internal register offset for ADC analog watchdog channel configuration */
259 #define ADC_AWD_CR1_REGOFFSET 0x00000000U
260
261 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
262
263 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
264 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
265
266 /* Internal register offset for ADC analog watchdog threshold configuration */
267 #define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000U
268 #define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001U
269 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
270
271 /* ADC registers bits positions */
272 #define ADC_CR1_RES_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */
273 #define ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
274 /**
275 * @}
276 */
277
278
279 /* Private macros ------------------------------------------------------------*/
280 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
281 * @{
282 */
283
284 /**
285 * @brief Driver macro reserved for internal use: isolate bits with the
286 * selected mask and shift them to the register LSB
287 * (shift mask on register position bit 0).
288 * @param __BITS__ Bits in register 32 bits
289 * @param __MASK__ Mask in register 32 bits
290 * @retval Bits in register 32 bits
291 */
292 #define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
293 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
294
295 /**
296 * @brief Driver macro reserved for internal use: set a pointer to
297 * a register from a register basis from which an offset
298 * is applied.
299 * @param __REG__ Register basis from which the offset is applied.
300 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
301 * @retval Pointer to register address
302 */
303 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
304 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
305
306 /**
307 * @}
308 */
309
310
311 /* Exported types ------------------------------------------------------------*/
312 #if defined(USE_FULL_LL_DRIVER)
313 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
314 * @{
315 */
316
317 /**
318 * @brief Structure definition of some features of ADC common parameters
319 * and multimode
320 * (all ADC instances belonging to the same ADC common instance).
321 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
322 * is conditioned to ADC instances state (all ADC instances
323 * sharing the same ADC common instance):
324 * All ADC instances sharing the same ADC common instance must be
325 * disabled.
326 */
327 typedef struct
328 {
329 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
330 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
331
332 This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
333
334 #if defined(ADC_MULTIMODE_SUPPORT)
335 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
336 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
337
338 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
339
340 uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
341 This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
342
343 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
344
345 uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
346 This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
347
348 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
349 #endif /* ADC_MULTIMODE_SUPPORT */
350
351 } LL_ADC_CommonInitTypeDef;
352
353 /**
354 * @brief Structure definition of some features of ADC instance.
355 * @note These parameters have an impact on ADC scope: ADC instance.
356 * Affects both group regular and group injected (availability
357 * of ADC group injected depends on STM32 families).
358 * Refer to corresponding unitary functions into
359 * @ref ADC_LL_EF_Configuration_ADC_Instance .
360 * @note The setting of these parameters by function @ref LL_ADC_Init()
361 * is conditioned to ADC state:
362 * ADC instance must be disabled.
363 * This condition is applied to all ADC features, for efficiency
364 * and compatibility over all STM32 families. However, the different
365 * features can be set under different ADC state conditions
366 * (setting possible with ADC enabled without conversion on going,
367 * ADC enabled with conversion on going, ...)
368 * Each feature can be updated afterwards with a unitary function
369 * and potentially with ADC in a different state than disabled,
370 * refer to description of each function for setting
371 * conditioned to ADC state.
372 */
373 typedef struct
374 {
375 uint32_t Resolution; /*!< Set ADC resolution.
376 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
377
378 This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
379
380 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
381 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
382
383 This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
384
385 uint32_t SequencersScanMode; /*!< Set ADC scan selection.
386 This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION
387
388 This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */
389
390 } LL_ADC_InitTypeDef;
391
392 /**
393 * @brief Structure definition of some features of ADC group regular.
394 * @note These parameters have an impact on ADC scope: ADC group regular.
395 * Refer to corresponding unitary functions into
396 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
397 * (functions with prefix "REG").
398 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
399 * is conditioned to ADC state:
400 * ADC instance must be disabled.
401 * This condition is applied to all ADC features, for efficiency
402 * and compatibility over all STM32 families. However, the different
403 * features can be set under different ADC state conditions
404 * (setting possible with ADC enabled without conversion on going,
405 * ADC enabled with conversion on going, ...)
406 * Each feature can be updated afterwards with a unitary function
407 * and potentially with ADC in a different state than disabled,
408 * refer to description of each function for setting
409 * conditioned to ADC state.
410 */
411 typedef struct
412 {
413 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
414 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
415 @note On this STM32 serie, setting of external trigger edge is performed
416 using function @ref LL_ADC_REG_StartConversionExtTrig().
417
418 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
419
420 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
421 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
422 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
423
424 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
425
426 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
427 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
428 @note This parameter has an effect only if group regular sequencer is enabled
429 (scan length of 2 ranks or more).
430
431 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
432
433 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
434 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
435 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
436
437 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
438
439 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
440 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
441
442 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
443
444 } LL_ADC_REG_InitTypeDef;
445
446 /**
447 * @brief Structure definition of some features of ADC group injected.
448 * @note These parameters have an impact on ADC scope: ADC group injected.
449 * Refer to corresponding unitary functions into
450 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
451 * (functions with prefix "INJ").
452 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
453 * is conditioned to ADC state:
454 * ADC instance must be disabled.
455 * This condition is applied to all ADC features, for efficiency
456 * and compatibility over all STM32 families. However, the different
457 * features can be set under different ADC state conditions
458 * (setting possible with ADC enabled without conversion on going,
459 * ADC enabled with conversion on going, ...)
460 * Each feature can be updated afterwards with a unitary function
461 * and potentially with ADC in a different state than disabled,
462 * refer to description of each function for setting
463 * conditioned to ADC state.
464 */
465 typedef struct
466 {
467 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
468 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
469 @note On this STM32 serie, setting of external trigger edge is performed
470 using function @ref LL_ADC_INJ_StartConversionExtTrig().
471
472 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
473
474 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
475 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
476 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
477
478 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
479
480 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
481 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
482 @note This parameter has an effect only if group injected sequencer is enabled
483 (scan length of 2 ranks or more).
484
485 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
486
487 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
488 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
489 Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
490
491 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
492
493 } LL_ADC_INJ_InitTypeDef;
494
495 /**
496 * @}
497 */
498 #endif /* USE_FULL_LL_DRIVER */
499
500 /* Exported constants --------------------------------------------------------*/
501 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
502 * @{
503 */
504
505 /** @defgroup ADC_LL_EC_FLAG ADC flags
506 * @brief Flags defines which can be used with LL_ADC_ReadReg function
507 * @{
508 */
509 #define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */
510 #define LL_ADC_FLAG_EOCS ADC_SR_EOC /*!< ADC flag ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
511 #define LL_ADC_FLAG_OVR ADC_SR_OVR /*!< ADC flag ADC group regular overrun */
512 #define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */
513 #define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
514 #define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */
515 #if defined(ADC_MULTIMODE_SUPPORT)
516 #define LL_ADC_FLAG_EOCS_MST ADC_CSR_EOC1 /*!< ADC flag ADC multimode master group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
517 #define LL_ADC_FLAG_EOCS_SLV1 ADC_CSR_EOC2 /*!< ADC flag ADC multimode slave 1 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
518 #define LL_ADC_FLAG_EOCS_SLV2 ADC_CSR_EOC3 /*!< ADC flag ADC multimode slave 2 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
519 #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR1 /*!< ADC flag ADC multimode master group regular overrun */
520 #define LL_ADC_FLAG_OVR_SLV1 ADC_CSR_OVR2 /*!< ADC flag ADC multimode slave 1 group regular overrun */
521 #define LL_ADC_FLAG_OVR_SLV2 ADC_CSR_OVR3 /*!< ADC flag ADC multimode slave 2 group regular overrun */
522 #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOC1 /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
523 #define LL_ADC_FLAG_JEOS_SLV1 ADC_CSR_JEOC2 /*!< ADC flag ADC multimode slave 1 group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
524 #define LL_ADC_FLAG_JEOS_SLV2 ADC_CSR_JEOC3 /*!< ADC flag ADC multimode slave 2 group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
525 #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1 /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
526 #define LL_ADC_FLAG_AWD1_SLV1 ADC_CSR_AWD2 /*!< ADC flag ADC multimode slave 1 analog watchdog 1 */
527 #define LL_ADC_FLAG_AWD1_SLV2 ADC_CSR_AWD3 /*!< ADC flag ADC multimode slave 2 analog watchdog 1 */
528 #endif
529 /**
530 * @}
531 */
532
533 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
534 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
535 * @{
536 */
537 #define LL_ADC_IT_EOCS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
538 #define LL_ADC_IT_OVR ADC_CR1_OVRIE /*!< ADC interruption ADC group regular overrun */
539 #define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
540 #define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */
541 /**
542 * @}
543 */
544
545 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
546 * @{
547 */
548 /* List of ADC registers intended to be used (most commonly) with */
549 /* DMA transfer. */
550 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
551 #define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000U /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
552 #if defined(ADC_MULTIMODE_SUPPORT)
553 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001U /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
554 #endif
555 /**
556 * @}
557 */
558
559 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
560 * @{
561 */
562 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000U /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
563 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 ( ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
564 #define LL_ADC_CLOCK_SYNC_PCLK_DIV6 (ADC_CCR_ADCPRE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 6 */
565 #define LL_ADC_CLOCK_SYNC_PCLK_DIV8 (ADC_CCR_ADCPRE_1 | ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 8 */
566 /**
567 * @}
568 */
569
570 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
571 * @{
572 */
573 /* Note: Other measurement paths to internal channels may be available */
574 /* (connections to other peripherals). */
575 /* If they are not listed below, they do not require any specific */
576 /* path enable. In this case, Access to measurement path is done */
577 /* only by selecting the corresponding ADC internal channel. */
578 #define LL_ADC_PATH_INTERNAL_NONE 0x00000000U /*!< ADC measurement pathes all disabled */
579 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */
580 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */
581 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATE) /*!< ADC measurement path to internal channel Vbat */
582 /**
583 * @}
584 */
585
586 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
587 * @{
588 */
589 #define LL_ADC_RESOLUTION_12B 0x00000000U /*!< ADC resolution 12 bits */
590 #define LL_ADC_RESOLUTION_10B ( ADC_CR1_RES_0) /*!< ADC resolution 10 bits */
591 #define LL_ADC_RESOLUTION_8B (ADC_CR1_RES_1 ) /*!< ADC resolution 8 bits */
592 #define LL_ADC_RESOLUTION_6B (ADC_CR1_RES_1 | ADC_CR1_RES_0) /*!< ADC resolution 6 bits */
593 /**
594 * @}
595 */
596
597 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
598 * @{
599 */
600 #define LL_ADC_DATA_ALIGN_RIGHT 0x00000000U /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
601 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
602 /**
603 * @}
604 */
605
606 /** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection
607 * @{
608 */
609 #define LL_ADC_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/
610 #define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */
611 /**
612 * @}
613 */
614
615 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
616 * @{
617 */
618 #define LL_ADC_GROUP_REGULAR 0x00000001U /*!< ADC group regular (available on all STM32 devices) */
619 #define LL_ADC_GROUP_INJECTED 0x00000002U /*!< ADC group injected (not available on all STM32 devices)*/
620 #define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003U /*!< ADC both groups regular and injected */
621 /**
622 * @}
623 */
624
625 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
626 * @{
627 */
628 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
629 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
630 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
631 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
632 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
633 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
634 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
635 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
636 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
637 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
638 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
639 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
640 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
641 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
642 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
643 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
644 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
645 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
646 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
647 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F4, ADC channel available only on ADC instance: ADC1. */
648 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32F4, ADC channel available only on ADC instance: ADC1. */
649 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
650 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32F4, ADC channel available only on ADC instance: ADC1. */
651 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx */
652 #if defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F411xE) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
653 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT) /*!< ADC internal channel connected to Temperature sensor. On STM32F4, ADC channel available only on ADC instance: ADC1. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
654 #endif /* STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F411xE || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
655 /**
656 * @}
657 */
658
659 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
660 * @{
661 */
662 #define LL_ADC_REG_TRIG_SOFTWARE 0x00000000U /*!< ADC group regular conversion trigger internal: SW start. */
663 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
664 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
665 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
666 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
667 #define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
668 #define LL_ADC_REG_TRIG_EXT_TIM2_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
669 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
670 #define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
671 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
672 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
673 #define LL_ADC_REG_TRIG_EXT_TIM5_CH1 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
674 #define LL_ADC_REG_TRIG_EXT_TIM5_CH2 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
675 #define LL_ADC_REG_TRIG_EXT_TIM5_CH3 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
676 #define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
677 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
678 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
679 /**
680 * @}
681 */
682
683 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
684 * @{
685 */
686 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
687 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CR2_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
688 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CR2_EXTEN_1 | ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
689 /**
690 * @}
691 */
692
693 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
694 * @{
695 */
696 #define LL_ADC_REG_CONV_SINGLE 0x00000000U /*!< ADC conversions are performed in single mode: one conversion per trigger */
697 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
698 /**
699 * @}
700 */
701
702 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
703 * @{
704 */
705 #define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000U /*!< ADC conversions are not transferred by DMA */
706 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
707 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DDS | ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
708 /**
709 * @}
710 */
711
712 /** @defgroup ADC_LL_EC_REG_FLAG_EOC_SELECTION ADC group regular - Flag EOC selection (unitary or sequence conversions)
713 * @{
714 */
715 #define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV 0x00000000U /*!< ADC flag EOC (end of unitary conversion) selected */
716 #define LL_ADC_REG_FLAG_EOC_UNITARY_CONV (ADC_CR2_EOCS) /*!< ADC flag EOS (end of sequence conversions) selected */
717 /**
718 * @}
719 */
720
721 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
722 * @{
723 */
724 #define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
725 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
726 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
727 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
728 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
729 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
730 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
731 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
732 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
733 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
734 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
735 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
736 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
737 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
738 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
739 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
740 /**
741 * @}
742 */
743
744 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
745 * @{
746 */
747 #define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group regular sequencer discontinuous mode disable */
748 #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
749 #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
750 #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
751 #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
752 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
753 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
754 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
755 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
756 /**
757 * @}
758 */
759
760 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
761 * @{
762 */
763 #define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
764 #define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
765 #define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
766 #define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
767 #define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
768 #define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
769 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
770 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
771 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
772 #define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
773 #define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
774 #define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
775 #define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
776 #define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
777 #define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
778 #define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
779 /**
780 * @}
781 */
782
783 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
784 * @{
785 */
786 #define LL_ADC_INJ_TRIG_SOFTWARE 0x00000000U /*!< ADC group injected conversion trigger internal: SW start. */
787 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
788 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
789 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
790 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
791 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH2 (ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
792 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
793 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH1 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
794 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH2 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
795 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (ADC_CR2_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
796 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
797 #define LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM5 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
798 #define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */
799 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
800 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH3 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
801 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
802 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
803 /**
804 * @}
805 */
806
807 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
808 * @{
809 */
810 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
811 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_CR2_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */
812 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_CR2_JEXTEN_1 | ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
813 /**
814 * @}
815 */
816
817 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
818 * @{
819 */
820 #define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000U /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
821 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
822 /**
823 * @}
824 */
825
826
827 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
828 * @{
829 */
830 #define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
831 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
832 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
833 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
834 /**
835 * @}
836 */
837
838 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
839 * @{
840 */
841 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group injected sequencer discontinuous mode disable */
842 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
843 /**
844 * @}
845 */
846
847 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
848 * @{
849 */
850 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001U) /*!< ADC group injected sequencer rank 1 */
851 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002U) /*!< ADC group injected sequencer rank 2 */
852 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003U) /*!< ADC group injected sequencer rank 3 */
853 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004U) /*!< ADC group injected sequencer rank 4 */
854 /**
855 * @}
856 */
857
858 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
859 * @{
860 */
861 #define LL_ADC_SAMPLINGTIME_3CYCLES 0x00000000U /*!< Sampling time 3 ADC clock cycles */
862 #define LL_ADC_SAMPLINGTIME_15CYCLES (ADC_SMPR1_SMP10_0) /*!< Sampling time 15 ADC clock cycles */
863 #define LL_ADC_SAMPLINGTIME_28CYCLES (ADC_SMPR1_SMP10_1) /*!< Sampling time 28 ADC clock cycles */
864 #define LL_ADC_SAMPLINGTIME_56CYCLES (ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0) /*!< Sampling time 56 ADC clock cycles */
865 #define LL_ADC_SAMPLINGTIME_84CYCLES (ADC_SMPR1_SMP10_2) /*!< Sampling time 84 ADC clock cycles */
866 #define LL_ADC_SAMPLINGTIME_112CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0) /*!< Sampling time 112 ADC clock cycles */
867 #define LL_ADC_SAMPLINGTIME_144CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1) /*!< Sampling time 144 ADC clock cycles */
868 #define LL_ADC_SAMPLINGTIME_480CYCLES (ADC_SMPR1_SMP10) /*!< Sampling time 480 ADC clock cycles */
869 /**
870 * @}
871 */
872
873 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
874 * @{
875 */
876 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
877 /**
878 * @}
879 */
880
881 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
882 * @{
883 */
884 #define LL_ADC_AWD_DISABLE 0x00000000U /*!< ADC analog watchdog monitoring disabled */
885 #define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
886 #define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
887 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
888 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
889 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
890 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
891 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
892 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
893 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
894 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
895 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
896 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
897 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
898 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
899 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
900 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
901 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
902 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
903 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
904 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
905 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
906 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
907 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
908 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
909 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
910 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
911 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
912 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
913 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
914 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
915 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
916 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
917 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
918 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
919 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
920 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
921 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
922 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
923 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
924 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
925 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
926 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
927 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
928 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
929 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
930 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
931 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
932 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
933 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
934 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
935 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
936 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
937 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
938 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
939 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
940 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
941 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
942 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
943 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
944 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
945 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
946 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
947 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
948 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
949 #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */
950 #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */
951 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
952 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
953 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
954 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
955 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx */
956 #if defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F411xE) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
957 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
958 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
959 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
960 #endif /* STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F411xE || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
961 /**
962 * @}
963 */
964
965 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
966 * @{
967 */
968 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */
969 #define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */
970 /**
971 * @}
972 */
973
974 #if defined(ADC_MULTIMODE_SUPPORT)
975 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
976 * @{
977 */
978 #define LL_ADC_MULTI_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */
979 #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
980 #define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
981 #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected simultaneous */
982 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
983 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
984 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
985 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
986 #if defined(ADC3)
987 #define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected simultaneous */
988 #define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected alternate trigger */
989 #define LL_ADC_MULTI_TRIPLE_INJ_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected simultaneous */
990 #define LL_ADC_MULTI_TRIPLE_REG_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: group regular simultaneous */
991 #define LL_ADC_MULTI_TRIPLE_REG_INTERL (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular interleaved */
992 #define LL_ADC_MULTI_TRIPLE_INJ_ALTERN (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
993 #endif
994 /**
995 * @}
996 */
997
998 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
999 * @{
1000 */
1001 #define LL_ADC_MULTI_REG_DMA_EACH_ADC 0x00000000U /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
1002 #define LL_ADC_MULTI_REG_DMA_LIMIT_1 ( ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */
1003 #define LL_ADC_MULTI_REG_DMA_LIMIT_2 ( ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words one by one, ADC2&1 then ADC1&3 then ADC3&2. */
1004 #define LL_ADC_MULTI_REG_DMA_LIMIT_3 ( ADC_CCR_DMA_0 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */
1005 #define LL_ADC_MULTI_REG_DMA_UNLMT_1 (ADC_CCR_DDS | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */
1006 #define LL_ADC_MULTI_REG_DMA_UNLMT_2 (ADC_CCR_DDS | ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words by pairs, ADC2&1 then ADC1&3 then ADC3&2. */
1007 #define LL_ADC_MULTI_REG_DMA_UNLMT_3 (ADC_CCR_DDS | ADC_CCR_DMA_0 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */
1008 /**
1009 * @}
1010 */
1011
1012 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
1013 * @{
1014 */
1015 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES 0x00000000U /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles*/
1016 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
1017 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
1018 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
1019 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
1020 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
1021 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
1022 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
1023 #define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 13 ADC clock cycles */
1024 #define LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 14 ADC clock cycles */
1025 #define LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 15 ADC clock cycles */
1026 #define LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 16 ADC clock cycles */
1027 #define LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 17 ADC clock cycles */
1028 #define LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 18 ADC clock cycles */
1029 #define LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 19 ADC clock cycles */
1030 #define LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 20 ADC clock cycles */
1031 /**
1032 * @}
1033 */
1034
1035 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
1036 * @{
1037 */
1038 #define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
1039 #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */
1040 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
1041 /**
1042 * @}
1043 */
1044
1045 #endif /* ADC_MULTIMODE_SUPPORT */
1046
1047
1048 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
1049 * @note Only ADC IP HW delays are defined in ADC LL driver driver,
1050 * not timeout values.
1051 * For details on delays values, refer to descriptions in source code
1052 * above each literal definition.
1053 * @{
1054 */
1055
1056 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
1057 /* not timeout values. */
1058 /* Timeout values for ADC operations are dependent to device clock */
1059 /* configuration (system clock versus ADC clock), */
1060 /* and therefore must be defined in user application. */
1061 /* Indications for estimation of ADC timeout delays, for this */
1062 /* STM32 serie: */
1063 /* - ADC enable time: maximum delay is 2us */
1064 /* (refer to device datasheet, parameter "tSTAB") */
1065 /* - ADC conversion time: duration depending on ADC clock and ADC */
1066 /* configuration. */
1067 /* (refer to device reference manual, section "Timing") */
1068
1069 /* Delay for internal voltage reference stabilization time. */
1070 /* Delay set to maximum value (refer to device datasheet, */
1071 /* parameter "tSTART"). */
1072 /* Unit: us */
1073 #define LL_ADC_DELAY_VREFINT_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */
1074
1075 /* Delay for temperature sensor stabilization time. */
1076 /* Literal set to maximum value (refer to device datasheet, */
1077 /* parameter "tSTART"). */
1078 /* Unit: us */
1079 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */
1080
1081 /**
1082 * @}
1083 */
1084
1085 /**
1086 * @}
1087 */
1088
1089
1090 /* Exported macro ------------------------------------------------------------*/
1091 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
1092 * @{
1093 */
1094
1095 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
1096 * @{
1097 */
1098
1099 /**
1100 * @brief Write a value in ADC register
1101 * @param __INSTANCE__ ADC Instance
1102 * @param __REG__ Register to be written
1103 * @param __VALUE__ Value to be written in the register
1104 * @retval None
1105 */
1106 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1107
1108 /**
1109 * @brief Read a value in ADC register
1110 * @param __INSTANCE__ ADC Instance
1111 * @param __REG__ Register to be read
1112 * @retval Register value
1113 */
1114 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1115 /**
1116 * @}
1117 */
1118
1119 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
1120 * @{
1121 */
1122
1123 /**
1124 * @brief Helper macro to get ADC channel number in decimal format
1125 * from literals LL_ADC_CHANNEL_x.
1126 * @note Example:
1127 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
1128 * will return decimal number "4".
1129 * @note The input can be a value from functions where a channel
1130 * number is returned, either defined with number
1131 * or with bitfield (only one bit must be set).
1132 * @param __CHANNEL__ This parameter can be one of the following values:
1133 * @arg @ref LL_ADC_CHANNEL_0
1134 * @arg @ref LL_ADC_CHANNEL_1
1135 * @arg @ref LL_ADC_CHANNEL_2
1136 * @arg @ref LL_ADC_CHANNEL_3
1137 * @arg @ref LL_ADC_CHANNEL_4
1138 * @arg @ref LL_ADC_CHANNEL_5
1139 * @arg @ref LL_ADC_CHANNEL_6
1140 * @arg @ref LL_ADC_CHANNEL_7
1141 * @arg @ref LL_ADC_CHANNEL_8
1142 * @arg @ref LL_ADC_CHANNEL_9
1143 * @arg @ref LL_ADC_CHANNEL_10
1144 * @arg @ref LL_ADC_CHANNEL_11
1145 * @arg @ref LL_ADC_CHANNEL_12
1146 * @arg @ref LL_ADC_CHANNEL_13
1147 * @arg @ref LL_ADC_CHANNEL_14
1148 * @arg @ref LL_ADC_CHANNEL_15
1149 * @arg @ref LL_ADC_CHANNEL_16
1150 * @arg @ref LL_ADC_CHANNEL_17
1151 * @arg @ref LL_ADC_CHANNEL_18
1152 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1153 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1154 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1155 *
1156 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
1157 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1158 * @retval Value between Min_Data=0 and Max_Data=18
1159 */
1160 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1161 (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
1162
1163 /**
1164 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
1165 * from number in decimal format.
1166 * @note Example:
1167 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1168 * will return a data equivalent to "LL_ADC_CHANNEL_4".
1169 * @param __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18
1170 * @retval Returned value can be one of the following values:
1171 * @arg @ref LL_ADC_CHANNEL_0
1172 * @arg @ref LL_ADC_CHANNEL_1
1173 * @arg @ref LL_ADC_CHANNEL_2
1174 * @arg @ref LL_ADC_CHANNEL_3
1175 * @arg @ref LL_ADC_CHANNEL_4
1176 * @arg @ref LL_ADC_CHANNEL_5
1177 * @arg @ref LL_ADC_CHANNEL_6
1178 * @arg @ref LL_ADC_CHANNEL_7
1179 * @arg @ref LL_ADC_CHANNEL_8
1180 * @arg @ref LL_ADC_CHANNEL_9
1181 * @arg @ref LL_ADC_CHANNEL_10
1182 * @arg @ref LL_ADC_CHANNEL_11
1183 * @arg @ref LL_ADC_CHANNEL_12
1184 * @arg @ref LL_ADC_CHANNEL_13
1185 * @arg @ref LL_ADC_CHANNEL_14
1186 * @arg @ref LL_ADC_CHANNEL_15
1187 * @arg @ref LL_ADC_CHANNEL_16
1188 * @arg @ref LL_ADC_CHANNEL_17
1189 * @arg @ref LL_ADC_CHANNEL_18
1190 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1191 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1192 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1193 *
1194 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
1195 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
1196 * (1) For ADC channel read back from ADC register,
1197 * comparison with internal channel parameter to be done
1198 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1199 */
1200 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1201 (((__DECIMAL_NB__) <= 9U) \
1202 ? ( \
1203 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1204 (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1205 ) \
1206 : \
1207 ( \
1208 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1209 (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1210 ) \
1211 )
1212
1213 /**
1214 * @brief Helper macro to determine whether the selected channel
1215 * corresponds to literal definitions of driver.
1216 * @note The different literal definitions of ADC channels are:
1217 * - ADC internal channel:
1218 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
1219 * - ADC external channel (channel connected to a GPIO pin):
1220 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
1221 * @note The channel parameter must be a value defined from literal
1222 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1223 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1224 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
1225 * must not be a value from functions where a channel number is
1226 * returned from ADC registers,
1227 * because internal and external channels share the same channel
1228 * number in ADC registers. The differentiation is made only with
1229 * parameters definitions of driver.
1230 * @param __CHANNEL__ This parameter can be one of the following values:
1231 * @arg @ref LL_ADC_CHANNEL_0
1232 * @arg @ref LL_ADC_CHANNEL_1
1233 * @arg @ref LL_ADC_CHANNEL_2
1234 * @arg @ref LL_ADC_CHANNEL_3
1235 * @arg @ref LL_ADC_CHANNEL_4
1236 * @arg @ref LL_ADC_CHANNEL_5
1237 * @arg @ref LL_ADC_CHANNEL_6
1238 * @arg @ref LL_ADC_CHANNEL_7
1239 * @arg @ref LL_ADC_CHANNEL_8
1240 * @arg @ref LL_ADC_CHANNEL_9
1241 * @arg @ref LL_ADC_CHANNEL_10
1242 * @arg @ref LL_ADC_CHANNEL_11
1243 * @arg @ref LL_ADC_CHANNEL_12
1244 * @arg @ref LL_ADC_CHANNEL_13
1245 * @arg @ref LL_ADC_CHANNEL_14
1246 * @arg @ref LL_ADC_CHANNEL_15
1247 * @arg @ref LL_ADC_CHANNEL_16
1248 * @arg @ref LL_ADC_CHANNEL_17
1249 * @arg @ref LL_ADC_CHANNEL_18
1250 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1251 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1252 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1253 *
1254 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
1255 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1256 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
1257 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1258 */
1259 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1260 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
1261
1262 /**
1263 * @brief Helper macro to convert a channel defined from parameter
1264 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1265 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1266 * to its equivalent parameter definition of a ADC external channel
1267 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
1268 * @note The channel parameter can be, additionally to a value
1269 * defined from parameter definition of a ADC internal channel
1270 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
1271 * a value defined from parameter definition of
1272 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1273 * or a value from functions where a channel number is returned
1274 * from ADC registers.
1275 * @param __CHANNEL__ This parameter can be one of the following values:
1276 * @arg @ref LL_ADC_CHANNEL_0
1277 * @arg @ref LL_ADC_CHANNEL_1
1278 * @arg @ref LL_ADC_CHANNEL_2
1279 * @arg @ref LL_ADC_CHANNEL_3
1280 * @arg @ref LL_ADC_CHANNEL_4
1281 * @arg @ref LL_ADC_CHANNEL_5
1282 * @arg @ref LL_ADC_CHANNEL_6
1283 * @arg @ref LL_ADC_CHANNEL_7
1284 * @arg @ref LL_ADC_CHANNEL_8
1285 * @arg @ref LL_ADC_CHANNEL_9
1286 * @arg @ref LL_ADC_CHANNEL_10
1287 * @arg @ref LL_ADC_CHANNEL_11
1288 * @arg @ref LL_ADC_CHANNEL_12
1289 * @arg @ref LL_ADC_CHANNEL_13
1290 * @arg @ref LL_ADC_CHANNEL_14
1291 * @arg @ref LL_ADC_CHANNEL_15
1292 * @arg @ref LL_ADC_CHANNEL_16
1293 * @arg @ref LL_ADC_CHANNEL_17
1294 * @arg @ref LL_ADC_CHANNEL_18
1295 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1296 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1297 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1298 *
1299 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
1300 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1301 * @retval Returned value can be one of the following values:
1302 * @arg @ref LL_ADC_CHANNEL_0
1303 * @arg @ref LL_ADC_CHANNEL_1
1304 * @arg @ref LL_ADC_CHANNEL_2
1305 * @arg @ref LL_ADC_CHANNEL_3
1306 * @arg @ref LL_ADC_CHANNEL_4
1307 * @arg @ref LL_ADC_CHANNEL_5
1308 * @arg @ref LL_ADC_CHANNEL_6
1309 * @arg @ref LL_ADC_CHANNEL_7
1310 * @arg @ref LL_ADC_CHANNEL_8
1311 * @arg @ref LL_ADC_CHANNEL_9
1312 * @arg @ref LL_ADC_CHANNEL_10
1313 * @arg @ref LL_ADC_CHANNEL_11
1314 * @arg @ref LL_ADC_CHANNEL_12
1315 * @arg @ref LL_ADC_CHANNEL_13
1316 * @arg @ref LL_ADC_CHANNEL_14
1317 * @arg @ref LL_ADC_CHANNEL_15
1318 * @arg @ref LL_ADC_CHANNEL_16
1319 * @arg @ref LL_ADC_CHANNEL_17
1320 * @arg @ref LL_ADC_CHANNEL_18
1321 */
1322 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1323 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1324
1325 /**
1326 * @brief Helper macro to determine whether the internal channel
1327 * selected is available on the ADC instance selected.
1328 * @note The channel parameter must be a value defined from parameter
1329 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1330 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1331 * must not be a value defined from parameter definition of
1332 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1333 * or a value from functions where a channel number is
1334 * returned from ADC registers,
1335 * because internal and external channels share the same channel
1336 * number in ADC registers. The differentiation is made only with
1337 * parameters definitions of driver.
1338 * @param __ADC_INSTANCE__ ADC instance
1339 * @param __CHANNEL__ This parameter can be one of the following values:
1340 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1341 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1342 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1343 *
1344 * (1) On STM32F4, parameter available only on ADC instance: ADC1.
1345 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1346 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1347 * Value "1" if the internal channel selected is available on the ADC instance selected.
1348 */
1349 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1350 ( \
1351 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1352 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1353 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
1354 )
1355 /**
1356 * @brief Helper macro to define ADC analog watchdog parameter:
1357 * define a single channel to monitor with analog watchdog
1358 * from sequencer channel and groups definition.
1359 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1360 * Example:
1361 * LL_ADC_SetAnalogWDMonitChannels(
1362 * ADC1, LL_ADC_AWD1,
1363 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
1364 * @param __CHANNEL__ This parameter can be one of the following values:
1365 * @arg @ref LL_ADC_CHANNEL_0
1366 * @arg @ref LL_ADC_CHANNEL_1
1367 * @arg @ref LL_ADC_CHANNEL_2
1368 * @arg @ref LL_ADC_CHANNEL_3
1369 * @arg @ref LL_ADC_CHANNEL_4
1370 * @arg @ref LL_ADC_CHANNEL_5
1371 * @arg @ref LL_ADC_CHANNEL_6
1372 * @arg @ref LL_ADC_CHANNEL_7
1373 * @arg @ref LL_ADC_CHANNEL_8
1374 * @arg @ref LL_ADC_CHANNEL_9
1375 * @arg @ref LL_ADC_CHANNEL_10
1376 * @arg @ref LL_ADC_CHANNEL_11
1377 * @arg @ref LL_ADC_CHANNEL_12
1378 * @arg @ref LL_ADC_CHANNEL_13
1379 * @arg @ref LL_ADC_CHANNEL_14
1380 * @arg @ref LL_ADC_CHANNEL_15
1381 * @arg @ref LL_ADC_CHANNEL_16
1382 * @arg @ref LL_ADC_CHANNEL_17
1383 * @arg @ref LL_ADC_CHANNEL_18
1384 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1385 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1386 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1387 *
1388 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
1389 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
1390 * (1) For ADC channel read back from ADC register,
1391 * comparison with internal channel parameter to be done
1392 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1393 * @param __GROUP__ This parameter can be one of the following values:
1394 * @arg @ref LL_ADC_GROUP_REGULAR
1395 * @arg @ref LL_ADC_GROUP_INJECTED
1396 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
1397 * @retval Returned value can be one of the following values:
1398 * @arg @ref LL_ADC_AWD_DISABLE
1399 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
1400 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
1401 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
1402 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
1403 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
1404 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
1405 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
1406 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
1407 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
1408 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
1409 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
1410 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
1411 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
1412 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
1413 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
1414 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
1415 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
1416 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
1417 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
1418 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
1419 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
1420 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
1421 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
1422 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
1423 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
1424 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
1425 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
1426 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
1427 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
1428 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
1429 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
1430 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
1431 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
1432 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
1433 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
1434 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
1435 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
1436 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
1437 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
1438 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
1439 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
1440 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
1441 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
1442 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
1443 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
1444 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
1445 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
1446 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
1447 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
1448 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
1449 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
1450 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
1451 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
1452 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
1453 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
1454 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
1455 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
1456 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
1457 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
1458 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
1459 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
1460 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
1461 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
1462 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2)
1463 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2)
1464 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2)
1465 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
1466 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1)
1467 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
1468 *
1469 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
1470 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1471 */
1472 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
1473 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
1474 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
1475 : \
1476 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
1477 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \
1478 : \
1479 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
1480 )
1481
1482 /**
1483 * @brief Helper macro to set the value of ADC analog watchdog threshold high
1484 * or low in function of ADC resolution, when ADC resolution is
1485 * different of 12 bits.
1486 * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
1487 * Example, with a ADC resolution of 8 bits, to set the value of
1488 * analog watchdog threshold high (on 8 bits):
1489 * LL_ADC_SetAnalogWDThresholds
1490 * (< ADCx param >,
1491 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
1492 * );
1493 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1494 * @arg @ref LL_ADC_RESOLUTION_12B
1495 * @arg @ref LL_ADC_RESOLUTION_10B
1496 * @arg @ref LL_ADC_RESOLUTION_8B
1497 * @arg @ref LL_ADC_RESOLUTION_6B
1498 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
1499 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1500 */
1501 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
1502 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U )))
1503
1504 /**
1505 * @brief Helper macro to get the value of ADC analog watchdog threshold high
1506 * or low in function of ADC resolution, when ADC resolution is
1507 * different of 12 bits.
1508 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1509 * Example, with a ADC resolution of 8 bits, to get the value of
1510 * analog watchdog threshold high (on 8 bits):
1511 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
1512 * (LL_ADC_RESOLUTION_8B,
1513 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
1514 * );
1515 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1516 * @arg @ref LL_ADC_RESOLUTION_12B
1517 * @arg @ref LL_ADC_RESOLUTION_10B
1518 * @arg @ref LL_ADC_RESOLUTION_8B
1519 * @arg @ref LL_ADC_RESOLUTION_6B
1520 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
1521 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1522 */
1523 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
1524 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U )))
1525
1526 #if defined(ADC_MULTIMODE_SUPPORT)
1527 /**
1528 * @brief Helper macro to get the ADC multimode conversion data of ADC master
1529 * or ADC slave from raw value with both ADC conversion data concatenated.
1530 * @note This macro is intended to be used when multimode transfer by DMA
1531 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
1532 * In this case the transferred data need to processed with this macro
1533 * to separate the conversion data of ADC master and ADC slave.
1534 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
1535 * @arg @ref LL_ADC_MULTI_MASTER
1536 * @arg @ref LL_ADC_MULTI_SLAVE
1537 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
1538 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1539 */
1540 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
1541 (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
1542 #endif
1543
1544 /**
1545 * @brief Helper macro to select the ADC common instance
1546 * to which is belonging the selected ADC instance.
1547 * @note ADC common register instance can be used for:
1548 * - Set parameters common to several ADC instances
1549 * - Multimode (for devices with several ADC instances)
1550 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1551 * @param __ADCx__ ADC instance
1552 * @retval ADC common register instance
1553 */
1554 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
1555 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1556 (ADC123_COMMON)
1557 #elif defined(ADC1) && defined(ADC2)
1558 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1559 (ADC12_COMMON)
1560 #else
1561 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1562 (ADC1_COMMON)
1563 #endif
1564
1565 /**
1566 * @brief Helper macro to check if all ADC instances sharing the same
1567 * ADC common instance are disabled.
1568 * @note This check is required by functions with setting conditioned to
1569 * ADC state:
1570 * All ADC instances of the ADC common group must be disabled.
1571 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1572 * @note On devices with only 1 ADC common instance, parameter of this macro
1573 * is useless and can be ignored (parameter kept for compatibility
1574 * with devices featuring several ADC common instances).
1575 * @param __ADCXY_COMMON__ ADC common instance
1576 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1577 * @retval Value "0" if all ADC instances sharing the same ADC common instance
1578 * are disabled.
1579 * Value "1" if at least one ADC instance sharing the same ADC common instance
1580 * is enabled.
1581 */
1582 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
1583 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1584 (LL_ADC_IsEnabled(ADC1) | \
1585 LL_ADC_IsEnabled(ADC2) | \
1586 LL_ADC_IsEnabled(ADC3) )
1587 #elif defined(ADC1) && defined(ADC2)
1588 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1589 (LL_ADC_IsEnabled(ADC1) | \
1590 LL_ADC_IsEnabled(ADC2) )
1591 #else
1592 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1593 (LL_ADC_IsEnabled(ADC1))
1594 #endif
1595
1596 /**
1597 * @brief Helper macro to define the ADC conversion data full-scale digital
1598 * value corresponding to the selected ADC resolution.
1599 * @note ADC conversion data full-scale corresponds to voltage range
1600 * determined by analog voltage references Vref+ and Vref-
1601 * (refer to reference manual).
1602 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1603 * @arg @ref LL_ADC_RESOLUTION_12B
1604 * @arg @ref LL_ADC_RESOLUTION_10B
1605 * @arg @ref LL_ADC_RESOLUTION_8B
1606 * @arg @ref LL_ADC_RESOLUTION_6B
1607 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1608 */
1609 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1610 (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)))
1611
1612 /**
1613 * @brief Helper macro to convert the ADC conversion data from
1614 * a resolution to another resolution.
1615 * @param __DATA__ ADC conversion data to be converted
1616 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
1617 * This parameter can be one of the following values:
1618 * @arg @ref LL_ADC_RESOLUTION_12B
1619 * @arg @ref LL_ADC_RESOLUTION_10B
1620 * @arg @ref LL_ADC_RESOLUTION_8B
1621 * @arg @ref LL_ADC_RESOLUTION_6B
1622 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
1623 * This parameter can be one of the following values:
1624 * @arg @ref LL_ADC_RESOLUTION_12B
1625 * @arg @ref LL_ADC_RESOLUTION_10B
1626 * @arg @ref LL_ADC_RESOLUTION_8B
1627 * @arg @ref LL_ADC_RESOLUTION_6B
1628 * @retval ADC conversion data to the requested resolution
1629 */
1630 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \
1631 (((__DATA__) \
1632 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U))) \
1633 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)) \
1634 )
1635
1636 /**
1637 * @brief Helper macro to calculate the voltage (unit: mVolt)
1638 * corresponding to a ADC conversion data (unit: digital value).
1639 * @note Analog reference voltage (Vref+) must be either known from
1640 * user board environment or can be calculated using ADC measurement
1641 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1642 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
1643 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
1644 * (unit: digital value).
1645 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1646 * @arg @ref LL_ADC_RESOLUTION_12B
1647 * @arg @ref LL_ADC_RESOLUTION_10B
1648 * @arg @ref LL_ADC_RESOLUTION_8B
1649 * @arg @ref LL_ADC_RESOLUTION_6B
1650 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1651 */
1652 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
1653 __ADC_DATA__,\
1654 __ADC_RESOLUTION__) \
1655 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
1656 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1657 )
1658
1659
1660 /**
1661 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1662 * from ADC conversion data of internal temperature sensor.
1663 * @note Computation is using temperature sensor typical values
1664 * (refer to device datasheet).
1665 * @note Calculation formula:
1666 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
1667 * / Avg_Slope + CALx_TEMP
1668 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1669 * (unit: digital value)
1670 * Avg_Slope = temperature sensor slope
1671 * (unit: uV/Degree Celsius)
1672 * TS_TYP_CALx_VOLT = temperature sensor digital value at
1673 * temperature CALx_TEMP (unit: mV)
1674 * Caution: Calculation relevancy under reserve the temperature sensor
1675 * of the current device has characteristics in line with
1676 * datasheet typical values.
1677 * If temperature sensor calibration values are available on
1678 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
1679 * temperature calculation will be more accurate using
1680 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
1681 * @note As calculation input, the analog reference voltage (Vref+) must be
1682 * defined as it impacts the ADC LSB equivalent voltage.
1683 * @note Analog reference voltage (Vref+) must be either known from
1684 * user board environment or can be calculated using ADC measurement
1685 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1686 * @note ADC measurement data must correspond to a resolution of 12bits
1687 * (full scale digital value 4095). If not the case, the data must be
1688 * preliminarily rescaled to an equivalent resolution of 12 bits.
1689 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
1690 * On STM32F4, refer to device datasheet parameter "Avg_Slope".
1691 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
1692 * On STM32F4, refer to device datasheet parameter "V25".
1693 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
1694 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
1695 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
1696 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
1697 * This parameter can be one of the following values:
1698 * @arg @ref LL_ADC_RESOLUTION_12B
1699 * @arg @ref LL_ADC_RESOLUTION_10B
1700 * @arg @ref LL_ADC_RESOLUTION_8B
1701 * @arg @ref LL_ADC_RESOLUTION_6B
1702 * @retval Temperature (unit: degree Celsius)
1703 */
1704 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
1705 __TEMPSENSOR_TYP_CALX_V__,\
1706 __TEMPSENSOR_CALX_TEMP__,\
1707 __VREFANALOG_VOLTAGE__,\
1708 __TEMPSENSOR_ADC_DATA__,\
1709 __ADC_RESOLUTION__) \
1710 ((( ( \
1711 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
1712 * 1000) \
1713 - \
1714 (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
1715 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
1716 * 1000) \
1717 ) \
1718 ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
1719 ) + (__TEMPSENSOR_CALX_TEMP__) \
1720 )
1721
1722 /**
1723 * @}
1724 */
1725
1726 /**
1727 * @}
1728 */
1729
1730
1731 /* Exported functions --------------------------------------------------------*/
1732 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
1733 * @{
1734 */
1735
1736 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
1737 * @{
1738 */
1739 /* Note: LL ADC functions to set DMA transfer are located into sections of */
1740 /* configuration of ADC instance, groups and multimode (if available): */
1741 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
1742
1743 /**
1744 * @brief Function to help to configure DMA transfer from ADC: retrieve the
1745 * ADC register address from ADC instance and a list of ADC registers
1746 * intended to be used (most commonly) with DMA transfer.
1747 * @note These ADC registers are data registers:
1748 * when ADC conversion data is available in ADC data registers,
1749 * ADC generates a DMA transfer request.
1750 * @note This macro is intended to be used with LL DMA driver, refer to
1751 * function "LL_DMA_ConfigAddresses()".
1752 * Example:
1753 * LL_DMA_ConfigAddresses(DMA1,
1754 * LL_DMA_CHANNEL_1,
1755 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
1756 * (uint32_t)&< array or variable >,
1757 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
1758 * @note For devices with several ADC: in multimode, some devices
1759 * use a different data register outside of ADC instance scope
1760 * (common data register). This macro manages this register difference,
1761 * only ADC instance has to be set as parameter.
1762 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
1763 * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
1764 * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
1765 * @param ADCx ADC instance
1766 * @param Register This parameter can be one of the following values:
1767 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
1768 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
1769 *
1770 * (1) Available on devices with several ADC instances.
1771 * @retval ADC register address
1772 */
1773 #if defined(ADC_MULTIMODE_SUPPORT)
1774 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
1775 {
1776 register uint32_t data_reg_addr = 0U;
1777
1778 if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
1779 {
1780 /* Retrieve address of register DR */
1781 data_reg_addr = (uint32_t)&(ADCx->DR);
1782 }
1783 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
1784 {
1785 /* Retrieve address of register CDR */
1786 data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
1787 }
1788
1789 return data_reg_addr;
1790 }
1791 #else
1792 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
1793 {
1794 /* Retrieve address of register DR */
1795 return (uint32_t)&(ADCx->DR);
1796 }
1797 #endif
1798
1799 /**
1800 * @}
1801 */
1802
1803 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
1804 * @{
1805 */
1806
1807 /**
1808 * @brief Set parameter common to several ADC: Clock source and prescaler.
1809 * @rmtoll CCR ADCPRE LL_ADC_SetCommonClock
1810 * @param ADCxy_COMMON ADC common instance
1811 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1812 * @param CommonClock This parameter can be one of the following values:
1813 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
1814 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
1815 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6
1816 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8
1817 * @retval None
1818 */
1819 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
1820 {
1821 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE, CommonClock);
1822 }
1823
1824 /**
1825 * @brief Get parameter common to several ADC: Clock source and prescaler.
1826 * @rmtoll CCR ADCPRE LL_ADC_GetCommonClock
1827 * @param ADCxy_COMMON ADC common instance
1828 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1829 * @retval Returned value can be one of the following values:
1830 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
1831 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
1832 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6
1833 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8
1834 */
1835 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
1836 {
1837 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE));
1838 }
1839
1840 /**
1841 * @brief Set parameter common to several ADC: measurement path to internal
1842 * channels (VrefInt, temperature sensor, ...).
1843 * @note One or several values can be selected.
1844 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1845 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1846 * @note Stabilization time of measurement path to internal channel:
1847 * After enabling internal paths, before starting ADC conversion,
1848 * a delay is required for internal voltage reference and
1849 * temperature sensor stabilization time.
1850 * Refer to device datasheet.
1851 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
1852 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
1853 * @note ADC internal channel sampling time constraint:
1854 * For ADC conversion of internal channels,
1855 * a sampling time minimum value is required.
1856 * Refer to device datasheet.
1857 * @rmtoll CCR TSVREFE LL_ADC_SetCommonPathInternalCh\n
1858 * CCR VBATE LL_ADC_SetCommonPathInternalCh
1859 * @param ADCxy_COMMON ADC common instance
1860 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1861 * @param PathInternal This parameter can be a combination of the following values:
1862 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1863 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1864 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1865 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
1866 * @retval None
1867 */
1868 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
1869 {
1870 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE, PathInternal);
1871 }
1872
1873 /**
1874 * @brief Get parameter common to several ADC: measurement path to internal
1875 * channels (VrefInt, temperature sensor, ...).
1876 * @note One or several values can be selected.
1877 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1878 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1879 * @rmtoll CCR TSVREFE LL_ADC_GetCommonPathInternalCh\n
1880 * CCR VBATE LL_ADC_GetCommonPathInternalCh
1881 * @param ADCxy_COMMON ADC common instance
1882 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1883 * @retval Returned value can be a combination of the following values:
1884 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1885 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1886 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1887 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
1888 */
1889 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
1890 {
1891 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE));
1892 }
1893
1894 /**
1895 * @}
1896 */
1897
1898 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
1899 * @{
1900 */
1901
1902 /**
1903 * @brief Set ADC resolution.
1904 * Refer to reference manual for alignments formats
1905 * dependencies to ADC resolutions.
1906 * @rmtoll CR1 RES LL_ADC_SetResolution
1907 * @param ADCx ADC instance
1908 * @param Resolution This parameter can be one of the following values:
1909 * @arg @ref LL_ADC_RESOLUTION_12B
1910 * @arg @ref LL_ADC_RESOLUTION_10B
1911 * @arg @ref LL_ADC_RESOLUTION_8B
1912 * @arg @ref LL_ADC_RESOLUTION_6B
1913 * @retval None
1914 */
1915 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
1916 {
1917 MODIFY_REG(ADCx->CR1, ADC_CR1_RES, Resolution);
1918 }
1919
1920 /**
1921 * @brief Get ADC resolution.
1922 * Refer to reference manual for alignments formats
1923 * dependencies to ADC resolutions.
1924 * @rmtoll CR1 RES LL_ADC_GetResolution
1925 * @param ADCx ADC instance
1926 * @retval Returned value can be one of the following values:
1927 * @arg @ref LL_ADC_RESOLUTION_12B
1928 * @arg @ref LL_ADC_RESOLUTION_10B
1929 * @arg @ref LL_ADC_RESOLUTION_8B
1930 * @arg @ref LL_ADC_RESOLUTION_6B
1931 */
1932 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
1933 {
1934 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_RES));
1935 }
1936
1937 /**
1938 * @brief Set ADC conversion data alignment.
1939 * @note Refer to reference manual for alignments formats
1940 * dependencies to ADC resolutions.
1941 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
1942 * @param ADCx ADC instance
1943 * @param DataAlignment This parameter can be one of the following values:
1944 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
1945 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
1946 * @retval None
1947 */
1948 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
1949 {
1950 MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment);
1951 }
1952
1953 /**
1954 * @brief Get ADC conversion data alignment.
1955 * @note Refer to reference manual for alignments formats
1956 * dependencies to ADC resolutions.
1957 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
1958 * @param ADCx ADC instance
1959 * @retval Returned value can be one of the following values:
1960 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
1961 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
1962 */
1963 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
1964 {
1965 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN));
1966 }
1967
1968 /**
1969 * @brief Set ADC sequencers scan mode, for all ADC groups
1970 * (group regular, group injected).
1971 * @note According to sequencers scan mode :
1972 * - If disabled: ADC conversion is performed in unitary conversion
1973 * mode (one channel converted, that defined in rank 1).
1974 * Configuration of sequencers of all ADC groups
1975 * (sequencer scan length, ...) is discarded: equivalent to
1976 * scan length of 1 rank.
1977 * - If enabled: ADC conversions are performed in sequence conversions
1978 * mode, according to configuration of sequencers of
1979 * each ADC group (sequencer scan length, ...).
1980 * Refer to function @ref LL_ADC_REG_SetSequencerLength()
1981 * and to function @ref LL_ADC_INJ_SetSequencerLength().
1982 * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode
1983 * @param ADCx ADC instance
1984 * @param ScanMode This parameter can be one of the following values:
1985 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
1986 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
1987 * @retval None
1988 */
1989 __STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode)
1990 {
1991 MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode);
1992 }
1993
1994 /**
1995 * @brief Get ADC sequencers scan mode, for all ADC groups
1996 * (group regular, group injected).
1997 * @note According to sequencers scan mode :
1998 * - If disabled: ADC conversion is performed in unitary conversion
1999 * mode (one channel converted, that defined in rank 1).
2000 * Configuration of sequencers of all ADC groups
2001 * (sequencer scan length, ...) is discarded: equivalent to
2002 * scan length of 1 rank.
2003 * - If enabled: ADC conversions are performed in sequence conversions
2004 * mode, according to configuration of sequencers of
2005 * each ADC group (sequencer scan length, ...).
2006 * Refer to function @ref LL_ADC_REG_SetSequencerLength()
2007 * and to function @ref LL_ADC_INJ_SetSequencerLength().
2008 * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode
2009 * @param ADCx ADC instance
2010 * @retval Returned value can be one of the following values:
2011 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
2012 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
2013 */
2014 __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)
2015 {
2016 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN));
2017 }
2018
2019 /**
2020 * @}
2021 */
2022
2023 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
2024 * @{
2025 */
2026
2027 /**
2028 * @brief Set ADC group regular conversion trigger source:
2029 * internal (SW start) or from external IP (timer event,
2030 * external interrupt line).
2031 * @note On this STM32 serie, setting of external trigger edge is performed
2032 * using function @ref LL_ADC_REG_StartConversionExtTrig().
2033 * @note Availability of parameters of trigger sources from timer
2034 * depends on timers availability on the selected device.
2035 * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource\n
2036 * CR2 EXTEN LL_ADC_REG_SetTriggerSource
2037 * @param ADCx ADC instance
2038 * @param TriggerSource This parameter can be one of the following values:
2039 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2040 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
2041 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
2042 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
2043 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
2044 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3
2045 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4
2046 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
2047 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1
2048 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
2049 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
2050 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1
2051 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH2
2052 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3
2053 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1
2054 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
2055 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
2056 * @retval None
2057 */
2058 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
2059 {
2060 /* Note: On this STM32 serie, ADC group regular external trigger edge */
2061 /* is used to perform a ADC conversion start. */
2062 /* This function does not set external trigger edge. */
2063 /* This feature is set using function */
2064 /* @ref LL_ADC_REG_StartConversionExtTrig(). */
2065 MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL));
2066 }
2067
2068 /**
2069 * @brief Get ADC group regular conversion trigger source:
2070 * internal (SW start) or from external IP (timer event,
2071 * external interrupt line).
2072 * @note To determine whether group regular trigger source is
2073 * internal (SW start) or external, without detail
2074 * of which peripheral is selected as external trigger,
2075 * (equivalent to
2076 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
2077 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
2078 * @note Availability of parameters of trigger sources from timer
2079 * depends on timers availability on the selected device.
2080 * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource\n
2081 * CR2 EXTEN LL_ADC_REG_GetTriggerSource
2082 * @param ADCx ADC instance
2083 * @retval Returned value can be one of the following values:
2084 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2085 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
2086 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
2087 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
2088 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
2089 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3
2090 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4
2091 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
2092 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1
2093 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
2094 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
2095 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1
2096 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH2
2097 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3
2098 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1
2099 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
2100 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
2101 */
2102 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
2103 {
2104 register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL | ADC_CR2_EXTEN);
2105
2106 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
2107 /* corresponding to ADC_CR2_EXTEN {0; 1; 2; 3}. */
2108 register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
2109
2110 /* Set bitfield corresponding to ADC_CR2_EXTEN and ADC_CR2_EXTSEL */
2111 /* to match with triggers literals definition. */
2112 return ((TriggerSource
2113 & (ADC_REG_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_EXTSEL)
2114 | ((ADC_REG_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_EXTEN)
2115 );
2116 }
2117
2118 /**
2119 * @brief Get ADC group regular conversion trigger source internal (SW start)
2120 or external.
2121 * @note In case of group regular trigger source set to external trigger,
2122 * to determine which peripheral is selected as external trigger,
2123 * use function @ref LL_ADC_REG_GetTriggerSource().
2124 * @rmtoll CR2 EXTEN LL_ADC_REG_IsTriggerSourceSWStart
2125 * @param ADCx ADC instance
2126 * @retval Value "0" if trigger source external trigger
2127 * Value "1" if trigger source SW start.
2128 */
2129 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
2130 {
2131 return (READ_BIT(ADCx->CR2, ADC_CR2_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN));
2132 }
2133
2134 /**
2135 * @brief Get ADC group regular conversion trigger polarity.
2136 * @note Applicable only for trigger source set to external trigger.
2137 * @note On this STM32 serie, setting of external trigger edge is performed
2138 * using function @ref LL_ADC_REG_StartConversionExtTrig().
2139 * @rmtoll CR2 EXTEN LL_ADC_REG_GetTriggerEdge
2140 * @param ADCx ADC instance
2141 * @retval Returned value can be one of the following values:
2142 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
2143 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
2144 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
2145 */
2146 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
2147 {
2148 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTEN));
2149 }
2150
2151
2152 /**
2153 * @brief Set ADC group regular sequencer length and scan direction.
2154 * @note Description of ADC group regular sequencer features:
2155 * - For devices with sequencer fully configurable
2156 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2157 * sequencer length and each rank affectation to a channel
2158 * are configurable.
2159 * This function performs configuration of:
2160 * - Sequence length: Number of ranks in the scan sequence.
2161 * - Sequence direction: Unless specified in parameters, sequencer
2162 * scan direction is forward (from rank 1 to rank n).
2163 * Sequencer ranks are selected using
2164 * function "LL_ADC_REG_SetSequencerRanks()".
2165 * - For devices with sequencer not fully configurable
2166 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2167 * sequencer length and each rank affectation to a channel
2168 * are defined by channel number.
2169 * This function performs configuration of:
2170 * - Sequence length: Number of ranks in the scan sequence is
2171 * defined by number of channels set in the sequence,
2172 * rank of each channel is fixed by channel HW number.
2173 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2174 * - Sequence direction: Unless specified in parameters, sequencer
2175 * scan direction is forward (from lowest channel number to
2176 * highest channel number).
2177 * Sequencer ranks are selected using
2178 * function "LL_ADC_REG_SetSequencerChannels()".
2179 * @note On this STM32 serie, group regular sequencer configuration
2180 * is conditioned to ADC instance sequencer mode.
2181 * If ADC instance sequencer mode is disabled, sequencers of
2182 * all groups (group regular, group injected) can be configured
2183 * but their execution is disabled (limited to rank 1).
2184 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2185 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2186 * ADC conversion on only 1 channel.
2187 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
2188 * @param ADCx ADC instance
2189 * @param SequencerNbRanks This parameter can be one of the following values:
2190 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2191 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2192 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2193 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2194 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2195 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2196 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2197 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2198 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
2199 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
2200 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
2201 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
2202 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
2203 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
2204 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
2205 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
2206 * @retval None
2207 */
2208 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
2209 {
2210 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
2211 }
2212
2213 /**
2214 * @brief Get ADC group regular sequencer length and scan direction.
2215 * @note Description of ADC group regular sequencer features:
2216 * - For devices with sequencer fully configurable
2217 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2218 * sequencer length and each rank affectation to a channel
2219 * are configurable.
2220 * This function retrieves:
2221 * - Sequence length: Number of ranks in the scan sequence.
2222 * - Sequence direction: Unless specified in parameters, sequencer
2223 * scan direction is forward (from rank 1 to rank n).
2224 * Sequencer ranks are selected using
2225 * function "LL_ADC_REG_SetSequencerRanks()".
2226 * - For devices with sequencer not fully configurable
2227 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2228 * sequencer length and each rank affectation to a channel
2229 * are defined by channel number.
2230 * This function retrieves:
2231 * - Sequence length: Number of ranks in the scan sequence is
2232 * defined by number of channels set in the sequence,
2233 * rank of each channel is fixed by channel HW number.
2234 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2235 * - Sequence direction: Unless specified in parameters, sequencer
2236 * scan direction is forward (from lowest channel number to
2237 * highest channel number).
2238 * Sequencer ranks are selected using
2239 * function "LL_ADC_REG_SetSequencerChannels()".
2240 * @note On this STM32 serie, group regular sequencer configuration
2241 * is conditioned to ADC instance sequencer mode.
2242 * If ADC instance sequencer mode is disabled, sequencers of
2243 * all groups (group regular, group injected) can be configured
2244 * but their execution is disabled (limited to rank 1).
2245 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2246 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2247 * ADC conversion on only 1 channel.
2248 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
2249 * @param ADCx ADC instance
2250 * @retval Returned value can be one of the following values:
2251 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2252 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2253 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2254 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2255 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2256 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2257 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2258 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2259 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
2260 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
2261 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
2262 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
2263 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
2264 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
2265 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
2266 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
2267 */
2268 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
2269 {
2270 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
2271 }
2272
2273 /**
2274 * @brief Set ADC group regular sequencer discontinuous mode:
2275 * sequence subdivided and scan conversions interrupted every selected
2276 * number of ranks.
2277 * @note It is not possible to enable both ADC group regular
2278 * continuous mode and sequencer discontinuous mode.
2279 * @note It is not possible to enable both ADC auto-injected mode
2280 * and ADC group regular sequencer discontinuous mode.
2281 * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
2282 * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont
2283 * @param ADCx ADC instance
2284 * @param SeqDiscont This parameter can be one of the following values:
2285 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2286 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2287 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
2288 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
2289 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
2290 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
2291 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
2292 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
2293 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
2294 * @retval None
2295 */
2296 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
2297 {
2298 MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont);
2299 }
2300
2301 /**
2302 * @brief Get ADC group regular sequencer discontinuous mode:
2303 * sequence subdivided and scan conversions interrupted every selected
2304 * number of ranks.
2305 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
2306 * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont
2307 * @param ADCx ADC instance
2308 * @retval Returned value can be one of the following values:
2309 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2310 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2311 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
2312 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
2313 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
2314 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
2315 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
2316 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
2317 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
2318 */
2319 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
2320 {
2321 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM));
2322 }
2323
2324 /**
2325 * @brief Set ADC group regular sequence: channel on the selected
2326 * scan sequence rank.
2327 * @note This function performs configuration of:
2328 * - Channels ordering into each rank of scan sequence:
2329 * whatever channel can be placed into whatever rank.
2330 * @note On this STM32 serie, ADC group regular sequencer is
2331 * fully configurable: sequencer length and each rank
2332 * affectation to a channel are configurable.
2333 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
2334 * @note Depending on devices and packages, some channels may not be available.
2335 * Refer to device datasheet for channels availability.
2336 * @note On this STM32 serie, to measure internal channels (VrefInt,
2337 * TempSensor, ...), measurement paths to internal channels must be
2338 * enabled separately.
2339 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2340 * @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n
2341 * SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n
2342 * SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n
2343 * SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n
2344 * SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n
2345 * SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n
2346 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
2347 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
2348 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
2349 * SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n
2350 * SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n
2351 * SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n
2352 * SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n
2353 * SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n
2354 * SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n
2355 * SQR1 SQ16 LL_ADC_REG_SetSequencerRanks
2356 * @param ADCx ADC instance
2357 * @param Rank This parameter can be one of the following values:
2358 * @arg @ref LL_ADC_REG_RANK_1
2359 * @arg @ref LL_ADC_REG_RANK_2
2360 * @arg @ref LL_ADC_REG_RANK_3
2361 * @arg @ref LL_ADC_REG_RANK_4
2362 * @arg @ref LL_ADC_REG_RANK_5
2363 * @arg @ref LL_ADC_REG_RANK_6
2364 * @arg @ref LL_ADC_REG_RANK_7
2365 * @arg @ref LL_ADC_REG_RANK_8
2366 * @arg @ref LL_ADC_REG_RANK_9
2367 * @arg @ref LL_ADC_REG_RANK_10
2368 * @arg @ref LL_ADC_REG_RANK_11
2369 * @arg @ref LL_ADC_REG_RANK_12
2370 * @arg @ref LL_ADC_REG_RANK_13
2371 * @arg @ref LL_ADC_REG_RANK_14
2372 * @arg @ref LL_ADC_REG_RANK_15
2373 * @arg @ref LL_ADC_REG_RANK_16
2374 * @param Channel This parameter can be one of the following values:
2375 * @arg @ref LL_ADC_CHANNEL_0
2376 * @arg @ref LL_ADC_CHANNEL_1
2377 * @arg @ref LL_ADC_CHANNEL_2
2378 * @arg @ref LL_ADC_CHANNEL_3
2379 * @arg @ref LL_ADC_CHANNEL_4
2380 * @arg @ref LL_ADC_CHANNEL_5
2381 * @arg @ref LL_ADC_CHANNEL_6
2382 * @arg @ref LL_ADC_CHANNEL_7
2383 * @arg @ref LL_ADC_CHANNEL_8
2384 * @arg @ref LL_ADC_CHANNEL_9
2385 * @arg @ref LL_ADC_CHANNEL_10
2386 * @arg @ref LL_ADC_CHANNEL_11
2387 * @arg @ref LL_ADC_CHANNEL_12
2388 * @arg @ref LL_ADC_CHANNEL_13
2389 * @arg @ref LL_ADC_CHANNEL_14
2390 * @arg @ref LL_ADC_CHANNEL_15
2391 * @arg @ref LL_ADC_CHANNEL_16
2392 * @arg @ref LL_ADC_CHANNEL_17
2393 * @arg @ref LL_ADC_CHANNEL_18
2394 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2395 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
2396 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2397 *
2398 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
2399 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
2400 * @retval None
2401 */
2402 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
2403 {
2404 /* Set bits with content of parameter "Channel" with bits position */
2405 /* in register and register position depending on parameter "Rank". */
2406 /* Parameters "Rank" and "Channel" are used with masks because containing */
2407 /* other bits reserved for other purpose. */
2408 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
2409
2410 MODIFY_REG(*preg,
2411 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
2412 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
2413 }
2414
2415 /**
2416 * @brief Get ADC group regular sequence: channel on the selected
2417 * scan sequence rank.
2418 * @note On this STM32 serie, ADC group regular sequencer is
2419 * fully configurable: sequencer length and each rank
2420 * affectation to a channel are configurable.
2421 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
2422 * @note Depending on devices and packages, some channels may not be available.
2423 * Refer to device datasheet for channels availability.
2424 * @note Usage of the returned channel number:
2425 * - To reinject this channel into another function LL_ADC_xxx:
2426 * the returned channel number is only partly formatted on definition
2427 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
2428 * with parts of literals LL_ADC_CHANNEL_x or using
2429 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2430 * Then the selected literal LL_ADC_CHANNEL_x can be used
2431 * as parameter for another function.
2432 * - To get the channel number in decimal format:
2433 * process the returned value with the helper macro
2434 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2435 * @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n
2436 * SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n
2437 * SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n
2438 * SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n
2439 * SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n
2440 * SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n
2441 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
2442 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
2443 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
2444 * SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n
2445 * SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n
2446 * SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n
2447 * SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n
2448 * SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n
2449 * SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n
2450 * SQR1 SQ16 LL_ADC_REG_GetSequencerRanks
2451 * @param ADCx ADC instance
2452 * @param Rank This parameter can be one of the following values:
2453 * @arg @ref LL_ADC_REG_RANK_1
2454 * @arg @ref LL_ADC_REG_RANK_2
2455 * @arg @ref LL_ADC_REG_RANK_3
2456 * @arg @ref LL_ADC_REG_RANK_4
2457 * @arg @ref LL_ADC_REG_RANK_5
2458 * @arg @ref LL_ADC_REG_RANK_6
2459 * @arg @ref LL_ADC_REG_RANK_7
2460 * @arg @ref LL_ADC_REG_RANK_8
2461 * @arg @ref LL_ADC_REG_RANK_9
2462 * @arg @ref LL_ADC_REG_RANK_10
2463 * @arg @ref LL_ADC_REG_RANK_11
2464 * @arg @ref LL_ADC_REG_RANK_12
2465 * @arg @ref LL_ADC_REG_RANK_13
2466 * @arg @ref LL_ADC_REG_RANK_14
2467 * @arg @ref LL_ADC_REG_RANK_15
2468 * @arg @ref LL_ADC_REG_RANK_16
2469 * @retval Returned value can be one of the following values:
2470 * @arg @ref LL_ADC_CHANNEL_0
2471 * @arg @ref LL_ADC_CHANNEL_1
2472 * @arg @ref LL_ADC_CHANNEL_2
2473 * @arg @ref LL_ADC_CHANNEL_3
2474 * @arg @ref LL_ADC_CHANNEL_4
2475 * @arg @ref LL_ADC_CHANNEL_5
2476 * @arg @ref LL_ADC_CHANNEL_6
2477 * @arg @ref LL_ADC_CHANNEL_7
2478 * @arg @ref LL_ADC_CHANNEL_8
2479 * @arg @ref LL_ADC_CHANNEL_9
2480 * @arg @ref LL_ADC_CHANNEL_10
2481 * @arg @ref LL_ADC_CHANNEL_11
2482 * @arg @ref LL_ADC_CHANNEL_12
2483 * @arg @ref LL_ADC_CHANNEL_13
2484 * @arg @ref LL_ADC_CHANNEL_14
2485 * @arg @ref LL_ADC_CHANNEL_15
2486 * @arg @ref LL_ADC_CHANNEL_16
2487 * @arg @ref LL_ADC_CHANNEL_17
2488 * @arg @ref LL_ADC_CHANNEL_18
2489 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2490 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
2491 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2492 *
2493 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
2494 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
2495 * (1) For ADC channel read back from ADC register,
2496 * comparison with internal channel parameter to be done
2497 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2498 */
2499 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
2500 {
2501 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
2502
2503 return (uint32_t) (READ_BIT(*preg,
2504 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
2505 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
2506 );
2507 }
2508
2509 /**
2510 * @brief Set ADC continuous conversion mode on ADC group regular.
2511 * @note Description of ADC continuous conversion mode:
2512 * - single mode: one conversion per trigger
2513 * - continuous mode: after the first trigger, following
2514 * conversions launched successively automatically.
2515 * @note It is not possible to enable both ADC group regular
2516 * continuous mode and sequencer discontinuous mode.
2517 * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode
2518 * @param ADCx ADC instance
2519 * @param Continuous This parameter can be one of the following values:
2520 * @arg @ref LL_ADC_REG_CONV_SINGLE
2521 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
2522 * @retval None
2523 */
2524 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
2525 {
2526 MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous);
2527 }
2528
2529 /**
2530 * @brief Get ADC continuous conversion mode on ADC group regular.
2531 * @note Description of ADC continuous conversion mode:
2532 * - single mode: one conversion per trigger
2533 * - continuous mode: after the first trigger, following
2534 * conversions launched successively automatically.
2535 * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode
2536 * @param ADCx ADC instance
2537 * @retval Returned value can be one of the following values:
2538 * @arg @ref LL_ADC_REG_CONV_SINGLE
2539 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
2540 */
2541 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
2542 {
2543 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT));
2544 }
2545
2546 /**
2547 * @brief Set ADC group regular conversion data transfer: no transfer or
2548 * transfer by DMA, and DMA requests mode.
2549 * @note If transfer by DMA selected, specifies the DMA requests
2550 * mode:
2551 * - Limited mode (One shot mode): DMA transfer requests are stopped
2552 * when number of DMA data transfers (number of
2553 * ADC conversions) is reached.
2554 * This ADC mode is intended to be used with DMA mode non-circular.
2555 * - Unlimited mode: DMA transfer requests are unlimited,
2556 * whatever number of DMA data transfers (number of
2557 * ADC conversions).
2558 * This ADC mode is intended to be used with DMA mode circular.
2559 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
2560 * mode non-circular:
2561 * when DMA transfers size will be reached, DMA will stop transfers of
2562 * ADC conversions data ADC will raise an overrun error
2563 * (overrun flag and interruption if enabled).
2564 * @note For devices with several ADC instances: ADC multimode DMA
2565 * settings are available using function @ref LL_ADC_SetMultiDMATransfer().
2566 * @note To configure DMA source address (peripheral address),
2567 * use function @ref LL_ADC_DMA_GetRegAddr().
2568 * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer\n
2569 * CR2 DDS LL_ADC_REG_SetDMATransfer
2570 * @param ADCx ADC instance
2571 * @param DMATransfer This parameter can be one of the following values:
2572 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
2573 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
2574 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
2575 * @retval None
2576 */
2577 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
2578 {
2579 MODIFY_REG(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS, DMATransfer);
2580 }
2581
2582 /**
2583 * @brief Get ADC group regular conversion data transfer: no transfer or
2584 * transfer by DMA, and DMA requests mode.
2585 * @note If transfer by DMA selected, specifies the DMA requests
2586 * mode:
2587 * - Limited mode (One shot mode): DMA transfer requests are stopped
2588 * when number of DMA data transfers (number of
2589 * ADC conversions) is reached.
2590 * This ADC mode is intended to be used with DMA mode non-circular.
2591 * - Unlimited mode: DMA transfer requests are unlimited,
2592 * whatever number of DMA data transfers (number of
2593 * ADC conversions).
2594 * This ADC mode is intended to be used with DMA mode circular.
2595 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
2596 * mode non-circular:
2597 * when DMA transfers size will be reached, DMA will stop transfers of
2598 * ADC conversions data ADC will raise an overrun error
2599 * (overrun flag and interruption if enabled).
2600 * @note For devices with several ADC instances: ADC multimode DMA
2601 * settings are available using function @ref LL_ADC_GetMultiDMATransfer().
2602 * @note To configure DMA source address (peripheral address),
2603 * use function @ref LL_ADC_DMA_GetRegAddr().
2604 * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer\n
2605 * CR2 DDS LL_ADC_REG_GetDMATransfer
2606 * @param ADCx ADC instance
2607 * @retval Returned value can be one of the following values:
2608 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
2609 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
2610 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
2611 */
2612 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
2613 {
2614 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS));
2615 }
2616
2617 /**
2618 * @brief Specify which ADC flag between EOC (end of unitary conversion)
2619 * or EOS (end of sequence conversions) is used to indicate
2620 * the end of conversion.
2621 * @note This feature is aimed to be set when using ADC with
2622 * programming model by polling or interruption
2623 * (programming model by DMA usually uses DMA interruptions
2624 * to indicate end of conversion and data transfer).
2625 * @note For ADC group injected, end of conversion (flag&IT) is raised
2626 * only at the end of the sequence.
2627 * @rmtoll CR2 EOCS LL_ADC_REG_SetFlagEndOfConversion
2628 * @param ADCx ADC instance
2629 * @param EocSelection This parameter can be one of the following values:
2630 * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
2631 * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV
2632 * @retval None
2633 */
2634 __STATIC_INLINE void LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef *ADCx, uint32_t EocSelection)
2635 {
2636 MODIFY_REG(ADCx->CR2, ADC_CR2_EOCS, EocSelection);
2637 }
2638
2639 /**
2640 * @brief Get which ADC flag between EOC (end of unitary conversion)
2641 * or EOS (end of sequence conversions) is used to indicate
2642 * the end of conversion.
2643 * @rmtoll CR2 EOCS LL_ADC_REG_GetFlagEndOfConversion
2644 * @param ADCx ADC instance
2645 * @retval Returned value can be one of the following values:
2646 * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
2647 * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV
2648 */
2649 __STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx)
2650 {
2651 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EOCS));
2652 }
2653
2654 /**
2655 * @}
2656 */
2657
2658 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
2659 * @{
2660 */
2661
2662 /**
2663 * @brief Set ADC group injected conversion trigger source:
2664 * internal (SW start) or from external IP (timer event,
2665 * external interrupt line).
2666 * @note On this STM32 serie, setting of external trigger edge is performed
2667 * using function @ref LL_ADC_INJ_StartConversionExtTrig().
2668 * @note Availability of parameters of trigger sources from timer
2669 * depends on timers availability on the selected device.
2670 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource\n
2671 * CR2 JEXTEN LL_ADC_INJ_SetTriggerSource
2672 * @param ADCx ADC instance
2673 * @param TriggerSource This parameter can be one of the following values:
2674 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
2675 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
2676 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
2677 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
2678 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
2679 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH2
2680 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
2681 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1
2682 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2
2683 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3
2684 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
2685 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4
2686 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO
2687 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2
2688 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH3
2689 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
2690 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
2691 * @retval None
2692 */
2693 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
2694 {
2695 /* Note: On this STM32 serie, ADC group injected external trigger edge */
2696 /* is used to perform a ADC conversion start. */
2697 /* This function does not set external trigger edge. */
2698 /* This feature is set using function */
2699 /* @ref LL_ADC_INJ_StartConversionExtTrig(). */
2700 MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL));
2701 }
2702
2703 /**
2704 * @brief Get ADC group injected conversion trigger source:
2705 * internal (SW start) or from external IP (timer event,
2706 * external interrupt line).
2707 * @note To determine whether group injected trigger source is
2708 * internal (SW start) or external, without detail
2709 * of which peripheral is selected as external trigger,
2710 * (equivalent to
2711 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
2712 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
2713 * @note Availability of parameters of trigger sources from timer
2714 * depends on timers availability on the selected device.
2715 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource\n
2716 * CR2 JEXTEN LL_ADC_INJ_GetTriggerSource
2717 * @param ADCx ADC instance
2718 * @retval Returned value can be one of the following values:
2719 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
2720 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
2721 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
2722 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
2723 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
2724 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH2
2725 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
2726 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1
2727 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2
2728 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3
2729 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
2730 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4
2731 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO
2732 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2
2733 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH3
2734 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
2735 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
2736 */
2737 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
2738 {
2739 register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN);
2740
2741 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
2742 /* corresponding to ADC_CR2_JEXTEN {0; 1; 2; 3}. */
2743 register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U));
2744
2745 /* Set bitfield corresponding to ADC_CR2_JEXTEN and ADC_CR2_JEXTSEL */
2746 /* to match with triggers literals definition. */
2747 return ((TriggerSource
2748 & (ADC_INJ_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_JEXTSEL)
2749 | ((ADC_INJ_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_JEXTEN)
2750 );
2751 }
2752
2753 /**
2754 * @brief Get ADC group injected conversion trigger source internal (SW start)
2755 or external
2756 * @note In case of group injected trigger source set to external trigger,
2757 * to determine which peripheral is selected as external trigger,
2758 * use function @ref LL_ADC_INJ_GetTriggerSource.
2759 * @rmtoll CR2 JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
2760 * @param ADCx ADC instance
2761 * @retval Value "0" if trigger source external trigger
2762 * Value "1" if trigger source SW start.
2763 */
2764 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
2765 {
2766 return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN));
2767 }
2768
2769 /**
2770 * @brief Get ADC group injected conversion trigger polarity.
2771 * Applicable only for trigger source set to external trigger.
2772 * @rmtoll CR2 JEXTEN LL_ADC_INJ_GetTriggerEdge
2773 * @param ADCx ADC instance
2774 * @retval Returned value can be one of the following values:
2775 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
2776 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
2777 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
2778 */
2779 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
2780 {
2781 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN));
2782 }
2783
2784 /**
2785 * @brief Set ADC group injected sequencer length and scan direction.
2786 * @note This function performs configuration of:
2787 * - Sequence length: Number of ranks in the scan sequence.
2788 * - Sequence direction: Unless specified in parameters, sequencer
2789 * scan direction is forward (from rank 1 to rank n).
2790 * @note On this STM32 serie, group injected sequencer configuration
2791 * is conditioned to ADC instance sequencer mode.
2792 * If ADC instance sequencer mode is disabled, sequencers of
2793 * all groups (group regular, group injected) can be configured
2794 * but their execution is disabled (limited to rank 1).
2795 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2796 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2797 * ADC conversion on only 1 channel.
2798 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
2799 * @param ADCx ADC instance
2800 * @param SequencerNbRanks This parameter can be one of the following values:
2801 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
2802 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
2803 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
2804 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
2805 * @retval None
2806 */
2807 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
2808 {
2809 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
2810 }
2811
2812 /**
2813 * @brief Get ADC group injected sequencer length and scan direction.
2814 * @note This function retrieves:
2815 * - Sequence length: Number of ranks in the scan sequence.
2816 * - Sequence direction: Unless specified in parameters, sequencer
2817 * scan direction is forward (from rank 1 to rank n).
2818 * @note On this STM32 serie, group injected sequencer configuration
2819 * is conditioned to ADC instance sequencer mode.
2820 * If ADC instance sequencer mode is disabled, sequencers of
2821 * all groups (group regular, group injected) can be configured
2822 * but their execution is disabled (limited to rank 1).
2823 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2824 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2825 * ADC conversion on only 1 channel.
2826 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
2827 * @param ADCx ADC instance
2828 * @retval Returned value can be one of the following values:
2829 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
2830 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
2831 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
2832 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
2833 */
2834 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
2835 {
2836 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
2837 }
2838
2839 /**
2840 * @brief Set ADC group injected sequencer discontinuous mode:
2841 * sequence subdivided and scan conversions interrupted every selected
2842 * number of ranks.
2843 * @note It is not possible to enable both ADC group injected
2844 * auto-injected mode and sequencer discontinuous mode.
2845 * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont
2846 * @param ADCx ADC instance
2847 * @param SeqDiscont This parameter can be one of the following values:
2848 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
2849 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
2850 * @retval None
2851 */
2852 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
2853 {
2854 MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont);
2855 }
2856
2857 /**
2858 * @brief Get ADC group injected sequencer discontinuous mode:
2859 * sequence subdivided and scan conversions interrupted every selected
2860 * number of ranks.
2861 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont
2862 * @param ADCx ADC instance
2863 * @retval Returned value can be one of the following values:
2864 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
2865 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
2866 */
2867 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
2868 {
2869 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN));
2870 }
2871
2872 /**
2873 * @brief Set ADC group injected sequence: channel on the selected
2874 * sequence rank.
2875 * @note Depending on devices and packages, some channels may not be available.
2876 * Refer to device datasheet for channels availability.
2877 * @note On this STM32 serie, to measure internal channels (VrefInt,
2878 * TempSensor, ...), measurement paths to internal channels must be
2879 * enabled separately.
2880 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2881 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
2882 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
2883 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
2884 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
2885 * @param ADCx ADC instance
2886 * @param Rank This parameter can be one of the following values:
2887 * @arg @ref LL_ADC_INJ_RANK_1
2888 * @arg @ref LL_ADC_INJ_RANK_2
2889 * @arg @ref LL_ADC_INJ_RANK_3
2890 * @arg @ref LL_ADC_INJ_RANK_4
2891 * @param Channel This parameter can be one of the following values:
2892 * @arg @ref LL_ADC_CHANNEL_0
2893 * @arg @ref LL_ADC_CHANNEL_1
2894 * @arg @ref LL_ADC_CHANNEL_2
2895 * @arg @ref LL_ADC_CHANNEL_3
2896 * @arg @ref LL_ADC_CHANNEL_4
2897 * @arg @ref LL_ADC_CHANNEL_5
2898 * @arg @ref LL_ADC_CHANNEL_6
2899 * @arg @ref LL_ADC_CHANNEL_7
2900 * @arg @ref LL_ADC_CHANNEL_8
2901 * @arg @ref LL_ADC_CHANNEL_9
2902 * @arg @ref LL_ADC_CHANNEL_10
2903 * @arg @ref LL_ADC_CHANNEL_11
2904 * @arg @ref LL_ADC_CHANNEL_12
2905 * @arg @ref LL_ADC_CHANNEL_13
2906 * @arg @ref LL_ADC_CHANNEL_14
2907 * @arg @ref LL_ADC_CHANNEL_15
2908 * @arg @ref LL_ADC_CHANNEL_16
2909 * @arg @ref LL_ADC_CHANNEL_17
2910 * @arg @ref LL_ADC_CHANNEL_18
2911 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2912 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
2913 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2914 *
2915 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
2916 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
2917 * @retval None
2918 */
2919 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
2920 {
2921 /* Set bits with content of parameter "Channel" with bits position */
2922 /* in register depending on parameter "Rank". */
2923 /* Parameters "Rank" and "Channel" are used with masks because containing */
2924 /* other bits reserved for other purpose. */
2925 register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
2926
2927 MODIFY_REG(ADCx->JSQR,
2928 ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))),
2929 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))));
2930 }
2931
2932 /**
2933 * @brief Get ADC group injected sequence: channel on the selected
2934 * sequence rank.
2935 * @note Depending on devices and packages, some channels may not be available.
2936 * Refer to device datasheet for channels availability.
2937 * @note Usage of the returned channel number:
2938 * - To reinject this channel into another function LL_ADC_xxx:
2939 * the returned channel number is only partly formatted on definition
2940 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
2941 * with parts of literals LL_ADC_CHANNEL_x or using
2942 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2943 * Then the selected literal LL_ADC_CHANNEL_x can be used
2944 * as parameter for another function.
2945 * - To get the channel number in decimal format:
2946 * process the returned value with the helper macro
2947 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2948 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
2949 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
2950 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
2951 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
2952 * @param ADCx ADC instance
2953 * @param Rank This parameter can be one of the following values:
2954 * @arg @ref LL_ADC_INJ_RANK_1
2955 * @arg @ref LL_ADC_INJ_RANK_2
2956 * @arg @ref LL_ADC_INJ_RANK_3
2957 * @arg @ref LL_ADC_INJ_RANK_4
2958 * @retval Returned value can be one of the following values:
2959 * @arg @ref LL_ADC_CHANNEL_0
2960 * @arg @ref LL_ADC_CHANNEL_1
2961 * @arg @ref LL_ADC_CHANNEL_2
2962 * @arg @ref LL_ADC_CHANNEL_3
2963 * @arg @ref LL_ADC_CHANNEL_4
2964 * @arg @ref LL_ADC_CHANNEL_5
2965 * @arg @ref LL_ADC_CHANNEL_6
2966 * @arg @ref LL_ADC_CHANNEL_7
2967 * @arg @ref LL_ADC_CHANNEL_8
2968 * @arg @ref LL_ADC_CHANNEL_9
2969 * @arg @ref LL_ADC_CHANNEL_10
2970 * @arg @ref LL_ADC_CHANNEL_11
2971 * @arg @ref LL_ADC_CHANNEL_12
2972 * @arg @ref LL_ADC_CHANNEL_13
2973 * @arg @ref LL_ADC_CHANNEL_14
2974 * @arg @ref LL_ADC_CHANNEL_15
2975 * @arg @ref LL_ADC_CHANNEL_16
2976 * @arg @ref LL_ADC_CHANNEL_17
2977 * @arg @ref LL_ADC_CHANNEL_18
2978 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2979 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
2980 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2981 *
2982 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
2983 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
2984 * (1) For ADC channel read back from ADC register,
2985 * comparison with internal channel parameter to be done
2986 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2987 */
2988 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
2989 {
2990 register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
2991
2992 return (uint32_t)(READ_BIT(ADCx->JSQR,
2993 ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))))
2994 >> (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))
2995 );
2996 }
2997
2998 /**
2999 * @brief Set ADC group injected conversion trigger:
3000 * independent or from ADC group regular.
3001 * @note This mode can be used to extend number of data registers
3002 * updated after one ADC conversion trigger and with data
3003 * permanently kept (not erased by successive conversions of scan of
3004 * ADC sequencer ranks), up to 5 data registers:
3005 * 1 data register on ADC group regular, 4 data registers
3006 * on ADC group injected.
3007 * @note If ADC group injected injected trigger source is set to an
3008 * external trigger, this feature must be must be set to
3009 * independent trigger.
3010 * ADC group injected automatic trigger is compliant only with
3011 * group injected trigger source set to SW start, without any
3012 * further action on ADC group injected conversion start or stop:
3013 * in this case, ADC group injected is controlled only
3014 * from ADC group regular.
3015 * @note It is not possible to enable both ADC group injected
3016 * auto-injected mode and sequencer discontinuous mode.
3017 * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto
3018 * @param ADCx ADC instance
3019 * @param TrigAuto This parameter can be one of the following values:
3020 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
3021 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
3022 * @retval None
3023 */
3024 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
3025 {
3026 MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto);
3027 }
3028
3029 /**
3030 * @brief Get ADC group injected conversion trigger:
3031 * independent or from ADC group regular.
3032 * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto
3033 * @param ADCx ADC instance
3034 * @retval Returned value can be one of the following values:
3035 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
3036 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
3037 */
3038 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
3039 {
3040 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO));
3041 }
3042
3043 /**
3044 * @brief Set ADC group injected offset.
3045 * @note It sets:
3046 * - ADC group injected rank to which the offset programmed
3047 * will be applied
3048 * - Offset level (offset to be subtracted from the raw
3049 * converted data).
3050 * Caution: Offset format is dependent to ADC resolution:
3051 * offset has to be left-aligned on bit 11, the LSB (right bits)
3052 * are set to 0.
3053 * @note Offset cannot be enabled or disabled.
3054 * To emulate offset disabled, set an offset value equal to 0.
3055 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n
3056 * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n
3057 * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n
3058 * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset
3059 * @param ADCx ADC instance
3060 * @param Rank This parameter can be one of the following values:
3061 * @arg @ref LL_ADC_INJ_RANK_1
3062 * @arg @ref LL_ADC_INJ_RANK_2
3063 * @arg @ref LL_ADC_INJ_RANK_3
3064 * @arg @ref LL_ADC_INJ_RANK_4
3065 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
3066 * @retval None
3067 */
3068 __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
3069 {
3070 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
3071
3072 MODIFY_REG(*preg,
3073 ADC_JOFR1_JOFFSET1,
3074 OffsetLevel);
3075 }
3076
3077 /**
3078 * @brief Get ADC group injected offset.
3079 * @note It gives offset level (offset to be subtracted from the raw converted data).
3080 * Caution: Offset format is dependent to ADC resolution:
3081 * offset has to be left-aligned on bit 11, the LSB (right bits)
3082 * are set to 0.
3083 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n
3084 * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n
3085 * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n
3086 * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset
3087 * @param ADCx ADC instance
3088 * @param Rank This parameter can be one of the following values:
3089 * @arg @ref LL_ADC_INJ_RANK_1
3090 * @arg @ref LL_ADC_INJ_RANK_2
3091 * @arg @ref LL_ADC_INJ_RANK_3
3092 * @arg @ref LL_ADC_INJ_RANK_4
3093 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3094 */
3095 __STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
3096 {
3097 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
3098
3099 return (uint32_t)(READ_BIT(*preg,
3100 ADC_JOFR1_JOFFSET1)
3101 );
3102 }
3103
3104 /**
3105 * @}
3106 */
3107
3108 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
3109 * @{
3110 */
3111
3112 /**
3113 * @brief Set sampling time of the selected ADC channel
3114 * Unit: ADC clock cycles.
3115 * @note On this device, sampling time is on channel scope: independently
3116 * of channel mapped on ADC group regular or injected.
3117 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
3118 * converted:
3119 * sampling time constraints must be respected (sampling time can be
3120 * adjusted in function of ADC clock frequency and sampling time
3121 * setting).
3122 * Refer to device datasheet for timings values (parameters TS_vrefint,
3123 * TS_temp, ...).
3124 * @note Conversion time is the addition of sampling time and processing time.
3125 * Refer to reference manual for ADC processing time of
3126 * this STM32 serie.
3127 * @note In case of ADC conversion of internal channel (VrefInt,
3128 * temperature sensor, ...), a sampling time minimum value
3129 * is required.
3130 * Refer to device datasheet.
3131 * @rmtoll SMPR1 SMP18 LL_ADC_SetChannelSamplingTime\n
3132 * SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n
3133 * SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n
3134 * SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n
3135 * SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n
3136 * SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n
3137 * SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n
3138 * SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n
3139 * SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n
3140 * SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n
3141 * SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n
3142 * SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n
3143 * SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n
3144 * SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n
3145 * SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n
3146 * SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n
3147 * SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n
3148 * SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n
3149 * SMPR2 SMP0 LL_ADC_SetChannelSamplingTime
3150 * @param ADCx ADC instance
3151 * @param Channel This parameter can be one of the following values:
3152 * @arg @ref LL_ADC_CHANNEL_0
3153 * @arg @ref LL_ADC_CHANNEL_1
3154 * @arg @ref LL_ADC_CHANNEL_2
3155 * @arg @ref LL_ADC_CHANNEL_3
3156 * @arg @ref LL_ADC_CHANNEL_4
3157 * @arg @ref LL_ADC_CHANNEL_5
3158 * @arg @ref LL_ADC_CHANNEL_6
3159 * @arg @ref LL_ADC_CHANNEL_7
3160 * @arg @ref LL_ADC_CHANNEL_8
3161 * @arg @ref LL_ADC_CHANNEL_9
3162 * @arg @ref LL_ADC_CHANNEL_10
3163 * @arg @ref LL_ADC_CHANNEL_11
3164 * @arg @ref LL_ADC_CHANNEL_12
3165 * @arg @ref LL_ADC_CHANNEL_13
3166 * @arg @ref LL_ADC_CHANNEL_14
3167 * @arg @ref LL_ADC_CHANNEL_15
3168 * @arg @ref LL_ADC_CHANNEL_16
3169 * @arg @ref LL_ADC_CHANNEL_17
3170 * @arg @ref LL_ADC_CHANNEL_18
3171 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3172 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
3173 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3174 *
3175 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
3176 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
3177 * @param SamplingTime This parameter can be one of the following values:
3178 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES
3179 * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES
3180 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES
3181 * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES
3182 * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES
3183 * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES
3184 * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES
3185 * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES
3186 * @retval None
3187 */
3188 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
3189 {
3190 /* Set bits with content of parameter "SamplingTime" with bits position */
3191 /* in register and register position depending on parameter "Channel". */
3192 /* Parameter "Channel" is used with masks because containing */
3193 /* other bits reserved for other purpose. */
3194 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
3195
3196 MODIFY_REG(*preg,
3197 ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
3198 SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
3199 }
3200
3201 /**
3202 * @brief Get sampling time of the selected ADC channel
3203 * Unit: ADC clock cycles.
3204 * @note On this device, sampling time is on channel scope: independently
3205 * of channel mapped on ADC group regular or injected.
3206 * @note Conversion time is the addition of sampling time and processing time.
3207 * Refer to reference manual for ADC processing time of
3208 * this STM32 serie.
3209 * @rmtoll SMPR1 SMP18 LL_ADC_GetChannelSamplingTime\n
3210 * SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n
3211 * SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n
3212 * SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n
3213 * SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n
3214 * SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n
3215 * SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n
3216 * SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n
3217 * SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n
3218 * SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n
3219 * SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n
3220 * SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n
3221 * SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n
3222 * SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n
3223 * SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n
3224 * SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n
3225 * SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n
3226 * SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n
3227 * SMPR2 SMP0 LL_ADC_GetChannelSamplingTime
3228 * @param ADCx ADC instance
3229 * @param Channel This parameter can be one of the following values:
3230 * @arg @ref LL_ADC_CHANNEL_0
3231 * @arg @ref LL_ADC_CHANNEL_1
3232 * @arg @ref LL_ADC_CHANNEL_2
3233 * @arg @ref LL_ADC_CHANNEL_3
3234 * @arg @ref LL_ADC_CHANNEL_4
3235 * @arg @ref LL_ADC_CHANNEL_5
3236 * @arg @ref LL_ADC_CHANNEL_6
3237 * @arg @ref LL_ADC_CHANNEL_7
3238 * @arg @ref LL_ADC_CHANNEL_8
3239 * @arg @ref LL_ADC_CHANNEL_9
3240 * @arg @ref LL_ADC_CHANNEL_10
3241 * @arg @ref LL_ADC_CHANNEL_11
3242 * @arg @ref LL_ADC_CHANNEL_12
3243 * @arg @ref LL_ADC_CHANNEL_13
3244 * @arg @ref LL_ADC_CHANNEL_14
3245 * @arg @ref LL_ADC_CHANNEL_15
3246 * @arg @ref LL_ADC_CHANNEL_16
3247 * @arg @ref LL_ADC_CHANNEL_17
3248 * @arg @ref LL_ADC_CHANNEL_18
3249 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3250 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
3251 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3252 *
3253 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
3254 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
3255 * @retval Returned value can be one of the following values:
3256 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES
3257 * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES
3258 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES
3259 * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES
3260 * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES
3261 * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES
3262 * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES
3263 * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES
3264 */
3265 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
3266 {
3267 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
3268
3269 return (uint32_t)(READ_BIT(*preg,
3270 ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
3271 >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
3272 );
3273 }
3274
3275 /**
3276 * @}
3277 */
3278
3279 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
3280 * @{
3281 */
3282
3283 /**
3284 * @brief Set ADC analog watchdog monitored channels:
3285 * a single channel or all channels,
3286 * on ADC groups regular and-or injected.
3287 * @note Once monitored channels are selected, analog watchdog
3288 * is enabled.
3289 * @note In case of need to define a single channel to monitor
3290 * with analog watchdog from sequencer channel definition,
3291 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
3292 * @note On this STM32 serie, there is only 1 kind of analog watchdog
3293 * instance:
3294 * - AWD standard (instance AWD1):
3295 * - channels monitored: can monitor 1 channel or all channels.
3296 * - groups monitored: ADC groups regular and-or injected.
3297 * - resolution: resolution is not limited (corresponds to
3298 * ADC resolution configured).
3299 * @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
3300 * CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
3301 * CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels
3302 * @param ADCx ADC instance
3303 * @param AWDChannelGroup This parameter can be one of the following values:
3304 * @arg @ref LL_ADC_AWD_DISABLE
3305 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
3306 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
3307 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
3308 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
3309 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
3310 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
3311 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
3312 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
3313 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
3314 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
3315 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
3316 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
3317 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
3318 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
3319 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
3320 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
3321 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
3322 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
3323 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
3324 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
3325 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
3326 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
3327 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
3328 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
3329 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
3330 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
3331 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
3332 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
3333 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
3334 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
3335 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
3336 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
3337 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
3338 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
3339 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
3340 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
3341 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
3342 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
3343 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
3344 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
3345 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
3346 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
3347 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
3348 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
3349 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
3350 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
3351 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
3352 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
3353 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
3354 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
3355 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
3356 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
3357 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
3358 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
3359 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
3360 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
3361 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
3362 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
3363 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
3364 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
3365 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
3366 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
3367 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
3368 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2)
3369 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2)
3370 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2)
3371 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
3372 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1)
3373 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
3374 *
3375 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
3376 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
3377 * @retval None
3378 */
3379 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
3380 {
3381 MODIFY_REG(ADCx->CR1,
3382 (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH),
3383 AWDChannelGroup);
3384 }
3385
3386 /**
3387 * @brief Get ADC analog watchdog monitored channel.
3388 * @note Usage of the returned channel number:
3389 * - To reinject this channel into another function LL_ADC_xxx:
3390 * the returned channel number is only partly formatted on definition
3391 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3392 * with parts of literals LL_ADC_CHANNEL_x or using
3393 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3394 * Then the selected literal LL_ADC_CHANNEL_x can be used
3395 * as parameter for another function.
3396 * - To get the channel number in decimal format:
3397 * process the returned value with the helper macro
3398 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3399 * Applicable only when the analog watchdog is set to monitor
3400 * one channel.
3401 * @note On this STM32 serie, there is only 1 kind of analog watchdog
3402 * instance:
3403 * - AWD standard (instance AWD1):
3404 * - channels monitored: can monitor 1 channel or all channels.
3405 * - groups monitored: ADC groups regular and-or injected.
3406 * - resolution: resolution is not limited (corresponds to
3407 * ADC resolution configured).
3408 * @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
3409 * CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
3410 * CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels
3411 * @param ADCx ADC instance
3412 * @retval Returned value can be one of the following values:
3413 * @arg @ref LL_ADC_AWD_DISABLE
3414 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
3415 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
3416 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
3417 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
3418 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
3419 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
3420 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
3421 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
3422 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
3423 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
3424 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
3425 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
3426 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
3427 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
3428 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
3429 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
3430 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
3431 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
3432 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
3433 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
3434 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
3435 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
3436 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
3437 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
3438 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
3439 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
3440 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
3441 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
3442 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
3443 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
3444 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
3445 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
3446 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
3447 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
3448 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
3449 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
3450 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
3451 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
3452 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
3453 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
3454 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
3455 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
3456 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
3457 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
3458 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
3459 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
3460 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
3461 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
3462 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
3463 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
3464 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
3465 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
3466 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
3467 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
3468 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
3469 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
3470 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
3471 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
3472 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
3473 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
3474 */
3475 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
3476 {
3477 return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH)));
3478 }
3479
3480 /**
3481 * @brief Set ADC analog watchdog threshold value of threshold
3482 * high or low.
3483 * @note In case of ADC resolution different of 12 bits,
3484 * analog watchdog thresholds data require a specific shift.
3485 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
3486 * @note On this STM32 serie, there is only 1 kind of analog watchdog
3487 * instance:
3488 * - AWD standard (instance AWD1):
3489 * - channels monitored: can monitor 1 channel or all channels.
3490 * - groups monitored: ADC groups regular and-or injected.
3491 * - resolution: resolution is not limited (corresponds to
3492 * ADC resolution configured).
3493 * @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n
3494 * LTR LT LL_ADC_SetAnalogWDThresholds
3495 * @param ADCx ADC instance
3496 * @param AWDThresholdsHighLow This parameter can be one of the following values:
3497 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
3498 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
3499 * @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF
3500 * @retval None
3501 */
3502 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
3503 {
3504 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
3505
3506 MODIFY_REG(*preg,
3507 ADC_HTR_HT,
3508 AWDThresholdValue);
3509 }
3510
3511 /**
3512 * @brief Get ADC analog watchdog threshold value of threshold high or
3513 * threshold low.
3514 * @note In case of ADC resolution different of 12 bits,
3515 * analog watchdog thresholds data require a specific shift.
3516 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
3517 * @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n
3518 * LTR LT LL_ADC_GetAnalogWDThresholds
3519 * @param ADCx ADC instance
3520 * @param AWDThresholdsHighLow This parameter can be one of the following values:
3521 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
3522 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
3523 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3524 */
3525 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
3526 {
3527 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
3528
3529 return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
3530 }
3531
3532 /**
3533 * @}
3534 */
3535
3536 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
3537 * @{
3538 */
3539
3540 #if defined(ADC_MULTIMODE_SUPPORT)
3541 /**
3542 * @brief Set ADC multimode configuration to operate in independent mode
3543 * or multimode (for devices with several ADC instances).
3544 * @note If multimode configuration: the selected ADC instance is
3545 * either master or slave depending on hardware.
3546 * Refer to reference manual.
3547 * @rmtoll CCR MULTI LL_ADC_SetMultimode
3548 * @param ADCxy_COMMON ADC common instance
3549 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3550 * @param Multimode This parameter can be one of the following values:
3551 * @arg @ref LL_ADC_MULTI_INDEPENDENT
3552 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
3553 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
3554 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
3555 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
3556 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
3557 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
3558 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
3559 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM
3560 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT
3561 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT
3562 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT
3563 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL
3564 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN
3565 * @retval None
3566 */
3567 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
3568 {
3569 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MULTI, Multimode);
3570 }
3571
3572 /**
3573 * @brief Get ADC multimode configuration to operate in independent mode
3574 * or multimode (for devices with several ADC instances).
3575 * @note If multimode configuration: the selected ADC instance is
3576 * either master or slave depending on hardware.
3577 * Refer to reference manual.
3578 * @rmtoll CCR MULTI LL_ADC_GetMultimode
3579 * @param ADCxy_COMMON ADC common instance
3580 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3581 * @retval Returned value can be one of the following values:
3582 * @arg @ref LL_ADC_MULTI_INDEPENDENT
3583 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
3584 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
3585 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
3586 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
3587 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
3588 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
3589 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
3590 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM
3591 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT
3592 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT
3593 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT
3594 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL
3595 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN
3596 */
3597 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
3598 {
3599 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MULTI));
3600 }
3601
3602 /**
3603 * @brief Set ADC multimode conversion data transfer: no transfer
3604 * or transfer by DMA.
3605 * @note If ADC multimode transfer by DMA is not selected:
3606 * each ADC uses its own DMA channel, with its individual
3607 * DMA transfer settings.
3608 * If ADC multimode transfer by DMA is selected:
3609 * One DMA channel is used for both ADC (DMA of ADC master)
3610 * Specifies the DMA requests mode:
3611 * - Limited mode (One shot mode): DMA transfer requests are stopped
3612 * when number of DMA data transfers (number of
3613 * ADC conversions) is reached.
3614 * This ADC mode is intended to be used with DMA mode non-circular.
3615 * - Unlimited mode: DMA transfer requests are unlimited,
3616 * whatever number of DMA data transfers (number of
3617 * ADC conversions).
3618 * This ADC mode is intended to be used with DMA mode circular.
3619 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3620 * mode non-circular:
3621 * when DMA transfers size will be reached, DMA will stop transfers of
3622 * ADC conversions data ADC will raise an overrun error
3623 * (overrun flag and interruption if enabled).
3624 * @note How to retrieve multimode conversion data:
3625 * Whatever multimode transfer by DMA setting: using function
3626 * @ref LL_ADC_REG_ReadMultiConversionData32().
3627 * If ADC multimode transfer by DMA is selected: conversion data
3628 * is a raw data with ADC master and slave concatenated.
3629 * A macro is available to get the conversion data of
3630 * ADC master or ADC slave: see helper macro
3631 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
3632 * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n
3633 * CCR DDS LL_ADC_SetMultiDMATransfer
3634 * @param ADCxy_COMMON ADC common instance
3635 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3636 * @param MultiDMATransfer This parameter can be one of the following values:
3637 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
3638 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1
3639 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2
3640 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3
3641 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1
3642 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2
3643 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3
3644 * @retval None
3645 */
3646 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
3647 {
3648 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS, MultiDMATransfer);
3649 }
3650
3651 /**
3652 * @brief Get ADC multimode conversion data transfer: no transfer
3653 * or transfer by DMA.
3654 * @note If ADC multimode transfer by DMA is not selected:
3655 * each ADC uses its own DMA channel, with its individual
3656 * DMA transfer settings.
3657 * If ADC multimode transfer by DMA is selected:
3658 * One DMA channel is used for both ADC (DMA of ADC master)
3659 * Specifies the DMA requests mode:
3660 * - Limited mode (One shot mode): DMA transfer requests are stopped
3661 * when number of DMA data transfers (number of
3662 * ADC conversions) is reached.
3663 * This ADC mode is intended to be used with DMA mode non-circular.
3664 * - Unlimited mode: DMA transfer requests are unlimited,
3665 * whatever number of DMA data transfers (number of
3666 * ADC conversions).
3667 * This ADC mode is intended to be used with DMA mode circular.
3668 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3669 * mode non-circular:
3670 * when DMA transfers size will be reached, DMA will stop transfers of
3671 * ADC conversions data ADC will raise an overrun error
3672 * (overrun flag and interruption if enabled).
3673 * @note How to retrieve multimode conversion data:
3674 * Whatever multimode transfer by DMA setting: using function
3675 * @ref LL_ADC_REG_ReadMultiConversionData32().
3676 * If ADC multimode transfer by DMA is selected: conversion data
3677 * is a raw data with ADC master and slave concatenated.
3678 * A macro is available to get the conversion data of
3679 * ADC master or ADC slave: see helper macro
3680 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
3681 * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n
3682 * CCR DDS LL_ADC_GetMultiDMATransfer
3683 * @param ADCxy_COMMON ADC common instance
3684 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3685 * @retval Returned value can be one of the following values:
3686 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
3687 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1
3688 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2
3689 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3
3690 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1
3691 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2
3692 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3
3693 */
3694 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
3695 {
3696 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS));
3697 }
3698
3699 /**
3700 * @brief Set ADC multimode delay between 2 sampling phases.
3701 * @note The sampling delay range depends on ADC resolution:
3702 * - ADC resolution 12 bits can have maximum delay of 12 cycles.
3703 * - ADC resolution 10 bits can have maximum delay of 10 cycles.
3704 * - ADC resolution 8 bits can have maximum delay of 8 cycles.
3705 * - ADC resolution 6 bits can have maximum delay of 6 cycles.
3706 * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
3707 * @param ADCxy_COMMON ADC common instance
3708 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3709 * @param MultiTwoSamplingDelay This parameter can be one of the following values:
3710 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
3711 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
3712 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
3713 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
3714 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
3715 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
3716 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
3717 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
3718 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
3719 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES
3720 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES
3721 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES
3722 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES
3723 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES
3724 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES
3725 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES
3726 * @retval None
3727 */
3728 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
3729 {
3730 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
3731 }
3732
3733 /**
3734 * @brief Get ADC multimode delay between 2 sampling phases.
3735 * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
3736 * @param ADCxy_COMMON ADC common instance
3737 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3738 * @retval Returned value can be one of the following values:
3739 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
3740 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
3741 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
3742 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
3743 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
3744 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
3745 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
3746 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
3747 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
3748 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES
3749 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES
3750 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES
3751 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES
3752 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES
3753 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES
3754 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES
3755 */
3756 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
3757 {
3758 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
3759 }
3760 #endif /* ADC_MULTIMODE_SUPPORT */
3761
3762 /**
3763 * @}
3764 */
3765 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
3766 * @{
3767 */
3768
3769 /**
3770 * @brief Enable the selected ADC instance.
3771 * @note On this STM32 serie, after ADC enable, a delay for
3772 * ADC internal analog stabilization is required before performing a
3773 * ADC conversion start.
3774 * Refer to device datasheet, parameter tSTAB.
3775 * @rmtoll CR2 ADON LL_ADC_Enable
3776 * @param ADCx ADC instance
3777 * @retval None
3778 */
3779 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
3780 {
3781 SET_BIT(ADCx->CR2, ADC_CR2_ADON);
3782 }
3783
3784 /**
3785 * @brief Disable the selected ADC instance.
3786 * @rmtoll CR2 ADON LL_ADC_Disable
3787 * @param ADCx ADC instance
3788 * @retval None
3789 */
3790 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
3791 {
3792 CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON);
3793 }
3794
3795 /**
3796 * @brief Get the selected ADC instance enable state.
3797 * @rmtoll CR2 ADON LL_ADC_IsEnabled
3798 * @param ADCx ADC instance
3799 * @retval 0: ADC is disabled, 1: ADC is enabled.
3800 */
3801 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
3802 {
3803 return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON));
3804 }
3805
3806 /**
3807 * @}
3808 */
3809
3810 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
3811 * @{
3812 */
3813
3814 /**
3815 * @brief Start ADC group regular conversion.
3816 * @note On this STM32 serie, this function is relevant only for
3817 * internal trigger (SW start), not for external trigger:
3818 * - If ADC trigger has been set to software start, ADC conversion
3819 * starts immediately.
3820 * - If ADC trigger has been set to external trigger, ADC conversion
3821 * start must be performed using function
3822 * @ref LL_ADC_REG_StartConversionExtTrig().
3823 * (if external trigger edge would have been set during ADC other
3824 * settings, ADC conversion would start at trigger event
3825 * as soon as ADC is enabled).
3826 * @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart
3827 * @param ADCx ADC instance
3828 * @retval None
3829 */
3830 __STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx)
3831 {
3832 SET_BIT(ADCx->CR2, ADC_CR2_SWSTART);
3833 }
3834
3835 /**
3836 * @brief Start ADC group regular conversion from external trigger.
3837 * @note ADC conversion will start at next trigger event (on the selected
3838 * trigger edge) following the ADC start conversion command.
3839 * @note On this STM32 serie, this function is relevant for
3840 * ADC conversion start from external trigger.
3841 * If internal trigger (SW start) is needed, perform ADC conversion
3842 * start using function @ref LL_ADC_REG_StartConversionSWStart().
3843 * @rmtoll CR2 EXTEN LL_ADC_REG_StartConversionExtTrig
3844 * @param ExternalTriggerEdge This parameter can be one of the following values:
3845 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3846 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3847 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3848 * @param ADCx ADC instance
3849 * @retval None
3850 */
3851 __STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
3852 {
3853 SET_BIT(ADCx->CR2, ExternalTriggerEdge);
3854 }
3855
3856 /**
3857 * @brief Stop ADC group regular conversion from external trigger.
3858 * @note No more ADC conversion will start at next trigger event
3859 * following the ADC stop conversion command.
3860 * If a conversion is on-going, it will be completed.
3861 * @note On this STM32 serie, there is no specific command
3862 * to stop a conversion on-going or to stop ADC converting
3863 * in continuous mode. These actions can be performed
3864 * using function @ref LL_ADC_Disable().
3865 * @rmtoll CR2 EXTEN LL_ADC_REG_StopConversionExtTrig
3866 * @param ADCx ADC instance
3867 * @retval None
3868 */
3869 __STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)
3870 {
3871 CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTEN);
3872 }
3873
3874 /**
3875 * @brief Get ADC group regular conversion data, range fit for
3876 * all ADC configurations: all ADC resolutions and
3877 * all oversampling increased data width (for devices
3878 * with feature oversampling).
3879 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
3880 * @param ADCx ADC instance
3881 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
3882 */
3883 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
3884 {
3885 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3886 }
3887
3888 /**
3889 * @brief Get ADC group regular conversion data, range fit for
3890 * ADC resolution 12 bits.
3891 * @note For devices with feature oversampling: Oversampling
3892 * can increase data width, function for extended range
3893 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
3894 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
3895 * @param ADCx ADC instance
3896 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3897 */
3898 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
3899 {
3900 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3901 }
3902
3903 /**
3904 * @brief Get ADC group regular conversion data, range fit for
3905 * ADC resolution 10 bits.
3906 * @note For devices with feature oversampling: Oversampling
3907 * can increase data width, function for extended range
3908 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
3909 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
3910 * @param ADCx ADC instance
3911 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
3912 */
3913 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
3914 {
3915 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3916 }
3917
3918 /**
3919 * @brief Get ADC group regular conversion data, range fit for
3920 * ADC resolution 8 bits.
3921 * @note For devices with feature oversampling: Oversampling
3922 * can increase data width, function for extended range
3923 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
3924 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
3925 * @param ADCx ADC instance
3926 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
3927 */
3928 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
3929 {
3930 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3931 }
3932
3933 /**
3934 * @brief Get ADC group regular conversion data, range fit for
3935 * ADC resolution 6 bits.
3936 * @note For devices with feature oversampling: Oversampling
3937 * can increase data width, function for extended range
3938 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
3939 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
3940 * @param ADCx ADC instance
3941 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
3942 */
3943 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
3944 {
3945 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3946 }
3947
3948 #if defined(ADC_MULTIMODE_SUPPORT)
3949 /**
3950 * @brief Get ADC multimode conversion data of ADC master, ADC slave
3951 * or raw data with ADC master and slave concatenated.
3952 * @note If raw data with ADC master and slave concatenated is retrieved,
3953 * a macro is available to get the conversion data of
3954 * ADC master or ADC slave: see helper macro
3955 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
3956 * (however this macro is mainly intended for multimode
3957 * transfer by DMA, because this function can do the same
3958 * by getting multimode conversion data of ADC master or ADC slave
3959 * separately).
3960 * @rmtoll CDR DATA1 LL_ADC_REG_ReadMultiConversionData32\n
3961 * CDR DATA2 LL_ADC_REG_ReadMultiConversionData32
3962 * @param ADCxy_COMMON ADC common instance
3963 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3964 * @param ConversionData This parameter can be one of the following values:
3965 * @arg @ref LL_ADC_MULTI_MASTER
3966 * @arg @ref LL_ADC_MULTI_SLAVE
3967 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
3968 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
3969 */
3970 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
3971 {
3972 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
3973 ADC_DR_ADC2DATA)
3974 >> POSITION_VAL(ConversionData)
3975 );
3976 }
3977 #endif /* ADC_MULTIMODE_SUPPORT */
3978
3979 /**
3980 * @}
3981 */
3982
3983 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
3984 * @{
3985 */
3986
3987 /**
3988 * @brief Start ADC group injected conversion.
3989 * @note On this STM32 serie, this function is relevant only for
3990 * internal trigger (SW start), not for external trigger:
3991 * - If ADC trigger has been set to software start, ADC conversion
3992 * starts immediately.
3993 * - If ADC trigger has been set to external trigger, ADC conversion
3994 * start must be performed using function
3995 * @ref LL_ADC_INJ_StartConversionExtTrig().
3996 * (if external trigger edge would have been set during ADC other
3997 * settings, ADC conversion would start at trigger event
3998 * as soon as ADC is enabled).
3999 * @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart
4000 * @param ADCx ADC instance
4001 * @retval None
4002 */
4003 __STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx)
4004 {
4005 SET_BIT(ADCx->CR2, ADC_CR2_JSWSTART);
4006 }
4007
4008 /**
4009 * @brief Start ADC group injected conversion from external trigger.
4010 * @note ADC conversion will start at next trigger event (on the selected
4011 * trigger edge) following the ADC start conversion command.
4012 * @note On this STM32 serie, this function is relevant for
4013 * ADC conversion start from external trigger.
4014 * If internal trigger (SW start) is needed, perform ADC conversion
4015 * start using function @ref LL_ADC_INJ_StartConversionSWStart().
4016 * @rmtoll CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig
4017 * @param ExternalTriggerEdge This parameter can be one of the following values:
4018 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4019 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4020 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4021 * @param ADCx ADC instance
4022 * @retval None
4023 */
4024 __STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4025 {
4026 SET_BIT(ADCx->CR2, ExternalTriggerEdge);
4027 }
4028
4029 /**
4030 * @brief Stop ADC group injected conversion from external trigger.
4031 * @note No more ADC conversion will start at next trigger event
4032 * following the ADC stop conversion command.
4033 * If a conversion is on-going, it will be completed.
4034 * @note On this STM32 serie, there is no specific command
4035 * to stop a conversion on-going or to stop ADC converting
4036 * in continuous mode. These actions can be performed
4037 * using function @ref LL_ADC_Disable().
4038 * @rmtoll CR2 JEXTEN LL_ADC_INJ_StopConversionExtTrig
4039 * @param ADCx ADC instance
4040 * @retval None
4041 */
4042 __STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
4043 {
4044 CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTEN);
4045 }
4046
4047 /**
4048 * @brief Get ADC group regular conversion data, range fit for
4049 * all ADC configurations: all ADC resolutions and
4050 * all oversampling increased data width (for devices
4051 * with feature oversampling).
4052 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
4053 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
4054 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
4055 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
4056 * @param ADCx ADC instance
4057 * @param Rank This parameter can be one of the following values:
4058 * @arg @ref LL_ADC_INJ_RANK_1
4059 * @arg @ref LL_ADC_INJ_RANK_2
4060 * @arg @ref LL_ADC_INJ_RANK_3
4061 * @arg @ref LL_ADC_INJ_RANK_4
4062 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
4063 */
4064 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
4065 {
4066 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4067
4068 return (uint32_t)(READ_BIT(*preg,
4069 ADC_JDR1_JDATA)
4070 );
4071 }
4072
4073 /**
4074 * @brief Get ADC group injected conversion data, range fit for
4075 * ADC resolution 12 bits.
4076 * @note For devices with feature oversampling: Oversampling
4077 * can increase data width, function for extended range
4078 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4079 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
4080 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
4081 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
4082 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
4083 * @param ADCx ADC instance
4084 * @param Rank This parameter can be one of the following values:
4085 * @arg @ref LL_ADC_INJ_RANK_1
4086 * @arg @ref LL_ADC_INJ_RANK_2
4087 * @arg @ref LL_ADC_INJ_RANK_3
4088 * @arg @ref LL_ADC_INJ_RANK_4
4089 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
4090 */
4091 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
4092 {
4093 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4094
4095 return (uint16_t)(READ_BIT(*preg,
4096 ADC_JDR1_JDATA)
4097 );
4098 }
4099
4100 /**
4101 * @brief Get ADC group injected conversion data, range fit for
4102 * ADC resolution 10 bits.
4103 * @note For devices with feature oversampling: Oversampling
4104 * can increase data width, function for extended range
4105 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4106 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
4107 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
4108 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
4109 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
4110 * @param ADCx ADC instance
4111 * @param Rank This parameter can be one of the following values:
4112 * @arg @ref LL_ADC_INJ_RANK_1
4113 * @arg @ref LL_ADC_INJ_RANK_2
4114 * @arg @ref LL_ADC_INJ_RANK_3
4115 * @arg @ref LL_ADC_INJ_RANK_4
4116 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
4117 */
4118 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
4119 {
4120 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4121
4122 return (uint16_t)(READ_BIT(*preg,
4123 ADC_JDR1_JDATA)
4124 );
4125 }
4126
4127 /**
4128 * @brief Get ADC group injected conversion data, range fit for
4129 * ADC resolution 8 bits.
4130 * @note For devices with feature oversampling: Oversampling
4131 * can increase data width, function for extended range
4132 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4133 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
4134 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
4135 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
4136 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
4137 * @param ADCx ADC instance
4138 * @param Rank This parameter can be one of the following values:
4139 * @arg @ref LL_ADC_INJ_RANK_1
4140 * @arg @ref LL_ADC_INJ_RANK_2
4141 * @arg @ref LL_ADC_INJ_RANK_3
4142 * @arg @ref LL_ADC_INJ_RANK_4
4143 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
4144 */
4145 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
4146 {
4147 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4148
4149 return (uint8_t)(READ_BIT(*preg,
4150 ADC_JDR1_JDATA)
4151 );
4152 }
4153
4154 /**
4155 * @brief Get ADC group injected conversion data, range fit for
4156 * ADC resolution 6 bits.
4157 * @note For devices with feature oversampling: Oversampling
4158 * can increase data width, function for extended range
4159 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4160 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
4161 * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
4162 * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
4163 * JDR4 JDATA LL_ADC_INJ_ReadConversionData6
4164 * @param ADCx ADC instance
4165 * @param Rank This parameter can be one of the following values:
4166 * @arg @ref LL_ADC_INJ_RANK_1
4167 * @arg @ref LL_ADC_INJ_RANK_2
4168 * @arg @ref LL_ADC_INJ_RANK_3
4169 * @arg @ref LL_ADC_INJ_RANK_4
4170 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
4171 */
4172 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
4173 {
4174 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4175
4176 return (uint8_t)(READ_BIT(*preg,
4177 ADC_JDR1_JDATA)
4178 );
4179 }
4180
4181 /**
4182 * @}
4183 */
4184
4185 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
4186 * @{
4187 */
4188
4189 /**
4190 * @brief Get flag ADC group regular end of unitary conversion
4191 * or end of sequence conversions, depending on
4192 * ADC configuration.
4193 * @note To configure flag of end of conversion,
4194 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4195 * @rmtoll SR EOC LL_ADC_IsActiveFlag_EOCS
4196 * @param ADCx ADC instance
4197 * @retval State of bit (1 or 0).
4198 */
4199 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCS(ADC_TypeDef *ADCx)
4200 {
4201 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS));
4202 }
4203
4204 /**
4205 * @brief Get flag ADC group regular overrun.
4206 * @rmtoll SR OVR LL_ADC_IsActiveFlag_OVR
4207 * @param ADCx ADC instance
4208 * @retval State of bit (1 or 0).
4209 */
4210 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
4211 {
4212 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
4213 }
4214
4215
4216 /**
4217 * @brief Get flag ADC group injected end of sequence conversions.
4218 * @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS
4219 * @param ADCx ADC instance
4220 * @retval State of bit (1 or 0).
4221 */
4222 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
4223 {
4224 /* Note: on this STM32 serie, there is no flag ADC group injected */
4225 /* end of unitary conversion. */
4226 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4227 /* in other STM32 families). */
4228 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
4229 }
4230
4231 /**
4232 * @brief Get flag ADC analog watchdog 1 flag
4233 * @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1
4234 * @param ADCx ADC instance
4235 * @retval State of bit (1 or 0).
4236 */
4237 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
4238 {
4239 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
4240 }
4241
4242 /**
4243 * @brief Clear flag ADC group regular end of unitary conversion
4244 * or end of sequence conversions, depending on
4245 * ADC configuration.
4246 * @note To configure flag of end of conversion,
4247 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4248 * @rmtoll SR EOC LL_ADC_ClearFlag_EOCS
4249 * @param ADCx ADC instance
4250 * @retval None
4251 */
4252 __STATIC_INLINE void LL_ADC_ClearFlag_EOCS(ADC_TypeDef *ADCx)
4253 {
4254 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOCS);
4255 }
4256
4257 /**
4258 * @brief Clear flag ADC group regular overrun.
4259 * @rmtoll SR OVR LL_ADC_ClearFlag_OVR
4260 * @param ADCx ADC instance
4261 * @retval None
4262 */
4263 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
4264 {
4265 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_OVR);
4266 }
4267
4268
4269 /**
4270 * @brief Clear flag ADC group injected end of sequence conversions.
4271 * @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS
4272 * @param ADCx ADC instance
4273 * @retval None
4274 */
4275 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
4276 {
4277 /* Note: on this STM32 serie, there is no flag ADC group injected */
4278 /* end of unitary conversion. */
4279 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4280 /* in other STM32 families). */
4281 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS);
4282 }
4283
4284 /**
4285 * @brief Clear flag ADC analog watchdog 1.
4286 * @rmtoll SR AWD LL_ADC_ClearFlag_AWD1
4287 * @param ADCx ADC instance
4288 * @retval None
4289 */
4290 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
4291 {
4292 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1);
4293 }
4294
4295 #if defined(ADC_MULTIMODE_SUPPORT)
4296 /**
4297 * @brief Get flag multimode ADC group regular end of unitary conversion
4298 * or end of sequence conversions, depending on
4299 * ADC configuration, of the ADC master.
4300 * @note To configure flag of end of conversion,
4301 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4302 * @rmtoll CSR EOC1 LL_ADC_IsActiveFlag_MST_EOCS
4303 * @param ADCxy_COMMON ADC common instance
4304 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4305 * @retval State of bit (1 or 0).
4306 */
4307 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
4308 {
4309 return (READ_BIT(ADC1->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS));
4310 }
4311
4312 /**
4313 * @brief Get flag multimode ADC group regular end of unitary conversion
4314 * or end of sequence conversions, depending on
4315 * ADC configuration, of the ADC slave 1.
4316 * @note To configure flag of end of conversion,
4317 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4318 * @rmtoll CSR EOC2 LL_ADC_IsActiveFlag_SLV1_EOCS
4319 * @param ADCxy_COMMON ADC common instance
4320 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4321 * @retval State of bit (1 or 0).
4322 */
4323 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
4324 {
4325 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV1) == (LL_ADC_FLAG_EOCS_SLV1));
4326 }
4327
4328 /**
4329 * @brief Get flag multimode ADC group regular end of unitary conversion
4330 * or end of sequence conversions, depending on
4331 * ADC configuration, of the ADC slave 2.
4332 * @note To configure flag of end of conversion,
4333 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4334 * @rmtoll CSR EOC3 LL_ADC_IsActiveFlag_SLV2_EOCS
4335 * @param ADCxy_COMMON ADC common instance
4336 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4337 * @retval State of bit (1 or 0).
4338 */
4339 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
4340 {
4341 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV2) == (LL_ADC_FLAG_EOCS_SLV2));
4342 }
4343 /**
4344 * @brief Get flag multimode ADC group regular overrun of the ADC master.
4345 * @rmtoll CSR OVR1 LL_ADC_IsActiveFlag_MST_OVR
4346 * @param ADCxy_COMMON ADC common instance
4347 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4348 * @retval State of bit (1 or 0).
4349 */
4350 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
4351 {
4352 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST));
4353 }
4354
4355 /**
4356 * @brief Get flag multimode ADC group regular overrun of the ADC slave 1.
4357 * @rmtoll CSR OVR2 LL_ADC_IsActiveFlag_SLV1_OVR
4358 * @param ADCxy_COMMON ADC common instance
4359 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4360 * @retval State of bit (1 or 0).
4361 */
4362 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
4363 {
4364 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV1) == (LL_ADC_FLAG_OVR_SLV1));
4365 }
4366
4367 /**
4368 * @brief Get flag multimode ADC group regular overrun of the ADC slave 2.
4369 * @rmtoll CSR OVR3 LL_ADC_IsActiveFlag_SLV2_OVR
4370 * @param ADCxy_COMMON ADC common instance
4371 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4372 * @retval State of bit (1 or 0).
4373 */
4374 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
4375 {
4376 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV2) == (LL_ADC_FLAG_OVR_SLV2));
4377 }
4378
4379
4380 /**
4381 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
4382 * @rmtoll CSR JEOC LL_ADC_IsActiveFlag_MST_EOCS
4383 * @param ADCxy_COMMON ADC common instance
4384 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4385 * @retval State of bit (1 or 0).
4386 */
4387 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
4388 {
4389 /* Note: on this STM32 serie, there is no flag ADC group injected */
4390 /* end of unitary conversion. */
4391 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4392 /* in other STM32 families). */
4393 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC1) == (ADC_CSR_JEOC1));
4394 }
4395
4396 /**
4397 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 1.
4398 * @rmtoll CSR JEOC2 LL_ADC_IsActiveFlag_SLV1_JEOS
4399 * @param ADCxy_COMMON ADC common instance
4400 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4401 * @retval State of bit (1 or 0).
4402 */
4403 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
4404 {
4405 /* Note: on this STM32 serie, there is no flag ADC group injected */
4406 /* end of unitary conversion. */
4407 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4408 /* in other STM32 families). */
4409 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC2) == (ADC_CSR_JEOC2));
4410 }
4411
4412 /**
4413 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 2.
4414 * @rmtoll CSR JEOC3 LL_ADC_IsActiveFlag_SLV2_JEOS
4415 * @param ADCxy_COMMON ADC common instance
4416 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4417 * @retval State of bit (1 or 0).
4418 */
4419 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
4420 {
4421 /* Note: on this STM32 serie, there is no flag ADC group injected */
4422 /* end of unitary conversion. */
4423 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4424 /* in other STM32 families). */
4425 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC3) == (ADC_CSR_JEOC3));
4426 }
4427
4428 /**
4429 * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
4430 * @rmtoll CSR AWD1 LL_ADC_IsActiveFlag_MST_AWD1
4431 * @param ADCxy_COMMON ADC common instance
4432 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4433 * @retval State of bit (1 or 0).
4434 */
4435 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
4436 {
4437 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST));
4438 }
4439
4440 /**
4441 * @brief Get flag multimode analog watchdog 1 of the ADC slave 1.
4442 * @rmtoll CSR AWD2 LL_ADC_IsActiveFlag_SLV1_AWD1
4443 * @param ADCxy_COMMON ADC common instance
4444 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4445 * @retval State of bit (1 or 0).
4446 */
4447 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
4448 {
4449 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV1) == (LL_ADC_FLAG_AWD1_SLV1));
4450 }
4451
4452 /**
4453 * @brief Get flag multimode analog watchdog 1 of the ADC slave 2.
4454 * @rmtoll CSR AWD3 LL_ADC_IsActiveFlag_SLV2_AWD1
4455 * @param ADCxy_COMMON ADC common instance
4456 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4457 * @retval State of bit (1 or 0).
4458 */
4459 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
4460 {
4461 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV2) == (LL_ADC_FLAG_AWD1_SLV2));
4462 }
4463
4464 #endif /* ADC_MULTIMODE_SUPPORT */
4465
4466 /**
4467 * @}
4468 */
4469
4470 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
4471 * @{
4472 */
4473
4474 /**
4475 * @brief Enable interruption ADC group regular end of unitary conversion
4476 * or end of sequence conversions, depending on
4477 * ADC configuration.
4478 * @note To configure flag of end of conversion,
4479 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4480 * @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOCS
4481 * @param ADCx ADC instance
4482 * @retval None
4483 */
4484 __STATIC_INLINE void LL_ADC_EnableIT_EOCS(ADC_TypeDef *ADCx)
4485 {
4486 SET_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
4487 }
4488
4489 /**
4490 * @brief Enable ADC group regular interruption overrun.
4491 * @rmtoll CR1 OVRIE LL_ADC_EnableIT_OVR
4492 * @param ADCx ADC instance
4493 * @retval None
4494 */
4495 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
4496 {
4497 SET_BIT(ADCx->CR1, LL_ADC_IT_OVR);
4498 }
4499
4500
4501 /**
4502 * @brief Enable interruption ADC group injected end of sequence conversions.
4503 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
4504 * @param ADCx ADC instance
4505 * @retval None
4506 */
4507 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
4508 {
4509 /* Note: on this STM32 serie, there is no flag ADC group injected */
4510 /* end of unitary conversion. */
4511 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4512 /* in other STM32 families). */
4513 SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
4514 }
4515
4516 /**
4517 * @brief Enable interruption ADC analog watchdog 1.
4518 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
4519 * @param ADCx ADC instance
4520 * @retval None
4521 */
4522 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
4523 {
4524 SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
4525 }
4526
4527 /**
4528 * @brief Disable interruption ADC group regular end of unitary conversion
4529 * or end of sequence conversions, depending on
4530 * ADC configuration.
4531 * @note To configure flag of end of conversion,
4532 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4533 * @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOCS
4534 * @param ADCx ADC instance
4535 * @retval None
4536 */
4537 __STATIC_INLINE void LL_ADC_DisableIT_EOCS(ADC_TypeDef *ADCx)
4538 {
4539 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
4540 }
4541
4542 /**
4543 * @brief Disable interruption ADC group regular overrun.
4544 * @rmtoll CR1 OVRIE LL_ADC_DisableIT_OVR
4545 * @param ADCx ADC instance
4546 * @retval None
4547 */
4548 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
4549 {
4550 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_OVR);
4551 }
4552
4553
4554 /**
4555 * @brief Disable interruption ADC group injected end of sequence conversions.
4556 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
4557 * @param ADCx ADC instance
4558 * @retval None
4559 */
4560 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
4561 {
4562 /* Note: on this STM32 serie, there is no flag ADC group injected */
4563 /* end of unitary conversion. */
4564 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4565 /* in other STM32 families). */
4566 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
4567 }
4568
4569 /**
4570 * @brief Disable interruption ADC analog watchdog 1.
4571 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
4572 * @param ADCx ADC instance
4573 * @retval None
4574 */
4575 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
4576 {
4577 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
4578 }
4579
4580 /**
4581 * @brief Get state of interruption ADC group regular end of unitary conversion
4582 * or end of sequence conversions, depending on
4583 * ADC configuration.
4584 * @note To configure flag of end of conversion,
4585 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4586 * (0: interrupt disabled, 1: interrupt enabled)
4587 * @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOCS
4588 * @param ADCx ADC instance
4589 * @retval State of bit (1 or 0).
4590 */
4591 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCS(ADC_TypeDef *ADCx)
4592 {
4593 return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOCS) == (LL_ADC_IT_EOCS));
4594 }
4595
4596 /**
4597 * @brief Get state of interruption ADC group regular overrun
4598 * (0: interrupt disabled, 1: interrupt enabled).
4599 * @rmtoll CR1 OVRIE LL_ADC_IsEnabledIT_OVR
4600 * @param ADCx ADC instance
4601 * @retval State of bit (1 or 0).
4602 */
4603 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
4604 {
4605 return (READ_BIT(ADCx->CR1, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
4606 }
4607
4608
4609 /**
4610 * @brief Get state of interruption ADC group injected end of sequence conversions
4611 * (0: interrupt disabled, 1: interrupt enabled).
4612 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
4613 * @param ADCx ADC instance
4614 * @retval State of bit (1 or 0).
4615 */
4616 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
4617 {
4618 /* Note: on this STM32 serie, there is no flag ADC group injected */
4619 /* end of unitary conversion. */
4620 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4621 /* in other STM32 families). */
4622 return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
4623 }
4624
4625 /**
4626 * @brief Get state of interruption ADC analog watchdog 1
4627 * (0: interrupt disabled, 1: interrupt enabled).
4628 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
4629 * @param ADCx ADC instance
4630 * @retval State of bit (1 or 0).
4631 */
4632 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
4633 {
4634 return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
4635 }
4636
4637 /**
4638 * @}
4639 */
4640
4641 #if defined(USE_FULL_LL_DRIVER)
4642 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
4643 * @{
4644 */
4645
4646 /* Initialization of some features of ADC common parameters and multimode */
4647 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
4648 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
4649 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
4650
4651 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
4652 /* (availability of ADC group injected depends on STM32 families) */
4653 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
4654
4655 /* Initialization of some features of ADC instance */
4656 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
4657 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
4658
4659 /* Initialization of some features of ADC instance and ADC group regular */
4660 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
4661 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
4662
4663 /* Initialization of some features of ADC instance and ADC group injected */
4664 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
4665 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
4666
4667 /**
4668 * @}
4669 */
4670 #endif /* USE_FULL_LL_DRIVER */
4671
4672 /**
4673 * @}
4674 */
4675
4676 /**
4677 * @}
4678 */
4679
4680 #endif /* ADC1 || ADC2 || ADC3 */
4681
4682 /**
4683 * @}
4684 */
4685
4686 #ifdef __cplusplus
4687 }
4688 #endif
4689
4690 #endif /* __STM32F4xx_LL_ADC_H */
4691
4692 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/