2 * This file is part of Cleanflight and Betaflight.
4 * Cleanflight and Betaflight are free software. You can redistribute
5 * this software and/or modify this software under the terms of the
6 * GNU General Public License as published by the Free Software
7 * Foundation, either version 3 of the License, or (at your option)
10 * Cleanflight and Betaflight are distributed in the hope that they
11 * will be useful, but WITHOUT ANY WARRANTY; without even the implied
12 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 * See the GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this software.
18 * If not, see <http://www.gnu.org/licenses/>.
29 #include "drivers/nvic.h"
35 dmaChannelDescriptor_t dmaDescriptors
[DMA_LAST_HANDLER
] = {
36 DEFINE_DMA_CHANNEL(DMA1
, 1, 0),
37 DEFINE_DMA_CHANNEL(DMA1
, 2, 4),
38 DEFINE_DMA_CHANNEL(DMA1
, 3, 8),
39 DEFINE_DMA_CHANNEL(DMA1
, 4, 12),
40 DEFINE_DMA_CHANNEL(DMA1
, 5, 16),
41 DEFINE_DMA_CHANNEL(DMA1
, 6, 20),
42 DEFINE_DMA_CHANNEL(DMA1
, 7, 24),
43 #if defined(STM32F3) || defined(STM32F10X_CL)
44 DEFINE_DMA_CHANNEL(DMA2
, 1, 0),
45 DEFINE_DMA_CHANNEL(DMA2
, 2, 4),
46 DEFINE_DMA_CHANNEL(DMA2
, 3, 8),
47 DEFINE_DMA_CHANNEL(DMA2
, 4, 12),
48 DEFINE_DMA_CHANNEL(DMA2
, 5, 16),
56 DEFINE_DMA_IRQ_HANDLER(1, 1, DMA1_CH1_HANDLER
)
57 DEFINE_DMA_IRQ_HANDLER(1, 2, DMA1_CH2_HANDLER
)
58 DEFINE_DMA_IRQ_HANDLER(1, 3, DMA1_CH3_HANDLER
)
59 DEFINE_DMA_IRQ_HANDLER(1, 4, DMA1_CH4_HANDLER
)
60 DEFINE_DMA_IRQ_HANDLER(1, 5, DMA1_CH5_HANDLER
)
61 DEFINE_DMA_IRQ_HANDLER(1, 6, DMA1_CH6_HANDLER
)
62 DEFINE_DMA_IRQ_HANDLER(1, 7, DMA1_CH7_HANDLER
)
64 #if defined(STM32F3) || defined(STM32F10X_CL)
65 DEFINE_DMA_IRQ_HANDLER(2, 1, DMA2_CH1_HANDLER
)
66 DEFINE_DMA_IRQ_HANDLER(2, 2, DMA2_CH2_HANDLER
)
67 DEFINE_DMA_IRQ_HANDLER(2, 3, DMA2_CH3_HANDLER
)
68 DEFINE_DMA_IRQ_HANDLER(2, 4, DMA2_CH4_HANDLER
)
69 DEFINE_DMA_IRQ_HANDLER(2, 5, DMA2_CH5_HANDLER
)
72 #define RETURN_TCIF_FLAG(s, d, n) if (s == DMA ## d ## _Channel ## n) return DMA ## d ## _FLAG_TC ## n
74 uint32_t dmaFlag_IT_TCIF(const dmaResource_t
*channel
)
76 RETURN_TCIF_FLAG((DMA_ARCH_TYPE
*)channel
, 1, 1);
77 RETURN_TCIF_FLAG((DMA_ARCH_TYPE
*)channel
, 1, 2);
78 RETURN_TCIF_FLAG((DMA_ARCH_TYPE
*)channel
, 1, 3);
79 RETURN_TCIF_FLAG((DMA_ARCH_TYPE
*)channel
, 1, 4);
80 RETURN_TCIF_FLAG((DMA_ARCH_TYPE
*)channel
, 1, 5);
81 RETURN_TCIF_FLAG((DMA_ARCH_TYPE
*)channel
, 1, 6);
82 RETURN_TCIF_FLAG((DMA_ARCH_TYPE
*)channel
, 1, 7);
83 RETURN_TCIF_FLAG((DMA_ARCH_TYPE
*)channel
, 2, 1);
84 RETURN_TCIF_FLAG((DMA_ARCH_TYPE
*)channel
, 2, 2);
85 RETURN_TCIF_FLAG((DMA_ARCH_TYPE
*)channel
, 2, 3);
86 RETURN_TCIF_FLAG((DMA_ARCH_TYPE
*)channel
, 2, 4);
87 RETURN_TCIF_FLAG((DMA_ARCH_TYPE
*)channel
, 2, 5);
91 #define DMA_RCC(x) ((x) == DMA1 ? RCC_AHBPeriph_DMA1 : RCC_AHBPeriph_DMA2)
92 void dmaEnable(dmaIdentifier_e identifier
)
94 const int index
= DMA_IDENTIFIER_TO_INDEX(identifier
);
96 RCC_AHBPeriphClockCmd(DMA_RCC(dmaDescriptors
[index
].dma
), ENABLE
);
99 void dmaSetHandler(dmaIdentifier_e identifier
, dmaCallbackHandlerFuncPtr callback
, uint32_t priority
, uint32_t userParam
)
101 NVIC_InitTypeDef NVIC_InitStructure
;
103 const int index
= DMA_IDENTIFIER_TO_INDEX(identifier
);
104 /* TODO: remove this - enforce the init */
105 RCC_AHBPeriphClockCmd(DMA_RCC(dmaDescriptors
[index
].dma
), ENABLE
);
106 dmaDescriptors
[index
].irqHandlerCallback
= callback
;
107 dmaDescriptors
[index
].userParam
= userParam
;
108 dmaDescriptors
[index
].completeFlag
= dmaFlag_IT_TCIF(dmaDescriptors
[index
].ref
);
110 NVIC_InitStructure
.NVIC_IRQChannel
= dmaDescriptors
[index
].irqN
;
111 NVIC_InitStructure
.NVIC_IRQChannelPreemptionPriority
= NVIC_PRIORITY_BASE(priority
);
112 NVIC_InitStructure
.NVIC_IRQChannelSubPriority
= NVIC_PRIORITY_SUB(priority
);
113 NVIC_InitStructure
.NVIC_IRQChannelCmd
= ENABLE
;
114 NVIC_Init(&NVIC_InitStructure
);