src/main/drivers/rcc.c

   1 /*
   2  * This file is part of Cleanflight and Betaflight.
   3  *
   4  * Cleanflight and Betaflight are free software. You can redistribute
   5  * this software and/or modify this software under the terms of the
   6  * GNU General Public License as published by the Free Software
   7  * Foundation, either version 3 of the License, or (at your option)
   8  * any later version.
   9  *
  10  * Cleanflight and Betaflight are distributed in the hope that they
  11  * will be useful, but WITHOUT ANY WARRANTY; without even the implied
  12  * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  13  * See the GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this software.
  17  *
  18  * If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "platform.h"
  22 #include "rcc.h"
  23
  24 void RCC_ClockCmd(rccPeriphTag_t periphTag, FunctionalState NewState)
  25 {
  26     int tag = periphTag >> 5;
  27     uint32_t mask = 1 << (periphTag & 0x1f);
  28
  29 #if defined(USE_HAL_DRIVER)
  30
  31 // Note on "suffix" macro parameter:
  32 // ENR and RSTR naming conventions for buses with multiple registers per bus differs among MCU types.
  33 // ST decided to use AxBn{L,H}ENR convention for H7 which can be handled with simple "ENR" (or "RSTR") contatenation,
  34 // while use AxBnENR{1,2} convention for G4 which requires extra "suffix" to be concatenated.
  35 // Here, we use "suffix" for all MCU types and leave it as empty where not applicable.
  36
  37 #define NOSUFFIX // Empty
  38
  39 #define __HAL_RCC_CLK_ENABLE(bus, suffix, enbit)   do {      \
  40         __IO uint32_t tmpreg;                                \
  41         SET_BIT(RCC->bus ## ENR ## suffix, enbit);           \
  42         /* Delay after an RCC peripheral clock enabling */   \
  43         tmpreg = READ_BIT(RCC->bus ## ENR ## suffix, enbit); \
  44         UNUSED(tmpreg);                                      \
  45     } while(0)
  46
  47 #define __HAL_RCC_CLK_DISABLE(bus, suffix, enbit) (RCC->bus ## ENR ## suffix &= ~(enbit))
  48
  49 #define __HAL_RCC_CLK(bus, suffix, enbit, newState) \
  50     if (newState == ENABLE) {                       \
  51         __HAL_RCC_CLK_ENABLE(bus, suffix, enbit);   \
  52     } else {                                        \
  53         __HAL_RCC_CLK_DISABLE(bus, suffix, enbit);  \
  54     }
  55
  56     switch (tag) {
  57     case RCC_AHB1:
  58         __HAL_RCC_CLK(AHB1, NOSUFFIX, mask, NewState);
  59         break;
  60
  61     case RCC_AHB2:
  62         __HAL_RCC_CLK(AHB2, NOSUFFIX, mask, NewState);
  63         break;
  64
  65 #if !(defined(STM32H7) || defined(STM32G4))
  66     case RCC_APB1:
  67         __HAL_RCC_CLK(APB1, NOSUFFIX, mask, NewState);
  68         break;
  69 #endif
  70
  71     case RCC_APB2:
  72         __HAL_RCC_CLK(APB2, NOSUFFIX, mask, NewState);
  73         break;
  74
  75 #ifdef STM32H7
  76
  77     case RCC_AHB3:
  78         __HAL_RCC_CLK(AHB3, NOSUFFIX, mask, NewState);
  79         break;
  80
  81     case RCC_AHB4:
  82         __HAL_RCC_CLK(AHB4, NOSUFFIX, mask, NewState);
  83         break;
  84
  85     case RCC_APB1L:
  86         __HAL_RCC_CLK(APB1L, NOSUFFIX, mask, NewState);
  87         break;
  88
  89     case RCC_APB1H:
  90         __HAL_RCC_CLK(APB1H, NOSUFFIX, mask, NewState);
  91         break;
  92
  93     case RCC_APB3:
  94         __HAL_RCC_CLK(APB3, NOSUFFIX, mask, NewState);
  95         break;
  96
  97     case RCC_APB4:
  98         __HAL_RCC_CLK(APB4, NOSUFFIX, mask, NewState);
  99         break;
 100 #endif
 101
 102 #ifdef STM32G4
 103
 104     case RCC_APB11:
 105         __HAL_RCC_CLK(APB1, 1, mask, NewState);
 106         break;
 107
 108     case RCC_APB12:
 109         __HAL_RCC_CLK(APB1, 2, mask, NewState);
 110         break;
 111
 112 #endif
 113     }
 114 #else
 115     switch (tag) {
 116 #if defined(STM32F3) || defined(STM32F1)
 117     case RCC_AHB:
 118         RCC_AHBPeriphClockCmd(mask, NewState);
 119         break;
 120 #endif
 121     case RCC_APB2:
 122         RCC_APB2PeriphClockCmd(mask, NewState);
 123         break;
 124     case RCC_APB1:
 125         RCC_APB1PeriphClockCmd(mask, NewState);
 126         break;
 127 #if defined(STM32F4)
 128     case RCC_AHB1:
 129         RCC_AHB1PeriphClockCmd(mask, NewState);
 130         break;
 131 #endif
 132     }
 133 #endif
 134 }
 135
 136 void RCC_ResetCmd(rccPeriphTag_t periphTag, FunctionalState NewState)
 137 {
 138     int tag = periphTag >> 5;
 139     uint32_t mask = 1 << (periphTag & 0x1f);
 140
 141 // Peripheral reset control relies on RSTR bits are identical to ENR bits where applicable
 142
 143 #define __HAL_RCC_FORCE_RESET(bus, suffix, enbit) (RCC->bus ## RSTR ## suffix |= (enbit))
 144 #define __HAL_RCC_RELEASE_RESET(bus, suffix, enbit) (RCC->bus ## RSTR ## suffix &= ~(enbit))
 145 #define __HAL_RCC_RESET(bus, suffix, enbit, NewState) \
 146     if (NewState == ENABLE) {                         \
 147         __HAL_RCC_RELEASE_RESET(bus, suffix, enbit);  \
 148     } else {                                          \
 149         __HAL_RCC_FORCE_RESET(bus, suffix, enbit);    \
 150     }
 151
 152 #if defined(USE_HAL_DRIVER)
 153
 154     switch (tag) {
 155     case RCC_AHB1:
 156         __HAL_RCC_RESET(AHB1, NOSUFFIX, mask, NewState);
 157         break;
 158
 159     case RCC_AHB2:
 160         __HAL_RCC_RESET(AHB2, NOSUFFIX, mask, NewState);
 161         break;
 162
 163 #if !(defined(STM32H7) || defined(STM32G4))
 164     case RCC_APB1:
 165         __HAL_RCC_RESET(APB1, NOSUFFIX, mask, NewState);
 166         break;
 167 #endif
 168
 169     case RCC_APB2:
 170         __HAL_RCC_RESET(APB2, NOSUFFIX, mask, NewState);
 171         break;
 172
 173 #ifdef STM32H7
 174
 175     case RCC_AHB3:
 176         __HAL_RCC_RESET(AHB3, NOSUFFIX, mask, NewState);
 177         break;
 178
 179     case RCC_AHB4:
 180         __HAL_RCC_RESET(AHB4, NOSUFFIX, mask, NewState);
 181         break;
 182
 183     case RCC_APB1L:
 184         __HAL_RCC_RESET(APB1L, NOSUFFIX, mask, NewState);
 185         break;
 186
 187     case RCC_APB1H:
 188         __HAL_RCC_RESET(APB1H, NOSUFFIX, mask, NewState);
 189         break;
 190
 191     case RCC_APB3:
 192         __HAL_RCC_RESET(APB3, NOSUFFIX, mask, NewState);
 193         break;
 194
 195     case RCC_APB4:
 196         __HAL_RCC_RESET(APB4, NOSUFFIX, mask, NewState);
 197         break;
 198 #endif
 199
 200 #ifdef STM32G4
 201
 202     case RCC_APB11:
 203         __HAL_RCC_CLK(APB1, 1, mask, NewState);
 204         break;
 205
 206     case RCC_APB12:
 207         __HAL_RCC_CLK(APB1, 2, mask, NewState);
 208         break;
 209
 210 #endif
 211     }
 212
 213 #else
 214
 215     switch (tag) {
 216 #if defined(STM32F3) || defined(STM32F10X_CL)
 217     case RCC_AHB:
 218         RCC_AHBPeriphResetCmd(mask, NewState);
 219         break;
 220 #endif
 221     case RCC_APB2:
 222         RCC_APB2PeriphResetCmd(mask, NewState);
 223         break;
 224     case RCC_APB1:
 225         RCC_APB1PeriphResetCmd(mask, NewState);
 226         break;
 227 #if defined(STM32F4)
 228     case RCC_AHB1:
 229         RCC_AHB1PeriphResetCmd(mask, NewState);
 230         break;
 231 #endif
 232     }
 233 #endif
 234 }